From 2c35570dc9ced8690ea269d1efab201c361fea98 Mon Sep 17 00:00:00 2001 From: tameraw <9868777+tameraw@users.noreply.github.com> Date: Thu, 16 Jul 2020 14:32:40 -0700 Subject: [PATCH] updated to 6.0.1 and added additional processors/toolchains --- common/inc/tx_api.h | 10 +- .../metaware/example_build/.metadata/.lock | 0 .../metaware/example_build/.metadata/.log | 937 ++ .../.plugins/org.eclipse.cdt.core/.log | 5 + .../sample_threadx.1453229896288.pdom | Bin 0 -> 225280 bytes .../sample_threadx.1592431055026.pdom | Bin 0 -> 262144 bytes .../sample_threadx.language.settings.xml | 4699 ++++++ .../org.eclipse.cdt.core/shareddefaults.xml | 1 + .../tx.1453229702368.pdom | Bin 0 -> 749568 bytes .../tx.language.settings.xml | 6159 ++++++++ .../org.eclipse.cdt.make.core/specs.c | 1 + .../org.eclipse.cdt.make.core/specs.cpp | 1 + .../spec.c | 0 .../spec.cpp | 0 .../org.eclipse.cdt.ui/dialog_settings.xml | 7 + .../sample_threadx/.indexes/properties.index | Bin 0 -> 422 bytes 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ports/cortex_r5/iar/example_build/settings/tx.Debug.cspy.ps1 create mode 100644 ports/cortex_r5/iar/example_build/settings/tx.Debug.driver.xcl create mode 100644 ports/cortex_r5/iar/example_build/settings/tx.Debug.general.xcl create mode 100644 ports/cortex_r5/iar/example_build/settings/tx.crun create mode 100644 ports/cortex_r5/iar/example_build/settings/tx.dbgdt create mode 100644 ports/cortex_r5/iar/example_build/settings/tx.dnx create mode 100644 ports/cortex_r5/iar/example_build/tx.dep create mode 100644 ports/cortex_r5/iar/example_build/tx.ewd create mode 100644 ports/cortex_r5/iar/example_build/tx.ewp create mode 100644 ports/cortex_r5/iar/example_build/tx.ewt create mode 100644 ports/cortex_r5/iar/example_build/tx_initialize_low_level.s create mode 100644 ports/cortex_r5/iar/inc/tx_port.h create mode 100644 ports/cortex_r5/iar/readme_threadx.txt create mode 100644 ports/cortex_r5/iar/src/tx_iar.c create mode 100644 ports/cortex_r5/iar/src/tx_thread_context_restore.s create mode 100644 ports/cortex_r5/iar/src/tx_thread_context_save.s create mode 100644 ports/cortex_r5/iar/src/tx_thread_interrupt_control.s create mode 100644 ports/cortex_r5/iar/src/tx_thread_interrupt_disable.s create mode 100644 ports/cortex_r5/iar/src/tx_thread_interrupt_restore.s create mode 100644 ports/cortex_r5/iar/src/tx_thread_irq_nesting_end.s create mode 100644 ports/cortex_r5/iar/src/tx_thread_irq_nesting_start.s create mode 100644 ports/cortex_r5/iar/src/tx_thread_schedule.s create mode 100644 ports/cortex_r5/iar/src/tx_thread_stack_build.s create mode 100644 ports/cortex_r5/iar/src/tx_thread_system_return.s create mode 100644 ports/cortex_r5/iar/src/tx_thread_vectored_context_save.s create mode 100644 ports/cortex_r5/iar/src/tx_timer_interrupt.s create mode 100644 ports/linux/gnu/example_build/file_list.mk create mode 100644 ports/linux/gnu/example_build/sample_threadx.c create mode 100644 ports/linux/gnu/inc/tx_port.h create mode 100644 ports/linux/gnu/readme_threadx.txt create mode 100644 ports/linux/gnu/src/tx_initialize_low_level.c create mode 100644 ports/linux/gnu/src/tx_thread_context_restore.c create mode 100644 ports/linux/gnu/src/tx_thread_context_save.c create mode 100644 ports/linux/gnu/src/tx_thread_interrupt_control.c create mode 100644 ports/linux/gnu/src/tx_thread_schedule.c create mode 100644 ports/linux/gnu/src/tx_thread_stack_build.c create mode 100644 ports/linux/gnu/src/tx_thread_system_return.c create mode 100644 ports/linux/gnu/src/tx_timer_interrupt.c create mode 100644 ports/win32/vs_2019/example_build/azure_rtos.sln create mode 100644 ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.c create mode 100644 ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.vcxproj create mode 100644 ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.vcxproj.filters create mode 100644 ports/win32/vs_2019/example_build/tx/tx.vcxproj create mode 100644 ports/win32/vs_2019/example_build/tx/tx.vcxproj.filters create mode 100644 ports/win32/vs_2019/inc/tx_port.h create mode 100644 ports/win32/vs_2019/readme_threadx.txt create mode 100644 ports/win32/vs_2019/src/tx_initialize_low_level.c create mode 100644 ports/win32/vs_2019/src/tx_thread_context_restore.c create mode 100644 ports/win32/vs_2019/src/tx_thread_context_save.c create mode 100644 ports/win32/vs_2019/src/tx_thread_interrupt_control.c create mode 100644 ports/win32/vs_2019/src/tx_thread_schedule.c create mode 100644 ports/win32/vs_2019/src/tx_thread_stack_build.c create mode 100644 ports/win32/vs_2019/src/tx_thread_system_return.c create mode 100644 ports/win32/vs_2019/src/tx_timer_interrupt.c diff --git a/common/inc/tx_api.h b/common/inc/tx_api.h index 4ca000be..75b443d2 100644 --- a/common/inc/tx_api.h +++ b/common/inc/tx_api.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* tx_api.h PORTABLE C */ -/* 6.0 */ +/* 6.0.1 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -44,6 +44,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 06-30-2020 William E. Lamie Modified comment(s), and */ +/* updated product constants, */ +/* resulting in version 6.0.1 */ /* */ /**************************************************************************/ @@ -73,10 +76,13 @@ extern "C" { /* Define the major/minor version information that can be used by the application and the ThreadX source as well. */ -#define EL_PRODUCT_THREADX +#define AZURE_RTOS_THREADX #define THREADX_MAJOR_VERSION 6 #define THREADX_MINOR_VERSION 0 +#define THREADX_PATCH_VERSION 1 +/* Define the following symbol for backward compatibility */ +#define EL_PRODUCT_THREADX /* API input parameters and general constants. */ diff --git a/ports/arc_em/metaware/example_build/.metadata/.lock b/ports/arc_em/metaware/example_build/.metadata/.lock new file mode 100644 index 00000000..e69de29b diff --git a/ports/arc_em/metaware/example_build/.metadata/.log b/ports/arc_em/metaware/example_build/.metadata/.log new file mode 100644 index 00000000..9119491b --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.log @@ -0,0 +1,937 @@ +!SESSION 2016-01-19 10:53:52.024 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.cdt.core 1 0 2016-01-19 10:55:02.458 +!MESSAGE Indexed 'tx' (0 sources, 0 headers) in 0 sec: 0 declarations; 0 references; 0 unresolved inclusions; 0 syntax errors; 0 unresolved names (0%) + +!ENTRY org.eclipse.cdt.core 1 0 2016-01-19 10:58:16.298 +!MESSAGE Indexed 'sample_threadx' (0 sources, 0 headers) in 0 sec: 0 declarations; 0 references; 0 unresolved inclusions; 0 syntax errors; 0 unresolved names (0%) + +!ENTRY org.eclipse.e4.ui.workbench.swt 4 2 2016-01-19 10:59:20.668 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.e4.ui.workbench.swt". +!STACK 0 +org.eclipse.e4.core.di.InjectionException: org.eclipse.swt.SWTException: Widget is disposed + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:62) + at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:888) + at org.eclipse.e4.core.internal.di.InjectorImpl.disposed(InjectorImpl.java:390) + at org.eclipse.e4.core.internal.di.Requestor.disposed(Requestor.java:143) + at org.eclipse.e4.core.internal.contexts.ContextObjectSupplier$ContextInjectionListener.update(ContextObjectSupplier.java:76) + at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.update(TrackableComputationExt.java:107) + at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.handleInvalid(TrackableComputationExt.java:70) + at org.eclipse.e4.core.internal.contexts.EclipseContext.dispose(EclipseContext.java:175) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.clearContext(PartRenderingEngine.java:974) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeRemoveGui(PartRenderingEngine.java:954) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$3(PartRenderingEngine.java:862) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$8.run(PartRenderingEngine.java:857) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.removeGui(PartRenderingEngine.java:841) + at org.eclipse.ui.internal.WorkbenchWindow.hardClose(WorkbenchWindow.java:1937) + at org.eclipse.ui.internal.WorkbenchWindow.busyClose(WorkbenchWindow.java:1560) + at org.eclipse.ui.internal.WorkbenchWindow.access$15(WorkbenchWindow.java:1527) + at org.eclipse.ui.internal.WorkbenchWindow$10.run(WorkbenchWindow.java:1592) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70) + at org.eclipse.ui.internal.WorkbenchWindow.close(WorkbenchWindow.java:1589) + at org.eclipse.ui.internal.Workbench$14.run(Workbench.java:1155) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench.busyClose(Workbench.java:1137) + at org.eclipse.ui.internal.Workbench.access$21(Workbench.java:1079) + at org.eclipse.ui.internal.Workbench$19.run(Workbench.java:1410) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70) + at org.eclipse.ui.internal.Workbench.close(Workbench.java:1407) + at org.eclipse.ui.internal.Workbench.restart(Workbench.java:2677) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction.restart(OpenWorkspaceAction.java:282) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction.access$0(OpenWorkspaceAction.java:274) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction$WorkspaceMRUAction.run(OpenWorkspaceAction.java:103) + at org.eclipse.jface.action.Action.runWithEvent(Action.java:519) + at org.eclipse.jface.action.ActionContributionItem.handleWidgetSelection(ActionContributionItem.java:595) + at org.eclipse.jface.action.ActionContributionItem.access$2(ActionContributionItem.java:511) + at org.eclipse.jface.action.ActionContributionItem$5.handleEvent(ActionContributionItem.java:420) + at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84) + at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1085) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1070) + at org.eclipse.swt.widgets.Widget.notifyListeners(Widget.java:782) + at org.eclipse.jface.action.ActionContributionItem$9.handleEvent(ActionContributionItem.java:1293) + at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84) + at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061) + at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172) + at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603) + at org.eclipse.equinox.launcher.Main.run(Main.java:1465) +Caused by: org.eclipse.swt.SWTException: Widget is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Widget.error(Widget.java:476) + at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348) + at org.eclipse.swt.widgets.Shell.getSize(Shell.java:1092) + at org.eclipse.ui.internal.quickaccess.SearchField.storeDialog(SearchField.java:580) + at org.eclipse.ui.internal.quickaccess.SearchField.dispose(SearchField.java:557) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55) + ... 67 more + +!ENTRY org.eclipse.e4.ui.workbench 4 0 2016-01-19 10:59:20.678 +!MESSAGE Exception occurred while unrendering: org.eclipse.e4.ui.model.application.ui.basic.impl.TrimmedWindowImpl@4d7f76 (elementId: IDEWindow, tags: [topLevel], contributorURI: platform:/plugin/org.eclipse.ui.workbench) (widget: null, renderer: null, toBeRendered: true, onTop: false, visible: true, containerData: null, accessibilityPhrase: null) (label: %trimmedwindow.label.eclipseSDK, iconURI: null, tooltip: null, context: null, variables: [], x: 250, y: 250, width: 1024, height: 768) +!STACK 0 +org.eclipse.e4.core.di.InjectionException: org.eclipse.swt.SWTException: Widget is disposed + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:62) + at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:888) + at org.eclipse.e4.core.internal.di.InjectorImpl.disposed(InjectorImpl.java:390) + at org.eclipse.e4.core.internal.di.Requestor.disposed(Requestor.java:143) + at org.eclipse.e4.core.internal.contexts.ContextObjectSupplier$ContextInjectionListener.update(ContextObjectSupplier.java:76) + at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.update(TrackableComputationExt.java:107) + at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.handleInvalid(TrackableComputationExt.java:70) + at org.eclipse.e4.core.internal.contexts.EclipseContext.dispose(EclipseContext.java:175) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.clearContext(PartRenderingEngine.java:974) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeRemoveGui(PartRenderingEngine.java:954) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$3(PartRenderingEngine.java:862) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$8.run(PartRenderingEngine.java:857) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.removeGui(PartRenderingEngine.java:841) + at org.eclipse.ui.internal.WorkbenchWindow.hardClose(WorkbenchWindow.java:1937) + at org.eclipse.ui.internal.WorkbenchWindow.busyClose(WorkbenchWindow.java:1560) + at org.eclipse.ui.internal.WorkbenchWindow.access$15(WorkbenchWindow.java:1527) + at org.eclipse.ui.internal.WorkbenchWindow$10.run(WorkbenchWindow.java:1592) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70) + at org.eclipse.ui.internal.WorkbenchWindow.close(WorkbenchWindow.java:1589) + at org.eclipse.ui.internal.Workbench$14.run(Workbench.java:1155) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench.busyClose(Workbench.java:1137) + at org.eclipse.ui.internal.Workbench.access$21(Workbench.java:1079) + at org.eclipse.ui.internal.Workbench$19.run(Workbench.java:1410) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70) + at org.eclipse.ui.internal.Workbench.close(Workbench.java:1407) + at org.eclipse.ui.internal.Workbench.restart(Workbench.java:2677) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction.restart(OpenWorkspaceAction.java:282) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction.access$0(OpenWorkspaceAction.java:274) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction$WorkspaceMRUAction.run(OpenWorkspaceAction.java:103) + at org.eclipse.jface.action.Action.runWithEvent(Action.java:519) + at org.eclipse.jface.action.ActionContributionItem.handleWidgetSelection(ActionContributionItem.java:595) + at org.eclipse.jface.action.ActionContributionItem.access$2(ActionContributionItem.java:511) + at org.eclipse.jface.action.ActionContributionItem$5.handleEvent(ActionContributionItem.java:420) + at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84) + at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1085) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1070) + at org.eclipse.swt.widgets.Widget.notifyListeners(Widget.java:782) + at org.eclipse.jface.action.ActionContributionItem$9.handleEvent(ActionContributionItem.java:1293) + at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84) + at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061) + at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172) + at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603) + at org.eclipse.equinox.launcher.Main.run(Main.java:1465) +Caused by: org.eclipse.swt.SWTException: Widget is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Widget.error(Widget.java:476) + at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348) + at org.eclipse.swt.widgets.Shell.getSize(Shell.java:1092) + at org.eclipse.ui.internal.quickaccess.SearchField.storeDialog(SearchField.java:580) + at org.eclipse.ui.internal.quickaccess.SearchField.dispose(SearchField.java:557) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55) + ... 67 more +!SESSION 2020-06-17 14:55:11.959 ----------------------------------------------- +eclipse.buildId=unknown +java.fullversion=1.8.0_212-b03 +JRE 1.8.0 Windows 8 amd64-64-Bit Compressed References 20190417_339 (JIT enabled, AOT enabled) +OpenJ9 - bad1d4d06 +OMR - 4a4278e6 +JCL - 5590c4f818 based on jdk8u212-b03 +BootLoader constants: OS=win32, ARCH=x86_64, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86_64 + +!ENTRY org.eclipse.e4.ui.workbench 2 0 2020-06-17 14:55:28.047 +!MESSAGE Could not run processor +!STACK 0 +org.eclipse.e4.core.di.InjectionException: java.lang.NullPointerException + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:65) + at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:282) + at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:259) + at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107) + at org.eclipse.e4.ui.internal.workbench.ModelAssembler.runProcessor(ModelAssembler.java:335) + at org.eclipse.e4.ui.internal.workbench.ModelAssembler.runProcessors(ModelAssembler.java:297) + at org.eclipse.e4.ui.internal.workbench.ModelAssembler.processModel(ModelAssembler.java:98) + at org.eclipse.e4.ui.internal.workbench.ResourceHandler.loadMostRecentModel(ResourceHandler.java:197) + at org.eclipse.e4.ui.internal.workbench.swt.E4Application.loadApplicationModel(E4Application.java:377) + at org.eclipse.e4.ui.internal.workbench.swt.E4Application.createE4Workbench(E4Application.java:252) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:632) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:336) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:610) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:148) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:138) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:388) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:243) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:498) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:673) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:610) + at org.eclipse.equinox.launcher.Main.run(Main.java:1519) +Caused by: java.lang.NullPointerException + at org.eclipse.cdt.launchbar.ui.internal.LaunchBarInjector.injectLaunchBar(LaunchBarInjector.java:109) + at org.eclipse.cdt.launchbar.ui.internal.LaunchBarInjector.injectIntoAll(LaunchBarInjector.java:84) + at org.eclipse.cdt.launchbar.ui.internal.LaunchBarInjector.execute(LaunchBarInjector.java:46) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:498) + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55) + ... 26 more + +!ENTRY org.eclipse.osgi 4 0 2020-06-17 14:55:34.531 +!MESSAGE An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). +!STACK 0 +org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +Root exception: +java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.eclipse.ui.workbench 4 2 2020-06-17 14:55:34.556 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.ui.workbench". +!STACK 1 +org.eclipse.core.runtime.CoreException: Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.throwException(RegistryStrategyOSGI.java:194) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:176) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + ... 10 more +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-17 14:55:34.558 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-17 14:55:34.558 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more + +!ENTRY org.eclipse.ui 4 0 2020-06-17 14:55:34.575 +!MESSAGE Unable to execute early startup code for the org.eclipse.ui.IStartup extension contributed by the 'com.synopsys.cdt.cnn.tools.ui' plug-in. +!STACK 1 +org.eclipse.core.runtime.CoreException: Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.throwException(RegistryStrategyOSGI.java:194) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:176) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + ... 10 more +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-17 14:55:34.576 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more + +!ENTRY org.eclipse.e4.ui.workbench 2 0 2020-06-17 14:55:34.888 +!MESSAGE Removing part descriptor with the 'org.eclipse.cdt.debug.ui.DisassemblyView' id and the 'Disassembly' description. Points to the invalid 'bundleclass://org.eclipse.ui.workbench/org.eclipse.ui.internal.e4.compatibility.CompatibilityView' class. +!SESSION 2020-06-17 14:57:04.375 ----------------------------------------------- +eclipse.buildId=unknown +java.fullversion=1.8.0_212-b03 +JRE 1.8.0 Windows 8 amd64-64-Bit Compressed References 20190417_339 (JIT enabled, AOT enabled) +OpenJ9 - bad1d4d06 +OMR - 4a4278e6 +JCL - 5590c4f818 based on jdk8u212-b03 +BootLoader constants: OS=win32, ARCH=x86_64, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86_64 + +!ENTRY org.eclipse.core.resources 4 567 2020-06-17 14:57:08.841 +!MESSAGE Workspace restored, but some problems occurred. +!SUBENTRY 1 org.eclipse.core.resources 4 567 2020-06-17 14:57:08.841 +!MESSAGE Could not read metadata for 'demo_threadx'. +!STACK 1 +org.eclipse.core.internal.resources.ResourceException: The project description file (.project) for 'demo_threadx' is missing. This file contains important information about the project. The project will not function properly until this file is restored. + at org.eclipse.core.internal.localstore.FileSystemResourceManager.read(FileSystemResourceManager.java:907) + at org.eclipse.core.internal.resources.SaveManager.restoreMetaInfo(SaveManager.java:904) + at org.eclipse.core.internal.resources.SaveManager.restoreMetaInfo(SaveManager.java:884) + at org.eclipse.core.internal.resources.SaveManager.restore(SaveManager.java:735) + at org.eclipse.core.internal.resources.SaveManager.startup(SaveManager.java:1587) + at org.eclipse.core.internal.resources.Workspace.startup(Workspace.java:2399) + at org.eclipse.core.internal.resources.Workspace.open(Workspace.java:2156) + at org.eclipse.core.resources.ResourcesPlugin.start(ResourcesPlugin.java:464) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.sources.SingleSourcePackage.loadClass(SingleSourcePackage.java:36) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:419) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:139) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:388) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:243) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:498) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:673) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:610) + at org.eclipse.equinox.launcher.Main.run(Main.java:1519) +!SUBENTRY 2 org.eclipse.core.resources 4 567 2020-06-17 14:57:08.842 +!MESSAGE The project description file (.project) for 'demo_threadx' is missing. This file contains important information about the project. The project will not function properly until this file is restored. + +!ENTRY org.eclipse.osgi 4 0 2020-06-17 14:57:12.158 +!MESSAGE An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). +!STACK 0 +org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +Root exception: +java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.eclipse.ui.workbench 4 2 2020-06-17 14:57:12.190 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.ui.workbench". +!STACK 1 +org.eclipse.core.runtime.CoreException: Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.throwException(RegistryStrategyOSGI.java:194) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:176) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + ... 10 more +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-17 14:57:12.191 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-17 14:57:12.191 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more + +!ENTRY org.eclipse.ui 4 0 2020-06-17 14:57:12.213 +!MESSAGE Unable to execute early startup code for the org.eclipse.ui.IStartup extension contributed by the 'com.synopsys.cdt.cnn.tools.ui' plug-in. +!STACK 1 +org.eclipse.core.runtime.CoreException: Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.throwException(RegistryStrategyOSGI.java:194) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:176) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + ... 10 more +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-17 14:57:12.214 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more + +!ENTRY org.eclipse.e4.ui.workbench 2 0 2020-06-17 14:57:12.604 +!MESSAGE Removing part descriptor with the 'org.eclipse.cdt.debug.ui.DisassemblyView' id and the 'Disassembly' description. Points to the invalid 'bundleclass://org.eclipse.ui.workbench/org.eclipse.ui.internal.e4.compatibility.CompatibilityView' class. + +!ENTRY org.eclipse.cdt.core 1 0 2020-06-17 14:57:35.283 +!MESSAGE Indexed 'sample_threadx' (1 sources, 0 headers) in 0.24 sec: 60 declarations; 165 references; 1 unresolved inclusions; 0 syntax errors; 105 unresolved names (32%) diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/.log b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/.log new file mode 100644 index 00000000..42f9bd76 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/.log @@ -0,0 +1,5 @@ +*** SESSION Jan 19, 2016 10:54:21.49 ------------------------------------------- +*** SESSION Jan 19, 2016 11:01:03.18 ------------------------------------------- +*** SESSION Feb 12, 2016 17:04:55.37 ------------------------------------------- +*** SESSION Jun 17, 2020 14:55:32.91 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a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-tx.prefs b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-tx.prefs new file mode 100644 index 00000000..9c00dc4e --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-tx.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 00000000..aa2411de --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.cDebug.default_source_containers=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.launchbar.core.prefs b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.launchbar.core.prefs new file mode 100644 index 00000000..c002721a --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.launchbar.core.prefs @@ -0,0 +1,5 @@ +activeConfigDesc=sample_threadx Debug.org.eclipse.cdt.launchbar.core.descriptor.default +configDescList=[sample_threadx Debug.org.eclipse.cdt.launchbar.core.descriptor.default] +sample_threadx\ Debug.org.eclipse.cdt.launchbar.core.descriptor.default/activeLaunchMode=debug +sample_threadx\ Debug.org.eclipse.cdt.launchbar.core.descriptor.default/activeLaunchTarget=org.eclipse.cdt.launchbar.core.target.local +eclipse.preferences.version=1 diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 00000000..c71aa03b --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,5 @@ +eclipse.preferences.version=1 +properties/sample_threadx.com.arc.cdt.toolchain.arc.av2em.exeProject.666673635/com.arc.cdt.toolchain.av2em.exeDebugConfig.1217165695=com.arc.cdt.toolchain.arc.archiver.887646463\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2em.asmDebugExe.502330268\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2em.exeDebugConfig.1217165695\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2em.exeLinkerDebug.994503969\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2em.exeToolChainDebug.687487123\=rebuildState\\\=false\\r\\n\r\nav2em.exe.debug.exeCompilerDebug.670850607\=rebuildState\\\=false\\r\\n\r\n +properties/sample_threadx.com.arc.cdt.toolchain.arc.av2em.exeProject.666673635/com.arc.cdt.toolchain.av2em.exeReleaseConfig.2022621224=com.arc.cdt.toolchain.av2em.asmReleaseExe.714380962\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.arc.archiver.1360196687\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2em.exelinkerRelease.1145338994\=rebuildState\\\=true\\r\\n\r\narc.cdt.toolchain.av2em.exeCompilerRelease.93257878\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2em.exeReleaseToolChain.1354693166\=rebuildState\\\=true\\r\\n\r\n +properties/tx.com.arc.cdt.toolchain.arc.av2em.libProject.1936758151/com.arc.cdt.toolchain.av2em.libDebugConfig.732975342=av2em.lib.debug.libCompiler.557728458\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2em.libDebugConfig.732975342\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.arc.Linker.1782192981\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2em.libDebugToolChain.1845103261\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2em.ArDebug.448807496\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2em.libDebugAsm.1772833895\=rebuildState\\\=false\\r\\n\r\n +properties/tx.com.arc.cdt.toolchain.arc.av2em.libProject.1936758151/com.arc.cdt.toolchain.av2em.libReleaseConfig.1738957053=com.arc.cdt.toolchain.av2em.libReleaseToolChain.637077717\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2em.ArRelease.50929117\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2em.libReleaseAsm.1659783437\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.arc.Linker.1430136995\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2em.libCompilerRelease.267590455\=rebuildState\\\=true\\r\\n\r\n diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs new file mode 100644 index 00000000..5e2da66d --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs @@ -0,0 +1,4 @@ +eclipse.preferences.version=1 +spelling_locale_initialized=true +useAnnotationsPrefPage=true +useQuickDiffPrefPage=true diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..dffc6b51 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +version=1 diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs new file mode 100644 index 00000000..47236716 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs @@ -0,0 +1,5 @@ +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.attachLaunchType=org.eclipse.cdt.dsf.gdb.launch.attachCLaunch,debug,; +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.localCLaunch=org.eclipse.cdt.cdi.launch.localCLaunch,run,; +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.postmortemLaunchType=org.eclipse.cdt.dsf.gdb.launch.coreCLaunch,debug,; +eclipse.preferences.version=1 +prefWatchExpressions=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs new file mode 100644 index 00000000..45b0d108 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs @@ -0,0 +1,8 @@ +eclipse.preferences.version=1 +org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=\r\n\r\n +org.eclipse.debug.ui.user_view_bindings=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n +pref_state_memento.org.eclipse.debug.ui.DebugVieworg.eclipse.debug.ui.DebugView=\r\n +pref_state_memento.org.eclipse.debug.ui.ExpressionView=\r\n\r\n\r\n\r\n\r\n +pref_state_memento.org.eclipse.debug.ui.VariableView=\r\n\r\n\r\n +preferredDetailPanes=DefaultDetailPane\:DefaultDetailPane| +preferredTargets=org.eclipse.cdt.debug.ui.toggleCBreakpointTarget,org.eclipse.cdt.debug.ui.toggleCDynamicPrintfTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget| diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs new file mode 100644 index 00000000..61f3bb8b --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +overviewRuler_migration=migrated_3.1 diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs new file mode 100644 index 00000000..76ce67b9 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs @@ -0,0 +1,5 @@ +PROBLEMS_FILTERS_MIGRATE=true +eclipse.preferences.version=1 +platformState=1590536495337 +quickStart=true +tipsAndTricks=true diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs new file mode 100644 index 00000000..08076f23 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +showIntro=false diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs new file mode 100644 index 00000000..60e7be60 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs @@ -0,0 +1,4 @@ +//org.eclipse.ui.commands/state/org.eclipse.ui.navigator.resources.nested.changeProjectPresentation/org.eclipse.ui.commands.radioState=false +UIActivities.com.arc.cdt.debug.seecode.ui.activity1=true +UIActivities.org.eclipse.cdt.debug.cdigdbActivity=true +eclipse.preferences.version=1 diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.debug.core/.launches/sample_threadx Debug.launch b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.debug.core/.launches/sample_threadx Debug.launch new file mode 100644 index 00000000..943da6ac --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.debug.core/.launches/sample_threadx Debug.launch @@ -0,0 +1,441 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml new file mode 100644 index 00000000..360c49ad --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml @@ -0,0 +1,11 @@ + +
+
+ + + + + + +
+
diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml new file mode 100644 index 00000000..c22cfeb5 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.e4.ui.workbench.swt/dialog_settings.xml b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.e4.ui.workbench.swt/dialog_settings.xml new file mode 100644 index 00000000..919834a6 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.e4.ui.workbench.swt/dialog_settings.xml @@ -0,0 +1,15 @@ + +
+
+ + + + + + + + + + +
+
diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi new file mode 100644 index 00000000..2c2508c6 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi @@ -0,0 +1,1779 @@ + + + + activeSchemeId:org.eclipse.ui.defaultAcceleratorConfiguration + ModelMigrationProcessor.001 + + + + + + + + topLevel + shellMaximized + + + + + persp.actionSet:com.arc.eclipse.aboutMWDebugger + persp.actionSet:com.arc.cdt.toolchain.PDFs + persp.actionSet:org.eclipse.ui.cheatsheets.actionSet + persp.actionSet:org.eclipse.search.searchActionSet + persp.actionSet:org.eclipse.ui.edit.text.actionSet.annotationNavigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.navigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.convertLineDelimitersTo + persp.actionSet:org.eclipse.ui.externaltools.ExternalToolsSet + persp.actionSet:org.eclipse.ui.actionSet.keyBindings + persp.actionSet:org.eclipse.ui.actionSet.openFiles + persp.actionSet:org.eclipse.cdt.ui.SearchActionSet + persp.actionSet:org.eclipse.cdt.ui.CElementCreationActionSet + persp.actionSet:org.eclipse.ui.NavigateActionSet + persp.viewSC:org.eclipse.ui.console.ConsoleView + persp.viewSC:org.eclipse.search.ui.views.SearchView + persp.viewSC:org.eclipse.ui.views.ContentOutline + persp.viewSC:org.eclipse.ui.views.ProblemView + persp.viewSC:org.eclipse.cdt.ui.CView + persp.viewSC:org.eclipse.ui.views.ResourceNavigator + persp.viewSC:org.eclipse.ui.views.PropertySheet + persp.viewSC:org.eclipse.ui.views.TaskList + persp.newWizSC:org.eclipse.cdt.ui.wizards.ConvertToMakeWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewMakeFromExisting + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewCWizard1 + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewCWizard2 + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewSourceFolderCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewFolderCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewSourceFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewHeaderFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewClassCreationWizard + persp.viewSC:org.eclipse.pde.runtime.LogView + persp.showIn:org.eclipse.cdt.codan.internal.ui.views.ProblemDetails + persp.viewSC:org.eclipse.cdt.codan.internal.ui.views.ProblemDetails + persp.actionSet:org.eclipse.debug.ui.breakpointActionSet + persp.viewSC:org.eclipse.cdt.make.ui.views.MakeView + persp.actionSet:org.eclipse.cdt.make.ui.makeTargetActionSet + persp.perspSC:org.eclipse.debug.ui.DebugPerspective + persp.perspSC:org.eclipse.team.ui.TeamSynchronizingPerspective + persp.actionSet:org.eclipse.debug.ui.launchActionSet + persp.actionSet:org.eclipse.cdt.ui.buildConfigActionSet + persp.actionSet:org.eclipse.cdt.ui.NavigationActionSet + persp.actionSet:org.eclipse.cdt.ui.OpenActionSet + persp.actionSet:org.eclipse.cdt.ui.CodingActionSet + persp.actionSet:org.eclipse.ui.edit.text.actionSet.presentation + persp.showIn:org.eclipse.cdt.ui.includeBrowser + persp.showIn:org.eclipse.cdt.ui.CView + persp.showIn:org.eclipse.ui.navigator.ProjectExplorer + persp.viewSC:org.eclipse.ui.navigator.ProjectExplorer + persp.viewSC:org.eclipse.cdt.ui.includeBrowser + persp.actionSet:org.eclipse.debug.ui.debugActionSet + + + newtablook + active + + + + + + + + + + newtablook + + + + + + + + newtablook + Debug + + + + + + + + + + + + persp.actionSet:com.arc.eclipse.aboutMWDebugger + persp.actionSet:com.arc.cdt.toolchain.PDFs + persp.actionSet:org.eclipse.ui.cheatsheets.actionSet + persp.actionSet:org.eclipse.search.searchActionSet + persp.actionSet:org.eclipse.ui.edit.text.actionSet.annotationNavigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.navigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.convertLineDelimitersTo + persp.actionSet:org.eclipse.ui.externaltools.ExternalToolsSet + persp.actionSet:org.eclipse.ui.actionSet.keyBindings + persp.actionSet:org.eclipse.ui.actionSet.openFiles + persp.actionSet:org.eclipse.debug.ui.launchActionSet + persp.actionSet:org.eclipse.debug.ui.debugActionSet + persp.viewSC:org.eclipse.debug.ui.DebugView + persp.viewSC:org.eclipse.debug.ui.VariableView + persp.viewSC:org.eclipse.debug.ui.BreakpointView + persp.viewSC:org.eclipse.debug.ui.ExpressionView + persp.viewSC:org.eclipse.ui.views.ContentOutline + persp.viewSC:org.eclipse.ui.console.ConsoleView + persp.viewSC:org.eclipse.ui.views.TaskList + persp.viewSC:com.arc.cdt.debug.seecode.ui.views.disasm + persp.viewSC:com.arc.cdt.debug.seecode.ui.command + persp.viewSC:com.arc.cdt.debug.seecode.ui.views.memsearch + persp.viewSC:com.arc.cdt.seecode.errorlog + persp.viewSC:org.eclipse.cdt.debug.ui.SignalsView + persp.viewSC:org.eclipse.cdt.debug.ui.RegisterView + persp.viewSC:org.eclipse.debug.ui.ModuleView + persp.viewSC:org.eclipse.debug.ui.MemoryView + persp.viewSC:org.eclipse.ui.views.ProblemView + persp.viewSC:org.eclipse.cdt.debug.ui.executablesView + persp.actionSet:org.eclipse.cdt.debug.ui.debugActionSet + persp.actionSet:org.eclipse.cdt.debug.ui.debugActionSetExt + persp.viewSC:org.eclipse.cdt.dsf.gdb.ui.tracecontrol.view + persp.viewSC:org.eclipse.cdt.dsf.debug.ui.disassembly.view + persp.perspSC:org.eclipse.cdt.ui.CPerspective + persp.viewSC:org.eclipse.cdt.visualizer.view + persp.actionSet:org.eclipse.ui.NavigateActionSet + persp.actionSet:org.eclipse.debug.ui.breakpointActionSet + persp.viewSC:org.eclipse.pde.runtime.LogView + persp.actionSet:org.eclipse.cdt.debug.ui.debugActionSetExt2 + + + + + + newtablook + org.eclipse.e4.primaryNavigationStack + + + + + newtablook + + + + + newtablook + + + + + + + + + + + + + + + + + + newtablook + + + + + + newtablook + org.eclipse.e4.secondaryNavigationStack + + + + + + + + + Standalone + + + + + + + newtablook + org.eclipse.e4.secondaryDataStack + + + + + + + + + + newtablook + + + + + + + + + + + + + + + + + View + categoryTag:Help + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Help + + + + newtablook + org.eclipse.e4.primaryDataStack + EditorStack + + + + + View + categoryTag:General + active + activeOnClose + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:&C/C++ + + + View + categoryTag:General + + + View + categoryTag:General + + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:General + + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:General + + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Make + + + View + categoryTag:Terminal + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + + toolbarSeparator + + + + Draggable + + + + toolbarSeparator + + + + Draggable + + + Draggable + + + Draggable + + + Draggable + + + toolbarSeparator + + + + Draggable + + + + toolbarSeparator + + + + toolbarSeparator + + + + Draggable + + + stretch + SHOW_RESTORE_MENU + + + Draggable + HIDEABLE + SHOW_RESTORE_MENU + + + + + stretch + + + Draggable + + + Draggable + + + + + TrimStack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + platform:win32 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + platform:win32 + + + + + + + + + + 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categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Help + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:Team + + + + + View + categoryTag:Team + + + + + View + categoryTag:Terminal + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:Help + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + glue + move_after:PerspectiveSpacer + SHOW_RESTORE_MENU + + + move_after:Spacer Glue + HIDEABLE + SHOW_RESTORE_MENU + + + glue + move_after:SearchField + SHOW_RESTORE_MENU + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.history b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.history new file mode 100644 index 00000000..023aad6a --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.history @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.index b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.index new file mode 100644 index 00000000..b1d64d87 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.index @@ -0,0 +1 @@ +1592431039575 Delete resource 'demo_threadx' diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml new file mode 100644 index 00000000..aa267842 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml @@ -0,0 +1,7 @@ + +
+
+ + +
+
diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml new file mode 100644 index 00000000..50f1edb3 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml @@ -0,0 +1,5 @@ + +
+
+
+
diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml new file mode 100644 index 00000000..dba32153 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml @@ -0,0 +1,14 @@ + +
+
+ + + + + + + + + +
+
diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml new file mode 100644 index 00000000..6c7a5b44 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml @@ -0,0 +1,29 @@ + +
+
+ + + + + + + + + + +
+
+ + + + +
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diff --git a/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml new file mode 100644 index 00000000..1ad3c528 --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/ports/arc_em/metaware/example_build/.metadata/version.ini b/ports/arc_em/metaware/example_build/.metadata/version.ini new file mode 100644 index 00000000..824cbfda --- /dev/null +++ b/ports/arc_em/metaware/example_build/.metadata/version.ini @@ -0,0 +1,3 @@ +#Wed Jun 17 14:57:08 PDT 2020 +org.eclipse.core.runtime=2 +org.eclipse.platform=4.6.3.v20170301-0400 diff --git a/ports/arc_em/metaware/example_build/sample_threadx/.cproject b/ports/arc_em/metaware/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..e14337b5 --- /dev/null +++ b/ports/arc_em/metaware/example_build/sample_threadx/.cproject @@ -0,0 +1,145 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/arc_em/metaware/example_build/sample_threadx/.project b/ports/arc_em/metaware/example_build/sample_threadx/.project new file mode 100644 index 00000000..a1b15572 --- /dev/null +++ b/ports/arc_em/metaware/example_build/sample_threadx/.project @@ -0,0 +1,26 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports/arc_em/metaware/example_build/sample_threadx/.settings/language.settings.xml b/ports/arc_em/metaware/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..02e19444 --- /dev/null +++ b/ports/arc_em/metaware/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.c b/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..24d05100 --- /dev/null +++ b/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,368 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); + + return(0); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.cmd b/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.cmd new file mode 100644 index 00000000..aced0777 --- /dev/null +++ b/ports/arc_em/metaware/example_build/sample_threadx/sample_threadx.cmd @@ -0,0 +1,56 @@ +// +// This is the linker script example (SRV3-style). +// (c) Synopsys, 2013 +// +// + +//number of exceptions and interrupts +NUMBER_OF_EXCEPTIONS = 16;//it is fixed (16) +NUMBER_OF_INTERRUPTS = 5;//depends on HW configuration + +//define Interrupt Vector Table size +IVT_SIZE_ITEMS = (NUMBER_OF_EXCEPTIONS + NUMBER_OF_INTERRUPTS);//the total IVT size (in "items") +IVT_SIZE_BYTES = IVT_SIZE_ITEMS * 4;//in bytes + +//define ICCM and DCCM locations +MEMORY { + + ICCM: ORIGIN = 0x00000000, LENGTH = 128K + DCCM: ORIGIN = 0x80000000, LENGTH = 128K +} + +//define sections and groups +SECTIONS { + GROUP: { + .ivt (TEXT) : # Interrupt table + { + ___ivt1 = .; + * (.ivt) + ___ivt2 = .; + // Make the IVT at least IVT_SIZE_BYTES + . += (___ivt2 - ___ivt1 < IVT_SIZE_BYTES) ? (IVT_SIZE_BYTES - (___ivt2 - ___ivt1)) : 0; + } + .ivh (TEXT) : // Interrupt handlers + + //TEXT sections + .text? : { *('.text$crt*') } + * (TEXT): {} + //Literals + * (LIT): {} + } > ICCM + + GROUP: { + //data sections + .sdata?: {} + .sbss?: {} + *(DATA): {} + *(BSS): {} + //stack + .stack_top: {} + .stack ALIGN(4) SIZE(DEFINED _STACKSIZE?_STACKSIZE:4096): {} + .stack_base: {} + //heap (empty) + .heap? ALIGN(4) SIZE(DEFINED _HEAPSIZE?_HEAPSIZE:0): {} + .free_memory: {} + } > DCCM + } diff --git a/ports/arc_em/metaware/example_build/sample_threadx/tx_initialize_low_level.s b/ports/arc_em/metaware/example_build/sample_threadx/tx_initialize_low_level.s new file mode 100644 index 00000000..8b75bf9f --- /dev/null +++ b/ports/arc_em/metaware/example_build/sample_threadx/tx_initialize_low_level.s @@ -0,0 +1,360 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + .equ IRQ_SELECT, 0x40B + .equ KSTACK_TOP, 0x264 + .equ KSTACK_BASE, 0x265 + .equ STATUS32_SC, 0x4000 +; +; +; /* Define section for placement after all linker allocated RAM memory. This +; is used to calculate the first free address that is passed to +; tx_appication_define, soley for the ThreadX application's use. */ +; + .section ".free_memory","aw" + .align 4 + .global _tx_first_free_address +_tx_first_free_address: + .space 4 +; +; /* Define section for placement before the main stack area for setting +; up the STACK_TOP address for hardware stack checking. */ +; + .section ".stack_top","aw" + .align 4 + .global _tx_system_stack_top_address +_tx_system_stack_top_address: + .space 4 +; +; /* Define section for placement after the main stack area for setting +; up the STACK_BASE address for hardware stack checking. */ +; + .section ".stack_base","aw" + .align 4 + .global _tx_system_stack_base_address +_tx_system_stack_base_address: + .space 4 +; +; + .text +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level ARCv2_EM/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + .global _tx_initialize_low_level + .type _tx_initialize_low_level, @function +_tx_initialize_low_level: + + .ifdef TX_ENABLE_HW_STACK_CHECKING + mov r0, _tx_system_stack_top_address ; Pickup top of system stack (lowest memory address) + sr r0, [KSTACK_TOP] ; Setup KSTACK_TOP + mov r0, _tx_system_stack_base_address ; Pickup base of system stack (highest memory address) + sr r0, [KSTACK_BASE] ; Setup KSTACK_BASE + lr r0, [status32] ; Pickup current STATUS32 + or r0, r0, STATUS32_SC ; Or in hardware stack checking enable bit (SC) + kflag r0 ; Enable hardware stack checking + .endif +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; + st sp, [gp, _tx_thread_system_stack_ptr@sda] ; Save system stack pointer +; +; +; /* Pickup the first available memory address. */ +; + mov r0, _tx_first_free_address ; Pickup first free memory address +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) _end; +; + st r0, [gp, _tx_initialize_unused_memory@sda] +; +; +; /* Setup Timer 0 for periodic interrupts at interrupt vector 16. */ +; + mov r0, 0 ; Disable additional ISR reg saving/restoring + sr r0, [AUX_IRQ_CTRL] ; + + mov r0, 16 ; Select timer 0 + sr r0, [IRQ_SELECT] ; + mov r0, 15 ; Set timer 0 to priority 15 + sr r0, [IRQ_PRIORITY] ; + mov r0, 1 ; Enable this interrupt + sr r0, [IRQ_ENABLE] ; + mov r0, 0x10000 ; Setup timer period + sr r0, [LIMIT0] ; + mov r0, 0 ; Clear timer 0 current count + sr r0, [COUNT0] ; + mov r0, 3 ; Enable timer 0 + sr r0, [CONTROL0] ; + + .ifdef TX_TIMER_1_SETUP + mov r0, 17 ; Select timer 1 + sr r0, [IRQ_SELECT] ; + mov r0, 2 ; Set timer 1 to priority 14 + sr r0, [IRQ_PRIORITY] ; + mov r0, 1 ; Enable this interrupt + sr r0, [IRQ_ENABLE] ; + mov r0, 0x10020 ; Setup timer period + sr r0, [LIMIT1] ; + mov r0, 0 ; Clear timer 0 current count + sr r0, [COUNT1] ; + mov r0, 3 ; Enable timer 0 + sr r0, [CONTROL1] ; + .endif +; +; /* Done, return to caller. */ +; + j_s.d [blink] ; Return to caller + nop +;} +; +; +; /* Define default vector table entries. */ +; + .global _tx_memory_error +_tx_memory_error: + flag 1 + nop + nop + nop + b _tx_memory_error + + .global _tx_instruction_error +_tx_instruction_error: + flag 1 + nop + nop + nop + b _tx_instruction_error + + .global _tx_ev_machine_check +_tx_ev_machine_check: + flag 1 + nop + nop + nop + b _tx_ev_machine_check + + .global _tx_ev_tblmiss_inst +_tx_ev_tblmiss_inst: + flag 1 + nop + nop + nop + b _tx_ev_tblmiss_inst + + .global _tx_ev_tblmiss_data +_tx_ev_tblmiss_data: + flag 1 + nop + nop + nop + b _tx_ev_tblmiss_data + + .global _tx_ev_protection_viol +_tx_ev_protection_viol: + flag 1 + nop + nop + nop + b _tx_ev_protection_viol + + .global _tx_ev_privilege_viol +_tx_ev_privilege_viol: + flag 1 + nop + nop + nop + b _tx_ev_privilege_viol + + .global _tx_ev_software_int +_tx_ev_software_int: + flag 1 + nop + nop + nop + b _tx_ev_software_int + + .global _tx_ev_trap +_tx_ev_trap: + flag 1 + nop + nop + nop + b _tx_ev_trap + + .global _tx_ev_extension +_tx_ev_extension: + flag 1 + nop + nop + nop + b _tx_ev_extension + + .global _tx_ev_divide_by_zero +_tx_ev_divide_by_zero: + flag 1 + nop + nop + nop + b _tx_ev_divide_by_zero + + .global _tx_ev_dc_error +_tx_ev_dc_error: + flag 1 + nop + nop + nop + b _tx_ev_dc_error + + .global _tx_ev_maligned +_tx_ev_maligned: + flag 1 + nop + nop + nop + b _tx_ev_maligned + + .global _tx_unsued_0 +_tx_unsued_0: + flag 1 + nop + nop + nop + b _tx_unsued_0 + + .global _tx_unused_1 +_tx_unused_1: + flag 1 + nop + nop + nop + b _tx_unused_1 + + .global _tx_timer_0 +_tx_timer_0: +; +; /* By default, setup Timer 0 as the ThreadX timer interrupt. */ +; + sub sp, sp, 160 ; Allocate an interrupt stack frame + st r0, [sp, 0] ; Save r0 + st r1, [sp, 4] ; Save r1 + st r2, [sp, 8] ; Save r2 + mov r0, 3 + sr r0, [CONTROL0] + + b _tx_timer_interrupt ; Jump to generic ThreadX timer interrupt + ; handler +; flag 1 +; nop +; nop +; nop +; b _tx_timer_0 + + .global _tx_timer_1 +_tx_timer_1: + sub sp, sp, 160 ; Allocate an interrupt stack frame + st blink, [sp, 16] ; Save blink + bl _tx_thread_context_save ; Call context save +; +; /* ISR processing goes here. If the applications wishes to re-enable +; interrupts, the SETI instruction can be used here. Also note that +; register usage in assembly code must be confined to the compiler +; scratch registers. */ +; + mov r0, 3 + sr r0, [CONTROL1] +; + b _tx_thread_context_restore ; Call context restore + +; flag 1 +; nop +; nop +; nop +; b _tx_timer_1 + + .global _tx_undefined_0 +_tx_undefined_0: + flag 1 + nop + nop + nop + b _tx_undefined_0 + + .global _tx_undefined_1 +_tx_undefined_1: + flag 1 + nop + nop + nop + b _tx_undefined_1 + + .global _tx_undefined_2 +_tx_undefined_2: + flag 1 + nop + nop + nop + b _tx_undefined_2 + + .end diff --git a/ports/arc_em/metaware/example_build/sample_threadx/vectors.s b/ports/arc_em/metaware/example_build/sample_threadx/vectors.s new file mode 100644 index 00000000..c6cbc893 --- /dev/null +++ b/ports/arc_em/metaware/example_build/sample_threadx/vectors.s @@ -0,0 +1,29 @@ + +.file "vectors.s" +.section .ivt,text +;; This directive forces this section to stay resident even if stripped out by the -zpurgetext linker option +.sectflag .ivt,include + +;// handler's name type number name offset in IVT (hex/dec) +.long _start ; exception 0 program entry point offset 0x0 0 +.long _tx_memory_error ; exception 1 memory_error offset 0x4 4 +.long _tx_instruction_error ; exception 2 instruction_error offset 0x8 8 +.long _tx_ev_machine_check ; exception 3 EV_MachineCheck offset 0xC 12 +.long _tx_ev_tblmiss_inst ; exception 4 EV_TLBMissI offset 0x10 16 +.long _tx_ev_tblmiss_data ; exception 5 EV_TLBMissD offset 0x14 20 +.long _tx_ev_protection_viol ; exception 6 EV_ProtV offset 0x18 24 +.long _tx_ev_privilege_viol ; exception 7 EV_PrivilegeV offset 0x1C 28 +.long _tx_ev_software_int ; exception 8 EV_SWI offset 0x20 32 +.long _tx_ev_trap ; exception 9 EV_Trap offset 0x24 36 +.long _tx_ev_extension ; exception 10 EV_Extension offset 0x28 40 +.long _tx_ev_divide_by_zero ; exception 11 EV_DivZero offset 0x2C 44 +.long _tx_ev_dc_error ; exception 12 EV_DCError offset 0x30 48 +.long _tx_ev_maligned ; exception 13 EV_Maligned offset 0x34 52 +.long _tx_unsued_0 ; exception 14 unused offset 0x38 56 +.long _tx_unused_1 ; exception 15 unused offset 0x3C 60 +.long _tx_timer_0 ; IRQ 16 Timer 0 offset 0x40 64 +.long _tx_timer_1 ; IRQ 17 Timer 1 offset 0x44 68 +.long _tx_undefined_0 ; IRQ 18 offset 0x48 72 +.long _tx_undefined_1 ; IRQ 19 offset 0x4C 76 +.long _tx_undefined_2 ; IRQ 20 offset 0x50 80 + diff --git a/ports/arc_em/metaware/example_build/tx/.cproject b/ports/arc_em/metaware/example_build/tx/.cproject new file mode 100644 index 00000000..ce329051 --- /dev/null +++ b/ports/arc_em/metaware/example_build/tx/.cproject @@ -0,0 +1,137 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/arc_em/metaware/example_build/tx/.project b/ports/arc_em/metaware/example_build/tx/.project new file mode 100644 index 00000000..863ca5cb --- /dev/null +++ b/ports/arc_em/metaware/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/arc_em/metaware/example_build/tx/.settings/language.settings.xml b/ports/arc_em/metaware/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..a0e8c9c5 --- /dev/null +++ b/ports/arc_em/metaware/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/arc_em/metaware/inc/tx_port.h b/ports/arc_em/metaware/inc/tx_port.h new file mode 100644 index 00000000..0a197ab6 --- /dev/null +++ b/ports/arc_em/metaware/inc/tx_port.h @@ -0,0 +1,325 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARCv2_EM/MetaWare */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Remove volatile for ThreadX source on the ARC. This is because the ARC + compiler generates different non-cache r/w access when using volatile + that is different from the assembly language access of the same + global variables in ThreadX. */ + +#ifdef TX_SOURCE_CODE +#define volatile +#else +#ifdef NX_SOURCE_CODE +#define volatile +#else +#ifdef FX_SOURCE_CODE +#define volatile +#else +#ifdef UX_SOURCE_CODE +#define volatile +#endif +#endif +#endif +#endif + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 800 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 2048 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARCv2 EM port. */ + +#define TX_INT_ENABLE 0x0000001F /* Enable all interrupts */ +#define TX_INT_DISABLE_MASK 0x00000000 /* Disable all interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 VOID *__mw_threadx_tls; \ + int __mw_errnum; \ + VOID (*__mw_thread_exit)(struct TX_THREAD_STRUCT *); +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#if __HIGHC__ + +/* The MetaWare thread safe C/C++ runtime library needs space to + store thread specific information. In addition, a function pointer + is also supplied so that certain thread-specific resources may be + released upon thread termination and/or thread completion. */ + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + thread_ptr -> __mw_threadx_tls = 0; \ + thread_ptr -> __mw_errnum = 0; \ + thread_ptr -> __mw_thread_exit = TX_NULL; +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) \ + if (thread_ptr -> __mw_thread_exit) \ + (thread_ptr -> __mw_thread_exit) (thread_ptr); +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) \ + if (thread_ptr -> __mw_thread_exit) \ + (thread_ptr -> __mw_thread_exit) (thread_ptr); + +#else + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _clri(); +#define TX_RESTORE _seti(interrupt_save); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARCv2_EM/MetaWare Version 6.0 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + + diff --git a/ports/arc_em/metaware/readme_threadx.txt b/ports/arc_em/metaware/readme_threadx.txt new file mode 100644 index 00000000..dcba11a8 --- /dev/null +++ b/ports/arc_em/metaware/readme_threadx.txt @@ -0,0 +1,219 @@ + Microsoft's Azure RTOS ThreadX for ARC EM + + Using the MetaWare Tools + +1. Open the Azure RTOS Workspace + +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace, which is located inside the "example_build" directory. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the ThreadX library project +file "tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the MetaWare ARCv2 EM +simulation. The instructions that follow describe how to get the ThreadX +demonstration running. + +Building the demonstration is easy; simply select the demonstration project file +"sample_threadx." At this point, select the build button and observe the +compilation, assembly, and linkage of the ThreadX demonstration application. + +After the demonstration is built, click on the "Debug" button and it will +automatically launch a pre-configured connection to the ARCv2 EM simulator. + +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c +application. + + +4. System Initialization + +The system entry point using the MetaWare tools is at the label _start. +This is defined within the crt1.s file supplied by MetaWare. In addition, +this is where all static and global preset C variable initialization +processing is called from. + +After the MetaWare startup function completes, ThreadX initialization is +called. The main initialization function is _tx_initialize_low_level and +is located in the file tx_initialize_low_level.s. This function is +responsible for setting up various system data structures, and interrupt +vectors. + +By default free memory is assumed to start at the section .free_memory +which is referenced in tx_initialize_low_level.s and located in the +linker control file after all the linker defined RAM addresses. This is +the address passed to the application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The ARC compiler assumes that registers r0-r12 are scratch registers for +each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a +context switch happens as a result of making a ThreadX service call (which +is itself a C function). In such cases, the saved context of a thread is +only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 LP_START blink + 0x08 LP_END fp + 0x0C LP_COUNT r26 + 0x10 blink r25 + 0x14 ilink r24 + 0x18 fp r23 + 0x1C r26 r22 + 0x20 r25 r21 + 0x24 r24 r20 + 0x28 r23 r19 + 0x2C r22 r18 + 0x30 r21 r17 + 0x34 r20 r16 + 0x38 r19 r15 + 0x3C r18 r14 + 0x40 r17 r13 + 0x44 r16 STATUS32 + 0x48 r15 r30 + 0x4C r14 + 0x50 r13 + 0x54 r12 + 0x58 r11 + 0x5C r10 + 0x60 r9 + 0x64 r8 + 0x68 r7 + 0x6C r6 + 0x70 r5 + 0x74 r4 + 0x78 r3 + 0x7C r2 + 0x80 r1 + 0x84 r0 + 0x88 r30 + 0x8C r58 (if TX_ENABLE_ACC defined) + 0x90 r59 (if TX_ENABLE_ACC defined) + 0x94 reserved + 0x98 reserved + 0x9C bta + 0xA0 point of interrupt + 0xA4 STATUS32 + + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat +file to remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for the +ARCv2 EM processor. The following template should be used for interrupts +managed by ThreadX: + + .global _tx_interrupt_x +_tx_interrupt_x: + sub sp, sp, 160 ; Allocate an interrupt stack frame + st blink, [sp, 16] ; Save blink (blink must be saved before _tx_thread_context_save) + bl _tx_thread_context_save ; Save interrupt context +; +; /* Application ISR processing goes here! Your ISR can be written in +; assembly language or in C. If it is written in C, you must allocate +; 16 bytes of stack space before it is called. This must also be +; recovered once your C ISR return. An example of this is shown below. +; +; If the ISR is written in assembly language, only the compiler scratch +; registers are available for use without saving/restoring (r0-r12). +; If use of additional registers are required they must be saved and +; restored. */ +; + bl.d your_ISR_written_in_C ; Call an ISR written in C + sub sp, sp, 16 ; Allocate stack space (delay slot) + add sp, sp, 16 ; Recover stack space + +; + b _tx_thread_context_restore ; Restore interrupt context + + +The application handle interrupts directly, which necessitates all register +preservation by the application's ISR. ISRs that do not use the ThreadX +_tx_thread_context_save and _tx_thread_context_restore routines are not +allowed access to the ThreadX API. In addition, custom application ISRs +should be higher priority than all ThreadX-managed ISRs. + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of +ThreadX will still run. + +By default, the ThreadX timer interrupt is mapped to the ARCv2 EM auxiliary +timer 0, which generates low priority interrupts on interrupt vector 16. +It is easy to change the timer interrupt source and priority by changing the +setup code in tx_initialize_low_level.s. + + +9. Hardware Stack Checking + +ThreadX optionally supports the ARCv2 EM hardware stack checking feature. When enabled, +the KSTACK_TOP and KSTACK_BASE registers are loaded with the stack top/bottom before +each thread's execution. In addition, the SC bit of STATUS32 is set to enable the stack +checking feature. During initialization, idle, or interrupt processing, the hardware +stack checking on the system stack is performed, when enabled. + +To enable ThreadX support for hardware stack checking, simply build the ThreadX library +and application assembly code with TX_ENABLE_HW_STACK_CHECKING defined. This will enable +the stack checking logic in ThreadX. + +For the system stack checking to function properly, there are two sections that must +be located around the .stack section, which defines the system stack location and size. +The new sections are .stack_top and .stack_base. The .stack_top section should be placed +immediately BEFORE the .stack section and .stack_base should be placed immediately AFTER +the .stack section. Please see the sample_threadx.cmd linker control file for an example. + +When/if a stack exception occurs, the hardware will fetch the _tx_ev_protection_viol +exception defined in tx_initialize_low_level.s. Processing for this exception is +application specific. + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 for ARCv2 EM using MetaWare tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/arc_em/metaware/src/tx_initialize_low_level.s b/ports/arc_em/metaware/src/tx_initialize_low_level.s new file mode 100644 index 00000000..8b75bf9f --- /dev/null +++ b/ports/arc_em/metaware/src/tx_initialize_low_level.s @@ -0,0 +1,360 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + .equ IRQ_SELECT, 0x40B + .equ KSTACK_TOP, 0x264 + .equ KSTACK_BASE, 0x265 + .equ STATUS32_SC, 0x4000 +; +; +; /* Define section for placement after all linker allocated RAM memory. This +; is used to calculate the first free address that is passed to +; tx_appication_define, soley for the ThreadX application's use. */ +; + .section ".free_memory","aw" + .align 4 + .global _tx_first_free_address +_tx_first_free_address: + .space 4 +; +; /* Define section for placement before the main stack area for setting +; up the STACK_TOP address for hardware stack checking. */ +; + .section ".stack_top","aw" + .align 4 + .global _tx_system_stack_top_address +_tx_system_stack_top_address: + .space 4 +; +; /* Define section for placement after the main stack area for setting +; up the STACK_BASE address for hardware stack checking. */ +; + .section ".stack_base","aw" + .align 4 + .global _tx_system_stack_base_address +_tx_system_stack_base_address: + .space 4 +; +; + .text +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level ARCv2_EM/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + .global _tx_initialize_low_level + .type _tx_initialize_low_level, @function +_tx_initialize_low_level: + + .ifdef TX_ENABLE_HW_STACK_CHECKING + mov r0, _tx_system_stack_top_address ; Pickup top of system stack (lowest memory address) + sr r0, [KSTACK_TOP] ; Setup KSTACK_TOP + mov r0, _tx_system_stack_base_address ; Pickup base of system stack (highest memory address) + sr r0, [KSTACK_BASE] ; Setup KSTACK_BASE + lr r0, [status32] ; Pickup current STATUS32 + or r0, r0, STATUS32_SC ; Or in hardware stack checking enable bit (SC) + kflag r0 ; Enable hardware stack checking + .endif +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; + st sp, [gp, _tx_thread_system_stack_ptr@sda] ; Save system stack pointer +; +; +; /* Pickup the first available memory address. */ +; + mov r0, _tx_first_free_address ; Pickup first free memory address +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) _end; +; + st r0, [gp, _tx_initialize_unused_memory@sda] +; +; +; /* Setup Timer 0 for periodic interrupts at interrupt vector 16. */ +; + mov r0, 0 ; Disable additional ISR reg saving/restoring + sr r0, [AUX_IRQ_CTRL] ; + + mov r0, 16 ; Select timer 0 + sr r0, [IRQ_SELECT] ; + mov r0, 15 ; Set timer 0 to priority 15 + sr r0, [IRQ_PRIORITY] ; + mov r0, 1 ; Enable this interrupt + sr r0, [IRQ_ENABLE] ; + mov r0, 0x10000 ; Setup timer period + sr r0, [LIMIT0] ; + mov r0, 0 ; Clear timer 0 current count + sr r0, [COUNT0] ; + mov r0, 3 ; Enable timer 0 + sr r0, [CONTROL0] ; + + .ifdef TX_TIMER_1_SETUP + mov r0, 17 ; Select timer 1 + sr r0, [IRQ_SELECT] ; + mov r0, 2 ; Set timer 1 to priority 14 + sr r0, [IRQ_PRIORITY] ; + mov r0, 1 ; Enable this interrupt + sr r0, [IRQ_ENABLE] ; + mov r0, 0x10020 ; Setup timer period + sr r0, [LIMIT1] ; + mov r0, 0 ; Clear timer 0 current count + sr r0, [COUNT1] ; + mov r0, 3 ; Enable timer 0 + sr r0, [CONTROL1] ; + .endif +; +; /* Done, return to caller. */ +; + j_s.d [blink] ; Return to caller + nop +;} +; +; +; /* Define default vector table entries. */ +; + .global _tx_memory_error +_tx_memory_error: + flag 1 + nop + nop + nop + b _tx_memory_error + + .global _tx_instruction_error +_tx_instruction_error: + flag 1 + nop + nop + nop + b _tx_instruction_error + + .global _tx_ev_machine_check +_tx_ev_machine_check: + flag 1 + nop + nop + nop + b _tx_ev_machine_check + + .global _tx_ev_tblmiss_inst +_tx_ev_tblmiss_inst: + flag 1 + nop + nop + nop + b _tx_ev_tblmiss_inst + + .global _tx_ev_tblmiss_data +_tx_ev_tblmiss_data: + flag 1 + nop + nop + nop + b _tx_ev_tblmiss_data + + .global _tx_ev_protection_viol +_tx_ev_protection_viol: + flag 1 + nop + nop + nop + b _tx_ev_protection_viol + + .global _tx_ev_privilege_viol +_tx_ev_privilege_viol: + flag 1 + nop + nop + nop + b _tx_ev_privilege_viol + + .global _tx_ev_software_int +_tx_ev_software_int: + flag 1 + nop + nop + nop + b _tx_ev_software_int + + .global _tx_ev_trap +_tx_ev_trap: + flag 1 + nop + nop + nop + b _tx_ev_trap + + .global _tx_ev_extension +_tx_ev_extension: + flag 1 + nop + nop + nop + b _tx_ev_extension + + .global _tx_ev_divide_by_zero +_tx_ev_divide_by_zero: + flag 1 + nop + nop + nop + b _tx_ev_divide_by_zero + + .global _tx_ev_dc_error +_tx_ev_dc_error: + flag 1 + nop + nop + nop + b _tx_ev_dc_error + + .global _tx_ev_maligned +_tx_ev_maligned: + flag 1 + nop + nop + nop + b _tx_ev_maligned + + .global _tx_unsued_0 +_tx_unsued_0: + flag 1 + nop + nop + nop + b _tx_unsued_0 + + .global _tx_unused_1 +_tx_unused_1: + flag 1 + nop + nop + nop + b _tx_unused_1 + + .global _tx_timer_0 +_tx_timer_0: +; +; /* By default, setup Timer 0 as the ThreadX timer interrupt. */ +; + sub sp, sp, 160 ; Allocate an interrupt stack frame + st r0, [sp, 0] ; Save r0 + st r1, [sp, 4] ; Save r1 + st r2, [sp, 8] ; Save r2 + mov r0, 3 + sr r0, [CONTROL0] + + b _tx_timer_interrupt ; Jump to generic ThreadX timer interrupt + ; handler +; flag 1 +; nop +; nop +; nop +; b _tx_timer_0 + + .global _tx_timer_1 +_tx_timer_1: + sub sp, sp, 160 ; Allocate an interrupt stack frame + st blink, [sp, 16] ; Save blink + bl _tx_thread_context_save ; Call context save +; +; /* ISR processing goes here. If the applications wishes to re-enable +; interrupts, the SETI instruction can be used here. Also note that +; register usage in assembly code must be confined to the compiler +; scratch registers. */ +; + mov r0, 3 + sr r0, [CONTROL1] +; + b _tx_thread_context_restore ; Call context restore + +; flag 1 +; nop +; nop +; nop +; b _tx_timer_1 + + .global _tx_undefined_0 +_tx_undefined_0: + flag 1 + nop + nop + nop + b _tx_undefined_0 + + .global _tx_undefined_1 +_tx_undefined_1: + flag 1 + nop + nop + nop + b _tx_undefined_1 + + .global _tx_undefined_2 +_tx_undefined_2: + flag 1 + nop + nop + nop + b _tx_undefined_2 + + .end diff --git a/ports/arc_em/metaware/src/tx_thread_context_restore.s b/ports/arc_em/metaware/src/tx_thread_context_restore.s new file mode 100644 index 00000000..8bc31394 --- /dev/null +++ b/ports/arc_em/metaware/src/tx_thread_context_restore.s @@ -0,0 +1,302 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; + .equ BTA, 0x412 + .equ KSTACK_TOP, 0x264 + .equ KSTACK_BASE, 0x265 + .equ STATUS32_SC, 0x4000 +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore ARCv2_EM/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore, @function +_tx_thread_context_restore: +; +; /* Note: it is assumed that the stack pointer is in the same position now as +; it was after the last context save call. */ +; +; /* Lockout interrupts. */ +; + clri ; Disable interrupts + nop ; Delay for interrupts to really be disabled + + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + bl.d _tx_execution_isr_exit ; Call the ISR exit function + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space + .endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + ld r0, [gp, _tx_thread_system_state@sda] ; Pickup system state contents + sub r0, r0, 1 ; Decrement the system state + st r0, [gp, _tx_thread_system_state@sda] ; Store the new system state + breq r0, 0, __tx_thread_not_nested_restore ; If zero, not a nested interrupt +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + +__tx_thread_nested_restore: + + ld r0, [sp, 4] ; Recover LP_START + sr r0, [LP_START] ; Restore LP_START + ld r1, [sp, 8] ; Recover LP_END + sr r1, [LP_END] ; Restore LP_END + ld r2, [sp, 12] ; Recover LP_COUNT + mov LP_COUNT, r2 + ld r2, [sp, 156] ; Pickup BTA + sr r2, [BTA] ; Recover BTA + .ifdef TX_ENABLE_ACC + ld r58, [sp, 140] ; Recover r58 + ld r59, [sp, 144] ; Recover r59 + .endif + ld blink, [sp, 16] ; Recover blink + ld r12, [sp, 84] ; Recover r12 + ld r11, [sp, 88] ; Recover r11 + ld r10, [sp, 92] ; Recover r10 + ld r9, [sp, 96] ; Recover r9 + ld r8, [sp, 100] ; Recover r8 + ld r7, [sp, 104] ; Recover r7 + ld r6, [sp, 108] ; Recover r6 + ld r5, [sp, 112] ; Recover r5 + ld r4, [sp, 116] ; Recover r4 + ld r3, [sp, 120] ; Recover r3 + ld r2, [sp, 124] ; Recover r2 + ld r1, [sp, 128] ; Recover r1 + ld r0, [sp, 132] ; Recover r0 + add sp, sp, 160 ; Recover interrupt stack frame + rtie ; Return from interrupt +; +; +; } +__tx_thread_not_nested_restore: +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread pointer + ld r2, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable flag + sub.f 0, r0, 0 ; Set condition codes + beq.d __tx_thread_idle_system_restore ; If NULL, idle system was interrupted + lr r4, [AUX_IRQ_ACT] ; Pickup the interrupt active register + neg r5, r4 ; Negate + and r5, r4, r5 ; See if there are any other interrupts present + brne.d r4, r5, __tx_thread_no_preempt_restore ; If more interrupts, just return to the point of interrupt + ld r4, [gp, _tx_thread_execute_ptr@sda] ; Pickup next thread to execute + brne r2, 0, __tx_thread_no_preempt_restore ; If set, don't preempt executing thread + brne r0, r4, __tx_thread_preempt_restore ; Not equal, preempt executing thread +; +; +__tx_thread_no_preempt_restore: +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; + +; /* Recover the saved context and return to the point of interrupt. */ +; + + .ifdef TX_ENABLE_HW_STACK_CHECKING + lr r2, [status32] ; Pickup current STATUS32 + and r2, r2, ~STATUS32_SC ; Clear the hardware stack checking enable bit (SC) + kflag r2 ; Disable hardware stack checking + ld r3, [r0, 12] ; Pickup the top of the thread's stack (lowest address) + sr r3, [KSTACK_TOP] ; Setup KSTACK_TOP + ld r3, [r0, 16] ; Pickup the base of the thread's stack (highest address) + sr r3, [KSTACK_BASE] ; Setup KSTACK_BASE + .endif + + ld sp, [r0, 8] ; Switch back to thread's stack + + .ifdef TX_ENABLE_HW_STACK_CHECKING + or r2, r2, STATUS32_SC ; Or in hardware stack checking enable bit (SC) + kflag r2 ; Enable hardware stack checking + .endif + + ld r0, [sp, 4] ; Recover LP_START + sr r0, [LP_START] ; Restore LP_START + ld r1, [sp, 8] ; Recover LP_END + sr r1, [LP_END] ; Restore LP_END + ld r2, [sp, 12] ; Recover LP_COUNT + mov LP_COUNT, r2 + ld r2, [sp, 156] ; Pickup BTA + sr r2, [BTA] ; Recover BTA + .ifdef TX_ENABLE_ACC + ld r58, [sp, 140] ; Recover r58 + ld r59, [sp, 144] ; Recover r59 + .endif + ld blink, [sp, 16] ; Recover blink + ld r12, [sp, 84] ; Recover r12 + ld r11, [sp, 88] ; Recover r11 + ld r10, [sp, 92] ; Recover r10 + ld r9, [sp, 96] ; Recover r9 + ld r8, [sp, 100] ; Recover r8 + ld r7, [sp, 104] ; Recover r7 + ld r6, [sp, 108] ; Recover r6 + ld r5, [sp, 112] ; Recover r5 + ld r4, [sp, 116] ; Recover r4 + ld r3, [sp, 120] ; Recover r3 + ld r2, [sp, 124] ; Recover r2 + ld r1, [sp, 128] ; Recover r1 + ld r0, [sp, 132] ; Recover r0 + add sp, sp, 160 ; Recover interrupt stack frame + rtie ; Return from interrupt +; +; } +; else +; { +__tx_thread_preempt_restore: +; + ld r7, [r0, 8] ; Pickup stack pointer + mov r6, 1 ; Build interrupt stack type + st r6, [r7, 0] ; Setup interrupt stack type + st fp, [r7, 24] ; Save fp + st gp, [r7, 28] ; Save gp + st r25, [r7, 32] ; Save r25 + st r24, [r7, 36] ; Save r24 + st r23, [r7, 40] ; Save r23 + st r22, [r7, 44] ; Save r22 + st r21, [r7, 48] ; Save r21 + st r20, [r7, 52] ; Save r20 + st r19, [r7, 56] ; Save r19 + st r18, [r7, 60] ; Save r18 + st r17, [r7, 64] ; Save r17 + st r16, [r7, 68] ; Save r16 + st r15, [r7, 72] ; Save r15 + st r14, [r7, 76] ; Save r14 + st r13, [r7, 80] ; Save r13 + st r30, [r7, 136] ; Save r30 +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + ld r2, [gp, _tx_timer_time_slice@sda] ; Pickup time-slice contents + mov r7, 0 ; Build clear/NULL value + breq r2, 0, __tx_thread_dont_save_ts ; No time-slice, don't need to save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + st r2, [r0, 24] ; If set, save remaining time-slice + st r7, [gp, _tx_timer_time_slice@sda] ; If set, clear time slice +; +; } +__tx_thread_dont_save_ts: +; +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + st r7, [gp, _tx_thread_current_ptr@sda] ; Set current thread ptr to NULL + + sub sp, sp, 8 ; Allocate a small stack frame on the system stack + lr r0, [STATUS32] ; Pickup STATUS32 + st r0, [sp, 4] ; Place on stack + mov r0, _tx_thread_schedule ; Build address of scheduler + st r0, [sp, 0] ; Write over the point of interrupt + rtie ; Return from interrupt to scheduler +; +; } +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; +__tx_thread_idle_system_restore: + + lr r4, [AUX_IRQ_ACT] ; Pickup the interrupt active register + neg r5, r4 ; Negate + and r5, r4, r5 ; See if there are any other interrupts present + sub.f 0, r4, r5 ; Set condition codes + bne __tx_thread_nested_restore ; If more interrupts, just return to the point of interrupt + + lr r0, [STATUS32] ; Pickup STATUS32 + st r0, [sp, 4] ; Place on stack + mov r0, _tx_thread_schedule ; Build address of scheduler + st r0, [sp, 0] ; Write over the point of interrupt + rtie ; Return from interrupt to scheduler +; +;} + .end + diff --git a/ports/arc_em/metaware/src/tx_thread_context_save.s b/ports/arc_em/metaware/src/tx_thread_context_save.s new file mode 100644 index 00000000..e60bc856 --- /dev/null +++ b/ports/arc_em/metaware/src/tx_thread_context_save.s @@ -0,0 +1,260 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; + .equ BTA, 0x412 + .equ KSTACK_TOP, 0x264 + .equ KSTACK_BASE, 0x265 + .equ STATUS32_SC, 0x4000 +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save ARCv2_EM/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + .global _tx_thread_context_save + .type _tx_thread_context_save, @function +_tx_thread_context_save: +; +; /* Upon entry to this routine, it is assumed that an interrupt stack frame +; has already been allocated, and the interrupted blink register is already saved. */ +; + clri ; Disable interrupts + st r1, [sp, 128] ; Save r1 + st r0, [sp, 132] ; Save r0 +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + ld r0, [gp, _tx_thread_system_state@sda] ; Pickup system state + st r3, [sp, 120] ; Save r3 + st r2, [sp, 124] ; Save r2 + breq r0, 0, __tx_thread_not_nested_save ; If 0, we are not in a nested + ; condition +; +; /* Nested interrupt condition. */ +; + add r0, r0, 1 ; Increment the nested interrupt count + st r0, [gp, _tx_thread_system_state@sda] ; Update system state +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; +__tx_thread_nested_save: ; Label is for special nested interrupt case from idle system save below + st r12, [sp, 84] ; Save r12 + st r11, [sp, 88] ; Save r11 + st r10, [sp, 92] ; Save r10 + st r9, [sp, 96] ; Save r9 + st r8, [sp, 100] ; Save r8 + st r7, [sp, 104] ; Save r7 + st r6, [sp, 108] ; Save r6 + st r5, [sp, 112] ; Save r5 + st r4, [sp, 116] ; Save r6 + lr r10, [LP_START] ; Pickup LP_START + lr r9, [LP_END] ; Pickup LP_END + st LP_COUNT, [sp, 12] ; Save LP_COUNT + st r10, [sp, 4] ; Save LP_START + st r9, [sp, 8] ; Save LP_END + .ifdef TX_ENABLE_ACC + st r58, [sp, 140] ; Save r58 + st r59, [sp, 144] ; Save r59 + .endif + lr r0, [BTA] ; Pickup BTA + st r0, [sp, 156] ; Save BTA + +; +; /* Return to the ISR. */ +; + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + sub sp, sp, 32 ; Allocating some space on the stack + st blink, [sp, 16] ; Save blink + bl.d _tx_execution_isr_enter ; Call the ISR enter function + nop ; Delay slot + ld blink, [sp, 16] ; Recover blink + add sp, sp, 32 ; Recover the stack space + .endif +; + + j.d [blink] ; Return to Level 1 ISR + st ilink, [sp, 20] ; Save ilink +; +__tx_thread_not_nested_save: +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + add r0, r0, 1 ; Increment the nested interrupt count + st r0, [gp, _tx_thread_system_state@sda] ; Update system state + ld r1, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread pointer + st r12, [sp, 84] ; Save r12 + st r11, [sp, 88] ; Save r11 + breq r1, 0, __tx_thread_idle_system_save ; If no thread is running, idle system was + ; interrupted. +; +; /* Save minimal context of interrupted thread. */ +; + st r10, [sp, 92] ; Save r10 + st r9, [sp, 96] ; Save r9 + st r8, [sp, 100] ; Save r8 + st r7, [sp, 104] ; Save r7 + st r6, [sp, 108] ; Save r6 + st r5, [sp, 112] ; Save r5 + st r4, [sp, 116] ; Save r4 + lr r10, [LP_START] ; Pickup LP_START + lr r9, [LP_END] ; Pickup LP_END + st LP_COUNT, [sp, 12] ; Save LP_COUNT + st r10, [sp, 4] ; Save LP_START + st r9, [sp, 8] ; Save LP_END + st ilink, [sp, 20] ; Save ilink + .ifdef TX_ENABLE_ACC + st r58, [sp, 140] ; Save r58 + st r59, [sp, 144] ; Save r59 + .endif + lr r0, [BTA] ; Pickup BTA + st r0, [sp, 156] ; Save BTA +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; + st sp, [r1, 8] ; Save thread's stack pointer + + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + sub sp, sp, 32 ; Allocating some space on the stack + st blink, [sp, 16] ; Save blink + bl.d _tx_execution_isr_enter ; Call the ISR enter function + nop ; Delay slot + ld blink, [sp, 16] ; Recover blink + add sp, sp, 32 ; Recover the stack space + .endif + + .ifdef TX_ENABLE_HW_STACK_CHECKING + lr r2, [status32] ; Pickup current STATUS32 + and r2, r2, ~STATUS32_SC ; Clear the hardware stack checking enable bit (SC) + kflag r2 ; Disable hardware stack checking + mov r1, _tx_system_stack_top_address ; Pickup top of system stack (lowest memory address) + sr r1, [KSTACK_TOP] ; Setup KSTACK_TOP + mov r1, _tx_system_stack_base_address ; Pickup base of system stack (highest memory address) + sr r1, [KSTACK_BASE] ; Setup KSTACK_BASE + ld sp, [gp, _tx_thread_system_stack_ptr@sda] ; Switch to system stack + or r2, r2, STATUS32_SC ; Or in hardware stack checking enable bit (SC) + j_s.d [blink] ; Return to calling ISR + kflag r2 ; Enable hardware stack checking + .else +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + j_s.d [blink] ; Return to calling ISR + ld sp, [gp, _tx_thread_system_stack_ptr@sda] ; Switch to system stack + .endif +; +; } +; else +; { +; +__tx_thread_idle_system_save: +; +; /* Interrupt occurred in the scheduling loop. */ +; + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + sub sp, sp, 32 ; Allocating some space on the stack + st blink, [sp, 16] ; Save blink + bl.d _tx_execution_isr_enter ; Call the ISR enter function + nop ; Delay slot + ld blink, [sp, 16] ; Recover blink + add sp, sp, 32 ; Recover the stack space + .endif +; +; /* See if we have a special nesting condition. This happens when the higher priority +; interrupt occurs before the nested interrupt logic is valid. */ +; + lr r0, [AUX_IRQ_ACT] ; Pickup the interrupt active register + neg r1, r0 ; Negate + and r1, r0, r1 ; See if there are any other interrupts present + brne r0, r1, __tx_thread_nested_save ; If more interrupts, go into the nested interrupt save logic +; +; /* Not much to do here, just adjust the stack pointer, and return to +; ISR processing. */ +; + j_s.d [blink] ; Return to ISR + add sp, sp, 160 ; Recover stack space +; +; } +;} + .end diff --git a/ports/arc_em/metaware/src/tx_thread_interrupt_control.s b/ports/arc_em/metaware/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..5bdf3ccb --- /dev/null +++ b/ports/arc_em/metaware/src/tx_thread_interrupt_control.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control ARCv2_EM/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control, @function +_tx_thread_interrupt_control: +; +; /* Pickup current interrupt lockout posture. */ +; + clri r1 ; Get current interrupt state +; +; /* Apply the new interrupt posture. */ +; + seti r0 ; Set desired interrupt state + j_s.d [blink] ; Return to caller with delay slot + mov r0, r1 ; Return previous mask value. Return value is TX_INT_DISABLE or TX_INT_ENABLE. +; +;} + .end diff --git a/ports/arc_em/metaware/src/tx_thread_schedule.s b/ports/arc_em/metaware/src/tx_thread_schedule.s new file mode 100644 index 00000000..2a310a16 --- /dev/null +++ b/ports/arc_em/metaware/src/tx_thread_schedule.s @@ -0,0 +1,238 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; + .equ BTA, 0x412 + .equ KSTACK_TOP, 0x264 + .equ KSTACK_BASE, 0x265 + .equ STATUS32_SC, 0x4000 +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule ARCv2_EM/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + .global _tx_thread_schedule + .type _tx_thread_schedule, @function +_tx_thread_schedule: +; +; /* Enable interrupts. */ +; + mov r0, 0x1F ; Build enable interrupt value + seti r0 ; Enable interrupts +; +; /* Wait for a thread to execute. */ +; do +; { +; +__tx_thread_schedule_loop: +; + ld r0, [gp, _tx_thread_execute_ptr@sda] ; Pickup next thread to execute + breq r0, 0, __tx_thread_schedule_loop ; If NULL, keep looking +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + clri ; Lockout interrupts + nop ; Delay for interrupts to really be disabled +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + st r0, [gp, _tx_thread_current_ptr@sda] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + ld r3, [r0, 4] ; Pickup run counter + ld r4, [r0, 24] ; Pickup time-slice for this thread + add r3, r3, 1 ; Increment run counter + st r3, [r0, 4] ; Store the new run counter + + .ifdef TX_ENABLE_HW_STACK_CHECKING + lr r2, [status32] ; Pickup current STATUS32 + and r2, r2, ~STATUS32_SC ; Clear the hardware stack checking enable bit (SC) + kflag r2 ; Disable hardware stack checking + ld r3, [r0, 12] ; Pickup the top of the thread's stack (lowest address) + sr r3, [KSTACK_TOP] ; Setup KSTACK_TOP + ld r3, [r0, 16] ; Pickup the base of the thread's stack (highest address) + sr r3, [KSTACK_BASE] ; Setup KSTACK_BASE + .endif +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + ld sp, [r0, 8] ; Switch to thread's stack + + .ifdef TX_ENABLE_HW_STACK_CHECKING + or r2, r2, STATUS32_SC ; Or in hardware stack checking enable bit (SC) + kflag r2 ; Enable hardware stack checking + .endif + + st r4, [gp, _tx_timer_time_slice@sda] ; Setup time-slice +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + bl.d _tx_execution_thread_enter ; Call the thread execution enter function + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space + .endif +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + ld r1, [sp, 0] ; Pickup the stack type + brne r1, 0, __tx_thread_schedule_int_ret ; Compare to solicited stack type. If not, thread was interrupted + ld blink, [sp, 4] ; Recover blink + ld fp, [sp, 8] ; Recover fp + ld gp, [sp, 12] ; Recover gp + ld r25, [sp, 16] ; Recover r25 + ld r24, [sp, 20] ; Recover r24 + ld r23, [sp, 24] ; Recover r23 + ld r22, [sp, 28] ; Recover r22 + ld r21, [sp, 32] ; Recover r21 + ld r20, [sp, 36] ; Recover r20 + ld r19, [sp, 40] ; Recover r19 + ld r18, [sp, 44] ; Recover r18 + ld r17, [sp, 48] ; Recover r17 + ld r16, [sp, 52] ; Recover r16 + ld r15, [sp, 56] ; Recover r15 + ld r14, [sp, 60] ; Recover r14 + ld r13, [sp, 64] ; Recover r13 + ld r1, [sp, 68] ; Pickup status32 + ld r30, [sp, 72] ; Recover r30 + add sp, sp, 76 ; Recover solicited stack frame + j_s.d [blink] ; Return to thread and restore flags + seti r1 ; Recover STATUS32 +; +__tx_thread_schedule_int_ret: +; + mov r0, 0x2 ; Pretend level 1 interrupt is returning + sr r0, [AUX_IRQ_ACT] ; + + ld r0, [sp, 4] ; Recover LP_START + sr r0, [LP_START] ; Restore LP_START + ld r1, [sp, 8] ; Recover LP_END + sr r1, [LP_END] ; Restore LP_END + ld r2, [sp, 12] ; Recover LP_COUNT + mov LP_COUNT, r2 + ld r0, [sp, 156] ; Pickup saved BTA + sr r0, [BTA] ; Recover BTA + ld blink, [sp, 16] ; Recover blink + ld ilink, [sp, 20] ; Recover ilink + ld fp, [sp, 24] ; Recover fp + ld gp, [sp, 28] ; Recover gp + ld r25, [sp, 32] ; Recover r25 + ld r24, [sp, 36] ; Recover r24 + ld r23, [sp, 40] ; Recover r23 + ld r22, [sp, 44] ; Recover r22 + ld r21, [sp, 48] ; Recover r21 + ld r20, [sp, 52] ; Recover r20 + ld r19, [sp, 56] ; Recover r19 + ld r18, [sp, 60] ; Recover r18 + ld r17, [sp, 64] ; Recover r17 + ld r16, [sp, 68] ; Recover r16 + ld r15, [sp, 72] ; Recover r15 + ld r14, [sp, 76] ; Recover r14 + ld r13, [sp, 80] ; Recover r13 + ld r12, [sp, 84] ; Recover r12 + ld r11, [sp, 88] ; Recover r11 + ld r10, [sp, 92] ; Recover r10 + ld r9, [sp, 96] ; Recover r9 + ld r8, [sp, 100] ; Recover r8 + ld r7, [sp, 104] ; Recover r7 + ld r6, [sp, 108] ; Recover r6 + ld r5, [sp, 112] ; Recover r5 + ld r4, [sp, 116] ; Recover r4 + ld r3, [sp, 120] ; Recover r3 + ld r2, [sp, 124] ; Recover r2 + ld r1, [sp, 128] ; Recover r1 + ld r0, [sp, 132] ; Recover r0 + ld r30, [sp, 136] ; Recover r30 + .ifdef TX_ENABLE_ACC + ld r58, [sp, 140] ; Recover r58 + ld r59, [sp, 144] ; Recover r59 + .endif + add sp, sp, 160 ; Recover interrupt stack frame + rtie ; Return to point of interrupt + +; +;} +; + .end + diff --git a/ports/arc_em/metaware/src/tx_thread_stack_build.s b/ports/arc_em/metaware/src/tx_thread_stack_build.s new file mode 100644 index 00000000..ecda6a4d --- /dev/null +++ b/ports/arc_em/metaware/src/tx_thread_stack_build.s @@ -0,0 +1,205 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + .equ LONG_ALIGN_MASK, 0xFFFFFFFC + .equ INT_ENABLE_BITS, 0x8000001E +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build ARCv2_EM/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build, @function +_tx_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the ARCv2 EM should look like the following after it is built. +; Note that the extension registers are always assigned space here. +; +; Stack Top: 1 Interrupt stack frame type +; LP_START Initial loop start +; LP_END Initial loop end +; LP_COUNT Initial loop count +; blink Initial blink value +; ilink Initial ilink (point of interrupt) +; fp (r27) Initial fp (0) +; gp Initial gp +; r25 Initial r25 +; r24 Initial r24 +; r23 Initial r23 +; r22 Initial r22 +; r21 Initial r21 +; r20 Initial r20 +; r19 Initial r19 +; r18 Initial r18 +; r17 Initial r17 +; r16 Initial r16 +; r15 Initial r15 +; r14 Initial r14 +; r13 Initial r13 +; r12 Initial r12 +; r11 Initial r11 +; r10 Initial r10 +; r9 Initial r9 +; r8 Initial r8 +; r7 Initial r7 +; r6 Initial r6 +; r5 Initial r5 +; r4 Initial r4 +; r3 Initial r3 +; r2 Initial r2 +; r1 Initial r1 +; r0 Initial r0 +; r30 Initial r30 +; r58 Initial r58 +; r59 Initial r59 +; 0 Reserved +; 0 Reserved +; 0 Initial BTA +; 0 Point of Interrupt (thread entry point) +; 0 Initial STATUS32 +; 0 Backtrace +; 0 Backtrace +; 0 Backtrace +; 0 Backtrace +; +; *: these registers will only be saved and restored if flag -Xxmac_d16 is passed to hcac +; +; Stack Bottom: (higher memory address) */ +; + ld r3, [r0, 16] ; Pickup end of stack area + and r3, r3, LONG_ALIGN_MASK ; Ensure long-word alignment + sub r3, r3, 196 ; Allocate an interrupt stack frame (ARCv2 EM) +; +; /* Actually build the stack frame. */ +; + st 1, [r3, 0] ; Store interrupt stack type on the + ; top of the stack + mov r5, 0 ; Build initial clear value + st r5, [r3, 4] ; Store initial LP_START + st r5, [r3, 8] ; Store initial LP_END + st r5, [r3, 12] ; Store initial LP_COUNT + st r5, [r3, 16] ; Store initial blink + st r1, [r3, 20] ; Store initial ilink + st r5, [r3, 24] ; Store initial fp (0 for backtrace) + st gp, [r3, 28] ; Store current gp + st r5, [r3, 32] ; Store initial r25 + st r5, [r3, 36] ; Store initial r24 + st r5, [r3, 40] ; Store initial r23 + st r5, [r3, 44] ; Store initial r22 + st r5, [r3, 48] ; Store initial r21 + st r5, [r3, 52] ; Store initial r20 + st r5, [r3, 56] ; Store initial r19 + st r5, [r3, 60] ; Store initial r18 + st r5, [r3, 64] ; Store initial r17 + st r5, [r3, 68] ; Store initial r16 + st r5, [r3, 72] ; Store initial r15 + st r5, [r3, 76] ; Store initial r14 + st r5, [r3, 80] ; Store initial r13 + st r5, [r3, 84] ; Store initial r12 + st r5, [r3, 88] ; Store initial r11 + st r5, [r3, 92] ; Store initial r10 + st r5, [r3, 96] ; Store initial r9 + st r5, [r3, 100] ; Store initial r8 + st r5, [r3, 104] ; Store initial r7 + st r5, [r3, 108] ; Store initial r6 + st r5, [r3, 112] ; Store initial r5 + st r5, [r3, 116] ; Store initial r4 + st r5, [r3, 120] ; Store initial r3 + st r5, [r3, 124] ; Store initial r2 + st r5, [r3, 128] ; Store initial r1 + st r5, [r3, 132] ; Store initial r0 + st r5, [r3, 136] ; Store initial r30 + st r5, [r3, 140] ; Store initial r58 + st r5, [r3, 144] ; Store initial r59 + st r5, [r3, 148] ; Reserved + st r5, [r3, 152] ; Reserved + st r5, [r3, 156] ; Store initial BTA + st r1, [r3, 160] ; Store initial point of entry + lr r6, [status32] ; Pickup STATUS32 + or r6, r6, INT_ENABLE_BITS ; Make sure interrupts are enabled + st r6, [r3, 164] ; Store initial STATUS32 + st r5, [r3, 168] ; Backtrace 0 + st r5, [r3, 172] ; Backtrace 0 + st r5, [r3, 176] ; Backtrace 0 + st r5, [r3, 180] ; Backtrace 0 +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r3; +; + j_s.d [blink] ; Return to caller + st r3, [r0, 8] ; Save stack pointer in thread's + ; control block +;} + .end + + diff --git a/ports/arc_em/metaware/src/tx_thread_system_return.s b/ports/arc_em/metaware/src/tx_thread_system_return.s new file mode 100644 index 00000000..61120d49 --- /dev/null +++ b/ports/arc_em/metaware/src/tx_thread_system_return.s @@ -0,0 +1,169 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; + .equ KSTACK_TOP, 0x264 + .equ KSTACK_BASE, 0x265 + .equ STATUS32_SC, 0x4000 +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return ARCv2_EM/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + .global _tx_thread_system_return + .type _tx_thread_system_return, @function +_tx_thread_system_return: +; +; /* Save minimal context on the stack. */ +; +; /* Lockout interrupts. */ +; + clri r2 ; Disable interrupts + sub sp, sp, 76 ; Allocate a solicited stack frame + mov r3, 0 ; Build a solicited stack type + st r3, [sp, 0] ; Store stack type on the top + st blink, [sp, 4] ; Save return address and flags + st fp, [sp, 8] ; Save fp + st r26, [sp, 12] ; Save r26 + st r25, [sp, 16] ; Save r25 + st r24, [sp, 20] ; Save r24 + st r23, [sp, 24] ; Save r23 + st r22, [sp, 28] ; Save r22 + st r21, [sp, 32] ; Save r21 + st r20, [sp, 36] ; Save r20 + st r19, [sp, 40] ; Save r19 + st r18, [sp, 44] ; Save r18 + st r17, [sp, 48] ; Save r17 + st r16, [sp, 52] ; Save r16 + st r15, [sp, 56] ; Save r15 + st r14, [sp, 60] ; Save r14 + st r13, [sp, 64] ; Save r13 + st r2, [sp, 68] ; Save status32 + st r30, [sp, 72] ; Save r30 +; + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + bl.d _tx_execution_thread_exit ; Call the thread exit function + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space + mov r3, 0 ; Build clear value + .endif +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread ptr + st sp, [r0, 8] ; Save thread's stack pointer + ld r5, [gp, _tx_timer_time_slice@sda] ; Pickup current time-slice + + .ifdef TX_ENABLE_HW_STACK_CHECKING + lr r2, [status32] ; Pickup current STATUS32 + and r2, r2, ~STATUS32_SC ; Clear the hardware stack checking enable bit (SC) + kflag r2 ; Disable hardware stack checking + mov r1, _tx_system_stack_top_address ; Pickup top of system stack (lowest memory address) + sr r1, [KSTACK_TOP] ; Setup KSTACK_TOP + mov r1, _tx_system_stack_base_address ; Pickup base of system stack (highest memory address) + sr r1, [KSTACK_BASE] ; Setup KSTACK_BASE + .endif + + ld sp, [gp, _tx_thread_system_stack_ptr@sda] ; Switch to system stack + + .ifdef TX_ENABLE_HW_STACK_CHECKING + or r2, r2, STATUS32_SC ; Or in hardware stack checking enable bit (SC) + kflag r2 ; Enable hardware stack checking + .endif +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + breq r5, 0, __tx_thread_dont_save_ts ; If not, skip save processing +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + st r3, [gp, _tx_timer_time_slice@sda] ; Clear time-slice variable + st r5, [r0, 24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts: +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + b.d _tx_thread_schedule ; Return to scheduler.. + st r3, [gp, _tx_thread_current_ptr@sda] ; ..clearing current thread pointer +; +;} + .end + + diff --git a/ports/arc_em/metaware/src/tx_timer_interrupt.s b/ports/arc_em/metaware/src/tx_timer_interrupt.s new file mode 100644 index 00000000..4c5e241c --- /dev/null +++ b/ports/arc_em/metaware/src/tx_timer_interrupt.s @@ -0,0 +1,238 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt ARCv2_EM/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Process timer expiration */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_context_save Save interrupt context */ +;/* _tx_thread_context_restore Restore interrupt context */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt, @function +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed the interrupt stack frame has +; already been allocated and registers r0, r1, and r2 have already been saved +; at offsets 0, 4, and 8 respectively. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + clri ; Lockout interrupts + ld r0, [gp,_tx_timer_system_clock@sda] ; Pickup current system clock + ld r2, [gp, _tx_timer_time_slice@sda] ; Pickup current time-slice + add r0, r0, 1 ; Increment the system clock + st r0, [gp,_tx_timer_system_clock@sda] ; Store system clock back in memory + +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + mov r1, 0 ; Clear expiration flag + breq r2, 0, __tx_timer_no_time_slice ; If zero, no time-slice is active +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + sub r2, r2, 1 ; Decrement time-slice + st r2, [gp, _tx_timer_time_slice@sda] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + brne r2, 0, __tx_timer_no_time_slice ; If non-zero, skip over expiration +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + mov r1, 1 ; Set register flag + st r1, [gp, _tx_timer_expired_time_slice@sda] ; Set the time-slice expired flag + +; +; } +; +__tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + ld r0, [gp, _tx_timer_current_ptr@sda] ; Pickup current timer pointer + ld r2, [r0, 0] ; Pickup examine actual list entry + breq r2, 0, __tx_timer_no_timer ; + ; If NULL, no timer has expired, just move to the next entry +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + mov r1, 1 ; Build expiration value + b.d __tx_timer_done ; Skip moving the timer pointer + st r1, [gp, _tx_timer_expired@sda] ; Set the expired value +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ld r2, [gp, _tx_timer_list_end@sda] ; Pickup end of list + add r0, r0, 4 ; Move to next timer entry +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + st r0, [gp, _tx_timer_current_ptr@sda] ; Store the current timer + brne r0, r2, __tx_timer_skip_wrap ; If not equal, don't wrap the list +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + ld r2, [gp, _tx_timer_list_start@sda] ; Pickup start of timer list + st r2, [gp, _tx_timer_current_ptr@sda] ; Set current timer to the start +; +__tx_timer_skip_wrap: +; +; } +; +__tx_timer_done: +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + breq r1, 0, __tx_timer_nothing_expired ; If 0, nothing has expired +; +__tx_something_expired: +; + ld r0, [sp, 0] ; Recover r0 + ld r1, [sp, 4] ; Recover r1 + ld r2, [sp, 8] ; Recover r2 + st blink, [sp, 16] ; Save blink + bl _tx_thread_context_save ; Save interrupted context +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + ld r2, [gp, _tx_timer_expired@sda] ; Pickup timer expired flag + ld r4, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable + breq r2, 0, __tx_timer_dont_activate ; If not set, skip expiration processing +; +; /* Process the timer expiration. */ +; /* _tx_timer_expiration_process(); */ + bl.d _tx_timer_expiration_process ; Call the timer expiration handling routine + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space +; +; } +__tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + ld r2, [gp, _tx_timer_expired_time_slice@sda] ; Pickup expired time-slice flag + breq r2, 0, __tx_timer_not_ts_expiration ; If not set, skip time-slice +; +; /* Time slice interrupted thread. */ +; /* _tx_thread_time_slice(); */ + + bl.d _tx_thread_time_slice ; Call time-slice processing + sub sp, sp, 16 ; ..allocating some stack space + add sp, sp, 16 ; Recover stack space +; +; } +; +__tx_timer_not_ts_expiration: +; + st 0, [gp, _tx_timer_expired_time_slice@sda] + b _tx_thread_context_restore ; Go restore interrupt context.. + ; ..clearing time-slice expired flag + ; Note that we don't return from + ; this function. +; +; } +; +__tx_timer_nothing_expired: +; + ld r0, [sp, 0] ; Recover r0 + ld r1, [sp, 4] ; Recover r1 + ld r2, [sp, 8] ; Recover r2 + add sp, sp, 160 ; Recover interrupt stack frame + rtie ; Return to point of interrupt +; +;} + .end + diff --git a/ports/arc_hs/metaware/example_build/.metadata/.lock b/ports/arc_hs/metaware/example_build/.metadata/.lock new file mode 100644 index 00000000..e69de29b diff --git a/ports/arc_hs/metaware/example_build/.metadata/.log b/ports/arc_hs/metaware/example_build/.metadata/.log new file mode 100644 index 00000000..7c78bb33 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.log @@ -0,0 +1,2291 @@ +!SESSION 2015-09-28 16:00:20.788 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 -data C:\temp1663\tesp + +!ENTRY org.eclipse.cdt.core 1 0 2015-09-28 16:03:16.758 +!MESSAGE Indexed 'tx' (0 sources, 0 headers) in 0.003 sec: 0 declarations; 0 references; 0 unresolved inclusions; 0 syntax errors; 0 unresolved names (0%) + +!ENTRY org.eclipse.cdt.core 1 0 2015-09-28 16:08:56.869 +!MESSAGE Indexed 'sample_threadx' (0 sources, 0 headers) in 0 sec: 0 declarations; 0 references; 0 unresolved inclusions; 0 syntax errors; 0 unresolved names (0%) + +!ENTRY org.eclipse.debug.core 4 5012 2015-09-28 16:13:02.280 +!MESSAGE org.xml.sax.SAXParseException; lineNumber: 438; columnNumber: 1; Content is not allowed in trailing section. occurred while reading launch configuration file: C:\temp1663\tesp\.metadata\.plugins\org.eclipse.debug.core\.launches\sample_threadx Debug.launch. +!STACK 0 +org.xml.sax.SAXParseException; lineNumber: 438; columnNumber: 1; Content is not allowed in trailing section. + at com.sun.org.apache.xerces.internal.util.ErrorHandlerWrapper.createSAXParseException(ErrorHandlerWrapper.java:203) + at com.sun.org.apache.xerces.internal.util.ErrorHandlerWrapper.fatalError(ErrorHandlerWrapper.java:177) + at com.sun.org.apache.xerces.internal.impl.XMLErrorReporter.reportError(XMLErrorReporter.java:441) + at com.sun.org.apache.xerces.internal.impl.XMLErrorReporter.reportError(XMLErrorReporter.java:368) + at com.sun.org.apache.xerces.internal.impl.XMLScanner.reportFatalError(XMLScanner.java:1436) + at com.sun.org.apache.xerces.internal.impl.XMLDocumentScannerImpl$TrailingMiscDriver.next(XMLDocumentScannerImpl.java:1433) + at com.sun.org.apache.xerces.internal.impl.XMLDocumentScannerImpl.next(XMLDocumentScannerImpl.java:606) + at com.sun.org.apache.xerces.internal.impl.XMLDocumentFragmentScannerImpl.scanDocument(XMLDocumentFragmentScannerImpl.java:510) + at com.sun.org.apache.xerces.internal.parsers.XML11Configuration.parse(XML11Configuration.java:848) + at com.sun.org.apache.xerces.internal.parsers.XML11Configuration.parse(XML11Configuration.java:777) + at com.sun.org.apache.xerces.internal.parsers.XMLParser.parse(XMLParser.java:141) + at com.sun.org.apache.xerces.internal.parsers.DOMParser.parse(DOMParser.java:243) + at com.sun.org.apache.xerces.internal.jaxp.DocumentBuilderImpl.parse(DocumentBuilderImpl.java:348) + at org.eclipse.debug.internal.core.LaunchManager.createInfoFromXML(LaunchManager.java:954) + at org.eclipse.debug.internal.core.LaunchManager.getInfo(LaunchManager.java:1372) + at org.eclipse.debug.internal.core.LaunchConfiguration.getInfo(LaunchConfiguration.java:470) + at org.eclipse.debug.internal.core.LaunchConfiguration.getAttribute(LaunchConfiguration.java:416) + at org.eclipse.debug.ui.RefreshTab.getRefreshScope(RefreshTab.java:431) + at org.eclipse.cdt.launch.AbstractCLaunchDelegate$CLaunch.refresh(AbstractCLaunchDelegate.java:109) + at org.eclipse.cdt.launch.internal.ui.LaunchUIPlugin.launchesTerminated(LaunchUIPlugin.java:225) + at org.eclipse.debug.internal.core.LaunchManager$LaunchesNotifier.run(LaunchManager.java:318) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.internal.core.LaunchManager$LaunchesNotifier.notify(LaunchManager.java:270) + at org.eclipse.debug.internal.core.LaunchManager.fireUpdate(LaunchManager.java:1055) + at org.eclipse.debug.core.Launch.fireTerminate(Launch.java:405) + at org.eclipse.debug.core.Launch.handleDebugEvents(Launch.java:577) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.run(DebugPlugin.java:1151) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.dispatch(DebugPlugin.java:1187) + at org.eclipse.debug.core.DebugPlugin$EventDispatchJob.run(DebugPlugin.java:431) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.e4.ui.workbench.swt 4 2 2015-09-28 16:13:17.470 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.e4.ui.workbench.swt". +!STACK 0 +org.eclipse.e4.core.di.InjectionException: org.eclipse.swt.SWTException: Widget is disposed + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:62) + at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:888) + at org.eclipse.e4.core.internal.di.InjectorImpl.disposed(InjectorImpl.java:390) + at org.eclipse.e4.core.internal.di.Requestor.disposed(Requestor.java:143) + at org.eclipse.e4.core.internal.contexts.ContextObjectSupplier$ContextInjectionListener.update(ContextObjectSupplier.java:76) + at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.update(TrackableComputationExt.java:107) + at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.handleInvalid(TrackableComputationExt.java:70) + at org.eclipse.e4.core.internal.contexts.EclipseContext.dispose(EclipseContext.java:175) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.clearContext(PartRenderingEngine.java:974) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeRemoveGui(PartRenderingEngine.java:954) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$3(PartRenderingEngine.java:862) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$8.run(PartRenderingEngine.java:857) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.removeGui(PartRenderingEngine.java:841) + at org.eclipse.ui.internal.WorkbenchWindow.hardClose(WorkbenchWindow.java:1937) + at org.eclipse.ui.internal.WorkbenchWindow.busyClose(WorkbenchWindow.java:1560) + at org.eclipse.ui.internal.WorkbenchWindow.access$15(WorkbenchWindow.java:1527) + at org.eclipse.ui.internal.WorkbenchWindow$10.run(WorkbenchWindow.java:1592) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70) + at org.eclipse.ui.internal.WorkbenchWindow.close(WorkbenchWindow.java:1589) + at org.eclipse.ui.internal.Workbench$14.run(Workbench.java:1155) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench.busyClose(Workbench.java:1137) + at org.eclipse.ui.internal.Workbench.access$21(Workbench.java:1079) + at org.eclipse.ui.internal.Workbench$19.run(Workbench.java:1410) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70) + at org.eclipse.ui.internal.Workbench.close(Workbench.java:1407) + at org.eclipse.ui.internal.Workbench.restart(Workbench.java:2677) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction.restart(OpenWorkspaceAction.java:282) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction.run(OpenWorkspaceAction.java:264) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction$OpenDialogAction.run(OpenWorkspaceAction.java:70) + at org.eclipse.jface.action.Action.runWithEvent(Action.java:519) + at org.eclipse.jface.action.ActionContributionItem.handleWidgetSelection(ActionContributionItem.java:595) + at org.eclipse.jface.action.ActionContributionItem.access$2(ActionContributionItem.java:511) + at org.eclipse.jface.action.ActionContributionItem$5.handleEvent(ActionContributionItem.java:420) + at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84) + at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1085) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1070) + at org.eclipse.swt.widgets.Widget.notifyListeners(Widget.java:782) + at org.eclipse.jface.action.ActionContributionItem$9.handleEvent(ActionContributionItem.java:1293) + at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84) + at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061) + at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172) + at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603) + at org.eclipse.equinox.launcher.Main.run(Main.java:1465) +Caused by: org.eclipse.swt.SWTException: Widget is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Widget.error(Widget.java:476) + at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348) + at org.eclipse.swt.widgets.Shell.getSize(Shell.java:1092) + at org.eclipse.ui.internal.quickaccess.SearchField.storeDialog(SearchField.java:580) + at org.eclipse.ui.internal.quickaccess.SearchField.dispose(SearchField.java:557) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55) + ... 67 more + +!ENTRY org.eclipse.e4.ui.workbench 4 0 2015-09-28 16:13:17.470 +!MESSAGE Exception occurred while unrendering: org.eclipse.e4.ui.model.application.ui.basic.impl.TrimmedWindowImpl@74d228 (elementId: IDEWindow, tags: [topLevel], contributorURI: platform:/plugin/org.eclipse.ui.workbench) (widget: null, renderer: null, toBeRendered: true, onTop: false, visible: true, containerData: null, accessibilityPhrase: null) (label: %trimmedwindow.label.eclipseSDK, iconURI: null, tooltip: null, context: null, variables: [], x: 369, y: 52, width: 1024, height: 775) +!STACK 0 +org.eclipse.e4.core.di.InjectionException: org.eclipse.swt.SWTException: Widget is disposed + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:62) + at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:888) + at org.eclipse.e4.core.internal.di.InjectorImpl.disposed(InjectorImpl.java:390) + at org.eclipse.e4.core.internal.di.Requestor.disposed(Requestor.java:143) + at org.eclipse.e4.core.internal.contexts.ContextObjectSupplier$ContextInjectionListener.update(ContextObjectSupplier.java:76) + at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.update(TrackableComputationExt.java:107) + at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.handleInvalid(TrackableComputationExt.java:70) + at org.eclipse.e4.core.internal.contexts.EclipseContext.dispose(EclipseContext.java:175) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.clearContext(PartRenderingEngine.java:974) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeRemoveGui(PartRenderingEngine.java:954) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$3(PartRenderingEngine.java:862) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$8.run(PartRenderingEngine.java:857) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.removeGui(PartRenderingEngine.java:841) + at org.eclipse.ui.internal.WorkbenchWindow.hardClose(WorkbenchWindow.java:1937) + at org.eclipse.ui.internal.WorkbenchWindow.busyClose(WorkbenchWindow.java:1560) + at org.eclipse.ui.internal.WorkbenchWindow.access$15(WorkbenchWindow.java:1527) + at org.eclipse.ui.internal.WorkbenchWindow$10.run(WorkbenchWindow.java:1592) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70) + at org.eclipse.ui.internal.WorkbenchWindow.close(WorkbenchWindow.java:1589) + at org.eclipse.ui.internal.Workbench$14.run(Workbench.java:1155) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench.busyClose(Workbench.java:1137) + at org.eclipse.ui.internal.Workbench.access$21(Workbench.java:1079) + at org.eclipse.ui.internal.Workbench$19.run(Workbench.java:1410) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70) + at org.eclipse.ui.internal.Workbench.close(Workbench.java:1407) + at org.eclipse.ui.internal.Workbench.restart(Workbench.java:2677) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction.restart(OpenWorkspaceAction.java:282) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction.run(OpenWorkspaceAction.java:264) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction$OpenDialogAction.run(OpenWorkspaceAction.java:70) + at org.eclipse.jface.action.Action.runWithEvent(Action.java:519) + at org.eclipse.jface.action.ActionContributionItem.handleWidgetSelection(ActionContributionItem.java:595) + at org.eclipse.jface.action.ActionContributionItem.access$2(ActionContributionItem.java:511) + at org.eclipse.jface.action.ActionContributionItem$5.handleEvent(ActionContributionItem.java:420) + at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84) + at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1085) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1070) + at org.eclipse.swt.widgets.Widget.notifyListeners(Widget.java:782) + at org.eclipse.jface.action.ActionContributionItem$9.handleEvent(ActionContributionItem.java:1293) + at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84) + at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061) + at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172) + at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603) + at org.eclipse.equinox.launcher.Main.run(Main.java:1465) +Caused by: org.eclipse.swt.SWTException: Widget is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Widget.error(Widget.java:476) + at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348) + at org.eclipse.swt.widgets.Shell.getSize(Shell.java:1092) + at org.eclipse.ui.internal.quickaccess.SearchField.storeDialog(SearchField.java:580) + at org.eclipse.ui.internal.quickaccess.SearchField.dispose(SearchField.java:557) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55) + ... 67 more +!SESSION 2015-10-02 16:29:55.871 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1b69ccb, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1b69ccb, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@9f0360, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@9f0360, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@112b637, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@112b637, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ea0b48, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ea0b48, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1eb8e9a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1eb8e9a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15d1204, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15d1204, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@184a296, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@184a296, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1ea4b65, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1ea4b65, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@f6839c, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@f6839c, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) + +!ENTRY org.eclipse.debug.core 4 2 2015-10-02 17:42:00.298 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.debug.core". +!STACK 0 +org.eclipse.swt.SWTException: Device is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Display.error(Display.java:1258) + at org.eclipse.swt.widgets.Display.getThread(Display.java:2602) + at org.eclipse.debug.internal.ui.stringsubstitution.SelectedResourceManager.getActiveWindow(SelectedResourceManager.java:239) + at org.eclipse.debug.ui.DebugUITools.getDebugContext(DebugUITools.java:229) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.update(RemoveAllGlobalsActionDelegate.java:99) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.handleDebugEvents(RemoveAllGlobalsActionDelegate.java:131) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.run(DebugPlugin.java:1151) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.dispatch(DebugPlugin.java:1187) + at org.eclipse.debug.core.DebugPlugin$EventDispatchJob.run(DebugPlugin.java:431) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.debug.core 4 125 2015-10-02 17:42:00.298 +!MESSAGE An exception occurred while dispatching debug events. +!STACK 0 +org.eclipse.swt.SWTException: Device is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Display.error(Display.java:1258) + at org.eclipse.swt.widgets.Display.getThread(Display.java:2602) + at org.eclipse.debug.internal.ui.stringsubstitution.SelectedResourceManager.getActiveWindow(SelectedResourceManager.java:239) + at org.eclipse.debug.ui.DebugUITools.getDebugContext(DebugUITools.java:229) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.update(RemoveAllGlobalsActionDelegate.java:99) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.handleDebugEvents(RemoveAllGlobalsActionDelegate.java:131) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.run(DebugPlugin.java:1151) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.dispatch(DebugPlugin.java:1187) + at org.eclipse.debug.core.DebugPlugin$EventDispatchJob.run(DebugPlugin.java:431) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SESSION 2015-10-05 13:04:20.828 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3cdce6, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3cdce6, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15453dc, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15453dc, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@a8e1f7, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@a8e1f7, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@7edea3, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@7edea3, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ffee26, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ffee26, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1149b96, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1149b96, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@7c6dda, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@7c6dda, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3d31b0, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3d31b0, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@12a690f, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@12a690f, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SESSION 2015-10-06 09:33:14.510 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@8206aa, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@8206aa, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@e8535e, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@e8535e, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1f4742b, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1f4742b, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1b3de87, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1b3de87, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@132284d, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@132284d, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15ae856, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15ae856, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15b83fa, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15b83fa, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3b3ab0, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3b3ab0, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@55167a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@55167a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SESSION 2015-10-08 14:32:52.274 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 -data C:\temp1663\working_base_hs + +!ENTRY org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d85a18, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d85a18, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1575bad, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1575bad, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1e89472, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1e89472, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1965d0c, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1965d0c, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@182d1bc, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@182d1bc, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@8d7592, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@8d7592, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@19737f5, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@19737f5, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@aa73f6, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@aa73f6, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15e422e, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15e422e, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) + +!ENTRY org.eclipse.cdt.debug.core 4 1000 2015-10-08 15:24:49.427 +!MESSAGE Internal error logged from CDI Debug: +!STACK 0 +org.eclipse.cdt.debug.core.cdi.TargetInvocationException: Can't load "C:\temp1663\working_base_hs\sample_threadx\Debug\sample_threadx.elf"[] + at com.arc.cdt.debug.seecode.internal.core.cdi.Target.loadProgram(Target.java:1289) + at com.arc.cdt.debug.seecode.internal.core.cdi.Target.confirmLoaded(Target.java:945) + at com.arc.cdt.debug.seecode.internal.core.cdi.Target.getRegisterGroups(Target.java:1816) + at org.eclipse.cdt.debug.internal.core.CRegisterManager.initialize(CRegisterManager.java:138) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.getRegisterManager(CDebugTarget.java:1808) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.initializeRegisters(CDebugTarget.java:425) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.initialize(CDebugTarget.java:319) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.(CDebugTarget.java:301) + at org.eclipse.cdt.debug.core.CDIDebugModel$1.run(CDIDebugModel.java:133) + at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2313) + at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2295) + at org.eclipse.cdt.debug.core.CDIDebugModel.newDebugTarget(CDIDebugModel.java:138) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launchLocalDebugSession(LocalCDILaunchDelegate.java:213) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launchDebugger(LocalCDILaunchDelegate.java:136) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launch(LocalCDILaunchDelegate.java:80) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:885) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:739) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1039) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1256) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.cdt.debug.core 4 1000 2015-10-08 15:25:33.059 +!MESSAGE Internal error logged from CDI Debug: +!STACK 0 +org.eclipse.cdt.debug.core.cdi.TargetInvocationException: Can't load "C:\temp1663\working_base_hs\sample_threadx\Debug\sample_threadx.elf"[] + at com.arc.cdt.debug.seecode.internal.core.cdi.Target.loadProgram(Target.java:1289) + at com.arc.cdt.debug.seecode.internal.core.cdi.Target.confirmLoaded(Target.java:945) + at com.arc.cdt.debug.seecode.internal.core.cdi.Target.getRegisterGroups(Target.java:1816) + at org.eclipse.cdt.debug.internal.core.CRegisterManager.initialize(CRegisterManager.java:138) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.getRegisterManager(CDebugTarget.java:1808) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.initializeRegisters(CDebugTarget.java:425) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.initialize(CDebugTarget.java:319) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.(CDebugTarget.java:301) + at org.eclipse.cdt.debug.core.CDIDebugModel$1.run(CDIDebugModel.java:133) + at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2313) + at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2295) + at org.eclipse.cdt.debug.core.CDIDebugModel.newDebugTarget(CDIDebugModel.java:138) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launchLocalDebugSession(LocalCDILaunchDelegate.java:213) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launchDebugger(LocalCDILaunchDelegate.java:136) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launch(LocalCDILaunchDelegate.java:80) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:885) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:739) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1039) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1256) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SESSION 2015-10-09 15:41:22.142 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.debug.ui 4 2 2015-10-09 16:32:33.850 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.debug.ui". +!STACK 0 +java.lang.NullPointerException + at org.eclipse.debug.core.sourcelookup.containers.CompositeSourceContainer.getSourceContainers(CompositeSourceContainer.java:134) + at org.eclipse.cdt.debug.internal.core.sourcelookup.SourceUtils.getCompilationPath(SourceUtils.java:205) + at org.eclipse.cdt.debug.internal.core.sourcelookup.CSourceLookupDirector.getCompilationPath(CSourceLookupDirector.java:181) + at org.eclipse.cdt.debug.internal.ui.actions.RunToLineAdapter.convertPath(RunToLineAdapter.java:171) + at org.eclipse.cdt.debug.internal.ui.actions.RunToLineAdapter.canRunToLine(RunToLineAdapter.java:141) + at org.eclipse.debug.internal.ui.actions.RetargetRunToLineAction.canPerformAction(RetargetRunToLineAction.java:95) + at org.eclipse.debug.internal.ui.actions.RetargetAction.isTargetEnabled(RetargetAction.java:245) + at org.eclipse.debug.internal.ui.actions.RetargetRunToLineAction$DebugContextListener.contextActivated(RetargetRunToLineAction.java:51) + at org.eclipse.debug.internal.ui.actions.RetargetRunToLineAction$DebugContextListener.debugContextChanged(RetargetRunToLineAction.java:57) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService$1.run(DebugWindowContextService.java:223) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService.notify(DebugWindowContextService.java:220) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService.notify(DebugWindowContextService.java:195) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService.debugContextChanged(DebugWindowContextService.java:436) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider$1.run(AbstractDebugContextProvider.java:83) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider.fire(AbstractDebugContextProvider.java:80) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$ContextProviderProxy.debugContextChanged(LaunchView.java:518) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider$1.run(AbstractDebugContextProvider.java:83) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider.fire(AbstractDebugContextProvider.java:80) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$TreeViewerContextProvider.possibleChange(LaunchView.java:404) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$TreeViewerContextProvider$Visitor.visit(LaunchView.java:326) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.doAccept(ModelDelta.java:401) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.doAccept(ModelDelta.java:404) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.doAccept(ModelDelta.java:404) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.accept(ModelDelta.java:397) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$TreeViewerContextProvider.modelChanged(LaunchView.java:434) + at org.eclipse.debug.internal.ui.viewers.model.TreeModelContentProvider.doModelChanged(TreeModelContentProvider.java:427) + at org.eclipse.debug.internal.ui.viewers.model.TreeModelContentProvider.access$0(TreeModelContentProvider.java:413) + at org.eclipse.debug.internal.ui.viewers.model.TreeModelContentProvider$2.run(TreeModelContentProvider.java:401) + at org.eclipse.swt.widgets.RunnableLock.run(RunnableLock.java:35) + at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:136) + at org.eclipse.swt.widgets.Display.runAsyncMessages(Display.java:4147) + at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3764) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603) + at org.eclipse.equinox.launcher.Main.run(Main.java:1465) + +!ENTRY org.eclipse.debug.ui 4 120 2015-10-09 16:32:33.881 +!MESSAGE Error logged from Debug UI: +!STACK 0 +java.lang.NullPointerException + at org.eclipse.debug.core.sourcelookup.containers.CompositeSourceContainer.getSourceContainers(CompositeSourceContainer.java:134) + at org.eclipse.cdt.debug.internal.core.sourcelookup.SourceUtils.getCompilationPath(SourceUtils.java:205) + at org.eclipse.cdt.debug.internal.core.sourcelookup.CSourceLookupDirector.getCompilationPath(CSourceLookupDirector.java:181) + at org.eclipse.cdt.debug.internal.ui.actions.RunToLineAdapter.convertPath(RunToLineAdapter.java:171) + at org.eclipse.cdt.debug.internal.ui.actions.RunToLineAdapter.canRunToLine(RunToLineAdapter.java:141) + at org.eclipse.debug.internal.ui.actions.RetargetRunToLineAction.canPerformAction(RetargetRunToLineAction.java:95) + at org.eclipse.debug.internal.ui.actions.RetargetAction.isTargetEnabled(RetargetAction.java:245) + at org.eclipse.debug.internal.ui.actions.RetargetRunToLineAction$DebugContextListener.contextActivated(RetargetRunToLineAction.java:51) + at org.eclipse.debug.internal.ui.actions.RetargetRunToLineAction$DebugContextListener.debugContextChanged(RetargetRunToLineAction.java:57) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService$1.run(DebugWindowContextService.java:223) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService.notify(DebugWindowContextService.java:220) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService.notify(DebugWindowContextService.java:195) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService.debugContextChanged(DebugWindowContextService.java:436) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider$1.run(AbstractDebugContextProvider.java:83) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider.fire(AbstractDebugContextProvider.java:80) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$ContextProviderProxy.debugContextChanged(LaunchView.java:518) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider$1.run(AbstractDebugContextProvider.java:83) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider.fire(AbstractDebugContextProvider.java:80) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$TreeViewerContextProvider.possibleChange(LaunchView.java:404) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$TreeViewerContextProvider$Visitor.visit(LaunchView.java:326) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.doAccept(ModelDelta.java:401) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.doAccept(ModelDelta.java:404) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.doAccept(ModelDelta.java:404) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.accept(ModelDelta.java:397) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$TreeViewerContextProvider.modelChanged(LaunchView.java:434) + at org.eclipse.debug.internal.ui.viewers.model.TreeModelContentProvider.doModelChanged(TreeModelContentProvider.java:427) + at org.eclipse.debug.internal.ui.viewers.model.TreeModelContentProvider.access$0(TreeModelContentProvider.java:413) + at org.eclipse.debug.internal.ui.viewers.model.TreeModelContentProvider$2.run(TreeModelContentProvider.java:401) + at org.eclipse.swt.widgets.RunnableLock.run(RunnableLock.java:35) + at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:136) + at org.eclipse.swt.widgets.Display.runAsyncMessages(Display.java:4147) + at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3764) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603) + at org.eclipse.equinox.launcher.Main.run(Main.java:1465) + +!ENTRY org.eclipse.debug.core 4 2 2015-10-09 17:50:18.411 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.debug.core". +!STACK 0 +org.eclipse.swt.SWTException: Device is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Display.error(Display.java:1258) + at org.eclipse.swt.widgets.Display.getThread(Display.java:2602) + at org.eclipse.debug.internal.ui.stringsubstitution.SelectedResourceManager.getActiveWindow(SelectedResourceManager.java:239) + at org.eclipse.debug.ui.DebugUITools.getDebugContext(DebugUITools.java:229) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.update(RemoveAllGlobalsActionDelegate.java:99) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.handleDebugEvents(RemoveAllGlobalsActionDelegate.java:131) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.run(DebugPlugin.java:1151) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.dispatch(DebugPlugin.java:1187) + at org.eclipse.debug.core.DebugPlugin$EventDispatchJob.run(DebugPlugin.java:431) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.debug.core 4 125 2015-10-09 17:50:18.411 +!MESSAGE An exception occurred while dispatching debug events. +!STACK 0 +org.eclipse.swt.SWTException: Device is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Display.error(Display.java:1258) + at org.eclipse.swt.widgets.Display.getThread(Display.java:2602) + at org.eclipse.debug.internal.ui.stringsubstitution.SelectedResourceManager.getActiveWindow(SelectedResourceManager.java:239) + at org.eclipse.debug.ui.DebugUITools.getDebugContext(DebugUITools.java:229) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.update(RemoveAllGlobalsActionDelegate.java:99) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.handleDebugEvents(RemoveAllGlobalsActionDelegate.java:131) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.run(DebugPlugin.java:1151) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.dispatch(DebugPlugin.java:1187) + at org.eclipse.debug.core.DebugPlugin$EventDispatchJob.run(DebugPlugin.java:431) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SESSION 2015-10-12 11:12:05.433 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1a045bd, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1a045bd, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@fada78, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@fada78, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@cc9674, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@cc9674, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@120387e, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@120387e, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d8100a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d8100a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d925b3, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d925b3, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d46f2a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d46f2a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@754906, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@754906, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@db5482, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@db5482, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) + +!ENTRY org.eclipse.debug.core 4 2 2015-10-12 13:31:22.583 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.debug.core". +!STACK 0 +org.eclipse.swt.SWTException: Device is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Display.error(Display.java:1258) + at org.eclipse.swt.widgets.Display.getThread(Display.java:2602) + at org.eclipse.debug.internal.ui.stringsubstitution.SelectedResourceManager.getActiveWindow(SelectedResourceManager.java:239) + at org.eclipse.debug.ui.DebugUITools.getDebugContext(DebugUITools.java:229) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.update(RemoveAllGlobalsActionDelegate.java:99) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.handleDebugEvents(RemoveAllGlobalsActionDelegate.java:131) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.run(DebugPlugin.java:1151) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.dispatch(DebugPlugin.java:1187) + at org.eclipse.debug.core.DebugPlugin$EventDispatchJob.run(DebugPlugin.java:431) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.debug.core 4 125 2015-10-12 13:31:22.583 +!MESSAGE An exception occurred while dispatching debug events. +!STACK 0 +org.eclipse.swt.SWTException: Device is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Display.error(Display.java:1258) + at org.eclipse.swt.widgets.Display.getThread(Display.java:2602) + at org.eclipse.debug.internal.ui.stringsubstitution.SelectedResourceManager.getActiveWindow(SelectedResourceManager.java:239) + at org.eclipse.debug.ui.DebugUITools.getDebugContext(DebugUITools.java:229) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.update(RemoveAllGlobalsActionDelegate.java:99) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.handleDebugEvents(RemoveAllGlobalsActionDelegate.java:131) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.run(DebugPlugin.java:1151) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.dispatch(DebugPlugin.java:1187) + at org.eclipse.debug.core.DebugPlugin$EventDispatchJob.run(DebugPlugin.java:431) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SESSION 2015-10-12 13:33:52.888 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@906078, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@906078, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1d5c7f6, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1d5c7f6, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@124ab90, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@124ab90, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ef1934, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ef1934, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@11522f1, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@11522f1, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@5eba52, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@5eba52, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@34f8e2, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@34f8e2, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@2a7429, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@2a7429, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@a8c837, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@a8c837, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SESSION 2020-06-17 17:46:26.532 ----------------------------------------------- +eclipse.buildId=unknown +java.fullversion=1.8.0_212-b03 +JRE 1.8.0 Windows 8 amd64-64-Bit Compressed References 20190417_339 (JIT enabled, AOT enabled) +OpenJ9 - bad1d4d06 +OMR - 4a4278e6 +JCL - 5590c4f818 based on jdk8u212-b03 +BootLoader constants: OS=win32, ARCH=x86_64, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86_64 + +!ENTRY org.eclipse.e4.ui.workbench 2 0 2020-06-17 17:46:42.545 +!MESSAGE Could not run processor +!STACK 0 +org.eclipse.e4.core.di.InjectionException: java.lang.NullPointerException + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:65) + at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:282) + at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:259) + at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107) + at org.eclipse.e4.ui.internal.workbench.ModelAssembler.runProcessor(ModelAssembler.java:335) + at org.eclipse.e4.ui.internal.workbench.ModelAssembler.runProcessors(ModelAssembler.java:297) + at org.eclipse.e4.ui.internal.workbench.ModelAssembler.processModel(ModelAssembler.java:98) + at org.eclipse.e4.ui.internal.workbench.ResourceHandler.loadMostRecentModel(ResourceHandler.java:197) + at org.eclipse.e4.ui.internal.workbench.swt.E4Application.loadApplicationModel(E4Application.java:377) + at org.eclipse.e4.ui.internal.workbench.swt.E4Application.createE4Workbench(E4Application.java:252) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:632) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:336) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:610) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:148) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:138) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:388) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:243) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:498) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:673) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:610) + at org.eclipse.equinox.launcher.Main.run(Main.java:1519) +Caused by: java.lang.NullPointerException + at org.eclipse.cdt.launchbar.ui.internal.LaunchBarInjector.injectLaunchBar(LaunchBarInjector.java:109) + at org.eclipse.cdt.launchbar.ui.internal.LaunchBarInjector.injectIntoAll(LaunchBarInjector.java:84) + at org.eclipse.cdt.launchbar.ui.internal.LaunchBarInjector.execute(LaunchBarInjector.java:46) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:498) + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55) + ... 26 more + +!ENTRY org.eclipse.osgi 4 0 2020-06-17 17:46:47.752 +!MESSAGE An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). +!STACK 0 +org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +Root exception: +java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.eclipse.ui.workbench 4 2 2020-06-17 17:46:47.787 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.ui.workbench". +!STACK 1 +org.eclipse.core.runtime.CoreException: Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.throwException(RegistryStrategyOSGI.java:194) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:176) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + ... 10 more +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-17 17:46:47.787 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-17 17:46:47.787 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more + +!ENTRY org.eclipse.ui 4 0 2020-06-17 17:46:47.806 +!MESSAGE Unable to execute early startup code for the org.eclipse.ui.IStartup extension contributed by the 'com.synopsys.cdt.cnn.tools.ui' plug-in. +!STACK 1 +org.eclipse.core.runtime.CoreException: Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.throwException(RegistryStrategyOSGI.java:194) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:176) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + ... 10 more +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-17 17:46:47.807 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more + +!ENTRY org.eclipse.e4.ui.workbench 2 0 2020-06-17 17:46:48.173 +!MESSAGE Removing part descriptor with the 'org.eclipse.cdt.debug.ui.DisassemblyView' id and the 'Disassembly' description. Points to the invalid 'bundleclass://org.eclipse.ui.workbench/org.eclipse.ui.internal.e4.compatibility.CompatibilityView' class. +!SESSION 2020-06-17 17:47:25.082 ----------------------------------------------- +eclipse.buildId=unknown +java.fullversion=1.8.0_212-b03 +JRE 1.8.0 Windows 8 amd64-64-Bit Compressed References 20190417_339 (JIT enabled, AOT enabled) +OpenJ9 - bad1d4d06 +OMR - 4a4278e6 +JCL - 5590c4f818 based on jdk8u212-b03 +BootLoader constants: OS=win32, ARCH=x86_64, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86_64 + +!ENTRY org.eclipse.core.resources 4 567 2020-06-17 17:47:30.736 +!MESSAGE Workspace restored, but some problems occurred. +!SUBENTRY 1 org.eclipse.core.resources 4 567 2020-06-17 17:47:30.736 +!MESSAGE Could not read metadata for 'demo_threadx'. +!STACK 1 +org.eclipse.core.internal.resources.ResourceException: The project description file (.project) for 'demo_threadx' is missing. This file contains important information about the project. The project will not function properly until this file is restored. + at org.eclipse.core.internal.localstore.FileSystemResourceManager.read(FileSystemResourceManager.java:907) + at org.eclipse.core.internal.resources.SaveManager.restoreMetaInfo(SaveManager.java:904) + at org.eclipse.core.internal.resources.SaveManager.restoreMetaInfo(SaveManager.java:884) + at org.eclipse.core.internal.resources.SaveManager.restore(SaveManager.java:735) + at org.eclipse.core.internal.resources.SaveManager.startup(SaveManager.java:1587) + at org.eclipse.core.internal.resources.Workspace.startup(Workspace.java:2399) + at org.eclipse.core.internal.resources.Workspace.open(Workspace.java:2156) + at org.eclipse.core.resources.ResourcesPlugin.start(ResourcesPlugin.java:464) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.sources.SingleSourcePackage.loadClass(SingleSourcePackage.java:36) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:419) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:139) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:388) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:243) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:498) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:673) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:610) + at org.eclipse.equinox.launcher.Main.run(Main.java:1519) +!SUBENTRY 2 org.eclipse.core.resources 4 567 2020-06-17 17:47:30.738 +!MESSAGE The project description file (.project) for 'demo_threadx' is missing. This file contains important information about the project. The project will not function properly until this file is restored. + +!ENTRY org.eclipse.osgi 4 0 2020-06-17 17:47:33.892 +!MESSAGE An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). +!STACK 0 +org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +Root exception: +java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.eclipse.ui.workbench 4 2 2020-06-17 17:47:33.922 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.ui.workbench". +!STACK 1 +org.eclipse.core.runtime.CoreException: Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.throwException(RegistryStrategyOSGI.java:194) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:176) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + ... 10 more +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-17 17:47:33.922 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-17 17:47:33.922 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more + +!ENTRY org.eclipse.ui 4 0 2020-06-17 17:47:33.942 +!MESSAGE Unable to execute early startup code for the org.eclipse.ui.IStartup extension contributed by the 'com.synopsys.cdt.cnn.tools.ui' plug-in. +!STACK 1 +org.eclipse.core.runtime.CoreException: Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.throwException(RegistryStrategyOSGI.java:194) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:176) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + ... 10 more +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-17 17:47:33.942 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more + +!ENTRY org.eclipse.e4.ui.workbench 2 0 2020-06-17 17:47:34.252 +!MESSAGE Removing part descriptor with the 'org.eclipse.cdt.debug.ui.DisassemblyView' id and the 'Disassembly' description. Points to the invalid 'bundleclass://org.eclipse.ui.workbench/org.eclipse.ui.internal.e4.compatibility.CompatibilityView' class. + +!ENTRY org.eclipse.cdt.core 1 0 2020-06-17 17:47:51.232 +!MESSAGE Indexed 'sample_threadx' (1 sources, 0 headers) in 0.18 sec: 60 declarations; 165 references; 1 unresolved inclusions; 0 syntax errors; 105 unresolved names (32%) diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/.log b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/.log new file mode 100644 index 00000000..8cdd960c --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/.log @@ -0,0 +1,16 @@ +*** SESSION Sep 28, 2015 16:00:26.42 ------------------------------------------- +*** SESSION Sep 28, 2015 16:24:47.48 ------------------------------------------- +*** SESSION Sep 28, 2015 16:43:36.06 ------------------------------------------- +*** SESSION Oct 01, 2015 14:52:43.41 ------------------------------------------- +*** SESSION Oct 01, 2015 16:50:35.31 ------------------------------------------- +*** SESSION Oct 02, 2015 16:30:04.53 ------------------------------------------- +*** SESSION Oct 05, 2015 13:04:34.94 ------------------------------------------- +*** SESSION Oct 05, 2015 17:02:39.29 ------------------------------------------- +*** SESSION Oct 06, 2015 09:33:29.71 ------------------------------------------- +*** SESSION Oct 08, 2015 14:32:58.71 ------------------------------------------- +*** SESSION Oct 09, 2015 15:42:00.42 ------------------------------------------- +*** SESSION Oct 12, 2015 11:13:19.78 ------------------------------------------- +*** SESSION Oct 12, 2015 13:34:17.27 ------------------------------------------- +*** SESSION Oct 12, 2015 13:59:21.03 ------------------------------------------- +*** SESSION Jun 17, 2020 17:46:46.45 ------------------------------------------- +*** SESSION Jun 17, 2020 17:47:32.95 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literal 0 HcmV?d00001 diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-sample_threadx.prefs b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-sample_threadx.prefs new file mode 100644 index 00000000..9c00dc4e --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-sample_threadx.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-tx.prefs b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-tx.prefs new file mode 100644 index 00000000..9c00dc4e --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-tx.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 00000000..9531fc3c --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.cDebug.default_source_containers=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n +org.eclipse.cdt.debug.corecDebug.Disassembly.instructionStepOn=true diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs new file mode 100644 index 00000000..c03690a1 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs @@ -0,0 +1,7 @@ +columnOrderKeyEXE=0,1,2,3,4,5 +columnOrderKeySF=0,1,2,3,4,5 +columnSortDirectionKeyEXE=128 +columnSortDirectionKeySF=128 +eclipse.preferences.version=1 +visibleColumnsKeyEXE=1,1,1,0,0,0 +visibleColumnsKeySF=1,1,0,0,0,0 diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.launchbar.core.prefs b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.launchbar.core.prefs new file mode 100644 index 00000000..c002721a --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.launchbar.core.prefs @@ -0,0 +1,5 @@ +activeConfigDesc=sample_threadx Debug.org.eclipse.cdt.launchbar.core.descriptor.default +configDescList=[sample_threadx Debug.org.eclipse.cdt.launchbar.core.descriptor.default] +sample_threadx\ Debug.org.eclipse.cdt.launchbar.core.descriptor.default/activeLaunchMode=debug +sample_threadx\ Debug.org.eclipse.cdt.launchbar.core.descriptor.default/activeLaunchTarget=org.eclipse.cdt.launchbar.core.target.local +eclipse.preferences.version=1 diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 00000000..db7c08cf --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,5 @@ +eclipse.preferences.version=1 +properties/sample_threadx.com.arc.cdt.toolchain.arc.av2hs.exeProject.1700533761/com.arc.cdt.toolchain.av2hs.exeDebugConfig.585788724=av2hs.exe.debug.exeCompilerDebug.1743110770\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.exeDebugConfig.585788724\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.asmDebugExe.1483523628\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.exeToolChainDebug.1358823635\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.arc.archiver.886382681\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.exeLinkerDebug.672502322\=rebuildState\\\=false\\r\\n\r\n +properties/sample_threadx.com.arc.cdt.toolchain.arc.av2hs.exeProject.1700533761/com.arc.cdt.toolchain.av2hs.exeReleaseConfig.2024992869=com.arc.cdt.toolchain.av2hs.exelinkerRelease.934772409\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.asmReleaseExe.813382130\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.exeReleaseToolChain.202924782\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.arc.archiver.990750758\=rebuildState\\\=true\\r\\n\r\narc.cdt.toolchain.av2hs.exeCompilerRelease.1463268267\=rebuildState\\\=true\\r\\n\r\n +properties/tx.com.arc.cdt.toolchain.arc.av2hs.libProject.1128858457/com.arc.cdt.toolchain.av2hs.libDebugConfig.2063275274=com.arc.cdt.toolchain.av2hs.ArDebug.1591578035\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.arc.Linker.41800372\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libDebugAsm.1626881776\=rebuildState\\\=false\\r\\n\r\nav2hs.lib.debug.libCompiler.2145942775\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libDebugConfig.2063275274\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libDebugToolChain.1385404397\=rebuildState\\\=false\\r\\n\r\n +properties/tx.com.arc.cdt.toolchain.arc.av2hs.libProject.1128858457/com.arc.cdt.toolchain.av2hs.libReleaseConfig.1202427021=com.arc.cdt.toolchain.av2hs.libCompilerRelease.1920721386\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libReleaseAsm.1207600374\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.ArRelease.217147730\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libReleaseToolChain.1456119623\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.arc.Linker.1382145468\=rebuildState\\\=true\\r\\n\r\n diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs new file mode 100644 index 00000000..5e2da66d --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs @@ -0,0 +1,4 @@ +eclipse.preferences.version=1 +spelling_locale_initialized=true +useAnnotationsPrefPage=true +useQuickDiffPrefPage=true diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..dffc6b51 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +version=1 diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs new file mode 100644 index 00000000..47236716 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs @@ -0,0 +1,5 @@ +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.attachLaunchType=org.eclipse.cdt.dsf.gdb.launch.attachCLaunch,debug,; +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.localCLaunch=org.eclipse.cdt.cdi.launch.localCLaunch,run,; +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.postmortemLaunchType=org.eclipse.cdt.dsf.gdb.launch.coreCLaunch,debug,; +eclipse.preferences.version=1 +prefWatchExpressions=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs new file mode 100644 index 00000000..f2a15ec2 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs @@ -0,0 +1,10 @@ +eclipse.preferences.version=1 +org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=\r\n\r\n +org.eclipse.debug.ui.user_view_bindings=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n +pref_state_memento.org.eclipse.debug.ui.BreakpointView=\r\n\r\n\r\n\r\n\r\n +pref_state_memento.org.eclipse.debug.ui.DebugVieworg.eclipse.debug.ui.DebugView=\r\n +pref_state_memento.org.eclipse.debug.ui.ExpressionView=\r\n\r\n\r\n\r\n\r\n +pref_state_memento.org.eclipse.debug.ui.ModuleView=\r\n +pref_state_memento.org.eclipse.debug.ui.VariableView=\r\n +preferredDetailPanes=DefaultDetailPane\:DefaultDetailPane| +preferredTargets=org.eclipse.cdt.debug.ui.toggleCBreakpointTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget|org.eclipse.cdt.debug.ui.toggleCBreakpointTarget,org.eclipse.cdt.debug.ui.toggleCDynamicPrintfTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget| diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs new file mode 100644 index 00000000..61f3bb8b --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +overviewRuler_migration=migrated_3.1 diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs new file mode 100644 index 00000000..76ce67b9 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs @@ -0,0 +1,5 @@ +PROBLEMS_FILTERS_MIGRATE=true +eclipse.preferences.version=1 +platformState=1590536495337 +quickStart=true +tipsAndTricks=true diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs new file mode 100644 index 00000000..08076f23 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +showIntro=false diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs new file mode 100644 index 00000000..60e7be60 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs @@ -0,0 +1,4 @@ +//org.eclipse.ui.commands/state/org.eclipse.ui.navigator.resources.nested.changeProjectPresentation/org.eclipse.ui.commands.radioState=false +UIActivities.com.arc.cdt.debug.seecode.ui.activity1=true +UIActivities.org.eclipse.cdt.debug.cdigdbActivity=true +eclipse.preferences.version=1 diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.debug.core/.launches/sample_threadx Debug.launch b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.debug.core/.launches/sample_threadx Debug.launch new file mode 100644 index 00000000..d8303802 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.debug.core/.launches/sample_threadx Debug.launch @@ -0,0 +1,457 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml new file mode 100644 index 00000000..c13038c2 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml @@ -0,0 +1,11 @@ + +
+
+ + + + + + +
+
diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml new file mode 100644 index 00000000..c22cfeb5 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.e4.ui.workbench.swt/dialog_settings.xml b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.e4.ui.workbench.swt/dialog_settings.xml new file mode 100644 index 00000000..2e57abac --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.e4.ui.workbench.swt/dialog_settings.xml @@ -0,0 +1,14 @@ + +
+
+ + + + + + + + + +
+
diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi new file mode 100644 index 00000000..5a2b8bd8 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi @@ -0,0 +1,1828 @@ + + + + activeSchemeId:org.eclipse.ui.defaultAcceleratorConfiguration + ModelMigrationProcessor.001 + + + + + + + + topLevel + shellMaximized + + + + + persp.actionSet:com.arc.eclipse.aboutMWDebugger + persp.actionSet:com.arc.cdt.toolchain.PDFs + persp.actionSet:org.eclipse.ui.cheatsheets.actionSet + persp.actionSet:org.eclipse.search.searchActionSet + persp.actionSet:org.eclipse.ui.edit.text.actionSet.annotationNavigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.navigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.convertLineDelimitersTo + persp.actionSet:org.eclipse.ui.externaltools.ExternalToolsSet + persp.actionSet:org.eclipse.ui.actionSet.keyBindings + persp.actionSet:org.eclipse.ui.actionSet.openFiles + persp.actionSet:org.eclipse.cdt.ui.SearchActionSet + persp.actionSet:org.eclipse.cdt.ui.CElementCreationActionSet + persp.actionSet:org.eclipse.ui.NavigateActionSet + persp.viewSC:org.eclipse.ui.console.ConsoleView + persp.viewSC:org.eclipse.search.ui.views.SearchView + persp.viewSC:org.eclipse.ui.views.ContentOutline + persp.viewSC:org.eclipse.ui.views.ProblemView + persp.viewSC:org.eclipse.cdt.ui.CView + persp.viewSC:org.eclipse.ui.views.ResourceNavigator + persp.viewSC:org.eclipse.ui.views.PropertySheet + persp.viewSC:org.eclipse.ui.views.TaskList + persp.newWizSC:org.eclipse.cdt.ui.wizards.ConvertToMakeWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewMakeFromExisting + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewCWizard1 + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewCWizard2 + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewSourceFolderCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewFolderCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewSourceFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewHeaderFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewClassCreationWizard + persp.viewSC:org.eclipse.pde.runtime.LogView + persp.showIn:org.eclipse.cdt.codan.internal.ui.views.ProblemDetails + persp.viewSC:org.eclipse.cdt.codan.internal.ui.views.ProblemDetails + persp.actionSet:org.eclipse.debug.ui.breakpointActionSet + persp.viewSC:org.eclipse.cdt.make.ui.views.MakeView + persp.actionSet:org.eclipse.cdt.make.ui.makeTargetActionSet + persp.perspSC:org.eclipse.debug.ui.DebugPerspective + persp.perspSC:org.eclipse.team.ui.TeamSynchronizingPerspective + persp.actionSet:org.eclipse.debug.ui.launchActionSet + persp.actionSet:org.eclipse.cdt.ui.buildConfigActionSet + persp.actionSet:org.eclipse.cdt.ui.NavigationActionSet + persp.actionSet:org.eclipse.cdt.ui.OpenActionSet + persp.actionSet:org.eclipse.cdt.ui.CodingActionSet + persp.actionSet:org.eclipse.ui.edit.text.actionSet.presentation + persp.showIn:org.eclipse.cdt.ui.includeBrowser + persp.showIn:org.eclipse.cdt.ui.CView + persp.showIn:org.eclipse.ui.navigator.ProjectExplorer + persp.viewSC:org.eclipse.ui.navigator.ProjectExplorer + persp.viewSC:org.eclipse.cdt.ui.includeBrowser + persp.actionSet:org.eclipse.debug.ui.debugActionSet + + + newtablook + active + + + + + + + + + + newtablook + + + + + + + + newtablook + Debug + + + + + + + + + + + + persp.actionSet:com.arc.eclipse.aboutMWDebugger + persp.actionSet:com.arc.cdt.toolchain.PDFs + persp.actionSet:org.eclipse.ui.cheatsheets.actionSet + persp.actionSet:org.eclipse.search.searchActionSet + persp.actionSet:org.eclipse.ui.edit.text.actionSet.annotationNavigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.navigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.convertLineDelimitersTo + persp.actionSet:org.eclipse.ui.externaltools.ExternalToolsSet + persp.actionSet:org.eclipse.ui.actionSet.keyBindings + persp.actionSet:org.eclipse.ui.actionSet.openFiles + persp.actionSet:org.eclipse.debug.ui.launchActionSet + persp.actionSet:org.eclipse.debug.ui.debugActionSet + persp.viewSC:org.eclipse.debug.ui.DebugView + persp.viewSC:org.eclipse.debug.ui.VariableView + persp.viewSC:org.eclipse.debug.ui.BreakpointView + persp.viewSC:org.eclipse.debug.ui.ExpressionView + persp.viewSC:org.eclipse.ui.views.ContentOutline + persp.viewSC:org.eclipse.ui.console.ConsoleView + persp.viewSC:org.eclipse.ui.views.TaskList + persp.viewSC:com.arc.cdt.debug.seecode.ui.views.disasm + persp.viewSC:com.arc.cdt.debug.seecode.ui.command + persp.viewSC:com.arc.cdt.debug.seecode.ui.views.memsearch + persp.viewSC:com.arc.cdt.seecode.errorlog + persp.viewSC:org.eclipse.cdt.debug.ui.SignalsView + persp.viewSC:org.eclipse.cdt.debug.ui.RegisterView + persp.viewSC:org.eclipse.debug.ui.ModuleView + persp.viewSC:org.eclipse.debug.ui.MemoryView + persp.viewSC:org.eclipse.ui.views.ProblemView + persp.viewSC:org.eclipse.cdt.debug.ui.executablesView + persp.actionSet:org.eclipse.cdt.debug.ui.debugActionSet + persp.actionSet:org.eclipse.cdt.debug.ui.debugActionSetExt + persp.viewSC:org.eclipse.cdt.dsf.gdb.ui.tracecontrol.view + persp.viewSC:org.eclipse.cdt.dsf.debug.ui.disassembly.view + persp.perspSC:org.eclipse.cdt.ui.CPerspective + persp.viewSC:org.eclipse.cdt.visualizer.view + persp.actionSet:org.eclipse.ui.NavigateActionSet + persp.actionSet:org.eclipse.debug.ui.breakpointActionSet + persp.viewSC:org.eclipse.pde.runtime.LogView + persp.actionSet:org.eclipse.cdt.debug.ui.debugActionSetExt2 + + + + + + newtablook + org.eclipse.e4.primaryNavigationStack + + + + + newtablook + + + + + newtablook + + + + + + + + + + + + + + + + + + + + + + + newtablook + + + + + + newtablook + org.eclipse.e4.secondaryNavigationStack + + + + + + + + + Standalone + + + + + + + newtablook + org.eclipse.e4.secondaryDataStack + + + + + + + + + + + newtablook + + + + + + + + + + + + + + + + + View + categoryTag:Help + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Help + + + + newtablook + org.eclipse.e4.primaryDataStack + EditorStack + + + + + View + categoryTag:General + active + activeOnClose + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:&C/C++ + + + View + categoryTag:General + + + View + categoryTag:General + + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:General + + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:General + + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Make + + + View + categoryTag:Terminal + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Debug + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + toolbarSeparator + + + + Draggable + + + + toolbarSeparator + + + + Draggable + + + Draggable + + + Draggable + + + Draggable + + + toolbarSeparator + + + + Draggable + + + + toolbarSeparator + + + + toolbarSeparator + + + + Draggable + + + stretch + SHOW_RESTORE_MENU + + + Draggable + HIDEABLE + SHOW_RESTORE_MENU + + + + + stretch + + + Draggable + + + Draggable + + + + + TrimStack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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categoryTag:&C/C++ + + + + + View + categoryTag:&C/C++ + + + + + View + categoryTag:&C/C++ + + + + + View + categoryTag:&C/C++ + + + + + View + categoryTag:&C/C++ + + + + + View + categoryTag:General + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Help + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:Team + + + + + View + categoryTag:Team + + + + + View + categoryTag:Terminal + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:Help + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + glue + move_after:PerspectiveSpacer + SHOW_RESTORE_MENU + + + move_after:Spacer Glue + HIDEABLE + SHOW_RESTORE_MENU + + + glue + move_after:SearchField + SHOW_RESTORE_MENU + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.history @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.index b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.index new file mode 100644 index 00000000..e3eb0266 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.index @@ -0,0 +1 @@ +1592441257832 Delete resource 'demo_threadx' diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml new file mode 100644 index 00000000..aa267842 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml @@ -0,0 +1,7 @@ + +
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diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml new file mode 100644 index 00000000..50f1edb3 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml @@ -0,0 +1,5 @@ + +
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diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml new file mode 100644 index 00000000..9c5013b7 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml @@ -0,0 +1,22 @@ + +
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diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml new file mode 100644 index 00000000..c8e48664 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml @@ -0,0 +1,30 @@ + +
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diff --git a/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml new file mode 100644 index 00000000..373b8d71 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/ports/arc_hs/metaware/example_build/.metadata/version.ini b/ports/arc_hs/metaware/example_build/.metadata/version.ini new file mode 100644 index 00000000..044ab217 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/.metadata/version.ini @@ -0,0 +1,3 @@ +#Wed Jun 17 17:47:30 PDT 2020 +org.eclipse.core.runtime=2 +org.eclipse.platform=4.6.3.v20170301-0400 diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/.bp.args b/ports/arc_hs/metaware/example_build/sample_threadx/.bp.args new file mode 100644 index 00000000..020c9022 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/sample_threadx/.bp.args @@ -0,0 +1,3 @@ +location=_tx_thread_system_return +condition_enabled=0 +cond= diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/.bp.properties b/ports/arc_hs/metaware/example_build/sample_threadx/.bp.properties new file mode 100644 index 00000000..8e467ac1 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/sample_threadx/.bp.properties @@ -0,0 +1,13 @@ +#Debugger engine properties +#Fri Oct 02 16:50:37 PDT 2015 +ARG_ACTION={"location\=_tx_thread_system_return" "condition_enabled\=0" "cond\=" } +docTitle=break_dialog +LOCATION=_tx_thread_system_return +on_push=bpsaved +TYPE=either +TEMPORARY=false +OK_ON_ENTER=1 +OK_ENABLED=1 +ReadingXML=false +THREAD_SPECIFIC=false +CONDITION_ENABLED=false diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/.cproject b/ports/arc_hs/metaware/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..e782f2f6 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/sample_threadx/.cproject @@ -0,0 +1,143 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/.project b/ports/arc_hs/metaware/example_build/sample_threadx/.project new file mode 100644 index 00000000..a1b15572 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/sample_threadx/.project @@ -0,0 +1,26 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/.settings/language.settings.xml b/ports/arc_hs/metaware/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..c63b0e46 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.c b/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..5a03f35c --- /dev/null +++ b/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,370 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); + + return(0); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.cmd b/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.cmd new file mode 100644 index 00000000..6c2dfb8a --- /dev/null +++ b/ports/arc_hs/metaware/example_build/sample_threadx/sample_threadx.cmd @@ -0,0 +1,54 @@ +// +// This is the linker script example (SRV3-style). +// (c) Synopsys, 2013 +// +// + +//number of exceptions and interrupts +NUMBER_OF_EXCEPTIONS = 16;//it is fixed (16) +NUMBER_OF_INTERRUPTS = 5;//depends on HW configuration + +//define Interrupt Vector Table size +IVT_SIZE_ITEMS = (NUMBER_OF_EXCEPTIONS + NUMBER_OF_INTERRUPTS);//the total IVT size (in "items") +IVT_SIZE_BYTES = IVT_SIZE_ITEMS * 4;//in bytes + +//define ICCM and DCCM locations +MEMORY { + + ICCM: ORIGIN = 0x00000000, LENGTH = 128K + DCCM: ORIGIN = 0x80000000, LENGTH = 128K +} + +//define sections and groups +SECTIONS { + GROUP: { + .ivt (TEXT) : # Interrupt table + { + ___ivt1 = .; + * (.ivt) + ___ivt2 = .; + // Make the IVT at least IVT_SIZE_BYTES + . += (___ivt2 - ___ivt1 < IVT_SIZE_BYTES) ? (IVT_SIZE_BYTES - (___ivt2 - ___ivt1)) : 0; + } + .ivh (TEXT) : // Interrupt handlers + + //TEXT sections + .text? : { *('.text$crt*') } + * (TEXT): {} + //Literals + * (LIT): {} + } > ICCM + + GROUP: { + //data sections + .sdata?: {} + .sbss?: {} + *(DATA): {} + *(BSS): {} + //stack + .stack ALIGN(4) SIZE(DEFINED _STACKSIZE?_STACKSIZE:4096): {} + //heap (empty) + .heap? ALIGN(4) SIZE(DEFINED _HEAPSIZE?_HEAPSIZE:0): {} + .free_memory: {} + } > DCCM + } diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/tx_initialize_low_level.s b/ports/arc_hs/metaware/example_build/sample_threadx/tx_initialize_low_level.s new file mode 100644 index 00000000..da17b687 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/sample_threadx/tx_initialize_low_level.s @@ -0,0 +1,328 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + .equ IRQ_SELECT, 0x40B + +; +; +; /* Define section for placement after all linker allocated RAM memory. This +; is used to calculate the first free address that is passed to +; tx_appication_define, soley for the ThreadX application's use. */ +; + .section ".free_memory","aw" + .align 4 + .global _tx_first_free_address +_tx_first_free_address: + .space 4 +; +; + .text +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + .global _tx_initialize_low_level + .type _tx_initialize_low_level, @function +_tx_initialize_low_level: + +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; + st sp, [gp, _tx_thread_system_stack_ptr@sda] ; Save system stack pointer +; +; +; /* Pickup the first available memory address. */ +; + mov r0, _tx_first_free_address ; Pickup first free memory address +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) _end; +; + st r0, [gp, _tx_initialize_unused_memory@sda] +; +; +; /* Setup Timer 0 for periodic interrupts at interrupt vector 16. */ +; + mov r0, 0 ; Disable additional ISR reg saving/restoring + sr r0, [AUX_IRQ_CTRL] ; + + mov r0, 16 ; Select timer 0 + sr r0, [IRQ_SELECT] ; + mov r0, 15 ; Set timer 0 to priority 15 + sr r0, [IRQ_PRIORITY] ; + mov r0, 1 ; Enable this interrupt + sr r0, [IRQ_ENABLE] ; + mov r0, 0x10000 ; Setup timer period + sr r0, [LIMIT0] ; + mov r0, 0 ; Clear timer 0 current count + sr r0, [COUNT0] ; + mov r0, 3 ; Enable timer 0 + sr r0, [CONTROL0] ; + + .ifdef TX_TIMER_1_SETUP + mov r0, 17 ; Select timer 1 + sr r0, [IRQ_SELECT] ; + mov r0, 0 ; Set timer 1 to priority 0 + sr r0, [IRQ_PRIORITY] ; + mov r0, 1 ; Enable this interrupt + sr r0, [IRQ_ENABLE] ; + mov r0, 0x10020 ; Setup timer period + sr r0, [LIMIT1] ; + mov r0, 0 ; Clear timer 0 current count + sr r0, [COUNT1] ; + mov r0, 3 ; Enable timer 0 + sr r0, [CONTROL1] ; + .endif +; +; /* Done, return to caller. */ +; + j_s.d [blink] ; Return to caller + nop +;} +; +; +; /* Define default vector table entries. */ +; + .global _tx_memory_error +_tx_memory_error: + flag 1 + nop + nop + nop + b _tx_memory_error + + .global _tx_instruction_error +_tx_instruction_error: + flag 1 + nop + nop + nop + b _tx_instruction_error + + .global _tx_ev_machine_check +_tx_ev_machine_check: + flag 1 + nop + nop + nop + b _tx_ev_machine_check + + .global _tx_ev_tblmiss_inst +_tx_ev_tblmiss_inst: + flag 1 + nop + nop + nop + b _tx_ev_tblmiss_inst + + .global _tx_ev_tblmiss_data +_tx_ev_tblmiss_data: + flag 1 + nop + nop + nop + b _tx_ev_tblmiss_data + + .global _tx_ev_protection_viol +_tx_ev_protection_viol: + flag 1 + nop + nop + nop + b _tx_ev_protection_viol + + .global _tx_ev_privilege_viol +_tx_ev_privilege_viol: + flag 1 + nop + nop + nop + b _tx_ev_privilege_viol + + .global _tx_ev_software_int +_tx_ev_software_int: + flag 1 + nop + nop + nop + b _tx_ev_software_int + + .global _tx_ev_trap +_tx_ev_trap: + flag 1 + nop + nop + nop + b _tx_ev_trap + + .global _tx_ev_extension +_tx_ev_extension: + flag 1 + nop + nop + nop + b _tx_ev_extension + + .global _tx_ev_divide_by_zero +_tx_ev_divide_by_zero: + flag 1 + nop + nop + nop + b _tx_ev_divide_by_zero + + .global _tx_ev_dc_error +_tx_ev_dc_error: + flag 1 + nop + nop + nop + b _tx_ev_dc_error + + .global _tx_ev_maligned +_tx_ev_maligned: + flag 1 + nop + nop + nop + b _tx_ev_maligned + + .global _tx_unsued_0 +_tx_unsued_0: + flag 1 + nop + nop + nop + b _tx_unsued_0 + + .global _tx_unused_1 +_tx_unused_1: + flag 1 + nop + nop + nop + b _tx_unused_1 + + .global _tx_timer_0 +_tx_timer_0: +; +; /* By default, setup Timer 0 as the ThreadX timer interrupt. */ +; + sub sp, sp, 160 ; Allocate an interrupt stack frame + st r0, [sp, 0] ; Save r0 + st r1, [sp, 4] ; Save r1 + st r2, [sp, 8] ; Save r2 + mov r0, 3 + sr r0, [CONTROL0] + + b _tx_timer_interrupt ; Jump to generic ThreadX timer interrupt + ; handler +; flag 1 +; nop +; nop +; nop +; b _tx_timer_0 + + .global _tx_timer_1 +_tx_timer_1: + flag 1 + nop + nop + nop + b _tx_timer_1 + +; bl _tx_thread_context_fast_save +; mov r0, 3 +; sr r0, [CONTROL1] +; +; /* Fast ISR processing goes here. Interrupts must not be re-enabled +; in the fast interrupt mode. Also note that multiple register banks +; are available and the fast interrupt processing always maps to +; register bank 1. */ +; +; b _tx_thread_context_fast_restore + + .global _tx_undefined_0 +_tx_undefined_0: + flag 1 + nop + nop + nop + b _tx_undefined_0 + + .global _tx_undefined_1 +_tx_undefined_1: + flag 1 + nop + nop + nop + b _tx_undefined_1 + + .global _tx_undefined_2 +_tx_undefined_2: + flag 1 + nop + nop + nop + b _tx_undefined_2 + + .end diff --git a/ports/arc_hs/metaware/example_build/sample_threadx/vectors.s b/ports/arc_hs/metaware/example_build/sample_threadx/vectors.s new file mode 100644 index 00000000..c6cbc893 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/sample_threadx/vectors.s @@ -0,0 +1,29 @@ + +.file "vectors.s" +.section .ivt,text +;; This directive forces this section to stay resident even if stripped out by the -zpurgetext linker option +.sectflag .ivt,include + +;// handler's name type number name offset in IVT (hex/dec) +.long _start ; exception 0 program entry point offset 0x0 0 +.long _tx_memory_error ; exception 1 memory_error offset 0x4 4 +.long _tx_instruction_error ; exception 2 instruction_error offset 0x8 8 +.long _tx_ev_machine_check ; exception 3 EV_MachineCheck offset 0xC 12 +.long _tx_ev_tblmiss_inst ; exception 4 EV_TLBMissI offset 0x10 16 +.long _tx_ev_tblmiss_data ; exception 5 EV_TLBMissD offset 0x14 20 +.long _tx_ev_protection_viol ; exception 6 EV_ProtV offset 0x18 24 +.long _tx_ev_privilege_viol ; exception 7 EV_PrivilegeV offset 0x1C 28 +.long _tx_ev_software_int ; exception 8 EV_SWI offset 0x20 32 +.long _tx_ev_trap ; exception 9 EV_Trap offset 0x24 36 +.long _tx_ev_extension ; exception 10 EV_Extension offset 0x28 40 +.long _tx_ev_divide_by_zero ; exception 11 EV_DivZero offset 0x2C 44 +.long _tx_ev_dc_error ; exception 12 EV_DCError offset 0x30 48 +.long _tx_ev_maligned ; exception 13 EV_Maligned offset 0x34 52 +.long _tx_unsued_0 ; exception 14 unused offset 0x38 56 +.long _tx_unused_1 ; exception 15 unused offset 0x3C 60 +.long _tx_timer_0 ; IRQ 16 Timer 0 offset 0x40 64 +.long _tx_timer_1 ; IRQ 17 Timer 1 offset 0x44 68 +.long _tx_undefined_0 ; IRQ 18 offset 0x48 72 +.long _tx_undefined_1 ; IRQ 19 offset 0x4C 76 +.long _tx_undefined_2 ; IRQ 20 offset 0x50 80 + diff --git a/ports/arc_hs/metaware/example_build/tx/.cproject b/ports/arc_hs/metaware/example_build/tx/.cproject new file mode 100644 index 00000000..18edc3d5 --- /dev/null +++ b/ports/arc_hs/metaware/example_build/tx/.cproject @@ -0,0 +1,136 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/arc_hs/metaware/example_build/tx/.project b/ports/arc_hs/metaware/example_build/tx/.project new file mode 100644 index 00000000..863ca5cb --- /dev/null +++ b/ports/arc_hs/metaware/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/arc_hs/metaware/example_build/tx/.settings/language.settings.xml b/ports/arc_hs/metaware/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..e071d37e --- /dev/null +++ b/ports/arc_hs/metaware/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/arc_hs/metaware/inc/tx_port.h b/ports/arc_hs/metaware/inc/tx_port.h new file mode 100644 index 00000000..b531615c --- /dev/null +++ b/ports/arc_hs/metaware/inc/tx_port.h @@ -0,0 +1,338 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARC_HS/MetaWare */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Remove volatile for ThreadX source on the ARC. This is because the ARC + compiler generates different non-cache r/w access when using volatile + that is different from the assembly language access of the same + global variables in ThreadX. */ + +#ifdef TX_SOURCE_CODE +#define volatile +#else +#ifdef NX_SOURCE_CODE +#define volatile +#else +#ifdef FX_SOURCE_CODE +#define volatile +#else +#ifdef UX_SOURCE_CODE +#define volatile +#endif +#endif +#endif +#endif + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 800 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 2048 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARC HS port. */ + +#define TX_INT_ENABLE 0x0000001F /* Enable all interrupts */ +#define TX_INT_DISABLE_MASK 0x00000000 /* Disable all interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 VOID *__mw_threadx_tls; \ + int __mw_errnum; \ + VOID (*__mw_thread_exit)(struct TX_THREAD_STRUCT *); +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#if __HIGHC__ + +/* The MetaWare thread safe C/C++ runtime library needs space to + store thread specific information. In addition, a function pointer + is also supplied so that certain thread-specific resources may be + released upon thread termination and/or thread completion. */ + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + thread_ptr -> __mw_threadx_tls = 0; \ + thread_ptr -> __mw_errnum = 0; \ + thread_ptr -> __mw_thread_exit = TX_NULL; +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) \ + if (thread_ptr -> __mw_thread_exit) \ + (thread_ptr -> __mw_thread_exit) (thread_ptr); +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) \ + if (thread_ptr -> __mw_thread_exit) \ + (thread_ptr -> __mw_thread_exit) (thread_ptr); + +#else + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _clri(); +#define TX_RESTORE _seti(interrupt_save); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define ARC HS extension for assigning a hardware register bank to a thread. Note that this API can only be + called after a thread is created from initialization. It is assumed that interrupts are disabled and the + initialization code is running in hardware register bank 0. It is also assumed that the application provides + a vaild register bank number to the API. */ + +#ifndef TX_SOURCE_CODE +#define tx_initialize_fast_interrupt_setup _tx_initialize_fast_interrupt_setup +#define tx_thread_register_bank_assign _tx_thread_register_bank_assign +#endif + +VOID tx_initialize_fast_interrupt_setup(VOID *stack_ptr); +VOID tx_thread_register_bank_assign(VOID *thread_ptr, UINT register_bank); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARC_HS/MetaWare Version 6.0 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + diff --git a/ports/arc_hs/metaware/readme_threadx.txt b/ports/arc_hs/metaware/readme_threadx.txt new file mode 100644 index 00000000..7f7e1716 --- /dev/null +++ b/ports/arc_hs/metaware/readme_threadx.txt @@ -0,0 +1,251 @@ + Microsoft's Azure RTOS ThreadX for ARC HS + + Using the MetaWare Tools + +1. Open the Azure RTOS Workspace + +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace, which is located inside the "example_build" directory. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the ThreadX library project +file "tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the MetaWare ARC HS +simulation. The instructions that follow describe how to get the ThreadX +demonstration running. + +Building the demonstration is easy; simply select the demonstration project file +"sample_threadx." At this point, select the build button and observe the +compilation, assembly, and linkage of the ThreadX demonstration application. + +After the demonstration is built, click on the "Debug" button and it will +automatically launch a pre-configured connection to the ARC HS simulator. + +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c +application. + + +4. System Initialization + +The system entry point using the MetaWare tools is at the label _start. +This is defined within the crt1.s file supplied by MetaWare. In addition, +this is where all static and global preset C variable initialization +processing is called from. + +After the MetaWare startup function completes, ThreadX initialization is +called. The main initialization function is _tx_initialize_low_level and +is located in the file tx_initialize_low_level.s. This function is +responsible for setting up various system data structures, and interrupt +vectors. + +By default free memory is assumed to start at the section .free_memory +which is referenced in tx_initialize_low_level.s and located in the +linker control file after all the linker defined RAM addresses. This is +the address passed to the application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The ARC compiler assumes that registers r0-r12 are scratch registers for +each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a +context switch happens as a result of making a ThreadX service call (which +is itself a C function). In such cases, the saved context of a thread is +only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 LP_START blink + 0x08 LP_END fp + 0x0C LP_COUNT r26 + 0x10 blink r25 + 0x14 ilink r24 + 0x18 fp r23 + 0x1C r26 r22 + 0x20 r25 r21 + 0x24 r24 r20 + 0x28 r23 r19 + 0x2C r22 r18 + 0x30 r21 r17 + 0x34 r20 r16 + 0x38 r19 r15 + 0x3C r18 r14 + 0x40 r17 r13 + 0x44 r16 STATUS32 + 0x48 r15 r30 + 0x4C r14 + 0x50 r13 + 0x54 r12 + 0x58 r11 + 0x5C r10 + 0x60 r9 + 0x64 r8 + 0x68 r7 + 0x6C r6 + 0x70 r5 + 0x74 r4 + 0x78 r3 + 0x7C r2 + 0x80 r1 + 0x84 r0 + 0x88 r30 + 0x8C reserved + 0x90 reserved + 0x94 reserved + 0x98 reserved + 0x9C bta + 0xA0 point of interrupt + 0xA4 STATUS32 + + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat +file to remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for the +ARC HS processor, including support for software interrupts and fast +hardware interrupts. + +7.1 Software Interrupt Handling + +The following template should be used for software interrupts +managed by ThreadX: + + .global _tx_interrupt_x +_tx_interrupt_x: + sub sp, sp, 160 ; Allocate an interrupt stack frame + st blink, [sp, 16] ; Save blink (blink must be saved before _tx_thread_context_save) + bl _tx_thread_context_save ; Save interrupt context +; +; /* Application ISR processing goes here! Your ISR can be written in +; assembly language or in C. If it is written in C, you must allocate +; 16 bytes of stack space before it is called. This must also be +; recovered once your C ISR return. An example of this is shown below. +; +; If the ISR is written in assembly language, only the compiler scratch +; registers are available for use without saving/restoring (r0-r12). +; If use of additional registers are required they must be saved and +; restored. */ +; + bl.d your_ISR_written_in_C ; Call an ISR written in C + sub sp, sp, 16 ; Allocate stack space (delay slot) + add sp, sp, 16 ; Recover stack space + +; + b _tx_thread_context_restore ; Restore interrupt context + + +The application handles interrupts directly, which necessitates all register +preservation by the application's ISR. ISRs that do not use the ThreadX +_tx_thread_context_save and _tx_thread_context_restore routines are not +allowed access to the ThreadX API. In addition, custom application ISRs +should be higher priority than all ThreadX-managed ISRs. + +7.2 Fast Interrupt Handling + +ThreadX supports the ARC HS fast interrupt processing. It is assumed that +multiple register banks are available and the ARC HS processor automatically +uses register bank 1 as the fast interrupt register bank. + +In order to use fast interrupts with register bank 1, the interrupt desired +must have priority 0 and the application must call the following ThreadX API +to setup register bank 1: + +void tx_initialize_fast_interrupt_setup(void *stack_ptr); + +The parameter "stack_ptr" is the first usable address for the fast interrupt +stack. For example, assume the fast interrupt stack is to be located in the +array "unsigned char fast_interrupt_stack[1024]" the call to this API would +look like: + + tx_initialize_fast_interrupt_setup(&fast_interrupt_stack[1020]); + +As for the fast interrupt ISR, the following template should be used for +ARC HS fast interrupts managed by ThreadX: + + .global _tx_fast_interrupt_x +_tx_fast_interrupt_x: + bl _tx_thread_context_fast_save +; +; /* Fast ISR processing goes here. Interrupts must not be re-enabled +; in the fast interrupt mode. Also note that multiple register banks +; are available and the fast interrupt processing always maps to +; register bank 1. */ +; + b _tx_thread_context_fast_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of +ThreadX will still run. + +By default, the ThreadX timer interrupt is mapped to the ARC HS auxiliary +timer 0, which generates low priority interrupts on interrupt vector 16. +It is easy to change the timer interrupt source and priority by changing the +setup code in tx_initialize_low_level.s. + + +9. Thread Hardware Register Bank Context + +ThreadX supports the use of hardware register banks on the ARC HS. A hardware +register bank may be associated with a specific application thread via the +following API: + +void tx_thread_register_bank_assign(TX_THREAD *thread_ptr, register_bank); + +This API is assumed to be called from initialization (interrupts are locked out +and execution is from register bank 0) and after the specified thread has been +created. This API assumes the register bank number is correct, i.e., a valid +register bank greater than 0 and one that hasn't been used for another thread. + +Note: if fast interrupts are used, register bank 1 must also not be used. In this +case the valid register bank range is 2 through maximum register banks minus 1. + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 for ARC HS using MetaWare tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s b/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s new file mode 100644 index 00000000..4effd106 --- /dev/null +++ b/ports/arc_hs/metaware/src/tx_initialize_fast_interrupt_setup.s @@ -0,0 +1,107 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_fast_interrupt_setup ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function initializes register bank 1 for fast interrupt use. */ +;/* The initialization includes setting the stack pointer to the value */ +;/* supplied by the caller. */ +;/* */ +;/* INPUT */ +;/* */ +;/* stack_ptr Pointer to stack for bank 1 */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_fast_interrupt_setup(VOID *stack_ptr) +;{ + .global _tx_initialize_fast_interrupt_setup + .type _tx_initialize_fast_interrupt_setup, @function +_tx_initialize_fast_interrupt_setup: +; +; /* Assume this routine is being called from initialization, with interrupts +; disabled and from register bank 0. Also assume that the stack pointer +; input is valid, i.e., there is no error checking on the validity of +; register_bank. */ +; + sub sp, sp, 8 ; Build a small stack frame to hold the setup information + st gp, [sp, 0] ; Save gp in the frame + st r0, [sp, 4] ; Save sp in the frame + mov ilink, sp ; Move the stack frame into ilink + mov r1, 1 ; Select register bank 1 + asl r2, r1, 16 ; Move the register bank bits over to proper location + lr r3, [status32] ; Pickup status32 register + or r3, r3, r2 ; Build new status32 register + kflag r3 ; Move to the hardware register bank + mov r0, ilink ; Place stack pointer in r0 + ld sp, [r0, 4] ; Setup stack pointer for this hardware register bank + mov fp, 0 ; Setup fp + ld gp, [r0, 0] ; Setup gp + mov blink, 0 ; Setup blink + mov r0, 0 ; Clear r0 + sub sp, sp, 8 ; Reserve space for saving ilink and status32.p0 on thread preemption + lr r3, [status32] ; Pickup status32 register + bclr r3, r3, 16 ; Build register bank 0 value + bclr r3, r3, 17 ; + bclr r3, r3, 18 ; + kflag r3 ; Move back to register bank 0 + j_s.d [blink] ; Return to caller + add sp, sp, 8 ; +;} + .end diff --git a/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s b/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s new file mode 100644 index 00000000..9b5e71b2 --- /dev/null +++ b/ports/arc_hs/metaware/src/tx_thread_context_fast_restore.s @@ -0,0 +1,303 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; + .equ BTA, 0x412 +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_fast_restore ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fast interrupt context, which can be a */ +;/* nesting condition on a non-fast ISR, an idle system restore, a */ +;/* restore of an interrupted thread, and a preemption of an interrupted*/ +;/* thread. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_fast_restore(VOID) +;{ + + .global _tx_thread_context_fast_restore + .type _tx_thread_context_fast_restore, @function +_tx_thread_context_fast_restore: +; +; /* Note: it is assumed that the stack pointer is in the same position now as +; it was after the last context fast save call. */ +; + + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + bl.d _tx_execution_isr_exit ; Call the ISR exit function + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space + .endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + ld r0, [gp, _tx_thread_system_state@sda] ; Pickup system state contents + sub r0, r0, 1 ; Decrement the system state + st r0, [gp, _tx_thread_system_state@sda] ; Store the new system state + breq r0, 0, __tx_thread_not_nested_restore ; If zero, not a nested interrupt +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + +__tx_thread_nested_restore: + rtie ; Return from interrupt +; +; +; } +__tx_thread_not_nested_restore: +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread pointer + ld r2, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable flag + sub.f 0, r0, 0 ; Set condition codes + beq.d __tx_thread_idle_system_restore ; If NULL, idle system was interrupted + lr r4, [AUX_IRQ_ACT] ; Pickup the interrupt active register + neg r5, r4 ; Negate + and r5, r4, r5 ; See if there are any other interrupts present + brne.d r4, r5, __tx_thread_no_preempt_restore ; If more interrupts, just return to the point of interrupt + ld r4, [gp, _tx_thread_execute_ptr@sda] ; Pickup next thread to execute + brne r2, 0, __tx_thread_no_preempt_restore ; If set, don't preempt executing thread + brne r0, r4, __tx_thread_preempt_restore ; Not equal, preempt executing thread +; +; +__tx_thread_no_preempt_restore: +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Return to the point of interrupt. */ +; + rtie ; Return from interrupt +; +; } +; else +; { +__tx_thread_preempt_restore: +; + lr r3, [status32_p0] ; Pickup the interrupted status32.p0 register + lsr r4, r3, 16 ; Move the register bank bits down + and r4, r4, 7 ; Isolate the register bank + breq r4, 0, __tx_software_interrupt_context ; If register bank 0, software interrupt context is present + st ilink, [sp, 0] ; Save ilink (point of interrupt) + st r3, [sp, 4] ; Save actual status32.p0 + bclr r4, r3, 16 ; Build register bank 0 value + bclr r4, r4, 17 ; + bclr r4, r4, 18 ; + sr r4, [status32_p0] ; Setup status32.p0 to return to bank 0 when fast ISR is finishe + mov ilink, sp ; Pass the information back to the other register bank via ilink + bclr r3, r3, 31 ; Make sure interrupts are not enabled + kflag r3 ; Switch back to the interrupted thread's hardware register bank + sub sp, sp, 168 ; Allocate an hardware interrupt stack frame + st r0, [sp, 132] ; Temporarily save r0 + mov r0, 3 ; Build hardware interrupt stack type + st r0, [sp, 0] ; Setup interrupt stack type + + .ifndef TX_DISABLE_LP + lr r0, [LP_START] ; Pickup LP_START + st r0, [sp, 4] ; Save LP_START + lr r0, [LP_END] ; Pickup LP_END + st r0, [sp, 8] ; Save LP_END + st LP_COUNT, [sp, 12] ; Save LP_COUNT + .endif + + lr r0, [BTA] ; Pickup BTA + st r0, [sp, 156] ; Save BTA + ld r0, [ilink, 0] ; Pickup the point of interrupt + st r0, [sp, 160] ; Setup the point of interrupt + st r0, [sp, 20] ; Save ilink + ld r0, [ilink, 4] ; Pickup the status32 + st r0, [sp, 164] ; Setup the status32 + ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread pointer + st sp, [r0, 8] ; Save stack pointer in thread control block + ld r0, [sp, 132] ; Restore r0 + lr ilink, [status32] ; Pickup status32 register + bset ilink, ilink, 16 ; Build register bank 1 value + bclr ilink, ilink, 17 ; + bclr ilink, ilink, 18 ; + kflag ilink ; Move back to register bank 0 + b __tx_preempt_save_done ; Done, finished with preemption save + +__tx_software_interrupt_context: + st ilink, [sp, 0] ; Save ilink (point of interrupt) + st r3, [sp, 4] ; Save status32 + mov ilink, sp ; Pass the information back to the other register bank via ilink + bclr r3, r3, 31 ; Make sure interrupts are not enabled + kflag r3 ; Switch back to the interrupted thread's hardware register bank + sub sp, sp, 168 ; Allocate an hardware interrupt stack frame + st blink, [sp, 16] ; Save blink + st fp, [sp, 24] ; Save fp + st gp, [sp, 28] ; Save gp + st r25, [sp, 32] ; Save r25 + st r24, [sp, 36] ; Save r24 + st r23, [sp, 40] ; Save r23 + st r22, [sp, 44] ; Save r22 + st r21, [sp, 48] ; Save r21 + st r20, [sp, 52] ; Save r20 + st r19, [sp, 56] ; Save r19 + st r18, [sp, 60] ; Save r18 + st r17, [sp, 64] ; Save r17 + st r16, [sp, 68] ; Save r16 + st r15, [sp, 72] ; Save r15 + st r14, [sp, 76] ; Save r14 + st r13, [sp, 80] ; Save r13 + st r12, [sp, 84] ; Save r12 + st r11, [sp, 88] ; Save r11 + st r10, [sp, 92] ; Save r10 + st r9, [sp, 96] ; Save r9 + st r8, [sp, 100] ; Save r8 + st r7, [sp, 104] ; Save r7 + st r6, [sp, 108] ; Save r6 + st r5, [sp, 112] ; Save r5 + st r4, [sp, 116] ; Save r6 + st r3, [sp, 120] ; Save r3 + st r2, [sp, 124] ; Save r2 + st r1, [sp, 128] ; Save r1 + st r0, [sp, 132] ; Save r0 + st r30, [sp, 136] ; Save r30 + + .ifndef TX_DISABLE_LP + lr r10, [LP_START] ; Pickup LP_START + lr r9, [LP_END] ; Pickup LP_END + st LP_COUNT, [sp, 12] ; Save LP_COUNT + st r10, [sp, 4] ; Save LP_START + st r9, [sp, 8] ; Save LP_END + .endif + + lr r0, [BTA] ; Pickup BTA + st r0, [sp, 156] ; Save BTA + mov r6, 1 ; Build interrupt stack type + st r6, [sp, 0] ; Setup interrupt stack type + ld r0, [ilink, 0] ; Pickup the point of interrupt + st r0, [sp, 160] ; Setup the point of interrupt + st r0, [sp, 20] ; Save ilink + ld r0, [ilink, 4] ; Pickup the status32 + st r0, [sp, 164] ; Setup the status32 + ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread pointer + st sp, [r0, 8] ; Save stack pointer in thread control block + lr ilink, [status32] ; Pickup status32 register + bset ilink, ilink, 16 ; Build register bank 1 value + bclr ilink, ilink, 17 ; + bclr ilink, ilink, 18 ; + kflag ilink ; Move back to register bank 1 +__tx_preempt_save_done: +; + ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread ptr +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + ld r2, [gp, _tx_timer_time_slice@sda] ; Pickup time-slice contents + mov r7, 0 ; Build clear/NULL value + breq r2, 0, __tx_thread_dont_save_ts ; No time-slice, don't need to save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + st r2, [r0, 24] ; If set, save remaining time-slice + st r7, [gp, _tx_timer_time_slice@sda] ; If set, clear time slice +; +; } +__tx_thread_dont_save_ts: +; +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + st r7, [gp, _tx_thread_current_ptr@sda] ; Set current thread ptr to NULL + mov ilink, _tx_thread_schedule ; Build address of scheduler + rtie ; Return from interrupt to scheduler +; +; } +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; +__tx_thread_idle_system_restore: + + lr r4, [AUX_IRQ_ACT] ; Pickup the interrupt active register + neg r5, r4 ; Negate + and r5, r4, r5 ; See if there are any other interrupts present + sub.f 0, r4, r5 ; Set condition codes + bne __tx_thread_nested_restore ; If more interrupts, just return to the point of interrupt + + mov ilink, _tx_thread_schedule ; Build address of scheduler + rtie ; Return from interrupt to scheduler +; +;} + .end + diff --git a/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s b/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s new file mode 100644 index 00000000..c25f39bb --- /dev/null +++ b/ports/arc_hs/metaware/src/tx_thread_context_fast_save.s @@ -0,0 +1,108 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_fast_save ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of fast interrupt processing. The function assumes that */ +;/* fast interrupts are enabled (priority 0) and multiple register */ +;/* banks are available. In this case, register bank 1 is reserved by */ +;/* hardware for fast interrupts. Additional assumptions include that */ +;/* there will be no nested fast interrupts and the LP_START, LP_END, */ +;/* and LP_COUNT registers are not used in the application's fast */ +;/* interrupt ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_fast_save(VOID) +;{ + .global _tx_thread_context_fast_save + .type _tx_thread_context_fast_save, @function +_tx_thread_context_fast_save: +; +; /* Increment nested interrupt count. */ +; _tx_thread_system_state++; +; + ld r0, [gp, _tx_thread_system_state@sda] ; Pickup system state + add r0, r0, 1 ; Increment the nested interrupt count + st r0, [gp, _tx_thread_system_state@sda] ; Update system state +; +; + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + sub sp, sp, 32 ; Allocating some space on the stack + st blink, [sp, 16] ; Save blink + bl.d _tx_execution_isr_enter ; Call the ISR enter function + nop ; Delay slot + ld blink, [sp, 16] ; Recover blink + add sp, sp, 32 ; Recover the stack space + .endif +; + + j [blink] ; Return to the ISR +; +;} + .end diff --git a/ports/arc_hs/metaware/src/tx_thread_context_restore.s b/ports/arc_hs/metaware/src/tx_thread_context_restore.s new file mode 100644 index 00000000..497aec43 --- /dev/null +++ b/ports/arc_hs/metaware/src/tx_thread_context_restore.s @@ -0,0 +1,322 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; + .equ BTA, 0x412 +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore, @function +_tx_thread_context_restore: +; +; /* Note: it is assumed that the stack pointer is in the same position now as +; it was after the last context save call. */ +; +; /* Lockout interrupts. */ +; + clri ; Disable interrupts + nop ; Delay for interrupts to really be disabled + + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + bl.d _tx_execution_isr_exit ; Call the ISR exit function + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space + .endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + ld r0, [gp, _tx_thread_system_state@sda] ; Pickup system state contents + sub r0, r0, 1 ; Decrement the system state + st r0, [gp, _tx_thread_system_state@sda] ; Store the new system state + breq r0, 0, __tx_thread_not_nested_restore ; If zero, not a nested interrupt +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + +__tx_thread_nested_restore: + + .ifndef TX_DISABLE_LP + ld r0, [sp, 4] ; Recover LP_START + sr r0, [LP_START] ; Restore LP_START + ld r1, [sp, 8] ; Recover LP_END + sr r1, [LP_END] ; Restore LP_END + ld r2, [sp, 12] ; Recover LP_COUNT + mov LP_COUNT, r2 + .endif + + ld r2, [sp, 156] ; Pickup BTA + sr r2, [BTA] ; Recover BTA + .ifdef TX_ENABLE_ACC + ld r58, [sp, 140] ; Recover r58 + ld r59, [sp, 144] ; Recover r59 + .endif + ld blink, [sp, 16] ; Recover blink + ld r12, [sp, 84] ; Recover r12 + ld r11, [sp, 88] ; Recover r11 + ld r10, [sp, 92] ; Recover r10 + ld r9, [sp, 96] ; Recover r9 + ld r8, [sp, 100] ; Recover r8 + ld r7, [sp, 104] ; Recover r7 + ld r6, [sp, 108] ; Recover r6 + ld r5, [sp, 112] ; Recover r5 + ld r4, [sp, 116] ; Recover r4 + ld r3, [sp, 120] ; Recover r3 + ld r2, [sp, 124] ; Recover r2 + ld r1, [sp, 128] ; Recover r1 + ld r0, [sp, 132] ; Recover r0 + add sp, sp, 160 ; Recover interrupt stack frame + rtie ; Return from interrupt +; +; +; } +__tx_thread_not_nested_restore: +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread pointer + ld r2, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable flag + sub.f 0, r0, 0 ; Set condition codes + beq.d __tx_thread_idle_system_restore ; If NULL, idle system was interrupted + lr r4, [AUX_IRQ_ACT] ; Pickup the interrupt active register + neg r5, r4 ; Negate + and r5, r4, r5 ; See if there are any other interrupts present + brne.d r4, r5, __tx_thread_no_preempt_restore ; If more interrupts, just return to the point of interrupt + ld r4, [gp, _tx_thread_execute_ptr@sda] ; Pickup next thread to execute + brne r2, 0, __tx_thread_no_preempt_restore ; If set, don't preempt executing thread + brne r0, r4, __tx_thread_preempt_restore ; Not equal, preempt executing thread +; +; +__tx_thread_no_preempt_restore: +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; + +; /* Recover the saved context and return to the point of interrupt. */ +; + ld sp, [r0, 8] ; Switch back to thread's stack + + .ifndef TX_DISABLE_LP + ld r0, [sp, 4] ; Recover LP_START + sr r0, [LP_START] ; Restore LP_START + ld r1, [sp, 8] ; Recover LP_END + sr r1, [LP_END] ; Restore LP_END + ld r2, [sp, 12] ; Recover LP_COUNT + mov LP_COUNT, r2 + .endif + + ld r2, [sp, 156] ; Pickup BTA + sr r2, [BTA] ; Recover BTA + .ifdef TX_ENABLE_ACC + ld r58, [sp, 140] ; Recover r58 + ld r59, [sp, 144] ; Recover r59 + .endif + ld blink, [sp, 16] ; Recover blink + ld r12, [sp, 84] ; Recover r12 + ld r11, [sp, 88] ; Recover r11 + ld r10, [sp, 92] ; Recover r10 + ld r9, [sp, 96] ; Recover r9 + ld r8, [sp, 100] ; Recover r8 + ld r7, [sp, 104] ; Recover r7 + ld r6, [sp, 108] ; Recover r6 + ld r5, [sp, 112] ; Recover r5 + ld r4, [sp, 116] ; Recover r4 + ld r3, [sp, 120] ; Recover r3 + ld r2, [sp, 124] ; Recover r2 + ld r1, [sp, 128] ; Recover r1 + ld r0, [sp, 132] ; Recover r0 + add sp, sp, 160 ; Recover interrupt stack frame + rtie ; Return from interrupt +; +; } +; else +; { +__tx_thread_preempt_restore: +; + ld r7, [r0, 8] ; Pickup stack pointer + lr r3, [status32] ; Pickup the status32 register + lsr r4, r3, 16 ; Move the register bank bits down + and r4, r4, 7 ; Isolate the register bank + breq r4, 0, __tx_software_interrupt_context ; If register bank 0, software interrupt context is present + mov sp, r7 ; Setup sp in this register bank + mov r6, 3 ; Build hardware interrupt stack type + st r6, [sp, 0] ; Setup interrupt stack type + ld blink, [sp, 16] ; Recover blink + ld r12, [sp, 84] ; Recover r12 + ld r11, [sp, 88] ; Recover r11 + ld r10, [sp, 92] ; Recover r10 + ld r9, [sp, 96] ; Recover r9 + ld r8, [sp, 100] ; Recover r8 + ld r7, [sp, 104] ; Recover r7 + ld r6, [sp, 108] ; Recover r6 + ld r5, [sp, 112] ; Recover r5 + ld r4, [sp, 116] ; Recover r4 + ld r3, [sp, 120] ; Recover r3 + ld r2, [sp, 124] ; Recover r2 + ld r1, [sp, 128] ; Recover r1 + ld r0, [sp, 132] ; Recover r0 + lr ilink, [status32] ; Pickup status32 register + bclr ilink, ilink, 16 ; Build register bank 0 value + bclr ilink, ilink, 17 ; + bclr ilink, ilink, 18 ; + kflag ilink ; Move back to register bank 0 + ld sp, [gp, _tx_thread_system_stack_ptr@sda] ; Switch to system stack + ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread ptr + b __tx_preempt_save_done ; Done, finished with preemption save + nop + +__tx_software_interrupt_context: + mov r6, 1 ; Build interrupt stack type + st r6, [r7, 0] ; Setup interrupt stack type + st fp, [r7, 24] ; Save fp + st gp, [r7, 28] ; Save gp + st r25, [r7, 32] ; Save r25 + st r24, [r7, 36] ; Save r24 + st r23, [r7, 40] ; Save r23 + st r22, [r7, 44] ; Save r22 + st r21, [r7, 48] ; Save r21 + st r20, [r7, 52] ; Save r20 + st r19, [r7, 56] ; Save r19 + st r18, [r7, 60] ; Save r18 + st r17, [r7, 64] ; Save r17 + st r16, [r7, 68] ; Save r16 + st r15, [r7, 72] ; Save r15 + st r14, [r7, 76] ; Save r14 + st r13, [r7, 80] ; Save r13 + st r30, [r7, 136] ; Save r30 +__tx_preempt_save_done: +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + ld r2, [gp, _tx_timer_time_slice@sda] ; Pickup time-slice contents + mov r7, 0 ; Build clear/NULL value + breq r2, 0, __tx_thread_dont_save_ts ; No time-slice, don't need to save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + st r2, [r0, 24] ; If set, save remaining time-slice + st r7, [gp, _tx_timer_time_slice@sda] ; If set, clear time slice +; +; } +__tx_thread_dont_save_ts: +; +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + st r7, [gp, _tx_thread_current_ptr@sda] ; Set current thread ptr to NULL + + sub sp, sp, 8 ; Allocate a small stack frame on the system stack + lr r0, [STATUS32] ; Pickup STATUS32 + st r0, [sp, 4] ; Place on stack + mov r0, _tx_thread_schedule ; Build address of scheduler + st r0, [sp, 0] ; Write over the point of interrupt + rtie ; Return from interrupt to scheduler +; +; } +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; +__tx_thread_idle_system_restore: + + lr r4, [AUX_IRQ_ACT] ; Pickup the interrupt active register + neg r5, r4 ; Negate + and r5, r4, r5 ; See if there are any other interrupts present + sub.f 0, r4, r5 ; Set condition codes + bne __tx_thread_nested_restore ; If more interrupts, just return to the point of interrupt + + lr r0, [STATUS32] ; Pickup STATUS32 + st r0, [sp, 4] ; Place on stack + mov r0, _tx_thread_schedule ; Build address of scheduler + st r0, [sp, 0] ; Write over the point of interrupt + rtie ; Return from interrupt to scheduler +; +;} + .end + diff --git a/ports/arc_hs/metaware/src/tx_thread_context_save.s b/ports/arc_hs/metaware/src/tx_thread_context_save.s new file mode 100644 index 00000000..b24cc042 --- /dev/null +++ b/ports/arc_hs/metaware/src/tx_thread_context_save.s @@ -0,0 +1,242 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; + .equ BTA, 0x412 +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + .global _tx_thread_context_save + .type _tx_thread_context_save, @function +_tx_thread_context_save: +; +; /* Upon entry to this routine, it is assumed that an interrupt stack frame +; has already been allocated, and the interrupted blink register is already saved. */ +; + clri ; Disable interrupts + st r1, [sp, 128] ; Save r1 + st r0, [sp, 132] ; Save r0 +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + ld r0, [gp, _tx_thread_system_state@sda] ; Pickup system state + st r3, [sp, 120] ; Save r3 + st r2, [sp, 124] ; Save r2 + breq r0, 0, __tx_thread_not_nested_save ; If 0, we are not in a nested + ; condition +; +; /* Nested interrupt condition. */ +; + add r0, r0, 1 ; Increment the nested interrupt count + st r0, [gp, _tx_thread_system_state@sda] ; Update system state +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; +__tx_thread_nested_save: ; Label is for special nested interrupt case from idle system save below + st r12, [sp, 84] ; Save r12 + st r11, [sp, 88] ; Save r11 + st r10, [sp, 92] ; Save r10 + st r9, [sp, 96] ; Save r9 + st r8, [sp, 100] ; Save r8 + st r7, [sp, 104] ; Save r7 + st r6, [sp, 108] ; Save r6 + st r5, [sp, 112] ; Save r5 + st r4, [sp, 116] ; Save r6 + lr r10, [LP_START] ; Pickup LP_START + lr r9, [LP_END] ; Pickup LP_END + st LP_COUNT, [sp, 12] ; Save LP_COUNT + st r10, [sp, 4] ; Save LP_START + st r9, [sp, 8] ; Save LP_END + .ifdef TX_ENABLE_ACC + st r58, [sp, 140] ; Save r58 + st r59, [sp, 144] ; Save r59 + .endif + lr r0, [BTA] ; Pickup BTA + st r0, [sp, 156] ; Save BTA + +; +; /* Return to the ISR. */ +; + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + sub sp, sp, 32 ; Allocating some space on the stack + st blink, [sp, 16] ; Save blink + bl.d _tx_execution_isr_enter ; Call the ISR enter function + nop ; Delay slot + ld blink, [sp, 16] ; Recover blink + add sp, sp, 32 ; Recover the stack space + .endif +; + + j.d [blink] ; Return to Level 1 ISR + st ilink, [sp, 20] ; Save ilink +; +__tx_thread_not_nested_save: +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + add r0, r0, 1 ; Increment the nested interrupt count + st r0, [gp, _tx_thread_system_state@sda] ; Update system state + ld r1, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread pointer + st r12, [sp, 84] ; Save r12 + st r11, [sp, 88] ; Save r11 + breq r1, 0, __tx_thread_idle_system_save ; If no thread is running, idle system was + ; interrupted. +; +; /* Save minimal context of interrupted thread. */ +; + st r10, [sp, 92] ; Save r10 + st r9, [sp, 96] ; Save r9 + st r8, [sp, 100] ; Save r8 + st r7, [sp, 104] ; Save r7 + st r6, [sp, 108] ; Save r6 + st r5, [sp, 112] ; Save r5 + st r4, [sp, 116] ; Save r4 + lr r10, [LP_START] ; Pickup LP_START + lr r9, [LP_END] ; Pickup LP_END + st LP_COUNT, [sp, 12] ; Save LP_COUNT + st r10, [sp, 4] ; Save LP_START + st r9, [sp, 8] ; Save LP_END + st ilink, [sp, 20] ; Save ilink + .ifdef TX_ENABLE_ACC + st r58, [sp, 140] ; Save r58 + st r59, [sp, 144] ; Save r59 + .endif + lr r0, [BTA] ; Pickup BTA + st r0, [sp, 156] ; Save BTA +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; + st sp, [r1, 8] ; Save thread's stack pointer + + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + sub sp, sp, 32 ; Allocating some space on the stack + st blink, [sp, 16] ; Save blink + bl.d _tx_execution_isr_enter ; Call the ISR enter function + nop ; Delay slot + ld blink, [sp, 16] ; Recover blink + add sp, sp, 32 ; Recover the stack space + .endif +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + j_s.d [blink] ; Return to calling ISR + ld sp, [gp, _tx_thread_system_stack_ptr@sda] ; Switch to system stack +; +; } +; else +; { +; +__tx_thread_idle_system_save: +; +; /* Interrupt occurred in the scheduling loop. */ +; + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + sub sp, sp, 32 ; Allocating some space on the stack + st blink, [sp, 16] ; Save blink + bl.d _tx_execution_isr_enter ; Call the ISR enter function + nop ; Delay slot + ld blink, [sp, 16] ; Recover blink + add sp, sp, 32 ; Recover the stack space + .endif +; +; /* See if we have a special nesting condition. This happens when the higher priority +; interrupt occurs before the nested interrupt logic is valid. */ +; + lr r0, [AUX_IRQ_ACT] ; Pickup the interrupt active register + neg r1, r0 ; Negate + and r1, r0, r1 ; See if there are any other interrupts present + brne r0, r1, __tx_thread_nested_save ; If more interrupts, go into the nested interrupt save logic +; +; /* Not much to do here, just adjust the stack pointer, and return to +; ISR processing. */ +; + j_s.d [blink] ; Return to ISR + add sp, sp, 160 ; Recover stack space +; +; } +;} + .end diff --git a/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s b/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..cfa6221b --- /dev/null +++ b/ports/arc_hs/metaware/src/tx_thread_interrupt_control.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control, @function +_tx_thread_interrupt_control: +; +; /* Pickup current interrupt lockout posture. */ +; + clri r1 ; Get current interrupt state +; +; /* Apply the new interrupt posture. */ +; + seti r0 ; Set desired interrupt state + j_s.d [blink] ; Return to caller with delay slot + mov r0, r1 ; Return previous mask value. Return value is TX_INT_DISABLE or TX_INT_ENABLE. +; +;} + .end diff --git a/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s b/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s new file mode 100644 index 00000000..172a7f31 --- /dev/null +++ b/ports/arc_hs/metaware/src/tx_thread_register_bank_assign.s @@ -0,0 +1,113 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_register_bank_assign ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* register_bank Register bank number */ +;/* (1 through max-1) */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_register_bank_assign(VOID *thread_ptr, UINT register_bank) +;{ + .global _tx_thread_register_bank_assign + .type _tx_thread_register_bank_assign, @function +_tx_thread_register_bank_assign: +; +; /* Assume this routine is being called from initialization, with interrupts +; disabled and from register bank 0. Also assume that the thread pointer and +; register bank input is valid, i.e., there is no error checking on the validity of +; the thread pointer or the register_bank. +; +; It is worth noting that if fast interrupts are being used, register bank 1 +; is reserved for the fast interrupt processing, so thread register bank assignments +; should begin at bank 2. */ +; + mov ilink, r0 ; Move the thread control block into ilink + asl r2, r1, 16 ; Move the register bank bits over to proper location + lr r3, [status32] ; Pickup status32 register + or r3, r3, r2 ; Build new status32 register + ld r4, [r0, 8] ; Pickup stack pointer for the thread + ld r5, [r4, 164] ; Pickup initial status32 from stack area + or r5, r5, r2 ; Modify initial status32 with register bank number + st r5, [r4, 164] ; Store initial status32 in stack area + kflag r3 ; Move to the hardware register bank + mov r0, ilink ; Place thread control block in r0 + ld sp, [r0, 8] ; Setup stack pointer for this hardware register bank + ld fp, [sp, 24] ; Setup fp + ld gp, [sp, 28] ; Setup gp + ld blink, [sp, 16] ; Setup blink + ld ilink, [sp, 20] ; Setup ilink + lr r3, [status32] ; Pickup status32 register + bclr r3, r3, 16 ; Build register bank 0 value + bclr r3, r3, 17 ; + bclr r3, r3, 18 ; + kflag r3 ; Move back to register bank 0 + mov r5, 3 ; Build type for hardware interrupt context + j_s.d [blink] ; Return to caller + st r5, [r4, 0] ; Set stack frame type +;} + .end diff --git a/ports/arc_hs/metaware/src/tx_thread_schedule.s b/ports/arc_hs/metaware/src/tx_thread_schedule.s new file mode 100644 index 00000000..7560e34f --- /dev/null +++ b/ports/arc_hs/metaware/src/tx_thread_schedule.s @@ -0,0 +1,265 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; + .equ BTA, 0x412 +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + .global _tx_thread_schedule + .type _tx_thread_schedule, @function +_tx_thread_schedule: +; +; /* Switch to system stack. */ +; + ld sp, [gp, _tx_thread_system_stack_ptr@sda] ; Switch to system stack +; +; /* Enable interrupts. */ +; + mov r0, 0x1F ; Build enable interrupt value + seti r0 ; Enable interrupts +; +; /* Wait for a thread to execute. */ +; do +; { +; +__tx_thread_schedule_loop: +; + ld r0, [gp, _tx_thread_execute_ptr@sda] ; Pickup next thread to execute + breq r0, 0, __tx_thread_schedule_loop ; If NULL, keep looking +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + clri ; Lockout interrupts + nop ; Delay for interrupts to really be disabled +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + st r0, [gp, _tx_thread_current_ptr@sda] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + ld r3, [r0, 4] ; Pickup run counter + ld r4, [r0, 24] ; Pickup time-slice for this thread + add r3, r3, 1 ; Increment run counter + st r3, [r0, 4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + st r4, [gp, _tx_timer_time_slice@sda] ; Setup time-slice +; + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + bl.d _tx_execution_thread_enter ; Call the thread execution enter function + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space + .endif +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; + ld sp, [r0, 8] ; Switch to thread's stack + ld r1, [sp, 0] ; Pickup stack type + brlt r1, 2, __tx_restore_non_hw_context ; If less than 2, restore a software context + breq r1, 3, __tx_hw_interrupt_restore ; If interrupt restore, restore interrupted hardware context + ld r2, [sp, 4] ; Pickup status32 + kflag r2 ; Enter the proper register bank + ld r3, [sp, 8] ; Pickup the saved interrupt posture + add sp, sp, 12 ; Recover small stack frame + j_s.d [blink] ; Return to thread and restore flags + seti r3 ; Recover STATUS32 + +__tx_hw_interrupt_restore: + + mov r0, 0x2 ; Pretend level 1 interrupt is returning + sr r0, [AUX_IRQ_ACT] ; + + .ifndef TX_DISABLE_LP + ld r0, [sp, 4] ; Recover LP_START + sr r0, [LP_START] ; Restore LP_START + ld r1, [sp, 8] ; Recover LP_END + sr r1, [LP_END] ; Restore LP_END + ld r2, [sp, 12] ; Recover LP_COUNT + mov LP_COUNT, r2 + .endif + + .ifdef TX_ENABLE_ACC + ld r58, [sp, 140] ; Recover r58 + ld r59, [sp, 144] ; Recover r59 + .endif + + ld r0, [sp, 156] ; Pickup saved BTA + sr r0, [BTA] ; Recover BTA + ld ilink, [sp, 20] ; Recover ilink + ld r0, [sp, 164] ; Pickup the interrupted status32 + bclr r0, r0, 31 ; Make sure interrupts are not enabled + kflag r0 ; Switch to the proper register bank + add sp, sp, 160 ; Recover the interrupt stack frame + rtie ; Return to point of interrupt + +__tx_restore_non_hw_context: +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + ld r1, [sp, 0] ; Pickup the stack type + brne r1, 0, __tx_thread_schedule_int_ret ; Compare to solicited stack type. If not, thread was interrupted + ld blink, [sp, 4] ; Recover blink + ld fp, [sp, 8] ; Recover fp + ld gp, [sp, 12] ; Recover gp + ld r25, [sp, 16] ; Recover r25 + ld r24, [sp, 20] ; Recover r24 + ld r23, [sp, 24] ; Recover r23 + ld r22, [sp, 28] ; Recover r22 + ld r21, [sp, 32] ; Recover r21 + ld r20, [sp, 36] ; Recover r20 + ld r19, [sp, 40] ; Recover r19 + ld r18, [sp, 44] ; Recover r18 + ld r17, [sp, 48] ; Recover r17 + ld r16, [sp, 52] ; Recover r16 + ld r15, [sp, 56] ; Recover r15 + ld r14, [sp, 60] ; Recover r14 + ld r13, [sp, 64] ; Recover r13 + ld r1, [sp, 68] ; Pickup status32 + ld r30, [sp, 72] ; Recover r30 + add sp, sp, 76 ; Recover solicited stack frame + j_s.d [blink] ; Return to thread and restore flags + seti r1 ; Recover STATUS32 +; +__tx_thread_schedule_int_ret: +; + mov r0, 0x2 ; Pretend level 1 interrupt is returning + sr r0, [AUX_IRQ_ACT] ; + + .ifndef TX_DISABLE_LP + ld r0, [sp, 4] ; Recover LP_START + sr r0, [LP_START] ; Restore LP_START + ld r1, [sp, 8] ; Recover LP_END + sr r1, [LP_END] ; Restore LP_END + ld r2, [sp, 12] ; Recover LP_COUNT + mov LP_COUNT, r2 + .endif + + ld r0, [sp, 156] ; Pickup saved BTA + sr r0, [BTA] ; Recover BTA + ld blink, [sp, 16] ; Recover blink + ld ilink, [sp, 20] ; Recover ilink + ld fp, [sp, 24] ; Recover fp + ld gp, [sp, 28] ; Recover gp + ld r25, [sp, 32] ; Recover r25 + ld r24, [sp, 36] ; Recover r24 + ld r23, [sp, 40] ; Recover r23 + ld r22, [sp, 44] ; Recover r22 + ld r21, [sp, 48] ; Recover r21 + ld r20, [sp, 52] ; Recover r20 + ld r19, [sp, 56] ; Recover r19 + ld r18, [sp, 60] ; Recover r18 + ld r17, [sp, 64] ; Recover r17 + ld r16, [sp, 68] ; Recover r16 + ld r15, [sp, 72] ; Recover r15 + ld r14, [sp, 76] ; Recover r14 + ld r13, [sp, 80] ; Recover r13 + ld r12, [sp, 84] ; Recover r12 + ld r11, [sp, 88] ; Recover r11 + ld r10, [sp, 92] ; Recover r10 + ld r9, [sp, 96] ; Recover r9 + ld r8, [sp, 100] ; Recover r8 + ld r7, [sp, 104] ; Recover r7 + ld r6, [sp, 108] ; Recover r6 + ld r5, [sp, 112] ; Recover r5 + ld r4, [sp, 116] ; Recover r4 + ld r3, [sp, 120] ; Recover r3 + ld r2, [sp, 124] ; Recover r2 + ld r1, [sp, 128] ; Recover r1 + ld r0, [sp, 132] ; Recover r0 + ld r30, [sp, 136] ; Recover r30 + .ifdef TX_ENABLE_ACC + ld r58, [sp, 140] ; Recover r58 + ld r59, [sp, 144] ; Recover r59 + .endif + add sp, sp, 160 ; Recover interrupt stack frame + rtie ; Return to point of interrupt +; +;} +; + .end + diff --git a/ports/arc_hs/metaware/src/tx_thread_stack_build.s b/ports/arc_hs/metaware/src/tx_thread_stack_build.s new file mode 100644 index 00000000..4562db37 --- /dev/null +++ b/ports/arc_hs/metaware/src/tx_thread_stack_build.s @@ -0,0 +1,205 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + .equ LONG_ALIGN_MASK, 0xFFFFFFFC + .equ INT_ENABLE_BITS, 0x8000001E +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build, @function +_tx_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the ARC HS should look like the following after it is built. +; Note that the extension registers are always assigned space here. +; +; Stack Top: 1 Interrupt stack frame type +; LP_START Initial loop start +; LP_END Initial loop end +; LP_COUNT Initial loop count +; blink Initial blink value +; ilink Initial ilink (point of interrupt) +; fp (r27) Initial fp (0) +; gp Initial gp +; r25 Initial r25 +; r24 Initial r24 +; r23 Initial r23 +; r22 Initial r22 +; r21 Initial r21 +; r20 Initial r20 +; r19 Initial r19 +; r18 Initial r18 +; r17 Initial r17 +; r16 Initial r16 +; r15 Initial r15 +; r14 Initial r14 +; r13 Initial r13 +; r12 Initial r12 +; r11 Initial r11 +; r10 Initial r10 +; r9 Initial r9 +; r8 Initial r8 +; r7 Initial r7 +; r6 Initial r6 +; r5 Initial r5 +; r4 Initial r4 +; r3 Initial r3 +; r2 Initial r2 +; r1 Initial r1 +; r0 Initial r0 +; r30 Initial r30 +; r58 Initial r58 +; r59 Initial r59 +; 0 Reserved +; 0 Reserved +; 0 Initial BTA +; 0 Point of Interrupt (thread entry point) +; 0 Initial STATUS32 +; 0 Backtrace +; 0 Backtrace +; 0 Backtrace +; 0 Backtrace +; +; *: these registers will only be saved and restored if flag -Xxmac_d16 is passed to hcac +; +; Stack Bottom: (higher memory address) */ +; + ld r3, [r0, 16] ; Pickup end of stack area + and r3, r3, LONG_ALIGN_MASK ; Ensure long-word alignment + sub r3, r3, 196 ; Allocate an interrupt stack frame (ARC HS) +; +; /* Actually build the stack frame. */ +; + st 1, [r3, 0] ; Store interrupt stack type on the + ; top of the stack + mov r5, 0 ; Build initial clear value + st r5, [r3, 4] ; Store initial LP_START + st r5, [r3, 8] ; Store initial LP_END + st r5, [r3, 12] ; Store initial LP_COUNT + st r5, [r3, 16] ; Store initial blink + st r1, [r3, 20] ; Store initial ilink + st r5, [r3, 24] ; Store initial fp (0 for backtrace) + st gp, [r3, 28] ; Store current gp + st r5, [r3, 32] ; Store initial r25 + st r5, [r3, 36] ; Store initial r24 + st r5, [r3, 40] ; Store initial r23 + st r5, [r3, 44] ; Store initial r22 + st r5, [r3, 48] ; Store initial r21 + st r5, [r3, 52] ; Store initial r20 + st r5, [r3, 56] ; Store initial r19 + st r5, [r3, 60] ; Store initial r18 + st r5, [r3, 64] ; Store initial r17 + st r5, [r3, 68] ; Store initial r16 + st r5, [r3, 72] ; Store initial r15 + st r5, [r3, 76] ; Store initial r14 + st r5, [r3, 80] ; Store initial r13 + st r5, [r3, 84] ; Store initial r12 + st r5, [r3, 88] ; Store initial r11 + st r5, [r3, 92] ; Store initial r10 + st r5, [r3, 96] ; Store initial r9 + st r5, [r3, 100] ; Store initial r8 + st r5, [r3, 104] ; Store initial r7 + st r5, [r3, 108] ; Store initial r6 + st r5, [r3, 112] ; Store initial r5 + st r5, [r3, 116] ; Store initial r4 + st r5, [r3, 120] ; Store initial r3 + st r5, [r3, 124] ; Store initial r2 + st r5, [r3, 128] ; Store initial r1 + st r5, [r3, 132] ; Store initial r0 + st r5, [r3, 136] ; Store initial r30 + st r5, [r3, 140] ; Store initial r58 + st r5, [r3, 144] ; Store initial r59 + st r5, [r3, 148] ; Reserved + st r5, [r3, 152] ; Reserved + st r5, [r3, 156] ; Store initial BTA + st r1, [r3, 160] ; Store initial point of entry + lr r6, [status32] ; Pickup STATUS32 + or r6, r6, INT_ENABLE_BITS ; Make sure interrupts are enabled + st r6, [r3, 164] ; Store initial STATUS32 + st r5, [r3, 168] ; Backtrace 0 + st r5, [r3, 172] ; Backtrace 0 + st r5, [r3, 176] ; Backtrace 0 + st r5, [r3, 180] ; Backtrace 0 +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r3; +; + j_s.d [blink] ; Return to caller + st r3, [r0, 8] ; Save stack pointer in thread's + ; control block +;} + .end + + diff --git a/ports/arc_hs/metaware/src/tx_thread_system_return.s b/ports/arc_hs/metaware/src/tx_thread_system_return.s new file mode 100644 index 00000000..7d661965 --- /dev/null +++ b/ports/arc_hs/metaware/src/tx_thread_system_return.s @@ -0,0 +1,169 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + .global _tx_thread_system_return + .type _tx_thread_system_return, @function +_tx_thread_system_return: +; +; /* Save minimal context on the stack. */ +; +; /* Lockout interrupts. */ +; + clri r2 ; Disable interrupts + ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread ptr + lr r3, [status32] ; Pickup the status32 register + lsr r4, r3, 16 ; Move the register bank bits down + and r4, r4, 7 ; Isolate the register bank + breq r4, 0, __tx_software_context ; If register bank 0, software context is present + sub sp, sp, 12 ; Build small stack frame + mov r4, 2 ; Build solicited hardward stack frame type + st r4, [sp, 0] ; Set stack frame type + st r3, [sp, 4] ; Save status32 + st r2, [sp, 8] ; Save interrupt posture + st sp, [r0, 8] ; Save thread's stack pointer + bclr r3, r3, 16 ; Build register bank 0 value + bclr r3, r3, 17 ; + bclr r3, r3, 18 ; + kflag r3 ; Move back to register bank 0 + ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread ptr + b.d __tx_save_done + mov r3, 0 ; Build clear value +__tx_software_context: + sub sp, sp, 76 ; Allocate a solicited stack frame + mov r3, 0 ; Build a solicited stack type + st r3, [sp, 0] ; Store stack type on the top + st blink, [sp, 4] ; Save return address and flags + st fp, [sp, 8] ; Save fp + st r26, [sp, 12] ; Save r26 + st r25, [sp, 16] ; Save r25 + st r24, [sp, 20] ; Save r24 + st r23, [sp, 24] ; Save r23 + st r22, [sp, 28] ; Save r22 + st r21, [sp, 32] ; Save r21 + st r20, [sp, 36] ; Save r20 + st r19, [sp, 40] ; Save r19 + st r18, [sp, 44] ; Save r18 + st r17, [sp, 48] ; Save r17 + st r16, [sp, 52] ; Save r16 + st r15, [sp, 56] ; Save r15 + st r14, [sp, 60] ; Save r14 + st r13, [sp, 64] ; Save r13 + st r2, [sp, 68] ; Save status32 + st r30, [sp, 72] ; Save r30 + st sp, [r0, 8] ; Save thread's stack pointer +__tx_save_done: +; + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + ld sp, [gp, _tx_thread_system_stack_ptr@sda] ; Switch to system stack + bl.d _tx_execution_thread_exit ; Call the thread exit function + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space + ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread ptr + mov r3, 0 ; Build clear value + .endif +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + ld r5, [gp, _tx_timer_time_slice@sda] ; Pickup current time-slice + breq r5, 0, __tx_thread_dont_save_ts ; If not, skip save processing +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + st r3, [gp, _tx_timer_time_slice@sda] ; Clear time-slice variable + st r5, [r0, 24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts: +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + b.d _tx_thread_schedule ; Return to scheduler.. + st r3, [gp, _tx_thread_current_ptr@sda] ; ..clearing current thread pointer +; +;} + .end + + diff --git a/ports/arc_hs/metaware/src/tx_timer_interrupt.s b/ports/arc_hs/metaware/src/tx_timer_interrupt.s new file mode 100644 index 00000000..4edc1aa4 --- /dev/null +++ b/ports/arc_hs/metaware/src/tx_timer_interrupt.s @@ -0,0 +1,238 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Process timer expiration */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_context_save Save interrupt context */ +;/* _tx_thread_context_restore Restore interrupt context */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt, @function +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed the interrupt stack frame has +; already been allocated and registers r0, r1, and r2 have already been saved +; at offsets 0, 4, and 8 respectively. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + clri ; Lockout interrupts + ld r0, [gp,_tx_timer_system_clock@sda] ; Pickup current system clock + ld r2, [gp, _tx_timer_time_slice@sda] ; Pickup current time-slice + add r0, r0, 1 ; Increment the system clock + st r0, [gp,_tx_timer_system_clock@sda] ; Store system clock back in memory + +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + mov r1, 0 ; Clear expiration flag + breq r2, 0, __tx_timer_no_time_slice ; If zero, no time-slice is active +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + sub r2, r2, 1 ; Decrement time-slice + st r2, [gp, _tx_timer_time_slice@sda] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + brne r2, 0, __tx_timer_no_time_slice ; If non-zero, skip over expiration +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + mov r1, 1 ; Set register flag + st r1, [gp, _tx_timer_expired_time_slice@sda] ; Set the time-slice expired flag + +; +; } +; +__tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + ld r0, [gp, _tx_timer_current_ptr@sda] ; Pickup current timer pointer + ld r2, [r0, 0] ; Pickup examine actual list entry + breq r2, 0, __tx_timer_no_timer ; + ; If NULL, no timer has expired, just move to the next entry +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + mov r1, 1 ; Build expiration value + b.d __tx_timer_done ; Skip moving the timer pointer + st r1, [gp, _tx_timer_expired@sda] ; Set the expired value +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ld r2, [gp, _tx_timer_list_end@sda] ; Pickup end of list + add r0, r0, 4 ; Move to next timer entry +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + st r0, [gp, _tx_timer_current_ptr@sda] ; Store the current timer + brne r0, r2, __tx_timer_skip_wrap ; If not equal, don't wrap the list +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + ld r2, [gp, _tx_timer_list_start@sda] ; Pickup start of timer list + st r2, [gp, _tx_timer_current_ptr@sda] ; Set current timer to the start +; +__tx_timer_skip_wrap: +; +; } +; +__tx_timer_done: +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + breq r1, 0, __tx_timer_nothing_expired ; If 0, nothing has expired +; +__tx_something_expired: +; + ld r0, [sp, 0] ; Recover r0 + ld r1, [sp, 4] ; Recover r1 + ld r2, [sp, 8] ; Recover r2 + st blink, [sp, 16] ; Save blink + bl _tx_thread_context_save ; Save interrupted context +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + ld r2, [gp, _tx_timer_expired@sda] ; Pickup timer expired flag + ld r4, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable + breq r2, 0, __tx_timer_dont_activate ; If not set, skip expiration processing +; +; /* Process the timer expiration. */ +; /* _tx_timer_expiration_process(); */ + bl.d _tx_timer_expiration_process ; Call the timer expiration handling routine + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space +; +; } +__tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + ld r2, [gp, _tx_timer_expired_time_slice@sda] ; Pickup expired time-slice flag + breq r2, 0, __tx_timer_not_ts_expiration ; If not set, skip time-slice +; +; /* Time slice interrupted thread. */ +; /* _tx_thread_time_slice(); */ + + bl.d _tx_thread_time_slice ; Call time-slice processing + sub sp, sp, 16 ; ..allocating some stack space + add sp, sp, 16 ; Recover stack space +; +; } +; +__tx_timer_not_ts_expiration: +; + st 0, [gp, _tx_timer_expired_time_slice@sda] + b _tx_thread_context_restore ; Go restore interrupt context.. + ; ..clearing time-slice expired flag + ; Note that we don't return from + ; this function. +; +; } +; +__tx_timer_nothing_expired: +; + ld r0, [sp, 0] ; Recover r0 + ld r1, [sp, 4] ; Recover r1 + ld r2, [sp, 8] ; Recover r2 + add sp, sp, 160 ; Recover interrupt stack frame + rtie ; Return to point of interrupt +; +;} + .end + diff --git a/ports/arm9/ac5/example_build/build_threadx.bat b/ports/arm9/ac5/example_build/build_threadx.bat new file mode 100644 index 00000000..196340df --- /dev/null +++ b/ports/arm9/ac5/example_build/build_threadx.bat @@ -0,0 +1,238 @@ +del tx.a +armasm -g --cpu ARM9TDMI --apcs /interwork tx_initialize_low_level.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_stack_build.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_schedule.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_system_return.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_context_save.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_context_restore.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_interrupt_control.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_timer_interrupt.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_interrupt_disable.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_interrupt_restore.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_fiq_context_save.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_fiq_nesting_start.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_irq_nesting_start.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_irq_nesting_end.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_fiq_nesting_end.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_fiq_context_restore.s +armasm -g --cpu ARM9TDMI --apcs /interwork ../src/tx_thread_vectored_context_save.s +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +armcc -c -g -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +armar -r tx.a tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_start.o tx_thread_irq_nesting_start.o tx_thread_irq_nesting_end.o +armar -r tx.a tx_thread_fiq_nesting_end.o tx_thread_fiq_context_restore.o tx_thread_vectored_context_save.o tx_initialize_low_level.o +armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/arm9/ac5/example_build/build_threadx_sample.bat b/ports/arm9/ac5/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..3fcb0856 --- /dev/null +++ b/ports/arm9/ac5/example_build/build_threadx_sample.bat @@ -0,0 +1,4 @@ +armasm -g --cpu ARM9TDMI --apcs /interwork tx_initialize_low_level.s +armcc -g -c -O2 --cpu ARM9TDMI --apcs /interwork -I../../../../common/inc -I../inc sample_threadx.c +armlink -d -o sample_threadx.axf --elf --ro 0 --first tx_initialize_low_level.o(Init) --remove --map --symbols --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a + diff --git a/ports/arm9/ac5/example_build/sample_threadx.c b/ports/arm9/ac5/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/arm9/ac5/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/arm9/ac5/example_build/tx_initialize_low_level.s b/ports/arm9/ac5/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..0aa438f5 --- /dev/null +++ b/ports/arm9/ac5/example_build/tx_initialize_low_level.s @@ -0,0 +1,444 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE EQU 0xD3 ; Disable IRQ/FIQ SVC mode +IRQ_MODE EQU 0xD2 ; Disable IRQ/FIQ IRQ mode +FIQ_MODE EQU 0xD1 ; Disable IRQ/FIQ FIQ mode +SYS_MODE EQU 0xDF ; Disable IRQ/FIQ SYS mode +HEAP_SIZE EQU 4096 ; Heap size +FIQ_STACK_SIZE EQU 512 ; FIQ stack size +SYS_STACK_SIZE EQU 1024 ; SYS stack size (used for nested interrupts) +IRQ_STACK_SIZE EQU 1024 ; IRQ stack size +; +; +;/* ARM9 ARMulator Timer and Interrupt controller information. This depends on +; the ARMulator's Interrupt Controller and Timer being enabled in the default.ami. +; In addition, the addresses must match those specified in the peripherals.ami file. +; Please refer to section 2.10 and 4.16 of the Debug Target Guide, version 1.2. */ +; +IRQStatus EQU 0x0a000000 ; IRQ Status Register +IRQRawStatus EQU 0x0a000004 ; IRQ Raw Status Register +IRQEnable EQU 0x0a000008 ; IRQ Enable Set Register +IRQEnableClear EQU 0x0a00000C ; IRQ Enable Clear Register +IRQSoft EQU 0x0a000010 ; IRQ Soft +FIQStatus EQU 0x0a000100 ; FIQ Status Register +FIQRawStatus EQU 0x0a000104 ; FIQ Raw Status Register +FIQEnable EQU 0x0a000108 ; FIQ Enable Set Register +FIQEnableClear EQU 0x0a00010C ; FIQ Enable Clear Register + +TIMER1_BIT EQU 0x00000010 ; IRQ/FIQ Timer1 bit +TIMER2_BIT EQU 0x00000020 ; IRQ/FIQ Timer2 bit + +Timer1Load EQU 0x0a800000 ; Timer1 Load Register +Timer1Value EQU 0x0a800004 ; Timer1 Value Register +Timer1Control EQU 0x0a800008 ; Timer1 Control Register +Timer1Clear EQU 0x0a80000C ; Timer1 Clear Register + +Timer1Mode EQU 0x000000C0 ; Timer1 Control Value, Timer enable, periodic, no prescaler +Timer1Period EQU 0x0000FFFF ; Timer1 count-down period, maximum value + +Timer2Load EQU 0x0a800020 ; Timer2 Load Register +Timer2Value EQU 0x0a800024 ; Timer2 Value Register +Timer2Control EQU 0x0a800028 ; Timer2 Control Register +Timer2Clear EQU 0x0a80002C ; Timer2 Clear Register +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IF :DEF:TX_ENABLE_FIQ_SUPPORT + IMPORT _tx_thread_fiq_context_save + IMPORT _tx_thread_fiq_context_restore + ENDIF + IF :DEF:TX_ENABLE_IRQ_NESTING + IMPORT _tx_thread_irq_nesting_start + IMPORT _tx_thread_irq_nesting_end + ENDIF + IF :DEF:TX_ENABLE_FIQ_NESTING + IMPORT _tx_thread_fiq_nesting_start + IMPORT _tx_thread_fiq_nesting_end + ENDIF + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT _tx_version_id + IMPORT _tx_build_options + IMPORT |Image$$ZI$$Limit| +; +; + AREA Init, CODE, READONLY +; +;/* Define the ARM9 vector area. This should be located or copied to 0. */ +; + EXPORT __vectors +__vectors + LDR pc,=__main ; Reset goes to startup function + LDR pc,=__tx_undefined ; Undefined handler + LDR pc,=__tx_swi_interrupt ; Software interrupt handler + LDR pc,=__tx_prefetch_handler ; Prefetch exception handler + LDR pc,=__tx_abort_handler ; Abort exception handler + LDR pc,=__tx_reserved_handler ; Reserved exception handler + LDR pc,=__tx_irq_handler ; IRQ interrupt handler + LDR pc,=__tx_fiq_handler ; FIQ interrupt handler +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; +; /****** NOTE ****** We must be in SVC MODE at this point. Some monitors +; enter this routine in USER mode and require a software interrupt to +; change into SVC mode. */ +; + LDR r1, =|Image$$ZI$$Limit| ; Get end of non-initialized RAM area + LDR r2, =HEAP_SIZE ; Pickup the heap size + ADD r1, r2, r1 ; Setup heap limit + ADD r1, r1, #4 ; Setup stack limit +; + IF :DEF:TX_ENABLE_IRQ_NESTING +; /* Setup the system mode stack for nested interrupt support */ + LDR r2, =SYS_STACK_SIZE ; Pickup stack size + MOV r3, #SYS_MODE ; Build SYS mode CPSR + MSR CPSR_cxsf, r3 ; Enter SYS mode + ADD r1, r1, r2 ; Calculate start of SYS stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup SYS stack pointer + ENDIF +; + LDR r2, =FIQ_STACK_SIZE ; Pickup stack size + MOV r0, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_c, r0 ; Enter FIQ mode + ADD r1, r1, r2 ; Calculate start of FIQ stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup FIQ stack pointer + MOV sl, #0 ; Clear sl + MOV fp, #0 ; Clear fp + LDR r2, =IRQ_STACK_SIZE ; Pickup IRQ (system stack size) + MOV r0, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Enter IRQ mode + ADD r1, r1, r2 ; Calculate start of IRQ stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup IRQ stack pointer + MOV r0, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r0 ; Enter SVC mode + LDR r3, =_tx_thread_system_stack_ptr ; Pickup stack pointer + STR r1, [r3, #0] ; Save the system stack +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; + LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr + LDR r0, [r1, #0] ; Pickup system stack + ADD r0, r0, #4 ; Increment to next free word +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) |Image$$ZI$$Limit| + HEAP + [SYS_STACK] + FIQ_STACK + IRQ_STACK; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Setup ARMulator Timer1 for periodic interrupts. */ +; + LDR r0,=IRQEnable ; Build address of IRQ enable register + LDR r1,=TIMER1_BIT ; Build value of Timer1 IRQ enable + STR r1,[r0] ; Enable IRQ interrupts for Timer1 + + LDR r0,=Timer1Load ; Build address of Timer1 load register + LDR r1,=Timer1Period ; Build Timer1 periodic value + STR r1,[r0] ; Set Timer1 load value + + LDR r0,=Timer1Control ; Build address of Timer1 control register + LDR r1,=Timer1Mode ; Build Timer1 control value + STR r1,[r0] ; Enable Timer1 +; +; /* Done, return to caller. */ +; + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; +; +;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This +; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; (optionally SYS) stack areas. */ +; + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR r0, =|Image$$ZI$$Limit| ; Get end of non-initialized RAM area + LDR r2, =HEAP_SIZE ; Pickup the heap size + ADD r2, r2, r0 ; Setup heap limit + ADD r3, r2, #4 ; Setup stack limit + MOV r1, r3 ; Setup start of stack + IF :DEF:TX_ENABLE_IRQ_NESTING + LDR r12, =SYS_STACK_SIZE ; Pickup IRQ system stack + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + ENDIF + LDR r12, =FIQ_STACK_SIZE ; Pickup FIQ stack size + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + LDR r12, =IRQ_STACK_SIZE ; Pickup IRQ system stack + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; +;/* Define shells for each of the interrupt vectors. */ +; + EXPORT __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + EXPORT __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt ; Software interrupt handler +; + EXPORT __tx_prefetch_handler +__tx_prefetch_handler + B __tx_prefetch_handler ; Prefetch exception handler +; + EXPORT __tx_abort_handler +__tx_abort_handler + B __tx_abort_handler ; Abort exception handler +; + EXPORT __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; +; + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; +; /* Check for Timer1 interrupts on the ARMulator. */ + + LDR r1,=IRQStatus ; Pickup address of IRQStatus register + LDR r2, [r1] ; Read IRQStatus + LDR r0,=TIMER1_BIT ; Pickup Timer1 interrupt present bit + AND r2, r2, r0 ; Is this a timer interrupt? + CMP r2, r0 ; + BNE _tx_not_timer_interrupt ; If 0, not a timer interrupt + + LDR r1,=Timer1Clear ; Build address of Timer1 clear register + MOV r0,#0 ; + STR r0, [r1] ; Clear timer 0 interrupt + + BL _tx_timer_interrupt ; Timer interrupt handler +_tx_not_timer_interrupt +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ + IF :DEF:TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start + ENDIF +; +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ + IF :DEF:TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end + ENDIF +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; + EXPORT __tx_example_vectored_irq_handler +__tx_example_vectored_irq_handler +; +; +; /* Save initial context and call context save to prepare for +; vectored ISR execution. */ +; +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers +; BL _tx_thread_vectored_context_save ; Vectored context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +; IF :DEF:TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +; ENDIF +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +; IF :DEF:TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +; ENDIF +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ + IF :DEF:TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start + ENDIF +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ + IF :DEF:TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end + ENDIF +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; + ELSE + EXPORT __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler + ENDIF +; +; /* Reference build options and version ID to ensure they come in. */ +; + LDR r2, =_tx_build_options ; Pickup build options variable address + LDR r0, [r2, #0] ; Pickup build options content + LDR r2, =_tx_version_id ; Pickup version ID variable address + LDR r0, [r2, #0] ; Pickup version ID content +; +; + END + diff --git a/ports/arm9/ac5/inc/tx_port.h b/ports/arm9/ac5/inc/tx_port.h new file mode 100644 index 00000000..eb445bef --- /dev/null +++ b/ports/arm9/ac5/inc/tx_port.h @@ -0,0 +1,329 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARM9/AC5 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (ULONG) __clz((unsigned int) m); \ + b = 31 - b; +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifndef __thumb +#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; + +#ifdef TX_ENABLE_FIQ_SUPPORT + +/* IRQ and FIQ support. */ + +#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); \ + __disable_fiq(); + +#define TX_RESTORE if (!interrupt_save_disabled) \ + { \ + __enable_irq(); \ + __enable_fiq(); \ + } + +#else + +#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); + +#define TX_RESTORE if (!interrupt_save_disabled) \ + { \ + __enable_irq(); \ + } +#endif + +#else + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/AC5 Version 6.0 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/arm9/ac5/readme_threadx.txt b/ports/arm9/ac5/readme_threadx.txt new file mode 100644 index 00000000..3fab29c2 --- /dev/null +++ b/ports/arm9/ac5/readme_threadx.txt @@ -0,0 +1,518 @@ + Microsoft's Azure RTOS ThreadX for ARM9 + + Thumb & 32-bit Mode + + Using ARM Compiler 5 (AC5) + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +AC5 development environment. At this point you may run the build_threadx.bat +batch file. This will build the ThreadX run-time environment in the +"example_build" directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the ARM +Windows-based simulator. + +Building the demonstration is easy; simply execute the build_threadx_demo.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf +is a binary file that can be downloaded and executed on the ARM simulator. + + +3. System Initialization + +The entry point in ThreadX for the ARM9 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning +of the Init area should be copied to address 0. + +This is also where initialization of a periodic timer interrupt source +should take place. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Assembler / Compiler Switches + +The following are compiler switches used in building the demonstration +system: + +Compiler Switch Meaning + + -g Specifies debug information + -c Specifies object code generation + --cpu ARM9TDMI Specifies ARM9TDMI instruction set + --apcs /interwork Specifies Thumb/32-bit compatibility + +Linker Switch Meaning + + -d Specifies to retain debug information in output file + -o demo.axf Specifies demo output file name + --elf Specifies elf output file format + --ro Specifies that Read-Only memory starts at address 0 + --first tx_initialize_low_level.o(Init) + Specifies that the first area loaded is Init + --remove Remove unused areas + --list Specifies map file name + --symbols Specifies symbols for map file + --map Creates a map file + +Application Defines + + --PD "TX_ENABLE_FIQ_SUPPORT SETL {TRUE}" This assembler define enables FIQ + interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}" This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. + --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}" This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. In addition, + IRQ nesting should also be enabled. + -DTX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ + interrupt handling in the ThreadX + generic C source. This define + should also be used in conjunction + with the corresponding assembler + define. + -DTX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + -DTX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + + +5. Register Usage and Stack Frames + +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for ARM9 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The ARM9 vectors start at address zero. The demonstration system startup +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save ; Jump to the context save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call(s) go here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + EXPORT __tx_irq_example_handler +__tx_irq_example_handler +; +; /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers + BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, +calling the _tx_thread_irq_nesting_end service disables nesting by disabling +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* Enable nested IRQ interrupts. NOTE: Since this service returns +; with IRQ interrupts enabled, all IRQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +; +; /* Application ISR call(s) go here! */ +; +; /* Disable nested IRQ interrupts. The mode is switched back to +; IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, ARM9 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ handlers can be called here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ handlers can be called here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.s in the Integrator sub-directories. + + +9. Thumb/ARM9 Mixed Mode + +By default, ThreadX is setup for running in ARM9 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be built +in 32-bit mode. In addition, if any Thumb code is used the entire ThreadX source- +both C and assembly - should be built with the "-apcs /interwork" option. + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for ARM9 using AC5 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/arm9/ac5/src/tx_thread_context_restore.s b/ports/arm9/ac5/src/tx_thread_context_restore.s new file mode 100644 index 00000000..1e5f4566 --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_context_restore.s @@ -0,0 +1,247 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +IRQ_MODE EQU 0xD2 ; IRQ mode +SVC_MODE EQU 0xD3 ; SVC mode + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +THUMB_MASK EQU 0x20 ; Thumb bit mask +SVC_MODE_BITS EQU 0x13 ; SVC mode value +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + MRS r3, CPSR ; Pickup current CPSR + ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value + MSR CPSR_cxsf, r0 ; Lockout interrupts + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block + BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS ; Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 ; Lockout interrupts +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r3, r3, #MODE_MASK ; Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +;} +; + END + diff --git a/ports/arm9/ac5/src/tx_thread_context_save.s b/ports/arm9/ac5/src/tx_thread_context_save.s new file mode 100644 index 00000000..07efa1a6 --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_context_save.s @@ -0,0 +1,207 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; IRQ & FIQ interrupts disabled + ELSE +DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled + ENDIF + + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_irq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + IF :DEF:TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r0 ; Disable interrupts + ENDIF + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + END + diff --git a/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s b/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..5cd93433 --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,259 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE EQU 0xD3 ; SVC mode +FIQ_MODE EQU 0xD1 ; FIQ mode + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +THUMB_MASK EQU 0x20 ; Thumb bit mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +SVC_MODE_BITS EQU 0x13 ; SVC mode value +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + EXPORT _tx_thread_fiq_context_restore +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + MRS r3, CPSR ; Pickup current CPSR + ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value + MSR CPSR_cxsf, r0 ; Lockout interrupts + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_cxsf, r2 ; Re-enter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block */ + BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS ; Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 ; Lockout interrupts +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MRS r3, CPSR ; Pickup current CPSR + BIC r3, r3, #MODE_MASK ; Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +; +;} +; + END + diff --git a/ports/arm9/ac5/src/tx_thread_fiq_context_save.s b/ports/arm9/ac5/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..941ae79b --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_fiq_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_fiq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + EXPORT _tx_thread_fiq_context_save +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} +; + END + diff --git a/ports/arm9/ac5/src/tx_thread_fiq_nesting_end.s b/ports/arm9/ac5/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..87d9bcc1 --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,111 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + EXPORT _tx_thread_fiq_nesting_end +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_cxsf, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_cxsf, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/arm9/ac5/src/tx_thread_fiq_nesting_start.s b/ports/arm9/ac5/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..f06e9ec2 --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +FIQ_DISABLE EQU 0x40 ; FIQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + EXPORT _tx_thread_fiq_nesting_start +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/arm9/ac5/src/tx_thread_interrupt_control.s b/ports/arm9/ac5/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..c21d687d --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_interrupt_control.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +INT_MASK EQU 0xC0 ; Interrupt bit mask + ELSE +INT_MASK EQU 0x80 ; Interrupt bit mask + ENDIF +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} +; + END + diff --git a/ports/arm9/ac5/src/tx_thread_interrupt_disable.s b/ports/arm9/ac5/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..efe72d25 --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_interrupt_disable.s @@ -0,0 +1,98 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; IRQ & FIQ interrupts disabled + ELSE +DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled + ENDIF +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(void) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + ORR r1, r0, #DISABLE_INTS ; Mask interrupts + MSR CPSR_cxsf, r1 ; Setup new CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/arm9/ac5/src/tx_thread_interrupt_restore.s b/ports/arm9/ac5/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..eac71e91 --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_restore(UINT old_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r0 ; Setup new CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/arm9/ac5/src/tx_thread_irq_nesting_end.s b/ports/arm9/ac5/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..a1bd87ed --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + EXPORT _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_cxsf, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_cxsf, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} + END + diff --git a/ports/arm9/ac5/src/tx_thread_irq_nesting_start.s b/ports/arm9/ac5/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..1fc8b2dd --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +IRQ_DISABLE EQU 0x80 ; IRQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + EXPORT _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/arm9/ac5/src/tx_thread_schedule.s b/ports/arm9/ac5/src/tx_thread_schedule.s new file mode 100644 index 00000000..fa1eef18 --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_schedule.s @@ -0,0 +1,172 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask + ELSE +ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask + ENDIF +; +; + IMPORT _tx_thread_execute_ptr + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + MRS r2, CPSR ; Pickup CPSR + BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s) + MSR CPSR_cxsf, r0 ; Enable interrupts +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + MSR CPSR_cxsf, r2 ; Disable interrupts +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ; variable + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + BL _tx_execution_thread_enter ; Call the thread execution enter function + ENDIF +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r0, r1} ; Pickup the stack type and saved CPSR + CMP r0, #0 ; Check for synchronous context switch + MSRNE SPSR_cxsf, r1 ; Setup SPSR for return + LDMNEIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously + MSR CPSR_cxsf, r1 ; Recover CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} +; + END + diff --git a/ports/arm9/ac5/src/tx_thread_stack_build.s b/ports/arm9/ac5/src/tx_thread_stack_build.s new file mode 100644 index 00000000..2da5649c --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_stack_build.s @@ -0,0 +1,156 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE EQU 0x13 ; SVC mode + IF :DEF:TX_ENABLE_FIQ_SUPPORT +CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled + ELSE +CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled + ENDIF +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the ARM9 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + MRS r1, CPSR ; Pickup CPSR + BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} + END + diff --git a/ports/arm9/ac5/src/tx_thread_system_return.s b/ports/arm9/ac5/src/tx_thread_system_return.s new file mode 100644 index 00000000..697085a3 --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_system_return.s @@ -0,0 +1,150 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; IRQ & FIQ interrupts disabled + ELSE +DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled + ENDIF +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Save minimal context on the stack. */ +; + MOV r0, #0 ; Build a solicited stack type + MRS r1, CPSR ; Pickup the CPSR + STMDB sp!, {r0-r1, r4-r11, lr} ; Save minimal context +; +; /* Lockout interrupts. */ +; + ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r2 ; Disable interrupts + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function + ENDIF + + LDR r3, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r0, [r3, #0] ; Pickup current thread pointer + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r0, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r0, #24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r3, #0] ; Clear current thread pointer + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports/arm9/ac5/src/tx_thread_vectored_context_save.s b/ports/arm9/ac5/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..c5e1e9f8 --- /dev/null +++ b/ports/arm9/ac5/src/tx_thread_vectored_context_save.s @@ -0,0 +1,209 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; IRQ & FIQ interrupts disabled + ELSE +DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled + ENDIF +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + EXPORT _tx_thread_vectored_context_save +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r0 ; Disable interrupts + ENDIF + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + ADD sp, sp, #32 ; Recover saved registers + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +;} +; + END + diff --git a/ports/arm9/ac5/src/tx_timer_interrupt.s b/ports/arm9/ac5/src/tx_timer_interrupt.s new file mode 100644 index 00000000..7997d994 --- /dev/null +++ b/ports/arm9/ac5/src/tx_timer_interrupt.s @@ -0,0 +1,258 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt ARM9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} + END + diff --git a/ports/arm9/gnu/example_build/build_threadx.bat b/ports/arm9/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..47617c67 --- /dev/null +++ b/ports/arm9/gnu/example_build/build_threadx.bat @@ -0,0 +1,238 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=arm9 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_interrupt_disable.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_interrupt_restore.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_fiq_context_save.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_fiq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_irq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_irq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_fiq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_fiq_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=arm9 ../src/tx_thread_vectored_context_save.S +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_start.o tx_thread_irq_nesting_start.o tx_thread_irq_nesting_end.o +arm-none-eabi-ar -r tx.a tx_thread_fiq_nesting_end.o tx_thread_fiq_context_restore.o tx_thread_vectored_context_save.o tx_initialize_low_level.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/arm9/gnu/example_build/build_threadx_sample.bat b/ports/arm9/gnu/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..c35d2bc6 --- /dev/null +++ b/ports/arm9/gnu/example_build/build_threadx_sample.bat @@ -0,0 +1,6 @@ +arm-none-eabi-gcc -c -g -mcpu=arm9 reset.S +arm-none-eabi-gcc -c -g -mcpu=arm9 crt0.S +arm-none-eabi-gcc -c -g -mcpu=arm9 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=arm9 -I../../../../common/inc -I../inc sample_threadx.c +arm-none-eabi-ld -A arm9 -T sample_threadx.ld reset.o crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libc.a libgcc.a -o sample_threadx.out -M > sample_threadx.map + diff --git a/ports/arm9/gnu/example_build/crt0.S b/ports/arm9/gnu/example_build/crt0.S new file mode 100644 index 00000000..aa0f3239 --- /dev/null +++ b/ports/arm9/gnu/example_build/crt0.S @@ -0,0 +1,90 @@ + +/* .text is used instead of .section .text so it works with arm-aout too. */ + .text + .code 32 + .align 0 + + .global _mainCRTStartup + .global _start + .global start +start: +_start: +_mainCRTStartup: + +/* Start by setting up a stack */ + /* Set up the stack pointer to a fixed value */ + ldr r3, .LC0 + mov sp, r3 + /* Setup a default stack-limit in case the code has been + compiled with "-mapcs-stack-check". Hard-wiring this value + is not ideal, since there is currently no support for + checking that the heap and stack have not collided, or that + this default 64k is enough for the program being executed. + However, it ensures that this simple crt0 world will not + immediately cause an overflow event: */ + sub sl, sp, #64 << 10 /* Still assumes 256bytes below sl */ + mov a2, #0 /* Second arg: fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr a1, .LC1 /* First arg: start of memory block */ + ldr a3, .LC2 + sub a3, a3, a1 /* Third arg: length of block */ + + + + bl memset + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ +#ifdef __USES_INITFINI__ + /* Some arm/elf targets use the .init and .fini sections + to create constructors and destructors, and for these + targets we need to call the _init function and arrange + for _fini to be called at program exit. */ + mov r4, r0 + mov r5, r1 +/* ldr r0, .Lfini */ + bl atexit +/* bl init */ + mov r0, r4 + mov r1, r5 +#endif + bl main + + bl exit /* Should not return. */ + + + /* For Thumb, constants must be after the code since only + positive offsets are supported for PC relative addresses. */ + + .align 0 +.LC0: +.LC1: + .word __bss_start__ +.LC2: + .word __bss_end__ +/* +#ifdef __USES_INITFINI__ +.Lfini: + .word _fini +#endif */ + /* Return ... */ +#ifdef __APCS_26__ + movs pc, lr +#else +#ifdef __THUMB_INTERWORK + bx lr +#else + mov pc, lr +#endif +#endif + + +/* Workspace for Angel calls. */ + .data +/* Data returned by monitor SWI. */ +.global __stack_base__ +HeapBase: .word 0 +HeapLimit: .word 0 +__stack_base__: .word 0 +StackLimit: .word 0 diff --git a/ports/arm9/gnu/example_build/libgcc.a b/ports/arm9/gnu/example_build/libgcc.a new file mode 100644 index 0000000000000000000000000000000000000000..d735349678a569441a4c7c45d9ce62d9b9b783e0 GIT binary patch literal 260152 zcmeFa3!EIqbuL~#J^Mgfq*<*1S(fct5JrHcon5VjAOx?3cv^zAcgu1GaBo}Eml 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zyyk;0u~c5dm1R37av%P?23us%dHPGDpFT$0GBczAKYnN6rVuiJ<@W-;X3iNSdGtC4 zZc0Al4tY)&I-P!o0#6|ykg|z--55Au=wiVt!DWKHH_4BuyvA0+F2RcgFA>}#_#GlT dhn|!HpOEmEh$!@SiRZoRqCc?z|Ecwv{|7^Je? +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef __thumb__ + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE asm volatile (" MRS %0,CPSR; ORR %1,%0,#0xC0; MSR CPSR_cxsf,%1 ": "=r" (interrupt_save), "=r" (tx_temp) ); +#else +#define TX_DISABLE asm volatile (" MRS %0,CPSR; ORR %1,%0,#0x80; MSR CPSR_cxsf,%1 ": "=r" (interrupt_save), "=r" (tx_temp) ); +#endif + +#define TX_RESTORE asm volatile (" MSR CPSR_cxsf,%0 "::"r" (interrupt_save) ); + +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/GNU Version 6.0 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/arm9/gnu/readme_threadx.txt b/ports/arm9/gnu/readme_threadx.txt new file mode 100644 index 00000000..262760e6 --- /dev/null +++ b/ports/arm9/gnu/readme_threadx.txt @@ -0,0 +1,496 @@ + Microsoft's Azure RTOS ThreadX for ARM9 + + Using the GNU Tools + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. + +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: TX.A. This file must be linked with your +application in order to use ThreadX. + + +2. Demonstration System + +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file +that can be downloaded and executed. + + +3. System Initialization + +The entry point in ThreadX for the ARM9 using GNU tools is at label _start. +This is defined within the modified version of the GNU startup code - crt0.S. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied +to address 0. + +This is also where initialization of a periodic timer interrupt source should take +place. + +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter +to your application definition function, tx_application_define. + + +4. Assembler / Compiler Switches + +The following are compiler switches used in building the demonstration +system: + +Compiler/Assembler Meaning + Switches + + -g Specifies debug information + -c Specifies object code generation + -mcpu=arm9 Specifies target cpu + +Linker Switch Meaning + + -o sample_threadx.out Specifies output file + -M > sample_threadx.map Specifies demo map file + -A arm9 Specifies target architecture + -T sample_threadx.ld Specifies the loader control file + +Application Defines ( -D option) + + TX_ENABLE_FIQ_SUPPORT This assembler define enables FIQ + interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + + TX_ENABLE_IRQ_NESTING This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.S. + + TX_ENABLE_FIQ_NESTING This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.S. In addition, + IRQ nesting should also be enabled. + + TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ + interrupt handling in the ThreadX + generic C source. This define + should also be used in conjunction + with the corresponding assembler + define. + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + +5. Register Usage and Stack Frames + +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for ARM9 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The ARM9 vectors start at address zero. The demonstration system startup +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +nested IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.S: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save @ Jump to the context save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.S: + + .global __tx_irq_example_handler +__tx_irq_example_handler: +@ +@ /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} @ Save some scratch registers + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers + BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call goes here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* Enable nested IRQ interrupts. NOTE: Since this service returns +@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Disable nested IRQ interrupts. The mode is switched back to +@ IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, ARM7 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.S. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.S: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Enable nested FIQ interrupts. NOTE: Since this service returns +@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Disable nested FIQ interrupts. The mode is switched back to +@ FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of +ThreadX will still run. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.S for the demonstration system. + + +9. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for ARM9 using GNU tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/arm9/gnu/src/tx_thread_context_restore.S b/ports/arm9/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..a6876848 --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,241 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE = 0xD3 @ Disable IRQ/FIQ, SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE = 0x93 @ Disable IRQ, SVC mode +IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode +#endif +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: +@ +@ /* Lockout interrupts. */ +@ + MOV r0, #IRQ_MODE @ Build disable interrupts CPSR + MSR CPSR, r0 @ Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_restore @ Yes, idle system was interrupted +@ + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_preempt_restore @ No, preemption needs to happen +@ +@ +__tx_thread_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_preempt_restore: +@ + LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR, r2 @ Enter IRQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR, r0 @ Enter SVC mode + B _tx_thread_schedule @ Return to scheduler +@} + + + diff --git a/ports/arm9/gnu/src/tx_thread_context_save.S b/ports/arm9/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..a1552e86 --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_context_save.S @@ -0,0 +1,210 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ IRQ & FIQ interrupts disabled +#else +DISABLE_INTS = 0x80 @ IRQ interrupts disabled +#endif +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_irq_processing_return + .global _tx_execution_isr_enter +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt CPSR + MSR CPSR_cxsf, r0 @ Disable interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} @ Store other registers +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr@ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #16 @ Recover saved registers + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@} + + + diff --git a/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S b/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S new file mode 100644 index 00000000..81e3299b --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_fiq_context_restore.S @@ -0,0 +1,256 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ +SVC_MODE = 0xD3 @ SVC mode +FIQ_MODE = 0xD1 @ FIQ mode +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +MODE_MASK = 0x1F @ Mode mask +THUMB_MASK = 0x20 @ Thumb bit mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +SVC_MODE_BITS = 0x13 @ SVC mode value +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_context_restore(VOID) +@{ + .global _tx_thread_fiq_context_restore + .type _tx_thread_fiq_context_restore,function +_tx_thread_fiq_context_restore: +@ +@ /* Lockout interrupts. */ +@ + MRS r3, CPSR @ Pickup current CPSR + ORR r0, r3, #DISABLE_INTS @ Build interrupt disable value + MSR CPSR_cxsf, r0 @ Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_fiq_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, [sp] @ Pickup the saved SPSR + MOV r2, #MODE_MASK @ Build mask to isolate the interrupted mode + AND r1, r1, r2 @ Isolate mode bits + CMP r1, #IRQ_MODE_BITS @ Was an interrupt taken in IRQ mode before we + @ got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore @ Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore @ Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_fiq_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore @ No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_fiq_preempt_restore: +@ + LDMIA sp!, {r3, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_cxsf, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR_cxsf, r2 @ Reenter FIQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_cxsf, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block */ + BIC r4, r4, #THUMB_MASK @ Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS @ Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 @ Lockout interrupts +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_fiq_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_fiq_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + ADD sp, sp, #24 @ Recover FIQ stack space + MRS r3, CPSR @ Pickup current CPSR + BIC r3, r3, #MODE_MASK @ Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS @ Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 @ Lockout interrupts + B _tx_thread_schedule @ Return to scheduler +@ +@} + diff --git a/ports/arm9/gnu/src/tx_thread_fiq_context_save.S b/ports/arm9/gnu/src/tx_thread_fiq_context_save.S new file mode 100644 index 00000000..88ad7e79 --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_fiq_context_save.S @@ -0,0 +1,204 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_fiq_processing_return + .global _tx_execution_isr_enter +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@ VOID _tx_thread_fiq_context_save(VOID) +@{ + .global _tx_thread_fiq_context_save + .type _tx_thread_fiq_context_save,function +_tx_thread_fiq_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +__tx_thread_fiq_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, lr} @ Store other registers, Note that we don't +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested +@ @ interrupt processing does need to save +@ @ these registers. +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_fiq_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif +@ +@ /* Not much to do here, save the current SPSR and LR for possible +@ use in IRQ interrupted in idle system conditions, and return to +@ FIQ interrupt processing. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, lr} @ Store other registers that will get used +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@} + diff --git a/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S b/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S new file mode 100644 index 00000000..9705cca4 --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_fiq_nesting_end.S @@ -0,0 +1,111 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +FIQ_MODE_BITS = 0x11 @ FIQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_end(VOID) +@{ + .global _tx_thread_fiq_nesting_end + .type _tx_thread_fiq_nesting_end,function +_tx_thread_fiq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_cxsf, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_cxsf, r0 @ Reenter IRQ mode + MOV pc, r3 @ Return to caller +@} + diff --git a/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S b/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S new file mode 100644 index 00000000..fd498616 --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_fiq_nesting_start.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +FIQ_DISABLE = 0x40 @ FIQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_start(VOID) +@{ + .global _tx_thread_fiq_nesting_start + .type _tx_thread_fiq_nesting_start,function +_tx_thread_fiq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_cxsf, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR + MSR CPSR_cxsf, r0 @ Enter system mode + MOV pc, r3 @ Return to caller +@} + diff --git a/ports/arm9/gnu/src/tx_thread_interrupt_control.S b/ports/arm9/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..ca95b8ac --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" */ +@ + +INT_MASK = 0x03F + +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_control +$_tx_thread_interrupt_control: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_control(UINT new_posture) +@{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r3, CPSR @ Pickup current CPSR + MOV r2, #INT_MASK @ Build interrupt mask + AND r1, r3, r2 @ Clear interrupt lockout bits + ORR r1, r1, r0 @ Or-in new interrupt lockout bits +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR, r1 @ Setup new CPSR + BIC r0, r3, r2 @ Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/arm9/gnu/src/tx_thread_interrupt_disable.S b/ports/arm9/gnu/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..76570a20 --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_interrupt_disable.S @@ -0,0 +1,116 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ IRQ & FIQ interrupts disabled +#else +DISABLE_INTS = 0x80 @ IRQ interrupts disabled +#endif +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_disable +$_tx_thread_interrupt_disable: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_disable(void) +@{ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r0, CPSR @ Pickup current CPSR +@ +@ /* Mask interrupts. */ +@ + ORR r1, r0, #DISABLE_INTS @ Mask interrupts + MSR CPSR_cxsf, r1 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/arm9/gnu/src/tx_thread_interrupt_restore.S b/ports/arm9/gnu/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..65e01e32 --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_interrupt_restore.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_restore +$_tx_thread_interrupt_restore: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring interrupts to the state */ +@/* returned by a previous _tx_thread_interrupt_disable call. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_restore(UINT old_posture) +@{ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_cxsf, r0 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S b/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..8ee9b216 --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,111 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_end(VOID) +@{ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_cxsf, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_cxsf, r0 @ Reenter IRQ mode + MOV pc, r3 @ Return to caller +@} + diff --git a/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S b/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..7174dc11 --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +IRQ_DISABLE = 0x80 @ IRQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_start(VOID) +@{ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_cxsf, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR + MSR CPSR_cxsf, r0 @ Enter system mode + MOV pc, r3 @ Return to caller +@} + diff --git a/ports/arm9/gnu/src/tx_thread_schedule.S b/ports/arm9/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..fde52ec5 --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_schedule.S @@ -0,0 +1,187 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +ENABLE_INTS = 0xC0 @ IRQ & FIQ Interrupts enabled mask +#else +ENABLE_INTS = 0x80 @ IRQ Interrupts enabled mask +#endif +@ +@ + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_execution_thread_enter +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_schedule + .type $_tx_thread_schedule,function +$_tx_thread_schedule: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_schedule @ Call _tx_thread_schedule function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: +@ +@ /* Enable interrupts. */ +@ + MRS r2, CPSR @ Pickup CPSR + BIC r0, r2, #ENABLE_INTS @ Clear the disable bit(s) + MSR CPSR_cxsf, r0 @ Enable interrupts +@ +@ /* Wait for a thread to execute. */ +@ do +@ { + LDR r1, =_tx_thread_execute_ptr @ Address of thread execute ptr +@ +__tx_thread_schedule_loop: +@ + LDR r0, [r1] @ Pickup next thread to execute + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_schedule_loop @ If so, keep looking for a thread +@ +@ } +@ while(_tx_thread_execute_ptr == TX_NULL); +@ +@ /* Yes! We have a thread to execute. Lockout interrupts and +@ transfer control to it. */ +@ + MSR CPSR_cxsf, r2 @ Disable interrupts +@ +@ /* Setup the current thread pointer. */ +@ _tx_thread_current_ptr = _tx_thread_execute_ptr; +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + STR r0, [r1] @ Setup current thread pointer +@ +@ /* Increment the run count for this thread. */ +@ _tx_thread_current_ptr -> tx_thread_run_count++; +@ + LDR r2, [r0, #4] @ Pickup run counter + LDR r3, [r0, #24] @ Pickup time-slice for this thread + ADD r2, r2, #1 @ Increment thread run-counter + STR r2, [r0, #4] @ Store the new run counter +@ +@ /* Setup time-slice, if present. */ +@ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + @ variable + LDR sp, [r0, #8] @ Switch stack pointers + STR r3, [r2] @ Setup time-slice +@ +@ /* Switch to the thread's stack. */ +@ sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + BL _tx_execution_thread_enter @ Call the thread execution enter function +#endif +@ +@ /* Determine if an interrupt frame or a synchronous task suspension frame +@ is present. */ +@ + LDMIA sp!, {r0, r1} @ Pickup the stack type and saved CPSR + CMP r0, #0 @ Check for synchronous context switch + MSRNE SPSR_cxsf, r1 @ Setup SPSR for return + LDMNEIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt + LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously + MSR CPSR_cxsf, r1 @ Recover CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ + diff --git a/ports/arm9/gnu/src/tx_thread_stack_build.S b/ports/arm9/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..7d6f47bb --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,178 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ + .arm + +SVC_MODE = 0x13 @ SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ interrupts enabled +#else +CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interrupts enabled +#endif +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_thread_stack_build + .type $_tx_thread_stack_build,function +$_tx_thread_stack_build: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_stack_build @ Call _tx_thread_stack_build function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the ARM9 should look like the following after it is built: +@ +@ Stack Top: 1 Interrupt stack frame type +@ CPSR Initial value for CPSR +@ a1 (r0) Initial value for a1 +@ a2 (r1) Initial value for a2 +@ a3 (r2) Initial value for a3 +@ a4 (r3) Initial value for a4 +@ v1 (r4) Initial value for v1 +@ v2 (r5) Initial value for v2 +@ v3 (r6) Initial value for v3 +@ v4 (r7) Initial value for v4 +@ v5 (r8) Initial value for v5 +@ sb (r9) Initial value for sb +@ sl (r10) Initial value for sl +@ fp (r11) Initial value for fp +@ ip (r12) Initial value for ip +@ lr (r14) Initial value for lr +@ pc (r15) Initial value for pc +@ 0 For stack backtracing +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #7 @ Ensure 8-byte alignment + SUB r2, r2, #76 @ Allocate space for the stack frame +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #1 @ Build interrupt stack type + STR r3, [r2, #0] @ Store stack type + MOV r3, #0 @ Build initial register value + STR r3, [r2, #8] @ Store initial r0 + STR r3, [r2, #12] @ Store initial r1 + STR r3, [r2, #16] @ Store initial r2 + STR r3, [r2, #20] @ Store initial r3 + STR r3, [r2, #24] @ Store initial r4 + STR r3, [r2, #28] @ Store initial r5 + STR r3, [r2, #32] @ Store initial r6 + STR r3, [r2, #36] @ Store initial r7 + STR r3, [r2, #40] @ Store initial r8 + STR r3, [r2, #44] @ Store initial r9 + LDR r3, [r0, #12] @ Pickup stack starting address + STR r3, [r2, #48] @ Store initial r10 (sl) + LDR r3,=_tx_thread_schedule @ Pickup address of _tx_thread_schedule for GDB backtrace + STR r3, [r2, #60] @ Store initial r14 (lr) + MOV r3, #0 @ Build initial register value + STR r3, [r2, #52] @ Store initial r11 + STR r3, [r2, #56] @ Store initial r12 + STR r1, [r2, #64] @ Store initial pc + STR r3, [r2, #68] @ 0 for back-trace + MRS r1, CPSR @ Pickup CPSR + BIC r1, r1, #CPSR_MASK @ Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] @ Store initial CPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/arm9/gnu/src/tx_thread_system_return.S b/ports/arm9/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..aa1599a6 --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_system_return.S @@ -0,0 +1,167 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ IRQ & FIQ interrupts disabled +#else +DISABLE_INTS = 0x80 @ IRQ interrupts disabled +#endif +@ +@ + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_execution_thread_exit +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_system_return + .type $_tx_thread_system_return,function +$_tx_thread_system_return: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_system_return @ Call _tx_thread_system_return function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_system_return(VOID) +@{ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: +@ +@ /* Save minimal context on the stack. */ +@ + MOV r0, #0 @ Build a solicited stack type + MRS r1, CPSR @ Pickup the CPSR + STMDB sp!, {r0-r1, r4-r11, lr} @ Save minimal context +@ +@ /* Lockout interrupts. */ +@ + ORR r2, r1, #DISABLE_INTS @ Build disable interrupt CPSR + MSR CPSR_cxsf, r2 @ Disable interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + BL _tx_execution_thread_exit @ Call the thread exit function +#endif + LDR r3, =_tx_thread_current_ptr @ Pickup address of current ptr + LDR r0, [r3] @ Pickup current thread pointer + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + LDR r1, [r2] @ Pickup current time slice +@ +@ /* Save current stack and switch to system stack. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ sp = _tx_thread_system_stack_ptr; +@ + STR sp, [r0, #8] @ Save thread stack pointer +@ +@ /* Determine if the time-slice is active. */ +@ if (_tx_timer_time_slice) +@ { +@ + MOV r4, #0 @ Build clear value + CMP r1, #0 @ Is a time-slice active? + BEQ __tx_thread_dont_save_ts @ No, don't save the time-slice +@ +@ /* Save time-slice for the thread and clear the current time-slice. */ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r4, [r2] @ Clear time-slice + STR r1, [r0, #24] @ Save current time-slice +@ +@ } +__tx_thread_dont_save_ts: +@ +@ /* Clear the current thread pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + STR r4, [r3] @ Clear current thread pointer + B _tx_thread_schedule @ Jump to scheduler! +@ +@} + diff --git a/ports/arm9/gnu/src/tx_thread_vectored_context_save.S b/ports/arm9/gnu/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..f69abcd9 --- /dev/null +++ b/ports/arm9/gnu/src/tx_thread_vectored_context_save.S @@ -0,0 +1,199 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ IRQ & FIQ interrupts disabled +#else +DISABLE_INTS = 0x80 @ IRQ interrupts disabled +#endif +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_execution_isr_enter +@ +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_vectored_context_save(VOID) +@{ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt CPSR + MSR CPSR_cxsf, r0 @ Disable interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #32 @ Recover saved registers + MOV pc, lr @ Return to caller +@ +@ } +@} + diff --git a/ports/arm9/gnu/src/tx_timer_interrupt.S b/ports/arm9/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..7871d1bc --- /dev/null +++ b/ports/arm9/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,279 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ + .arm + +@ +@/* Define Assembly language external references... */ +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_timer_interrupt + .type $_tx_timer_interrupt,function +$_tx_timer_interrupt: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_timer_interrupt @ Call _tx_timer_interrupt function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt ARM9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1] @ Pickup current timer + LDR r2, [r0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wraparound. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup address of timer list end + LDR r2, [r3] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wraparound logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup address of timer list start + LDR r0, [r3] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + LDR r2, [r3] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup address of other expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup address of expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r2, [r3] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} + diff --git a/ports/arm9/iar/example_build/azure_rtos.eww b/ports/arm9/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..17e0d329 --- /dev/null +++ b/ports/arm9/iar/example_build/azure_rtos.eww @@ -0,0 +1,13 @@ + + + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\tx.ewp + + + + + diff --git a/ports/arm9/iar/example_build/cstartup.s b/ports/arm9/iar/example_build/cstartup.s new file mode 100644 index 00000000..b95efc0e --- /dev/null +++ b/ports/arm9/iar/example_build/cstartup.s @@ -0,0 +1,161 @@ + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 14520 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector + PUBLIC __vector_0x14 + PUBLIC __iar_program_start + EXTERN __tx_undefined + EXTERN __tx_swi_interrupt + EXTERN __tx_prefetch_handler + EXTERN __tx_abort_handler + EXTERN __tx_irq_handler + EXTERN __tx_fiq_handler + + ARM +__vector: + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort +__vector_0x14: + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + +Reset_Addr: DCD __iar_program_start +Undefined_Addr: DCD __tx_undefined +SWI_Addr: DCD __tx_swi_interrupt +Prefetch_Addr: DCD __tx_prefetch_handler +Abort_Addr: DCD __tx_abort_handler +IRQ_Addr: DCD __tx_irq_handler +FIQ_Addr: DCD __tx_fiq_handler + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reser execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + +; PUBLIC ?cstartup + EXTERN ?main + REQUIRE __vector + + ARM + +__iar_program_start: +?cstartup: + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR + +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + + + MRS r0, cpsr ; Original PSR value + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + +#ifdef __ARMVFP__ + ;; Enable the VFP coprocessor. + + MOV r0, #0x40000000 ; Set EN bit in VFP + FMXR fpexc, r0 ; FPEXC, clear others. + +; +; Disable underflow exceptions by setting flush to zero mode. +; For full IEEE 754 underflow compliance this code should be removed +; and the appropriate exception handler installed. +; + + MOV r0, #0x01000000 ; Set FZ bit in VFP + FMXR fpscr, r0 ; FPSCR, clear others. +#endif + +; +; Add more initialization here +; + +; Continue to ?main for C-level initialization. + + B ?main + + END + + + diff --git a/ports/arm9/iar/example_build/sample_threadx.c b/ports/arm9/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..68cd97fe --- /dev/null +++ b/ports/arm9/iar/example_build/sample_threadx.c @@ -0,0 +1,374 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define byte pool memory. */ + +UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/arm9/iar/example_build/sample_threadx.dep b/ports/arm9/iar/example_build/sample_threadx.dep new file mode 100644 index 00000000..94d9a38b --- /dev/null +++ b/ports/arm9/iar/example_build/sample_threadx.dep @@ -0,0 +1,220 @@ + + + 4 + 3136050671 + + Debug + + $PROJ_DIR$\cstartup.s + $PROJ_DIR$\sample_threadx.c + $PROJ_DIR$\Debug\Exe\tx.a + $PROJ_DIR$\tx_api.h + $PROJ_DIR$\tx_initialize_low_level.s + $PROJ_DIR$\tx_port.h + $TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h + $TOOLKIT_DIR$\inc\xencoding_limits.h + $PROJ_DIR$\TX_ILL.s79 + $TOOLKIT_DIR$\lib\rt4t_al.a + $PROJ_DIR$\Debug\Obj\demo.r79 + $PROJ_DIR$\Debug\List\sample_threadx.map + $PROJ_DIR$\DEMO.C + $PROJ_DIR$\Debug\Obj\sample_threadx.o + $PROJ_DIR$\Debug\Obj\cstartup.o + $PROJ_DIR$\sample_threadx.icf + $TOOLKIT_DIR$\inc\DLib_Config_Normal.h + $PROJ_DIR$\Debug\Exe\sample_threadx.out + $PROJ_DIR$\Debug\Obj\TX_ILL.r79 + $TOOLKIT_DIR$\inc\string.h + $PROJ_DIR$\Debug\Obj\tx_execution_profile.pbi + $TOOLKIT_DIR$\inc\intrinsics.h + $TOOLKIT_DIR$\lib\shs_l.a + $TOOLKIT_DIR$\inc\DLib_Product.h + $PROJ_DIR$\tx_cstartup.s79 + $TOOLKIT_DIR$\inc\DLib_Product_string.h + $TOOLKIT_DIR$\inc\c\DLib_Product_string.h + $TOOLKIT_DIR$\inc\DLib_Defaults.h + $PROJ_DIR$\Debug\Obj\tx_execution_profile.o + $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h + $TOOLKIT_DIR$\inc\DLib_Threads.h + $TOOLKIT_DIR$\inc\stdlib.h + $PROJ_DIR$\Debug\Obj\sample_threadx.pbd + $PROJ_DIR$\cstartup.s79 + $TOOLKIT_DIR$\inc\yvals.h + $TOOLKIT_DIR$\inc\c\yvals.h + $PROJ_DIR$\tx_execution_profile.c + $PROJ_DIR$\Debug\List\tx_initialize_low_level.lst + $TOOLKIT_DIR$\inc\ycheck.h + $TOOLKIT_DIR$\inc\ysizet.h + $PROJ_DIR$\Debug\Obj\tx_initialize_low_level.o + $TOOLKIT_DIR$\inc\c\stdlib.h + $PROJ_DIR$\Debug\List\cstartup.lst + $TOOLKIT_DIR$\lib\dl4t_aln.a + $PROJ_DIR$\Debug\Obj\tx_cstartup.r79 + $TOOLKIT_DIR$\inc\c\intrinsics.h + $TOOLKIT_DIR$\inc\c\ysizet.h + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $TOOLKIT_DIR$\inc\c\ycheck.h + $TOOLKIT_DIR$\lib\m4t_al.a + $PROJ_DIR$\Debug\Obj\sample_threadx.xcl + $PROJ_DIR$\tx_initialize_low_level.s79 + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $TOOLKIT_DIR$\inc\c\string.h + $PROJ_DIR$\..\inc\tx_port.h + $TOOLKIT_DIR$\inc\c\iccarm_builtin.h + $TOOLKIT_DIR$\inc\c\iar_intrinsics_common.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_api.h + $PROJ_DIR$\Debug\Obj\sample_threadx.__cstat.et + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_receive.c + + + [ROOT_NODE] + + + ILINK + 17 11 + + + + + $PROJ_DIR$\cstartup.s + + + AARM + 14 42 + + + + + $PROJ_DIR$\sample_threadx.c + + + ICCARM + 13 + + + BICOMP + 50 + + + __cstat + 58 + + + + + ICCARM + 57 54 41 48 35 47 29 52 46 6 53 26 45 55 56 + + + + + $PROJ_DIR$\tx_initialize_low_level.s + + + AARM + 40 37 + + + + + $PROJ_DIR$\TX_ILL.s79 + + + AARM + 18 + + + + + $PROJ_DIR$\DEMO.C + + + ICCARM + 10 + + + + + ICCARM + 3 5 + + + + + $PROJ_DIR$\Debug\Exe\sample_threadx.out + + + ILINK + 11 + + + + + ILINK + 15 14 13 2 40 22 9 49 43 + + + + + $PROJ_DIR$\tx_cstartup.s79 + + + AARM + 44 + + + + + $PROJ_DIR$\cstartup.s79 + + + AARM + 14 + + + + + $PROJ_DIR$\tx_execution_profile.c + + + ICCARM + 28 + + + BICOMP + 20 + + + + + ICCARM + 3 5 31 38 34 27 16 23 7 30 39 19 25 21 + + + BICOMP + 3 5 31 38 34 27 23 7 30 39 19 25 21 + + + + + $PROJ_DIR$\tx_initialize_low_level.s79 + + + AARM + 40 37 + + + + + + Release + + + [MULTI_TOOL] + ILINK + + + [REBUILD_ALL] + + + diff --git a/ports/arm9/iar/example_build/sample_threadx.ewd b/ports/arm9/iar/example_build/sample_threadx.ewd new file mode 100644 index 00000000..572d1f45 --- /dev/null +++ b/ports/arm9/iar/example_build/sample_threadx.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/ports/arm9/iar/example_build/sample_threadx.icf b/ports/arm9/iar/example_build/sample_threadx.icf new file mode 100644 index 00000000..9c95e1d1 --- /dev/null +++ b/ports/arm9/iar/example_build/sample_threadx.icf @@ -0,0 +1,49 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x80; +define symbol __ICFEDIT_region_ROM_end__ = 0x1FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x100000; +define symbol __ICFEDIT_region_RAM_end__ = 0x1FFFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_size_freemem__ = 0x100000; + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_freemem = mem:[from 0x200000 to 0x300000]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}; + +place in RAM_region { last section FREE_MEM}; \ No newline at end of file diff --git a/ports/arm9/iar/example_build/settings/azure_rtos.wsdt b/ports/arm9/iar/example_build/settings/azure_rtos.wsdt new file mode 100644 index 00000000..0fbbf9bf --- /dev/null +++ b/ports/arm9/iar/example_build/settings/azure_rtos.wsdt @@ -0,0 +1,535 @@ + + + + + sample_threadx/Debug + tx/Debug + + sample_threadx + 1 + + + + + 21 + 2518 + 2 + + 0 + -1 + + + + 34001 + 0 + + + + + 57600 + 57601 + 57603 + 33024 + 0 + 57607 + 0 + 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+ + + 34050 + 0A0000000A0000006E0000006E000000 + 0000000000000000FE0200001A000000 + 8192 + 0 + 0 + 744 + 0 + + + 1 + + + + 34048 + 34049 + 34050 + 34051 + 34052 + 34053 + 34054 + 34055 + 34056 + 34057 + 34058 + 34059 + 34060 + 34061 + 34062 + 34063 + 34064 + 34065 + + + + 01000000030000000100000000000000000000000100000001000000FFFFFFFF00000000010000000100000000000000280000002800000000000000 + + + + diff --git a/ports/arm9/iar/example_build/settings/sample_threadx.Debug.cspy.bat b/ports/arm9/iar/example_build/settings/sample_threadx.Debug.cspy.bat new file mode 100644 index 00000000..8e5310b2 --- /dev/null +++ b/ports/arm9/iar/example_build/settings/sample_threadx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\arm9\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\arm9\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\arm9\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\arm9\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports/arm9/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports/arm9/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 new file mode 100644 index 00000000..9aeceb8c --- /dev/null +++ b/ports/arm9/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\arm9\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\arm9\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\arm9\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\arm9\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} diff --git a/ports/arm9/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports/arm9/iar/example_build/settings/sample_threadx.Debug.driver.xcl new file mode 100644 index 00000000..f90fa82c --- /dev/null +++ b/ports/arm9/iar/example_build/settings/sample_threadx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=ARM9TDMI" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/arm9/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports/arm9/iar/example_build/settings/sample_threadx.Debug.general.xcl new file mode 100644 index 00000000..60a8329a --- /dev/null +++ b/ports/arm9/iar/example_build/settings/sample_threadx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\arm9\iar\example_build\Debug\Exe\sample_threadx.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports/arm9/iar/example_build/settings/sample_threadx.crun b/ports/arm9/iar/example_build/settings/sample_threadx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/arm9/iar/example_build/settings/sample_threadx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports/arm9/iar/example_build/settings/sample_threadx.dbgdt b/ports/arm9/iar/example_build/settings/sample_threadx.dbgdt new file mode 100644 index 00000000..bb3377a6 --- /dev/null +++ b/ports/arm9/iar/example_build/settings/sample_threadx.dbgdt @@ -0,0 +1,1686 @@ + + + + + + + 394 + 27 + 27 + 2010398909 + + + + + 2 + 0 + 0 + + + 1 + 0 + 0 + + + 35 + 1470 + + + 20 + 915 + 244 + 61 + + + + 2 + 0 + 0 + + + + + + 3 + 0 + 0 + + + 0 + 1 + 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b/ports/arm9/iar/example_build/settings/tx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports/arm9/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports/arm9/iar/example_build/settings/tx.Debug.cspy.ps1 new file mode 100644 index 00000000..6a1889c0 --- /dev/null +++ b/ports/arm9/iar/example_build/settings/tx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} diff --git a/ports/arm9/iar/example_build/settings/tx.Debug.driver.xcl b/ports/arm9/iar/example_build/settings/tx.Debug.driver.xcl new file mode 100644 index 00000000..f90fa82c --- /dev/null +++ b/ports/arm9/iar/example_build/settings/tx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=ARM9TDMI" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/arm9/iar/example_build/settings/tx.Debug.general.xcl b/ports/arm9/iar/example_build/settings/tx.Debug.general.xcl new file mode 100644 index 00000000..deeeb2f9 --- /dev/null +++ b/ports/arm9/iar/example_build/settings/tx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armsim2.dll" + +"C:\release\threadx\Debug\Exe\tx.out" + +--plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armbat.dll" + + + + diff --git a/ports/arm9/iar/example_build/settings/tx.crun b/ports/arm9/iar/example_build/settings/tx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/arm9/iar/example_build/settings/tx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports/arm9/iar/example_build/settings/tx.dbgdt b/ports/arm9/iar/example_build/settings/tx.dbgdt new file mode 100644 index 00000000..73e71f6e --- /dev/null +++ b/ports/arm9/iar/example_build/settings/tx.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports/arm9/iar/example_build/settings/tx.dnx b/ports/arm9/iar/example_build/settings/tx.dnx new file mode 100644 index 00000000..1872e83f --- /dev/null +++ b/ports/arm9/iar/example_build/settings/tx.dnx @@ -0,0 +1,58 @@ + + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports/arm9/iar/example_build/tx.dep b/ports/arm9/iar/example_build/tx.dep new file mode 100644 index 00000000..ffa06c4e --- /dev/null +++ b/ports/arm9/iar/example_build/tx.dep @@ -0,0 +1,9603 @@ + + + 4 + 501655296 + + Debug + + $PROJ_DIR$\tx_event_flags_initialize.c + $PROJ_DIR$\tx_event_flags_performance_info_get.c + $PROJ_DIR$\tx_event_flags_set.c + $PROJ_DIR$\tx_byte_pool_performance_info_get.c + $PROJ_DIR$\tx_byte_pool_search.c + $PROJ_DIR$\tx_event_flags_cleanup.c + $PROJ_DIR$\tx_event_flags_performance_system_info_get.c + $PROJ_DIR$\tx_event_flags_set_notify.c + $PROJ_DIR$\tx_initialize_high_level.c + $PROJ_DIR$\tx_initialize_kernel_enter.c + $PROJ_DIR$\tx_initialize.h + $PROJ_DIR$\tx_initialize_kernel_setup.c + $PROJ_DIR$\tx_mutex.h + $PROJ_DIR$\tx_mutex_cleanup.c + $PROJ_DIR$\tx_byte_pool_initialize.c + $PROJ_DIR$\tx_event_flags_create.c + $PROJ_DIR$\tx_iar.c + $PROJ_DIR$\tx_mutex_create.c + $PROJ_DIR$\tx_mutex_delete.c + $PROJ_DIR$\tx_mutex_get.c + $PROJ_DIR$\tx_byte_pool_info_get.c + $PROJ_DIR$\tx_mutex_info_get.c + $PROJ_DIR$\tx_mutex_initialize.c + $PROJ_DIR$\tx_mutex_performance_info_get.c + $PROJ_DIR$\tx_event_flags_info_get.c + $PROJ_DIR$\tx_event_flags_delete.c + $PROJ_DIR$\tx_byte_release.c + $PROJ_DIR$\tx_byte_pool_prioritize.c + $PROJ_DIR$\tx_event_flags.h + $PROJ_DIR$\tx_byte_pool_delete.c + $PROJ_DIR$\tx_byte_pool_performance_system_info_get.c + $PROJ_DIR$\tx_event_flags_get.c + $PROJ_DIR$\tx_byte_allocate.c + $PROJ_DIR$\tx_byte_pool.h + $PROJ_DIR$\tx_byte_pool_cleanup.c + $PROJ_DIR$\tx_block_pool_initialize.c + $PROJ_DIR$\tx_byte_pool_create.c + $PROJ_DIR$\tx_block_pool_create.c + $PROJ_DIR$\tx_block_pool_cleanup.c + $PROJ_DIR$\tx_block_pool_delete.c + $PROJ_DIR$\tx_block_pool_performance_info_get.c + $PROJ_DIR$\tx_block_pool_performance_system_info_get.c + $PROJ_DIR$\tx_block_pool_prioritize.c + $PROJ_DIR$\tx_api.h + $PROJ_DIR$\tx_block_allocate.c + $PROJ_DIR$\tx_block_pool.h + $PROJ_DIR$\tx_block_release.c + $PROJ_DIR$\tx_block_pool_info_get.c + $PROJ_DIR$\Debug\Obj\tx_trace_user_event_insert.o + $PROJ_DIR$\Tx_tim.h + $PROJ_DIR$\Debug\Obj\txe_byte_pool_create.o + $PROJ_DIR$\Debug\Obj\tx_mutex_prioritize.o + $PROJ_DIR$\Debug\Obj\txe_event_flags_delete.o + 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$PROJ_DIR$\..\..\..\..\common\src\tx_initialize_kernel_setup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_misra.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_priority_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_put.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_delete.c + + + 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$PROJ_DIR$\..\..\..\..\common\src\txe_thread_relinquish.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_reset.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_resume.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_suspend.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_terminate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_time_slice_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c + + + diff --git a/ports/arm9/iar/example_build/tx_initialize_low_level.s b/ports/arm9/iar/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..36bcc6a3 --- /dev/null +++ b/ports/arm9/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,327 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; Disable irq,fiq SVC mode +IRQ_MODE DEFINE 0xD2 ; Disable irq,fiq IRQ mode +FIQ_MODE DEFINE 0xD1 ; Disable irq,fiq FIQ mode +SYS_MODE DEFINE 0xDF ; Disable irq,fiq SYS mode +; +; + + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_thread_context_save +; EXTERN _tx_thread_vectored_context_save + EXTERN _tx_thread_context_restore +#ifdef TX_ENABLE_FIQ_SUPPORT + EXTERN _tx_thread_fiq_context_save + EXTERN _tx_thread_fiq_context_restore +#endif +#ifdef TX_ENABLE_IRQ_NESTING + EXTERN _tx_thread_irq_nesting_start + EXTERN _tx_thread_irq_nesting_end +#endif +#ifdef TX_ENABLE_FIQ_NESTING + EXTERN _tx_thread_fiq_nesting_start + EXTERN _tx_thread_fiq_nesting_end +#endif + EXTERN _tx_timer_interrupt + EXTERN ?cstartup + EXTERN _tx_build_options + EXTERN _tx_version_id +; +; +; +;/* Define the FREE_MEM segment that will specify where free memory is +; defined. This must also be located in at the end of other RAM segments +; in the linker control file. The value of this segment is what is passed +; to tx_application_define. */ +; + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + CODE32 + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level +; +; /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode. */ +; +; /* Remember the stack pointer, link register, and switch to SVC mode. */ +; + MOV r0, sp ; Remember the SP + MOV r1, lr ; Remember the LR + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r3 ; Switch to SVC mode + MOV sp, r0 ; Inherit the stack pointer setup by cstartup + MOV lr, r1 ; Inherit the link register +; +; /* Pickup the start of free memory. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) FREE_MEM; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Done, return to caller. */ +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +;/* Define shells for each of the interrupt vectors. */ +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt ; Software interrupt handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_prefetch_handler +__tx_prefetch_handler + B __tx_prefetch_handler ; Prefetch exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_abort_handler +__tx_abort_handler + B __tx_abort_handler ; Abort exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +; +; /* For debug purpose, execute the timer interrupt processing here. In +; a real system, some kind of status indication would have to be checked +; before the timer interrupt handler could be called. */ +; + BL _tx_timer_interrupt ; Timer interrupt handler +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; +; RSEG .text:CODE:NOROOT(2) +; PUBLIC __tx_example_vectored_irq_handler +;__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +;#endif +; +; /* Application IRQ handler is called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +;#endif +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; +#else + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler +#endif +; +; +BUILD_OPTIONS + DC32 _tx_build_options ; Reference to ensure it comes in +VERSION_ID + DC32 _tx_version_id ; Reference to ensure it comes in + END + diff --git a/ports/arm9/iar/inc/tx_port.h b/ports/arm9/iar/inc/tx_port.h new file mode 100644 index 00000000..ed501c4b --- /dev/null +++ b/ports/arm9/iar/inc/tx_port.h @@ -0,0 +1,388 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARM9/IAR */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#if __CORE__ > __ARM4TM__ + +#if __CPU_MODE__ == 2 + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (UINT) __CLZ(m); \ + b = 31 - b; +#endif +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +/* First, check and see what mode the file is being compiled in. The IAR compiler + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros + are available. Otherwise, if Thumb mode is present, we must use function calls. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else +#if __CPU_MODE__ == 2 + +#if (__VER__ < 8002000) +__intrinsic unsigned long __get_CPSR(); +__intrinsic void __set_CPSR( unsigned long ); +#endif + + +#if (__VER__ < 8002000) +#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#else +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#endif + +#define TX_DISABLE interrupt_save = __get_CPSR(); \ + __set_CPSR(interrupt_save | TX_INT_DISABLE); +#define TX_RESTORE __set_CPSR(interrupt_save); + +#else + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#endif +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/IAR Version 6.0 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + diff --git a/ports/arm9/iar/readme_threadx.txt b/ports/arm9/iar/readme_threadx.txt new file mode 100644 index 00000000..67ea7d01 --- /dev/null +++ b/ports/arm9/iar/readme_threadx.txt @@ -0,0 +1,528 @@ + Microsoft's Azure RTOS ThreadX for ARM9 + + Thumb & 32-bit Mode + + Using the IAR Tools + +1. Building the ThreadX run-time Library + +Building the ThreadX library is easy. First, open the Azure RTOS workspace +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by +the application. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the IAR +Windows-based ARM9 simulator. + +Building the demonstration is easy; simply make the sample_threadx.ewp project +the "active project" in the IAR Embedded Workbench and select the +"Make" button. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a +binary file that can be downloaded and executed on IAR's ARM9 simulator. + +A SPECIAL NOTE: The IAR ARM simulator does simulate interrupts. In order +for the ThreadX demonstration to run properly, a periodic IRQ interrupt must +be setup in the IAR debugging environment. We recommend setting an IRQ +interrupt to execute every 9999 cycles. + + +3. System Initialization + +The entry point in ThreadX for the ARM9 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. +By default, the vector area is defined at the top of cstartup.s, which is +a slightly modified from the base IAR file. + +The _tx_initialize_low_level function inside of tx_initialize_low_level.s +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all +other RAM sections in memory. + + +4. Register Usage and Stack Frames + +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +5. Conditional Compilation Switches + +The following are conditional compilation options for building the ThreadX library +and application: + + + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + FIQ interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + + TX_ENABLE_IRQ_NESTING This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. + + TX_ENABLE_FIQ_NESTING This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. In addition, + IRQ nesting should also be enabled. + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + TX_THUMB Defined, this option enables the BX LR calling return sequence + in assembly files, to ensure correct operation on systems that + use both ARM and Thumb mode. By default, this option is + not defined + + + + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the ThreadX library +project to enable various compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for ARM9 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The ARM9 vectors start at address zero. The demonstration system startup +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + PUBLIC __tx_irq_handler + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR dispatch call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_example_vectored_irq_handler +__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers + BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR dispatch call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +; + BL _tx_thread_irq_nesting_start + +; /* Application ISR dispatch call goes here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +; + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, ARM9 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ dispatch call goes here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in +preparation for the FIQ context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ dispatch call goes here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +in the IRQ processing. + + +9. Thumb/ARM9 Mixed Mode + +By default, ThreadX is setup for running in ARM9 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire +ThreadX assembly source should be built with TX_THUMB defined. + + +10. IAR Thread-safe Library Support + +Thread-safe support for the IAR tools is easily enabled by building the ThreadX library +and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file +should have the following line added (if not already in place): + +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application + + +11. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX version 6.0.1 for ARM9 using IAR's ARM tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/arm9/iar/src/tx_iar.c b/ports/arm9/iar/src/tx_iar.c new file mode 100644 index 00000000..11fcefb3 --- /dev/null +++ b/ports/arm9/iar/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports/arm9/iar/src/tx_thread_context_restore.s b/ports/arm9/iar/src/tx_thread_context_restore.s new file mode 100644 index 00000000..8f8f4047 --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_context_restore.s @@ -0,0 +1,245 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +SVC_MODE DEFINE 0xD3 ; SVC mode +IRQ_MODE DEFINE 0xD2 ; IRQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +THUMB_MASK DEFINE 0x20 ; Thumb bit mask +SVC_MODE_BITS DEFINE 0x13 ; SVC mode value + +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_restore + CODE32 +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + MRS r3, CPSR ; Pickup current CPSR + ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value + MSR CPSR_cxsf, r0 ; Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block + BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS ; Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 ; Lockout interrupts +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r3, r3, #MODE_MASK ; Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +;} +; +; + END + diff --git a/ports/arm9/iar/src/tx_thread_context_save.s b/ports/arm9/iar/src/tx_thread_context_save.s new file mode 100644 index 00000000..8d39c7f0 --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_context_save.s @@ -0,0 +1,211 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif + + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_irq_processing_return + EXTERN _tx_execution_isr_enter +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_save + CODE32 +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r0 ; Disable interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + +; +; + END + diff --git a/ports/arm9/iar/src/tx_thread_fiq_context_restore.s b/ports/arm9/iar/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..3d9b735f --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,257 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; SVC mode +FIQ_MODE DEFINE 0xD1 ; FIQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +THUMB_MASK DEFINE 0x20 ; Thumb bit mask +IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits +SVC_MODE_BITS DEFINE 0x13 ; SVC mode value + +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_restore + CODE32 +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + MRS r3, CPSR ; Pickup current CPSR + ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value + MSR CPSR_cxsf, r0 ; Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_cxsf, r2 ; Re-enter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block */ + BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS ; Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 ; Lockout interrupts +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MRS r3, CPSR ; Pickup current CPSR + BIC r3, r3, #MODE_MASK ; Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +; +;} +; +; + END + diff --git a/ports/arm9/iar/src/tx_thread_fiq_context_save.s b/ports/arm9/iar/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..3c65cda2 --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_fiq_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_fiq_processing_return + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_save + CODE32 +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} +; +; + END + diff --git a/ports/arm9/iar/src/tx_thread_fiq_nesting_end.s b/ports/arm9/iar/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..673c912a --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,109 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_end + CODE32 +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_cxsf, r0 ; Disable interrupts + LDR lr, [sp] ; Pickup saved lr + ADD sp, sp, #4 ; Adjust stack pointer + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_cxsf, r0 ; Re-enter IRQ mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/arm9/iar/src/tx_thread_fiq_nesting_start.s b/ports/arm9/iar/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..b4bd8c67 --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit +MODE_MASK DEFINE 0x1F ; Mode mask +SYS_MODE_BITS DEFINE 0x1F ; System mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_start + CODE32 +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + STR lr, [sp, #-4]! ; Push the system mode lr on the system mode stack + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/arm9/iar/src/tx_thread_interrupt_control.s b/ports/arm9/iar/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..6c02c8e3 --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_interrupt_control.s @@ -0,0 +1,103 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +INT_MASK DEFINE 0xC0 ; Interrupt bit mask +#else +INT_MASK DEFINE 0x80 ; Interrupt bit mask +#endif +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_control + CODE32 +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} +; +; + END diff --git a/ports/arm9/iar/src/tx_thread_interrupt_disable.s b/ports/arm9/iar/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..4b36594c --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_interrupt_disable.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_disable + CODE32 +_tx_thread_interrupt_disable??rA +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + ORR r1, r0, #DISABLE_INTS ; Mask interrupts + MSR CPSR_cxsf, r1 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +; + END diff --git a/ports/arm9/iar/src/tx_thread_interrupt_restore.s b/ports/arm9/iar/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..0a929e6d --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;void _tx_thread_interrupt_restore(UINT old_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_restore + CODE32 +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r0 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; + END diff --git a/ports/arm9/iar/src/tx_thread_irq_nesting_end.s b/ports/arm9/iar/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..93db4900 --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_end + CODE32 +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_cxsf, r0 ; Disable interrupts + LDR lr, [sp] ; Pickup saved lr + ADD sp, sp, #4 ; Adjust stack pointer + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_cxsf, r0 ; Re-enter IRQ mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/arm9/iar/src/tx_thread_irq_nesting_start.s b/ports/arm9/iar/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..300f7838 --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +IRQ_DISABLE DEFINE 0x80 ; IRQ disable bit +MODE_MASK DEFINE 0x1F ; Mode mask +SYS_MODE_BITS DEFINE 0x1F ; System mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_start + CODE32 +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + STR lr, [sp, #-4]! ; Push the system mode lr on the system mode stack + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/arm9/iar/src/tx_thread_schedule.s b/ports/arm9/iar/src/tx_thread_schedule.s new file mode 100644 index 00000000..09e832e1 --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_schedule.s @@ -0,0 +1,171 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask +#else +ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask +#endif +; +; + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_execution_thread_enter +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_schedule + CODE32 +_tx_thread_schedule??rA +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + MRS r2, CPSR ; Pickup CPSR + BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s) + MSR CPSR_cxsf, r0 ; Enable interrupts +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + MSR CPSR_cxsf, r2 ; Disable interrupts +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ; variable + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + BL _tx_execution_thread_enter ; Call the thread execution enter function +#endif +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r0, r1} ; Pickup the stack type and saved CPSR + CMP r0, #0 ; Check for synchronous context switch + MSRNE SPSR_cxsf, r1 ; Setup SPSR for return + LDMNEIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously + MSR CPSR_cxsf, r1 ; Recover CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} +; + END + diff --git a/ports/arm9/iar/src/tx_thread_stack_build.s b/ports/arm9/iar/src/tx_thread_stack_build.s new file mode 100644 index 00000000..fcf39a3f --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_stack_build.s @@ -0,0 +1,158 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE DEFINE 0x13 ; SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK DEFINE 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled +#else +CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled +#endif +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_stack_build + + CODE32 +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the ARM9 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure long-word alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + MRS r1, CPSR ; Pickup CPSR + BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} + END + diff --git a/ports/arm9/iar/src/tx_thread_system_return.s b/ports/arm9/iar/src/tx_thread_system_return.s new file mode 100644 index 00000000..5212168d --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_system_return.s @@ -0,0 +1,149 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif +; +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_execution_thread_exit +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_system_return + CODE32 +_tx_thread_system_return??rA +_tx_thread_system_return +; +; /* Save minimal context on the stack. */ +; + MOV r0, #0 ; Build a solicited stack type + MRS r1, CPSR ; Pickup the CPSR + STMDB sp!, {r0-r1, r4-r11, lr} ; Save minimal context +; +; /* Lockout interrupts. */ +; + ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r2 ; Disable interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function +#endif + + LDR r3, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r0, [r3, #0] ; Pickup current thread pointer + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r0, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r0, #24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r3, #0] ; Clear current thread pointer + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports/arm9/iar/src/tx_thread_vectored_context_save.s b/ports/arm9/iar/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..cf11f910 --- /dev/null +++ b/ports/arm9/iar/src/tx_thread_vectored_context_save.s @@ -0,0 +1,195 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_vectored_context_save + CODE32 +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, the minimal context is already saved, and the +; lr register contains the return ISR address. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; +#ifdef TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r0 ; Disable interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + MOV pc, lr ; Return to caller +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + MOV pc, lr ; Return to caller +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #32 ; Recover saved registers + MOV pc, lr ; Return to caller +; +; } +;} + END + diff --git a/ports/arm9/iar/src/tx_timer_interrupt.s b/ports/arm9/iar/src/tx_timer_interrupt.s new file mode 100644 index 00000000..1a508c6a --- /dev/null +++ b/ports/arm9/iar/src/tx_timer_interrupt.s @@ -0,0 +1,260 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt ARM9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_timer_interrupt + CODE32 +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} + END + diff --git a/ports/c667x/ccs/example_build/include/C66XX.h b/ports/c667x/ccs/example_build/include/C66XX.h new file mode 100644 index 00000000..581b563e --- /dev/null +++ b/ports/c667x/ccs/example_build/include/C66XX.h @@ -0,0 +1,150 @@ +/****************************************************************************** + TMS320C66xx KeyStone Multicore DSP Software Development Kit (SDK). Rev 2A. + Definitions, macros and API functions for DSP Environment. + (C) MicroLAB Systems, 2015 + + + http://www.mlabsys.com + ftp://ftp.mlabsys.com + email: techsupport@mlabsys.com + + + Description: + ------------ + This file contains definitions, macros and API functions for KeyStone + Multicore DSP environment and must be included in the user C-application. + DSP Software Development Kit library is based on TI Chip Support Library + (CSL), so it's needed to add CSL libraries into the project along with DSP + Software Development Kit library. + + Note that C66xx CorePac interrupt controller (INTC) functions are not + included in this DSP Software Utilities library. + It's delivered as a separate library from the remaining DSP Software + Utilities. When using an embedded operating system that contains interrupt + controller/dispatcher support, do not link in the INTC library. + For interrupt controller support, SYS/BIOS users should use + the HWI (Hardware Interrupt) and ECM (Event Combiner Manager) modules + supported under SYS/BIOS v5.21 or later. + + + Revision history: + ----------------- + rev.1A - 2014, initial release for C6678 DSP. + rev.1B - 2015, fixed minor bugs. + rev.1C - 2015: + - changed C66XX_init_ddr3() DDR3 initialization + function; + - added DSP chip-level (CPINTC) interrupt controller + functions; + rev.2A - 2015, totally redesigned DSP SDK; + + + Notes: + ------ + 1. This C-header file is an include file for TI C6xxx C/C++ Code + Generation Tools, which must be invoked to compile code for C66xx DSP + platform. + + 2. The following additional libraries should be included: + TI Chip Support Library (CSL) (ti.csl.ae66) should be included in + Linker options (this library is located at + $(TI_PDK_C6678_INSTALL_DIR)\packages\ti\csl\lib). + + 3. This file is best viewed with the TAB setting set to '4'. + + 4. This header file is externally controlled from user C-code by run-time + compiler keys definitions in order to apply DSP-type specific + definitions to refer to particular definitions included for different + DSP type: + + __C66XX_SELECT_C6678_DSP__ + - if defined in user code prior inclusion of this header file, + then DSP-type specific definitions are applied to C6678 DSP + + Copyright: + ---------- + This utility is supplied free of charge as it is without any obligation + from MicroLAB Systems. No responsibility is assumed for any use or misuse + of these utilities. + +******************************************************************************/ + + +/** + * @file C66XX.h + * + * @brief KeyStone Multicore DSP SDK include file + * + * This file contains definitions, macros and API functions for KeyStone + * Multicore DSP environment + * + */ + + +#ifndef __C66XX_H__ // check for this file has been already included +#define __C66XX_H__ 1 + + +// General defs +#define C66XX_ON 1 +#define C66XX_OFF 0 + + +//============================================================================= +//------------ DSP-type specific run-time compiler keys processing ------------ +// (this is required in order to exclude key confusions) + +// Default setting is C6678 definitions +#ifndef __C66XX_SELECT_C6678_DSP__ +#define __C66XX_SELECT_C6678_DSP__ 1 +#endif /* __C66XX_SELECT_C6678_DSP__ */ + +//============================================================================= + + +/** KeyStone Multicore DSP SDK revision ID */ +#define C66XX_SDK_REVISION_ID "2A" + + +// Include TI Chip Support Library (CSL) defs +// CSL Chip Functional Layer +#include +// CSL TSC Functional Layer +#include +// CSL Cache Functional Layer +#include +// CSL Boot configuration defs +#include +// CSL Power and Sleep Controller defs +#include +// CSL XMC Controller defs +#include +// CSL DDR3 defs +#include +#include +// CSL INTC defs +#include +// CSL CPINTC defs +#include +// CSL SGMII defs +#include +#include +// CSL GPIO Functional Layer +#include +// CSL Timer Functional Layer +#include +// CSL UART Functional Layer +#include +// CSL SRIO Functional Layer +#include +#include + + +// Include C66xx DSP defs, macros and aux functions +#include "C66XX_DEF.hxx" +#include "C66XX_MACROS.hxx" +#include "C66XX_FUNCTIONS.hxx" + + +//============================================================================= +#endif /* __C66XX_H__ */ diff --git a/ports/c667x/ccs/example_build/include/C66XX_DEF.hxx b/ports/c667x/ccs/example_build/include/C66XX_DEF.hxx new file mode 100644 index 00000000..9764a47f --- /dev/null +++ b/ports/c667x/ccs/example_build/include/C66XX_DEF.hxx @@ -0,0 +1,1678 @@ +/****************************************************************************** + TMS320C66xx KeyStone Multicore DSP Software Development Kit (SDK). Rev 2A. + (C) MicroLAB Systems, 2014-2015 + + File: Definitions + ----- + + Notes: + ------ + 1. This C-header file contains general DSP definitions and + is used with C66XX.h C-header file. + + 2. This file is best viewed with the TAB setting set to '4'. + +******************************************************************************/ + + +/** + * @file C66XX_DEF.hxx + * + * @brief Definitions + * + * This file contains general C66xx DSP definitions + * + */ + + +#ifndef __C66XX_DEF_HXX__ // check for this file has been already included +#define __C66XX_DEF_HXX__ 1 + + +//============================================================================= +//============ DSP CPU ID ===================================================== +//============================================================================= + +// DSP CPU ID is located at CSR register and is used to identify the chip +#define C66XX_DSP_CPU_ID 0x15 +//============================================================================= + + + +#ifdef __C66XX_SELECT_C6678_DSP__ +//============================================================================= +//============ DSP cores number =============================================== +//============================================================================= +#define C66XX_DSP_NUMBER_OF_CORES 8 +//============================================================================= + + +//============================================================================= +//============ DSP memory map ================================================= +//============================================================================= +// All address ranges refer to 32-bit LOGICAL addresses!!! + +// Local L2 SRAM - 512KB +#define C66XX_LOCAL_L2_SRAM_SADDR 0x00800000 +#define C66XX_LOCAL_L2_SRAM_EADDR 0x0087ffff +#define C66XX_LOCAL_L2_SRAM_LEN (C66XX_LOCAL_L2_SRAM_EADDR - C66XX_LOCAL_L2_SRAM_SADDR + 1) + +// Local L1P SRAM - 32KB +#define C66XX_LOCAL_L1P_SRAM_SADDR 0x00e00000 +#define C66XX_LOCAL_L1P_SRAM_EADDR 0x00e07fff +#define C66XX_LOCAL_L1P_SRAM_LEN (C66XX_LOCAL_L1P_SRAM_EADDR - C66XX_LOCAL_L1P_SRAM_SADDR + 1) + +// Local L1D SRAM - 32KB +#define C66XX_LOCAL_L1D_SRAM_SADDR 0x00f00000 +#define C66XX_LOCAL_L1D_SRAM_EADDR 0x00f07fff +#define C66XX_LOCAL_L1D_SRAM_LEN (C66XX_LOCAL_L1D_SRAM_EADDR - C66XX_LOCAL_L1D_SRAM_SADDR + 1) + +// C66xx CorePack registers area - 4MB +#define C66XX_DSP_RG_AREA_SADDR 0x01800000 +#define C66XX_DSP_RG_AREA_EADDR 0x01bfffff +#define C66XX_DSP_RG_AREA_LEN (C66XX_DSP_RG_AREA_EADDR - C66XX_DSP_RG_AREA_SADDR + 1) + +// Tracer MSMC 0 registers area - 128B +#define C66XX_TRACER_MSMC_0_RG_AREA_SADDR 0x01d00000 +#define C66XX_TRACER_MSMC_0_RG_AREA_EADDR 0x01d0007f +#define C66XX_TRACER_MSMC_0_RG_AREA_LEN (C66XX_TRACER_MSMC_0_RG_AREA_EADDR - C66XX_TRACER_MSMC_0_RG_AREA_SADDR + 1) + +// Tracer MSMC 1 registers area - 128B +#define C66XX_TRACER_MSMC_1_RG_AREA_SADDR 0x01d08000 +#define C66XX_TRACER_MSMC_1_RG_AREA_EADDR 0x01d0807f +#define C66XX_TRACER_MSMC_1_RG_AREA_LEN (C66XX_TRACER_MSMC_1_RG_AREA_EADDR - C66XX_TRACER_MSMC_1_RG_AREA_SADDR + 1) + +// Tracer MSMC 2 registers area - 128B +#define C66XX_TRACER_MSMC_2_RG_AREA_SADDR 0x01d10000 +#define C66XX_TRACER_MSMC_2_RG_AREA_EADDR 0x01d1007f +#define C66XX_TRACER_MSMC_2_RG_AREA_LEN (C66XX_TRACER_MSMC_2_RG_AREA_EADDR - C66XX_TRACER_MSMC_2_RG_AREA_SADDR + 1) + +// Tracer MSMC 3 registers area - 128B +#define C66XX_TRACER_MSMC_3_RG_AREA_SADDR 0x01d18000 +#define C66XX_TRACER_MSMC_3_RG_AREA_EADDR 0x01d1807f +#define C66XX_TRACER_MSMC_3_RG_AREA_LEN (C66XX_TRACER_MSMC_3_RG_AREA_EADDR - C66XX_TRACER_MSMC_3_RG_AREA_SADDR + 1) + +// Tracer QM DMA registers area - 128B +#define C66XX_TRACER_QM_DMA_RG_AREA_SADDR 0x01d20000 +#define C66XX_TRACER_QM_DMA_RG_AREA_EADDR 0x01d2007f +#define C66XX_TRACER_QM_DMA_RG_AREA_LEN (C66XX_TRACER_QM_DMA_RG_AREA_EADDR - C66XX_TRACER_QM_DMA_RG_AREA_SADDR + 1) + +// Tracer DDR registers area - 128B +#define C66XX_TRACER_DDR_RG_AREA_SADDR 0x01d28000 +#define C66XX_TRACER_DDR_RG_AREA_EADDR 0x01d2807f +#define C66XX_TRACER_DDR_RG_AREA_LEN (C66XX_TRACER_DDR_RG_AREA_EADDR - C66XX_TRACER_DDR_RG_AREA_SADDR + 1) + +// Tracer SM registers area - 128B +#define C66XX_TRACER_SM_RG_AREA_SADDR 0x01d30000 +#define C66XX_TRACER_SM_RG_AREA_EADDR 0x01d3007f +#define C66XX_TRACER_SM_RG_AREA_LEN (C66XX_TRACER_SM_RG_AREA_EADDR - C66XX_TRACER_SM_RG_AREA_SADDR + 1) + +// Tracer QM CFG registers area - 128B +#define C66XX_TRACER_QM_CFG_RG_AREA_SADDR 0x01d38000 +#define C66XX_TRACER_QM_CFG_RG_AREA_EADDR 0x01d3807f +#define C66XX_TRACER_QM_CFG_RG_AREA_LEN (C66XX_TRACER_QM_CFG_RG_AREA_EADDR - C66XX_TRACER_QM_CFG_RG_AREA_SADDR + 1) + +// Tracer CFG registers area - 128B +#define C66XX_TRACER_CFG_RG_AREA_SADDR 0x01d40000 +#define C66XX_TRACER_CFG_RG_AREA_EADDR 0x01d4007f +#define C66XX_TRACER_CFG_RG_AREA_LEN (C66XX_TRACER_CFG_RG_AREA_EADDR - C66XX_TRACER_CFG_RG_AREA_SADDR + 1) + +// Tracer L2 0 registers area - 128B +#define C66XX_TRACER_L2_0_RG_AREA_SADDR 0x01d48000 +#define C66XX_TRACER_L2_0_RG_AREA_EADDR 0x01d4807f +#define C66XX_TRACER_L2_0_RG_AREA_LEN (C66XX_TRACER_L2_0_RG_AREA_EADDR - C66XX_TRACER_L2_0_RG_AREA_SADDR + 1) + +// Tracer L2 1 registers area - 128B +#define C66XX_TRACER_L2_1_RG_AREA_SADDR 0x01d50000 +#define C66XX_TRACER_L2_1_RG_AREA_EADDR 0x01d5007f +#define C66XX_TRACER_L2_1_RG_AREA_LEN (C66XX_TRACER_L2_1_RG_AREA_EADDR - C66XX_TRACER_L2_1_RG_AREA_SADDR + 1) + +// Tracer L2 2 registers area - 128B +#define C66XX_TRACER_L2_2_RG_AREA_SADDR 0x01d58000 +#define C66XX_TRACER_L2_2_RG_AREA_EADDR 0x01d5807f +#define C66XX_TRACER_L2_2_RG_AREA_LEN (C66XX_TRACER_L2_2_RG_AREA_EADDR - C66XX_TRACER_L2_2_RG_AREA_SADDR + 1) + +// Tracer L2 3 registers area - 128B +#define C66XX_TRACER_L2_3_RG_AREA_SADDR 0x01d60000 +#define C66XX_TRACER_L2_3_RG_AREA_EADDR 0x01d6007f +#define C66XX_TRACER_L2_3_RG_AREA_LEN (C66XX_TRACER_L2_3_RG_AREA_EADDR - C66XX_TRACER_L2_3_RG_AREA_SADDR + 1) + +// Tracer L2 4 registers area - 128B +#define C66XX_TRACER_L2_4_RG_AREA_SADDR 0x01d68000 +#define C66XX_TRACER_L2_4_RG_AREA_EADDR 0x01d6807f +#define C66XX_TRACER_L2_4_RG_AREA_LEN (C66XX_TRACER_L2_4_RG_AREA_EADDR - C66XX_TRACER_L2_4_RG_AREA_SADDR + 1) + +// Tracer L2 5 registers area - 128B +#define C66XX_TRACER_L2_5_RG_AREA_SADDR 0x01d70000 +#define C66XX_TRACER_L2_5_RG_AREA_EADDR 0x01d7007f +#define C66XX_TRACER_L2_5_RG_AREA_LEN (C66XX_TRACER_L2_5_RG_AREA_EADDR - C66XX_TRACER_L2_5_RG_AREA_SADDR + 1) + +// Tracer L2 6 registers area - 128B +#define C66XX_TRACER_L2_6_RG_AREA_SADDR 0x01d78000 +#define C66XX_TRACER_L2_6_RG_AREA_EADDR 0x01d7807f +#define C66XX_TRACER_L2_6_RG_AREA_LEN (C66XX_TRACER_L2_6_RG_AREA_EADDR - C66XX_TRACER_L2_6_RG_AREA_SADDR + 1) + +// Tracer L2 7 registers area - 128B +#define C66XX_TRACER_L2_7_RG_AREA_SADDR 0x01d80000 +#define C66XX_TRACER_L2_7_RG_AREA_EADDR 0x01d8007f +#define C66XX_TRACER_L2_7_RG_AREA_LEN (C66XX_TRACER_L2_7_RG_AREA_EADDR - C66XX_TRACER_L2_7_RG_AREA_SADDR + 1) + +// Telecom Serial Interface Port (TSIP) 0 registers area - 256KB +#define C66XX_TSIP_0_RG_AREA_SADDR 0x01e00000 +#define C66XX_TSIP_0_RG_AREA_EADDR 0x01e3ffff +#define C66XX_TSIP_0_RG_AREA_LEN (C66XX_TSIP_0_RG_AREA_EADDR - C66XX_TSIP_0_RG_AREA_SADDR + 1) + +// Telecom Serial Interface Port (TSIP) 1 registers area - 256KB +#define C66XX_TSIP_1_RG_AREA_SADDR 0x01e80000 +#define C66XX_TSIP_1_RG_AREA_EADDR 0x01ebffff +#define C66XX_TSIP_1_RG_AREA_LEN (C66XX_TSIP_1_RG_AREA_EADDR - C66XX_TSIP_1_RG_AREA_SADDR + 1) + +// Network Coprocessor (NETCP) registers area - 1MB +#define C66XX_NETCP_RG_AREA_SADDR 0x02000000 +#define C66XX_NETCP_RG_AREA_EADDR 0x020fffff +#define C66XX_NETCP_RG_AREA_LEN (C66XX_NETCP_RG_AREA_EADDR - C66XX_NETCP_RG_AREA_SADDR + 1) + +// Timer0 registers area - 128B +#define C66XX_TIMER_0_RG_AREA_SADDR 0x02200000 +#define C66XX_TIMER_0_RG_AREA_EADDR 0x0220007f +#define C66XX_TIMER_0_RG_AREA_LEN (C66XX_TIMER_0_RG_AREA_EADDR - C66XX_TIMER_0_RG_AREA_SADDR + 1) + +// Timer1 registers area - 128B +#define C66XX_TIMER_1_RG_AREA_SADDR 0x02210000 +#define C66XX_TIMER_1_RG_AREA_EADDR 0x0221007f +#define C66XX_TIMER_1_RG_AREA_LEN (C66XX_TIMER_1_RG_AREA_EADDR - C66XX_TIMER_1_RG_AREA_SADDR + 1) + +// Timer2 registers area - 128B +#define C66XX_TIMER_2_RG_AREA_SADDR 0x02220000 +#define C66XX_TIMER_2_RG_AREA_EADDR 0x0222007f +#define C66XX_TIMER_2_RG_AREA_LEN (C66XX_TIMER_2_RG_AREA_EADDR - C66XX_TIMER_2_RG_AREA_SADDR + 1) + +// Timer3 registers area - 128B +#define C66XX_TIMER_3_RG_AREA_SADDR 0x02230000 +#define C66XX_TIMER_3_RG_AREA_EADDR 0x0223007f +#define C66XX_TIMER_3_RG_AREA_LEN (C66XX_TIMER_3_RG_AREA_EADDR - C66XX_TIMER_3_RG_AREA_SADDR + 1) + +// Timer4 registers area - 128B +#define C66XX_TIMER_4_RG_AREA_SADDR 0x02240000 +#define C66XX_TIMER_4_RG_AREA_EADDR 0x0224007f +#define C66XX_TIMER_4_RG_AREA_LEN (C66XX_TIMER_4_RG_AREA_EADDR - C66XX_TIMER_4_RG_AREA_SADDR + 1) + +// Timer5 registers area - 128B +#define C66XX_TIMER_5_RG_AREA_SADDR 0x02250000 +#define C66XX_TIMER_5_RG_AREA_EADDR 0x0225007f +#define C66XX_TIMER_5_RG_AREA_LEN (C66XX_TIMER_5_RG_AREA_EADDR - C66XX_TIMER_5_RG_AREA_SADDR + 1) + +// Timer6 registers area - 128B +#define C66XX_TIMER_6_RG_AREA_SADDR 0x02260000 +#define C66XX_TIMER_6_RG_AREA_EADDR 0x0226007f +#define C66XX_TIMER_6_RG_AREA_LEN (C66XX_TIMER_6_RG_AREA_EADDR - C66XX_TIMER_6_RG_AREA_SADDR + 1) + +// Timer7 registers area - 128B +#define C66XX_TIMER_7_RG_AREA_SADDR 0x02270000 +#define C66XX_TIMER_7_RG_AREA_EADDR 0x0227007f +#define C66XX_TIMER_7_RG_AREA_LEN (C66XX_TIMER_7_RG_AREA_EADDR - C66XX_TIMER_7_RG_AREA_SADDR + 1) + +// Timer8 registers area - 128B +#define C66XX_TIMER_8_RG_AREA_SADDR 0x02280000 +#define C66XX_TIMER_8_RG_AREA_EADDR 0x0228007f +#define C66XX_TIMER_8_RG_AREA_LEN (C66XX_TIMER_8_RG_AREA_EADDR - C66XX_TIMER_8_RG_AREA_SADDR + 1) + +// Timer9 registers area - 128B +#define C66XX_TIMER_9_RG_AREA_SADDR 0x02290000 +#define C66XX_TIMER_9_RG_AREA_EADDR 0x0229007f +#define C66XX_TIMER_9_RG_AREA_LEN (C66XX_TIMER_9_RG_AREA_EADDR - C66XX_TIMER_9_RG_AREA_SADDR + 1) + +// Timer10 registers area - 128B +#define C66XX_TIMER_10_RG_AREA_SADDR 0x022a0000 +#define C66XX_TIMER_10_RG_AREA_EADDR 0x022a007f +#define C66XX_TIMER_10_RG_AREA_LEN (C66XX_TIMER_10_RG_AREA_EADDR - C66XX_TIMER_10_RG_AREA_SADDR + 1) + +// Timer11 registers area - 128B +#define C66XX_TIMER_11_RG_AREA_SADDR 0x022b0000 +#define C66XX_TIMER_11_RG_AREA_EADDR 0x022b007f +#define C66XX_TIMER_11_RG_AREA_LEN (C66XX_TIMER_11_RG_AREA_EADDR - C66XX_TIMER_11_RG_AREA_SADDR + 1) + +// Timer12 registers area - 128B +#define C66XX_TIMER_12_RG_AREA_SADDR 0x022c0000 +#define C66XX_TIMER_12_RG_AREA_EADDR 0x022c007f +#define C66XX_TIMER_12_RG_AREA_LEN (C66XX_TIMER_12_RG_AREA_EADDR - C66XX_TIMER_12_RG_AREA_SADDR + 1) + +// Timer13 registers area - 128B +#define C66XX_TIMER_13_RG_AREA_SADDR 0x022d0000 +#define C66XX_TIMER_13_RG_AREA_EADDR 0x022d007f +#define C66XX_TIMER_13_RG_AREA_LEN (C66XX_TIMER_13_RG_AREA_EADDR - C66XX_TIMER_13_RG_AREA_SADDR + 1) + +// Timer14 registers area - 128B +#define C66XX_TIMER_14_RG_AREA_SADDR 0x022e0000 +#define C66XX_TIMER_14_RG_AREA_EADDR 0x022e007f +#define C66XX_TIMER_14_RG_AREA_LEN (C66XX_TIMER_14_RG_AREA_EADDR - C66XX_TIMER_14_RG_AREA_SADDR + 1) + +// Timer15 registers area - 128B +#define C66XX_TIMER_15_RG_AREA_SADDR 0x022f0000 +#define C66XX_TIMER_15_RG_AREA_EADDR 0x022f007f +#define C66XX_TIMER_15_RG_AREA_LEN (C66XX_TIMER_15_RG_AREA_EADDR - C66XX_TIMER_15_RG_AREA_SADDR + 1) + +// PLL controller registers area - 512B +#define C66XX_PLL_RG_AREA_SADDR 0x02310000 +#define C66XX_PLL_RG_AREA_EADDR 0x023101ff +#define C66XX_PLL_RG_AREA_LEN (C66XX_PLL_RG_AREA_EADDR - C66XX_PLL_RG_AREA_SADDR + 1) + +// GPIO registers area - 256B +#define C66XX_GPIO_RG_AREA_SADDR 0x02320000 +#define C66XX_GPIO_RG_AREA_EADDR 0x023200ff +#define C66XX_GPIO_RG_AREA_LEN (C66XX_GPIO_RG_AREA_EADDR - C66XX_GPIO_RG_AREA_SADDR + 1) + +// SmartReflex registers area - 256B +#define C66XX_SMARTREFLEX_RG_AREA_SADDR 0x02330000 +#define C66XX_SMARTREFLEX_RG_AREA_EADDR 0x023303ff +#define C66XX_SMARTREFLEX_RG_AREA_LEN (C66XX_SMARTREFLEX_RG_AREA_EADDR - C66XX_SMARTREFLEX_RG_AREA_SADDR + 1) + +// Power Sleep Controller (PSC) registers area - 4KB +#define C66XX_PSC_RG_AREA_SADDR 0x02350000 +#define C66XX_PSC_RG_AREA_EADDR 0x02350fff +#define C66XX_PSC_RG_AREA_LEN (C66XX_PSC_RG_AREA_EADDR - C66XX_PSC_RG_AREA_SADDR + 1) + +// Memory Protection Unit (MPU) 0 registers area - 1KB +#define C66XX_MPU_0_RG_AREA_SADDR 0x02360000 +#define C66XX_MPU_0_RG_AREA_EADDR 0x023603ff +#define C66XX_MPU_0_RG_AREA_LEN (C66XX_MPU_0_RG_AREA_EADDR - C66XX_MPU_0_RG_AREA_SADDR + 1) + +// Memory Protection Unit (MPU) 1 registers area - 1KB +#define C66XX_MPU_1_RG_AREA_SADDR 0x02368000 +#define C66XX_MPU_1_RG_AREA_EADDR 0x023683ff +#define C66XX_MPU_1_RG_AREA_LEN (C66XX_MPU_1_RG_AREA_EADDR - C66XX_MPU_1_RG_AREA_SADDR + 1) + +// Memory Protection Unit (MPU) 2 registers area - 1KB +#define C66XX_MPU_2_RG_AREA_SADDR 0x02370000 +#define C66XX_MPU_2_RG_AREA_EADDR 0x023703ff +#define C66XX_MPU_2_RG_AREA_LEN (C66XX_MPU_2_RG_AREA_EADDR - C66XX_MPU_2_RG_AREA_SADDR + 1) + +// Memory Protection Unit (MPU) 3 registers area - 1KB +#define C66XX_MPU_3_RG_AREA_SADDR 0x02378000 +#define C66XX_MPU_3_RG_AREA_EADDR 0x023783ff +#define C66XX_MPU_3_RG_AREA_LEN (C66XX_MPU_3_RG_AREA_EADDR - C66XX_MPU_3_RG_AREA_SADDR + 1) + +// Debug subsystem configuration registers area - 256KB +#define C66XX_DEBUG_CFG_RG_AREA_SADDR 0x02400000 +#define C66XX_DEBUG_CFG_RG_AREA_EADDR 0x0243ffff +#define C66XX_DEBUG_CFG_RG_AREA_LEN (C66XX_DEBUG_CFG_RG_AREA_EADDR - C66XX_DEBUG_CFG_RG_AREA_SADDR + 1) + +// DSP trace formatter 0 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_SADDR 0x02440000 +#define C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_EADDR 0x02443fff +#define C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_0_RG_AREA_SADDR + 1) + +// DSP trace formatter 1 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_SADDR 0x02450000 +#define C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_EADDR 0x02453fff +#define C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_1_RG_AREA_SADDR + 1) + +// DSP trace formatter 2 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_SADDR 0x02460000 +#define C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_EADDR 0x02463fff +#define C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_2_RG_AREA_SADDR + 1) + +// DSP trace formatter 3 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_SADDR 0x02470000 +#define C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_EADDR 0x02473fff +#define C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_3_RG_AREA_SADDR + 1) + +// DSP trace formatter 4 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_SADDR 0x02480000 +#define C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_EADDR 0x02483fff +#define C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_4_RG_AREA_SADDR + 1) + +// DSP trace formatter 5 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_SADDR 0x02490000 +#define C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_EADDR 0x02493fff +#define C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_5_RG_AREA_SADDR + 1) + +// DSP trace formatter 6 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_SADDR 0x024a0000 +#define C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_EADDR 0x024a3fff +#define C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_6_RG_AREA_SADDR + 1) + +// DSP trace formatter 7 registers area - 16KB +#define C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_SADDR 0x024b0000 +#define C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_EADDR 0x024b3fff +#define C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_LEN (C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_EADDR - C66XX_DSP_TRACE_FORMATTER_7_RG_AREA_SADDR + 1) + +// I2C registers area - 128B +#define C66XX_I2C_RG_AREA_SADDR 0x02530000 +#define C66XX_I2C_RG_AREA_EADDR 0x0253007f +#define C66XX_I2C_RG_AREA_LEN (C66XX_I2C_RG_AREA_EADDR - C66XX_I2C_RG_AREA_SADDR + 1) + +// UART registers area - 64B +#define C66XX_UART_RG_AREA_SADDR 0x02540000 +#define C66XX_UART_RG_AREA_EADDR 0x0254003f +#define C66XX_UART_RG_AREA_LEN (C66XX_UART_RG_AREA_EADDR - C66XX_UART_RG_AREA_SADDR + 1) + +// Chip Interrupt Controller (CIC) 0 registers area - 8KB +#define C66XX_CIC_0_RG_AREA_SADDR 0x02600000 +#define C66XX_CIC_0_RG_AREA_EADDR 0x02601fff +#define C66XX_CIC_0_RG_AREA_LEN (C66XX_CIC_0_RG_AREA_EADDR - C66XX_CIC_0_RG_AREA_SADDR + 1) + +// Chip Interrupt Controller (CIC) 1 registers area - 8KB +#define C66XX_CIC_1_RG_AREA_SADDR 0x02604000 +#define C66XX_CIC_1_RG_AREA_EADDR 0x02605fff +#define C66XX_CIC_1_RG_AREA_LEN (C66XX_CIC_1_RG_AREA_EADDR - C66XX_CIC_1_RG_AREA_SADDR + 1) + +// Chip Interrupt Controller (CIC) 2 registers area - 8KB +#define C66XX_CIC_2_RG_AREA_SADDR 0x02608000 +#define C66XX_CIC_2_RG_AREA_EADDR 0x02609fff +#define C66XX_CIC_2_RG_AREA_LEN (C66XX_CIC_2_RG_AREA_EADDR - C66XX_CIC_2_RG_AREA_SADDR + 1) + +// Chip Interrupt Controller (CIC) 3 registers area - 8KB +#define C66XX_CIC_3_RG_AREA_SADDR 0x0260c000 +#define C66XX_CIC_3_RG_AREA_EADDR 0x0260dfff +#define C66XX_CIC_3_RG_AREA_LEN (C66XX_CIC_3_RG_AREA_EADDR - C66XX_CIC_3_RG_AREA_SADDR + 1) + +// Device State Control registers area - 2KB +#define C66XX_BOOTCFG_RG_AREA_SADDR 0x02620000 +#define C66XX_BOOTCFG_RG_AREA_EADDR 0x026207ff +#define C66XX_BOOTCFG_RG_AREA_LEN (C66XX_BOOTCFG_RG_AREA_EADDR - C66XX_BOOTCFG_RG_AREA_SADDR + 1) + +// Semaphore (SEM) registers area - 2KB +#define C66XX_SEM_RG_AREA_SADDR 0x02640000 +#define C66XX_SEM_RG_AREA_EADDR 0x026407ff +#define C66XX_SEM_RG_AREA_LEN (C66XX_SEM_RG_AREA_EADDR - C66XX_SEM_RG_AREA_SADDR + 1) + +// EDMA3 Channel Controller (EDMA3CC) 0 registers area - 32KB +#define C66XX_EDMA3CC_0_RG_AREA_SADDR 0x02700000 +#define C66XX_EDMA3CC_0_RG_AREA_EADDR 0x02707fff +#define C66XX_EDMA3CC_0_RG_AREA_LEN (C66XX_EDMA3CC_0_RG_AREA_EADDR - C66XX_EDMA3CC_0_RG_AREA_SADDR + 1) + +// EDMA3 Channel Controller (EDMA3CC) 1 registers area - 32KB +#define C66XX_EDMA3CC_1_RG_AREA_SADDR 0x02720000 +#define C66XX_EDMA3CC_1_RG_AREA_EADDR 0x02727fff +#define C66XX_EDMA3CC_1_RG_AREA_LEN (C66XX_EDMA3CC_1_RG_AREA_EADDR - C66XX_EDMA3CC_1_RG_AREA_SADDR + 1) + +// EDMA3 Channel Controller (EDMA3CC) 2 registers area - 32KB +#define C66XX_EDMA3CC_2_RG_AREA_SADDR 0x02740000 +#define C66XX_EDMA3CC_2_RG_AREA_EADDR 0x02747fff +#define C66XX_EDMA3CC_2_RG_AREA_LEN (C66XX_EDMA3CC_2_RG_AREA_EADDR - C66XX_EDMA3CC_2_RG_AREA_SADDR + 1) + +// EDMA3CC0 Transfer Controller (EDMA3TC) 0 registers area - 1KB +#define C66XX_EDMA3CC_0_TC_0_RG_AREA_SADDR 0x02760000 +#define C66XX_EDMA3CC_0_TC_0_RG_AREA_EADDR 0x027603ff +#define C66XX_EDMA3CC_0_TC_0_RG_AREA_LEN (C66XX_EDMA3CC_0_TC_0_RG_AREA_EADDR - C66XX_EDMA3CC_0_TC_0_RG_AREA_SADDR + 1) + +// EDMA3CC0 Transfer Controller (EDMA3TC) 1 registers area - 1KB +#define C66XX_EDMA3CC_0_TC_1_RG_AREA_SADDR 0x02768000 +#define C66XX_EDMA3CC_0_TC_1_RG_AREA_EADDR 0x027683ff +#define C66XX_EDMA3CC_0_TC_1_RG_AREA_LEN (C66XX_EDMA3CC_0_TC_1_RG_AREA_EADDR - C66XX_EDMA3CC_0_TC_1_RG_AREA_SADDR + 1) + +// EDMA3CC1 Transfer Controller (EDMA3TC) 0 registers area - 1KB +#define C66XX_EDMA3CC_1_TC_0_RG_AREA_SADDR 0x02770000 +#define C66XX_EDMA3CC_1_TC_0_RG_AREA_EADDR 0x027703ff +#define C66XX_EDMA3CC_1_TC_0_RG_AREA_LEN (C66XX_EDMA3CC_1_TC_0_RG_AREA_EADDR - C66XX_EDMA3CC_1_TC_0_RG_AREA_SADDR + 1) + +// EDMA3CC1 Transfer Controller (EDMA3TC) 1 registers area - 1KB +#define C66XX_EDMA3CC_1_TC_1_RG_AREA_SADDR 0x02778000 +#define C66XX_EDMA3CC_1_TC_1_RG_AREA_EADDR 0x027783ff +#define C66XX_EDMA3CC_1_TC_1_RG_AREA_LEN (C66XX_EDMA3CC_1_TC_1_RG_AREA_EADDR - C66XX_EDMA3CC_1_TC_1_RG_AREA_SADDR + 1) + +// EDMA3CC1 Transfer Controller (EDMA3TC) 2 registers area - 1KB +#define C66XX_EDMA3CC_1_TC_2_RG_AREA_SADDR 0x02780000 +#define C66XX_EDMA3CC_1_TC_2_RG_AREA_EADDR 0x027803ff +#define C66XX_EDMA3CC_1_TC_2_RG_AREA_LEN (C66XX_EDMA3CC_1_TC_2_RG_AREA_EADDR - C66XX_EDMA3CC_1_TC_2_RG_AREA_SADDR + 1) + +// EDMA3CC1 Transfer Controller (EDMA3TC) 3 registers area - 1KB +#define C66XX_EDMA3CC_1_TC_3_RG_AREA_SADDR 0x02788000 +#define C66XX_EDMA3CC_1_TC_3_RG_AREA_EADDR 0x027883ff +#define C66XX_EDMA3CC_1_TC_3_RG_AREA_LEN (C66XX_EDMA3CC_1_TC_3_RG_AREA_EADDR - C66XX_EDMA3CC_1_TC_3_RG_AREA_SADDR + 1) + +// EDMA3CC2 Transfer Controller (EDMA3TC) 0 registers area - 1KB +#define C66XX_EDMA3CC_2_TC_0_RG_AREA_SADDR 0x02790000 +#define C66XX_EDMA3CC_2_TC_0_RG_AREA_EADDR 0x027903ff +#define C66XX_EDMA3CC_2_TC_0_RG_AREA_LEN (C66XX_EDMA3CC_2_TC_0_RG_AREA_EADDR - C66XX_EDMA3CC_2_TC_0_RG_AREA_SADDR + 1) + +// EDMA3CC2 Transfer Controller (EDMA3TC) 1 registers area - 1KB +#define C66XX_EDMA3CC_2_TC_1_RG_AREA_SADDR 0x02798000 +#define C66XX_EDMA3CC_2_TC_1_RG_AREA_EADDR 0x027983ff +#define C66XX_EDMA3CC_2_TC_1_RG_AREA_LEN (C66XX_EDMA3CC_2_TC_1_RG_AREA_EADDR - C66XX_EDMA3CC_2_TC_1_RG_AREA_SADDR + 1) + +// EDMA3CC2 Transfer Controller (EDMA3TC) 2 registers area - 1KB +#define C66XX_EDMA3CC_2_TC_2_RG_AREA_SADDR 0x027a0000 +#define C66XX_EDMA3CC_2_TC_2_RG_AREA_EADDR 0x027a03ff +#define C66XX_EDMA3CC_2_TC_2_RG_AREA_LEN (C66XX_EDMA3CC_2_TC_2_RG_AREA_EADDR - C66XX_EDMA3CC_2_TC_2_RG_AREA_SADDR + 1) + +// EDMA3CC2 Transfer Controller (EDMA3TC) 3 registers area - 1KB +#define C66XX_EDMA3CC_2_TC_3_RG_AREA_SADDR 0x027a8000 +#define C66XX_EDMA3CC_2_TC_3_RG_AREA_EADDR 0x027a83ff +#define C66XX_EDMA3CC_2_TC_3_RG_AREA_LEN (C66XX_EDMA3CC_2_TC_3_RG_AREA_EADDR - C66XX_EDMA3CC_2_TC_3_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac0 registers area - 4KB +#define C66XX_TETB_0_RG_AREA_SADDR 0x027d0000 +#define C66XX_TETB_0_RG_AREA_EADDR 0x027d0fff +#define C66XX_TETB_0_RG_AREA_LEN (C66XX_TETB_0_RG_AREA_EADDR - C66XX_TETB_0_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac1 registers area - 4KB +#define C66XX_TETB_1_RG_AREA_SADDR 0x027e0000 +#define C66XX_TETB_1_RG_AREA_EADDR 0x027e0fff +#define C66XX_TETB_1_RG_AREA_LEN (C66XX_TETB_1_RG_AREA_EADDR - C66XX_TETB_1_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac2 registers area - 4KB +#define C66XX_TETB_2_RG_AREA_SADDR 0x027f0000 +#define C66XX_TETB_2_RG_AREA_EADDR 0x027f0fff +#define C66XX_TETB_2_RG_AREA_LEN (C66XX_TETB_2_RG_AREA_EADDR - C66XX_TETB_2_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac3 registers area - 4KB +#define C66XX_TETB_3_RG_AREA_SADDR 0x02800000 +#define C66XX_TETB_3_RG_AREA_EADDR 0x02800fff +#define C66XX_TETB_3_RG_AREA_LEN (C66XX_TETB_3_RG_AREA_EADDR - C66XX_TETB_3_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac4 registers area - 4KB +#define C66XX_TETB_4_RG_AREA_SADDR 0x02810000 +#define C66XX_TETB_4_RG_AREA_EADDR 0x02810fff +#define C66XX_TETB_4_RG_AREA_LEN (C66XX_TETB_4_RG_AREA_EADDR - C66XX_TETB_4_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac5 registers area - 4KB +#define C66XX_TETB_5_RG_AREA_SADDR 0x02820000 +#define C66XX_TETB_5_RG_AREA_EADDR 0x02820fff +#define C66XX_TETB_5_RG_AREA_LEN (C66XX_TETB_5_RG_AREA_EADDR - C66XX_TETB_5_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac6 registers area - 4KB +#define C66XX_TETB_6_RG_AREA_SADDR 0x02830000 +#define C66XX_TETB_6_RG_AREA_EADDR 0x02830fff +#define C66XX_TETB_6_RG_AREA_LEN (C66XX_TETB_6_RG_AREA_EADDR - C66XX_TETB_6_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) CorePac7 registers area - 4KB +#define C66XX_TETB_7_RG_AREA_SADDR 0x02840000 +#define C66XX_TETB_7_RG_AREA_EADDR 0x02840fff +#define C66XX_TETB_7_RG_AREA_LEN (C66XX_TETB_7_RG_AREA_EADDR - C66XX_TETB_7_RG_AREA_SADDR + 1) + +// TI embedded trace buffer (TETB) system registers area - 32KB +#define C66XX_TETB_SYSTEM_RG_AREA_SADDR 0x02850000 +#define C66XX_TETB_SYSTEM_RG_AREA_EADDR 0x02857fff +#define C66XX_TETB_SYSTEM_RG_AREA_LEN (C66XX_TETB_SYSTEM_RG_AREA_EADDR - C66XX_TETB_SYSTEM_RG_AREA_SADDR + 1) + +// Serial RapidIO (SRIO) configuration registers area - 132KB +#define C66XX_SRIO_RG_AREA_SADDR 0x02900000 +#define C66XX_SRIO_RG_AREA_EADDR 0x02920fff +#define C66XX_SRIO_RG_AREA_LEN (C66XX_SRIO_RG_AREA_EADDR - C66XX_SRIO_RG_AREA_SADDR + 1) + +// Queue manager subsystem (QMSS) configuration registers area - 2MB +#define C66XX_QMSS_RG_AREA_SADDR 0x02a00000 +#define C66XX_QMSS_RG_AREA_EADDR 0x02bfffff +#define C66XX_QMSS_RG_AREA_LEN (C66XX_QMSS_RG_AREA_EADDR - C66XX_QMSS_RG_AREA_SADDR + 1) + +// Extended memory controller (XMC) configuration registers area - 64KB +#define C66XX_XMC_RG_AREA_SADDR 0x08000000 +#define C66XX_XMC_RG_AREA_EADDR 0x0800ffff +#define C66XX_XMC_RG_AREA_LEN (C66XX_XMC_RG_AREA_EADDR - C66XX_XMC_RG_AREA_SADDR + 1) + +// Multicore shared memory controller (MSMC) configuration registers area - 1MB +#define C66XX_MSMC_RG_AREA_SADDR 0x0bc00000 +#define C66XX_MSMC_RG_AREA_EADDR 0x0bcfffff +#define C66XX_MSMC_RG_AREA_LEN (C66XX_MSMC_RG_AREA_EADDR - C66XX_MSMC_RG_AREA_SADDR + 1) + +// Multicore shared memory (MSM) area - 4MB +#define C66XX_MSM_SRAM_AREA_SADDR 0x0c000000 +#define C66XX_MSM_SRAM_AREA_EADDR 0x0c3fffff +#define C66XX_MSM_SRAM_AREA_LEN (C66XX_MSM_SRAM_AREA_EADDR - C66XX_MSM_SRAM_AREA_SADDR + 1) + +// CorePac0 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_0_L2_SRAM_SADDR 0x10800000 +#define C66XX_DSP_0_L2_SRAM_EADDR 0x1087ffff +#define C66XX_DSP_0_L2_SRAM_LEN (C66XX_DSP_0_L2_SRAM_EADDR - C66XX_DSP_0_L2_SRAM_SADDR + 1) + +// CorePac0 L1P SRAM - 32KB +#define C66XX_DSP_0_L1P_SRAM_SADDR 0x10e00000 +#define C66XX_DSP_0_L1P_SRAM_EADDR 0x10e07fff +#define C66XX_DSP_0_L1P_SRAM_LEN (C66XX_DSP_0_L1P_SRAM_EADDR - C66XX_DSP_0_L1P_SRAM_SADDR + 1) + +// CorePac0 L1D SRAM - 32KB +#define C66XX_DSP_0_L1D_SRAM_SADDR 0x10f00000 +#define C66XX_DSP_0_L1D_SRAM_EADDR 0x10f07fff +#define C66XX_DSP_0_L1D_SRAM_LEN (C66XX_DSP_0_L1D_SRAM_EADDR - C66XX_DSP_0_L1D_SRAM_SADDR + 1) + +// CorePac1 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_1_L2_SRAM_SADDR 0x11800000 +#define C66XX_DSP_1_L2_SRAM_EADDR 0x1187ffff +#define C66XX_DSP_1_L2_SRAM_LEN (C66XX_DSP_1_L2_SRAM_EADDR - C66XX_DSP_1_L2_SRAM_SADDR + 1) + +// CorePac1 L1P SRAM - 32KB +#define C66XX_DSP_1_L1P_SRAM_SADDR 0x11e00000 +#define C66XX_DSP_1_L1P_SRAM_EADDR 0x11e07fff +#define C66XX_DSP_1_L1P_SRAM_LEN (C66XX_DSP_1_L1P_SRAM_EADDR - C66XX_DSP_1_L1P_SRAM_SADDR + 1) + +// CorePac1 L1D SRAM - 32KB +#define C66XX_DSP_1_L1D_SRAM_SADDR 0x11f00000 +#define C66XX_DSP_1_L1D_SRAM_EADDR 0x11f07fff +#define C66XX_DSP_1_L1D_SRAM_LEN (C66XX_DSP_1_L1D_SRAM_EADDR - C66XX_DSP_1_L1D_SRAM_SADDR + 1) + +// CorePac2 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_2_L2_SRAM_SADDR 0x12800000 +#define C66XX_DSP_2_L2_SRAM_EADDR 0x1287ffff +#define C66XX_DSP_2_L2_SRAM_LEN (C66XX_DSP_2_L2_SRAM_EADDR - C66XX_DSP_2_L2_SRAM_SADDR + 1) + +// CorePac2 L1P SRAM - 32KB +#define C66XX_DSP_2_L1P_SRAM_SADDR 0x12e00000 +#define C66XX_DSP_2_L1P_SRAM_EADDR 0x12e07fff +#define C66XX_DSP_2_L1P_SRAM_LEN (C66XX_DSP_2_L1P_SRAM_EADDR - C66XX_DSP_2_L1P_SRAM_SADDR + 1) + +// CorePac2 L1D SRAM - 32KB +#define C66XX_DSP_2_L1D_SRAM_SADDR 0x12f00000 +#define C66XX_DSP_2_L1D_SRAM_EADDR 0x12f07fff +#define C66XX_DSP_2_L1D_SRAM_LEN (C66XX_DSP_2_L1D_SRAM_EADDR - C66XX_DSP_2_L1D_SRAM_SADDR + 1) + +// CorePac3 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_3_L2_SRAM_SADDR 0x13800000 +#define C66XX_DSP_3_L2_SRAM_EADDR 0x1387ffff +#define C66XX_DSP_3_L2_SRAM_LEN (C66XX_DSP_3_L2_SRAM_EADDR - C66XX_DSP_3_L2_SRAM_SADDR + 1) + +// CorePac3 L1P SRAM - 32KB +#define C66XX_DSP_3_L1P_SRAM_SADDR 0x13e00000 +#define C66XX_DSP_3_L1P_SRAM_EADDR 0x13e07fff +#define C66XX_DSP_3_L1P_SRAM_LEN (C66XX_DSP_3_L1P_SRAM_EADDR - C66XX_DSP_3_L1P_SRAM_SADDR + 1) + +// CorePac3 L1D SRAM - 32KB +#define C66XX_DSP_3_L1D_SRAM_SADDR 0x13f00000 +#define C66XX_DSP_3_L1D_SRAM_EADDR 0x13f07fff +#define C66XX_DSP_3_L1D_SRAM_LEN (C66XX_DSP_3_L1D_SRAM_EADDR - C66XX_DSP_3_L1D_SRAM_SADDR + 1) + +// CorePac4 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_4_L2_SRAM_SADDR 0x14800000 +#define C66XX_DSP_4_L2_SRAM_EADDR 0x1487ffff +#define C66XX_DSP_4_L2_SRAM_LEN (C66XX_DSP_4_L2_SRAM_EADDR - C66XX_DSP_4_L2_SRAM_SADDR + 1) + +// CorePac4 L1P SRAM - 32KB +#define C66XX_DSP_4_L1P_SRAM_SADDR 0x14e00000 +#define C66XX_DSP_4_L1P_SRAM_EADDR 0x14e07fff +#define C66XX_DSP_4_L1P_SRAM_LEN (C66XX_DSP_4_L1P_SRAM_EADDR - C66XX_DSP_4_L1P_SRAM_SADDR + 1) + +// CorePac4 L1D SRAM - 32KB +#define C66XX_DSP_4_L1D_SRAM_SADDR 0x14f00000 +#define C66XX_DSP_4_L1D_SRAM_EADDR 0x14f07fff +#define C66XX_DSP_4_L1D_SRAM_LEN (C66XX_DSP_4_L1D_SRAM_EADDR - C66XX_DSP_4_L1D_SRAM_SADDR + 1) + +// CorePac5 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_5_L2_SRAM_SADDR 0x15800000 +#define C66XX_DSP_5_L2_SRAM_EADDR 0x1587ffff +#define C66XX_DSP_5_L2_SRAM_LEN (C66XX_DSP_5_L2_SRAM_EADDR - C66XX_DSP_5_L2_SRAM_SADDR + 1) + +// CorePac5 L1P SRAM - 32KB +#define C66XX_DSP_5_L1P_SRAM_SADDR 0x15e00000 +#define C66XX_DSP_5_L1P_SRAM_EADDR 0x15e07fff +#define C66XX_DSP_5_L1P_SRAM_LEN (C66XX_DSP_5_L1P_SRAM_EADDR - C66XX_DSP_5_L1P_SRAM_SADDR + 1) + +// CorePac5 L1D SRAM - 32KB +#define C66XX_DSP_5_L1D_SRAM_SADDR 0x15f00000 +#define C66XX_DSP_5_L1D_SRAM_EADDR 0x15f07fff +#define C66XX_DSP_5_L1D_SRAM_LEN (C66XX_DSP_5_L1D_SRAM_EADDR - C66XX_DSP_5_L1D_SRAM_SADDR + 1) + +// CorePac6 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_6_L2_SRAM_SADDR 0x16800000 +#define C66XX_DSP_6_L2_SRAM_EADDR 0x1687ffff +#define C66XX_DSP_6_L2_SRAM_LEN (C66XX_DSP_6_L2_SRAM_EADDR - C66XX_DSP_6_L2_SRAM_SADDR + 1) + +// CorePac6 L1P SRAM - 32KB +#define C66XX_DSP_6_L1P_SRAM_SADDR 0x16e00000 +#define C66XX_DSP_6_L1P_SRAM_EADDR 0x16e07fff +#define C66XX_DSP_6_L1P_SRAM_LEN (C66XX_DSP_6_L1P_SRAM_EADDR - C66XX_DSP_6_L1P_SRAM_SADDR + 1) + +// CorePac6 L1D SRAM - 32KB +#define C66XX_DSP_6_L1D_SRAM_SADDR 0x16f00000 +#define C66XX_DSP_6_L1D_SRAM_EADDR 0x16f07fff +#define C66XX_DSP_6_L1D_SRAM_LEN (C66XX_DSP_6_L1D_SRAM_EADDR - C66XX_DSP_6_L1D_SRAM_SADDR + 1) + +// CorePac7 L2 SRAM (address to access from external masters) - 512KB +#define C66XX_DSP_7_L2_SRAM_SADDR 0x17800000 +#define C66XX_DSP_7_L2_SRAM_EADDR 0x1787ffff +#define C66XX_DSP_7_L2_SRAM_LEN (C66XX_DSP_7_L2_SRAM_EADDR - C66XX_DSP_7_L2_SRAM_SADDR + 1) + +// CorePac7 L1P SRAM - 32KB +#define C66XX_DSP_7_L1P_SRAM_SADDR 0x17e00000 +#define C66XX_DSP_7_L1P_SRAM_EADDR 0x17e07fff +#define C66XX_DSP_7_L1P_SRAM_LEN (C66XX_DSP_7_L1P_SRAM_EADDR - C66XX_DSP_7_L1P_SRAM_SADDR + 1) + +// CorePac7 L1D SRAM - 32KB +#define C66XX_DSP_7_L1D_SRAM_SADDR 0x17f00000 +#define C66XX_DSP_7_L1D_SRAM_EADDR 0x17f07fff +#define C66XX_DSP_7_L1D_SRAM_LEN (C66XX_DSP_7_L1D_SRAM_EADDR - C66XX_DSP_7_L1D_SRAM_SADDR + 1) + +// System trace manager (STM) configuration registers area - 1MB +#define C66XX_STM_RG_AREA_SADDR 0x20000000 +#define C66XX_STM_RG_AREA_EADDR 0x200fffff +#define C66XX_STM_RG_AREA_LEN (C66XX_STM_RG_AREA_EADDR - C66XX_STM_RG_AREA_SADDR + 1) + +// Boot ROM - 128KB +#define C66XX_BOOT_ROM_SADDR 0x20b00000 +#define C66XX_BOOT_ROM_EADDR 0x20b1ffff +#define C66XX_BOOT_ROM_LEN (C66XX_BOOT_ROM_EADDR - C66XX_BOOT_ROM_SADDR + 1) + +// SPI configuration registers area - 512B +#define C66XX_SPI_RG_AREA_SADDR 0x20bf0000 +#define C66XX_SPI_RG_AREA_EADDR 0x20bf01ff +#define C66XX_SPI_RG_AREA_LEN (C66XX_SPI_RG_AREA_EADDR - C66XX_SPI_RG_AREA_SADDR + 1) + +// EMIF16 configuration registers area - 256B +#define C66XX_EMIF16_RG_AREA_SADDR 0x20c00000 +#define C66XX_EMIF16_RG_AREA_EADDR 0x20c000ff +#define C66XX_EMIF16_RG_AREA_LEN (C66XX_EMIF16_RG_AREA_EADDR - C66XX_EMIF16_RG_AREA_SADDR + 1) + +// DDR3 EMIF configuration registers area - 512B +#define C66XX_DDR3_EMIF_RG_AREA_SADDR 0x21000000 +#define C66XX_DDR3_EMIF_RG_AREA_EADDR 0x210001ff +#define C66XX_DDR3_EMIF_RG_AREA_LEN (C66XX_DDR3_EMIF_RG_AREA_EADDR - C66XX_DDR3_EMIF_RG_AREA_SADDR + 1) + +// HyperLink configuration registers area - 256B +#define C66XX_HYPERLINK_RG_AREA_SADDR 0x21400000 +#define C66XX_HYPERLINK_RG_AREA_EADDR 0x214000ff +#define C66XX_HYPERLINK_RG_AREA_LEN (C66XX_HYPERLINK_RG_AREA_EADDR - C66XX_HYPERLINK_RG_AREA_SADDR + 1) + +// PCIe configuration registers area - 32KB +#define C66XX_PCIE_RG_AREA_SADDR 0x21800000 +#define C66XX_PCIE_RG_AREA_EADDR 0x21807fff +#define C66XX_PCIE_RG_AREA_LEN (C66XX_PCIE_RG_AREA_EADDR - C66XX_PCIE_RG_AREA_SADDR + 1) + +// Queue manager subsystem (QMSS) data area - 2MB +#define C66XX_QMSS_DATA_AREA_SADDR 0x34000000 +#define C66XX_QMSS_DATA_AREA_EADDR 0x341fffff +#define C66XX_QMSS_DATA_AREA_LEN (C66XX_QMSS_DATA_AREA_EADDR - C66XX_QMSS_DATA_AREA_SADDR + 1) + +// HyperLink data area - 256MB +#define C66XX_HYPERLINK_DATA_AREA_SADDR 0x40000000 +#define C66XX_HYPERLINK_DATA_AREA_EADDR 0x4fffffff +#define C66XX_HYPERLINK_DATA_AREA_LEN (C66XX_HYPERLINK_DATA_AREA_EADDR - C66XX_HYPERLINK_DATA_AREA_SADDR + 1) + +// PCIe data area - 256MB +#define C66XX_PCIE_DATA_AREA_SADDR 0x60000000 +#define C66XX_PCIE_DATA_AREA_EADDR 0x6fffffff +#define C66XX_PCIE_DATA_AREA_LEN (C66XX_PCIE_DATA_AREA_EADDR - C66XX_PCIE_DATA_AREA_SADDR + 1) + +// EMIF16 CE0 area - 64MB +#define C66XX_EMIF16_CE0_AREA_SADDR 0x70000000 +#define C66XX_EMIF16_CE0_AREA_EADDR 0x73ffffff +#define C66XX_EMIF16_CE0_AREA_LEN (C66XX_EMIF16_CE0_AREA_EADDR - C66XX_EMIF16_CE0_AREA_SADDR + 1) + +// EMIF16 CE1 area - 64MB +#define C66XX_EMIF16_CE1_AREA_SADDR 0x74000000 +#define C66XX_EMIF16_CE1_AREA_EADDR 0x77ffffff +#define C66XX_EMIF16_CE1_AREA_LEN (C66XX_EMIF16_CE1_AREA_EADDR - C66XX_EMIF16_CE1_AREA_SADDR + 1) + +// EMIF16 CE2 area - 64MB +#define C66XX_EMIF16_CE2_AREA_SADDR 0x78000000 +#define C66XX_EMIF16_CE2_AREA_EADDR 0x7bffffff +#define C66XX_EMIF16_CE2_AREA_LEN (C66XX_EMIF16_CE2_AREA_EADDR - C66XX_EMIF16_CE2_AREA_SADDR + 1) + +// EMIF16 CE3 area - 64MB +#define C66XX_EMIF16_CE3_AREA_SADDR 0x7c000000 +#define C66XX_EMIF16_CE3_AREA_EADDR 0x7fffffff +#define C66XX_EMIF16_CE3_AREA_LEN (C66XX_EMIF16_CE3_AREA_EADDR - C66XX_EMIF16_CE3_AREA_SADDR + 1) + +// DDR3 EMIF data area - 2GB +#define C66XX_DDR3_AREA_SADDR 0x80000000 +#define C66XX_DDR3_AREA_EADDR 0xffffffff +#define C66XX_DDR3_AREA_LEN (C66XX_DDR3_AREA_EADDR - C66XX_DDR3_AREA_SADDR + 1) + +//============================================================================= +#endif /* __C66XX_SELECT_C6678_DSP__ */ + + + +//============================================================================= +//============ DSP core registers ============================================= +//============================================================================= +// DSP CorePack revision register - r-only +#define C66XX_CORE_MM_REVID_RG_ADDR 0x01812000 + +//------------ DSP CorePack revision register defs ---------------------------- +#define C66XX_CORE_MM_REVID_VERSION_BITMASK 0xffff0000 +#define C66XX_CORE_MM_REVID_VERSION_BITSHIFT 16 +#define C66XX_CORE_MM_REVID_REVISION_BITMASK 0x0000ffff +#define C66XX_CORE_MM_REVID_REVISION_BITSHIFT 0 + +#define C66XX_CORE_MM_REVID_VERSION_C6678 0x0008 +#define C66XX_CORE_MM_REVID_REVISION_1_0 0x0 +#define C66XX_CORE_MM_REVID_REVISION_2_0 0x1 + + +// DSP interrupt controller registers addresses + +// DSP Event Flag register 0 - r-only +#define C66XX_CORE_EVTFLAG0_RG_ADDR 0x01800000 +// DSP Event Flag register 1 - r-only +#define C66XX_CORE_EVTFLAG1_RG_ADDR 0x01800004 +// DSP Event Flag register 2 - r-only +#define C66XX_CORE_EVTFLAG2_RG_ADDR 0x01800008 +// DSP Event Flag register 3 - r-only +#define C66XX_CORE_EVTFLAG3_RG_ADDR 0x0180000c +// DSP Event Set register 0 - r/w +#define C66XX_CORE_EVTSET0_RG_ADDR 0x01800020 +// DSP Event Set register 1 - r/w +#define C66XX_CORE_EVTSET1_RG_ADDR 0x01800024 +// DSP Event Set register 2 - r/w +#define C66XX_CORE_EVTSET2_RG_ADDR 0x01800028 +// DSP Event Set register 3 - r/w +#define C66XX_CORE_EVTSET3_RG_ADDR 0x0180002c +// DSP Event Clear register 0 - r/w +#define C66XX_CORE_EVTCLR0_RG_ADDR 0x01800040 +// DSP Event Clear register 1 - r/w +#define C66XX_CORE_EVTCLR1_RG_ADDR 0x01800044 +// DSP Event Clear register 2 - r/w +#define C66XX_CORE_EVTCLR2_RG_ADDR 0x01800048 +// DSP Event Clear register 3 - r/w +#define C66XX_CORE_EVTCLR3_RG_ADDR 0x0180004c +// DSP Event Mask register 0 - r/w +#define C66XX_CORE_EVTMASK0_RG_ADDR 0x01800080 +// DSP Event Mask register 1 - r/w +#define C66XX_CORE_EVTMASK1_RG_ADDR 0x01800084 +// DSP Event Mask register 2 - r/w +#define C66XX_CORE_EVTMASK2_RG_ADDR 0x01800088 +// DSP Event Mask register 3 - r/w +#define C66XX_CORE_EVTMASK3_RG_ADDR 0x0180008c + +// DSP Event Flag registers base address +#define C66XX_CORE_EVTFLAG_RG_BADDR 0x01800000 +// DSP Event Flag registers offset +#define C66XX_CORE_EVTFLAG_RG_OFFSET 0x00000004 + +// DSP Event Set registers base address +#define C66XX_CORE_EVTSET_RG_BADDR 0x01800020 +// DSP Event Set registers offset +#define C66XX_CORE_EVTSET_RG_OFFSET 0x00000004 + +// DSP Event Clear registers base address +#define C66XX_CORE_EVTCLR_RG_BADDR 0x01800040 +// DSP Event Clear registers offset +#define C66XX_CORE_EVTCLR_RG_OFFSET 0x00000004 + +// DSP Event Mask registers base address +#define C66XX_CORE_EVTMASK_RG_BADDR 0x01800080 +// DSP Event Mask registers offset +#define C66XX_CORE_EVTMASK_RG_OFFSET 0x00000004 + +//============================================================================= + + + +//============================================================================= +//============ PLL controller registers ======================================= +//============================================================================= +// PLL control register - r/w +#define C66XX_PLL_PLLCTL_RG_OFFSET 0x100 +// PLL secondary control register - r/w +#define C66XX_PLL_SECCTL_RG_OFFSET 0x108 +// PLL multiplier control register - r/w +#define C66XX_PLL_PLLM_RG_OFFSET 0x110 +// PLL controller divider 1 register - r/w +#define C66XX_PLL_PLLDIV1_RG_OFFSET 0x118 +// PLL controller divider 2 register - r/w +#define C66XX_PLL_PLLDIV2_RG_OFFSET 0x11c +// PLL controller divider 3 register - r/w +#define C66XX_PLL_PLLDIV3_RG_OFFSET 0x120 +// PLL controller command register - r/w +#define C66XX_PLL_PLLCMD_RG_OFFSET 0x138 +// PLL controller status register - r/w +#define C66XX_PLL_PLLSTAT_RG_OFFSET 0x13c +// PLL controller clock align control register - r/w +#define C66XX_PLL_ALNCTL_RG_OFFSET 0x140 +// PLL controller divider ratio change status register - r/w +#define C66XX_PLL_DCHANGE_RG_OFFSET 0x144 +// SYSCLK status register - r-only +#define C66XX_PLL_SYSTAT_RG_OFFSET 0x150 +// PLL controller divider 4 register - r/w +#define C66XX_PLL_PLLDIV4_RG_OFFSET 0x160 +// PLL controller divider 5 register - r/w +#define C66XX_PLL_PLLDIV5_RG_OFFSET 0x164 +// PLL controller divider 6 register - r/w +#define C66XX_PLL_PLLDIV6_RG_OFFSET 0x168 +// PLL controller divider 7 register - r/w +#define C66XX_PLL_PLLDIV7_RG_OFFSET 0x16c +// PLL controller divider 8 register - r/w +#define C66XX_PLL_PLLDIV8_RG_OFFSET 0x170 +// PLL controller divider 9 register - r/w +#define C66XX_PLL_PLLDIV9_RG_OFFSET 0x174 +// PLL controller divider 10 register - r/w +#define C66XX_PLL_PLLDIV10_RG_OFFSET 0x178 +// PLL controller divider 11 register - r/w +#define C66XX_PLL_PLLDIV11_RG_OFFSET 0x17c +// PLL controller divider 12 register - r/w +#define C66XX_PLL_PLLDIV12_RG_OFFSET 0x180 +// PLL controller divider 13 register - r/w +#define C66XX_PLL_PLLDIV13_RG_OFFSET 0x184 +// PLL controller divider 14 register - r/w +#define C66XX_PLL_PLLDIV14_RG_OFFSET 0x188 +// PLL controller divider 15 register - r/w +#define C66XX_PLL_PLLDIV15_RG_OFFSET 0x18c +// PLL controller divider 16 register - r/w +#define C66XX_PLL_PLLDIV16_RG_OFFSET 0x190 + +#define C66XX_PLL_PLLCTL_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLCTL_RG_OFFSET) +#define C66XX_PLL_SECCTL_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_SECCTL_RG_OFFSET) +#define C66XX_PLL_PLLM_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLM_RG_OFFSET) +#define C66XX_PLL_PLLDIV1_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV1_RG_OFFSET) +#define C66XX_PLL_PLLDIV2_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV2_RG_OFFSET) +#define C66XX_PLL_PLLDIV3_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV3_RG_OFFSET) +#define C66XX_PLL_PLLCMD_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLCMD_RG_OFFSET) +#define C66XX_PLL_PLLSTAT_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLSTAT_RG_OFFSET) +#define C66XX_PLL_ALNCTL_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_ALNCTL_RG_OFFSET) +#define C66XX_PLL_DCHANGE_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_DCHANGE_RG_OFFSET) +#define C66XX_PLL_SYSTAT_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_SYSTAT_RG_OFFSET) +#define C66XX_PLL_PLLDIV4_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV4_RG_OFFSET) +#define C66XX_PLL_PLLDIV5_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV5_RG_OFFSET) +#define C66XX_PLL_PLLDIV6_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV6_RG_OFFSET) +#define C66XX_PLL_PLLDIV7_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV7_RG_OFFSET) +#define C66XX_PLL_PLLDIV8_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV8_RG_OFFSET) +#define C66XX_PLL_PLLDIV9_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV9_RG_OFFSET) +#define C66XX_PLL_PLLDIV10_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV10_RG_OFFSET) +#define C66XX_PLL_PLLDIV11_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV11_RG_OFFSET) +#define C66XX_PLL_PLLDIV12_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV12_RG_OFFSET) +#define C66XX_PLL_PLLDIV13_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV13_RG_OFFSET) +#define C66XX_PLL_PLLDIV14_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV14_RG_OFFSET) +#define C66XX_PLL_PLLDIV15_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV15_RG_OFFSET) +#define C66XX_PLL_PLLDIV16_RG_ADDR (C66XX_PLL_RG_AREA_SADDR + C66XX_PLL_PLLDIV16_RG_OFFSET) + + +//------------ PLL control register defs -------------------------------------- +#define C66XX_PLL_PLLCTL_PLLENSRC_BITMASK 0x20 +#define C66XX_PLL_PLLCTL_PLLENSRC_BITSHIFT 5 +#define C66XX_PLL_PLLCTL_PLLRST_BITMASK 0x8 +#define C66XX_PLL_PLLCTL_PLLRST_BITSHIFT 3 +#define C66XX_PLL_PLLCTL_PLLPWRDN_BITMASK 0x2 +#define C66XX_PLL_PLLCTL_PLLPWRDN_BITSHIFT 1 +#define C66XX_PLL_PLLCTL_PLLEN_BITMASK 0x1 +#define C66XX_PLL_PLLCTL_PLLEN_BITSHIFT 0 + + +//------------ PLL secondary control register defs ---------------------------- +#define C66XX_PLL_SECCTL_BYPASS_BITMASK 0x00800000 +#define C66XX_PLL_SECCTL_BYPASS_BITSHIFT 23 +#define C66XX_PLL_SECCTL_OUTPUT_DIVIDE_BITMASK 0x00780000 +#define C66XX_PLL_SECCTL_OUTPUT_DIVIDE_BITSHIFT 19 + + +//------------ PLL multiplier control register defs --------------------------- +#define C66XX_PLL_PLLM_PLLM_BITMASK 0x3f +#define C66XX_PLL_PLLM_PLLM_BITSHIFT 0 + + +//------------ PLL controller divider registers defs -------------------------- +#define C66XX_PLL_PLLDIV_DEN_BITMASK 0x8000 +#define C66XX_PLL_PLLDIV_DEN_BITSHIFT 15 +#define C66XX_PLL_PLLDIV_RATIO_BITMASK 0xff +#define C66XX_PLL_PLLDIV_RATIO_BITSHIFT 0 + + +//------------ PLL controller command register defs --------------------------- +#define C66XX_PLL_PLLCMD_GOSET_BITMASK 0x1 +#define C66XX_PLL_PLLCMD_GOSET_BITSHIFT 0 + + +//------------ PLL controller status register defs ---------------------------- +#define C66XX_PLL_PLLSTAT_GOSTAT_BITMASK 0x1 +#define C66XX_PLL_PLLSTAT_GOSTAT_BITSHIFT 0 + + +//------------ PLL controller clock align control register defs --------------- +#define C66XX_PLL_ALNCTL_ALN_BITMASK 0xffff +#define C66XX_PLL_ALNCTL_ALN_BITSHIFT 0 + + +//------------ PLL controller divider ratio change status register defs ------- +#define C66XX_PLL_DCHANGE_SYS_BITMASK 0xffff +#define C66XX_PLL_DCHANGE_SYS_BITSHIFT 0 + + +//------------ SYSCLK status register defs ------------------------------------ +#define C66XX_PLL_SYSTAT_SYSON_BITMASK 0xffff +#define C66XX_PLL_SYSTAT_SYSON_BITSHIFT 0 + +//============================================================================= + + + +//============================================================================= +//============ Device State Control registers ================================= +//============================================================================= +/* + * !!! Note that this section contains only those definitions + * that are missed in TI C6000 Chip Support Library (CSL) !!! + */ + +// JTAG ID register - r-only +#define C66XX_BOOTCFG_JTAGID_RG_OFFSET 0x18 +// Device status register - r/w +#define C66XX_BOOTCFG_DEVSTAT_RG_OFFSET 0x20 +// Boot kicker 0 register - r/w +#define C66XX_BOOTCFG_KICK0_RG_OFFSET 0x38 +// Boot kicker 1 register - r/w +#define C66XX_BOOTCFG_KICK1_RG_OFFSET 0x3c +// DSP0 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR0_RG_OFFSET 0x40 +// DSP1 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR1_RG_OFFSET 0x44 +// DSP2 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR2_RG_OFFSET 0x48 +// DSP3 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR3_RG_OFFSET 0x4c +// DSP4 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR4_RG_OFFSET 0x50 +// DSP5 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR5_RG_OFFSET 0x54 +// DSP6 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR6_RG_OFFSET 0x58 +// DSP7 boot address register - r/w +#define C66XX_BOOTCFG_DSP_BOOT_ADDR7_RG_OFFSET 0x5c +// MAC 1 address register - r-only +#define C66XX_BOOTCFG_MACID1_RG_OFFSET 0x110 +// MAC 2 address register - r-only +#define C66XX_BOOTCFG_MACID2_RG_OFFSET 0x114 +// LRESETNMI PIN status clear register - r/w +#define C66XX_BOOTCFG_LRSTNMIPINSTAT_CLR_RG_OFFSET 0x130 +// Reset status clear register - r/w +#define C66XX_BOOTCFG_RESET_STAT_CLR_RG_OFFSET 0x134 +// Boot complete register - r/w +#define C66XX_BOOTCFG_BOOTCOMPLETE_RG_OFFSET 0x13c +// Reset status register - r-only +#define C66XX_BOOTCFG_RESET_STAT_RG_OFFSET 0x144 +// LRESETNMI PIN status register - r-only +#define C66XX_BOOTCFG_LRSTNMIPINSTAT_RG_OFFSET 0x148 +// Device configuration register - r/w +#define C66XX_BOOTCFG_DEVCFG_RG_OFFSET 0x14c +// Power state control register - r/w +#define C66XX_BOOTCFG_PWRSTATECTL_RG_OFFSET 0x150 +// SRIO SerDes macro status register - r-only +#define C66XX_BOOTCFG_SRIO_SERDES_STS_RG_OFFSET 0x154 +// SMGII SerDes macro status register - r-only +#define C66XX_BOOTCFG_SMGII_SERDES_STS_RG_OFFSET 0x158 +// PCIe SerDes macro status register - r-only +#define C66XX_BOOTCFG_PCIE_SERDES_STS_RG_OFFSET 0x15c +// HyperLink SerDes macro status register - r-only +#define C66XX_BOOTCFG_HYPERLINK_SERDES_STS_RG_OFFSET 0x160 +// NMI generation for CorePac0 register - r/w +#define C66XX_BOOTCFG_NMIGR0_RG_OFFSET 0x200 +// NMI generation for CorePac1 register - r/w +#define C66XX_BOOTCFG_NMIGR1_RG_OFFSET 0x204 +// NMI generation for CorePac2 register - r/w +#define C66XX_BOOTCFG_NMIGR2_RG_OFFSET 0x208 +// NMI generation for CorePac3 register - r/w +#define C66XX_BOOTCFG_NMIGR3_RG_OFFSET 0x20c +// NMI generation for CorePac4 register - r/w +#define C66XX_BOOTCFG_NMIGR4_RG_OFFSET 0x210 +// NMI generation for CorePac5 register - r/w +#define C66XX_BOOTCFG_NMIGR5_RG_OFFSET 0x214 +// NMI generation for CorePac6 register - r/w +#define C66XX_BOOTCFG_NMIGR6_RG_OFFSET 0x218 +// NMI generation for CorePac7 register - r/w +#define C66XX_BOOTCFG_NMIGR7_RG_OFFSET 0x21c +// IPC generation for CorePac0 register - r/w +#define C66XX_BOOTCFG_IPCGR0_RG_OFFSET 0x240 +// IPC generation for CorePac1 register - r/w +#define C66XX_BOOTCFG_IPCGR1_RG_OFFSET 0x244 +// IPC generation for CorePac2 register - r/w +#define C66XX_BOOTCFG_IPCGR2_RG_OFFSET 0x248 +// IPC generation for CorePac3 register - r/w +#define C66XX_BOOTCFG_IPCGR3_RG_OFFSET 0x24c +// IPC generation for CorePac4 register - r/w +#define C66XX_BOOTCFG_IPCGR4_RG_OFFSET 0x250 +// IPC generation for CorePac5 register - r/w +#define C66XX_BOOTCFG_IPCGR5_RG_OFFSET 0x254 +// IPC generation for CorePac6 register - r/w +#define C66XX_BOOTCFG_IPCGR6_RG_OFFSET 0x258 +// IPC generation for CorePac7 register - r/w +#define C66XX_BOOTCFG_IPCGR7_RG_OFFSET 0x25c + +// Timer Input Selection register - r/w +#define C66XX_BOOTCFG_TINPSEL_RG_OFFSET 0x300 +// Timer Output Selection register - r/w +#define C66XX_BOOTCFG_TOUTPSEL_RG_OFFSET 0x304 + +// Main PLL Control register 0 - r/w +#define C66XX_BOOTCFG_MAINPLLCTL0_RG_OFFSET 0x328 +// Main PLL Control register 1 - r/w +#define C66XX_BOOTCFG_MAINPLLCTL1_RG_OFFSET 0x32c +// DDR3 PLL Control register 0 - r/w +#define C66XX_BOOTCFG_DDR3PLLCTL0_RG_OFFSET 0x330 +// DDR3 PLL Control register 1 - r/w +#define C66XX_BOOTCFG_DDR3PLLCTL1_RG_OFFSET 0x334 +// Pass PLL Control register 0 - r/w +#define C66XX_BOOTCFG_PASSPLLCTL0_RG_OFFSET 0x338 +// Pass PLL Control register 1 - r/w +#define C66XX_BOOTCFG_PASSPLLCTL1_RG_OFFSET 0x33c +// Device speed register - r-only +#define C66XX_BOOTCFG_DEVSPEED_RG_OFFSET 0x3f8 + +#define C66XX_BOOTCFG_TINPSEL_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_TINPSEL_RG_OFFSET) +#define C66XX_BOOTCFG_TOUTPSEL_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_TOUTPSEL_RG_OFFSET) +#define C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_MAINPLLCTL0_RG_OFFSET) +#define C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_MAINPLLCTL1_RG_OFFSET) +#define C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_DDR3PLLCTL0_RG_OFFSET) +#define C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_DDR3PLLCTL1_RG_OFFSET) +#define C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_PASSPLLCTL0_RG_OFFSET) +#define C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_PASSPLLCTL1_RG_OFFSET) +#define C66XX_BOOTCFG_DEVSPEED_RG_ADDR (C66XX_BOOTCFG_RG_AREA_SADDR + C66XX_BOOTCFG_DEVSPEED_RG_OFFSET) + + +//------------ Main PLL Control register 0 defs ------------------------------- +#define C66XX_BOOTCFG_MAINPLLCTL0_BWADJ_BITMASK 0xff000000 +#define C66XX_BOOTCFG_MAINPLLCTL0_BWADJ_BITSHIFT 24 +#define C66XX_BOOTCFG_MAINPLLCTL0_PLLM_BITMASK 0x7f000 +#define C66XX_BOOTCFG_MAINPLLCTL0_PLLM_BITSHIFT 12 +#define C66XX_BOOTCFG_MAINPLLCTL0_PLLD_BITMASK 0x3f +#define C66XX_BOOTCFG_MAINPLLCTL0_PLLD_BITSHIFT 0 + + +//------------ Main PLL Control register 1 defs ------------------------------- +#define C66XX_BOOTCFG_MAINPLLCTL1_ENSAT_BITMASK 0x40 +#define C66XX_BOOTCFG_MAINPLLCTL1_ENSAT_BITSHIFT 6 +#define C66XX_BOOTCFG_MAINPLLCTL1_BWADJ_BITMASK 0xf +#define C66XX_BOOTCFG_MAINPLLCTL1_BWADJ_BITSHIFT 0 + + +//------------ DDR3 PLL Control register 0 defs ------------------------------- +#define C66XX_BOOTCFG_DDR3PLLCTL0_BWADJ_BITMASK 0xff000000 +#define C66XX_BOOTCFG_DDR3PLLCTL0_BWADJ_BITSHIFT 24 +#define C66XX_BOOTCFG_DDR3PLLCTL0_BYPASS_BITMASK 0x800000 +#define C66XX_BOOTCFG_DDR3PLLCTL0_BYPASS_BITSHIFT 23 +#define C66XX_BOOTCFG_DDR3PLLCTL0_PLLM_BITMASK 0x7ffc0 +#define C66XX_BOOTCFG_DDR3PLLCTL0_PLLM_BITSHIFT 6 +#define C66XX_BOOTCFG_DDR3PLLCTL0_PLLD_BITMASK 0x3f +#define C66XX_BOOTCFG_DDR3PLLCTL0_PLLD_BITSHIFT 0 + + +//------------ DDR3 PLL Control register 1 defs ------------------------------- +#define C66XX_BOOTCFG_DDR3PLLCTL1_PLLRST_BITMASK 0x2000 +#define C66XX_BOOTCFG_DDR3PLLCTL1_PLLRST_BITSHIFT 13 +#define C66XX_BOOTCFG_DDR3PLLCTL1_ENSAT_BITMASK 0x40 +#define C66XX_BOOTCFG_DDR3PLLCTL1_ENSAT_BITSHIFT 6 +#define C66XX_BOOTCFG_DDR3PLLCTL1_BWADJ_BITMASK 0xf +#define C66XX_BOOTCFG_DDR3PLLCTL1_BWADJ_BITSHIFT 0 + + +//------------ PASS PLL Control register 0 defs ------------------------------- +#define C66XX_BOOTCFG_PASSPLLCTL0_BWADJ_BITMASK 0xff000000 +#define C66XX_BOOTCFG_PASSPLLCTL0_BWADJ_BITSHIFT 24 +#define C66XX_BOOTCFG_PASSPLLCTL0_BYPASS_BITMASK 0x800000 +#define C66XX_BOOTCFG_PASSPLLCTL0_BYPASS_BITSHIFT 23 +#define C66XX_BOOTCFG_PASSPLLCTL0_PLLM_BITMASK 0x7ffc0 +#define C66XX_BOOTCFG_PASSPLLCTL0_PLLM_BITSHIFT 6 +#define C66XX_BOOTCFG_PASSPLLCTL0_PLLD_BITMASK 0x3f +#define C66XX_BOOTCFG_PASSPLLCTL0_PLLD_BITSHIFT 0 + + +//------------ PASS PLL Control register 1 defs ------------------------------- +#define C66XX_BOOTCFG_PASSPLLCTL1_PLLRST_BITMASK 0x4000 +#define C66XX_BOOTCFG_PASSPLLCTL1_PLLRST_BITSHIFT 14 +#define C66XX_BOOTCFG_PASSPLLCTL1_PLLSELECT_BITMASK 0x2000 +#define C66XX_BOOTCFG_PASSPLLCTL1_PLLSELECT_BITSHIFT 13 +#define C66XX_BOOTCFG_PASSPLLCTL1_ENSAT_BITMASK 0x40 +#define C66XX_BOOTCFG_PASSPLLCTL1_ENSAT_BITSHIFT 6 +#define C66XX_BOOTCFG_PASSPLLCTL1_BWADJ_BITMASK 0xf +#define C66XX_BOOTCFG_PASSPLLCTL1_BWADJ_BITSHIFT 0 + + +//------------ Device speed register defs ------------------------------------- +#define C66XX_BOOTCFG_DEVSPEED_DEVSPEED_BITMASK 0xff800000 +#define C66XX_BOOTCFG_DEVSPEED_DEVSPEED_BITSHIFT 23 + +// DSP core speed defs in MHz +#define C66XX_DSP_CORE_SPEED_800MHZ 800 +#define C66XX_DSP_CORE_SPEED_1000MHZ 1000 +#define C66XX_DSP_CORE_SPEED_1200MHZ 1200 +#define C66XX_DSP_CORE_SPEED_1250MHZ 1250 +#define C66XX_DSP_CORE_SPEED_1400MHZ 1400 + + +//------------ MACID2 register defs ------------------------------------------- +#define C66XX_BOOTCFG_MACID2_MACID_BITMASK 0xffff +#define C66XX_BOOTCFG_MACID2_MACID_BITSHIFT 0 + +//============================================================================= + + + +//============================================================================= +//============ Power & sleep controller definitions =========================== +//============================================================================= +/* + * !!! Note that this section contains only those definitions + * that are missed in TI C6000 Chip Support Library (CSL) !!! + */ + +// Power Domains Definitions +#define C66XX_PSC_PD_ALWAYSON 0 +#define C66XX_PSC_PD_TETB 1 +#define C66XX_PSC_PD_PA 2 +#define C66XX_PSC_PD_PCIE 3 +#define C66XX_PSC_PD_SRIO 4 +#define C66XX_PSC_PD_HYPERLINK 5 +#define C66XX_PSC_PD_MSM_SRAM 7 +#define C66XX_PSC_PD_DSP0 8 +#define C66XX_PSC_PD_DSP1 9 +#define C66XX_PSC_PD_DSP2 10 +#define C66XX_PSC_PD_DSP3 11 +#define C66XX_PSC_PD_DSP4 12 +#define C66XX_PSC_PD_DSP5 13 +#define C66XX_PSC_PD_DSP6 14 +#define C66XX_PSC_PD_DSP7 15 +#define C66XX_PSC_PD_COUNT (C66XX_PSC_PD_DSP7 + 1) + +// Power Domains State Definitions +#define C66XX_PSC_PD_STATE_OFF PSC_PDSTATE_OFF +#define C66XX_PSC_PD_STATE_ON PSC_PDSTATE_ON + + +// Power & Sleep Controller Clock Domains Definitions +#define C66XX_PSC_LPSC_SHARED_LPSC 0 +#define C66XX_PSC_LPSC_SMARTREFLEX 1 +#define C66XX_PSC_LPSC_DDR3_EMIF 2 +#define C66XX_PSC_LPSC_EMIF16_SPI 3 +#define C66XX_PSC_LPSC_TSIP 4 +#define C66XX_PSC_LPSC_DEBUG_TRACE 5 +#define C66XX_PSC_LPSC_TETB 6 +#define C66XX_PSC_LPSC_PA 7 +#define C66XX_PSC_LPSC_ETHERNET 8 +#define C66XX_PSC_LPSC_SA 9 +#define C66XX_PSC_LPSC_PCIE 10 +#define C66XX_PSC_LPSC_SRIO 11 +#define C66XX_PSC_LPSC_HYPERLINK 12 +#define C66XX_PSC_LPSC_MSM_SRAM 14 +#define C66XX_PSC_LPSC_DSP0 15 +#define C66XX_PSC_LPSC_DSP1 16 +#define C66XX_PSC_LPSC_DSP2 17 +#define C66XX_PSC_LPSC_DSP3 18 +#define C66XX_PSC_LPSC_DSP4 19 +#define C66XX_PSC_LPSC_DSP5 20 +#define C66XX_PSC_LPSC_DSP6 21 +#define C66XX_PSC_LPSC_DSP7 22 +#define C66XX_PSC_LPSC_COUNT (C66XX_PSC_LPSC_DSP7 + 1) + +// Clock Domains State Definitions +#define C66XX_PSC_LPSC_STATE_OFF PSC_MODSTATE_SWRSTDISABLE +#define C66XX_PSC_LPSC_STATE_ON PSC_MODSTATE_ENABLE + +//============================================================================= + + + +//============================================================================= +//============ I2C definitions ================================================ +//============================================================================= +/* + * !!! Note that this section contains only those definitions + * that are missed in TI C6000 Chip Support Library (CSL) !!! + */ + +// I2C own address register - r/w +#define C66XX_I2C_ICOAR_RG_OFFSET 0x00 +// I2C interrupt mask register - r/w +#define C66XX_I2C_ICIMR_RG_OFFSET 0x04 +// I2C interrupt status register - r/w +#define C66XX_I2C_ICSTR_RG_OFFSET 0x08 +// I2C clock low-time divider register - r/w +#define C66XX_I2C_ICCLKL_RG_OFFSET 0x0c +// I2C clock high-time divider register - r/w +#define C66XX_I2C_ICCLKH_RG_OFFSET 0x10 +// I2C data count register - r/w +#define C66XX_I2C_ICCNT_RG_OFFSET 0x14 +// I2C data receive register - r-only +#define C66XX_I2C_ICDRR_RG_OFFSET 0x18 +// I2C slave address register - r/w +#define C66XX_I2C_ICSAR_RG_OFFSET 0x1c +// I2C data transmit register - r/w +#define C66XX_I2C_ICDXR_RG_OFFSET 0x20 +// I2C mode register - r/w +#define C66XX_I2C_ICMDR_RG_OFFSET 0x24 +// I2C interrupt vector register - r/w +#define C66XX_I2C_ICIVR_RG_OFFSET 0x28 +// I2C extended mode register - r/w +#define C66XX_I2C_ICEMDR_RG_OFFSET 0x2c +// I2C prescaler register - r/w +#define C66XX_I2C_ICPSC_RG_OFFSET 0x30 +// I2C peripheral identification 1 register - r/w +#define C66XX_I2C_ICPID1_RG_OFFSET 0x34 +// I2C peripheral identification 2 register - r/w +#define C66XX_I2C_ICPID2_RG_OFFSET 0x38 + +#define C66XX_I2C_ICOAR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICOAR_RG_OFFSET) +#define C66XX_I2C_ICIMR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICIMR_RG_OFFSET) +#define C66XX_I2C_ICSTR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICSTR_RG_OFFSET) +#define C66XX_I2C_ICCLKL_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICCLKL_RG_OFFSET) +#define C66XX_I2C_ICCLKH_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICCLKH_RG_OFFSET) +#define C66XX_I2C_ICCNT_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICCNT_RG_OFFSET) +#define C66XX_I2C_ICDRR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICDRR_RG_OFFSET) +#define C66XX_I2C_ICSAR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICSAR_RG_OFFSET) +#define C66XX_I2C_ICDXR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICDXR_RG_OFFSET) +#define C66XX_I2C_ICMDR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICMDR_RG_OFFSET) +#define C66XX_I2C_ICIVR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICIVR_RG_OFFSET) +#define C66XX_I2C_ICEMDR_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICEMDR_RG_OFFSET) +#define C66XX_I2C_ICPSC_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICPSC_RG_OFFSET) +#define C66XX_I2C_ICPID1_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICPID1_RG_OFFSET) +#define C66XX_I2C_ICPID2_RG_ADDR (C66XX_I2C_RG_AREA_SADDR + C66XX_I2C_ICPID2_RG_OFFSET) + + +//------------ I2C own address register defs ---------------------------------- +#define C66XX_I2C_ICOAR_OADDR_BITMASK 0x3ff +#define C66XX_I2C_ICOAR_OADDR_BITSHIFT 0 + + +//------------ I2C interrupt mask register defs ------------------------------- +#define C66XX_I2C_ICIMR_AAS_BITMASK 0x40 +#define C66XX_I2C_ICIMR_AAS_BITSHIFT 6 +#define C66XX_I2C_ICIMR_SCD_BITMASK 0x20 +#define C66XX_I2C_ICIMR_SCD_BITSHIFT 5 +#define C66XX_I2C_ICIMR_ICXRDY_BITMASK 0x10 +#define C66XX_I2C_ICIMR_ICXRDY_BITSHIFT 4 +#define C66XX_I2C_ICIMR_ICRDRDY_BITMASK 0x8 +#define C66XX_I2C_ICIMR_ICRDRDY_BITSHIFT 3 +#define C66XX_I2C_ICIMR_ARDY_BITMASK 0x4 +#define C66XX_I2C_ICIMR_ARDY_BITSHIFT 2 +#define C66XX_I2C_ICIMR_NACK_BITMASK 0x2 +#define C66XX_I2C_ICIMR_NACK_BITSHIFT 1 +#define C66XX_I2C_ICIMR_AL_BITMASK 0x1 +#define C66XX_I2C_ICIMR_AL_BITSHIFT 0 +#define C66XX_I2C_ICIMR_RG_BITMASK 0x7f + + +//------------ I2C interrupt status register defs ----------------------------- +#define C66XX_I2C_ICSTR_SDIR_BITMASK 0x4000 +#define C66XX_I2C_ICSTR_SDIR_BITSHIFT 14 +#define C66XX_I2C_ICSTR_NACKSNT_BITMASK 0x2000 +#define C66XX_I2C_ICSTR_NACKSNT_BITSHIFT 13 +#define C66XX_I2C_ICSTR_BB_BITMASK 0x1000 +#define C66XX_I2C_ICSTR_BB_BITSHIFT 12 +#define C66XX_I2C_ICSTR_RSFULL_BITMASK 0x800 +#define C66XX_I2C_ICSTR_RSFULL_BITSHIFT 11 +#define C66XX_I2C_ICSTR_XSMT_BITMASK 0x400 +#define C66XX_I2C_ICSTR_XSMT_BITSHIFT 10 +#define C66XX_I2C_ICSTR_AAS_BITMASK 0x200 +#define C66XX_I2C_ICSTR_AAS_BITSHIFT 9 +#define C66XX_I2C_ICSTR_AD0_BITMASK 0x100 +#define C66XX_I2C_ICSTR_AD0_BITSHIFT 8 +#define C66XX_I2C_ICSTR_SCD_BITMASK 0x20 +#define C66XX_I2C_ICSTR_SCD_BITSHIFT 5 +#define C66XX_I2C_ICSTR_ICXRDY_BITMASK 0x10 +#define C66XX_I2C_ICSTR_ICXRDY_BITSHIFT 4 +#define C66XX_I2C_ICSTR_ICRDRDY_BITMASK 0x8 +#define C66XX_I2C_ICSTR_ICRDRDY_BITSHIFT 3 +#define C66XX_I2C_ICSTR_ARDY_BITMASK 0x4 +#define C66XX_I2C_ICSTR_ARDY_BITSHIFT 2 +#define C66XX_I2C_ICSTR_NACK_BITMASK 0x2 +#define C66XX_I2C_ICSTR_NACK_BITSHIFT 1 +#define C66XX_I2C_ICSTR_AL_BITMASK 0x1 +#define C66XX_I2C_ICSTR_AL_BITSHIFT 0 + + +//------------ I2C clock low-time divider register defs ----------------------- +#define C66XX_I2C_ICCLKL_ICCL_BITMASK 0xffff +#define C66XX_I2C_ICCLKL_ICCL_BITSHIFT 0 + + +//------------ I2C clock high-time divider register defs ---------------------- +#define C66XX_I2C_ICCLKH_ICCH_BITMASK 0xffff +#define C66XX_I2C_ICCLKH_ICCH_BITSHIFT 0 + + +//------------ I2C data count register defs ----------------------------------- +#define C66XX_I2C_ICCNT_ICDC_BITMASK 0xffff +#define C66XX_I2C_ICCNT_ICDC_BITSHIFT 0 + + +//------------ I2C data receive register defs --------------------------------- +#define C66XX_I2C_ICDRR_D_BITMASK 0xff +#define C66XX_I2C_ICDRR_D_BITSHIFT 0 + + +//------------ I2C slave address register defs -------------------------------- +#define C66XX_I2C_ICSAR_SADDR_BITMASK 0x3ff +#define C66XX_I2C_ICSAR_SADDR_BITSHIFT 0 + + +//------------ I2C data transmit register defs -------------------------------- +#define C66XX_I2C_ICDXR_D_BITMASK 0xff +#define C66XX_I2C_ICDXR_D_BITSHIFT 0 + + +//------------ I2C mode register defs ----------------------------------------- +#define C66XX_I2C_ICMDR_NACKMOD_BITMASK 0x8000 +#define C66XX_I2C_ICMDR_NACKMOD_BITSHIFT 15 +#define C66XX_I2C_ICMDR_FREE_BITMASK 0x4000 +#define C66XX_I2C_ICMDR_FREE_BITSHIFT 14 +#define C66XX_I2C_ICMDR_STT_BITMASK 0x2000 +#define C66XX_I2C_ICMDR_STT_BITSHIFT 13 +#define C66XX_I2C_ICMDR_STP_BITMASK 0x800 +#define C66XX_I2C_ICMDR_STP_BITSHIFT 11 +#define C66XX_I2C_ICMDR_MST_BITMASK 0x400 +#define C66XX_I2C_ICMDR_MST_BITSHIFT 10 +#define C66XX_I2C_ICMDR_TRX_BITMASK 0x200 +#define C66XX_I2C_ICMDR_TRX_BITSHIFT 9 +#define C66XX_I2C_ICMDR_XA_BITMASK 0x100 +#define C66XX_I2C_ICMDR_XA_BITSHIFT 8 +#define C66XX_I2C_ICMDR_RM_BITMASK 0x80 +#define C66XX_I2C_ICMDR_RM_BITSHIFT 7 +#define C66XX_I2C_ICMDR_DLB_BITMASK 0x40 +#define C66XX_I2C_ICMDR_DLB_BITSHIFT 6 +#define C66XX_I2C_ICMDR_IRS_BITMASK 0x20 +#define C66XX_I2C_ICMDR_IRS_BITSHIFT 5 +#define C66XX_I2C_ICMDR_STB_BITMASK 0x10 +#define C66XX_I2C_ICMDR_STB_BITSHIFT 4 +#define C66XX_I2C_ICMDR_FDF_BITMASK 0x8 +#define C66XX_I2C_ICMDR_FDF_BITSHIFT 3 +#define C66XX_I2C_ICMDR_BC_BITMASK 0x7 +#define C66XX_I2C_ICMDR_BC_BITSHIFT 0 + + +//------------ I2C interrupt vector register defs ----------------------------- +#define C66XX_I2C_ICIVR_INTCODE_BITMASK 0x7 +#define C66XX_I2C_ICIVR_INTCODE_BITSHIFT 0 + + +//------------ I2C extended mode register defs -------------------------------- +#define C66XX_I2C_ICEMDR_IGNACK_BITMASK 0x2 +#define C66XX_I2C_ICEMDR_IGNACK_BITSHIFT 1 +#define C66XX_I2C_ICEMDR_BCM_BITMASK 0x1 +#define C66XX_I2C_ICEMDR_BCM_BITSHIFT 0 + + +//------------ I2C prescaler register defs ------------------------------------ +#define C66XX_I2C_ICPSC_IPSC_BITMASK 0xff +#define C66XX_I2C_ICPSC_IPSC_BITSHIFT 0 + + +//------------ I2C peripheral identification 1 register defs ------------------ +#define C66XX_I2C_ICPID1_CLASS_BITMASK 0xff00 +#define C66XX_I2C_ICPID1_CLASS_BITSHIFT 8 +#define C66XX_I2C_ICPID1_REVISION_BITMASK 0xff +#define C66XX_I2C_ICPID1_REVISION_BITSHIFT 0 + + +//------------ I2C peripheral identification 2 register defs ------------------ +#define C66XX_I2C_ICPID2_TYPE_BITMASK 0xffff +#define C66XX_I2C_ICPID2_TYPE_BITSHIFT 0 + +//============================================================================= + + + +//============================================================================= +//============ EMIF16 configuration registers ================================= +//============================================================================= +// Revision code and status register - r-only +#define C66XX_EMIF16_RCSR_RG_OFFSET 0x00 +// Async wait cycle config register - r/w +#define C66XX_EMIF16_AWCCR_RG_OFFSET 0x04 +// Async 1 (CE0) config register - r/w +#define C66XX_EMIF16_A1CR_RG_OFFSET 0x10 +// Async 2 (CE1) config register - r/w +#define C66XX_EMIF16_A2CR_RG_OFFSET 0x14 +// Async 3 (CE2) config register - r/w +#define C66XX_EMIF16_A3CR_RG_OFFSET 0x18 +// Async 4 (CE3) config register - r/w +#define C66XX_EMIF16_A4CR_RG_OFFSET 0x1c +// Interrupt raw register - r/w +#define C66XX_EMIF16_IRR_RG_OFFSET 0x40 +// Interrupt masked register - r/w +#define C66XX_EMIF16_IMR_RG_OFFSET 0x44 +// Interrupt mask set register - r/w +#define C66XX_EMIF16_IMSR_RG_OFFSET 0x48 +// Interrupt mask clear register - r/w +#define C66XX_EMIF16_IMCR_RG_OFFSET 0x4c +// Page mode control register - r/w +#define C66XX_EMIF16_PMCR_RG_OFFSET 0x68 + +#define C66XX_EMIF16_RCSR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_RCSR_RG_OFFSET) +#define C66XX_EMIF16_AWCCR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_AWCCR_RG_OFFSET) +#define C66XX_EMIF16_A1CR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_A1CR_RG_OFFSET) +#define C66XX_EMIF16_A2CR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_A2CR_RG_OFFSET) +#define C66XX_EMIF16_A3CR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_A3CR_RG_OFFSET) +#define C66XX_EMIF16_A4CR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_A4CR_RG_OFFSET) +#define C66XX_EMIF16_IRR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_IRR_RG_OFFSET) +#define C66XX_EMIF16_IMR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_IMR_RG_OFFSET) +#define C66XX_EMIF16_IMSR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_IMSR_RG_OFFSET) +#define C66XX_EMIF16_IMCR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_IMCR_RG_OFFSET) +#define C66XX_EMIF16_PMCR_RG_ADDR (C66XX_EMIF16_RG_AREA_SADDR + C66XX_EMIF16_PMCR_RG_OFFSET) + + +//------------ Revision code and status register defs ------------------------- +#define C66XX_EMIF16_RCSR_BE_BITMASK 0x80000000 +#define C66XX_EMIF16_RCSR_BE_BITSHIFT 31 +#define C66XX_EMIF16_RCSR_MOD_ID_BITMASK 0x3fff0000 +#define C66XX_EMIF16_RCSR_MOD_ID_BITSHIFT 16 +#define C66XX_EMIF16_RCSR_MJ_REV_BITMASK 0xff00 +#define C66XX_EMIF16_RCSR_MJ_REV_BITSHIFT 8 +#define C66XX_EMIF16_RCSR_MIN_REV_BITMASK 0xff +#define C66XX_EMIF16_RCSR_MIN_REV_BITSHIFT 0 + +#define C66XX_EMIF16_RCSR_MOD_ID_DEFAULT_VALUE 0x46 +#define C66XX_EMIF16_RCSR_MJ_REV_DEFAULT_VALUE 0x4 +#define C66XX_EMIF16_RCSR_MIN_REV_DEFAULT_VALUE 0x0 + + +//------------ Async wait cycle config register defs -------------------------- +#define C66XX_EMIF16_AWCCR_WP1_BITMASK 0x20000000 +#define C66XX_EMIF16_AWCCR_WP1_BITSHIFT 29 +#define C66XX_EMIF16_AWCCR_WP0_BITMASK 0x10000000 +#define C66XX_EMIF16_AWCCR_WP0_BITSHIFT 28 +#define C66XX_EMIF16_AWCCR_CS5_WAIT_BITMASK 0xc00000 +#define C66XX_EMIF16_AWCCR_CS5_WAIT_BITSHIFT 22 +#define C66XX_EMIF16_AWCCR_CS4_WAIT_BITMASK 0x300000 +#define C66XX_EMIF16_AWCCR_CS4_WAIT_BITSHIFT 20 +#define C66XX_EMIF16_AWCCR_CS3_WAIT_BITMASK 0xc0000 +#define C66XX_EMIF16_AWCCR_CS3_WAIT_BITSHIFT 18 +#define C66XX_EMIF16_AWCCR_CS2_WAIT_BITMASK 0x30000 +#define C66XX_EMIF16_AWCCR_CS2_WAIT_BITSHIFT 16 +#define C66XX_EMIF16_AWCCR_MAX_EXT_WAIT_BITMASK 0xff +#define C66XX_EMIF16_AWCCR_MAX_EXT_WAIT_BITSHIFT 0 + + +//------------ Async 1 config register defs ----------------------------------- +#define C66XX_EMIF16_A1CR_SS_BITMASK 0x80000000 +#define C66XX_EMIF16_A1CR_SS_BITSHIFT 31 +#define C66XX_EMIF16_A1CR_EW_BITMASK 0x40000000 +#define C66XX_EMIF16_A1CR_EW_BITSHIFT 30 +#define C66XX_EMIF16_A1CR_W_SETUP_BITMASK 0x3c000000 +#define C66XX_EMIF16_A1CR_W_SETUP_BITSHIFT 26 +#define C66XX_EMIF16_A1CR_W_STROBE_BITMASK 0x3f00000 +#define C66XX_EMIF16_A1CR_W_STROBE_BITSHIFT 20 +#define C66XX_EMIF16_A1CR_W_HOLD_BITMASK 0xe0000 +#define C66XX_EMIF16_A1CR_W_HOLD_BITSHIFT 17 +#define C66XX_EMIF16_A1CR_R_SETUP_BITMASK 0x1e000 +#define C66XX_EMIF16_A1CR_R_SETUP_BITSHIFT 13 +#define C66XX_EMIF16_A1CR_R_STROBE_BITMASK 0x1f80 +#define C66XX_EMIF16_A1CR_R_STROBE_BITSHIFT 7 +#define C66XX_EMIF16_A1CR_R_HOLD_BITMASK 0x70 +#define C66XX_EMIF16_A1CR_R_HOLD_BITSHIFT 4 +#define C66XX_EMIF16_A1CR_TA_BITMASK 0xc +#define C66XX_EMIF16_A1CR_TA_BITSHIFT 2 +#define C66XX_EMIF16_A1CR_ASIZE_BITMASK 0x3 +#define C66XX_EMIF16_A1CR_ASIZE_BITSHIFT 0 + +#define C66XX_EMIF16_A1CR_ASIZE_8BIT 0 +#define C66XX_EMIF16_A1CR_ASIZE_16BIT 1 + + +//------------ Interrupt raw register defs ------------------------------------ +#define C66XX_EMIF16_IRR_WR_BITMASK 0x3c +#define C66XX_EMIF16_IRR_WR_BITSHIFT 2 +#define C66XX_EMIF16_IRR_AT_BITMASK 0x1 +#define C66XX_EMIF16_IRR_AT_BITSHIFT 0 + + +//------------ Interrupt masked register defs --------------------------------- +#define C66XX_EMIF16_IMR_WR_MASKED_BITMASK 0x3c +#define C66XX_EMIF16_IMR_WR_MASKED_BITSHIFT 2 +#define C66XX_EMIF16_IMR_AT_MASKED_BITMASK 0x1 +#define C66XX_EMIF16_IMR_AT_MASKED_BITSHIFT 0 + + +//------------ Interrupt mask set register defs ------------------------------- +#define C66XX_EMIF16_IMSR_WR_MASK_SET_BITMASK 0x3c +#define C66XX_EMIF16_IMSR_WR_MASK_SET_BITSHIFT 2 +#define C66XX_EMIF16_IMSR_AT_MASK_SET_BITMASK 0x1 +#define C66XX_EMIF16_IMSR_AT_MASK_SET_BITSHIFT 0 + + +//------------ Interrupt mask clear register defs ----------------------------- +#define C66XX_EMIF16_IMCR_WR_MASK_CLR_BITMASK 0x3c +#define C66XX_EMIF16_IMCR_WR_MASK_CLR_BITSHIFT 2 +#define C66XX_EMIF16_IMCR_AT_MASK_CLR_BITMASK 0x1 +#define C66XX_EMIF16_IMCR_AT_MASK_CLR_BITSHIFT 0 + +//============================================================================= + + + +//============================================================================= +//============ Timer definitions ============================================== +//============================================================================= + +// Emulation Management and Clock Speed register - r-only +#define C66XX_TIMER_EMUMGT_CLKSPD_RG_OFFSET 0x0004 +// Counter register low register - r/w +#define C66XX_TIMER_CNTLO_RG_OFFSET 0x0010 +// Counter register high register - r/w +#define C66XX_TIMER_CNTHI_RG_OFFSET 0x0014 +// Period register low register - r/w +#define C66XX_TIMER_PRDLO_RG_OFFSET 0x0018 +// Period register high register - r/w +#define C66XX_TIMER_PRDHI_RG_OFFSET 0x001c +// Timer control register - r/w +#define C66XX_TIMER_TCR_RG_OFFSET 0x0020 +// Timer global control register - r/w +#define C66XX_TIMER_TGCR_RG_OFFSET 0x0024 +// Watchdog timer control register - r/w +#define C66XX_TIMER_WDTCR_RG_OFFSET 0x0028 +// Timer Reload register low register - r/w +#define C66XX_TIMER_RELLO_RG_OFFSET 0x0034 +// Timer Reload register high register - r/w +#define C66XX_TIMER_RELHI_RG_OFFSET 0x0038 +// Timer Capture register low register - r/w +#define C66XX_TIMER_CAPLO_RG_OFFSET 0x003c +// Timer Capture register high register - r/w +#define C66XX_TIMER_CAPHI_RG_OFFSET 0x0040 +// Timer interrupt control and status register - r/w +#define C66XX_TIMER_INTCTLSTAT_RG_OFFSET 0x0044 + +// Timer 0-15 registers area offset addresses +#define C66XX_TIMER_RG_AREA_OFFSET 0x00010000 +// Timer 0-15 registers addresses: timer = 0-15 +#define C66XX_TIMER_EMUMGT_CLKSPD_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_EMUMGT_CLKSPD_RG_OFFSET) +#define C66XX_TIMER_CNTLO_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_CNTLO_RG_OFFSET) +#define C66XX_TIMER_CNTHI_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_CNTHI_RG_OFFSET) +#define C66XX_TIMER_PRDLO_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_PRDLO_RG_OFFSET) +#define C66XX_TIMER_PRDHI_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_PRDHI_RG_OFFSET) +#define C66XX_TIMER_TCR_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_TCR_RG_OFFSET) +#define C66XX_TIMER_TGCR_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_TGCR_RG_OFFSET) +#define C66XX_TIMER_WDTCR_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_WDTCR_RG_OFFSET) +#define C66XX_TIMER_RELLO_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_RELLO_RG_OFFSET) +#define C66XX_TIMER_RELHI_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_RELHI_RG_OFFSET) +#define C66XX_TIMER_CAPLO_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_CAPLO_RG_OFFSET) +#define C66XX_TIMER_CAPHI_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_CAPHI_RG_OFFSET) +#define C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer) (C66XX_TIMER_0_RG_AREA_SADDR + (timer * C66XX_TIMER_RG_AREA_OFFSET) + C66XX_TIMER_INTCTLSTAT_RG_OFFSET) + + +//------------ Emulation Management and Clock Speed register defs ------------- +#define C66XX_TIMER_EMUMGT_CLKSPD_CLKDIV_BITMASK 0x000f0000 +#define C66XX_TIMER_EMUMGT_CLKSPD_CLKDIV_BITSHIFT 16 + + +//------------ Timer control register defs ------------------------------------ +#define C66XX_TIMER_TCR_READRSTMODE_HI_BITMASK 0x04000000 +#define C66XX_TIMER_TCR_READRSTMODE_HI_BITSHIFT 26 +#define C66XX_TIMER_TCR_ENAMODE_HI_BITMASK 0x00c00000 +#define C66XX_TIMER_TCR_ENAMODE_HI_BITSHIFT 22 +#define C66XX_TIMER_TCR_PWID_HI_BITMASK 0x00300000 +#define C66XX_TIMER_TCR_PWID_HI_BITSHIFT 20 +#define C66XX_TIMER_TCR_CP_HI_BITMASK 0x00080000 +#define C66XX_TIMER_TCR_CP_HI_BITSHIFT 19 +#define C66XX_TIMER_TCR_INVOUTP_HI_BITMASK 0x00020000 +#define C66XX_TIMER_TCR_INVOUTP_HI_BITSHIFT 17 +#define C66XX_TIMER_TCR_TSTAT_HI_BITMASK 0x00010000 +#define C66XX_TIMER_TCR_TSTAT_HI_BITSHIFT 16 +#define C66XX_TIMER_TCR_CAPEVTMODE_LO_BITMASK 0x00003000 +#define C66XX_TIMER_TCR_CAPEVTMODE_LO_BITSHIFT 12 +#define C66XX_TIMER_TCR_CAPMODE_LO_BITMASK 0x00000800 +#define C66XX_TIMER_TCR_CAPMODE_LO_BITSHIFT 11 +#define C66XX_TIMER_TCR_READRSTMODE_LO_BITMASK 0x00000400 +#define C66XX_TIMER_TCR_READRSTMODE_LO_BITSHIFT 10 +#define C66XX_TIMER_TCR_TIEN_LO_BITMASK 0x00000200 +#define C66XX_TIMER_TCR_TIEN_LO_BITSHIFT 9 +#define C66XX_TIMER_TCR_CLKSRC_LO_BITMASK 0x00000100 +#define C66XX_TIMER_TCR_CLKSRC_LO_BITSHIFT 8 +#define C66XX_TIMER_TCR_ENAMODE_LO_BITMASK 0x000000c0 +#define C66XX_TIMER_TCR_ENAMODE_LO_BITSHIFT 6 +#define C66XX_TIMER_TCR_PWID_LO_BITMASK 0x00000030 +#define C66XX_TIMER_TCR_PWID_LO_BITSHIFT 4 +#define C66XX_TIMER_TCR_CP_LO_BITMASK 0x00000008 +#define C66XX_TIMER_TCR_CP_LO_BITSHIFT 3 +#define C66XX_TIMER_TCR_INVINP_LO_BITMASK 0x00000004 +#define C66XX_TIMER_TCR_INVINP_LO_BITSHIFT 2 +#define C66XX_TIMER_TCR_INVOUTP_LO_BITMASK 0x00000002 +#define C66XX_TIMER_TCR_INVOUTP_LO_BITSHIFT 1 +#define C66XX_TIMER_TCR_TSTAT_LO_BITMASK 0x00000001 +#define C66XX_TIMER_TCR_TSTAT_LO_BITSHIFT 0 + +#define C66XX_TIMER_TCR_ENAMODE_DISABLED 0 +#define C66XX_TIMER_TCR_ENAMODE_ONE_SHOT 1 +#define C66XX_TIMER_TCR_ENAMODE_CONT 2 +#define C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD 3 + +#define C66XX_TIMER_TCR_PWID_1_CLK 0 +#define C66XX_TIMER_TCR_PWID_2_CLK 1 +#define C66XX_TIMER_TCR_PWID_3_CLK 2 +#define C66XX_TIMER_TCR_PWID_4_CLK 3 + +#define C66XX_TIMER_TCR_CAPEVTMODE_RISING_EDGE 0 +#define C66XX_TIMER_TCR_CAPEVTMODE_FALLING_EDGE 1 +#define C66XX_TIMER_TCR_CAPEVTMODE_ANY_EDGE 2 + + +//------------ Timer global control register defs ----------------------------- +#define C66XX_TIMER_TGCR_TDDRHI_BITMASK 0x0000f000 +#define C66XX_TIMER_TGCR_TDDRHI_BITSHIFT 12 +#define C66XX_TIMER_TGCR_PSCHI_BITMASK 0x00000f00 +#define C66XX_TIMER_TGCR_PSCHI_BITSHIFT 8 +#define C66XX_TIMER_TGCR_PLUSEN_BITMASK 0x00000010 +#define C66XX_TIMER_TGCR_PLUSEN_BITSHIFT 4 +#define C66XX_TIMER_TGCR_TIMMODE_BITMASK 0x0000000c +#define C66XX_TIMER_TGCR_TIMMODE_BITSHIFT 2 +#define C66XX_TIMER_TGCR_TIMHIRS_BITMASK 0x00000002 +#define C66XX_TIMER_TGCR_TIMHIRS_BITSHIFT 1 +#define C66XX_TIMER_TGCR_TIMLORS_BITMASK 0x00000001 +#define C66XX_TIMER_TGCR_TIMLORS_BITSHIFT 0 + +#define C66XX_TIMER_TGCR_TIMMODE_64BIT_GPT 0 +#define C66XX_TIMER_TGCR_TIMMODE_32BIT_UNCHAINED 1 +#define C66XX_TIMER_TGCR_TIMMODE_64BIT_WDT 2 +#define C66XX_TIMER_TGCR_TIMMODE_32BIT_CHAINED 3 + + +//------------ Watchdog Timer Control Register defs --------------------------- +#define C66XX_TIMER_WDTCR_WDKEY_BITMASK 0xffff0000 +#define C66XX_TIMER_WDTCR_WDKEY_BITSHIFT 16 +#define C66XX_TIMER_WDTCR_WDFLAG_BITMASK 0x00008000 +#define C66XX_TIMER_WDTCR_WDFLAG_BITSHIFT 15 +#define C66XX_TIMER_WDTCR_WDEN_BITMASK 0x00004000 +#define C66XX_TIMER_WDTCR_WDEN_BITSHIFT 14 + +#define C66XX_TIMER_WDTCR_WDKEY_FIRST_KEY 0xa5c6 +#define C66XX_TIMER_WDTCR_WDKEY_SECOND_KEY 0xda7e + + +//------------ Timer interrupt control and status register defs --------------- +#define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_HI_BITMASK 0x00080000 +#define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_HI_BITSHIFT 19 +#define C66XX_TIMER_INTCTLSTAT_EVTINTEN_HI_BITMASK 0x00040000 +#define C66XX_TIMER_INTCTLSTAT_EVTINTEN_HI_BITSHIFT 18 +#define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_HI_BITMASK 0x00020000 +#define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_HI_BITSHIFT 17 +#define C66XX_TIMER_INTCTLSTAT_PRDINTEN_HI_BITMASK 0x00010000 +#define C66XX_TIMER_INTCTLSTAT_PRDINTEN_HI_BITSHIFT 16 +#define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_LO_BITMASK 0x00000008 +#define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_LO_BITSHIFT 3 +#define C66XX_TIMER_INTCTLSTAT_EVTINTEN_LO_BITMASK 0x00000004 +#define C66XX_TIMER_INTCTLSTAT_EVTINTEN_LO_BITSHIFT 2 +#define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_LO_BITMASK 0x00000002 +#define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_LO_BITSHIFT 1 +#define C66XX_TIMER_INTCTLSTAT_PRDINTEN_LO_BITMASK 0x00000001 +#define C66XX_TIMER_INTCTLSTAT_PRDINTEN_LO_BITSHIFT 0 + +//============================================================================= + + + +//============================================================================= +#endif /* __C66XX_DEF_HXX__ */ diff --git a/ports/c667x/ccs/example_build/include/C66XX_FUNCTIONS.hxx b/ports/c667x/ccs/example_build/include/C66XX_FUNCTIONS.hxx new file mode 100644 index 00000000..8564e44d --- /dev/null +++ b/ports/c667x/ccs/example_build/include/C66XX_FUNCTIONS.hxx @@ -0,0 +1,1693 @@ +/****************************************************************************** + TMS320C66xx KeyStone Multicore DSP Software Development Kit (SDK). Rev 2A. + (C) MicroLAB Systems, 2014-2015 + + File: C66xx DSP SDK API functions declarations + ----- + + Notes: + ------ + 1. This C-header file contains C66xx DSP SDK API functions declarations + and is used with C66XX.h C-header file. + + 2. This file is best viewed with the TAB setting set to '4'. + +******************************************************************************/ + + +/** + * @file C66XX_FUNCTIONS.hxx + * + * @brief SDK API functions declarations + * + * This file contains C66xx DSP SDK API functions declarations + * + */ + + +#ifndef __C66XX_FUNCTIONS_HXX__ // check for this file has been already included +#define __C66XX_FUNCTIONS_HXX__ 1 + + + +//============================================================================= +//============ Returned error codes =========================================== +//============================================================================= +/** @addtogroup C66XX_ERRORS DSP SDK API returned error codes + * @{ + */ +#define C66XX_OK 0 /**< No errors */ +#define C66XX_PARAM_ERR -1 /**< Invalid function parameter */ +#define C66XX_INVALID_HW_ERR -2 /**< Invalid H/W error (invalid board, etc.) */ +#define C66XX_HW_ERR -3 /**< H/W error (error writing to the DSP control registers, etc) */ +#define C66XX_I2C_ERR -10 /**< I2C module is not correctly operated */ +#define C66XX_I2C_AL_ERR -11 /**< I2C module arbitration lost error */ +#define C66XX_I2C_RSFULL_ERR -12 /**< I2C module overrun error */ +#define C66XX_I2C_XSMT_ERR -13 /**< I2C module underflow error */ +#define C66XX_I2C_NACK_ERR -14 /**< I2C module no-acknowledgement error */ +#define C66XX_I2C_ARDY_ERR -15 /**< I2C module register-access-ready error */ +#define C66XX_I2C_READ_ERR -16 /**< I2C module read error */ +#define C66XX_I2C_WRITE_ERR -17 /**< I2C module write error */ +#define C66XX_I2C_TIMEOUT_ERR -18 /**< I2C bus timeout error */ +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ SDK API functions ID defs ====================================== +//============================================================================= +/** @addtogroup C66XX_FUNCTIONS_ID SDK API functions ID defs + * @{ + */ + +enum +{ + C66XX_GET_ERROR_MESSAGE_FUNCTION_ID = 0, + C66XX_GET_FUNCTION_NAME_FUNCTION_ID, + C66XX_SYS_SET_CORE_RESET_STATE_FUNCTION_ID, + C66XX_SYS_GET_CORE_RESET_STATE_FUNCTION_ID, + C66XX_SYS_GET_CORE_RESET_SOURCE_FUNCTION_ID, + C66XX_SYS_SET_CORE_BOOT_ADDRESS_FUNCTION_ID, + C66XX_SYS_INIT_MAIN_PLL_FUNCTION_ID, + C66XX_SYS_GET_MAIN_PLL_SETTINGS_FUNCTION_ID, + C66XX_SYS_INIT_DDR3_PLL_FUNCTION_ID, + C66XX_SYS_GET_DDR3_PLL_SETTINGS_FUNCTION_ID, + C66XX_SYS_INIT_PASS_PLL_FUNCTION_ID, + C66XX_SYS_GET_PASS_PLL_SETTINGS_FUNCTION_ID, + C66XX_SYS_ENABLE_POWER_DOMAIN_FUNCTION_ID, + C66XX_MEM_INIT_XMC_MPAX_SEGMENT_FUNCTION_ID, + C66XX_MEM_INIT_DDR3_FUNCTION_ID, + C66XX_INT_INIT_CORE_FUNCTION_ID, + C66XX_INT_MAP_CORE_EVENT_HANDLER_FUNCTION_ID, + C66XX_INT_UNMAP_CORE_EVENT_HANDLER_FUNCTION_ID, + C66XX_INT_INIT_CHIP_FUNCTION_ID, + C66XX_GPIO_INIT_FUNCTION_ID, + C66XX_TIMER_INIT_FUNCTION_ID, + C66XX_TIMER_START_FUNCTION_ID, + C66XX_TIMER_STOP_FUNCTION_ID, + C66XX_TIMER_RESET_FUNCTION_ID, + C66XX_TIMER_ENABLE_INTERRUPTS_FUNCTION_ID, + C66XX_TIMER_DISABLE_INTERRUPTS_FUNCTION_ID, + C66XX_UART_INIT_FUNCTION_ID, + C66XX_I2C_INIT_FUNCTION_ID, + C66XX_I2C_WRITE_DATA_FUNCTION_ID, + C66XX_I2C_READ_DATA_FUNCTION_ID, + C66XX_GBE_INIT_SERDES_FUNCTION_ID, + C66XX_GBE_INIT_SGMII_FUNCTION_ID, + C66XX_SRIO_INIT_FUNCTION_ID, + C66XX_SRIO_MAP_TX_QUEUE_FUNCTION_ID, + C66XX_SRIO_ROUTE_DOORBELL_INTERRUPT_FUNCTION_ID, + C66XX_NUMBER_OF_FUNCTIONS +}; +/** @}*/ +//============================================================================= + + + +#ifdef __cplusplus +extern "C" { +#endif + + +//============================================================================= +//============ General SDK API functions declarations ========================= +//============================================================================= + +/** @addtogroup C66XX_GENERAL_FUNCTIONS General DSP SDK API functions + * @{ + */ + +/*------------ C66XX_get_last_error() function ---------------------------*//** + * @brief Function returns error code of last executed API function + * + * @return Error code of last executed API function + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_get_last_error(void); + + +/*------------ C66XX_get_error_flag() function ---------------------------*//** + * @brief Function returns status of ERROR_FLAG for API functions + * + * ERROR_FLAG is set by each API function in case error has been detected. + * ERROR_FLAG can be reset by C66XX_clear_error_flag() API function + * + * @param[out] error_code - pointer to a variable to receive the error code in + * case error has been detected. In case pointer is NULL, then + * no error code is returned; + * @param[out] error_function_id - pointer to a variable to receive ID of the + * first API function, which has returned with error. In case + * pointer is NULL, then no function ID is returned; + * + * @return Status of ERROR_FLAG: ON or OFF + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_get_error_flag(int32_t *error_code, int32_t *error_function_id); + + +/*------------ C66XX_clear_error_flag() function -------------------------*//** + * @brief Function clear ERROR_FLAG for API functions + * + * @return Always OK + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_clear_error_flag(void); + + +/*------------ C66XX_get_error_message() function ------------------------*//** + * @brief Function returns the text interpretation of the error code. + * + * @param[in] error - error code to be interpreted; + * @param[out] error_message - pointer to the returned string. In case pointer + * is NULL, then no text is filled in; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_get_error_message(int32_t error, char *error_message); + + +/*------------ C66XX_get_function_name() function ------------------------*//** + * @brief Function returns the text interpretation of API function. + * + * @param[in] function_id - ID of the API function to be interpreted; + * @param[out] function_name - pointer to the returned string. In case pointer + * is NULL, then no text is filled in; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_get_function_name(int32_t function_id, char *function_name); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ System functions =============================================== +//============================================================================= + +/** @addtogroup C66XX_SYS System functions + * @{ + */ + + +/** DSP core reset source is global reset */ +#define C66XX_DSP_CORE_RESET_SRC_IS_GLOBAL_RESET 1 +/** DSP core reset source is local reset */ +#define C66XX_DSP_CORE_RESET_SRC_IS_LOCAL_RESET 2 + + +/** Main PLL Multiplier bitmask */ +#define C66XX_MAIN_PLL_PLLM_BITMASK 0x1fff +/** Main PLL Divider bitmask */ +#define C66XX_MAIN_PLL_PLLD_BITMASK 0x3f +/** Number of PLL dividers */ +#define C66XX_MAIN_PLL_PLLDIV_COUNT 16 + +/** Main PLL divider data descriptor */ +typedef struct +{ + uint32_t enable; /**< PLL divider enable flag */ + uint32_t ratio; /**< PLL divider value (8-bit) */ +} C66XX_MAIN_PLL_PLLDIV_DD; + +// Main PLL divider data descriptor length in bytes +#define C66XX_MAIN_PLL_PLLDIV_DD_LEN sizeof(C66XX_MAIN_PLL_PLLDIV_DD) + + +/** Main PLL data descriptor (contains parameters which are used to init PLL) */ +typedef struct +{ + uint32_t bypass; /**< PLL mode: bypass or not */ + uint32_t pllm; /**< PLL multiplier value (13-bit) */ + uint32_t plld; /**< PLL divider value (6-bit) */ + uint32_t output_divide; /**< PLL output divider value (4-bit) */ + C66XX_MAIN_PLL_PLLDIV_DD plldiv[C66XX_MAIN_PLL_PLLDIV_COUNT]; /**< PLL dividers */ +} C66XX_MAIN_PLL_DD; + +// Main PLL data descriptor length in bytes +#define C66XX_MAIN_PLL_DD_LEN sizeof(C66XX_MAIN_PLL_DD) + + +/** DDR3 PLL data descriptor (contains parameters which are used to init DDR3 PLL) */ +typedef struct +{ + uint32_t pllm; /**< PLL multiplier value (13-bit) */ + uint32_t plld; /**< PLL divider value (6-bit) */ +} C66XX_DDR3_PLL_DD; + +// DDR3 PLL data descriptor length in bytes +#define C66XX_DDR3_PLL_DD_LEN sizeof(C66XX_DDR3_PLL_DD) + + +/** PASS PLL data descriptor (contains parameters which are used to init PASS PLL) */ +typedef struct +{ + uint32_t pllm; /**< PLL multiplier value (13-bit) */ + uint32_t plld; /**< PLL divider value (6-bit) */ +} C66XX_PASS_PLL_DD; + +// PASS PLL data descriptor length in bytes +#define C66XX_PASS_PLL_DD_LEN sizeof(C66XX_PASS_PLL_DD) + + +/*------------ C66XX_SYS_get_core_number() function ----------------------*//** + * @brief Function returns DSP core number at which the program is running + * + * @return DSP core number + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_SYS_get_core_number(void); + + +/*------------ C66XX_SYS_get_max_core_freq() function --------------------*//** + * @brief Function returns DSP core max speed in MHz + * + * @return DSP core max speed in MHz + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_SYS_get_max_core_freq(void); + + +/*------------ C66XX_SYS_set_core_reset_state() function -----------------*//** + * @brief Function sets or releases DSP core local reset + * + * @param[in] core - DSP core number to set or release from local reset + * @param[in] state - DSP core local reset state: ON or OFF + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_set_core_reset_state(uint32_t core, uint32_t state); + + +/*------------ C66XX_SYS_get_core_reset_state() function -----------------*//** + * @brief Function returns DSP core local reset state + * + * @param[in] core - DSP core number to return local reset state + * @param[out] state - pointer to a variable to receive DSP core local reset + * state: ON or OFF + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_get_core_reset_state(uint32_t core, uint32_t *state); + + +/*------------ C66XX_SYS_get_core_reset_source() function ----------------*//** + * @brief Function returns DSP core reset source: global or local + * + * @param[in] core - DSP core number to return reset source + * @param[out] state - pointer to a variable to receive DSP core reset source: + * global or local + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_get_core_reset_source(uint32_t core, uint32_t *source); + + +/*------------ C66XX_SYS_set_core_boot_address() function ----------------*//** + * @brief Function sets DSP core boot address. After releasing DSP core from + * reset it will start execution from this memory address. + * Note that DSP core boot address should be 1024 bytes aligned + * + * @param[in] core - DSP core number to set boot address + * @param[in] addr - DSP core boot address: should be 1024 bytes aligned + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_set_core_boot_address(uint32_t core, uint32_t addr); + + +/*------------ C66XX_SYS_init_main_pll() function ------------------------*//** + * @brief Function inits DSP Main PLL according to supplied parameters + * + * @param[in] pll_dd - Main PLL data descriptor + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_init_main_pll(C66XX_MAIN_PLL_DD *pll_dd); + + +/*------------ C66XX_SYS_get_main_pll_settings() function ----------------*//** + * @brief Function returns DSP Main PLL settings + * + * @param[out] pll_dd - Pointer to a main PLL data descriptor to receive data + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_get_main_pll_settings(C66XX_MAIN_PLL_DD *pll_dd); + + +/*------------ C66XX_SYS_init_ddr3_pll() function ------------------------*//** + * @brief Function inits DSP DDR3 PLL according to supplied parameters + * + * @param[in] ddr3_pll_dd - DDR3 PLL data descriptor + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_init_ddr3_pll(C66XX_DDR3_PLL_DD *ddr3_pll_dd); + + +/*------------ C66XX_SYS_get_ddr3_pll_settings() function ----------------*//** + * @brief Function returns DSP DDR3 PLL settings + * + * @param[out] ddr3_pll_dd - Pointer to DDR3 PLL data descriptor to receive +* data + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_get_ddr3_pll_settings(C66XX_DDR3_PLL_DD *ddr3_pll_dd); + + +/*------------ C66XX_SYS_init_pass_pll() function ------------------------*//** + * @brief Function inits DSP PASS PLL according to supplied parameters + * + * @param[in] pass_pll_dd - PASS PLL data descriptor + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_init_pass_pll(C66XX_PASS_PLL_DD *pass_pll_dd); + + +/*------------ C66XX_SYS_get_pass_pll_settings() function ----------------*//** + * @brief Function returns DSP PASS PLL settings + * + * @param[out] pass_pll_dd - Pointer to PASS PLL data descriptor to receive +* data + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_get_pass_pll_settings(C66XX_PASS_PLL_DD *pass_pll_dd); + + +/*------------ C66XX_SYS_enable_power_domain() function ------------------*//** + * @brief Function powers up selected power domain + * + * @param[in] domain - power domain number to enable + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SYS_enable_power_domain(uint32_t domain); + + +/** @}*/ +//============================================================================= + + +//============================================================================= +//============ DSP memory controller functions ================================ +//============================================================================= + +/** @addtogroup C66XX_MEM DSP memory controller functions + * @{ + */ + + +/** DSP L1 (P or D) cache sizes */ +#define C66XX_CACHE_L1_0KB CACHE_L1_0KCACHE +#define C66XX_CACHE_L1_4KB CACHE_L1_4KCACHE +#define C66XX_CACHE_L1_8KB CACHE_L1_8KCACHE +#define C66XX_CACHE_L1_16KB CACHE_L1_16KCACHE +#define C66XX_CACHE_L1_32KB CACHE_L1_32KCACHE +#define C66XX_CACHE_L1_MAX_SIZE CACHE_L1_MAXIM3 + + +/** DSP L2 cache sizes */ +#define C66XX_CACHE_L2_0KB CACHE_0KCACHE +#define C66XX_CACHE_L2_32KB CACHE_32KCACHE +#define C66XX_CACHE_L2_64KB CACHE_64KCACHE +#define C66XX_CACHE_L2_128KB CACHE_128KCACHE +#define C66XX_CACHE_L2_256KB CACHE_256KCACHE +#define C66XX_CACHE_L2_512KB CACHE_512KCACHE +#define C66XX_CACHE_L2_MAX_SIZE C66XX_CACHE_L2_512KB + + +/** DDR3 controller initialization data descriptor (contains parameters which are used to init DDR3 controller) */ +typedef struct +{ + EMIF4F_TIMING1_CONFIG timing1_config; /**< DDR3 controller Timing 1 configuration */ + EMIF4F_TIMING2_CONFIG timing2_config; /**< DDR3 controller Timing 2 configuration */ + EMIF4F_TIMING3_CONFIG timing3_config; /**< DDR3 controller Timing 3 configuration */ + EMIF4F_SDRAM_CONFIG sdram_config; /**< DDR3 controller SDRAM configuration */ +} C66XX_DDR3_EMIF_DD; + +// DDR3 controller initialization data descriptor length in bytes +#define C66XX_DDR3_EMIF_DD_LEN sizeof(C66XX_DDR3_EMIF_DD) + + +/** DDR3 controller physical interface (PHY) data descriptor (contains parameters which are used to perform leveling) */ +// All these values should be obtained from DDR3 PHY Calc spreadsheet (sprabl2) provided by TI +typedef struct +{ + uint32_t data0_wrlvl_init_ratio; /**< DDR3 byte lane 7 write leveling initialization ratio */ + uint32_t data1_wrlvl_init_ratio; /**< DDR3 byte lane 6 write leveling initialization ratio */ + uint32_t data2_wrlvl_init_ratio; /**< DDR3 byte lane 5 write leveling initialization ratio */ + uint32_t data3_wrlvl_init_ratio; /**< DDR3 byte lane 4 write leveling initialization ratio */ + uint32_t data4_wrlvl_init_ratio; /**< DDR3 byte lane 3 write leveling initialization ratio */ + uint32_t data5_wrlvl_init_ratio; /**< DDR3 byte lane 2 write leveling initialization ratio */ + uint32_t data6_wrlvl_init_ratio; /**< DDR3 byte lane 1 write leveling initialization ratio */ + uint32_t data7_wrlvl_init_ratio; /**< DDR3 byte lane 0 write leveling initialization ratio */ + uint32_t data8_wrlvl_init_ratio; /**< DDR3 ECC byte lane write leveling initialization ratio */ + uint32_t data0_gatelvl_init_ratio; /**< DDR3 byte lane 7 gate leveling initialization ratio */ + uint32_t data1_gatelvl_init_ratio; /**< DDR3 byte lane 6 gate leveling initialization ratio */ + uint32_t data2_gatelvl_init_ratio; /**< DDR3 byte lane 5 gate leveling initialization ratio */ + uint32_t data3_gatelvl_init_ratio; /**< DDR3 byte lane 4 gate leveling initialization ratio */ + uint32_t data4_gatelvl_init_ratio; /**< DDR3 byte lane 3 gate leveling initialization ratio */ + uint32_t data5_gatelvl_init_ratio; /**< DDR3 byte lane 2 gate leveling initialization ratio */ + uint32_t data6_gatelvl_init_ratio; /**< DDR3 byte lane 1 gate leveling initialization ratio */ + uint32_t data7_gatelvl_init_ratio; /**< DDR3 byte lane 0 gate leveling initialization ratio */ + uint32_t data8_gatelvl_init_ratio; /**< DDR3 ECC byte lane gate leveling initialization ratio */ + uint32_t ddr3_config_reg_12_bitmask; /**< DDR3 configuration 12 register bitmask for INVERT_CLK_OUT field */ +} C66XX_DDR3_PHY_DD; + +// DDR3 controller initialization data descriptor length in bytes +#define C66XX_DDR3_PHY_DD_LEN sizeof(C66XX_DDR3_PHY_DD) + + +/*------------ C66XX_MEM_set_L1P_cache_size() function -------------------*//** + * @brief Function sets DSP L1P cache to the new size + * + * @param[in] new_size - new size of DSP L1P cache + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_MEM_set_L1P_cache_size(uint32_t new_size); + + +/*------------ C66XX_MEM_get_L1P_cache_size() function -------------------*//** + * @brief Function returns DSP L1P cache size + * + * @return DSP L1P cache size + * +-----------------------------------------------------------------------------*/ +#define C66XX_MEM_get_L1P_cache_size() CACHE_getL1PSize() + + +/*------------ C66XX_MEM_set_L1D_cache_size() function -------------------*//** + * @brief Function sets DSP L1D cache to the new size + * + * @param[in] new_size - new size of DSP L1D cache + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_MEM_set_L1D_cache_size(uint32_t new_size); + + +/*------------ C66XX_MEM_get_L1D_cache_size() function -------------------*//** + * @brief Function returns DSP L1D cache size + * + * @return DSP L1D cache size + * +-----------------------------------------------------------------------------*/ +#define C66XX_MEM_get_L1D_cache_size() CACHE_getL1DSize() + + +/*------------ C66XX_MEM_set_L2_cache_size() function --------------------*//** + * @brief Function sets DSP L2 cache to the new size + * + * @param[in] new_size - new size of DSP L2 cache + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_MEM_set_L2_cache_size(uint32_t new_size); + + +/*------------ C66XX_MEM_get_L2_cache_size() function --------------------*//** + * @brief Function returns DSP L2 cache size + * + * @return DSP L2 cache size + * +-----------------------------------------------------------------------------*/ +#define C66XX_MEM_get_L2_cache_size() CACHE_getL2Size() + + +/*------------ C66XX_MEM_set_memory_region_cache_config() function -------*//** + * @brief Function enables or disables DSP caching for specified memory region + * + * @param[in] mar - MAR register number from 0 to 255 (note that the first 12 + * memory regions are read-only) + * @param[in] cacheable - cache mode to set: ON - enable caching, + * OFF - disable caching + * @param[in] prefetchable - DSP XMC controller prefetch mode to set: + * ON - enable prefetch support, OFF - disable prefetch support + * + * @return None + * +-----------------------------------------------------------------------------*/ +#define C66XX_MEM_set_memory_region_cache_config(mar, cacheable, prefetchable) CACHE_setMemRegionInfo(mar, cacheable, prefetchable) + + +/*------------ C66XX_MEM_get_memory_region_cache_config() function -------*//** + * @brief Function returns DSP cache configuration for specified memory region + * + * @param[in] mar - MAR register number from 0 to 255 (note that the first 12 + * memory regions are read-only) + * @param[in] cacheable - pointer to a variable to receive current cache mode: + * ON - caching is enabled, OFF - caching is disabled + * @param[in] prefetchable - pointer to a variable to receive current DSP XMC + * controller prefetch mode: ON - prefetch support is enabled, + * OFF - prefetch support is disabled + * + * @return None + * +-----------------------------------------------------------------------------*/ +#define C66XX_MEM_get_memory_region_cache_config(mar, cacheable, prefetchable) CACHE_getMemRegionInfo(mar, cacheable, prefetchable) + + +/*------------ C66XX_MEM_init_xmc_mpax_segment() function ----------------*//** + * @brief Function configures XMC MPAX segment according to supplied + * parameters + * + * @param[in] index - MPAX segment index from 0 to 15 (note that the first 2 + * segments are already configured by default) + * @param[in] baddr - upper 20 bit of base 32-bit address to remap + * @param[in] size - encoded segment size + * @param[in] raddr - upper 24 bit of replacement 36-bit address + * @param[in] perm - access types allowed in this segment + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_MEM_init_xmc_mpax_segment(uint32_t index, uint32_t baddr, uint32_t size, uint32_t raddr, uint32_t perm); + + +/*------------ C66XX_MEM_convert_local_to_global_address() function ------*//** + * @brief Function converts local DSP core address to global address + * + * @param[in] addr - local DSP core address to be converted + * + * @return Global address + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_MEM_convert_local_to_global_address(uint32_t addr); + + +/*------------ C66XX_MEM_init_ddr3() function --------------------------------*//** + * @brief Function inits DDR3 controller according to supplied parameters + * + * @param[in] ddr3_emif_dd - DDR3 controller initialization data descriptor + * @param[in] ddr3_phy_dd - DDR3 PHY controller initialization data descriptor + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_MEM_init_ddr3(C66XX_DDR3_EMIF_DD *ddr3_emif_dd, C66XX_DDR3_PHY_DD *ddr3_phy_dd); + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ Timer TSC functions ============================================ +//============================================================================= + +/** @addtogroup C66XX_TSC DSP 64-bit Time Stamp Counter (TSC) functions + * @{ + */ + +/*------------ C66XX_TSC_get_current_value() function --------------------*//** + * @brief Function returns DSP TSC current value + * + * @return 64-bit Time Stamp Counter value + * +-----------------------------------------------------------------------------*/ +uint64_t C66XX_TSC_get_current_value(void); + + +/*------------ C66XX_TSC_get_duration_s() function -----------------------*//** + * @brief Function returns time duration in seconds from Time Stamp Counter + * start value + * + * @param[in] start - 64-bit Time Stamp Counter value + * + * @return Time duration in seconds + * +-----------------------------------------------------------------------------*/ +double C66XX_TSC_get_duration_s(uint64_t start); + + +/*------------ C66XX_TSC_set_delay_us() function -------------------------*//** + * @brief Function is used to delay the execution for selected number of + * microseconds + * + * @param[in] us - Number of microseconds to delay + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_TSC_set_delay_us(uint32_t us); + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ C66xx interrupt controller functions =========================== +//============================================================================= + +/** @addtogroup C66XX_INT C66xx interrupt controller functions + * @{ + */ + + +/** DSP interrupt vector IDs */ +#define C66XX_DSP_VECTID_NMI CSL_INTC_VECTID_NMI +#define C66XX_DSP_VECTID_4 CSL_INTC_VECTID_4 +#define C66XX_DSP_VECTID_5 CSL_INTC_VECTID_5 +#define C66XX_DSP_VECTID_6 CSL_INTC_VECTID_6 +#define C66XX_DSP_VECTID_7 CSL_INTC_VECTID_7 +#define C66XX_DSP_VECTID_8 CSL_INTC_VECTID_8 +#define C66XX_DSP_VECTID_9 CSL_INTC_VECTID_9 +#define C66XX_DSP_VECTID_10 CSL_INTC_VECTID_10 +#define C66XX_DSP_VECTID_11 CSL_INTC_VECTID_11 +#define C66XX_DSP_VECTID_12 CSL_INTC_VECTID_12 +#define C66XX_DSP_VECTID_13 CSL_INTC_VECTID_13 +#define C66XX_DSP_VECTID_14 CSL_INTC_VECTID_14 +#define C66XX_DSP_VECTID_15 CSL_INTC_VECTID_15 +#define C66XX_DSP_VECTID_COMBINE CSL_INTC_VECTID_COMBINE +#define C66XX_DSP_VECTID_EXCEP CSL_INTC_VECTID_EXCEP + + +/*------------ C66XX_INT_init_core() function ----------------------------*//** + * @brief Function initializes C66x CorePac interrupt controller (INTC) using + * CSL library. + * + * If SYS/BIOS RTOS is used, then it's recommended to use the relevant + * SYS/BIOS interrupt API (HWI, EventCombiner and CpIntc), as there will be + * conflicts since both CSL and SYS/BIOS will use their own Interrupt Service + * Table Pointer (ISTP). + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_INT_init_core(void); + + +/*------------ C66XX_INT_map_core_event_handler() function ---------------*//** + * @brief Function maps DSP interrupt vector to INTC input event ID, plugs + * the specified function as DSP interrupt handler function, and enables DSP + * interrupt + * + * @param[in] dsp_vector_id - DSP interrupt vector + * @param[in] input_event_id - INTC input event ID + * @param[in] handler - pointer to DSP interrupt handler function + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_INT_map_core_event_handler(uint32_t dsp_vector_id, uint32_t input_event_id, CSL_IntcEventHandler handler); + + +/*------------ C66XX_INT_unmap_core_event_handler() function -------------*//** + * @brief Function unmaps DSP interrupt vector and disables the corresponding + * DSP interrupt. + * + * @param[in] dsp_vector_id - DSP interrupt vector + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_INT_unmap_core_event_handler(uint32_t dsp_vector_id); + + +/*------------ C66XX_INT_set_core_dsp_interrupt_handler() function -------*//** + * @brief Function sets the specified function as a direct handler for DSP + * interrupt vector ID. + * + * This handler function will be branched to from DSP interrupt vector table + * for specified DSP interrupt vector ID, so either it should be declared in C + * with "interrupt" keyword or manually save and restore interrupt context and + * return with "B IRP" assembler instruction. + * The specified DSP interrupt will be enabled too. + * + * @param[in] dsp_vector_id - DSP interrupt vector + * @param[in] isr_handler - direct handler function for DSP interrupt vector + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_INT_set_core_dsp_interrupt_handler(uint32_t dsp_vector_id, void *isr_handler); + + +/** Chip interrupt controllers defs */ +#define C66XX_CPINTC_ID_0 0 +#define C66XX_CPINTC_ID_1 1 +#define C66XX_CPINTC_ID_2 2 +#define C66XX_CPINTC_ID_3 3 + + +/*------------ C66XX_INT_init_chip() function ----------------------------*//** + * @brief Function initializes the specified chip interrupt controller + * (CPINTC or CIC) and returns a handle which should be used in all subsequent + * CPINTC function calls. + * + * @param[in] cpintc_id - chip interrupt controller number to initialize (0-3) + * + * @return Handle to the CPINTC instance: >0 - OK, + * 0 - error is occurred + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_INT_init_chip(uint32_t cpintc_id); + + +/*------------ C66XX_INT_map_chip_system_to_host_event() function --------*//** + * @brief Function maps chip-level event (system event) to CPINTC output event + * (host event) end enables it. + * + * System events are those events generated by a hardware module in the system. + * These events are inputs into CPINTC. + * Host events are the output events of CPINTC, which act as event inputs to + * C66x CorePac interrupt controllers (INTC). + * + * @param[in] cpintc_handle - chip interrupt controller handle returned by + * C66XX_init_cpintc() function call; + * @param[in] system_event_id - chip-level (system) event from a hardware + * module in the system. + * @param[in] host_event_id - CPINTC output event ID + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_INT_map_chip_system_to_host_event(uint32_t cpintc_handle, uint32_t system_event_id, uint32_t host_event_id); + + +/*------------ C66XX_INT_enable_chip_host_event() function ---------------*//** + * @brief Function enables CPINTC output event (host event). + * + * @param[in] cpintc_handle - chip interrupt controller handle returned by + * C66XX_init_cpintc() function call; + * @param[in] host_event_id - CPINTC output event ID to enable + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +#define C66XX_INT_enable_chip_host_event(cpintc_handle, host_event_id) CSL_CPINTC_enableHostInterrupt(cpintc_handle, host_event_id) + + +/*------------ C66XX_INT_disable_chip_host_event() function --------------*//** + * @brief Function disables CPINTC output event (host event). + * + * @param[in] cpintc_handle - chip interrupt controller handle returned by + * C66XX_init_cpintc() function call; + * @param[in] host_event_id - CPINTC output event ID to disable + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +#define C66XX_INT_disable_chip_host_event(cpintc_handle, host_event_id) CSL_CPINTC_disableHostInterrupt(cpintc_handle, host_event_id) + + +/*------------ C66XX_INT_clear_chip_system_event() function --------------*//** + * @brief Function clears CPINTC input event (system event). + * + * @param[in] cpintc_handle - chip interrupt controller handle returned by + * C66XX_init_cpintc() function call; + * @param[in] sys_event_id - CPINTC input event ID to clear + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +#define C66XX_INT_clear_chip_system_event(cpintc_handle, sys_event_id) CSL_CPINTC_clearSysInterrupt(cpintc_handle, sys_event_id) + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ General purpose I/O (GPIO) functions =========================== +//============================================================================= + +/** @addtogroup C66XX_GPIO DSP GPIO functions + * @{ + */ + +/** GPIO pins number defs */ +enum C66XX_GPIO_PINS +{ + C66XX_GPIO_PIN_0 = 0, + C66XX_GPIO_PIN_1, + C66XX_GPIO_PIN_2, + C66XX_GPIO_PIN_3, + C66XX_GPIO_PIN_4, + C66XX_GPIO_PIN_5, + C66XX_GPIO_PIN_6, + C66XX_GPIO_PIN_7, + C66XX_GPIO_PIN_8, + C66XX_GPIO_PIN_9, + C66XX_GPIO_PIN_10, + C66XX_GPIO_PIN_11, + C66XX_GPIO_PIN_12, + C66XX_GPIO_PIN_13, + C66XX_GPIO_PIN_14, + C66XX_GPIO_PIN_15 +}; + +/** GPIO pins bitmask defs */ +enum C66XX_GPIO_PIN_BITMASKS +{ + C66XX_GPIO_PIN_0_BITMASK = 0x0001, + C66XX_GPIO_PIN_1_BITMASK = 0x0002, + C66XX_GPIO_PIN_2_BITMASK = 0x0004, + C66XX_GPIO_PIN_3_BITMASK = 0x0008, + C66XX_GPIO_PIN_4_BITMASK = 0x0010, + C66XX_GPIO_PIN_5_BITMASK = 0x0020, + C66XX_GPIO_PIN_6_BITMASK = 0x0040, + C66XX_GPIO_PIN_7_BITMASK = 0x0080, + C66XX_GPIO_PIN_8_BITMASK = 0x0100, + C66XX_GPIO_PIN_9_BITMASK = 0x0200, + C66XX_GPIO_PIN_10_BITMASK = 0x0400, + C66XX_GPIO_PIN_11_BITMASK = 0x0800, + C66XX_GPIO_PIN_12_BITMASK = 0x1000, + C66XX_GPIO_PIN_13_BITMASK = 0x2000, + C66XX_GPIO_PIN_14_BITMASK = 0x4000, + C66XX_GPIO_PIN_15_BITMASK = 0x8000 +}; + + +/** GPIO bank number for CSL utilities */ +#define C66XX_GPIO_BANK_NUMBER 0 +/** GPIO data definitions */ +#define C66XX_GPIO_DATA_OFF 0 +#define C66XX_GPIO_DATA_ON 1 +/** GPIO direction definitions */ +#define C66XX_GPIO_DIR_OUT 0 +#define C66XX_GPIO_DIR_IN 1 +/** GPIO pin edge defs */ +#define C66XX_GPIO_PIN_EDGE_RISING 0 +#define C66XX_GPIO_PIN_EDGE_FALLING 1 +#define C66XX_GPIO_PIN_EDGE_ANY 2 +/** GPIO pins bitmask definitions */ +#define C66XX_GPIO_DATA_BITMASK 0x0000ffff + + +/*------------ C66XX_GPIO_init() function --------------------------------*//** + * @brief Function inits the GPIO peripheral: all pins are configured as + * inputs, interrupts are disabled + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_GPIO_init(void); + + +/*------------ C66XX_GPIO_set_pin_direction() function -------------------*//** + * @brief Function configures the specified GPIO pin direction + * + * @param[in] pin_number - GPIO pin number to configure + * @param[in] direction - GPIO direction definition + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_set_pin_direction(uint32_t pin_number, uint32_t direction); + + +/*------------ C66XX_GPIO_get_pin_direction() function -------------------*//** + * @brief Function returns the specified GPIO pin direction + * + * @param[in] pin_number - GPIO pin number to get direction + * + * @return GPIO direction definition + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_GPIO_get_pin_direction(uint32_t pin_number); + + +/*------------ C66XX_GPIO_set_pin_data() function ------------------------*//** + * @brief Function sets the specified GPIO pin state to data + * + * @param[in] pin_number - GPIO pin number to configure + * @param[in] data - GPIO pin state: ON or OFF + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_set_pin_data(uint32_t pin_number, uint32_t data); + + +/*------------ C66XX_GPIO_get_pin_data() function ------------------------*//** + * @brief Function returns the specified GPIO pin state + * + * @param[in] pin_number - GPIO pin number to get pin state + * + * @return GPIO pin state: ON or OFF + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_GPIO_get_pin_data(uint32_t pin_number); + + +/*------------ C66XX_GPIO_set_direction() function -----------------------*//** + * @brief Function configures the specified GPIO pins direction + * + * @param[in] pin_bitmask - GPIO pins (ORed) bitmask to configure + * @param[in] direction - GPIO direction definition + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_set_direction(uint32_t pin_bitmask, uint32_t direction); + + +/*------------ C66XX_GPIO_get_direction() function -----------------------*//** + * @brief Function returns the specified GPIO pins direction + * + * @param[in] pin_bitmask - GPIO pins (ORed) bitmask to get pins direction + * + * @return Specified GPIO pins direction + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_GPIO_get_direction(uint32_t pin_bitmask); + + +/*------------ C66XX_GPIO_set_data() function ----------------------------*//** + * @brief Function sets the specified GPIO pins state to data + * + * @param[in] pin_bitmask - GPIO pins (ORed) bitmask to configure + * @param[in] data - GPIO pins state: ON or OFF + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_set_data(uint32_t pin_bitmask, uint32_t data); + + +/*------------ C66XX_GPIO_get_data() function ----------------------------*//** + * @brief Function returns the specified GPIO pins state + * + * @param[in] pin_bitmask - GPIO pins (ORed) bitmask to get pins state + * + * @return Specified GPIO pins state + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_GPIO_get_data(uint32_t pin_bitmask); + + +/*------------ C66XX_GPIO_enable_interrupts() function -------------------*//** + * @brief Function enables GPIO peripheral interrupts + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_enable_interrupts(void); + + +/*------------ C66XX_GPIO_disable_interrupts() function ------------------*//** + * @brief Function disables GPIO peripheral interrupts + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_disable_interrupts(void); + + +/*------------ C66XX_GPIO_enable_edge_interrupt() function ---------------*//** + * @brief Function enables the specified GPIO pin edge interrupt + * + * @param[in] pin - GPIO pin number to configure + * @param[in] edge - GPIO pin edge which triggers GPIO interrupt + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_enable_edge_interrupt(uint32_t pin, uint32_t edge); + + +/*------------ C66XX_GPIO_disable_edge_interrupt() function --------------*//** + * @brief Function disables the specified GPIO pin edge interrupt + * + * @param[in] pin - GPIO pin number to configure + * @param[in] edge - GPIO pin edge which shouldn't trigger GPIO interrupt + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_GPIO_disable_edge_interrupt(uint32_t pin, uint32_t edge); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ Timer module functions ========================================= +//============================================================================= + +/** @addtogroup C66XX_TIMER DSP 64-bit Timer module functions + * @{ + */ + + +/** DSP 64-bit Timer module number defs */ +typedef enum +{ + C66XX_TIMER_0 = 0, + C66XX_TIMER_1, + C66XX_TIMER_2, + C66XX_TIMER_3, + C66XX_TIMER_4, + C66XX_TIMER_5, + C66XX_TIMER_6, + C66XX_TIMER_7, + C66XX_TIMER_8, + C66XX_TIMER_9, + C66XX_TIMER_10, + C66XX_TIMER_11, + C66XX_TIMER_12, + C66XX_TIMER_13, + C66XX_TIMER_14, + C66XX_TIMER_15 +} C66XX_TIMER; + + +/** DSP 64-bit Timer mode defs */ +typedef enum +{ + C66XX_TIMER_MODE_64BIT_GPT = 0, + C66XX_TIMER_MODE_32BIT_UNCHAINED, + C66XX_TIMER_MODE_64BIT_WDT, + C66XX_TIMER_MODE_32BIT_CHAINED +} C66XX_TIMER_MODE; + + +/** DSP 64-bit Timer hardware configuration defs */ +typedef enum +{ + C66XX_TIMER_HW_CFG_64BIT = 0, + C66XX_TIMER_HW_CFG_32BIT_LOW, + C66XX_TIMER_HW_CFG_32BIT_HIGH +} C66XX_TIMER_HW_CFG; + + +/** DSP 64-bit Timer count mode defs */ +typedef enum +{ + C66XX_TIMER_COUNT_MODE_DISABLED = 0, + C66XX_TIMER_COUNT_MODE_ONE_SHOT, + C66XX_TIMER_COUNT_MODE_CONTINUOUSLY, + C66XX_TIMER_COUNT_MODE_CONTINUOUSLY_RELOAD +} C66XX_TIMER_COUNT_MODE; + + +/** DSP timer input enable defs */ +typedef enum +{ + C66XX_TIMER_CLK_INPUT_DISABLED = 0, + C66XX_TIMER_CLK_INPUT_ENABLED +} C66XX_TIMER_CLK_INPUT; + + +/** DSP timer input inverter control defs */ +typedef enum +{ + C66XX_TIMER_CLK_INPUT_INVERTER_DISABLED = 0, + C66XX_TIMER_CLK_INPUT_INVERTER_ENABLED +} C66XX_TIMER_CLK_INPUT_INVERTER; + + +/** DSP timer clock source defs */ +typedef enum +{ + C66XX_TIMER_CLK_SRC_INTERNAL = 0, + C66XX_TIMER_CLK_SRC_EXTERNAL +} C66XX_TIMER_CLK_SRC; + + +/** DSP timer clock/pulse mode for timer output defs */ +typedef enum +{ + C66XX_TIMER_CLK_OUTPUT_MODE_PULSE = 0, + C66XX_TIMER_CLK_OUTPUT_MODE_CLK +} C66XX_TIMER_CLK_OUTPUT_MODE; + + +/** DSP timer pulse width used in pulse mode for timer output defs */ +typedef enum +{ + C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH_1CLK = 0, + C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH_2CLK, + C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH_3CLK, + C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH_4CLK +} C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH; + + +/** DSP timer output inverter control defs */ +typedef enum +{ + C66XX_TIMER_CLK_OUTPUT_INVERTER_DISABLED = 0, + C66XX_TIMER_CLK_OUTPUT_INVERTER_ENABLED +} C66XX_TIMER_CLK_OUTPUT_INVERTER; + + +/** DSP 32-bit Timer configuration data descriptor */ +typedef struct +{ + C66XX_TIMER_CLK_SRC clk_src; /**< Clock source for 32-bit timer */ + C66XX_TIMER_CLK_INPUT clk_input_enabled; /**< Timer clock is gated by the timer input for 32-bit timer */ + C66XX_TIMER_CLK_INPUT_INVERTER clk_input_inverter_enabled; /**< An inverted timer input drives the 32-bit timer */ + C66XX_TIMER_CLK_OUTPUT_MODE clk_src_output_mode; /**< Clock output mode for 32-bit timer */ + C66XX_TIMER_CLK_OUTPUT_PULSE_WIDTH clk_src_output_pulse_width; /**< Clock output pulse width used in pulse mode for 32-bit timer */ + C66XX_TIMER_CLK_OUTPUT_INVERTER clk_output_inverter_enabled; /**< 32-bit timer output is inverted */ +} C66XX_TIMER_32BIT_CFG_DD; + + +/** DSP 64-bit Timer module configuration data descriptor */ +typedef struct +{ + C66XX_TIMER_MODE timer_mode; /**< Timer mode: 64-bit GPT, 64-bit WDT, dual 32-bit unchained or chained */ + C66XX_TIMER_32BIT_CFG_DD timer_high; /**< Configuration data descriptor for 32-bit HIGH timer */ + C66XX_TIMER_32BIT_CFG_DD timer_low; /**< Configuration data descriptor for 32-bit LOW timer */ +} C66XX_TIMER_CFG_DD; + +// DSP 64-bit Timer module configuration data descriptor length in bytes +#define C66XX_TIMER_CFG_DD_LEN sizeof(C66XX_TIMER_CFG_DD) + + +/*------------ C66XX_TIMER_init() function -------------------------------*//** + * @brief Function configures selected DSP 64-bit timer module + * + * @param[in] timer_number - DSP 64-bit timer module number + * @param[in] frequency - DSP timer output frequency in Hz + * @param[in] cfg_dd - pointer to filled DSP 64-bit timer module configuration + * data descriptor + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_TIMER_init(C66XX_TIMER timer_number, uint32_t frequency, C66XX_TIMER_CFG_DD *cfg_dd); + + +/*------------ C66XX_TIMER_start() function ------------------------------*//** + * @brief Function starts selected DSP timer + * + * @param[in] timer_number - DSP 64-bit timer module number + * @param[in] timer_to_start - hardware timer to start (64BIT/32BIT_LOW/ + * 32BIT_HIGH) + * @param[in] count_mode - DSP timer counting mode (DISABLED/ONE_SHOT/ + * CONTINUOUSLY/CONTINUOUSLY_RELOAD) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_TIMER_start(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_start, C66XX_TIMER_COUNT_MODE count_mode); + + +/*------------ C66XX_TIMER_stop() function -------------------------------*//** + * @brief Function stops selected DSP timer + * + * @param[in] timer_number - DSP 64-bit timer module number + * @param[in] timer_to_stop - hardware timer to stop (64BIT/32BIT_LOW/ + * 32BIT_HIGH) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_TIMER_stop(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_stop); + + +/*------------ C66XX_TIMER_reset() function ------------------------------*//** + * @brief Function resets selected DSP timer + * + * @param[in] timer_number - DSP 64-bit timer module number + * @param[in] timer_to_reset - hardware timer to reset (64BIT/32BIT_LOW/ + * 32BIT_HIGH) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_TIMER_reset(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_reset); + + +/*------------ C66XX_TIMER_enable_interrupts() function ------------------*//** + * @brief Function enables interrupts from selected DSP timer + * + * @param[in] timer_number - DSP 64-bit timer module number + * @param[in] timer_to_enable - hardware timer to enable interrupts from + * (64BIT/32BIT_LOW/32BIT_HIGH) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_TIMER_enable_interrupts(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_enable); + + +/*------------ C66XX_TIMER_disable_interrupts() function ------------------*//** + * @brief Function disables interrupts from selected DSP timer + * + * @param[in] timer_number - DSP 64-bit timer module number + * @param[in] timer_to_disable - hardware timer to disable interrupts from + * (64BIT/32BIT_LOW/32BIT_HIGH) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_TIMER_disable_interrupts(C66XX_TIMER timer_number, C66XX_TIMER_HW_CFG timer_to_disable); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ UART functions ================================================= +//============================================================================= + +/** @addtogroup C66XX_UART DSP UART functions + * @{ + */ + +// UART baud rate defs (max 128 kBauds) +#define C66XX_UART_BAUD_RATE_2400 2400 /**< UART baud rate 2400 bps */ +#define C66XX_UART_BAUD_RATE_4800 4800 /**< UART baud rate 4800 bps */ +#define C66XX_UART_BAUD_RATE_9600 9600 /**< UART baud rate 9600 bps */ +#define C66XX_UART_BAUD_RATE_19200 19200 /**< UART baud rate 19200 bps */ +#define C66XX_UART_BAUD_RATE_38400 38400 /**< UART baud rate 38400 bps */ +#define C66XX_UART_BAUD_RATE_57600 57600 /**< UART baud rate 57600 bps */ +#define C66XX_UART_BAUD_RATE_115200 115200 /**< UART baud rate 115200 bps */ + +// UART data bits defs +#define C66XX_UART_DATA_BITS_5BITS 5 /**< UART 5-bits data words */ +#define C66XX_UART_DATA_BITS_6BITS 6 /**< UART 6-bits data words */ +#define C66XX_UART_DATA_BITS_7BITS 7 /**< UART 7-bits data words */ +#define C66XX_UART_DATA_BITS_8BITS 8 /**< UART 8-bits data words */ + +// UART parity parameter defs +#define C66XX_UART_PARITY_NONE 0 /**< no parity */ +#define C66XX_UART_PARITY_EVEN 1 /**< even parity */ +#define C66XX_UART_PARITY_ODD 2 /**< odd parity */ + +// UART stop bits defs +#define C66XX_UART_STOP_BITS_1BIT 0 /**< one stop bit */ +#define C66XX_UART_STOP_BITS_1_5BITS 1 /**< one and a half stop bits */ +#define C66XX_UART_STOP_BITS_2BITS 2 /**< two stop bits */ + +// UART key defs +#define C66XX_UART_KEY_BEEP 0x7 /**< BELL value in HEX */ +#define C66XX_UART_KEY_ESC 0x1b /**< ESC value in HEX */ +#define C66XX_UART_KEY_CR 0xd /**< Carriage Return value in HEX */ +#define C66XX_UART_KEY_BS 0x8 /**< Back space value in HEX */ +#define C66XX_UART_LINE_LEN_MAX 80 /**< Maximum available received line length */ + + + +/*------------ C66XX_UART_init() function --------------------------------*//** + * @brief Function inits the UART peripheral + * + * @param[in] core_clk - DSP core clock frequency in MHz; + * @param[in] baud_rate - desired baud rate; + * @param[in] data_bits - number of data bits; + * @param[in] parity - parity bit; + * @param[in] stop_bits - number of stop bits; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_UART_init(uint32_t core_clk, uint32_t baud_rate, uint32_t data_bits, uint32_t parity, uint32_t stop_bits); + + +/*------------ C66XX_UART_receiver_is_ready() function -------------------*//** + * @brief Function checks if a character is received over UART + * + * @return 1 - a character is received over UART, + * 0 - otherwise + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_UART_receiver_is_ready(void); + + +/*------------ C66XX_UART_receive_char() function ------------------------*//** + * @brief Function receives a character over UART + * + * @return Received character + * +-----------------------------------------------------------------------------*/ +uint8_t C66XX_UART_receive_char(void); + + +/*------------ C66XX_UART_transmit_char() function -----------------------*//** + * @brief Function transmits a character over UART + * + * @param[in] c - A character to transmit + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_UART_transmit_char(uint8_t c); + + +/*------------ C66XX_UART_transmit_string() function ---------------------*//** + * @brief Function transmits a string until '0' character + * + * @param[in] s - A pointer to the string to transmit + * + * @return None + * +-----------------------------------------------------------------------------*/ +void C66XX_UART_transmit_string(char *s); + + +/*------------ C66XX_UART_receive_line_string() function -----------------*//** + * @brief Function receives a line ended with CR character, and stores + * received characters into string with '\0' symbol. + * + * Note that maximum received line length should not exceed + * C66XX_UART_LINE_LEN_MAX value! + * + * @param[in] s - Pointer to a string to store received characters + * + * @return Number of received characters without '\0' symbol. + * +-----------------------------------------------------------------------------*/ +uint32_t C66XX_UART_receive_line_string(char *s); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ I2C functions ================================================== +//============================================================================= + +/** @addtogroup C66XX_I2C DSP I2C functions + * @{ + */ + + +// I2C interrupt codes +#define C66XX_I2C_INTCODE_NONE 0 /**< No interrupt */ +#define C66XX_I2C_INTCODE_AL 1 /**< Arbitration-lost interrupt */ +#define C66XX_I2C_INTCODE_NACK 2 /**< No-acknowledge interrupt */ +#define C66XX_I2C_INTCODE_ARDY 3 /**< Register-access-ready interrupt */ +#define C66XX_I2C_INTCODE_ICRRDY 4 /**< Receive-data-ready interrupt */ +#define C66XX_I2C_INTCODE_ICXRDY 5 /**< Transmit-data-ready interrupt */ +#define C66XX_I2C_INTCODE_SCD 6 /**< Stop-condition-detected interrupt */ +#define C66XX_I2C_INTCODE_AAS 7 /**< Address-as-slave interrupt */ + + +/*------------ C66XX_I2C_init() function ---------------------------------*//** + * @brief Function inits the I2C peripheral + * + * @param[in] core_clk - DSP core clock frequency in MHz; + * @param[in] i2c_clk - I2C clock in Hz; + * @param[in] own_addr - I2C own slave address; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_I2C_init(uint32_t core_clk, uint32_t i2c_clk, uint32_t own_addr); + + +/*------------ C66XX_I2C_write_data() function ---------------------------*//** + * @brief Function writes data[len] to I2C chip_addr at mem_addr memory + * address + * + * @param[in] chip_addr - I2C chip address; + * @param[in] mem_addr - memory (register) address within the chip; + * @param[in] mem_addr_len - number of bytes to use for mem_addr (typically 1, + * 2 for larger memories, 0 for register type devices with only + * one register); + * @param[in] data - pointer to data; + * @param[in] len - data len in bytes; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_I2C_write_data(uint8_t chip_addr, uint32_t mem_addr, uint32_t mem_addr_len, uint8_t *data, uint32_t len); + + +/*------------ C66XX_I2C_read_data() function ----------------------------*//** + * @brief Function reads data[len] from I2C chip_addr at mem_addr memory + * + * @param[in] chip_addr - I2C chip address; + * @param[in] mem_addr - memory (register) address within the chip; + * @param[in] mem_addr_len - number of bytes to use for mem_addr (typically 1, + * 2 for larger memories, 0 for register type devices with only + * one register); + * @param[out] buf - pointer to data buffer to store data; + * @param[in] len - data len in bytes; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_I2C_read_data(uint8_t chip_addr, uint32_t mem_addr, uint32_t mem_addr_len, uint8_t *buf, uint32_t len); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ Gigabit Ethernet (GbE) Switch functions ======================== +//============================================================================= + +/** @addtogroup C66XX_GBE DSP Gigabit Ethernet Switch functions + * @{ + */ + +/*------------ C66XX_GBE_get_mac_id() function ---------------------------*//** + * @brief Function returns DSP MAC address for this device + * + * @return 64-bit variable that contains 48-bit MAC ID + * +-----------------------------------------------------------------------------*/ +uint64_t C66XX_GBE_get_mac_id(void); + + +/*------------ C66XX_GBE_init_serdes() function --------------------------*//** + * @brief Function inits Gigabit Ethernet Serdes block to the default state + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_GBE_init_serdes(void); + + +/** SGMII port Slave operation mode */ +#define C66XX_SGMII_PORT_SLAVE_MODE 0 +/** SGMII port Master operation mode */ +#define C66XX_SGMII_PORT_MASTER_MODE 1 + + +/** SGMII port autonegotiation disabled */ +#define C66XX_SGMII_PORT_AUTONEGOTIATION_DISABLED 0 +/** SGMII port autonegotiation enabled */ +#define C66XX_SGMII_PORT_AUTONEGOTIATION_ENABLED 1 + + +/*------------ C66XX_GBE_init_sgmii() function ---------------------------*//** + * @brief Function inits Gigabit Ethernet SGMII block + * + * Note that this function requires the presence of link partner connected + * at specified SGMII port - PHY or another SGMII. + * + * @param[in] port - MAC port number for which the SGMII port setup should + * be performed + * @param[in] mode - SGMII port operation mode: master or slave. + * @param[in] autoneg - flag to enable autonegotiation on this SGMII port. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_GBE_init_sgmii(uint32_t port, uint32_t mode, uint32_t autoneg); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ SRIO functions ================================================= +//============================================================================= + +/** @addtogroup C66XX_SRIO DSP SRIO functions + * @{ + */ + +/** SRIO vendor identifier */ +#define C66XX_SRIO_DEVICE_VENDOR_ID 0x30 +/** SRIO device revision */ +#define C66XX_SRIO_DEVICE_REVISION 0x0 +/** SRIO assembly identifier */ +#define C66XX_SRIO_DEVICE_ASSEMBLY_ID 0x0 +/** SRIO assembly vendor identifier */ +#define C66XX_SRIO_DEVICE_ASSEMBLY_VENDOR_ID C66XX_SRIO_DEVICE_VENDOR_ID +/** SRIO assembly device revision */ +#define C66XX_SRIO_DEVICE_ASSEMBLY_REVISION C66XX_SRIO_DEVICE_REVISION +/** SRIO assembly extension features */ +#define C66XX_SRIO_DEVICE_ASSEMBLY_FEATURES 0x0100 + + +/** SRIO link rate 1.25 Gbps */ +#define C66XX_SRIO_LINK_RATE_1_25GB 1 +/** SRIO link rate 2.5 Gbps */ +#define C66XX_SRIO_LINK_RATE_2_5GB 2 +/** SRIO link rate 3.125 Gbps */ +#define C66XX_SRIO_LINK_RATE_3_125GB 3 +/** SRIO link rate 5 Gbps */ +#define C66XX_SRIO_LINK_RATE_5GB 4 + + +// SRIO port widths defs - corresponds to SRIO path modes +/** SRIO port width with 1 receive and transmit lane */ +#define C66XX_SRIO_PORT_WIDTH_1X 0 +/** SRIO port width with 2 receive and transmit lanes */ +#define C66XX_SRIO_PORT_WIDTH_2X 3 +/** SRIO port width with 4 receive and transmit lanes */ +#define C66XX_SRIO_PORT_WIDTH_4X 4 + + +/** SRIO port 0 */ +#define C66XX_SRIO_PORT_0 0 +/** SRIO port 1 */ +#define C66XX_SRIO_PORT_1 1 +/** SRIO port 2 */ +#define C66XX_SRIO_PORT_2 2 +/** SRIO port 3 */ +#define C66XX_SRIO_PORT_3 3 + + +/** SRIO peripheral normal operation mode */ +#define C66XX_SRIO_OPMODE_NORMAL 0 +/** SRIO peripheral loopback operation mode - used to test the peripheral */ +#define C66XX_SRIO_OPMODE_LOOPBACK 1 + + +/** SRIO device identificator data descriptor */ +typedef struct +{ + uint32_t dev_id_8bit; /**< SRIO 8-bit device identificator */ + uint32_t dev_id_16bit; /**< SRIO 16-bit device identificator */ +} C66XX_SRIO_DEVICE_ID_DD; + +// SRIO device identificator data descriptor length in bytes +#define C66XX_SRIO_DEVICE_ID_DD_LEN sizeof(C66XX_SRIO_DEVICE_ID_DD) + + +/** SRIO destination device identificators number */ +#define C66XX_SRIO_DESTINATION_DEVICE_ID_COUNT 4 + + +/** SRIO messages (Type9 and Type11) transmit queues mapping data descriptor */ +typedef struct +{ + uint32_t port; /**< SRIO port to which the queue is mapped */ + uint32_t priority; /**< priority bit */ +} C66XX_SRIO_TX_QUEUE_SCH_DD; + +// SRIO messages (Type9 and Type11) transmit queues mapping data descriptor length in bytes +#define C66XX_SRIO_TX_QUEUE_SCH_DD_LEN sizeof(C66XX_SRIO_TX_QUEUE_SCH_DD) + + +/** SRIO peripheral initialization data descriptor */ +typedef struct +{ + uint32_t mode; /**< SRIO peripheral operation mode */ + uint32_t link_rate; /**< SRIO link rate definition */ + uint32_t port_width; /**< SRIO port width definition (1x, 2x, or 4x) */ + C66XX_SRIO_DEVICE_ID_DD src_dev_id_dd; /**< SRIO base device identificators */ + C66XX_SRIO_DEVICE_ID_DD dst_dev_id_dd[C66XX_SRIO_DESTINATION_DEVICE_ID_COUNT]; /**< SRIO destination device identificators */ +} C66XX_SRIO_DD; + +// SRIO peripheral initialization data descriptor length in bytes +#define C66XX_SRIO_DD_LEN sizeof(C66XX_SRIO_DD) + + +/*------------ C66XX_SRIO_init() function --------------------------------*//** + * @brief Function inits the SRIO peripheral + * + * The function does the following: + * 1. SRIO peripheral supports directIO, doorbell, data messaging (Type9 + * packets) and data streaming (Type11 packets) operations. + * 2. Max MTU length is set to 256 bytes. + * 3. SRIO 8-bit and 16-bit base device IDs are set to supplied parameters. + * 4. Available destination SRIO 8-bit and 16-bit device IDs are set + * according to supplied parameters. + * 5. Operation mode is set according to supplied parameter. + * 6. Link rate and ports configuration (4 ports are available) are set + * according to supplied parameters. + * 7. SRIO transmit queues used in data message (Type9 and Type11) operations + * are configured by default: all 16 queues send packets onto Port 0 and + * operate at the same minimum priority level. In case the different mapping + * is needed then C66XX_srio_map_tx_queue() function should be called. + * 8. 64 SRIO doorbell interrupts are configured by default: the first 16 + * interrupts (0-15) are routed to INTDST16 (Interrupt destination 16), + * 16-31 - to INTDST17 (Interrupt destination 17), 32-47 - to INTDST18 + * (Interrupt destination 18), 48-63 - to INTDST19 (Interrupt destination + * 19). In case the different interrupt routing is needed then + * C66XX_srio_route_doorbell_interrupt() function should be called. + * 9. GARBAGE queues, which can used by the TXU, are not configured. + * + * @param[in] srio_dd - SRIO peripheral initialization data descriptor + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SRIO_init(C66XX_SRIO_DD *srio_dd); + + +/*------------ C66XX_SRIO_map_tx_queue() function ------------------------*//** + * @brief Function configures the selected SRIO transmit queue according to + * supplied parameters: SRIO port to which the queue is mapped and priority + * bit + * + * @param[in] queue - transmit queue number (0 - 15) + * @param[in] tx_queue_sch_dd - transmit queue mapping data descriptor + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SRIO_map_tx_queue(uint32_t queue, C66XX_SRIO_TX_QUEUE_SCH_DD *tx_queue_sch_dd); + + +/*------------ C66XX_SRIO_route_doorbell_interrupt() function ------------*//** + * @brief Function configures the selected SRIO doorbell interrupt to + * specified interrupt destination number + * + * @param[in] doorbell - SRIO doorbell interrupt number (0 - 63) + * @param[in] intdst - interrupt destination number (0 - 23) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t C66XX_SRIO_route_doorbell_interrupt(uint32_t doorbell, uint32_t intdst); + + +/** @}*/ +//============================================================================= + + + +#ifdef __cplusplus +} +#endif + + + +//============================================================================= +#endif /* __C66XX_FUNCTIONS_HXX__ */ diff --git a/ports/c667x/ccs/example_build/include/C66XX_MACROS.hxx b/ports/c667x/ccs/example_build/include/C66XX_MACROS.hxx new file mode 100644 index 00000000..54e7ef57 --- /dev/null +++ b/ports/c667x/ccs/example_build/include/C66XX_MACROS.hxx @@ -0,0 +1,1154 @@ +/****************************************************************************** + TMS320C66xx KeyStone Multicore DSP Software Development Kit (SDK). Rev 2A. + (C) MicroLAB Systems, 2014-2015 + + File: Macros + ----- + + Notes: + ------ + 1. This C-header file contains C66xx DSP macro definitions and + is used with C66XX.h C-header file. + + 2. This file is best viewed with the TAB setting set to '4'. + +******************************************************************************/ + + +/** + * @file C66XX_MACROS.hxx + * + * @brief Macros + * + * This file contains C66xx DSP macro definitions + * + */ + + +#ifndef __C66XX_MACROS_HXX__ // check for this file has been already included +#define __C66XX_MACROS_HXX__ 1 + + +//============================================================================= +//------------ I/O peripherals data type selector for C66xx DSP --------------- +// C66xx DSP has all I/O peripherals aligned as LSB of 32-bit words, then +// I/O peripherals should be accessed as UNSIGNED only. + +// The declared __C66XX_IO_DATA_TYPE__ is used to unify below macros and +// functions and to make particular selection at the run-time compilation time. +//================================================================ + +typedef volatile uint32_t __C66XX_IO_DATA_TYPE__; + +// read-back data bitmask for DSP memory-mapped registers (32-bit wide) +#define C66XX_RG_DATA_BITMASK 0xffffffff +//============================================================================= + + + +//============================================================================= +//============ General register access macros ================================= +//============================================================================= +// Macro to get selected register value +#define C66XX_GET_RG_VALUE(addr) ((*(__C66XX_IO_DATA_TYPE__ *) addr) & C66XX_RG_DATA_BITMASK) + +// Macro to set selected register to value +#define C66XX_SET_RG_VALUE(addr, val) ((*(__C66XX_IO_DATA_TYPE__ *) addr) = (val & C66XX_RG_DATA_BITMASK)) + +// Macro to make FIELD for the supplied value +#define C66XX_MAKE_FIELD(FIELD, val) (((val) << C66XX_##FIELD##_BITSHIFT) & C66XX_##FIELD##_BITMASK) + +// Macro to get FIELD value from the selected register +#define C66XX_GET_FIELD_VALUE(addr, FIELD) (((*(__C66XX_IO_DATA_TYPE__ *) addr) & C66XX_##FIELD##_BITMASK) >> C66XX_##FIELD##_BITSHIFT) + +// Macro to set FIELD to value in the selected register +#define C66XX_SET_FIELD_VALUE(addr, FIELD, val) ((*(__C66XX_IO_DATA_TYPE__ *) addr) = ((*(__C66XX_IO_DATA_TYPE__ *) addr) & ~C66XX_##FIELD##_BITMASK) | C66XX_MAKE_FIELD(FIELD, val)) + +//============================================================================= + + + +//============================================================================= +//============ DSP core registers macros ====================================== +//============================================================================= + +//------------ DSP CorePack revision register macros -------------------------- +#define C66XX_get_core_mm_revid_rg() C66XX_GET_RG_VALUE(C66XX_CORE_MM_REVID_RG_ADDR) + + // dedicated bit specific macros +#define C66XX_get_core_mm_revid_version() C66XX_GET_FIELD_VALUE(C66XX_CORE_MM_REVID_RG_ADDR, CORE_MM_REVID_VERSION) +#define C66XX_get_core_mm_revid_revision() C66XX_GET_FIELD_VALUE(C66XX_CORE_MM_REVID_RG_ADDR, CORE_MM_REVID_REVISION) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_CORE_MM_REVID_VERSION_IS_C6678 (C66XX_get_core_mm_revid_version() == C66XX_CORE_MM_REVID_VERSION_C6678) +#define C66XX_CORE_MM_REVID_REVISION_IS_1_0 (C66XX_get_core_mm_revid_revision() == C66XX_CORE_MM_REVID_REVISION_1_0) +#define C66XX_CORE_MM_REVID_REVISION_IS_2_0 (C66XX_get_core_mm_revid_revision() == C66XX_CORE_MM_REVID_REVISION_2_0) + +//------------ DSP interrupt controller registers macros ---------------------- +// i index corresonds to DSP Event registers number +// Note that i index should be from 0 to 3 !!! +#define C66XX_get_core_evtflag_rg_addr(i) (C66XX_CORE_EVTFLAG_RG_BADDR + i * C66XX_CORE_EVTFLAG_RG_OFFSET) +#define C66XX_get_core_evtflag_rg(i) C66XX_GET_RG_VALUE(C66XX_get_core_evtflag_rg_addr(i)) + +#define C66XX_get_core_evtset_rg_addr(i) (C66XX_CORE_EVTSET_RG_BADDR + i * C66XX_CORE_EVTSET_RG_OFFSET) +#define C66XX_set_core_evtset_rg(i, v) C66XX_SET_RG_VALUE(C66XX_get_core_evtset_rg_addr(i), v) + +#define C66XX_get_core_evtclr_rg_addr(i) (C66XX_CORE_EVTCLR_RG_BADDR + i * C66XX_CORE_EVTCLR_RG_OFFSET) +#define C66XX_set_core_evtclr_rg(i, v) C66XX_SET_RG_VALUE(C66XX_get_core_evtclr_rg_addr(i), v) + +#define C66XX_get_core_evtmask_rg_addr(i) (C66XX_CORE_EVTMASK_RG_BADDR + i * C66XX_CORE_EVTMASK_RG_OFFSET) +#define C66XX_get_core_evtmask_rg(i) C66XX_GET_RG_VALUE(C66XX_get_core_evtmask_rg_addr(i)) +#define C66XX_set_core_evtmask_rg(i, v) C66XX_SET_RG_VALUE(C66XX_get_core_evtmask_rg_addr(i), v) + +//------------ DSP interrupt macros ------------------------------------------- +// These macros are used to set/get particular DSP Event in DSP Event registers +// i index corresonds to DSP Event ID number (0 - 127) +#define C66XX_get_core_event_id_rg(i) (i / 32) +#define C66XX_get_core_event_id_bitmask(i) (0x1 << (i % 32)) + +#define C66XX_get_core_event_id_flag(i) (C66XX_get_core_evtflag_rg(C66XX_get_core_event_id_rg(i)) & C66XX_get_core_event_id_bitmask(i)) +#define C66XX_set_core_event_id_flag(i) (C66XX_set_core_evtset_rg(C66XX_get_core_event_id_rg(i), C66XX_get_core_event_id_bitmask(i))) +#define C66XX_clear_core_event_id_flag(i) (C66XX_set_core_evtclr_rg(C66XX_get_core_event_id_rg(i), C66XX_get_core_event_id_bitmask(i))) +#define C66XX_get_core_event_id_mask(i) (C66XX_get_core_evtmask_rg(C66XX_get_core_event_id_rg(i)) & C66XX_get_core_event_id_bitmask(i)) +#define C66XX_set_core_event_id_mask(i) (C66XX_set_core_evtmask_rg(C66XX_get_core_event_id_rg(i), C66XX_get_core_event_id_bitmask(i))) + +//============================================================================= + + + +//============================================================================= +//============ PLL controller registers macros ================================ +//============================================================================= + +//------------ PLL control register macros ------------------------------------ +#define C66XX_get_pll_pllctl_rg() C66XX_GET_RG_VALUE(C66XX_PLL_PLLCTL_RG_ADDR) +#define C66XX_set_pll_pllctl_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_pll_pllctl_pllensrc() C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLENSRC) +#define C66XX_set_pll_pllctl_pllensrc(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLENSRC, v) +#define C66XX_get_pll_pllctl_pllrst() C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLRST) +#define C66XX_set_pll_pllctl_pllrst(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLRST, v) +#define C66XX_get_pll_pllctl_pllpwrdn() C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLPWRDN) +#define C66XX_set_pll_pllctl_pllpwrdn(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLPWRDN, v) +#define C66XX_get_pll_pllctl_pllen() C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLEN) +#define C66XX_set_pll_pllctl_pllen(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLCTL_PLLEN, v) + + // direct bit set macros +#define C66XX_SET_PLL_PLLCTL_PLLENSRC_ON C66XX_set_pll_pllctl_pllensrc(C66XX_ON) +#define C66XX_SET_PLL_PLLCTL_PLLENSRC_OFF C66XX_set_pll_pllctl_pllensrc(C66XX_OFF) +#define C66XX_SET_PLL_PLLCTL_PLLRST_ON C66XX_set_pll_pllctl_pllrst(C66XX_ON) +#define C66XX_SET_PLL_PLLCTL_PLLRST_OFF C66XX_set_pll_pllctl_pllrst(C66XX_OFF) +#define C66XX_SET_PLL_PLLCTL_PLLPWRDN_ON C66XX_set_pll_pllctl_pllpwrdn(C66XX_ON) +#define C66XX_SET_PLL_PLLCTL_PLLPWRDN_OFF C66XX_set_pll_pllctl_pllpwrdn(C66XX_OFF) +#define C66XX_SET_PLL_PLLCTL_PLLEN_ON C66XX_set_pll_pllctl_pllen(C66XX_ON) +#define C66XX_SET_PLL_PLLCTL_PLLEN_OFF C66XX_set_pll_pllctl_pllen(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_PLL_PLLCTL_PLLENSRC_IS_ON (C66XX_get_pll_pllctl_pllensrc() == C66XX_ON) +#define C66XX_PLL_PLLCTL_PLLRST_IS_ON (C66XX_get_pll_pllctl_pllrst() == C66XX_ON) +#define C66XX_PLL_PLLCTL_PLLPWRDN_IS_ON (C66XX_get_pll_pllctl_pllpwrdn() == C66XX_ON) +#define C66XX_PLL_PLLCTL_PLLEN_IS_ON (C66XX_get_pll_pllctl_pllen() == C66XX_ON) + + +//------------ PLL secondary control register macros -------------------------- +#define C66XX_get_pll_secctl_rg() C66XX_GET_RG_VALUE(C66XX_PLL_SECCTL_RG_ADDR) +#define C66XX_set_pll_secctl_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_SECCTL_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_pll_secctl_bypass() C66XX_GET_FIELD_VALUE(C66XX_PLL_SECCTL_RG_ADDR, PLL_SECCTL_BYPASS) +#define C66XX_set_pll_secctl_bypass(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_SECCTL_RG_ADDR, PLL_SECCTL_BYPASS, v) +#define C66XX_get_pll_secctl_output_divide() C66XX_GET_FIELD_VALUE(C66XX_PLL_SECCTL_RG_ADDR, PLL_SECCTL_OUTPUT_DIVIDE) +#define C66XX_set_pll_secctl_output_divide(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_SECCTL_RG_ADDR, PLL_SECCTL_OUTPUT_DIVIDE, v) + + // direct bit set macros +#define C66XX_SET_PLL_SECCTL_BYPASS_ON C66XX_set_pll_secctl_bypass(C66XX_ON) +#define C66XX_SET_PLL_SECCTL_BYPASS_OFF C66XX_set_pll_secctl_bypass(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_PLL_SECCTL_BYPASS_IS_ON (C66XX_get_pll_secctl_bypass() == C66XX_ON) + + +//------------ PLL multiplier control register macros ------------------------- +#define C66XX_get_pll_pllm_rg() C66XX_GET_RG_VALUE(C66XX_PLL_PLLM_RG_ADDR) +#define C66XX_set_pll_pllm_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_PLLM_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_pll_pllm_pllm() C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLM_RG_ADDR, PLL_PLLM_PLLM) +#define C66XX_set_pll_pllm_pllm(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLM_RG_ADDR, PLL_PLLM_PLLM, v) + + +//------------ PLL controller divider registers macros ------------------------ +// i index corresonds to PLL controller divider registers number +// Note that i index should be from 0 to 15 instead of 1 to 16 !!! +#define C66XX_get_pll_plldiv_rg_addr(i) (i < 3 ? (C66XX_PLL_PLLDIV1_RG_ADDR + i * 0x4) : (C66XX_PLL_PLLDIV4_RG_ADDR + (i - 3) * 0x4)) +#define C66XX_get_pll_plldiv_rg(i) C66XX_GET_RG_VALUE(C66XX_get_pll_plldiv_rg_addr(i)) +#define C66XX_set_pll_plldiv_rg(i, v) C66XX_SET_RG_VALUE(C66XX_get_pll_plldiv_rg_addr(i), v) + + // dedicated bit specific macros +#define C66XX_get_pll_plldiv_den(i) C66XX_GET_FIELD_VALUE(C66XX_get_pll_plldiv_rg_addr(i), PLL_PLLDIV_DEN) +#define C66XX_set_pll_plldiv_den(i, v) C66XX_SET_FIELD_VALUE(C66XX_get_pll_plldiv_rg_addr(i), PLL_PLLDIV_DEN, v) +#define C66XX_get_pll_plldiv_ratio(i) C66XX_GET_FIELD_VALUE(C66XX_get_pll_plldiv_rg_addr(i), PLL_PLLDIV_RATIO) +#define C66XX_set_pll_plldiv_ratio(i, v) C66XX_SET_FIELD_VALUE(C66XX_get_pll_plldiv_rg_addr(i), PLL_PLLDIV_RATIO, v) + + // direct bit set macros +#define C66XX_SET_PLL_PLLDIV_DEN_ON(i) C66XX_set_pll_plldiv_den(i, C66XX_ON) +#define C66XX_SET_PLL_PLLDIV_DEN_OFF(i) C66XX_set_pll_plldiv_den(i, C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_PLL_PLLDIV_DEN_IS_ON(i) (C66XX_get_pll_plldiv_den(i) == C66XX_ON) + + +//------------ PLL controller command register macros ------------------------- +#define C66XX_get_pll_pllcmd_rg() C66XX_GET_RG_VALUE(C66XX_PLL_PLLCMD_RG_ADDR) +#define C66XX_set_pll_pllcmd_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_PLLCMD_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_pll_pllcmd_goset() C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLCMD_RG_ADDR, PLL_PLLCMD_GOSET) +#define C66XX_set_pll_pllcmd_goset(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCMD_RG_ADDR, PLL_PLLCMD_GOSET, v) + + // direct bit set macros +#define C66XX_SET_PLL_PLLCMD_GOSET_ON C66XX_set_pll_pllcmd_goset(C66XX_ON) +#define C66XX_SET_PLL_PLLCMD_GOSET_OFF C66XX_set_pll_pllcmd_goset(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_PLL_PLLCMD_GOSET_IS_ON (C66XX_get_pll_pllcmd_goset() == C66XX_ON) + + +//------------ PLL controller status register macros -------------------------- +#define C66XX_get_pll_pllstat_rg() C66XX_GET_RG_VALUE(C66XX_PLL_PLLSTAT_RG_ADDR) +#define C66XX_set_pll_pllstat_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_PLLSTAT_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_pll_pllstat_gostat() C66XX_GET_FIELD_VALUE(C66XX_PLL_PLLSTAT_RG_ADDR, PLL_PLLSTAT_GOSTAT) +#define C66XX_set_pll_pllstat_gostat(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLSTAT_RG_ADDR, PLL_PLLSTAT_GOSTAT, v) + + // direct bit set macros +#define C66XX_SET_PLL_PLLSTAT_GOSTAT_ON C66XX_set_pll_pllstat_gostat(C66XX_ON) +#define C66XX_SET_PLL_PLLSTAT_GOSTAT_OFF C66XX_set_pll_pllstat_gostat(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_PLL_PLLSTAT_GOSTAT_IS_ON (C66XX_get_pll_pllstat_gostat() == C66XX_ON) + + +//------------ PLL controller clock align control register macros ------------- +#define C66XX_get_pll_alnctl_rg() C66XX_GET_RG_VALUE(C66XX_PLL_ALNCTL_RG_ADDR) +#define C66XX_set_pll_alnctl_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_ALNCTL_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_pll_alnctl_aln() C66XX_GET_FIELD_VALUE(C66XX_PLL_ALNCTL_RG_ADDR, PLL_ALNCTL_ALN) +#define C66XX_set_pll_alnctl_aln(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_ALNCTL_RG_ADDR, PLL_ALNCTL_ALN, v) + + +//------------ PLL controller divider ratio change status register macros ----- +#define C66XX_get_pll_dchange_rg() C66XX_GET_RG_VALUE(C66XX_PLL_DCHANGE_RG_ADDR) +#define C66XX_set_pll_dchange_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_DCHANGE_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_pll_dchange_sys() C66XX_GET_FIELD_VALUE(C66XX_PLL_DCHANGE_RG_ADDR, PLL_DCHANGE_SYS) +#define C66XX_set_pll_dchange_sys(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_DCHANGE_RG_ADDR, PLL_DCHANGE_SYS, v) + + +//------------ SYSCLK status register macros ---------------------------------- +#define C66XX_get_pll_systat_rg() C66XX_GET_RG_VALUE(C66XX_PLL_SYSTAT_RG_ADDR) + + // dedicated bit specific macros +#define C66XX_get_pll_systat_syson() C66XX_GET_FIELD_VALUE(C66XX_PLL_SYSTAT_RG_ADDR, PLL_SYSTAT_SYSON) + +//============================================================================= + + + +//============================================================================= +//============ Device State Control registers macros ========================== +//============================================================================= + +//------------ Main PLL Control register 0 macros ----------------------------- +#define C66XX_get_bootcfg_mainpllctl0_rg() C66XX_GET_RG_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR) +#define C66XX_set_bootcfg_mainpllctl0_rg(v) C66XX_SET_RG_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_bootcfg_mainpllctl0_bwadj() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_BWADJ) +#define C66XX_set_bootcfg_mainpllctl0_bwadj(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_BWADJ, v) +#define C66XX_get_bootcfg_mainpllctl0_pllm() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_PLLM) +#define C66XX_set_bootcfg_mainpllctl0_pllm(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_PLLM, v) +#define C66XX_get_bootcfg_mainpllctl0_plld() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_PLLD) +#define C66XX_set_bootcfg_mainpllctl0_plld(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL0_RG_ADDR, BOOTCFG_MAINPLLCTL0_PLLD, v) + + +//------------ Main PLL Control register 1 macros ----------------------------- +#define C66XX_get_bootcfg_mainpllctl1_rg() C66XX_GET_RG_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR) +#define C66XX_set_bootcfg_mainpllctl1_rg(v) C66XX_SET_RG_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_bootcfg_mainpllctl1_ensat() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, BOOTCFG_MAINPLLCTL1_ENSAT) +#define C66XX_set_bootcfg_mainpllctl1_ensat(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, BOOTCFG_MAINPLLCTL1_ENSAT, v) +#define C66XX_get_bootcfg_mainpllctl1_bwadj() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, BOOTCFG_MAINPLLCTL1_BWADJ) +#define C66XX_set_bootcfg_mainpllctl1_bwadj(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_MAINPLLCTL1_RG_ADDR, BOOTCFG_MAINPLLCTL1_BWADJ, v) + + // direct bit set macros +#define C66XX_SET_BOOTCFG_MAINPLLCTL1_ENSAT_ON C66XX_set_bootcfg_mainpllctl1_ensat(C66XX_ON) +#define C66XX_SET_BOOTCFG_MAINPLLCTL1_ENSAT_OFF C66XX_set_bootcfg_mainpllctl1_ensat(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_BOOTCFG_MAINPLLCTL1_ENSAT_IS_ON (C66XX_get_bootcfg_mainpllctl1_ensat() == C66XX_ON) + + +//------------ DDR3 PLL Control register 0 macros ----------------------------- +#define C66XX_get_bootcfg_ddr3pllctl0_rg() C66XX_GET_RG_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR) +#define C66XX_set_bootcfg_ddr3pllctl0_rg(v) C66XX_SET_RG_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_bootcfg_ddr3pllctl0_bwadj() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_BWADJ) +#define C66XX_set_bootcfg_ddr3pllctl0_bwadj(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_BWADJ, v) +#define C66XX_get_bootcfg_ddr3pllctl0_bypass() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_BYPASS) +#define C66XX_set_bootcfg_ddr3pllctl0_bypass(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_BYPASS, v) +#define C66XX_get_bootcfg_ddr3pllctl0_pllm() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_PLLM) +#define C66XX_set_bootcfg_ddr3pllctl0_pllm(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_PLLM, v) +#define C66XX_get_bootcfg_ddr3pllctl0_plld() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_PLLD) +#define C66XX_set_bootcfg_ddr3pllctl0_plld(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL0_RG_ADDR, BOOTCFG_DDR3PLLCTL0_PLLD, v) + + // direct bit set macros +#define C66XX_SET_BOOTCFG_DDR3PLLCTL0_BYPASS_ON C66XX_set_bootcfg_ddr3pllctl0_bypass(C66XX_ON) +#define C66XX_SET_BOOTCFG_DDR3PLLCTL0_BYPASS_OFF C66XX_set_bootcfg_ddr3pllctl0_bypass(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_BOOTCFG_DDR3PLLCTL0_BYPASS_IS_ON (C66XX_get_bootcfg_ddr3pllctl0_bypass() == C66XX_ON) + + +//------------ DDR3 PLL Control register 1 macros ----------------------------- +#define C66XX_get_bootcfg_ddr3pllctl1_rg() C66XX_GET_RG_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR) +#define C66XX_set_bootcfg_ddr3pllctl1_rg(v) C66XX_SET_RG_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_bootcfg_ddr3pllctl1_pllrst() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_PLLRST) +#define C66XX_set_bootcfg_ddr3pllctl1_pllrst(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_PLLRST, v) +#define C66XX_get_bootcfg_ddr3pllctl1_ensat() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_ENSAT) +#define C66XX_set_bootcfg_ddr3pllctl1_ensat(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_ENSAT, v) +#define C66XX_get_bootcfg_ddr3pllctl1_bwadj() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_BWADJ) +#define C66XX_set_bootcfg_ddr3pllctl1_bwadj(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_DDR3PLLCTL1_RG_ADDR, BOOTCFG_DDR3PLLCTL1_BWADJ, v) + + // direct bit set macros +#define C66XX_SET_BOOTCFG_DDR3PLLCTL1_PLLRST_ON C66XX_set_bootcfg_ddr3pllctl1_pllrst(C66XX_ON) +#define C66XX_SET_BOOTCFG_DDR3PLLCTL1_PLLRST_OFF C66XX_set_bootcfg_ddr3pllctl1_pllrst(C66XX_OFF) +#define C66XX_SET_BOOTCFG_DDR3PLLCTL1_ENSAT_ON C66XX_set_bootcfg_ddr3pllctl1_ensat(C66XX_ON) +#define C66XX_SET_BOOTCFG_DDR3PLLCTL1_ENSAT_OFF C66XX_set_bootcfg_ddr3pllctl1_ensat(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_BOOTCFG_DDR3PLLCTL1_PLLRST_IS_ON (C66XX_get_bootcfg_ddr3pllctl1_pllrst() == C66XX_ON) +#define C66XX_BOOTCFG_DDR3PLLCTL1_ENSAT_IS_ON (C66XX_get_bootcfg_ddr3pllctl1_ensat() == C66XX_ON) + + +//------------ PASS PLL Control register 0 macros ----------------------------- +#define C66XX_get_bootcfg_passpllctl0_rg() C66XX_GET_RG_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR) +#define C66XX_set_bootcfg_passpllctl0_rg(v) C66XX_SET_RG_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_bootcfg_passpllctl0_bwadj() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_BWADJ) +#define C66XX_set_bootcfg_passpllctl0_bwadj(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_BWADJ, v) +#define C66XX_get_bootcfg_passpllctl0_bypass() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_BYPASS) +#define C66XX_set_bootcfg_passpllctl0_bypass(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_BYPASS, v) +#define C66XX_get_bootcfg_passpllctl0_pllm() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_PLLM) +#define C66XX_set_bootcfg_passpllctl0_pllm(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_PLLM, v) +#define C66XX_get_bootcfg_passpllctl0_plld() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_PLLD) +#define C66XX_set_bootcfg_passpllctl0_plld(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL0_RG_ADDR, BOOTCFG_PASSPLLCTL0_PLLD, v) + + // direct bit set macros +#define C66XX_SET_BOOTCFG_PASSPLLCTL0_BYPASS_ON C66XX_set_bootcfg_passpllctl0_bypass(C66XX_ON) +#define C66XX_SET_BOOTCFG_PASSPLLCTL0_BYPASS_OFF C66XX_set_bootcfg_passpllctl0_bypass(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_BOOTCFG_PASSPLLCTL0_BYPASS_IS_ON (C66XX_get_bootcfg_passpllctl0_bypass() == C66XX_ON) + + +//------------ PASS PLL Control register 1 macros ----------------------------- +#define C66XX_get_bootcfg_passpllctl1_rg() C66XX_GET_RG_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR) +#define C66XX_set_bootcfg_passpllctl1_rg(v) C66XX_SET_RG_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_bootcfg_passpllctl1_pllrst() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_PLLRST) +#define C66XX_set_bootcfg_passpllctl1_pllrst(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_PLLRST, v) +#define C66XX_get_bootcfg_passpllctl1_pllselect() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_PLLSELECT) +#define C66XX_set_bootcfg_passpllctl1_pllselect(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_PLLSELECT, v) +#define C66XX_get_bootcfg_passpllctl1_ensat() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_ENSAT) +#define C66XX_set_bootcfg_passpllctl1_ensat(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_ENSAT, v) +#define C66XX_get_bootcfg_passpllctl1_bwadj() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_BWADJ) +#define C66XX_set_bootcfg_passpllctl1_bwadj(v) C66XX_SET_FIELD_VALUE(C66XX_BOOTCFG_PASSPLLCTL1_RG_ADDR, BOOTCFG_PASSPLLCTL1_BWADJ, v) + + // direct bit set macros +#define C66XX_SET_BOOTCFG_PASSPLLCTL1_PLLRST_ON C66XX_set_bootcfg_passpllctl1_pllrst(C66XX_ON) +#define C66XX_SET_BOOTCFG_PASSPLLCTL1_PLLRST_OFF C66XX_set_bootcfg_passpllctl1_pllrst(C66XX_OFF) +#define C66XX_SET_BOOTCFG_PASSPLLCTL1_PLLSELECT_ON C66XX_set_bootcfg_passpllctl1_pllselect(C66XX_ON) +#define C66XX_SET_BOOTCFG_PASSPLLCTL1_PLLSELECT_OFF C66XX_set_bootcfg_passpllctl1_pllselect(C66XX_OFF) +#define C66XX_SET_BOOTCFG_PASSPLLCTL1_ENSAT_ON C66XX_set_bootcfg_passpllctl1_ensat(C66XX_ON) +#define C66XX_SET_BOOTCFG_PASSPLLCTL1_ENSAT_OFF C66XX_set_bootcfg_passpllctl1_ensat(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_BOOTCFG_PASSPLLCTL1_PLLRST_IS_ON (C66XX_get_bootcfg_passpllctl1_pllrst() == C66XX_ON) +#define C66XX_BOOTCFG_PASSPLLCTL1_PLLSELECT_IS_ON (C66XX_get_bootcfg_passpllctl1_pllselect() == C66XX_ON) +#define C66XX_BOOTCFG_PASSPLLCTL1_ENSAT_IS_ON (C66XX_get_bootcfg_passpllctl1_ensat() == C66XX_ON) + + +//------------ Device speed register macros ----------------------------------- +#define C66XX_get_bootcfg_devspeed_rg() C66XX_GET_RG_VALUE(C66XX_BOOTCFG_DEVSPEED_RG_ADDR) + // dedicated bit specific macros +#define C66XX_get_bootcfg_devspeed_devspeed() C66XX_GET_FIELD_VALUE(C66XX_BOOTCFG_DEVSPEED_RG_ADDR, BOOTCFG_DEVSPEED_DEVSPEED) + +//============================================================================= + + + +//============================================================================= +//============ I2C registers macros =========================================== +//============================================================================= + +//------------ I2C own address register macros -------------------------------- +#define C66XX_get_i2c_icoar_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICOAR_RG_ADDR) +#define C66XX_set_i2c_icoar_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICOAR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icoar_oaddr() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICOAR_RG_ADDR, I2C_ICOAR_OADDR) +#define C66XX_set_i2c_icoar_oaddr(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICOAR_RG_ADDR, I2C_ICOAR_OADDR, v) + + +//------------ I2C interrupt mask register macros ----------------------------- +#define C66XX_get_i2c_icimr_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICIMR_RG_ADDR) +#define C66XX_set_i2c_icimr_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICIMR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icimr_aas() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_AAS) +#define C66XX_set_i2c_icimr_aas(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_AAS, v) +#define C66XX_get_i2c_icimr_scd() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_SCD) +#define C66XX_set_i2c_icimr_scd(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_SCD, v) +#define C66XX_get_i2c_icimr_icxrdy() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ICXRDY) +#define C66XX_set_i2c_icimr_icxrdy(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ICXRDY, v) +#define C66XX_get_i2c_icimr_icrdrdy() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ICRDRDY) +#define C66XX_set_i2c_icimr_icrdrdy(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ICRDRDY, v) +#define C66XX_get_i2c_icimr_ardy() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ARDY) +#define C66XX_set_i2c_icimr_ardy(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_ARDY, v) +#define C66XX_get_i2c_icimr_nack() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_NACK) +#define C66XX_set_i2c_icimr_nack(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_NACK, v) +#define C66XX_get_i2c_icimr_al() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_AL) +#define C66XX_set_i2c_icimr_al(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICIMR_RG_ADDR, I2C_ICIMR_AL, v) + + // direct bit set macros +#define C66XX_SET_I2C_ICIMR_AAS_ON C66XX_set_i2c_icimr_aas(C66XX_ON) +#define C66XX_SET_I2C_ICIMR_AAS_OFF C66XX_set_i2c_icimr_aas(C66XX_OFF) +#define C66XX_SET_I2C_ICIMR_SCD_ON C66XX_set_i2c_icimr_scd(C66XX_ON) +#define C66XX_SET_I2C_ICIMR_SCD_OFF C66XX_set_i2c_icimr_scd(C66XX_OFF) +#define C66XX_SET_I2C_ICIMR_ICXRDY_ON C66XX_set_i2c_icimr_icxrdy(C66XX_ON) +#define C66XX_SET_I2C_ICIMR_ICXRDY_OFF C66XX_set_i2c_icimr_icxrdy(C66XX_OFF) +#define C66XX_SET_I2C_ICIMR_ICRDRDY_ON C66XX_set_i2c_icimr_icrdrdy(C66XX_ON) +#define C66XX_SET_I2C_ICIMR_ICRDRDY_OFF C66XX_set_i2c_icimr_icrdrdy(C66XX_OFF) +#define C66XX_SET_I2C_ICIMR_ARDY_ON C66XX_set_i2c_icimr_ardy(C66XX_ON) +#define C66XX_SET_I2C_ICIMR_ARDY_OFF C66XX_set_i2c_icimr_ardy(C66XX_OFF) +#define C66XX_SET_I2C_ICIMR_NACK_ON C66XX_set_i2c_icimr_nack(C66XX_ON) +#define C66XX_SET_I2C_ICIMR_NACK_OFF C66XX_set_i2c_icimr_nack(C66XX_OFF) +#define C66XX_SET_I2C_ICIMR_AL_ON C66XX_set_i2c_icimr_al(C66XX_ON) +#define C66XX_SET_I2C_ICIMR_AL_OFF C66XX_set_i2c_icimr_al(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_I2C_ICIMR_AAS_IS_ON (C66XX_get_i2c_icimr_aas() == C66XX_ON) +#define C66XX_I2C_ICIMR_SCD_IS_ON (C66XX_get_i2c_icimr_scd() == C66XX_ON) +#define C66XX_I2C_ICIMR_ICXRDY_IS_ON (C66XX_get_i2c_icimr_icxrdy() == C66XX_ON) +#define C66XX_I2C_ICIMR_ICRDRDY_IS_ON (C66XX_get_i2c_icimr_icrdrdy() == C66XX_ON) +#define C66XX_I2C_ICIMR_ARDY_IS_ON (C66XX_get_i2c_icimr_ardy() == C66XX_ON) +#define C66XX_I2C_ICIMR_NACK_IS_ON (C66XX_get_i2c_icimr_nack() == C66XX_ON) +#define C66XX_I2C_ICIMR_AL_IS_ON (C66XX_get_i2c_icimr_al() == C66XX_ON) + + +//------------ I2C interrupt status register macros --------------------------- +#define C66XX_get_i2c_icstr_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICSTR_RG_ADDR) +#define C66XX_set_i2c_icstr_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICSTR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icstr_sdir() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_SDIR) +#define C66XX_set_i2c_icstr_sdir(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_SDIR, v) +#define C66XX_get_i2c_icstr_nacksnt() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_NACKSNT) +#define C66XX_set_i2c_icstr_nacksnt(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_NACKSNT, v) +#define C66XX_get_i2c_icstr_bb() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_BB) +#define C66XX_set_i2c_icstr_bb(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_BB, v) +#define C66XX_get_i2c_icstr_rsfull() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_RSFULL) +#define C66XX_get_i2c_icstr_xsmt() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_XSMT) +#define C66XX_get_i2c_icstr_aas() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_AAS) +#define C66XX_get_i2c_icstr_ad0() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_AD0) +#define C66XX_get_i2c_icstr_scd() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_SCD) +#define C66XX_set_i2c_icstr_scd(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_SCD, v) +#define C66XX_get_i2c_icstr_icxrdy() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ICXRDY) +#define C66XX_set_i2c_icstr_icxrdy(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ICXRDY, v) +#define C66XX_get_i2c_icstr_icrdrdy() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ICRDRDY) +#define C66XX_set_i2c_icstr_icrdrdy(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ICRDRDY, v) +#define C66XX_get_i2c_icstr_ardy() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ARDY) +#define C66XX_set_i2c_icstr_ardy(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_ARDY, v) +#define C66XX_get_i2c_icstr_nack() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_NACK) +#define C66XX_set_i2c_icstr_nack(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_NACK, v) +#define C66XX_get_i2c_icstr_al() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_AL) +#define C66XX_set_i2c_icstr_al(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSTR_RG_ADDR, I2C_ICSTR_AL, v) + + // direct bit set macros +#define C66XX_CLEAR_I2C_ICSTR_SDIR C66XX_set_i2c_icstr_sdir(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_NACKSNT C66XX_set_i2c_icstr_nacksnt(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_BB C66XX_set_i2c_icstr_bb(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_SCD C66XX_set_i2c_icstr_scd(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_ICXRDY C66XX_set_i2c_icstr_icxrdy(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_ICRDRDY C66XX_set_i2c_icstr_icrdrdy(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_ARDY C66XX_set_i2c_icstr_ardy(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_NACK C66XX_set_i2c_icstr_nack(C66XX_ON) +#define C66XX_CLEAR_I2C_ICSTR_AL C66XX_set_i2c_icstr_al(C66XX_ON) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_I2C_ICSTR_SDIR_IS_ON (C66XX_get_i2c_icstr_sdir() == C66XX_ON) +#define C66XX_I2C_ICSTR_NACKSNT_IS_ON (C66XX_get_i2c_icstr_nacksnt() == C66XX_ON) +#define C66XX_I2C_ICSTR_BB_IS_ON (C66XX_get_i2c_icstr_bb() == C66XX_ON) +#define C66XX_I2C_ICSTR_RSFULL_IS_ON (C66XX_get_i2c_icstr_rsfull() == C66XX_ON) +#define C66XX_I2C_ICSTR_XSMT_IS_ON (C66XX_get_i2c_icstr_xsmt() == C66XX_ON) +#define C66XX_I2C_ICSTR_AAS_IS_ON (C66XX_get_i2c_icstr_aas() == C66XX_ON) +#define C66XX_I2C_ICSTR_AD0_IS_ON (C66XX_get_i2c_icstr_ad0() == C66XX_ON) +#define C66XX_I2C_ICSTR_SCD_IS_ON (C66XX_get_i2c_icstr_scd() == C66XX_ON) +#define C66XX_I2C_ICSTR_ICXRDY_IS_ON (C66XX_get_i2c_icstr_icxrdy() == C66XX_ON) +#define C66XX_I2C_ICSTR_ICRDRDY_IS_ON (C66XX_get_i2c_icstr_icrdrdy() == C66XX_ON) +#define C66XX_I2C_ICSTR_ARDY_IS_ON (C66XX_get_i2c_icstr_ardy() == C66XX_ON) +#define C66XX_I2C_ICSTR_NACK_IS_ON (C66XX_get_i2c_icstr_nack() == C66XX_ON) +#define C66XX_I2C_ICSTR_AL_IS_ON (C66XX_get_i2c_icstr_al() == C66XX_ON) + + +//------------ I2C clock low-time divider register macros --------------------- +#define C66XX_get_i2c_icclkl_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICCLKL_RG_ADDR) +#define C66XX_set_i2c_icclkl_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICCLKL_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icclkl_iccl() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICCLKL_RG_ADDR, I2C_ICCLKL_ICCL) +#define C66XX_set_i2c_icclkl_iccl(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICCLKL_RG_ADDR, I2C_ICCLKL_ICCL, v) + + +//------------ I2C clock high-time divider register macros -------------------- +#define C66XX_get_i2c_icclkh_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICCLKH_RG_ADDR) +#define C66XX_set_i2c_icclkh_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICCLKH_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icclkh_icch() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICCLKH_RG_ADDR, I2C_ICCLKH_ICCH) +#define C66XX_set_i2c_icclkh_icch(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICCLKH_RG_ADDR, I2C_ICCLKH_ICCH, v) + + +//------------ I2C data count register macros --------------------------------- +#define C66XX_get_i2c_iccnt_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICCNT_RG_ADDR) +#define C66XX_set_i2c_iccnt_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICCNT_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_iccnt_icdc() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICCNT_RG_ADDR, I2C_ICCNT_ICDC) +#define C66XX_set_i2c_iccnt_icdc(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICCNT_RG_ADDR, I2C_ICCNT_ICDC, v) + + +//------------ I2C data receive register macros ------------------------------- +#define C66XX_get_i2c_icdrr_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICDRR_RG_ADDR) + + // dedicated bit specific macros +#define C66XX_get_i2c_icdrr_d() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICDRR_RG_ADDR, I2C_ICDRR_D) + + +//------------ I2C slave address register macros ------------------------------ +#define C66XX_get_i2c_icsar_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICSAR_RG_ADDR) +#define C66XX_set_i2c_icsar_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICSAR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icsar_saddr() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICSAR_RG_ADDR, I2C_ICSAR_SADDR) +#define C66XX_set_i2c_icsar_saddr(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICSAR_RG_ADDR, I2C_ICSAR_SADDR, v) + + +//------------ I2C data transmit register macros ------------------------------ +#define C66XX_get_i2c_icdxr_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICDXR_RG_ADDR) +#define C66XX_set_i2c_icdxr_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICDXR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icdxr_d() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICDXR_RG_ADDR, I2C_ICDXR_D) +#define C66XX_set_i2c_icdxr_d(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICDXR_RG_ADDR, I2C_ICDXR_D, v) + + +//------------ I2C mode register macros --------------------------------------- +#define C66XX_get_i2c_icmdr_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICMDR_RG_ADDR) +#define C66XX_set_i2c_icmdr_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICMDR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icmdr_nackmod() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_NACKMOD) +#define C66XX_set_i2c_icmdr_nackmod(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_NACKMOD, v) +#define C66XX_get_i2c_icmdr_free() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_FREE) +#define C66XX_set_i2c_icmdr_free(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_FREE, v) +#define C66XX_get_i2c_icmdr_stt() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STT) +#define C66XX_set_i2c_icmdr_stt(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STT, v) +#define C66XX_get_i2c_icmdr_stp() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STP) +#define C66XX_set_i2c_icmdr_stp(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STP, v) +#define C66XX_get_i2c_icmdr_mst() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_MST) +#define C66XX_set_i2c_icmdr_mst(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_MST, v) +#define C66XX_get_i2c_icmdr_trx() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_TRX) +#define C66XX_set_i2c_icmdr_trx(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_TRX, v) +#define C66XX_get_i2c_icmdr_xa() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_XA) +#define C66XX_set_i2c_icmdr_xa(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_XA, v) +#define C66XX_get_i2c_icmdr_rm() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_RM) +#define C66XX_set_i2c_icmdr_rm(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_RM, v) +#define C66XX_get_i2c_icmdr_dlb() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_DLB) +#define C66XX_set_i2c_icmdr_dlb(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_DLB, v) +#define C66XX_get_i2c_icmdr_irs() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_IRS) +#define C66XX_set_i2c_icmdr_irs(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_IRS, v) +#define C66XX_get_i2c_icmdr_stb() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STB) +#define C66XX_set_i2c_icmdr_stb(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_STB, v) +#define C66XX_get_i2c_icmdr_fdf() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_FDF) +#define C66XX_set_i2c_icmdr_fdf(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_FDF, v) +#define C66XX_get_i2c_icmdr_bc() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_BC) +#define C66XX_set_i2c_icmdr_bc(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICMDR_RG_ADDR, I2C_ICMDR_BC, v) + + // direct bit set macros +#define C66XX_SET_I2C_ICMDR_NACKMOD_ON C66XX_set_i2c_icmdr_nackmod(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_NACKMOD_OFF C66XX_set_i2c_icmdr_nackmod(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_FREE_ON C66XX_set_i2c_icmdr_free(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_FREE_OFF C66XX_set_i2c_icmdr_free(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_STT_ON C66XX_set_i2c_icmdr_stt(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_STT_OFF C66XX_set_i2c_icmdr_stt(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_STP_ON C66XX_set_i2c_icmdr_stp(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_STP_OFF C66XX_set_i2c_icmdr_stp(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_MST_ON C66XX_set_i2c_icmdr_mst(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_MST_OFF C66XX_set_i2c_icmdr_mst(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_TRX_ON C66XX_set_i2c_icmdr_trx(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_TRX_OFF C66XX_set_i2c_icmdr_trx(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_XA_OFF C66XX_set_i2c_icmdr_xa(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_XA_ON C66XX_set_i2c_icmdr_xa(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_RM_OFF C66XX_set_i2c_icmdr_rm(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_RM_ON C66XX_set_i2c_icmdr_rm(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_DLB_OFF C66XX_set_i2c_icmdr_dlb(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_DLB_ON C66XX_set_i2c_icmdr_dlb(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_IRS_OFF C66XX_set_i2c_icmdr_irs(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_IRS_ON C66XX_set_i2c_icmdr_irs(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_STB_OFF C66XX_set_i2c_icmdr_stb(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_STB_ON C66XX_set_i2c_icmdr_stb(C66XX_ON) +#define C66XX_SET_I2C_ICMDR_FDF_OFF C66XX_set_i2c_icmdr_fdf(C66XX_OFF) +#define C66XX_SET_I2C_ICMDR_FDF_ON C66XX_set_i2c_icmdr_fdf(C66XX_ON) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_I2C_ICMDR_NACKMOD_IS_ON (C66XX_get_i2c_icmdr_nackmod() == C66XX_ON) +#define C66XX_I2C_ICMDR_FREE_IS_ON (C66XX_get_i2c_icmdr_free() == C66XX_ON) +#define C66XX_I2C_ICMDR_STT_IS_ON (C66XX_get_i2c_icmdr_stt() == C66XX_ON) +#define C66XX_I2C_ICMDR_STP_IS_ON (C66XX_get_i2c_icmdr_stp() == C66XX_ON) +#define C66XX_I2C_ICMDR_MST_IS_ON (C66XX_get_i2c_icmdr_mst() == C66XX_ON) +#define C66XX_I2C_ICMDR_TRX_IS_ON (C66XX_get_i2c_icmdr_trx() == C66XX_ON) +#define C66XX_I2C_ICMDR_XA_IS_ON (C66XX_get_i2c_icmdr_xa() == C66XX_ON) +#define C66XX_I2C_ICMDR_RM_IS_ON (C66XX_get_i2c_icmdr_rm() == C66XX_ON) +#define C66XX_I2C_ICMDR_DLB_IS_ON (C66XX_get_i2c_icmdr_dlb() == C66XX_ON) +#define C66XX_I2C_ICMDR_IRS_IS_ON (C66XX_get_i2c_icmdr_irs() == C66XX_ON) +#define C66XX_I2C_ICMDR_STB_IS_ON (C66XX_get_i2c_icmdr_stb() == C66XX_ON) +#define C66XX_I2C_ICMDR_FDF_IS_ON (C66XX_get_i2c_icmdr_fdf() == C66XX_ON) + + +//------------ I2C interrupt vector register macros --------------------------- +#define C66XX_get_i2c_icivr_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICIVR_RG_ADDR) + + // dedicated bit specific macros +#define C66XX_get_i2c_icivr_intcode() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICIVR_RG_ADDR, I2C_ICIVR_INTCODE) + + +//------------ I2C extended mode register macros ------------------------------ +#define C66XX_get_i2c_icemdr_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICEMDR_RG_ADDR) +#define C66XX_set_i2c_icemdr_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icemdr_ignack() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, I2C_ICEMDR_IGNACK) +#define C66XX_set_i2c_icemdr_ignack(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, I2C_ICEMDR_IGNACK, v) +#define C66XX_get_i2c_icemdr_bcm() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, I2C_ICEMDR_BCM) +#define C66XX_set_i2c_icemdr_bcm(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICEMDR_RG_ADDR, I2C_ICEMDR_BCM, v) + + // direct bit set macros +#define C66XX_SET_I2C_ICEMDR_IGNACK_ON C66XX_set_i2c_icemdr_ignack(C66XX_ON) +#define C66XX_SET_I2C_ICEMDR_IGNACK_OFF C66XX_set_i2c_icemdr_ignack(C66XX_OFF) +#define C66XX_SET_I2C_ICEMDR_BCM_ON C66XX_set_i2c_icemdr_bcm(C66XX_ON) +#define C66XX_SET_I2C_ICEMDR_BCM_OFF C66XX_set_i2c_icemdr_bcm(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_I2C_ICEMDR_IGNACK_IS_ON (C66XX_get_i2c_icemdr_ignack() == C66XX_ON) +#define C66XX_I2C_ICEMDR_BCM_IS_ON (C66XX_get_i2c_icemdr_bcm() == C66XX_ON) + + +//------------ I2C prescaler register macros ---------------------------------- +#define C66XX_get_i2c_icpsc_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICPSC_RG_ADDR) +#define C66XX_set_i2c_icpsc_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICPSC_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icpsc_ipsc() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICPSC_RG_ADDR, I2C_ICPSC_IPSC) +#define C66XX_set_i2c_icpsc_ipsc(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICPSC_RG_ADDR, I2C_ICPSC_IPSC, v) + + +//------------ I2C peripheral identification 1 register macros ---------------- +#define C66XX_get_i2c_icpid1_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICPID1_RG_ADDR) +#define C66XX_set_i2c_icpid1_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICPID1_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icpid1_class() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICPID1_RG_ADDR, I2C_ICPID1_CLASS) +#define C66XX_set_i2c_icpid1_class(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICPID1_RG_ADDR, I2C_ICPID1_CLASS, v) +#define C66XX_get_i2c_icpid1_revision() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICPID1_RG_ADDR, I2C_ICPID1_REVISION) +#define C66XX_set_i2c_icpid1_revision(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICPID1_RG_ADDR, I2C_ICPID1_REVISION, v) + + +//------------ I2C peripheral identification 2 register macros ---------------- +#define C66XX_get_i2c_icpid2_rg() C66XX_GET_RG_VALUE(C66XX_I2C_ICPID2_RG_ADDR) +#define C66XX_set_i2c_icpid2_rg(v) C66XX_SET_RG_VALUE(C66XX_I2C_ICPID2_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_i2c_icpid2_type() C66XX_GET_FIELD_VALUE(C66XX_I2C_ICPID2_RG_ADDR, I2C_ICPID2_TYPE) +#define C66XX_set_i2c_icpid2_type(v) C66XX_SET_FIELD_VALUE(C66XX_I2C_ICPID2_RG_ADDR, I2C_ICPID2_TYPE, v) +//============================================================================= + + + +//============================================================================= +//============ EMIF16 configuration macros ==================================== +//============================================================================= + +//------------ Revision code and status register macros ----------------------- +#define C66XX_get_emif16_rcsr_rg() C66XX_GET_RG_VALUE(C66XX_EMIF16_RCSR_RG_ADDR) + + // dedicated bit specific macros +#define C66XX_get_emif16_rcsr_be() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_RCSR_RG_ADDR, EMIF16_RCSR_BE) +#define C66XX_get_emif16_rcsr_mod_id() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_RCSR_RG_ADDR, EMIF16_RCSR_MOD_ID) +#define C66XX_get_emif16_rcsr_mj_rev() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_RCSR_RG_ADDR, EMIF16_RCSR_MJ_REV) +#define C66XX_get_emif16_rcsr_min_rev() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_RCSR_RG_ADDR, EMIF16_RCSR_MIN_REV) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_EMIF16_RCSR_BE_IS_ON (C66XX_get_emif16_rcsr_be() == C66XX_ON) +#define C66XX_EMIF16_RCSR_MOD_ID_IS_DEFAULT_VALUE (C66XX_get_emif16_rcsr_mod_id() == C66XX_EMIF16_RCSR_MOD_ID_DEFAULT_VALUE) +#define C66XX_EMIF16_RCSR_MJ_REV_IS_DEFAULT_VALUE (C66XX_get_emif16_rcsr_mj_rev() == C66XX_EMIF16_RCSR_MJ_REV_DEFAULT_VALUE) +#define C66XX_EMIF16_RCSR_MIN_REV_IS_DEFAULT_VALUE (C66XX_get_emif16_rcsr_min_rev() == C66XX_EMIF16_RCSR_MIN_REV_DEFAULT_VALUE) + + +//------------ Async wait cycle config register macros ------------------------ +#define C66XX_get_emif16_awccr_rg() C66XX_GET_RG_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR) +#define C66XX_set_emif16_awccr_rg(v) C66XX_SET_RG_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_emif16_awccr_wp1() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_WP1) +#define C66XX_set_emif16_awccr_wp1(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_WP1, v) +#define C66XX_get_emif16_awccr_wp0() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_WP0) +#define C66XX_set_emif16_awccr_wp0(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_WP0, v) +#define C66XX_get_emif16_awccr_cs5_wait() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS5_WAIT) +#define C66XX_set_emif16_awccr_cs5_wait(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS5_WAIT, v) +#define C66XX_get_emif16_awccr_cs4_wait() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS4_WAIT) +#define C66XX_set_emif16_awccr_cs4_wait(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS4_WAIT, v) +#define C66XX_get_emif16_awccr_cs3_wait() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS3_WAIT) +#define C66XX_set_emif16_awccr_cs3_wait(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS3_WAIT, v) +#define C66XX_get_emif16_awccr_cs2_wait() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS2_WAIT) +#define C66XX_set_emif16_awccr_cs2_wait(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_CS2_WAIT, v) +#define C66XX_get_emif16_awccr_max_ext_wait() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_MAX_EXT_WAIT) +#define C66XX_set_emif16_awccr_max_ext_wait(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_AWCCR_RG_ADDR, EMIF16_AWCCR_MAX_EXT_WAIT, v) + + // direct bit set macros +#define C66XX_SET_EMIF16_AWCCR_WP1_ON C66XX_set_emif16_awccr_wp1(C66XX_ON) +#define C66XX_SET_EMIF16_AWCCR_WP1_OFF C66XX_set_emif16_awccr_wp1(C66XX_OFF) +#define C66XX_SET_EMIF16_AWCCR_WP0_ON C66XX_set_emif16_awccr_wp0(C66XX_ON) +#define C66XX_SET_EMIF16_AWCCR_WP0_OFF C66XX_set_emif16_awccr_wp0(C66XX_OFF) +#define C66XX_SET_EMIF16_AWCCR_CS5_WAIT1 C66XX_set_emif16_awccr_cs5_wait(C66XX_ON) +#define C66XX_SET_EMIF16_AWCCR_CS5_WAIT0 C66XX_set_emif16_awccr_cs5_wait(C66XX_OFF) +#define C66XX_SET_EMIF16_AWCCR_CS4_WAIT1 C66XX_set_emif16_awccr_cs4_wait(C66XX_ON) +#define C66XX_SET_EMIF16_AWCCR_CS4_WAIT0 C66XX_set_emif16_awccr_cs4_wait(C66XX_OFF) +#define C66XX_SET_EMIF16_AWCCR_CS3_WAIT1 C66XX_set_emif16_awccr_cs3_wait(C66XX_ON) +#define C66XX_SET_EMIF16_AWCCR_CS3_WAIT0 C66XX_set_emif16_awccr_cs3_wait(C66XX_OFF) +#define C66XX_SET_EMIF16_AWCCR_CS2_WAIT1 C66XX_set_emif16_awccr_cs2_wait(C66XX_ON) +#define C66XX_SET_EMIF16_AWCCR_CS2_WAIT0 C66XX_set_emif16_awccr_cs2_wait(C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_EMIF16_AWCCR_WP1_IS_ON (C66XX_get_emif16_awccr_wp1() == C66XX_ON) +#define C66XX_EMIF16_AWCCR_WP0_IS_ON (C66XX_get_emif16_awccr_wp0() == C66XX_ON) +#define C66XX_EMIF16_AWCCR_CS5_WAIT_IS_WAIT1 (C66XX_get_emif16_awccr_cs5_wait() == C66XX_ON) +#define C66XX_EMIF16_AWCCR_CS4_WAIT_IS_WAIT1 (C66XX_get_emif16_awccr_cs4_wait() == C66XX_ON) +#define C66XX_EMIF16_AWCCR_CS3_WAIT_IS_WAIT1 (C66XX_get_emif16_awccr_cs3_wait() == C66XX_ON) +#define C66XX_EMIF16_AWCCR_CS2_WAIT_IS_WAIT1 (C66XX_get_emif16_awccr_cs2_wait() == C66XX_ON) + + +//------------ Async config registers macros ---------------------------------- +// i index corresonds to Async config registers number +#define C66XX_get_emif16_acr_rg_addr(i) (C66XX_EMIF16_A1CR_RG_ADDR + i * 0x4) +#define C66XX_get_emif16_acr_rg(i) C66XX_GET_RG_VALUE(C66XX_get_emif16_acr_rg_addr(i)) +#define C66XX_set_emif16_acr_rg(i,v) C66XX_SET_RG_VALUE(C66XX_get_emif16_acr_rg_addr(i), v) + + // dedicated bit specific macros +#define C66XX_get_emif16_acr_ss(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_SS) +#define C66XX_set_emif16_acr_ss(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_SS, v) +#define C66XX_get_emif16_acr_ew(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_EW) +#define C66XX_set_emif16_acr_ew(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_EW, v) +#define C66XX_get_emif16_acr_w_setup(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_SETUP) +#define C66XX_set_emif16_acr_w_setup(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_SETUP, v) +#define C66XX_get_emif16_acr_w_strobe(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_STROBE) +#define C66XX_set_emif16_acr_w_strobe(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_STROBE, v) +#define C66XX_get_emif16_acr_w_hold(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_HOLD) +#define C66XX_set_emif16_acr_w_hold(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_W_HOLD, v) +#define C66XX_get_emif16_acr_r_setup(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_SETUP) +#define C66XX_set_emif16_acr_r_setup(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_SETUP, v) +#define C66XX_get_emif16_acr_r_strobe(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_STROBE) +#define C66XX_set_emif16_acr_r_strobe(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_STROBE, v) +#define C66XX_get_emif16_acr_r_hold(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_HOLD) +#define C66XX_set_emif16_acr_r_hold(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_R_HOLD, v) +#define C66XX_get_emif16_acr_ta(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_TA) +#define C66XX_set_emif16_acr_ta(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_TA, v) +#define C66XX_get_emif16_acr_asize(i) C66XX_GET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_ASIZE) +#define C66XX_set_emif16_acr_asize(i,v) C66XX_SET_FIELD_VALUE(C66XX_get_emif16_acr_rg_addr(i), EMIF16_A1CR_ASIZE, v) + + // direct bit set macros +#define C66XX_SET_EMIF16_ACR_SS_ON(i) C66XX_set_emif16_acr_ss(i, C66XX_ON) +#define C66XX_SET_EMIF16_ACR_SS_OFF(i) C66XX_set_emif16_acr_ss(i, C66XX_OFF) +#define C66XX_SET_EMIF16_ACR_EW_ON(i) C66XX_set_emif16_acr_ew(i, C66XX_ON) +#define C66XX_SET_EMIF16_ACR_EW_OFF(i) C66XX_set_emif16_acr_ew(i, C66XX_OFF) +#define C66XX_SET_EMIF16_ACR_ASIZE_16BIT(i) C66XX_set_emif16_acr_asize(i, C66XX_EMIF16_A1CR_ASIZE_16BIT) +#define C66XX_SET_EMIF16_ACR_ASIZE_8BIT(i) C66XX_set_emif16_acr_asize(i, C66XX_EMIF16_A1CR_ASIZE_8BIT) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_EMIF16_ACR_SS_IS_ON(i) (C66XX_get_emif16_acr_ss(i) == C66XX_ON) +#define C66XX_EMIF16_ACR_EW_IS_ON(i) (C66XX_get_emif16_acr_ew(i) == C66XX_ON) +#define C66XX_EMIF16_ACR_ASIZE_IS_16BIT(i) (C66XX_get_emif16_acr_asize(i) == C66XX_EMIF16_A1CR_ASIZE_16BIT) + + +//------------ Interrupt raw register macros ---------------------------------- +#define C66XX_get_emif16_irr_rg() C66XX_GET_RG_VALUE(C66XX_EMIF16_IRR_RG_ADDR) +#define C66XX_set_emif16_irr_rg(v) C66XX_SET_RG_VALUE(C66XX_EMIF16_IRR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_emif16_irr_wr() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IRR_RG_ADDR, EMIF16_IRR_WR) +#define C66XX_set_emif16_irr_wr(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IRR_RG_ADDR, EMIF16_IRR_WR, v) +#define C66XX_get_emif16_irr_at() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IRR_RG_ADDR, EMIF16_IRR_AT) +#define C66XX_set_emif16_irr_at(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IRR_RG_ADDR, EMIF16_IRR_AT, v) + + // direct bit set macros +#define C66XX_CLEAR_EMIF16_IRR_AT C66XX_set_emif16_irr_at(C66XX_ON) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_EMIF16_IRR_AT_IS_ON (C66XX_get_emif16_irr_at() == C66XX_ON) + + +//------------ Interrupt masked register macros ------------------------------- +#define C66XX_get_emif16_imr_rg() C66XX_GET_RG_VALUE(C66XX_EMIF16_IMR_RG_ADDR) +#define C66XX_set_emif16_imr_rg(v) C66XX_SET_RG_VALUE(C66XX_EMIF16_IMR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_emif16_imr_wr_masked() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMR_RG_ADDR, EMIF16_IMR_WR_MASKED) +#define C66XX_set_emif16_imr_wr_masked(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMR_RG_ADDR, EMIF16_IMR_WR_MASKED, v) +#define C66XX_get_emif16_imr_at_masked() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMR_RG_ADDR, EMIF16_IMR_AT_MASKED) +#define C66XX_set_emif16_imr_at_masked(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMR_RG_ADDR, EMIF16_IMR_AT_MASKED, v) + + // direct bit set macros +#define C66XX_CLEAR_EMIF16_IMR_AT_MASKED C66XX_set_emif16_imr_at_masked(C66XX_ON) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_EMIF16_IMR_AT_MASKED_IS_ON (C66XX_get_emif16_imr_at_masked() == C66XX_ON) + + +//------------ Interrupt mask set register macros ----------------------------- +#define C66XX_get_emif16_imsr_rg() C66XX_GET_RG_VALUE(C66XX_EMIF16_IMSR_RG_ADDR) +#define C66XX_set_emif16_imsr_rg(v) C66XX_SET_RG_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_emif16_imsr_wr_mask_set() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, EMIF16_IMSR_WR_MASK_SET) +#define C66XX_set_emif16_imsr_wr_mask_set(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, EMIF16_IMSR_WR_MASK_SET, v) +#define C66XX_get_emif16_imsr_at_mask_set() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, EMIF16_IMSR_AT_MASK_SET) +#define C66XX_set_emif16_imsr_at_mask_set(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMSR_RG_ADDR, EMIF16_IMSR_AT_MASK_SET, v) + + // direct bit set macros +#define C66XX_SET_EMIF16_IMSR_AT_MASK_SET_ON C66XX_set_emif16_imsr_at_mask_set(C66XX_ON) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_EMIF16_IMSR_AT_MASK_SET_IS_ON (C66XX_get_emif16_imsr_at_mask_set() == C66XX_ON) + + +//------------ Interrupt mask clear register macros ----------------------------- +#define C66XX_get_emif16_imcr_rg() C66XX_GET_RG_VALUE(C66XX_EMIF16_IMCR_RG_ADDR) +#define C66XX_set_emif16_imcr_rg(v) C66XX_SET_RG_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, v) + + // dedicated bit specific macros +#define C66XX_get_emif16_imcr_wr_mask_clr() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, EMIF16_IMCR_WR_MASK_CLR) +#define C66XX_set_emif16_imcr_wr_mask_clr(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, EMIF16_IMCR_WR_MASK_CLR, v) +#define C66XX_get_emif16_imcr_at_mask_clr() C66XX_GET_FIELD_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, EMIF16_IMCR_AT_MASK_CLR) +#define C66XX_set_emif16_imcr_at_mask_clr(v) C66XX_SET_FIELD_VALUE(C66XX_EMIF16_IMCR_RG_ADDR, EMIF16_IMCR_AT_MASK_CLR, v) + + // direct bit set macros +#define C66XX_SET_EMIF16_IMCR_AT_MASK_CLR_ON C66XX_set_emif16_imcr_at_mask_clr(C66XX_ON) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_EMIF16_IMCR_AT_MASK_CLR_IS_ON (C66XX_get_emif16_imcr_at_mask_clr() == C66XX_ON) +//============================================================================= + + + +//============================================================================= +//============ Timer registers macros ========================================= +//============================================================================= + +//------------ Emulation Management and Clock Speed register macros ----------- +#define C66XX_get_timer_emumgt_clkspd_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_EMUMGT_CLKSPD_RG_ADDR(timer)) + + // dedicated bit specific macros +#define C66XX_get_timer_emumgt_clkspd_clkdiv(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_EMUMGT_CLKSPD_RG_ADDR(timer), TIMER_EMUMGT_CLKSPD_CLKDIV) + + +//------------ Counter register low register macros --------------------------- +#define C66XX_get_timer_cntlo_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_CNTLO_RG_ADDR(timer)) +#define C66XX_set_timer_cntlo_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_CNTLO_RG_ADDR(timer), v) + + +//------------ Counter register high register macros -------------------------- +#define C66XX_get_timer_cnthi_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_CNTHI_RG_ADDR(timer)) +#define C66XX_set_timer_cnthi_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_CNTHI_RG_ADDR(timer), v) + + +//------------ Period register low register macros ---------------------------- +#define C66XX_get_timer_prdlo_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_PRDLO_RG_ADDR(timer)) +#define C66XX_set_timer_prdlo_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_PRDLO_RG_ADDR(timer), v) + + +//------------ Period register high register macros --------------------------- +#define C66XX_get_timer_prdhi_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_PRDHI_RG_ADDR(timer)) +#define C66XX_set_timer_prdhi_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_PRDHI_RG_ADDR(timer), v) + + +//------------ Timer control register macros ---------------------------------- +#define C66XX_get_timer_tcr_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer)) +#define C66XX_set_timer_tcr_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), v) + + // dedicated bit specific macros +#define C66XX_get_timer_tcr_readrstmode_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_READRSTMODE_HI) +#define C66XX_set_timer_tcr_readrstmode_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_READRSTMODE_HI, v) +#define C66XX_get_timer_tcr_enamode_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_ENAMODE_HI) +#define C66XX_set_timer_tcr_enamode_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_ENAMODE_HI, v) +#define C66XX_get_timer_tcr_pwid_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_PWID_HI) +#define C66XX_set_timer_tcr_pwid_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_PWID_HI, v) +#define C66XX_get_timer_tcr_cp_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CP_HI) +#define C66XX_set_timer_tcr_cp_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CP_HI, v) +#define C66XX_get_timer_tcr_invoutp_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVOUTP_HI) +#define C66XX_set_timer_tcr_invoutp_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVOUTP_HI, v) +#define C66XX_get_timer_tcr_tstat_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_TSTAT_HI) +#define C66XX_get_timer_tcr_capevtmode_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CAPEVTMODE_LO) +#define C66XX_set_timer_tcr_capevtmode_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CAPEVTMODE_LO, v) +#define C66XX_get_timer_tcr_capmode_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CAPMODE_LO) +#define C66XX_set_timer_tcr_capmode_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CAPMODE_LO, v) +#define C66XX_get_timer_tcr_readrstmode_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_READRSTMODE_LO) +#define C66XX_set_timer_tcr_readrstmode_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_READRSTMODE_LO, v) +#define C66XX_get_timer_tcr_tien_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_TIEN_LO) +#define C66XX_set_timer_tcr_tien_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_TIEN_LO, v) +#define C66XX_get_timer_tcr_clksrc_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CLKSRC_LO) +#define C66XX_set_timer_tcr_clksrc_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CLKSRC_LO, v) +#define C66XX_get_timer_tcr_enamode_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_ENAMODE_LO) +#define C66XX_set_timer_tcr_enamode_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_ENAMODE_LO, v) +#define C66XX_get_timer_tcr_pwid_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_PWID_LO) +#define C66XX_set_timer_tcr_pwid_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_PWID_LO, v) +#define C66XX_get_timer_tcr_cp_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CP_LO) +#define C66XX_set_timer_tcr_cp_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_CP_LO, v) +#define C66XX_get_timer_tcr_invinp_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVINP_LO) +#define C66XX_set_timer_tcr_invinp_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVINP_LO, v) +#define C66XX_get_timer_tcr_invoutp_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVOUTP_LO) +#define C66XX_set_timer_tcr_invoutp_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_INVOUTP_LO, v) +#define C66XX_get_timer_tcr_tstat_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TCR_RG_ADDR(timer), TIMER_TCR_TSTAT_LO) + + // direct bit set macros +#define C66XX_SET_TIMER_TCR_READRSTMODE_HI_ON(timer) C66XX_set_timer_tcr_readrstmode_hi(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_READRSTMODE_HI_OFF(timer) C66XX_set_timer_tcr_readrstmode_hi(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_ENAMODE_HI_DISABLED(timer) C66XX_set_timer_tcr_enamode_hi(timer, C66XX_TIMER_TCR_ENAMODE_DISABLED) +#define C66XX_SET_TIMER_TCR_ENAMODE_HI_ONE_SHOT(timer) C66XX_set_timer_tcr_enamode_hi(timer, C66XX_TIMER_TCR_ENAMODE_ONE_SHOT) +#define C66XX_SET_TIMER_TCR_ENAMODE_HI_CONT(timer) C66XX_set_timer_tcr_enamode_hi(timer, C66XX_TIMER_TCR_ENAMODE_CONT) +#define C66XX_SET_TIMER_TCR_ENAMODE_HI_CONT_RELOAD(timer) C66XX_set_timer_tcr_enamode_hi(timer, C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD) +#define C66XX_SET_TIMER_TCR_PWID_HI_1_CLK(timer) C66XX_set_timer_tcr_pwid_hi(timer, C66XX_TIMER_TCR_PWID_1_CLK) +#define C66XX_SET_TIMER_TCR_PWID_HI_2_CLK(timer) C66XX_set_timer_tcr_pwid_hi(timer, C66XX_TIMER_TCR_PWID_2_CLK) +#define C66XX_SET_TIMER_TCR_PWID_HI_3_CLK(timer) C66XX_set_timer_tcr_pwid_hi(timer, C66XX_TIMER_TCR_PWID_3_CLK) +#define C66XX_SET_TIMER_TCR_PWID_HI_4_CLK(timer) C66XX_set_timer_tcr_pwid_hi(timer, C66XX_TIMER_TCR_PWID_4_CLK) +#define C66XX_SET_TIMER_TCR_CP_HI_ON(timer) C66XX_set_timer_tcr_cp_hi(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_CP_HI_OFF(timer) C66XX_set_timer_tcr_cp_hi(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_INVOUTP_HI_ON(timer) C66XX_set_timer_tcr_invoutp_hi(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_INVOUTP_HI_OFF(timer) C66XX_set_timer_tcr_invoutp_hi(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_CAPEVTMODE_LO_RISING_EDGE(timer) C66XX_set_timer_tcr_capevtmode_lo(timer, C66XX_TIMER_TCR_CAPEVTMODE_RISING_EDGE) +#define C66XX_SET_TIMER_TCR_CAPEVTMODE_LO_FALLING_EDGE(timer) C66XX_set_timer_tcr_capevtmode_lo(timer, C66XX_TIMER_TCR_CAPEVTMODE_FALLING_EDGE) +#define C66XX_SET_TIMER_TCR_CAPEVTMODE_LO_ANY_EDGE(timer) C66XX_set_timer_tcr_capevtmode_lo(timer, C66XX_TIMER_TCR_CAPEVTMODE_ANY_EDGE) +#define C66XX_SET_TIMER_TCR_CAPMODE_LO_ON(timer) C66XX_set_timer_tcr_capmode_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_CAPMODE_LO_OFF(timer) C66XX_set_timer_tcr_capmode_lo(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_READRSTMODE_LO_ON(timer) C66XX_set_timer_tcr_readrstmode_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_READRSTMODE_LO_OFF(timer) C66XX_set_timer_tcr_readrstmode_lo(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_TIEN_LO_ON(timer) C66XX_set_timer_tcr_tien_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_TIEN_LO_OFF(timer) C66XX_set_timer_tcr_tien_lo(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_CLKSRC_LO_ON(timer) C66XX_set_timer_tcr_clksrc_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_CLKSRC_LO_OFF(timer) C66XX_set_timer_tcr_clksrc_lo(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_ENAMODE_LO_DISABLED(timer) C66XX_set_timer_tcr_enamode_lo(timer, C66XX_TIMER_TCR_ENAMODE_DISABLED) +#define C66XX_SET_TIMER_TCR_ENAMODE_LO_ONE_SHOT(timer) C66XX_set_timer_tcr_enamode_lo(timer, C66XX_TIMER_TCR_ENAMODE_ONE_SHOT) +#define C66XX_SET_TIMER_TCR_ENAMODE_LO_CONT(timer) C66XX_set_timer_tcr_enamode_lo(timer, C66XX_TIMER_TCR_ENAMODE_CONT) +#define C66XX_SET_TIMER_TCR_ENAMODE_LO_CONT_RELOAD(timer) C66XX_set_timer_tcr_enamode_lo(timer, C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD) +#define C66XX_SET_TIMER_TCR_PWID_LO_1_CLK(timer) C66XX_set_timer_tcr_pwid_lo(timer, C66XX_TIMER_TCR_PWID_1_CLK) +#define C66XX_SET_TIMER_TCR_PWID_LO_2_CLK(timer) C66XX_set_timer_tcr_pwid_lo(timer, C66XX_TIMER_TCR_PWID_2_CLK) +#define C66XX_SET_TIMER_TCR_PWID_LO_3_CLK(timer) C66XX_set_timer_tcr_pwid_lo(timer, C66XX_TIMER_TCR_PWID_3_CLK) +#define C66XX_SET_TIMER_TCR_PWID_LO_4_CLK(timer) C66XX_set_timer_tcr_pwid_lo(timer, C66XX_TIMER_TCR_PWID_4_CLK) +#define C66XX_SET_TIMER_TCR_CP_LO_ON(timer) C66XX_set_timer_tcr_cp_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_CP_LO_OFF(timer) C66XX_set_timer_tcr_cp_lo(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_INVINP_LO_ON(timer) C66XX_set_timer_tcr_invinp_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_INVINP_LO_OFF(timer) C66XX_set_timer_tcr_invinp_lo(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TCR_INVOUTP_LO_ON(timer) C66XX_set_timer_tcr_invoutp_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_TCR_INVOUTP_LO_OFF(timer) C66XX_set_timer_tcr_invoutp_lo(timer, C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_TIMER_TCR_READRSTMODE_HI_IS_ON(timer) (C66XX_get_timer_tcr_readrstmode_hi(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_ENAMODE_HI_IS_DISABLED(timer) (C66XX_get_timer_tcr_enamode_hi(timer) == C66XX_TIMER_TCR_ENAMODE_DISABLED) +#define C66XX_TIMER_TCR_ENAMODE_HI_IS_ONE_SHOT(timer) (C66XX_get_timer_tcr_enamode_hi(timer) == C66XX_TIMER_TCR_ENAMODE_ONE_SHOT) +#define C66XX_TIMER_TCR_ENAMODE_HI_IS_CONT(timer) (C66XX_get_timer_tcr_enamode_hi(timer) == C66XX_TIMER_TCR_ENAMODE_CONT) +#define C66XX_TIMER_TCR_ENAMODE_HI_IS_CONT_RELOAD(timer) (C66XX_get_timer_tcr_enamode_hi(timer) == C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD) +#define C66XX_TIMER_TCR_PWI_HI_IS_1_CLK(timer) (C66XX_get_timer_tcr_pwid_hi(timer) == C66XX_TIMER_TCR_PWID_1_CLK) +#define C66XX_TIMER_TCR_PWI_HI_IS_2_CLK(timer) (C66XX_get_timer_tcr_pwid_hi(timer) == C66XX_TIMER_TCR_PWID_2_CLK) +#define C66XX_TIMER_TCR_PWI_HI_IS_3_CLK(timer) (C66XX_get_timer_tcr_pwid_hi(timer) == C66XX_TIMER_TCR_PWID_3_CLK) +#define C66XX_TIMER_TCR_PWI_HI_IS_4_CLK(timer) (C66XX_get_timer_tcr_pwid_hi(timer) == C66XX_TIMER_TCR_PWID_4_CLK) +#define C66XX_TIMER_TCR_CP_HI_IS_ON(timer) (C66XX_get_timer_tcr_cp_hi(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_INVOUTP_HI_IS_ON(timer) (C66XX_get_timer_tcr_invoutp_hi(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_TSTAT_HI_IS_ON(timer) (C66XX_get_timer_tcr_tstat_hi(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_CAPEVTMODE_LO_IS_RISING_EDGE(timer) (C66XX_get_timer_tcr_capevtmode_lo(timer) == C66XX_TIMER_TCR_CAPEVTMODE_RISING_EDGE) +#define C66XX_TIMER_TCR_CAPEVTMODE_LO_IS_FALLING_EDGE(timer) (C66XX_get_timer_tcr_capevtmode_lo(timer) == C66XX_TIMER_TCR_CAPEVTMODE_FALLING_EDGE) +#define C66XX_TIMER_TCR_CAPEVTMODE_LO_IS_ANY_EDGE(timer) (C66XX_get_timer_tcr_capevtmode_lo(timer) == C66XX_TIMER_TCR_CAPEVTMODE_ANY_EDGE) +#define C66XX_TIMER_TCR_CAPMODE_LO_IS_ON(timer) (C66XX_get_timer_tcr_capmode_lo(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_READRSTMODE_LO_IS_ON(timer) (C66XX_get_timer_tcr_readrstmode_lo(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_TIEN_LO_IS_ON(timer) (C66XX_get_timer_tcr_tien_lo(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_CLKSRC_LO_IS_ON(timer) (C66XX_get_timer_tcr_clksrc_lo(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_ENAMODE_LO_IS_DISABLED(timer) (C66XX_get_timer_tcr_enamode_lo(timer) == C66XX_TIMER_TCR_ENAMODE_DISABLED) +#define C66XX_TIMER_TCR_ENAMODE_LO_IS_ONE_SHOT(timer) (C66XX_get_timer_tcr_enamode_lo(timer) == C66XX_TIMER_TCR_ENAMODE_ONE_SHOT) +#define C66XX_TIMER_TCR_ENAMODE_LO_IS_CONT(timer) (C66XX_get_timer_tcr_enamode_lo(timer) == C66XX_TIMER_TCR_ENAMODE_CONT) +#define C66XX_TIMER_TCR_ENAMODE_LO_IS_CONT_RELOAD(timer) (C66XX_get_timer_tcr_enamode_lo(timer) == C66XX_TIMER_TCR_ENAMODE_CONT_RELOAD) +#define C66XX_TIMER_TCR_PWI_LO_IS_1_CLK(timer) (C66XX_get_timer_tcr_pwid_lo(timer) == C66XX_TIMER_TCR_PWID_1_CLK) +#define C66XX_TIMER_TCR_PWI_LO_IS_2_CLK(timer) (C66XX_get_timer_tcr_pwid_lo(timer) == C66XX_TIMER_TCR_PWID_2_CLK) +#define C66XX_TIMER_TCR_PWI_LO_IS_3_CLK(timer) (C66XX_get_timer_tcr_pwid_lo(timer) == C66XX_TIMER_TCR_PWID_3_CLK) +#define C66XX_TIMER_TCR_PWI_LO_IS_4_CLK(timer) (C66XX_get_timer_tcr_pwid_lo(timer) == C66XX_TIMER_TCR_PWID_4_CLK) +#define C66XX_TIMER_TCR_CP_LO_IS_ON(timer) (C66XX_get_timer_tcr_cp_lo(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_INVINP_LO_IS_ON(timer) (C66XX_get_timer_tcr_invinp_lo(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_INVOUTP_LO_IS_ON(timer) (C66XX_get_timer_tcr_invoutp_lo(timer) == C66XX_ON) +#define C66XX_TIMER_TCR_TSTAT_LO_IS_ON(timer) (C66XX_get_timer_tcr_tstat_lo(timer) == C66XX_ON) + + +//------------ Timer global control register macros --------------------------- +#define C66XX_get_timer_tgcr_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer)) +#define C66XX_set_timer_tgcr_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), v) + + // dedicated bit specific macros +#define C66XX_get_timer_tgcr_tddrhi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TDDRHI) +#define C66XX_set_timer_tgcr_tddrhi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TDDRHI, v) +#define C66XX_get_timer_tgcr_pschi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_PSCHI) +#define C66XX_set_timer_tgcr_pschi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_PSCHI, v) +#define C66XX_get_timer_tgcr_plusen(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_PLUSEN) +#define C66XX_set_timer_tgcr_plusen(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_PLUSEN, v) +#define C66XX_get_timer_tgcr_timmode(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMMODE) +#define C66XX_set_timer_tgcr_timmode(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMMODE, v) +#define C66XX_get_timer_tgcr_timhirs(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMHIRS) +#define C66XX_set_timer_tgcr_timhirs(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMHIRS, v) +#define C66XX_get_timer_tgcr_timlors(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMLORS) +#define C66XX_set_timer_tgcr_timlors(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_TGCR_RG_ADDR(timer), TIMER_TGCR_TIMLORS, v) + + // direct bit set macros +#define C66XX_SET_TIMER_TGCR_PLUSEN_ON(timer) C66XX_set_timer_tgcr_plusen(timer, C66XX_ON) +#define C66XX_SET_TIMER_TGCR_PLUSEN_OFF(timer) C66XX_set_timer_tgcr_plusen(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TGCR_TIMMODE_64BIT_GPT(timer) C66XX_set_timer_tgcr_timmode(timer, C66XX_TIMER_TGCR_TIMMODE_64BIT_GPT) +#define C66XX_SET_TIMER_TGCR_TIMMODE_32BIT_UNCHAINED(timer) C66XX_set_timer_tgcr_timmode(timer, C66XX_TIMER_TGCR_TIMMODE_32BIT_UNCHAINED) +#define C66XX_SET_TIMER_TGCR_TIMMODE_64BIT_WDT(timer) C66XX_set_timer_tgcr_timmode(timer, C66XX_TIMER_TGCR_TIMMODE_64BIT_WDT) +#define C66XX_SET_TIMER_TGCR_TIMMODE_32BIT_CHAINED(timer) C66XX_set_timer_tgcr_timmode(timer, C66XX_TIMER_TGCR_TIMMODE_32BIT_CHAINED) +#define C66XX_SET_TIMER_TGCR_TIMHIRS_ON(timer) C66XX_set_timer_tgcr_timhirs(timer, C66XX_ON) +#define C66XX_SET_TIMER_TGCR_TIMHIRS_OFF(timer) C66XX_set_timer_tgcr_timhirs(timer, C66XX_OFF) +#define C66XX_SET_TIMER_TGCR_TIMLORS_ON(timer) C66XX_set_timer_tgcr_timlors(timer, C66XX_ON) +#define C66XX_SET_TIMER_TGCR_TIMLORS_OFF(timer) C66XX_set_timer_tgcr_timlors(timer, C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_TIMER_TGCR_PLUSEN_IS_ON(timer) (C66XX_get_timer_tgcr_plusen(timer) == C66XX_ON) +#define C66XX_TIMER_TGCR_TIMMODE_IS_64BIT_GPT(timer) (C66XX_get_timer_tgcr_timmode(timer) == C66XX_TIMER_TGCR_TIMMODE_64BIT_GPT) +#define C66XX_TIMER_TGCR_TIMMODE_IS_32BIT_UNCHAINED(timer) (C66XX_get_timer_tgcr_timmode(timer) == C66XX_TIMER_TGCR_TIMMODE_32BIT_UNCHAINED) +#define C66XX_TIMER_TGCR_TIMMODE_IS_64BIT_WDT(timer) (C66XX_get_timer_tgcr_timmode(timer) == C66XX_TIMER_TGCR_TIMMODE_64BIT_WDT) +#define C66XX_TIMER_TGCR_TIMMODE_IS_32BIT_CHAINED(timer) (C66XX_get_timer_tgcr_timmode(timer) == C66XX_TIMER_TGCR_TIMMODE_32BIT_CHAINED) +#define C66XX_TIMER_TGCR_TIMHIRS_IS_ON(timer) (C66XX_get_timer_tgcr_timhirs(timer) == C66XX_ON) +#define C66XX_TIMER_TGCR_TIMLORS_IS_ON(timer) (C66XX_get_timer_tgcr_timlors(timer) == C66XX_ON) + + +//------------ Watchdog Timer Control Register macros ------------------------- +#define C66XX_get_timer_wdtcr_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer)) +#define C66XX_set_timer_wdtcr_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), v) + + // dedicated bit specific macros +#define C66XX_get_timer_wdtcr_wdkey(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDKEY) +#define C66XX_set_timer_wdtcr_wdkey(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDKEY, v) +#define C66XX_get_timer_wdtcr_wdflag(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDFLAG) +#define C66XX_set_timer_wdtcr_wdflag(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDFLAG, v) +#define C66XX_get_timer_wdtcr_wden(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDEN) +#define C66XX_set_timer_wdtcr_wden(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_WDTCR_RG_ADDR(timer), TIMER_WDTCR_WDEN, v) + + // direct bit set macros +#define C66XX_SET_TIMER_WDTCR_WDKEY_FIRST_KEY(timer) C66XX_set_timer_wdtcr_wdkey(timer, C66XX_TIMER_WDTCR_WDKEY_FIRST_KEY) +#define C66XX_SET_TIMER_WDTCR_WDKEY_SECOND_KEY(timer) C66XX_set_timer_wdtcr_wdkey(timer, C66XX_TIMER_WDTCR_WDKEY_SECOND_KEY) +#define C66XX_SET_TIMER_WDTCR_WDFLAG_ON(timer) C66XX_set_timer_wdtcr_wdflag(timer, C66XX_ON) +#define C66XX_SET_TIMER_WDTCR_WDFLAG_OFF(timer) C66XX_set_timer_wdtcr_wdflag(timer, C66XX_OFF) +#define C66XX_SET_TIMER_WDTCR_WDEN_ON(timer) C66XX_set_timer_wdtcr_wden(timer, C66XX_ON) +#define C66XX_SET_TIMER_WDTCR_WDEN_OFF(timer) C66XX_set_timer_wdtcr_wden(timer, C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_TIMER_WDTCR_WDFLAG_IS_ON(timer) (C66XX_get_timer_wdtcr_wdflag(timer) == C66XX_ON) +#define C66XX_TIMER_WDTCR_WDEN_IS_ON(timer) (C66XX_get_timer_wdtcr_wden(timer) == C66XX_ON) + + +//------------ Timer Reload register low register macros ---------------------- +#define C66XX_get_timer_rello_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_RELLO_RG_ADDR(timer)) +#define C66XX_set_timer_rello_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_RELLO_RG_ADDR(timer), v) + + +//------------ Timer Reload register high register macros --------------------- +#define C66XX_get_timer_relhi_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_RELHI_RG_ADDR(timer)) +#define C66XX_set_timer_relhi_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_RELHI_RG_ADDR(timer), v) + + +//------------ Timer Capture register low register macros --------------------- +#define C66XX_get_timer_caplo_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_CAPLO_RG_ADDR(timer)) +#define C66XX_set_timer_caplo_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_CAPLO_RG_ADDR(timer), v) + + +//------------ Timer Capture register high register macros -------------------- +#define C66XX_get_timer_caphi_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_CAPHI_RG_ADDR(timer)) +#define C66XX_set_timer_caphi_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_CAPHI_RG_ADDR(timer), v) + + +//------------ Timer interrupt control and status register macros ------------- +#define C66XX_get_timer_intctlstat_rg(timer) C66XX_GET_RG_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer)) +#define C66XX_set_timer_intctlstat_rg(timer,v) C66XX_SET_RG_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), v) + + // dedicated bit specific macros +#define C66XX_get_timer_intctlstat_evtintstat_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTSTAT_HI) +#define C66XX_set_timer_intctlstat_evtintstat_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTSTAT_HI, v) +#define C66XX_get_timer_intctlstat_evtinten_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTEN_HI) +#define C66XX_set_timer_intctlstat_evtinten_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTEN_HI, v) +#define C66XX_get_timer_intctlstat_prdintstat_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTSTAT_HI) +#define C66XX_set_timer_intctlstat_prdintstat_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTSTAT_HI, v) +#define C66XX_get_timer_intctlstat_prdinten_hi(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTEN_HI) +#define C66XX_set_timer_intctlstat_prdinten_hi(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTEN_HI, v) +#define C66XX_get_timer_intctlstat_evtintstat_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTSTAT_LO) +#define C66XX_set_timer_intctlstat_evtintstat_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTSTAT_LO, v) +#define C66XX_get_timer_intctlstat_evtinten_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTEN_LO) +#define C66XX_set_timer_intctlstat_evtinten_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_EVTINTEN_LO, v) +#define C66XX_get_timer_intctlstat_prdintstat_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTSTAT_LO) +#define C66XX_set_timer_intctlstat_prdintstat_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTSTAT_LO, v) +#define C66XX_get_timer_intctlstat_prdinten_lo(timer) C66XX_GET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTEN_LO) +#define C66XX_set_timer_intctlstat_prdinten_lo(timer,v) C66XX_SET_FIELD_VALUE(C66XX_TIMER_INTCTLSTAT_RG_ADDR(timer), TIMER_INTCTLSTAT_PRDINTEN_LO, v) + + // direct bit set macros +#define C66XX_CLEAR_TIMER_INTCTLSTAT_EVTINTSTAT_HI(timer) C66XX_set_timer_intctlstat_evtintstat_hi(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_EVTINTEN_HI_ON(timer) C66XX_set_timer_intctlstat_evtinten_hi(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_EVTINTEN_HI_OFF(timer) C66XX_set_timer_intctlstat_evtinten_hi(timer, C66XX_OFF) +#define C66XX_CLEAR_TIMER_INTCTLSTAT_PRDINTSTAT_HI(timer) C66XX_set_timer_intctlstat_prdintstat_hi(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_PRDINTEN_HI_ON(timer) C66XX_set_timer_intctlstat_prdinten_hi(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_PRDINTEN_HI_OFF(timer) C66XX_set_timer_intctlstat_prdinten_hi(timer, C66XX_OFF) +#define C66XX_CLEAR_TIMER_INTCTLSTAT_EVTINTSTAT_LO(timer) C66XX_set_timer_intctlstat_evtintstat_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_EVTINTEN_LO_ON(timer) C66XX_set_timer_intctlstat_evtinten_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_EVTINTEN_LO_OFF(timer) C66XX_set_timer_intctlstat_evtinten_lo(timer, C66XX_OFF) +#define C66XX_CLEAR_TIMER_INTCTLSTAT_PRDINTSTAT_LO(timer) C66XX_set_timer_intctlstat_prdintstat_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_PRDINTEN_LO_ON(timer) C66XX_set_timer_intctlstat_prdinten_lo(timer, C66XX_ON) +#define C66XX_SET_TIMER_INTCTLSTAT_PRDINTEN_LO_OFF(timer) C66XX_set_timer_intctlstat_prdinten_lo(timer, C66XX_OFF) + + // condition check macros (for use in IF() and other conditional operators) +#define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_HI_IS_ON(timer) (C66XX_get_timer_intctlstat_evtintstat_hi(timer) == C66XX_ON) +#define C66XX_TIMER_INTCTLSTAT_EVTINTEN_HI_IS_ON(timer) (C66XX_get_timer_intctlstat_evtinten_hi(timer) == C66XX_ON) +#define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_HI_IS_ON(timer) (C66XX_get_timer_intctlstat_prdintstat_hi(timer) == C66XX_ON) +#define C66XX_TIMER_INTCTLSTAT_PRDINTEN_HI_IS_ON(timer) (C66XX_get_timer_intctlstat_prdinten_hi(timer) == C66XX_ON) +#define C66XX_TIMER_INTCTLSTAT_EVTINTSTAT_LO_IS_ON(timer) (C66XX_get_timer_intctlstat_evtintstat_lo(timer) == C66XX_ON) +#define C66XX_TIMER_INTCTLSTAT_EVTINTEN_LO_IS_ON(timer) (C66XX_get_timer_intctlstat_evtinten_lo(timer) == C66XX_ON) +#define C66XX_TIMER_INTCTLSTAT_PRDINTSTAT_LO_IS_ON(timer) (C66XX_get_timer_intctlstat_prdintstat_lo(timer) == C66XX_ON) +#define C66XX_TIMER_INTCTLSTAT_PRDINTEN_LO_IS_ON(timer) (C66XX_get_timer_intctlstat_prdinten_lo(timer) == C66XX_ON) + +//============================================================================= + + + +//============================================================================= +#endif /* __C66XX_MACROS_HXX__ */ diff --git a/ports/c667x/ccs/example_build/include/TA66XX_DSP.h b/ports/c667x/ccs/example_build/include/TA66XX_DSP.h new file mode 100644 index 00000000..04dfc4b7 --- /dev/null +++ b/ports/c667x/ccs/example_build/include/TA66XX_DSP.h @@ -0,0 +1,251 @@ +/****************************************************************************** + TORNADO AMC modules Software Development Kit (SDK). Rev 4A. + General definitions and API functions. + (C) MicroLAB Systems, 2015-2017 + + + http://www.mlabsys.com + ftp://ftp.mlabsys.com + email: techsupport@mlabsys.com + + + Description: + ------------ + This file contains general definitions and API functions for TORNADO AMC + modules SDK and must be included in the user C-application for + TORNADO AMC modules. + + + Revision history: + ----------------- + rev.2A - 2015, initial release for TORNADO-A6678 board rev.1B; + rev.3A - 2016: + - added support for TORNADO-A6678/FMC board rev.1A; + rev.3B - 2017: + - added support for TORNADO-A6678/FMC board rev.1B; + rev.4A - 2017: + - added support for TORNADO-AZ/FMC board rev.1A; + + + Notes: + ------ + 1. This C-header file is an include file for TI C6xxx C/C++ Code + Generation Tools, which must be invoked to compile for C66xx DSP + platform. + + 2. This file is best viewed with the TAB setting set to '4'. + + + Copyright: + ---------- + This utility is supplied free of charge as it is without any obligation + from MicroLAB Systems. No responsibility is assumed for any use or misuse + of these utilities. + +******************************************************************************/ + + +/** + * @file TA66XX_DSP.h + * + * @brief Main include file + * + * This file contains general definitions and API functions for TORNADO + * AMC modules SDK + * + */ + + +#ifndef __TA66XX_DSP_H__ // check for this file has been already included +#define __TA66XX_DSP_H__ 1 + + +// General defs +#define TA66XX_ON 1 +#define TA66XX_OFF 0 + + +// Include C66xx DSP defs, macros and aux functions +#include "C66XX.h" +// Include TORNADO AMC SDK functions errors +#include "TASDK_ERR.h" + + + +//============================================================================= +/** TORNADO AMC SDK revision ID */ +#define TA66XX_SDK_REVISION_ID "4A" +//============================================================================= + + + +//============================================================================= +//============ TORNADO AMC SDK API functions ID defs ========================== +//============================================================================= +/** @addtogroup TA66XX_FUNCTIONS_ID SDK API functions ID defs + * @{ + */ + + +/**< Function name max size */ +#define TA66XX_FUNCTION_NAME_LEN_MAX 64 + + +enum +{ + TA66XX_GET_ERROR_MESSAGE_FUNCTION_ID = 0, + TA66XX_GET_FUNCTION_NAME_FUNCTION_ID, + TA66XX_BC_SET_I2C_INTERRUPT_NUMBER_FUNCTION_ID, + TA66XX_BC_SET_UART_INTERRUPT_NUMBER_FUNCTION_ID, + TA66XX_BC_INIT_FUNCTION_ID, + TA66XX_BC_MAP_DSP_GPIO_INTERRUPT_FUNCTION_ID, + TA66XX_BC_UNMAP_DSP_GPIO_INTERRUPT_FUNCTION_ID, + TA66XX_BC_INIT_UART_FUNCTION_ID, + TA66XX_BC_WRITE_EEPROM_FUNCTION_ID, + TA66XX_BC_READ_EEPROM_FUNCTION_ID, + TA66XX_BC_ERASE_EEPROM_FUNCTION_ID, + TA66XX_BC_GET_DEVICE_INFO_FUNCTION_ID, + TA66XX_BC_GET_HW_CFG_INFO_FUNCTION_ID, + TA66XX_BC_GET_FMC_INFO_FUNCTION_ID, + TA66XX_BC_GET_TEMP_STATE_FUNCTION_ID, + TA66XX_BC_GET_POWER_STATE_FUNCTION_ID, + TA66XX_BC_GET_FMC_POWER_STATE_FUNCTION_ID, + TA66XX_BC_GET_SFP_INFO_FUNCTION_ID, + TA66XX_BC_SET_FPGA_HIF_CONFIG_FUNCTION_ID, + TA66XX_BC_GET_FPGA_HIF_CONFIG_FUNCTION_ID, + TA66XX_BC_CLEAR_FPGA_CNF_FUNCTION_ID, + TA66XX_BC_LOAD_FPGA_CNF_FUNCTION_ID, + TA66XX_BC_GET_GBE_PORT_INFO_FUNCTION_ID, + TA66XX_BC_INIT_GBE_PORT_FUNCTION_ID, + TA66XX_BC_ERASE_FLASH_FUNCTION_ID, + TA66XX_BC_WRITE_FLASH_FUNCTION_ID, + TA66XX_BC_READ_FLASH_FUNCTION_ID, + TA66XX_SC_INIT_FLASH_RECORD_LIST_FUNCTION_ID, + TA66XX_SC_GET_NUMBER_OF_FLASH_RECORDS_FUNCTION_ID, + TA66XX_SC_GET_FLASH_RECORD_LIST_FUNCTION_ID, + TA66XX_SC_GET_FLASH_RECORD_INFO_FUNCTION_ID, + TA66XX_SC_READ_FLASH_RECORD_DATA_FUNCTION_ID, + TA66XX_SC_CREATE_FLASH_RECORD_FUNCTION_ID, + TA66XX_SC_WRITE_FLASH_RECORD_DATA_FUNCTION_ID, + TA66XX_SC_XCLOSE_FLASH_RECORD_FUNCTION_ID, + TA66XX_SC_UPDATE_FLASH_RECORD_FUNCTION_ID, + TA66XX_SC_DELETE_FLASH_RECORD_FUNCTION_ID, + TA66XX_SC_SQUEEZE_FLASH_RECORDS_FUNCTION_ID, + TA66XX_SC_GET_FLASH_FREE_SPACE_FUNCTION_ID, + TA66XX_SC_GET_BOOT_SEQ_FUNCTION_ID, + TA66XX_SC_DELETE_BOOT_SEQ_FUNCTION_ID, + TA66XX_SC_SET_BOOT_SEQ_FUNCTION_ID, + TA66XX_SC_LOAD_DSP_APPL_FROM_MEMORY_FUNCTION_ID, + TA66XX_SC_LOAD_DSP_APPL_FROM_FLASH_RECORD_FUNCTION_ID, + TA66XX_SC_LOAD_FPGA_CNF_FROM_FLASH_RECORD_FUNCTION_ID, + TA66XX_NUMBER_OF_FUNCTIONS +}; +/** @}*/ +//============================================================================= + + + +#ifdef __cplusplus +extern "C" { +#endif + + + +//============================================================================= +//============ General SDK API functions declarations ========================= +//============================================================================= + +/** @addtogroup TA66XX_GENERAL TORNADO AMC SDK general API functions + * @{ + */ + +/*------------ TA66XX_set_error() function -------------------------------*//** + * @brief Function should be used on exit from SDK API functions in + * order to set error code and function ID of SDK API functions + * + * @param[in] err - error code; + * @param[in] function_id - function ID of SDK API functions; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_set_error(int32_t err, int32_t function_id); + + +/*------------ TA66XX_get_last_error() function --------------------------*//** + * @brief Function returns error code of last executed API function + * + * @return Error code of last executed API function + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_get_last_error(void); + + +/*------------ TA66XX_get_error_flag() function --------------------------*//** + * @brief Function returns status of ERROR_FLAG for API functions + * + * ERROR_FLAG is set by each API function in case error has been detected. + * ERROR_FLAG can be reset by TA66XX_clear_error_flag() API function + * + * @param[out] error_code - pointer to a variable to receive the error code in + * case error has been detected. In case pointer is NULL, then + * no error code is returned; + * @param[out] error_function_id - pointer to a variable to receive ID of the + * first API function, which has returned with error. In case + * pointer is NULL, then no function ID is returned; + * + * @return Status of ERROR_FLAG: ON or OFF + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_get_error_flag(int32_t *error_code, int32_t *error_function_id); + + +/*------------ TA66XX_clear_error_flag() function ------------------------*//** + * @brief Function clear ERROR_FLAG for API functions + * + * @return Always OK + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_clear_error_flag(void); + + +/*------------ TA66XX_get_error_message() function -----------------------*//** + * @brief Function returns the text interpretation of the error code. + * + * @param[in] error - error code to be interpreted; + * @param[out] error_message - pointer to the returned string. In case pointer + * is NULL, then no text is filled in; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_get_error_message(int32_t error, char *error_message); + + +/*------------ TA66XX_get_function_name() function -----------------------*//** + * @brief Function returns the text interpretation of API function. + * + * @param[in] function_id - ID of the API function to be interpreted; + * @param[out] function_name - pointer to the returned string. In case pointer + * is NULL, then no text is filled in; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_get_function_name(int32_t function_id, char *function_name); + + +/** @}*/ +//============================================================================= + + + +#ifdef __cplusplus +} +#endif + + + +//============================================================================= +#endif /* __TA66XX_DSP_H__ */ + diff --git a/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC.h b/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC.h new file mode 100644 index 00000000..dbc748e0 --- /dev/null +++ b/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC.h @@ -0,0 +1,121 @@ +/****************************************************************************** + TORNADO AMC modules Software Development Kit (SDK). Rev 4A. + Definitions, macros and API functions for DSP Environment. + (C) MicroLAB Systems, 2014-2017 + + + http://www.mlabsys.com + ftp://ftp.mlabsys.com + email: techsupport@mlabsys.com + + + Description: + ------------ + This file contains definitions, macros and API functions for TORNADO AMC + modules on-board DSP environment and must be included in the user + C-application for TORNADO AMC modules. + + + Revision history: + ----------------- + rev.1A - 2014, initial release for TORNADO-A6678 board rev.1A. + rev.1B - 2015, fixed some bugs. + rev.1C - 2015, added support for TORNADO-A6678 board rev.1B: + - updated DSP external control registers area; + - updated TA66XX_init_dsp() DSP initialization + function; + - added MMC-to-DSP communication functions in DSP + I2C functions. + rev.2A - 2015, totally redesigned SDK for TORNADO-A6678 board rev.1B; + rev.3A - 2016, added support for TORNADO-A6678/FMC board rev.1A; + rev.3B - 2017: + - added support for TORNADO-A6678/FMC board rev.1B; + rev.4A - 2017: + - added support for TORNADO-AZ/FMC board rev.1A; + + + Notes: + ------ + 1. This C-header file is an include file for TI C6xxx C/C++ Code + Generation Tools, which must be invoked to compile for C66xx DSP + platform. + + 2. This file is best viewed with the TAB setting set to '4'. + + 3. This library uses dynamic memory allocation in erase FLASH functions, + so user should provide enough memory area for dynamic memory allocation + (-heap parameter) and place the section (.sysmem) in the corresponding + memory area in linker command file. + The max requested memory allocation block length is up to FLASH memory + sector length in bytes (128 KB). + + 4. This header file is externally controlled from user C-code by run-time + compiler keys definitions in order to apply board-type specific + definitions to refer to particular definitions included for different + board type: + + __TA66XX_BC_USE_BIOS__ + - if defined in user code prior inclusion of this header file, + then TI SYS/BIOS modules(HWI (Hardware Interrupt) and ECM + (Event Combiner Manager)), will be used to support + C66xx CorePac interrupt controller (INTC). + TI INTC Chip Support Library (CSL) should be used in case + NO embedded operating system is used in user application. + DEFAULT is NOT DEFINED, so CSL INTC library will be used + to support C66xx CorePac interrupt controller. + + Copyright: + ---------- + This utility is supplied free of charge as it is without any obligation + from MicroLAB Systems. No responsibility is assumed for any use or misuse + of these utilities. + +******************************************************************************/ + + +/** + * @file TA66XX_DSP_BC.h + * + * @brief Main include file + * + * This file contains definitions, macros and API functions for TORNADO + * AMC modules on-board DSP environment + * + */ + + +#ifndef __TA66XX_DSP_BC_H__ // check for this file has been already included +#define __TA66XX_DSP_BC_H__ 1 + + +#if defined __TA66XX_BC_USE_BIOS__ +// Include this file to prevent compiler errors +// when using SYS/BIOS +#include +#endif /* __TA66XX_BC_USE_BIOS__ */ + + +// Include general TORNADO AMC SDK defs +#include "TA66XX_DSP.h" + + +//============================================================================= +//------------ board-type specific run-time compiler keys processing ---------- +// (this is required in order to exclude key confusions) + +// Default setting is C6678 DSP definitions +#define __C66XX_SELECT_C6678_DSP__ 1 + +// Finally we must define C-code data type for accessing I/O areas +typedef volatile uint16_t __TA66XX_BC_DSP_XCR_RG_DATA_TYPE__; +typedef volatile uint16_t __TA66XX_BC_FLASH_DATA_TYPE__; +//============================================================================= + + +// Include TORNADO AMC SDK functions +#include "TA66XX_DSP_BC_FUNCTIONS.hxx" + + +//============================================================================= +#endif /* __TA66XX_DSP_BC_H__ */ + diff --git a/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC_FUNCTIONS.hxx b/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC_FUNCTIONS.hxx new file mode 100644 index 00000000..338a01ee --- /dev/null +++ b/ports/c667x/ccs/example_build/include/TA66XX_DSP_BC_FUNCTIONS.hxx @@ -0,0 +1,1732 @@ +/****************************************************************************** + TORNADO AMC modules Software Development Kit (SDK). Rev 3B. + (C) MicroLAB Systems, 2014-2017 + + File: TORNADO AMC SDK functions for DSP environment declarations + ----- + + Notes: + ------ + 1. This C-header file contains TORNADO AMC modules SDK functions + for DSP environment declarations and is an include file for + TI C6xxx C/C++ Code Generation Tools, which must be invoked to compile + for TORNADO AMC platform. + + 2. This file is best viewed with the TAB setting set to '4'. + +******************************************************************************/ + + +/** + * @file TA66XX_DSP_BC_FUNCTIONS.hxx + * + * @brief Board control (BC) SDK functions declarations + * + * This file contains declarations of TORNADO AMC modules SDK functions for + * board control + * + */ + + +#ifndef __TA66XX_DSP_BC_FUNCTIONS_HXX__ // check for this file has been already included +#define __TA66XX_DSP_BC_FUNCTIONS_HXX__ 1 + + + +#ifdef __cplusplus +extern "C" { +#endif + + + +//============================================================================= +//============ DSP environment functions ====================================== +//============================================================================= + +/** @addtogroup TA66XX_BC_INIT TORNADO AMC DSP environment init functions + * @{ + */ + + +/** Default DSP interrupt vector for DSP I2C interrupt */ +#define TA66XX_BC_I2C_INTERRUPT_NUMBER_USED 4 + + +/*------------ TA66XX_BC_set_i2c_interrupt_number() function -------------*//** + * @brief Function should be called before calling TA66XX_BC_init() function + * and is used to select DSP interrupt vector number for DSP I2C interrupt. + * + * @param[in] dsp_vector_id - DSP interrupt vector number, which will be used + * for DSP I2C interrupt. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_set_i2c_interrupt_number(uint32_t dsp_vector_id); + + +/*------------ TA66XX_BC_get_i2c_interrupt_number() function -------------*//** + * @brief Function returns current DSP interrupt vector number for DSP I2C + * interrupt. + * + * @return DSP interrupt vector number, which is used for DSP I2C interrupt. + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_i2c_interrupt_number(void); + + +/** Default DSP interrupt vector for DSP UART interrupt */ +#define TA66XX_BC_UART_INTERRUPT_NUMBER_USED 5 + + +/*------------ TA66XX_BC_set_uart_interrupt_number() function ------------*//** + * @brief Function should be called before calling TA66XX_BC_init() function + * and is used to select DSP interrupt vector number for DSP UART interrupt. + * + * @param[in] dsp_vector_id - DSP interrupt vector number, which will be used + * for DSP UART interrupt. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_set_uart_interrupt_number(uint32_t dsp_vector_id); + + +/*------------ TA66XX_BC_get_uart_interrupt_number() function ------------*//** + * @brief Function returns current DSP interrupt vector number for DSP UART + * interrupt. + * + * @return DSP interrupt vector number, which is used for DSP UART interrupt. + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_uart_interrupt_number(void); + + +/*------------ TA66XX_BC_init() function ---------------------------------*//** + * @brief Function performs initialization of TORNADO AMC modules + * DSP environment in accordance with board type + * + * The function does the following: + * 1. DSP on-chip caches are configured by default: L1P and L1D caches are + * enabled and set to max available size, L2 cache is disabled so L2 memory + * acts as SRAM. + * 2. DSP main PLL, DDR3 PLL and PASS PLL are configured by default: DSP core + * clock is set to TA66XX_BC_DSP_CORE_SPEED_VALUE, DDR3 and PASS controllers + * to default values + * 3. DDR3 memory is configured and ready to use + * 4. All DSP power domains are enabled + * 5. DSP EMIF-16 bus is configured. + * 6. In case external 1GE interface is installed then DSP SGMII port is + * initialized. + * 7. DSP GPIO pins are configured as outputs and cleared. + * 8. DSP LEDs are enabled. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_init(void); + + +/*------------ TA66XX_BC_get_ddr_area_base_addr() function ---------------*//** + * @brief Function returns DDR3 area base address + * + * @return DDR3 area base address + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_ddr_area_base_addr(void); + + +/*------------ TA66XX_BC_get_ddr_area_length() function ------------------*//** + * @brief Function returns DDR3 area length in bytes + * + * @return DDR3 area length in bytes + * +-----------------------------------------------------------------------------*/ +uint64_t TA66XX_BC_get_ddr_area_length(void); + + +//----------------------------------------------------------------------------- +// These functions are used to map either lower 2 GB DDR3 page or high 2 GB +// DDR3 page of 4GB DDR3 memory area to DSP 32-bit logical memory map. + +/** The lower 2GB DDR3 memory page */ +#define TA66XX_BC_DDR3_MEM_PAGE0 0 +/** The high 2GB DDR3 memory page */ +#define TA66XX_BC_DDR3_MEM_PAGE1 1 +//----------------------------------------------------------------------------- + +/*------------ TA66XX_BC_set_ddr_area_page() function --------------------*//** + * @brief Function sets the specified 2 GB DDR3 memory page (0 or 1) to be + * mapped to DSP 32-bit logical memory map. + * + * This function should be used only in case of 4 GB and more DDR3 memory is + * installed otherwise it does nothing. + * + * @param[in] page - 2 GB DDR3 memory page (0 or 1); + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_set_ddr_area_page(uint32_t page); + + +/*------------ TA66XX_BC_get_ddr_area_page() function --------------------*//** + * @brief Function returns current selected 2 GB DDR3 memory page (0 or 1) + * which is mapped to DSP 32-bit logical memory map. + * + * @return Current selected 2 GB DDR3 memory page (0 or 1) + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_ddr_area_page(void); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ DSP LED functions ============================================== +//============================================================================= + +/** @addtogroup TA66XX_BC_DSP_LED TORNADO AMC DSP LED functions + * @{ + */ + +/** DSP LED definitions */ +enum TA66XX_BC_DSP_LEDS +{ + TA66XX_BC_DSP_LED0 = 0, /**< DSP LED-0 */ + TA66XX_BC_DSP_LED1, /**< DSP LED-1 */ + TA66XX_BC_DSP_LED2, /**< DSP LED-2 */ + TA66XX_BC_DSP_LED3, /**< DSP LED-3 */ + TA66XX_BC_DSP_LED4, /**< DSP LED-4 */ + TA66XX_BC_DSP_LED5, /**< DSP LED-5 */ + TA66XX_BC_DSP_LED6, /**< DSP LED-6 */ + TA66XX_BC_DSP_LED7 /**< DSP LED-7 */ +}; + +/** DSP LED bitmask definitions */ +enum TA66XX_BC_DSP_LED_BITMASKS +{ + TA66XX_BC_DSP_LED0_BITMASK = 0x0001, /**< DSP LED-0 bitmask */ + TA66XX_BC_DSP_LED1_BITMASK = 0x0002, /**< DSP LED-1 bitmask */ + TA66XX_BC_DSP_LED2_BITMASK = 0x0004, /**< DSP LED-2 bitmask */ + TA66XX_BC_DSP_LED3_BITMASK = 0x0008, /**< DSP LED-3 bitmask */ + TA66XX_BC_DSP_LED4_BITMASK = 0x0010, /**< DSP LED-4 bitmask */ + TA66XX_BC_DSP_LED5_BITMASK = 0x0020, /**< DSP LED-5 bitmask */ + TA66XX_BC_DSP_LED6_BITMASK = 0x0040, /**< DSP LED-6 bitmask */ + TA66XX_BC_DSP_LED7_BITMASK = 0x0080, /**< DSP LED-7 bitmask */ + TA66XX_BC_DSP_LEDS_BITMASK = 0x00ff /**< DSP LEDs bitmask */ +}; + +// Definitions for DSP LEDs used for TORNADO-A6678/FMC rev.1A and later boards +/** DSP LED GREEN-0 */ +#define TA66XX_BC_DSP_LED_GREEN0 TA66XX_BC_DSP_LED0 +#define TA66XX_BC_DSP_LED_GREEN0_BITMASK TA66XX_BC_DSP_LED0_BITMASK +/** DSP LED RED-0 */ +#define TA66XX_BC_DSP_LED_RED0 TA66XX_BC_DSP_LED1 +#define TA66XX_BC_DSP_LED_RED0_BITMASK TA66XX_BC_DSP_LED1_BITMASK +/** DSP LED GREEN-1 */ +#define TA66XX_BC_DSP_LED_GREEN1 TA66XX_BC_DSP_LED2 +#define TA66XX_BC_DSP_LED_GREEN1_BITMASK TA66XX_BC_DSP_LED2_BITMASK +/** DSP LED RED-1 */ +#define TA66XX_BC_DSP_LED_RED1 TA66XX_BC_DSP_LED3 +#define TA66XX_BC_DSP_LED_RED1_BITMASK TA66XX_BC_DSP_LED3_BITMASK +/** DSP LED GREEN-2 */ +#define TA66XX_BC_DSP_LED_GREEN2 TA66XX_BC_DSP_LED4 +#define TA66XX_BC_DSP_LED_GREEN2_BITMASK TA66XX_BC_DSP_LED4_BITMASK +/** DSP LED YELLOW-0 */ +#define TA66XX_BC_DSP_LED_YELLOW0 TA66XX_BC_DSP_LED5 +#define TA66XX_BC_DSP_LED_YELLOW0_BITMASK TA66XX_BC_DSP_LED5_BITMASK +/** DSP LED YELLOW-1 */ +#define TA66XX_BC_DSP_LED_YELLOW1 TA66XX_BC_DSP_LED6 +#define TA66XX_BC_DSP_LED_YELLOW1_BITMASK TA66XX_BC_DSP_LED6_BITMASK +/** DSP LED RED-2 */ +#define TA66XX_BC_DSP_LED_RED2 TA66XX_BC_DSP_LED7 +#define TA66XX_BC_DSP_LED_RED2_BITMASK TA66XX_BC_DSP_LED7_BITMASK + +/** DSP LED aliases for compatibility with TORNADO-A6678 rev.1B-1 board definitions */ +#define TA66XX_BC_DSP_LED_RED TA66XX_BC_DSP_LED_RED0 +#define TA66XX_BC_DSP_LED_AMBER TA66XX_BC_DSP_LED_YELLOW0 +#define TA66XX_BC_DSP_LED_BLUE TA66XX_BC_DSP_LED_GREEN2 +#define TA66XX_BC_DSP_LED_WHITE TA66XX_BC_DSP_LED_RED2 + + +// Aliases for DSP LEDs used for TORNADO-A6678 rev.1B-1 board +/** DSP LED GREEN-0 */ +#define TA6678_REV1B_BC_DSP_LED_GREEN0 TA66XX_BC_DSP_LED0 +#define TA6678_REV1B_BC_DSP_LED_GREEN0_BITMASK TA66XX_BC_DSP_LED0_BITMASK +/** DSP LED GREEN-1 */ +#define TA6678_REV1B_BC_DSP_LED_GREEN1 TA66XX_BC_DSP_LED1 +#define TA6678_REV1B_BC_DSP_LED_GREEN1_BITMASK TA66XX_BC_DSP_LED1_BITMASK +/** DSP LED YELLOW-0 */ +#define TA6678_REV1B_BC_DSP_LED_YELLOW0 TA66XX_BC_DSP_LED2 +#define TA6678_REV1B_BC_DSP_LED_YELLOW0_BITMASK TA66XX_BC_DSP_LED2_BITMASK +/** DSP LED YELLOW-1 */ +#define TA6678_REV1B_BC_DSP_LED_YELLOW1 TA66XX_BC_DSP_LED3 +#define TA6678_REV1B_BC_DSP_LED_YELLOW1_BITMASK TA66XX_BC_DSP_LED3_BITMASK +/** DSP LED AMBER */ +#define TA6678_REV1B_BC_DSP_LED_AMBER TA66XX_BC_DSP_LED4 +#define TA6678_REV1B_BC_DSP_LED_AMBER_BITMASK TA66XX_BC_DSP_LED4_BITMASK +/** DSP LED RED */ +#define TA6678_REV1B_BC_DSP_LED_RED TA66XX_BC_DSP_LED5 +#define TA6678_REV1B_BC_DSP_LED_RED_BITMASK TA66XX_BC_DSP_LED5_BITMASK +/** DSP LED BLUE */ +#define TA6678_REV1B_BC_DSP_LED_BLUE TA66XX_BC_DSP_LED6 +#define TA6678_REV1B_BC_DSP_LED_BLUE_BITMASK TA66XX_BC_DSP_LED6_BITMASK +/** DSP LED WHITE */ +#define TA6678_REV1B_BC_DSP_LED_WHITE TA66XX_BC_DSP_LED7 +#define TA6678_REV1B_BC_DSP_LED_WHITE_BITMASK TA66XX_BC_DSP_LED7_BITMASK + + + +/*------------ TA66XX_BC_set_dsp_leds_enable() function ------------------*//** + * @brief Function enables or disables on-board DSP LEDs + * + * @param[in] state - DSP LEDs enable state: TA66XX_ON or TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_leds_enable(uint32_t enable); + + +/*------------ TA66XX_BC_get_dsp_leds_enable_status() function -----------*//** + * @brief Function returns enable status of on-board DSP LEDs + * + * @return DSP LEDs enable state: TA66XX_ON or TA66XX_OFF + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_leds_enable_status(void); + + +/*------------ TA66XX_BC_set_dsp_led_state() function --------------------*//** + * @brief Function sets selected DSP LED to the desired state: ON or OFF + * + * @param[in] led_number - DSP LED number definition; + * @param[in] state - DSP LED state: TA66XX_ON or TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_led_state(uint32_t led_number, uint32_t state); + + +/*------------ TA66XX_BC_get_dsp_led_state() function --------------------*//** + * @brief Function returns selected DSP LED state: ON or OFF + * + * @param[in] led_number - DSP LED number definition; + * + * @return DSP LED state: TA66XX_ON or TA66XX_OFF + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_led_state(uint32_t led_number); + + +/*------------ TA66XX_BC_set_dsp_leds() function -------------------------*//** + * @brief Function sets selected DSP LEDs to the desired state: ON or OFF + * + * @param[in] led_bitmask - DSP LEDs (ORed) bitmask; + * @param[in] state - DSP LEDs state: TA66XX_ON or TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_leds(uint32_t led_bitmask, uint32_t state); + + +/*------------ TA66XX_BC_get_dsp_leds() function -------------------------*//** + * @brief Function returns selected DSP LEDs state: ON or OFF + * + * @param[in] led_bitmask - DSP LEDs (ORed) bitmask; + * + * @return DSP LEDs state + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_leds(uint32_t led_bitmask); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ DSP-to-FPGA GPIO functions ===================================== +//============================================================================= + +/** @addtogroup TA66XX_BC_DSP_FPGA_GPIO TORNADO AMC DSP-to-FPGA GPIO functions + * @{ + */ + +/** DSP-to-FPGA GPIO pins definitions */ +enum TA66XX_BC_DSP_FPGA_GPIO +{ + TA66XX_BC_DSP_FPGA_GPIO0 = 0, /**< DSP-to-FPGA GPIO pin 0 */ + TA66XX_BC_DSP_FPGA_GPIO1, /**< DSP-to-FPGA GPIO pin 1 */ + TA66XX_BC_DSP_FPGA_GPIO2, /**< DSP-to-FPGA GPIO pin 2 */ + TA66XX_BC_DSP_FPGA_GPIO3, /**< DSP-to-FPGA GPIO pin 3 */ + TA66XX_BC_DSP_FPGA_GPIO4, /**< DSP-to-FPGA GPIO pin 4 */ + TA66XX_BC_DSP_FPGA_GPIO5, /**< DSP-to-FPGA GPIO pin 5 */ + TA66XX_BC_DSP_FPGA_GPIO6, /**< DSP-to-FPGA GPIO pin 6 */ + TA66XX_BC_DSP_FPGA_GPIO7 /**< DSP-to-FPGA GPIO pin 7 */ +}; + +/** DSP-to-FPGA GPIO pins bitmask definitions */ +enum TA66XX_BC_DSP_FPGA_GPIO_BITMASKS +{ + TA66XX_BC_DSP_FPGA_GPIO0_BITMASK = 0x0001, /**< DSP-to-FPGA GPIO pin 0 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO1_BITMASK = 0x0002, /**< DSP-to-FPGA GPIO pin 1 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO2_BITMASK = 0x0004, /**< DSP-to-FPGA GPIO pin 2 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO3_BITMASK = 0x0008, /**< DSP-to-FPGA GPIO pin 3 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO4_BITMASK = 0x0010, /**< DSP-to-FPGA GPIO pin 4 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO5_BITMASK = 0x0020, /**< DSP-to-FPGA GPIO pin 5 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO6_BITMASK = 0x0040, /**< DSP-to-FPGA GPIO pin 6 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO7_BITMASK = 0x0080, /**< DSP-to-FPGA GPIO pin 7 bitmask */ + TA66XX_BC_DSP_FPGA_GPIO_BITMASK = 0x00ff /**< DSP-to-FPGA GPIO pins bitmask */ +}; + + +/** DSP-to-FPGA GPIO pins direction definitions */ +#define TA66XX_BC_DSP_FPGA_GPIO_DIR_OUT C66XX_GPIO_DIR_OUT +#define TA66XX_BC_DSP_FPGA_GPIO_DIR_IN C66XX_GPIO_DIR_IN + + +/*------------ TA66XX_BC_set_dsp_to_fpga_gpio_enable() function ----------*//** + * @brief Function enables or disables on-board DSP-to-FPGA GPIO pins + * + * @param[in] state - DSP-to-FPGA GPIO pins enable state: TA66XX_ON or + * TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_to_fpga_gpio_enable(uint32_t enable); + + +/*------------ TA66XX_BC_get_dsp_to_fpga_gpio_enable_status() function ---*//** + * @brief Function returns enable status of on-board DSP-to-FPGA GPIO pins + * + * @return DSP-to-FPGA GPIO pins enable state: TA66XX_ON or TA66XX_OFF; + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_to_fpga_gpio_enable_status(void); + + +/*------------ TA66XX_BC_set_dsp_to_fpga_gpio_pin_dir() function ---------*//** + * @brief Function sets selected DSP-to-FPGA GPIO pin direction: IN or OUT + * + * @param[in] pin - DSP-to-FPGA GPIO pin number; + * @param[in] dir - DSP-to-FPGA GPIO pin direction: IN or OUT + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_to_fpga_gpio_pin_dir(uint32_t pin, uint32_t dir); + + +/*------------ TA66XX_BC_get_dsp_to_fpga_gpio_pin_dir() function ---------*//** + * @brief Function returns selected DSP-to-FPGA GPIO pin direction: IN or OUT + * + * @param[in] pin - DSP-to-FPGA GPIO pin number; + * + * @return DSP-to-FPGA GPIO pin direction: IN or OUT + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_to_fpga_gpio_pin_dir(uint32_t pin); + + +/*------------ TA66XX_BC_set_dsp_to_fpga_gpio_pin_data() function --------*//** + * @brief Function sets selected DSP-to-FPGA GPIO pin to the desired state: ON + * or OFF + * + * @param[in] pin - DSP-to-FPGA GPIO pin number; + * @param[in] data - DSP-to-FPGA GPIO pin state: TA66XX_ON or TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_to_fpga_gpio_pin_data(uint32_t pin, uint32_t data); + + +/*------------ TA66XX_BC_get_dsp_to_fpga_gpio_pin_data() function --------*//** + * @brief Function returns selected DSP-to-FPGA GPIO pin state: ON or OFF + * + * @param[in] pin - DSP-to-FPGA GPIO pin number; + * + * @return DSP-to-FPGA GPIO pin state: TA66XX_ON or TA66XX_OFF + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_to_fpga_gpio_pin_data(uint32_t pin); + + +/*------------ TA66XX_BC_set_dsp_to_fpga_gpio_dir() function -------------*//** + * @brief Function sets selected DSP-to-FPGA GPIO pins direction: IN or OUT + * + * @param[in] pin_bitmask - DSP-to-FPGA GPIO pins (ORed) bitmask; + * @param[in] dir - DSP-to-FPGA GPIO pin direction: IN or OUT + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_to_fpga_gpio_dir(uint32_t pin_bitmask, uint32_t dir); + + +/*------------ TA66XX_BC_get_dsp_to_fpga_gpio_dir() function -------------*//** + * @brief Function returns selected DSP-to-FPGA GPIO pins direction: IN or OUT + * + * @param[in] pin - DSP-to-FPGA GPIO pins (ORed) bitmask; + * + * @return DSP-to-FPGA GPIO pins direction: IN or OUT + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_to_fpga_gpio_dir(uint32_t pin_bitmask); + + +/*------------ TA66XX_BC_set_dsp_to_fpga_gpio_data() function ------------*//** + * @brief Function sets selected DSP-to-FPGA GPIO pins to the desired state: ON + * or OFF + * + * @param[in] pin_bitmask - DSP-to-FPGA GPIO pins (ORed) bitmask; + * @param[in] data - DSP-to-FPGA GPIO pins state: TA66XX_ON or TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_dsp_to_fpga_gpio_data(uint32_t pin_bitmask, uint32_t data); + + +/*------------ TA66XX_BC_get_dsp_to_fpga_gpio_data() function ------------*//** + * @brief Function returns selected DSP-to-FPGA GPIO pins state: ON or OFF + * + * @param[in] pin - DSP-to-FPGA GPIO pins (ORed) bitmask; + * + * @return DSP-to-FPGA GPIO pins state + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_dsp_to_fpga_gpio_data(uint32_t pin_bitmask); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ DSP GPIO IRQ functions ========================================= +//============================================================================= + +/** @addtogroup TA66XX_BC_DSP_GPIO_IRQ TORNADO AMC DSP GPIO IRQ mapping functions + * @{ + */ + +/** DSP GPIO pins IRQ source definitions */ +enum TA66XX_BC_DSP_GPIO_IRQ_SEL_SOURCE +{ + TA66XX_BC_DSP_GPIO_IRQ_SEL_OFF = 0, /**< DSP IRQ is disabled */ + TA66XX_BC_DSP_GPIO_IRQ_SEL_MMC_TO_DSP_PD_ALERT, /**< MMC-to-DSP power-down alert is used to generate DSP IRQ */ + TA66XX_BC_DSP_GPIO_IRQ_SEL_MMC_TO_DSP_COMM_RQ, /**< MMC-to-DSP communication request is used to generate DSP IRQ */ + TA66XX_BC_DSP_GPIO_IRQ_SEL_1GE_PHY_IRQ /**< 1GE PHY IRQ is used to generate DSP IRQ */ +}; + +/** DSP GPIO-6 and GPIO-7 pins definitions for TA6678 rev.1B and TA6678/FMC rev.1A boards */ +#define TA66XX_BC_DSP_GPIO6_PIN 6 +#define TA66XX_BC_DSP_GPIO7_PIN 7 +/** DSP GPIO-8 and GPIO-9 pins definitions for TA6678/FMC rev.1B and later boards */ +#define TA66XX_BC_DSP_GPIO8_PIN 8 +#define TA66XX_BC_DSP_GPIO9_PIN 9 + + +/*------------ TA66XX_BC_map_dsp_gpio_interrupt() function ---------------*//** + * @brief Function maps IRQ source to selected DSP GPIO pin + * + * @param[in] gpio_pin - DSP GPIO pin; + * @param[in] irq_src - IRQ source; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_map_dsp_gpio_interrupt(uint32_t gpio_pin, uint32_t irq_src); + + +/*------------ TA66XX_BC_unmap_dsp_gpio_interrupt() function -------------*//** + * @brief Function unmaps IRQ source from selected DSP GPIO pin + * + * @param[in] gpio_pin - DSP GPIO pin; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_unmap_dsp_gpio_interrupt(uint32_t gpio_pin); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ UART functions ================================================= +//============================================================================= + +/** @addtogroup TA66XX_BC_UART TORNADO AMC UART functions + * @{ + */ + +/** DSP UART printf-like string max length */ +#define TA66XX_BC_UART_PRINTF_LEN_MAX 1023 + + +/*------------ TA66XX_BC_init_uart() function ---------------------------*//** + * @brief Function inits the DSP UART peripheral + * + * @param[in] baud_rate - desired baud rate; + * @param[in] data_bits - number of data bits; + * @param[in] parity - parity bit; + * @param[in] stop_bits - number of stop bits; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_init_uart(uint32_t baud_rate, uint32_t data_bits, uint32_t parity, uint32_t stop_bits); + + +/*------------ TA66XX_BC_uart_receiver_is_ready() function ---------------*//** + * @brief Function checks if a character is received over DSP UART + * + * @return 1 - a character is received over DSP UART, + * 0 - otherwise + * +-----------------------------------------------------------------------------*/ +#define TA66XX_BC_uart_receiver_is_ready() C66XX_UART_receiver_is_ready() + + +/*------------ TA66XX_BC_uart_receive_char() function --------------------*//** + * @brief Function receives a character over DSP UART + * + * @return Received character + * +-----------------------------------------------------------------------------*/ +#define TA66XX_BC_uart_receive_char() C66XX_UART_receive_char() + + +/*------------ TA66XX_BC_uart_transmit_char() function -------------------*//** + * @brief Function transmits a character over DSP UART + * + * @param[in] c - A character to transmit + * + * @return None + * +-----------------------------------------------------------------------------*/ +#define TA66XX_BC_uart_transmit_char(c) C66XX_UART_transmit_char(c) + + +/*------------ TA66XX_BC_uart_transmit_string() function -----------------*//** + * @brief Function transmits a string until '0' charachter + * + * @param[in] s - A pointer to the string to transmit + * + * @return None + * +-----------------------------------------------------------------------------*/ +#define TA66XX_BC_uart_transmit_string(s) C66XX_UART_transmit_string(s) + + +/*------------ TA66XX_BC_uart_receive_line_string() function -------------*//** + * @brief Function receives a line ended with CR character, and stores + * received characters into string with '\0' symbol. + * + * @param[in] s - Pointer to a string to store received characters + * + * @return Number of received characters without '\0' symbol. + * +-----------------------------------------------------------------------------*/ +#define TA66XX_BC_uart_receive_line_string(s) C66XX_UART_receive_line_string(s) + + +/*------------ TA66XX_BC_uart_printf() function --------------------------*//** + * @brief Function prints messages to UART + * + * @param[in] format - format string; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_uart_printf(const char *format, ...); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ EEPROM functions =============================================== +//============================================================================= + +/** @addtogroup TA66XX_BC_EEPROM TORNADO AMC EEPROM memory functions + * @{ + */ + +/*------------ TA66XX_BC_get_eeprom_length() function --------------------*//** + * @brief Function returns on-board EEPROM memory length in bytes + * + * @return On-board EEPROM memory length in bytes + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_eeprom_length(void); + + +/*------------ TA66XX_BC_write_eeprom() function -------------------------*//** + * @brief Function writes data[len] to EEPROM memory starting at memory + * address addr + * + * @param[in] addr - memory address within the chip; + * @param[in] data - pointer to data; + * @param[in] len - data len in bytes; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_write_eeprom(uint32_t addr, uint8_t *data, uint32_t len); + + +/*------------ TA66XX_BC_read_eeprom() function --------------------------*//** + * @brief Function reads data[len] from EEPROM memory starting at memory + * address addr + * + * @param[in] addr - memory address within the chip; + * @param[out] buf - pointer to data buffer to store data; + * @param[in] len - data len in bytes; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_read_eeprom(uint32_t addr, uint8_t *buf, uint32_t len); + + +/*------------ TA66XX_BC_erase_eeprom() function -------------------------*//** + * @brief Function erases len bytes from EEPROM memory starting at memory + * address addr + * + * @param[in] addr - memory address within the chip; + * @param[in] len - number of bytes to erase; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_erase_eeprom(uint32_t addr, uint32_t len); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ Board info functions =========================================== +//============================================================================= + +/** @addtogroup TA66XX_BC_BOARD_INFO TORNADO AMC board info functions + * @{ + */ + + +/** Board info data descriptor IDs */ +#define TA66XX_BC_BOARD_INFO_ID_TA6678_REV1B 1 +#define TA66XX_BC_BOARD_INFO_ID_TA6678FMC_REV1A 2 +#define TA66XX_BC_BOARD_INFO_ID_TA6678FMC_REV1B 3 + + +/** Board temperature data descriptor */ +typedef struct +{ + float temp_pcb, /**< PCB current temperature */ + temp_dsp, /**< DSP current temperature */ + temp_fpga; /**< FPGA current temperature */ + + // TEMP zone classification status + // This var is set according to TA6678_MC_TEMP_ZONE_ID_xxxx defs. + uint32_t temp_zone_id; /**< Temperature zone ID */ + + // 8-bit integer thresholds for MMC TEMP zones + // These thresholds are used to classify summary temparature, which MMC derives + // from PCB, DSP and FPGA temperatures. + char overheated_low_zone_threshold, /**< OVERHEATED low threshold (P/S will be switched OFF at this threshold and upper) */ + hot_low_zone_threshold, /**< HOT low threshold (P/S will be not switched ON at this threshold and upper) */ + warm3_low_zone_threshold, /**< WARM3 low threshold */ + warm2_low_zone_threshold, /**< WARM2 low threshold */ + warm1_low_zone_threshold, /**< WARM1 low threshold */ + normal_low_zone_threshold, /**< NORMAL low threshold */ + cold1_low_zone_threshold, /**< COLD1 low threshold */ + cold2_low_zone_threshold, /**< COLD2 low threshold */ + cold3_low_zone_threshold, /**< COLD3 low threshold (P/S will be not switched ON below this threshold) */ + frosty_low_zone_threshold; /**< FROSTY low threshold (P/S will be switched OFF below this threshold) */ + + // 8-bit integer thresholds for AMC TEMP zones for every on-board temp sensor + char amc_pcb_temp_noncritical_threshold, /**< PCB temperature AMC UPPER NON-CRITICAL ASSERTING EVENT threshold */ + amc_pcb_temp_critical_threshold, /**< PCB temperature AMC UPPER CRITICAL ASSERTING EVENT threshold */ + amc_pcb_temp_nonrecoverable_threshold, /**< PCB temperature AMC UPPER NON-RECOVERABLE ASSERTING EVENT threshold */ + amc_pcb_temp_hysteresis, /**< PCB temperature AMC positive going hysteresis */ + + amc_dsp_temp_noncritical_threshold, /**< DSP temperature AMC UPPER NON-CRITICAL ASSERTING EVENT threshold */ + amc_dsp_temp_critical_threshold, /**< DSP temperature AMC UPPER CRITICAL ASSERTING EVENT threshold */ + amc_dsp_temp_nonrecoverable_threshold, /**< DSP temperature AMC UPPER NON-RECOVERABLE ASSERTING EVENT threshold */ + amc_dsp_temp_hysteresis, /**< DSP temperature AMC positive going hysteresis */ + + amc_fpga_temp_noncritical_threshold, /**< FPGA temperature AMC UPPER NON-CRITICAL ASSERTING EVENT threshold */ + amc_fpga_temp_critical_threshold, /**< FPGA temperature AMC UPPER CRITICAL ASSERTING EVENT threshold */ + amc_fpga_temp_nonrecoverable_threshold, /**< FPGA temperature AMC UPPER NON-RECOVERABLE ASSERTING EVENT threshold */ + amc_fpga_temp_hysteresis; /**< FPGA temperature AMC positive going hysteresis */ + +} TA66XX_BC_TEMP_DATA_DD; +// Board temperature data descriptor length +#define TA66XX_BC_TEMP_DATA_DD_LEN sizeof(TA66XX_BC_TEMP_DATA_DD) + + +/** Board current power data descriptor for TA6678 rev.1B-1 board */ +typedef struct +{ + float v_12v, /**< Input +12V power supply voltage value */ + i_12v, /**< Input +12V power supply current value */ + v_3v3_aux, /**< On-board auxiliary +3.3V power supply voltage value */ + i_3v3_aux, /**< On-board auxiliary +3.3V power supply current value */ + v_mc, /**< Module management power supply voltage value */ + i_mc, /**< Module management power supply current value */ + v_3v3, /**< On-board +3.3V power supply voltage value */ + i_3v3, /**< On-board +3.3V power supply current value */ + v_2v5, /**< On-board +2.5V power supply voltage value */ + i_2v5, /**< On-board +2.5V power supply current value */ + v_1v8, /**< On-board +1.8V power supply voltage value */ + i_1v8, /**< On-board +1.8V power supply current value */ + v_1v5, /**< On-board +1.5V power supply voltage value */ + i_1v5, /**< On-board +1.5V power supply current value */ + v_1v0, /**< On-board +1.0V power supply voltage value */ + i_1v0, /**< On-board +1.0V power supply current value */ + v_ddr_vtt, /**< On-board DDR3 VTT power supply voltage value */ + v_dsp_vcore, /**< On-board DSP core power supply voltage value */ + i_dsp_vcore, /**< On-board DSP core power supply current value */ + v_fpga_vcore, /**< On-board FPGA core power supply voltage value */ + i_fpga_vcore, /**< On-board FPGA core power supply current value */ + v_fpga_mgtavcc, /**< On-board FPGA MGTAVCC power supply voltage value */ + v_fpga_mgtavtt; /**< On-board FPGA MGTAVTT power supply voltage value */ + +} TA6678_REV1B_BC_POWER_DATA_DD; +// Board current power data descriptor for TA6678 rev.1B-1 board length +#define TA6678_REV1B_BC_POWER_DATA_DD_LEN sizeof(TA6678_REV1B_BC_POWER_DATA_DD) + + +/** Board current power data descriptor for TA6678/FMC rev.1A and later boards */ +typedef struct +{ + float power_12v, /**< Input +12V power supply value */ + power_fpga_core, /**< On-board FPGA core power supply value */ + power_dsp_core, /**< On-board DSP core power supply value */ + v_12v, /**< Input +12V power supply voltage value */ + i_12v, /**< Input +12V power supply current value */ + i_fpga_core, /**< On-board FPGA core power supply current value */ + i_dsp_core; /**< On-board DSP core power supply current value */ + +} TA66XX_BC_PRIMARY_POWER_DATA_DD; +// Board current power data descriptor length +#define TA66XX_BC_PRIMARY_POWER_DATA_DD_LEN sizeof(TA66XX_BC_PRIMARY_POWER_DATA_DD) + + +/** Board current power data union */ +typedef union +{ + TA6678_REV1B_BC_POWER_DATA_DD ta6678_rev1b_dd; + TA66XX_BC_PRIMARY_POWER_DATA_DD primary_power_dd; +} POWER_DATA_DD; + + +/** Board current power data descriptor */ +typedef struct +{ + unsigned id; // ID to decode the UNION structure type + POWER_DATA_DD power_data_dd; + +} TA66XX_BC_POWER_DATA_DD; +// Board current power data descriptor length +#define TA66XX_BC_POWER_DATA_DD_LEN sizeof(TA66XX_BC_POWER_DATA_DD) + + +/** FMC interface power data descriptor for TA6678/FMC rev.1A and later boards */ +typedef struct +{ + float power_fmc_12v, /**< FMC I/F +12V power supply value */ + power_fmc_3v3, /**< FMC I/F +3.3V power supply value */ + power_fmc_vadj, /**< FMC I/F Vadj power supply value */ + v_fmc_12v, /**< FMC I/F +12V power supply voltage value */ + i_fmc_12v, /**< FMC I/F +12V power supply current value */ + v_fmc_3v3, /**< FMC I/F +3.3V power supply voltage value */ + i_fmc_3v3, /**< FMC I/F +3.3V power supply current value */ + v_fmc_vadj, /**< FMC I/F Vadj power supply voltage value */ + i_fmc_vadj, /**< FMC I/F Vadj power supply current value */ + v_fmc_vio_b_m2c, /**< FMC I/F VIO_B_M2C power supply voltage value */ + v_fmc_vref_a_m2c, /**< FMC I/F VREF_A_M2C power supply voltage value */ + v_fmc_vref_b_m2c; /**< FMC I/F VREF_B_M2C power supply voltage value */ + +} TA66XX_BC_FMC_POWER_DATA_DD; +// FMC interface power data descriptor length +#define TA66XX_BC_FMC_POWER_DATA_DD_LEN sizeof(TA66XX_BC_FMC_POWER_DATA_DD) + + +/** Max string length in device info structure */ +#define TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX 32 +#define TA66XX_BC_DEVICE_PN_STRING_LEN_MAX 64 +#define TA66XX_BC_DEVICE_HW_REVISION_STRING_LEN_MAX 16 + + +/** Board info data descriptor for TA6678 rev.1B-1 board */ +typedef struct +{ + uint32_t op_mode; /**< Operation mode: '0' - stand-alone mode, '1' - AMC host mode */ + uint32_t amc_slot_id; /**< AMC slot ID (in case AMC host mode is used) */ + uint8_t manufacturing_date_day_of_month; /**< Manufacturing day: 1..31 */ + uint8_t manufacturing_date_month; /**< Manufacturing month: 1..12 ('1' - January) */ + uint16_t manufacturing_date_year; /**< Manufacturing year: 2015.. */ + char device_sn[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< Device serial number */ + char mmc_fw_rev[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< MMC firmware revision string */ + char tammc_fw_rev[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< TAMMC firmware revision string */ + char mmc_core_fw_rev[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< MMC core firmware revision string */ +} TA6678_REV1B_BC_DEVICE_INFO_DATA_DD; +// Board info data descriptor for TA6678 rev.1B-1 board length +#define TA6678_REV1B_BC_DEVICE_INFO_DATA_DD_LEN sizeof(TA6678_REV1B_BC_DEVICE_INFO_DATA_DD) + + +/** Board info data descriptor for TA6678/FMC rev.1A and later boards */ +typedef struct +{ + uint32_t op_mode; /**< Operation mode: '0' - stand-alone mode, '1' - AMC host mode */ + uint32_t amc_slot_id; /**< AMC slot ID (in case AMC host mode is used) */ + uint8_t manufacturing_date_day_of_month; /**< Manufacturing day: 1..31 */ + uint8_t manufacturing_date_month; /**< Manufacturing month: 1..12 ('1' - January) */ + uint16_t manufacturing_date_year; /**< Manufacturing year: 2015.. */ + char manufacturer_name[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< Manufacturer name */ + char device_name[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< Device name */ + char device_pn[TA66XX_BC_DEVICE_PN_STRING_LEN_MAX]; /**< Device part number */ + char device_sn[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< Device serial number */ + char device_hw_revision[TA66XX_BC_DEVICE_HW_REVISION_STRING_LEN_MAX]; /**< Device H/W revision */ + char mmc_fw_rev[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< MMC firmware revision string */ + char tammc_fw_rev[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< TAMMC firmware revision string */ + char mmc_core_fw_rev[TA66XX_BC_DEVICE_INFO_STRING_LEN_MAX]; /**< MMC core firmware revision string */ +} TA66XX_BC_FULL_DEVICE_INFO_DATA_DD; +// Board info data descriptor length +#define TA66XX_BC_FULL_DEVICE_INFO_DATA_DD_LEN sizeof(TA66XX_BC_FULL_DEVICE_INFO_DATA_DD) + + +/** Board current power data union */ +typedef union +{ + TA6678_REV1B_BC_DEVICE_INFO_DATA_DD ta6678_rev1b_dd; + TA66XX_BC_FULL_DEVICE_INFO_DATA_DD ta66xx_full_device_info_dd; +} DEVICE_INFO_DATA_DD; + + +/** Board current power data descriptor */ +typedef struct +{ + uint32_t id; // ID to decode the UNION structure type + DEVICE_INFO_DATA_DD device_info_data_dd; + +} TA66XX_BC_DEVICE_INFO_DATA_DD; +// Board current power data descriptor length +#define TA66XX_BC_DEVICE_INFO_DATA_DD_LEN sizeof(TA66XX_BC_DEVICE_INFO_DATA_DD) + + +/** Hardware configuration info data descriptor for TA6678/FMC rev.1A and later boards */ +typedef struct +{ + uint32_t fpga_ddr0_len; /**< FPGA DDR memory bank #0 length in MB: 0 - not installed */ + uint32_t fpga_ddr1_len; /**< FPGA DDR memory bank #1 length in MB: 0 - not installed */ + uint32_t cpu_ddr_len; /**< CPU DDR memory length in MB: 0 - not installed */ + uint32_t flash_len; /**< FLASH memory length in MB: 0 - not installed */ + uint32_t mram_len; /**< MRAM memory length in KB: 0 - not installed */ + uint32_t i2c_eeprom_len; /**< I2C EEPROM memory length in KB: 0 - not installed */ + uint32_t cpu_clk_freq_id; /**< CPU input clock frequency in MHz: 0 - not available */ + uint32_t x1ge0_phy_installed_id; /**< External 1GE PHY #0 installed ID: 0 - not installed */ + uint32_t x1ge1_phy_installed_id; /**< External 1GE PHY #1 installed ID: 0 - not installed */ + uint32_t sfp0_if_installed_id; /**< SFP interface #0 installed ID: 0 - not installed */ + uint32_t sfp1_if_installed_id; /**< SFP interface #1 installed ID: 0 - not installed */ + uint32_t qsfp_if_installed_id; /**< QSFP interface installed ID: 0 - not installed */ + uint32_t fmc_if_installed_id; /**< FMC interface installed ID: 0 - not installed */ + uint32_t sd_slot_installed_id; /**< uSD slot installed ID: 0 - not installed */ +} TA66XX_BC_HW_CFG_INFO_DATA_DD; +// Hardware configuration info data descriptor length +#define TA66XX_BC_HW_CFG_INFO_DATA_DD_LEN sizeof(TA66XX_BC_HW_CFG_INFO_DATA_DD) + + +/** Max string length in FMC info structure */ +#define TA66XX_BC_FMC_STATUS_STRING_LEN_MAX 48 +#define TA66XX_BC_FMC_INFO_STRING_LEN_MAX 64 +#define TA66XX_BC_MANUFACTURING_TIME_STRING_LEN_MAX 32 + + +/** FMC info data descriptor for TA6678/FMC rev.1A and later boards */ +typedef struct +{ + char fmc_status_text[TA66XX_BC_FMC_STATUS_STRING_LEN_MAX]; /**< FMC status */ + char manufacturer_name[TA66XX_BC_FMC_INFO_STRING_LEN_MAX]; /**< Manufacturer name */ + char device_name[TA66XX_BC_FMC_INFO_STRING_LEN_MAX]; /**< Device name */ + char device_pn[TA66XX_BC_FMC_INFO_STRING_LEN_MAX]; /**< Device part number */ + char device_sn[TA66XX_BC_FMC_INFO_STRING_LEN_MAX]; /**< Device serial number */ + char device_version[TA66XX_BC_FMC_INFO_STRING_LEN_MAX]; /**< Device version */ + char manufacturing_time[TA66XX_BC_MANUFACTURING_TIME_STRING_LEN_MAX]; /**< Manufacturing time */ +} TA66XX_BC_FMC_INFO_DATA_DD; +// FMC info data descriptor length +#define TA66XX_BC_FMC_INFO_DATA_DD_LEN sizeof(TA66XX_BC_FMC_INFO_DATA_DD) + + + +/*------------ TA66XX_BC_get_device_info() function ----------------------*//** + * @brief Function returns AMC module device info: operation mode, serial + * number, manufacturing date, firmware revisions + * + * @param[out] info_dd - pointer to a buffer that receives device info data + * descriptor in case function is completed without errors. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_device_info(TA66XX_BC_DEVICE_INFO_DATA_DD *info_dd); + + +/*------------ TA66XX_BC_get_hw_cfg_info() function ----------------------*//** + * @brief Function returns AMC module hardware configuration info: installed + * memories, interfaces, etc. + * + * @param[out] info_dd - pointer to a buffer that receives hardware + * configuration data descriptor in case function is completed + * without errors. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_hw_cfg_info(TA66XX_BC_HW_CFG_INFO_DATA_DD *info_dd); + + +/*------------ TA66XX_BC_get_fmc_info() function -------------------------*//** + * @brief Function returns FMC module device info: installed status, device + * name, serial number, manufacturing date, firmware revisions, etc. + * + * @param[out] info_dd - pointer to a buffer that receives FMC info data + * descriptor in case function is completed without errors. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_fmc_info(TA66XX_BC_FMC_INFO_DATA_DD *info_dd); + + +/*------------ TA66XX_BC_get_temp_state() function -----------------------*//** + * @brief Function returns AMC module temperature monitor current info + * + * @param[out] temp_data_dd - pointer to a buffer that receives board + * temperature data descriptor in case function is completed + * without errors. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_temp_state(TA66XX_BC_TEMP_DATA_DD *temp_data_dd); + + +/*------------ TA66XX_BC_get_power_state() function ----------------------*//** + * @brief Function returns AMC module power monitor current info + * + * @param[out] power_data_dd - pointer to a buffer that receives board power + * data descriptor in case function is completed without errors. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_power_state(TA66XX_BC_POWER_DATA_DD *power_data_dd); + + +/*------------ TA66XX_BC_get_fmc_power_state() function ------------------*//** + * @brief Function returns FMC module power monitor current info + * + * @param[out] fmc_power_data_dd - pointer to a buffer that receives FMC + * module power data descriptor in case function is completed + * without errors. + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_fmc_power_state(TA66XX_BC_FMC_POWER_DATA_DD *fmc_power_data_dd); + + +/*------------ TA66XX_BC_set_mmc_to_dsp_rq() function --------------------*//** + * @brief Function sets MMC-to-DSP request from DSP (for test purposes) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_set_mmc_to_dsp_rq(void); + + +/*------------ TA66XX_BC_set_mmc_power_down_notification() function ------*//** + * @brief Function sets MMC-to-DSP power down notification from DSP + * (for test purposes) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_set_mmc_power_down_notification(void); + + +/*------------ TA66XX_BC_get_sfp_info() function -------------------------*//** + * @brief Function returns identification info about installed SFP + * transceiver: 256-byte array read from address 0x50 (identification info + * according to SFF-8472) and 256-byte array read from address 0x51 (digital + * diagnostic monitoring interface (DDMI) data) + * + * @param[out] id_data - pointer to a buffer that receives 256-byte array read + * from address 0x50 (identification info according to SFF-8472). + * In case pointer is NULL, then no data are filled in; + * @param[out] ddmi_data - pointer to a buffer that receives 256-byte array + * read from address 0x51 (DDMI data). In case pointer is NULL, + * then no data are filled in; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_sfp_info(uint8_t *id_data, uint8_t *ddmi_data); + + +/** @}*/ + +//============================================================================= + + + +//============================================================================= +//============ FPGA functions ================================================= +//============================================================================= + +/** @addtogroup TA66XX_BC_FPGA TORNADO AMC FPGA functions + * @{ + */ + +/** FPGA host interface (HIF) configuration data descriptor */ +typedef struct +{ + uint32_t w_setup; /**< Write strobe setup EMIF-16 cycles */ + uint32_t w_strobe; /**< Write strobe duration EMIF-16 cycles */ + uint32_t w_hold; /**< Write strobe hold EMIF-16 cycles */ + uint32_t r_setup; /**< Read strobe setup EMIF-16 cycles */ + uint32_t r_strobe; /**< Read strobe duration EMIF-16 cycles */ + uint32_t r_hold; /**< Read strobe hold EMIF-16 cycles */ + uint32_t turn_around; /**< Turn around EMIF-16 cycles */ +} TA66XX_BC_FPGA_HIF_CNF_DD; +// FPGA HIF configuration data descriptor length in bytes +#define TA66XX_BC_FPGA_HIF_CNF_DD_LEN sizeof(TA66XX_BC_FPGA_HIF_CNF_DD) + + +/*------------ TA66XX_BC_set_fpga_hif_cnf() function ---------------------*//** + * @brief Function sets new configuration to FPGA host interface according to + * supplied parameters + * + * @param[in] cfg_dd - pointer to new FPGA HIF configuration data descriptor; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_set_fpga_hif_cnf(TA66XX_BC_FPGA_HIF_CNF_DD *cfg_dd); + + +/*------------ TA66XX_BC_get_fpga_hif_cnf() function ---------------------*//** + * @brief Function returns current configuration of FPGA host interface + * + * @param[in] cfg_dd - pointer to buffer to receive current FPGA HIF + * configuration data descriptor; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_fpga_hif_cnf(TA66XX_BC_FPGA_HIF_CNF_DD *cfg_dd); + + +/*------------ TA66XX_BC_get_fpga_hif_base_addr() function ---------------*//** + * @brief Function returns FPGA host interface base address + * + * @return FPGA host interface base address + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_fpga_hif_base_addr(void); + + +/*------------ TA66XX_BC_get_fpga_hif_length() function ------------------*//** + * @brief Function returns FPGA host interface length in bytes + * + * @return FPGA host interface length in bytes + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_fpga_hif_length(void); + + +/*------------ TA66XX_BC_set_fpga_hif_reset() function -------------------*//** + * @brief Function sets or releases FPGA host interface reset + * + * @param[in] state - FPGA host interface reset state: ON or OFF + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_fpga_hif_reset(uint32_t state); + + +/*------------ TA66XX_BC_get_fpga_hif_reset_state() function -------------*//** + * @brief Function returns FPGA host interface reset state + * + * @return FPGA host interface reset state: ON or OFF + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_fpga_hif_reset_state(void); + + +/*------------ TA66XX_BC_read_fpga_hif_byte() function -------------------*//** + * @brief Function reads a byte from FPGA host interface at address addr. + * + * @param[in] addr - FPGA address to read from + * + * @return A byte read from FPGA host interface + * +-----------------------------------------------------------------------------*/ +uint8_t TA66XX_BC_read_fpga_hif_byte(uint32_t addr); + + +/*------------ TA66XX_BC_write_fpga_hif_byte() function ------------------*//** + * @brief Function writes a byte to FPGA host interface at address addr. + * + * @param[in] addr - FPGA address to write to + * @param[in] v - A byte to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_fpga_hif_byte(uint32_t addr, uint8_t v); + + +/*------------ TA66XX_BC_read_fpga_hif_w16() function --------------------*//** + * @brief Function reads a 16-bit word from FPGA host interface at address + * addr. + * + * @param[in] addr - FPGA address to read from + * + * @return A 16-bit word read from FPGA host interface + * +-----------------------------------------------------------------------------*/ +uint16_t TA66XX_BC_read_fpga_hif_w16(uint32_t addr); + + +/*------------ TA66XX_BC_write_fpga_hif_w16() function -------------------*//** + * @brief Function writes a 16-bit word to FPGA host interface at address + * addr. + * + * @param[in] addr - FPGA address to write to + * @param[in] v - A 16-bit word to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_fpga_hif_w16(uint32_t addr, uint16_t v); + + +/*------------ TA66XX_BC_read_fpga_hif_w32() function --------------------*//** + * @brief Function reads a 32-bit word from FPGA host interface at address + * addr. + * + * @param[in] addr - FPGA address to read from + * + * @return A 32-bit word read from FPGA host interface + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_read_fpga_hif_w32(uint32_t addr); + + +/*------------ TA66XX_BC_write_fpga_hif_w32() function -------------------*//** + * @brief Function writes a 32-bit word to FPGA host interface at address + * addr. + * + * @param[in] addr - FPGA address to write to + * @param[in] v - A 32-bit word to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_fpga_hif_w32(uint32_t addr, uint32_t v); + + +/*------------ TA66XX_BC_read_fpga_hif_w64() function --------------------*//** + * @brief Function reads a 64-bit word from FPGA host interface at address + * addr. + * + * @param[in] addr - FPGA address to read from + * + * @return A 64-bit word read from FPGA host interface + * +-----------------------------------------------------------------------------*/ +uint64_t TA66XX_BC_read_fpga_hif_w64(uint32_t addr); + + +/*------------ TA66XX_BC_write_fpga_hif_w64() function -------------------*//** + * @brief Function writes a 64-bit word to FPGA host interface at address + * addr. + * + * @param[in] addr - FPGA address to write to + * @param[in] v - A 64-bit word to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_fpga_hif_w64(uint32_t addr, uint64_t v); + + +/*------------ TA66XX_BC_clear_fpga_cnf() function -----------------------*//** + * @brief Function clears FPGA configuration memory + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_clear_fpga_cnf(void); + + +/*------------ TA66XX_BC_load_fpga_cnf() function ------------------------*//** + * @brief Function loads FPGA firmware file using the supported configuration + * interfaces (serial or parallel) + * + * @param[in] addr - address where FPGA firmware file data were saved; + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_load_fpga_cnf(uint32_t addr); + + +/*------------ TA66XX_BC_get_fpga_cnf_status() function ------------------*//** + * @brief Function returns FPGA configuration memory status: either + * loaded by FPGA firmware file or not + * + * @return TA66XX_OK - FPGA configuration memory is loaded, + * TA66XX_FPGA_CNF_LOAD_ERR - FPGA configuration memory is cleared. + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_fpga_cnf_status(void); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ FLASH functions ================================================ +//============================================================================= + +/** @addtogroup TA66XX_BC_FLASH TORNADO AMC FLASH API functions + * @{ + */ + + +/** FLASH memory sector is protected for write/erase operations */ +#define TA66XX_BC_FLASH_SECTOR_PROTECTED 1 +/** FLASH memory sector is unprotected for write/erase operations */ +#define TA66XX_BC_FLASH_SECTOR_UNPROTECTED 0 + + +/*------------ TA66XX_BC_get_flash_area_base_addr() function -------------*//** + * @brief Function returns FLASH area base address + * + * @return FLASH area base address + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_flash_area_base_addr(void); + + +/*------------ TA66XX_BC_get_flash_length() function ---------------------*//** + * @brief Function returns on-board FLASH memory length in bytes + * + * @return On-board FLASH memory length in bytes + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_flash_length(void); + + +/*------------ TA66XX_BC_get_flash_hw_wp_enable_status() function --------*//** + * @brief Function returns enable status of on-board FLASH memory hardware + * (via on-board switch) write-protection + * + * @return On-board FLASH memory hardware write-protection enable state: + * TA66XX_ON or TA66XX_OFF + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_flash_hw_wp_enable_status(void); + + +/*------------ TA66XX_BC_get_flash_sw_wp_enable_status() function --------*//** + * @brief Function returns enable status of on-board FLASH memory software + * write-protection + * + * @return On-board FLASH memory software write-protection enable state: + * TA66XX_ON or TA66XX_OFF + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_flash_sw_wp_enable_status(void); + + +/*------------ TA66XX_BC_set_flash_sw_wp_enable() function ---------------*//** + * @brief Function enables or disables on-board FLASH memory software + * write-protection + * + * @param[in] enable - on-board FLASH memory software write-protection enable + * state: TA66XX_ON or TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_flash_sw_wp_enable(uint32_t enable); + + +/*------------ TA66XX_BC_erase_flash() function --------------------------*//** + * @brief Function erases FLASH block, which starts from address a + * and of size len (in bytes) + * + * @param[in] addr - Block start address (in bytes) + * @param[in] len - block length (in bytes) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_erase_flash(uint32_t addr, uint32_t len); + + +/** Flag to disable FLASH memory erasing before write operation */ +#define TA66XX_BC_FLASH_ERASE_IS_DISABLED 0 +/** Flag to enable FLASH memory erasing before write operation */ +#define TA66XX_BC_FLASH_ERASE_IS_ENABLED 1 + + +/*------------ TA66XX_BC_write_flash() function --------------------------*//** + * @brief Function writes data block of size len to FLASH address a + * The function erases FLASH before writing data to FLASH if erase input + * parameter is set. + * + * @param[in] a - FLASH address (in bytes) + * @param[in] ptr - data block to write + * @param[in] len - data block length (in bytes) + * @param[in] erase - flag to enable FLASH erasing before write operation + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_write_flash(uint32_t a, void *ptr, uint32_t len, uint32_t erase); + + +/*------------ TA66XX_BC_write_flash_byte() function ---------------------*//** + * @brief Function writes data byte d to FLASH address a + * + * @param[in] a - FLASH address (in bytes) + * @param[in] d - data byte to write + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_write_flash_byte(uint32_t addr, uint8_t d); + + +/*------------ TA66XX_BC_write_flash_w16() function ----------------------*//** + * @brief Function writes 16-bit data word d to FLASH address a + * + * @param[in] addr - FLASH address (in bytes) + * @param[in] d - 16-bit data word to write + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_write_flash_w16(uint32_t addr, uint16_t d); + + +/*------------ TA66XX_BC_write_flash_w32() function ----------------------*//** + * @brief Function writes 32-bit data word d to FLASH address a + * + * @param[in] addr - FLASH address (in bytes) + * @param[in] d - 32-bit data word to write + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_write_flash_w32(uint32_t addr, uint32_t d); + + +/*------------ TA66XX_BC_read_flash() function ---------------------------*//** + * @brief Function reads data block of size len from FLASH address a + * + * @param[in] addr - FLASH address (in bytes) + * @param[in] ptr - pointer to data buffer to store data block + * @param[in] len - data block length (in bytes) + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_read_flash(uint32_t addr, void *ptr, uint32_t len); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ MRAM functions ================================================= +//============================================================================= + +/** @addtogroup TA66XX_BC_MRAM TORNADO AMC MRAM API functions + * @{ + */ + + +/*------------ TA66XX_BC_get_mram_area_base_addr() function --------------*//** + * @brief Function returns MRAM area base address + * + * @return MRAM area base address + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_mram_area_base_addr(void); + + +/*------------ TA66XX_BC_get_mram_length() function ----------------------*//** + * @brief Function returns on-board MRAM memory length in bytes + * + * @return On-board MRAM memory length in bytes + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_mram_length(void); + + +/*------------ TA66XX_BC_get_mram_sw_wp_enable_status() function ---------*//** + * @brief Function returns enable status of on-board MRAM memory software + * write-protection + * + * @return On-board MRAM memory software write-protection enable state: + * TA66XX_ON or TA66XX_OFF + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_get_mram_sw_wp_enable_status(void); + + +/*------------ TA66XX_BC_set_mram_sw_wp_enable() function ----------------*//** + * @brief Function enables or disables on-board MRAM memory software + * write-protection + * + * @param[in] enable - on-board MRAM memory software write-protection enable + * state: TA66XX_ON or TA66XX_OFF; + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_set_mram_sw_wp_enable(uint32_t enable); + + +/*------------ TA66XX_BC_read_mram_byte() function -----------------------*//** + * @brief Function reads a byte from MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to read from + * + * @return A byte read from MRAM memory + * +-----------------------------------------------------------------------------*/ +uint8_t TA66XX_BC_read_mram_byte(uint32_t addr); + + +/*------------ TA66XX_BC_write_mram_byte() function ----------------------*//** + * @brief Function writes a byte to MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to write to + * @param[in] v - A byte to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_mram_byte(uint32_t addr, uint8_t v); + + +/*------------ TA66XX_BC_read_mram_w16() function ------------------------*//** + * @brief Function reads a 16-bit word from MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to read from + * + * @return A 16-bit word read from MRAM memory + * +-----------------------------------------------------------------------------*/ +uint16_t TA66XX_BC_read_mram_w16(uint32_t addr); + + +/*------------ TA66XX_BC_write_mram_w16() function -----------------------*//** + * @brief Function writes a 16-bit word to MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to write to + * @param[in] v - A 16-bit word to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_mram_w16(uint32_t addr, uint16_t v); + + +/*------------ TA66XX_BC_read_mram_w32() function ------------------------*//** + * @brief Function reads a 32-bit word from MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to read from + * + * @return A 32-bit word read from MRAM memory + * +-----------------------------------------------------------------------------*/ +uint32_t TA66XX_BC_read_mram_w32(uint32_t addr); + + +/*------------ TA66XX_BC_write_mram_w32() function -----------------------*//** + * @brief Function writes a 32-bit word to MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to write to + * @param[in] v - A 32-bit word to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_mram_w32(uint32_t addr, uint32_t v); + + +/*------------ TA66XX_BC_read_mram_w64() function ------------------------*//** + * @brief Function reads a 64-bit word from MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to read from + * + * @return A 64-bit word read from MRAM memory + * +-----------------------------------------------------------------------------*/ +uint64_t TA66XX_BC_read_mram_w64(uint32_t addr); + + +/*------------ TA66XX_BC_write_mram_w64() function -----------------------*//** + * @brief Function writes a 64-bit word to MRAM memory at address addr. + * + * @param[in] addr - MRAM memory address to write to + * @param[in] v - A 64-bit word to write + * + * @return None + * +-----------------------------------------------------------------------------*/ +void TA66XX_BC_write_mram_w64(uint32_t addr, uint64_t v); + + +/** @}*/ +//============================================================================= + + + +//============================================================================= +//============ Gigabit Ethernet (GbE) Switch functions ======================== +//============================================================================= + +/** @addtogroup TA66XX_BC_GBE TORNADO AMC Gigabit Ethernet Switch functions + * @{ + */ + +/** Gigabit Ethernet ports count available at the board */ +#define TA66XX_BC_GBE_PORT_COUNT 2 + +/** DSP SGMII port number which is routed to AMC connector */ +#define TA66XX_BC_GBE_PORT_AMC_PORT_NUMBER 0 +/** Alias for DSP SGMII port-0 number */ +#define TA66XX_BC_GBE_PORT_AMC0_PORT_NUMBER TA66XX_BC_GBE_PORT_AMC_PORT_NUMBER +/** DSP SGMII port number which is routed to external PHY */ +#define TA66XX_BC_GBE_PORT_X1GE_PORT_NUMBER 1 +/** Alias for DSP SGMII port-1 number */ +#define TA66XX_BC_GBE_PORT_AMC1_PORT_NUMBER TA66XX_BC_GBE_PORT_X1GE_PORT_NUMBER + + +/** Gigabit Ethernet port type */ +typedef enum +{ + TA66XX_BC_GBE_PORT_TYPE_NONE = 0, /**< Gigabit Ethernet port is not used */ + TA66XX_BC_GBE_PORT_TYPE_PHY, /**< Gigabit Ethernet port is connected to on-board PHY */ + TA66XX_BC_GBE_PORT_TYPE_AMC, /**< Gigabit Ethernet port is connected to the backplane AMC chassis */ + TA66XX_BC_GBE_PORT_TYPE_MAX /**< End of port type */ +} TA66XX_BC_GBE_PORT_TYPE; + + +/** Gigabit Ethernet port link status */ +typedef enum +{ + TA66XX_BC_GBE_PORT_LINK_STATUS_DOWN = 0, /**< Gigabit Ethernet port link is down */ + TA66XX_BC_GBE_PORT_LINK_STATUS_UP, /**< Gigabit Ethernet port link is up */ + TA66XX_BC_GBE_PORT_LINK_STATUS_MAX /**< End of link status */ +} TA66XX_BC_GBE_PORT_LINK_STATUS; + + +/** T-AMC Gigabit Ethernet port data descriptor */ +typedef struct +{ + uint32_t number; /**< Port number */ + TA66XX_BC_GBE_PORT_TYPE type; /**< Gigabit Ethernet port type */ + TA66XX_BC_GBE_PORT_LINK_STATUS link_status; /**< Gigabit Ethernet port link status */ + uint8_t mac_address[6]; /**< MAC (physical) address of the port */ +} TA66XX_BC_GBE_PORT_DD; +// T-AMC Gigabit Ethernet port data descriptor length in bytes +#define TA66XX_BC_GBE_PORT_DD_LEN sizeof(TA66XX_BC_GBE_PORT_DD) + + +/** IP address string max size in bytes*/ +#define TA66XX_BC_IP_ADDRESS_LEN_MAX 16 +/** Host name max size in bytes*/ +#define TA66XX_BC_HOSTNAME_LEN_MAX 256 + + +/** Static IP configuration */ +#define TA66XX_BC_IP_CFG_TYPE_STATIC 0 +/** Dynamic (DHCP) IP configuration */ +#define TA66XX_BC_IP_CFG_TYPE_DYNAMIC 1 + + +/*------------ TA66XX_BC_init_gbe_port() function ------------------------*//** + * @brief Function initializes selected DSP Gigabit Ethernet port + * + * @param[in] port - DSP Gigabit Ethernet port number + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_init_gbe_port(uint32_t port); + + +/*------------ TA66XX_BC_get_gbe_port_info() function --------------------*//** + * @brief Function returns Gigabit Ethernet port info: port mode, MAC address, + * link status + * + * @param[in] port - Gigabit Ethernet port number for which port info should + * be returned + * @param[out] port_dd - pointer to a buffer to which Gigabit Ethernet port + * data descriptor should be returned + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t TA66XX_BC_get_gbe_port_info(uint32_t port, TA66XX_BC_GBE_PORT_DD *port_dd); + + +/** @}*/ +//============================================================================= + + + +#ifdef __cplusplus +} +#endif + + + +//============================================================================= +#endif /* __TA66XX_BC_DSP_BC_FUNCTIONS_HXX__ */ diff --git a/ports/c667x/ccs/example_build/include/TA66XX_OSAL.h b/ports/c667x/ccs/example_build/include/TA66XX_OSAL.h new file mode 100644 index 00000000..d61af0e9 --- /dev/null +++ b/ports/c667x/ccs/example_build/include/TA66XX_OSAL.h @@ -0,0 +1,649 @@ +/****************************************************************************** + TORNADO AMC modules Software Development Kit (SDK). Rev 3A. + TI SYS/BIOS RTOS abstraction layer for TORNADO AMC embedded controllers. + (C) MicroLAB Systems, 2014-2015 + + + File: This file contains TI SYS/BIOS RTOS abstraction layer definitions + ----- for TORNADO AMC embedded controllers, which is used for various + low-level drivers (LLD) and libraries that the application use. + + + Revision history: + ----------------- + rev.1A - 2014, initial release for TORNADO-A6678 board + rev.2A - 2015, totally redesigned SDK; + rev.3A - 2016, added support for TORNADO-A6678/FMC board rev.1A; + +******************************************************************************/ + + +/** + * @file TA66XX_OSAL.h + * + * @brief RTOS abstraction layer definitions + * + * This file contains TI SYS/BIOS RTOS abstraction layer (OSAL) definitions for + * TORNADO AMC embedded controllers, which is used for various + * low-level drivers (LLD) and libraries that the application use. + * + */ + + +#ifndef __TA66XX_OSAL_H__ // check for this file has been already included +#define __TA66XX_OSAL_H__ 1 + + + +#ifdef __cplusplus +extern "C" { +#endif + + + +//============================================================================= +//------------ Definitions ---------------------------------------------------- +//============================================================================= +/** @addtogroup TA66XX_OSAL_GENERAL OS abstraction layer (OSAL) general definitions + * @{ + */ + +// Hardware semaphore defs +#define TA66XX_OSAL_CPPI_HW_SEM 1 /**< CPPI LLD hardware semaphore */ +#define TA66XX_OSAL_QMSS_HW_SEM 2 /**< QMSS LLD hardware semaphore */ +#define TA66XX_OSAL_SRIO_HW_SEM 3 /**< SRIO LLD hardware semaphore */ +#define TA66XX_OSAL_SPI_HW_SEM 4 /**< SPI driver hardware semaphore */ + +/** Macro to define high-priority QMSS queue for accumulator (depends on DSP event ID and core number) */ +#define TA66XX_OSAL_set_qmss_queue_acc(eventid, core) (704 + (eventid - 48) * 8 + core) + +// Interrupts and event IDs used by NIMU library (DSP core 0 is assumed to be used) +#define TA66XX_OSAL_ETHERNET_AMC_EVENTID 48 /**< Ethernet AMC port event - used by NIMU library */ +#define TA66XX_OSAL_ETHERNET_AMC_INTERRUPT 7 /**< Ethernet AMC port interrupt - used by NIMU library */ +/** QMSS queue for AMC Ethernet port accumulator (depends on TA66XX_OSAL_ETHERNET_AMC_EVENTID) */ +#define TA66XX_OSAL_ETHERNET_AMC_QMSS_QUEUE_ACC TA66XX_OSAL_set_qmss_queue_acc(TA66XX_OSAL_ETHERNET_AMC_EVENTID, 0) +#define TA66XX_OSAL_ETHERNET_PHY_EVENTID 49 /**< Ethernet PHY port event - used by NIMU library */ +#define TA66XX_OSAL_ETHERNET_PHY_INTERRUPT 8 /**< Ethernet PHY port interrupt - used by NIMU library */ +/** QMSS queue for PHY Ethernet port accumulator (depends on TA66XX_OSAL_ETHERNET_PHY_EVENTID) */ +#define TA66XX_OSAL_ETHERNET_PHY_QMSS_QUEUE_ACC TA66XX_OSAL_set_qmss_queue_acc(TA66XX_OSAL_ETHERNET_PHY_EVENTID, 0) + +// Interrupts and event IDs used by SRIO (DSP core 0 is assumed to be used) +#define TA66XX_OSAL_SRIO_MESSAGES_EVENTID 50 /**< SRIO event ID used by messages (Type 9 and Type 11) */ +#define TA66XX_OSAL_SRIO_INTERRUPT 9 /**< SRIO interrupt */ +/** QMSS queue for SRIO accumulator (depends on TA66XX_OSAL_SRIO_MESSAGES_EVENTID) */ +#define TA66XX_OSAL_SRIO_QMSS_QUEUE_ACC TA66XX_OSAL_set_qmss_queue_acc(TA66XX_OSAL_SRIO_MESSAGES_EVENTID, 0) +#define TA66XX_OSAL_SRIO_DIO_EVENTID 20 /**< SRIO event ID used by DirectIO (INTDST(n + 16), n - core number) */ +/** @}*/ +//============================================================================= + + + +//============================================================================= +//------------ Global variables ----------------------------------------------- +//============================================================================= +extern uint32_t qmssMallocCounter; +extern uint32_t qmssFreeCounter; +extern uint32_t cppiMallocCounter; +extern uint32_t cppiFreeCounter; +extern uint32_t srioMallocCounter; +extern uint32_t srioFreeCounter; +extern uint32_t srioDataBufferMallocCounter; +extern uint32_t srioDataBufferFreeCounter; +//============================================================================= + + + +//============================================================================= +//============ T-AMC controllers OSAL functions declarations ================== +//============================================================================= +/** @addtogroup TA66XX_OSAL_FUNCTIONS TORNADO AMC OSAL functions + * @{ + */ + + +//============================================================================= +//============ QMSS LLD OSAL functions ======================================== +//============================================================================= + +/*------------ Osal_qmssBeginMemAccess() function ------------------------*//** + * @brief Function is used to indicate that a block of memory is about to be + * accessed + * + * If the memory block is cached then this indicates that the application + * would need to ensure that the cache is updated with the data from the actual + * memory + * + * @param[in] ptr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_qmssBeginMemAccess(void *ptr, uint32_t size); + + +/*------------ Osal_qmssEndMemAccess() function --------------------------*//** + * @brief Function is used to indicate that the block of memory has finished + * being accessed + * + * If the memory block is cached then the application would need to ensure that + * the contents of the cache are updated immediately to the actual memory. + * + * @param[in] ptr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_qmssEndMemAccess(void *ptr, uint32_t size); + + +/*------------ Osal_qmssMalloc() function --------------------------------*//** + * @brief Function implements the memory allocation library function + * + * This function allocates a memory block of a given size specified by input + * parameter 'num_bytes'. + * + * @param[in] num_bytes - number of bytes to be allocated + * + * @return Allocated block address + * +-----------------------------------------------------------------------------*/ +Ptr Osal_qmssMalloc(uint32_t num_bytes); + + +/*------------ Osal_qmssFree() function ----------------------------------*//** + * @brief Function implements the memory free library function + * + * This function frees up memory allocated using Osal_qmssMalloc() + * function call. + * + * @param[in] dataPtr - pointer to the memory block to be cleaned up + * @param[in] num_bytes - size of the memory block to be cleaned up in bytes + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_qmssFree(Ptr dataPtr, uint32_t num_bytes); + + +/*------------ Osal_qmssCsEnter() function -------------------------------*//** + * @brief Function is used to enter a critical section + * + * Function protects against access from multiple cores and access from + * multiple threads on single core + * + * @return Handle used to lock critical section + * +-----------------------------------------------------------------------------*/ +void *Osal_qmssCsEnter(void); + + +/*------------ Osal_qmssCsExit() function --------------------------------*//** + * @brief Function is used to exit a critical section protected using + * Osal_qmssCsEnter() API. + * + * @param[in] CsHandle - handle for unlocking critical section + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_qmssCsExit(void *CsHandle); + +//============================================================================= + + + +//============================================================================= +//============ CPPI LLD OSAL functions ======================================== +//============================================================================= + +/*------------ Osal_cppiBeginMemAccess() function ------------------------*//** + * @brief Function is used to indicate that a block of memory is about to be + * accessed + * + * If the memory block is cached then this indicates that the application + * would need to ensure that the cache is updated with the data from the actual + * memory + * + * @param[in] ptr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_cppiBeginMemAccess(void *ptr, uint32_t size); + + +/*------------ Osal_cppiEndMemAccess() function --------------------------*//** + * @brief Function is used to indicate that the block of memory has finished + * being accessed + * + * If the memory block is cached then the application would need to ensure that + * the contents of the cache are updated immediately to the actual memory. + * + * @param[in] ptr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_cppiEndMemAccess(void *ptr, uint32_t size); + + +/*------------ Osal_cppiMalloc() function --------------------------------*//** + * @brief Function implements the memory allocation library function + * + * This function allocates a memory block of a given size specified by input + * parameter 'num_bytes'. + * + * @param[in] num_bytes - number of bytes to be allocated + * + * @return Allocated block address + * +-----------------------------------------------------------------------------*/ +Ptr Osal_cppiMalloc(uint32_t num_bytes); + + +/*------------ Osal_cppiFree() function ----------------------------------*//** + * @brief Function implements the memory free library function + * + * This function frees up memory allocated using Osal_cppiMalloc() + * function call. + * + * @param[in] dataPtr - pointer to the memory block to be cleaned up + * @param[in] num_bytes - size of the memory block to be cleaned up in bytes + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_cppiFree(Ptr dataPtr, uint32_t num_bytes); + + +/*------------ Osal_cppiCsEnter() function -------------------------------*//** + * @brief Function is used to enter a critical section + * + * Function protects against access from multiple cores and access from + * multiple threads on single core + * + * @return Handle used to lock critical section + * +-----------------------------------------------------------------------------*/ +void *Osal_cppiCsEnter(void); + + +/*------------ Osal_cppiCsExit() function --------------------------------*//** + * @brief Function is used to exit a critical section protected using + * Osal_cppiCsEnter() API. + * + * @param[in] CsHandle - handle for unlocking critical section + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_cppiCsExit(void *CsHandle); + +//============================================================================= + + +#ifdef __TA66XX_FUNCTIONS_INCLUDE_SRIO__ + + +//============================================================================= +//============ SRIO LLD OSAL functions ======================================== +//============================================================================= + +/*------------ Osal_srioBeginMemAccess() function ------------------------*//** + * @brief Function is used to indicate that a block of memory is about to be + * accessed + * + * If the memory block is cached then this indicates that the application + * would need to ensure that the cache is updated with the data from the actual + * memory + * + * @param[in] ptr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioBeginMemAccess(void *ptr, uint32_t size); + + +/*------------ Osal_srioEndMemAccess() function --------------------------*//** + * @brief Function is used to indicate that the block of memory has finished + * being accessed + * + * If the memory block is cached then the application would need to ensure that + * the contents of the cache are updated immediately to the actual memory. + * + * @param[in] ptr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioEndMemAccess(void *ptr, uint32_t size); + + +/*------------ Osal_srioBeginDescriptorAccess() function -----------------*//** + * @brief Function is invoked by the SRIO LLD to indicate that a descriptor is + * being accessed. + * + * @param[in] drvHandle - driver instance for which descriptor is being + * accessed + * @param[in] ptr - pointer to the descriptor being accessed + * @param[in] descSize - size of the descriptor (valid only for driver managed + * configuration) + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioBeginDescriptorAccess(Srio_DrvHandle drvHandle, void *ptr, uint32_t descSize); + + +/*------------ Osal_srioEndDescriptorAccess() function -------------------*//** + * @brief Function is invoked by the SRIO LLD to indicate that a descriptor is + * finished being accessed. + * + * @param[in] drvHandle - driver instance for which descriptor is being + * accessed + * @param[in] ptr - pointer to the descriptor being accessed + * @param[in] descSize - size of the descriptor (valid only for driver managed + * configuration) + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioEndDescriptorAccess(Srio_DrvHandle drvHandle, void *ptr, uint32_t descSize); + + +/*------------ Osal_srioMalloc() function --------------------------------*//** + * @brief Function implements the memory allocation library function + * + * This function allocates a memory block of a given size specified by input + * parameter 'num_bytes'. + * + * @param[in] num_bytes - number of bytes to be allocated + * + * @return Allocated block address + * +-----------------------------------------------------------------------------*/ +Ptr Osal_srioMalloc(uint32_t num_bytes); + + +/*------------ Osal_srioFree() function ----------------------------------*//** + * @brief Function implements the memory free library function + * + * This function frees up memory allocated using Osal_srioMalloc() + * function call. + * + * @param[in] dataPtr - pointer to the memory block to be cleaned up + * @param[in] num_bytes - size of the memory block to be cleaned up in bytes + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioFree(Ptr dataPtr, uint32_t num_bytes); + + +/*------------ Osal_dataBufferInitMemory() function ----------------------*//** + * @brief Function is used to allocate a block of memory for all the data + * buffer operations. This function is called by the application. + * + * @param[in] dataBufferSize - size of each data buffer + * + * @return Error code + * +-----------------------------------------------------------------------------*/ +int32_t Osal_dataBufferInitMemory(uint32_t dataBufferSize); + + +/*------------ Osal_srioDataBufferMalloc() function ----------------------*//** + * @brief Function is used to allocate a data buffer of the specified size. + * Data buffers should always be allocated from the global address space. + * + * @param[in] numBytes - number of bytes to be allocated + * + * @return Allocated block address + * +-----------------------------------------------------------------------------*/ +void *Osal_srioDataBufferMalloc(uint32_t numBytes); + + +/*------------ Osal_srioDataBufferFree() function ------------------------*//** + * @brief Function is used to clean up a previously allocated data buffer + * block. All data buffers are in the global address space. + * + * @param[in] ptr - pointer to the memory block to be cleaned up + * @param[in] numBytes - size of the memory block to be cleaned up in bytes + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioDataBufferFree(void *ptr, uint32_t numBytes); + + +/*------------ Osal_srioLog() function -----------------------------------*//** + * @brief Function is used to log the messages from SRIO LLD on the console. + * + * @param[in] fmt - formatted string + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioLog(String fmt, ... ); + + +/*------------ Osal_srioCreateSem() function -----------------------------*//** + * @brief Function is used to create a critical section. + * + * @return Semaphore handle created + * +-----------------------------------------------------------------------------*/ +void *Osal_srioCreateSem(void); + + +/*------------ Osal_srioDeleteSem() function -----------------------------*//** + * @brief Function is used to delete a critical section. + * + * @param[in] semHandle - semaphore handle to be deleted + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioDeleteSem(void *semHandle); + + +/*------------ Osal_srioPendSem() function -------------------------------*//** + * @brief Function is used to pend on a semaphore + * + * @param[in] semHandle - semaphore handle on which the API will pend + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioPendSem(void *semHandle); + + +/*------------ Osal_srioPostSem() function -------------------------------*//** + * @brief Function is used to post a semaphore + * + * @param[in] semHandle - semaphore handle which will be posted + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioPostSem(void *semHandle); + + +/*------------ Osal_srioEnterMultipleCoreCriticalSection() function ------*//** + * @brief Function is used to protect the driver shared resources across + * multiple cores. + * + * @return Handle used to lock critical section + * +-----------------------------------------------------------------------------*/ +void *Osal_srioEnterMultipleCoreCriticalSection(void); + + +/*------------ Osal_srioExitMultipleCoreCriticalSection() function -------*//** + * @brief Function is called to end the critical section which was protecting + * shared resources from access across multiple cores. + * + * @param[in] critSectHandle - handle for unlocking critical section + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioExitMultipleCoreCriticalSection(void *critSectHandle); + + +/*------------ Osal_srioEnterSingleCoreCriticalSection() function --------*//** + * @brief Function is used to provide critical section to prevent access of + * shared resources from single core and multiple threads. + * + * @param[in] drvHandle - driver handle which needs critical section to + * protect its resources + * + * @return Handle used to lock critical section + * +-----------------------------------------------------------------------------*/ +void *Osal_srioEnterSingleCoreCriticalSection(Srio_DrvHandle drvHandle); + + +/*------------ Osal_srioExitSingleCoreCriticalSection() function ---------*//** + * @brief Function is called to end the critical section access of shared + * resources from single cores. + * + * @param[in] drvHandle - driver handle which needs critical section to + * protect its resources + * @param[in] critSectHandle - critical handle retreived by + * Osal_srioEnterSingleCoreCriticalSection() function call + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_srioExitSingleCoreCriticalSection(Srio_DrvHandle drvHandle, void *critSectHandle); + +//============================================================================= + + +#endif /* __TA66XX_FUNCTIONS_INCLUDE_SRIO__ */ + + +//============================================================================= +//============ NIMU LLD OSAL functions ======================================== +//============================================================================= + +/*------------ Osal_nimuMalloc() function --------------------------------*//** + * @brief Function implements the memory allocate function for the NIMU + * library. + * + * This function allocates a memory block of a given size specified by input + * parameter 'num_bytes'. + * + * @param[in] num_bytes - number of bytes to be allocated + * @param[in] alignment - alignment of allocated memory block in bytes + * + * @return Allocated block address + * +-----------------------------------------------------------------------------*/ +Ptr Osal_nimuMalloc(uint32_t num_bytes, uint32_t alignment); + + +/*------------ Osal_nimuFree() function ----------------------------------*//** + * @brief Function implements the memory free function for the NIMU library. + * + * This function frees up memory allocated using Osal_nimuMalloc() + * function call. + * + * @param[in] dataPtr - pointer to the memory block to be cleaned up + * @param[in] num_bytes - size of the memory block to be cleaned up in bytes + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_nimuFree(Ptr dataPtr, uint32_t num_bytes); + +//============================================================================= + + + +//============================================================================= +//============ PASS LLD OSAL functions ======================================== +//============================================================================= + + +/*------------ Osal_paBeginMemAccess() function --------------------------*//** + * @brief Function is used to indicate that a block of memory is about to be + * accessed + * + * If the memory block is cached then this indicates that the application + * would need to ensure that the cache is updated with the data from the actual + * memory + * + * @param[in] addr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_paBeginMemAccess(Ptr addr, uint32_t size); + + +/*------------ Osal_paEndMemAccess() function ----------------------------*//** + * @brief Function is used to indicate that the block of memory has finished + * being accessed + * + * If the memory block is cached then the application would need to ensure that + * the contents of the cache are updated immediately to the actual memory. + * + * @param[in] addr - address of memory block + * @param[in] size - size of memory block + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_paEndMemAccess(Ptr addr, uint32_t size); + + +/*------------ Osal_paMtCsEnter() function -------------------------------*//** + * @brief Function is used to enter a critical section + * + * Function protects against access from multiple cores and access from + * multiple threads on single core + * + * @param[out] key - pointer to a variable to receive a handle for unlocking + * critical section + + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_paMtCsEnter(uint32_t *key); + + +/*------------ Osal_paMtCsExit() function --------------------------------*//** + * @brief Function is used to exit a critical section protected using + * Osal_paMtCsEnter() API. + * + * @param[in] key - handle for unlocking critical section + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_paMtCsExit(uint32_t key); + +/** @}*/ +//============================================================================= + + + +#ifdef __cplusplus +} +#endif + + + +//============================================================================= +#endif /* __TA66XX_OSAL_H__ */ diff --git a/ports/c667x/ccs/example_build/include/TASDK_ERR.h b/ports/c667x/ccs/example_build/include/TASDK_ERR.h new file mode 100644 index 00000000..8245e95b --- /dev/null +++ b/ports/c667x/ccs/example_build/include/TASDK_ERR.h @@ -0,0 +1,87 @@ +/****************************************************************************** + TORNADO AMC modules Software Development Kit (SDK). Rev 4A. + (C) MicroLAB Systems, 2015-2017 + + + File: TORNADO AMC SDK functions errors + ----- + +******************************************************************************/ + + +/** + * @file TASDK_ERR.h + * + * @brief SDK functions errors + * + * This file contains TORNADO AMC SDK functions errors + * + */ + + +#ifndef __TASDK_ERR_H__ // check for this file has been already included +#define __TASDK_ERR_H__ 1 + + +//============================================================================= +//============ Returned error codes =========================================== +//============================================================================= +/** @addtogroup TASDK_ERRORS SDK API functions returned error codes + * @{ + */ +#define TASDK_OK 0 /**< No errors */ +#define TASDK_PARAM_ERR -100 /**< Erroneous function parameter */ +#define TASDK_INVALID_HW_ERR -101 /**< Invalid H/W error (invalid board, etc.) */ +#define TASDK_HW_ERR -102 /**< H/W error (error writing to the DSP control registers, etc) */ +#define TASDK_SYS_CALL_ERR -103 /**< system API call error */ +#define TASDK_INVALID_DSP_CORE_ERR -104 /**< Only DSP core 0 may call the function */ +#define TASDK_INVALID_DSP_CORE_BOOT_ADDR_ERR -105 /**< Invalid DSP core boot address */ +#define TASDK_API_OPEN_ERR -106 /**< API has not been open */ +#define TASDK_MMC_TO_CPU_COMM_CHECKSUM_ERR -150 /**< Invalid data frame checksum */ +#define TASDK_MMC_TO_CPU_COMM_DATA_BUF_LEN_ERR -151 /**< Data buffer is not large enough to store received data frame */ +#define TASDK_MMC_TO_CPU_COMM_INV_CMD_ERR -152 /**< Invalid command */ +#define TASDK_MMC_TO_CPU_COMM_RECV_DATA_LEN_ERR -153 /**< Invalid received data length */ +#define TASDK_MMC_TO_CPU_COMM_RECV_DATA_INV_ERR -154 /**< Received data is invalid */ +#define TASDK_MMC_TO_CPU_COMM_TIMEOUT_ERR -155 /**< MMC-to-DSP communication timeout error */ +#define TASDK_SFP_NOT_INSTALLED_ERR -156 /**< SFP module is not installed */ +#define TASDK_FMC_NOT_INSTALLED_ERR -157 /**< FMC module is not installed */ +#define TASDK_FMC_INFO_INVALID_ERR -158 /**< FMC module info is invalid */ +#define TASDK_FLASH_INV_DEV_ERR -200 /**< unsupported FLASH device */ +#define TASDK_FLASH_ERASE_ERR -201 /**< FLASH erase error */ +#define TASDK_FLASH_WR_ERR -202 /**< FLASH write error */ +#define TASDK_FLASH_CANNOT_WR_ERR -203 /**< FLASH contents does not allow to write this data */ +#define TASDK_FLASH_INV_RD_ERR -204 /**< invalid FLASH read data during AUTO-SELECT */ +#define TASDK_FLASH_INFO_NOT_MATCH_ERR -205 /**< FLASH info from the FLASH chip does not match FLASH_LEN_ID from System Configuration register */ +#define TASDK_FLASH_SECTOR_WRPROT_ERR -206 /**< FLASH sector is write-protected */ +#define TASDK_FLASH_WR_BUF_ABORT_ERR -207 /**< FLASH write-to-buffer program is aborted */ +#define TASDK_FLASH_HW_WP_ERR -208 /**< FLASH writes are disabled by on-board switch */ +#define TASDK_FLASH_WR_DISABLED_ERR -209 /**< FLASH writes are disabled by application */ +#define TASDK_FPGA_CNF_BITFILE_HD_FORMAT_ERR -500 /**< invalid FPGA bitfile header format */ +#define TASDK_FPGA_CNF_LOAD_ERR -501 /**< error during FPGA configuration */ +#define TASDK_FPGA_CNF_CRC_ERR -502 /**< CRC check failed during FPGA configuration */ +#define TASDK_FPGA_CNF_LOAD_LEN_ERR -503 /**< not all the data has been loaded */ +#define TASDK_FPGA_CNF_BITFILE_INV_PART_ERR -504 /**< invalid FPGA bitfile header part name */ +#define TASDK_FPGA_CNF_INV_IF_ERR -505 /**< invalid FPGA configuration interface selected */ +#define TASDK_FLASH_RECORD_GLOBAL_HD_NOT_VALID_ERR -600 /**< FLASH record global header is invalid */ +#define TASDK_FLASH_RECORD_HD_NOT_VALID_ERR -601 /**< FLASH record header is invalid */ +#define TASDK_FLASH_RECORD_HD_LIST_NOT_VALID_ERR -602 /**< FLASH record header list is invalid */ +#define TASDK_FLASH_RECORD_FREE_SPACE_ERR -603 /**< not available free space in FLASH */ +#define TASDK_FLASH_RECORD_CHECKSUM_ERR -604 /**< FLASH record checksum mismatch */ +#define TASDK_FLASH_RECORD_ALREADY_OPENED_ERR -605 /**< another FLASH record is opened for writing */ +#define TASDK_FLASH_RECORD_INVALID_LOAD_ADDR_ERR -606 /**< invalid FLASH record load address */ +#define TASDK_FLASH_RECORD_INV_NUMBER_ERR -607 /**< invalid FLASH record number */ +#define TASDK_FLASH_BOOT_SEQ_NOT_VALID_ERR -608 /**< FLASH boot sequence is invalid */ +#define ELF_LOADER_BASE_ERR -1000 /**< ELF file loader base error */ +#define ELF_LOADER_PARAM_ERR (ELF_LOADER_BASE_ERR) /**< erroneous function parameter */ +#define ELF_LOADER_INV_ELF_HEADER_ERR (ELF_LOADER_BASE_ERR - 1) /**< invalid ELF header */ +#define ELF_LOADER_INV_FILE_TYPE_ERR (ELF_LOADER_BASE_ERR - 2) /**< invalid file type (non-executable) */ +#define ELF_LOADER_INV_ENTRY_POINT_ERR (ELF_LOADER_BASE_ERR - 3) /**< invalid entry-point address */ +#define ELF_LOADER_INV_SEGMENT_ERR (ELF_LOADER_BASE_ERR - 4) /**< invalid or missing segment data */ +/** @}*/ +//============================================================================= + + + +//============================================================================= +#endif /* __TASDK_ERR_H__ */ + diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.ccsproject b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.ccsproject new file mode 100644 index 00000000..9c03abfb --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.ccsproject @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.cproject b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.cproject new file mode 100644 index 00000000..f4a158fb --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.cproject @@ -0,0 +1,167 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.project b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.project new file mode 100644 index 00000000..b18fc136 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.project @@ -0,0 +1,89 @@ + + + sample_threadx_c6678evm + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -k + + + org.eclipse.cdt.make.core.buildCommand + ${CCS_UTILS_DIR}/bin/gmake + + + org.eclipse.cdt.make.core.buildLocation + ${BuildDirectory} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + true + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + false + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + ORIGINAL_PROJECT_ROOT + file:/C:/release/threadx/sample_threadx_c6678evm + + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.cdt.codan.core.prefs b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 00000000..f653028c --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.cdt.debug.core.prefs b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 00000000..2adc7b1d --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.core.resources.prefs b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..093dbb95 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,6 @@ +eclipse.preferences.version=1 +encoding//Debug/makefile=UTF-8 +encoding//Debug/objects.mk=UTF-8 +encoding//Debug/sources.mk=UTF-8 +encoding//Debug/subdir_rules.mk=UTF-8 +encoding//Debug/subdir_vars.mk=UTF-8 diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.c b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.c new file mode 100644 index 00000000..31e8056b --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.c @@ -0,0 +1,441 @@ +/* + * board_setup.c + * + */ + + +#include "board_setup.h" +#include "C66XX.h" +#include + + +//============================================================================= +//============ General definitions ============================================ +//============================================================================= +// DSP Timer-8 definition +#define C66XX_DSP_TIMER C66XX_TIMER_8 +// DSP Timer-8 output frequency in Hz +#define C66XX_DSP_TIMER_FREQ 100 +/* DSP Timer-8 interrupt event ID */ +#define C66XX_DSP_TIMER_EVENT_ID 67 +//============================================================================= + + +//============================================================================= +//============ Global functions =============================================== +//============================================================================= +void _tx_nmi_vector(void); +void _tx_int4_vector(void); +void _tx_int5_vector(void); +void _tx_int6_vector(void); +void _tx_int7_vector(void); +void _tx_int8_vector(void); +void _tx_int9_vector(void); +void _tx_int10_vector(void); +void _tx_int11_vector(void); +void _tx_int12_vector(void); +void _tx_int13_vector(void); +void _tx_int14_vector(void); +void _tx_int15_vector(void); +//============================================================================= + + +//============================================================================= +//============ Static functions =============================================== +//============================================================================= +static int32_t tx_timer_init(C66XX_TIMER timer, uint32_t frequency); +static int32_t tx_interrupt_init(void); +//============================================================================= + + +/*------------ init_output_timer() function ----------------------------------- + * DESCRIPTION: Function initializes Timer64 module + * ARGUMENTS: + * None + * RETURNED VALUE: Error code +-----------------------------------------------------------------------------*/ +static int32_t tx_timer_init(C66XX_TIMER timer, uint32_t frequency) +{ + int32_t r; + C66XX_TIMER_CFG_DD cfg_dd; + + // Reset 64-bit timer + if ((r = C66XX_TIMER_reset(timer, C66XX_TIMER_HW_CFG_64BIT)) != C66XX_OK) + goto exit; + + // Fill configuration data descriptor + memset(&cfg_dd, 0, C66XX_TIMER_CFG_DD_LEN); + cfg_dd.timer_mode = C66XX_TIMER_MODE_32BIT_UNCHAINED; + cfg_dd.timer_high.clk_src_output_mode = C66XX_TIMER_CLK_OUTPUT_MODE_CLK; + // Init DSP Timer64 module + if ((r = C66XX_TIMER_init(timer, frequency, &cfg_dd)) != C66XX_OK) + goto exit; + + // Enable timer interrupt + if ((r = C66XX_TIMER_enable_interrupts(timer, C66XX_TIMER_HW_CFG_32BIT_HIGH)) != C66XX_OK) + goto exit; + + // Start 32-bit timer high to enable continuously + if ((r = C66XX_TIMER_start(timer, C66XX_TIMER_HW_CFG_32BIT_HIGH, C66XX_TIMER_COUNT_MODE_CONTINUOUSLY)) != C66XX_OK) + goto exit; + + // TIMER module configuration is completed + printf("Timer #%u configuration is completed\n", timer); + +exit: + return (r); +} +//----------------------------------------------------------------------------- + + +/*------------ tx_interrupt_init() function ----------------------------------- + * DESCRIPTION: Function initializes CorePack interrupt module + * ARGUMENTS: + * None + * RETURNED VALUE: Error code +-----------------------------------------------------------------------------*/ +static int32_t tx_interrupt_init(void) +{ + int32_t r; + + // Set DSP interrupt handlers to the ones defined in tx_initialize_low_level.asm + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_NMI, _tx_nmi_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_4, _tx_int4_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_5, _tx_int5_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_6, _tx_int6_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_7, _tx_int7_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_8, _tx_int8_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_9, _tx_int9_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_10, _tx_int10_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_11, _tx_int11_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_12, _tx_int12_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_13, _tx_int13_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_14, _tx_int14_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_15, _tx_int15_vector)) != C66XX_OK) + goto exit; + + /* CorePack interrupt module configuration is completed */ + printf("INTC configuration is completed\n"); + // Exit without errors + r = C66XX_OK; + +exit: + return (r); +} +//----------------------------------------------------------------------------- + + +/*------------ hardware_setup() function -------------------------------------- + * DESCRIPTION: Function intializes board hardware + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +int hardware_setup() +{ + platform_init_flags init_flags; + platform_init_config init_config; + platform_info p_info; + int32_t r; + + /* + * Initialize all platform peripherals with default values: + * PLL, DDR, TCSL, PHY, ECC + */ + init_flags.pll = 1; + init_flags.ddr = 1; + init_flags.tcsl = 1; + init_flags.phy = 1; + init_flags.ecc = 0; + memset(&init_config, 0, sizeof(platform_init_config)); + if ((r = platform_init(&init_flags, &init_config)) != Platform_EOK) + goto exit; + + /* Initialize platform UART */ + if ((r = platform_uart_init()) != Platform_EOK) + goto exit; + if ((r = platform_uart_set_baudrate(115200)) != Platform_EOK) + goto exit; + + /* Get platform info */ + platform_get_info(&p_info); + /* Write data to the UART */ + platform_write("Platform library version is %s\n", p_info.version); + platform_write("Board name is %s\n", p_info.board_name); + platform_write("Board serial number is %s\n", p_info.serial_nbr); + platform_write("Board revision ID is %u\n", p_info.board_rev); + platform_write("CPU name is %s\n", p_info.cpu.name); + platform_write("CPU revision ID is %u\n", p_info.cpu.revision_id); + platform_write("Number of CPU cores is %u\n", p_info.cpu.core_count); + platform_write("CPU frequency is %u MHz\n", p_info.frequency); + + // Init CorePac INTC + if ((r = C66XX_INT_init_core()) != C66XX_OK) + goto exit; + + // Init DSP Timer + if ((r = tx_timer_init(C66XX_DSP_TIMER, C66XX_DSP_TIMER_FREQ)) != C66XX_OK) + goto exit; + + // Init DSP interrupt controller + if ((r = tx_interrupt_init()) != C66XX_OK) + goto exit; + + printf("Board is initialized\n"); + /* Exit with no errors */ + +exit: + return (r); +} +//----------------------------------------------------------------------------- + + +/*------------ tx_nmi_handler() function -------------------------------------- + * DESCRIPTION: Function handles NMI interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_nmi_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int4_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT4 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int4_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int5_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT5 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int5_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int6_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT6 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int6_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int7_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT7 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int7_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int8_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT8 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int8_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int9_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT9 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int9_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int10_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT10 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int10_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int11_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT11 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int11_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int12_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT12 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int12_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int13_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT13 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int13_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int14_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT14 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int14_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int15_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT15 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int15_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +//============================================================================= +//============ Platform OSAL functions ======================================== +//============================================================================= + +/*------------ Osal_platformMalloc() function ----------------------------*//** + * @brief Function implements the memory allocate function for the platform + * library. + * + * This function allocates a memory block of a given size specified by input + * parameter 'num_bytes'. + * + * @param[in] num_bytes - number of bytes to be allocated + * @param[in] alignment - alignment of allocated memory block in bytes + * + * @return Allocated block address + * +-----------------------------------------------------------------------------*/ +uint8_t *Osal_platformMalloc(uint32_t num_bytes, uint32_t alignment) +{ + // Allocate memory from default system heap + return (NULL); +} +//----------------------------------------------------------------------------- + + +/*------------ Osal_platformFree() function ------------------------------*//** + * @brief Function implements the memory free function for the platform + * library. + * + * This function frees up memory allocated using Osal_platformMalloc() + * function call. + * + * @param[in] mem_ptr - pointer to the memory block to be cleaned up + * @param[in] num_bytes - size of the memory block to be cleaned up in bytes + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_platformFree(uint8_t *mem_ptr, uint32_t num_bytes) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ Osal_platformSpiCsEnter() function ------------------------*//** + * @brief Function is used to enter a critical section + * + * Function protects against access from multiple cores and access from + * multiple threads on single core + * + * @param[out] key - pointer to a variable to receive a handle for unlocking + * critical section + + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_platformSpiCsEnter(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ Osal_platformSpiCsExit() function -------------------------*//** + * @brief Function is used to exit a critical section protected using + * Osal_paMtCsEnter() API. + * + * @param[in] key - handle for unlocking critical section + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_platformSpiCsExit(void) +{ +} +//----------------------------------------------------------------------------- + + +//============================================================================= + + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.h b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.h new file mode 100644 index 00000000..9e252dcd --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/board_setup.h @@ -0,0 +1,209 @@ +/* + * board_setup.h + * + */ + + +#ifndef BOARD_SETUP_H /* check for this file has been already included */ +#define BOARD_SETUP_H 1 + + +#include "ti\platform\platform.h" + + +/*===========================================================================*/ +/*============ Printf output definitions ====================================*/ +/*===========================================================================*/ +#define printf platform_write +/*===========================================================================*/ + + +/*------------ hardware_setup() function -------------------------------------- + * DESCRIPTION: Function intializes board hardware + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +int hardware_setup(); + + +/*------------ tx_nmi_handler() function -------------------------------------- + * DESCRIPTION: Function handles NMI interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_nmi_handler(void); + + +/*------------ tx_int4_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT4 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int4_handler(void); + + +/*------------ tx_int5_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT5 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int5_handler(void); + + +/*------------ tx_int6_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT6 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int6_handler(void); + + +/*------------ tx_int7_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT7 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int7_handler(void); + + +/*------------ tx_int8_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT8 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int8_handler(void); + + +/*------------ tx_int9_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT9 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int9_handler(void); + + +/*------------ tx_int10_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT10 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int10_handler(void); + + +/*------------ tx_int11_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT11 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int11_handler(void); + + +/*------------ tx_int12_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT12 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int12_handler(void); + + +/*------------ tx_int13_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT13 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int13_handler(void); + + +/*------------ tx_int14_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT14 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int14_handler(void); + + +/*------------ tx_int15_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT15 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int15_handler(void); + + +/*------------ Osal_platformMalloc() function ----------------------------*//** + * @brief Function implements the memory allocate function for the platform + * library. + * + * This function allocates a memory block of a given size specified by input + * parameter 'num_bytes'. + * + * @param[in] num_bytes - number of bytes to be allocated + * @param[in] alignment - alignment of allocated memory block in bytes + * + * @return Allocated block address + * +-----------------------------------------------------------------------------*/ +uint8_t *Osal_platformMalloc(uint32_t num_bytes, uint32_t alignment); + + +/*------------ Osal_platformFree() function ------------------------------*//** + * @brief Function implements the memory free function for the platform + * library. + * + * This function frees up memory allocated using Osal_platformMalloc() + * function call. + * + * @param[in] mem_ptr - pointer to the memory block to be cleaned up + * @param[in] num_bytes - size of the memory block to be cleaned up in bytes + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_platformFree(uint8_t *mem_ptr, uint32_t num_bytes); + + +/*------------ Osal_platformSpiCsEnter() function ------------------------*//** + * @brief Function is used to enter a critical section + * + * Function protects against access from multiple cores and access from + * multiple threads on single core + * + * @param[out] key - pointer to a variable to receive a handle for unlocking + * critical section + + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_platformSpiCsEnter(void); + + +/*------------ Osal_platformSpiCsExit() function -------------------------*//** + * @brief Function is used to exit a critical section protected using + * Osal_paMtCsEnter() API. + * + * @param[in] key - handle for unlocking critical section + * + * @return None + * +-----------------------------------------------------------------------------*/ +void Osal_platformSpiCsExit(void); + + +/*===========================================================================*/ +#endif /* BOARD_SETUP_H */ + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.c b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.c new file mode 100644 index 00000000..18bad8de --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.c @@ -0,0 +1,528 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include "board_setup.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define TraceX trace oblects */ +#define TRACE_BUFFER_SIZE (4 * 1024) +#define TRACE_OBJECTS_COUNT 20 +/* Define TraceX trace buffer */ +UCHAR tx_trace_buffer[TRACE_BUFFER_SIZE]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define demo timer */ +#define DEMO_TIMER_PERIOD 10 +#define DEMO_TIMER_VALUE 0xaaaaaaaa +TX_TIMER timer_0; +ULONG timer_0_counter; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); +void my_stack_error_handler(TX_THREAD *thread_ptr); +void my_timer_function(ULONG timer_input); + + +/* Define main entry point. */ + +void main() +{ + /* Setup the hardware. */ + hardware_setup(); + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; +UINT status; + + /* Enable event tracing using the global “trace_buffer” memory and supporting + a maximum of TRACE_OBJECTS_COUNT ThreadX objects in the registry. */ + if ((status = tx_trace_enable(tx_trace_buffer, TRACE_BUFFER_SIZE, TRACE_OBJECTS_COUNT)) != TX_SUCCESS) + { + while (1); + } + + /* Register thread stack error notification callback */ + if ((status = tx_thread_stack_error_notify(my_stack_error_handler)) != TX_SUCCESS) + { + while (1); + } + + /* Create a byte memory pool from which to allocate the thread stacks. */ + status = tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the main thread. */ + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 1. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 2. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 3. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + status = tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 4. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + status = tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 5. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 6. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + status = tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 7. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + status = tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the message queue. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the message queue shared by threads 1 and 2. */ + status = tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the semaphore used by threads 3 and 4. */ + status = tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the event flags group used by threads 1 and 5. */ + status = tx_event_flags_create(&event_flags_0, "event flags 0"); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + status = tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the memory for a small block pool. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create a block memory pool to allocate a message buffer from. */ + status = tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate a block and release the block memory. */ + status = tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Release the block back to the pool. */ + status = tx_block_release(pointer); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the periodic timer. */ + status = tx_timer_create(&timer_0, "timer 0", my_timer_function, (ULONG) DEMO_TIMER_VALUE, DEMO_TIMER_PERIOD, DEMO_TIMER_PERIOD, TX_AUTO_ACTIVATE); + if (status != TX_SUCCESS) + { + while (1); + } +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void my_stack_error_handler(TX_THREAD *thread_ptr) +{ + while(1); +} + + +void my_timer_function(ULONG timer_input) +{ + /* Increment the thread counter. */ + timer_0_counter++; + + if (timer_input != DEMO_TIMER_VALUE) + while(1); +} + diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.cmd b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.cmd new file mode 100644 index 00000000..a2267231 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/sample_threadx.cmd @@ -0,0 +1,55 @@ +-c +-heap 0x400 +-stack 0x1000 +-l C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\lib\ti.csl.ae66 +-l C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\lib\ti.csl.intc.ae66 +-l c:\ti\pdk_C6678_1_1_2_6\packages\ti\platform\evmc6678l\platform_lib\lib\release\ti.platform.evm6678l.ae66 + +/* Memory Map */ +MEMORY +{ + L1PSRAM (RWX) : org = 0x00E00000, len = 0x00008000 + L1DSRAM (RWX) : org = 0x00F00000, len = 0x00008000 + CODE_RAM (RWX) : org = 0x00800000, len = 0x00020000 + DATA_RAM (RWX) : org = 0x00820000, len = 0x00060000 + MSMCSRAM (RWX) : org = 0x0c000000, len = 0x00400000 + DDR3 (RWX) : org = 0x80000000, len = 0x80000000 +} + +SECTIONS +{ + .text > CODE_RAM + .stack > CODE_RAM + .cio > CODE_RAM + .const > CODE_RAM + .data > CODE_RAM + .switch > CODE_RAM + .sysmem > CODE_RAM + .far > CODE_RAM + .args > CODE_RAM + .ppinfo > CODE_RAM + .ppdata > CODE_RAM + .csl_vect > CODE_RAM + platform_lib > CODE_RAM + + GROUP + { + .neardata + .rodata + .bss + } > CODE_RAM + + /* COFF sections */ + .pinit > CODE_RAM + .cinit > CODE_RAM + + /* EABI sections */ + .binit > CODE_RAM + .init_array > CODE_RAM + .fardata > CODE_RAM + .c6xabi.exidx > CODE_RAM + .c6xabi.extab > CODE_RAM + + /* ThreadX section which should be the last RAM section loaded */ + .zend > DATA_RAM +} diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/TMS320C6678.ccxml b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/TMS320C6678.ccxml new file mode 100644 index 00000000..b7147d7f --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/TMS320C6678.ccxml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/readme.txt b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/readme.txt new file mode 100644 index 00000000..d783fef4 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/ports/c667x/ccs/example_build/sample_threadx_c6678evm/tx_initialize_low_level.asm b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/tx_initialize_low_level.asm new file mode 100644 index 00000000..cdc14f20 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_c6678evm/tx_initialize_low_level.asm @@ -0,0 +1,405 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; + +SP .set B15 +ADDRESS_MSK .set 0xFFFFFFF0 ; Ensure 16-byte alignment + +; Use Timer 8 as it's available for all DSP cores at C6678 +; Timer 8 interrupt high event (TINT8H) ID is 67 +; Assume DSP core clock 1000 MHz +; Timer is clocked at DSP core clock / 6 = 167 MHz +; Timer frequency will set to 100 Hz +TMR8_INTCTLSTAT_ADDR .set 0x02280044 ; Timer 8 Interrupt Control and Status Register +INTCTLSTAT_VAL .set 0x00010000 ; Enable TIMHI interrupt + +EVTCLR2_ADDR .set 0x01800048 ; Event Clear register 2 address +EVTCLR2_TMR8_VAL .set 0x00000008 ; Clear event 67 - TINT8H + +EVTMASK2_ADDR .set 0x01800088 ; Event Mask register 2 address +EVTMASK2_TMR8_VAL .set 0x00000008 ; Mask event 67 - TINT8H + +INTMUX1_ADDR .set 0x01800104 ; Interrupt Mux Register 1 address +INTMUX1_TMR8_VAL .set 0x43 ; Tie in Event 67 (TINT8H) to INT4 +; +; + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + + +; External interrupt handlers - should be defined by user + .global tx_nmi_handler + .global tx_int5_handler + .global tx_int6_handler + .global tx_int7_handler + .global tx_int8_handler + .global tx_int9_handler + .global tx_int10_handler + .global tx_int11_handler + .global tx_int12_handler + .global tx_int13_handler + .global tx_int14_handler + .global tx_int15_handler + +; +; +;/* Define the first available address in memory, which is typically just the last +; RAM section loaded. */ + .sect ".zend" + .space 20 + .global _tx_first_free_memory + .align 16 +_tx_first_free_memory: + .space 4 + +; Useful macro definitions +; Load 32-bit integer into register +MVK_LH .macro val,reg + MVKL val,reg + MVKH val,reg + .endm +; Interrupt entry - allocate stack space, save A0-A4 and B3 registers to stack, +; build return address in B3 register for context save function and +; call context save function +TX_INTERRUPT_ENTRY .macro + ADDK.S2 -288,SP + STW B3,*+SP(96) + STW A0,*+SP(20) + STW A1,*+SP(24) + STW A2,*+SP(28) + STW A3,*+SP(32) + STW A4,*+SP(36) + B _tx_thread_context_save + .endm +; Interrupt exit - jump to context restore function +TX_INTERRUPT_EXIT .macro + B _tx_thread_context_restore + NOP 5 + .endm + + + .sect ".text" +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level C667x/TI */ +;/* 6.0 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + .global _tx_initialize_low_level +_tx_initialize_low_level: +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (SP); +; + MVK_LH _tx_thread_system_stack_ptr,A0 ; Build address of system stack + STW SP,*A0 ; Save system stack address +; +; /* Pickup the first available memory address. */ +; + MVK_LH ADDRESS_MSK,A0 ; Build address mask + MVK_LH _tx_first_free_memory,A1 ; Build address of free memory + AND A0,A1,A1 ; Ensure alignment +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) end; +; + MVK_LH _tx_initialize_unused_memory,A0 ; Build address of variable + STW A1,*A0 ; Save free memory address +; +; /* Setup Timer 8 HIGH interrupt event */ +; + MVK_LH INTMUX1_ADDR,A0 ; Select event 67 to send through INT4 + MVK_LH INTMUX1_TMR8_VAL,A1 + STW A1,*A0 + + MVK_LH EVTMASK2_ADDR,A0 ; Build address of Event Mask 2 Register + MVK_LH EVTMASK2_TMR8_VAL,A1 ; Build value of Event Mask 2 Register + STW A1,*A0 +; +; /* Done, return to caller. */ +; + B B3 ; Return to caller + NOP 5 ; Delay slots +;} +; + + + .global _tx_nmi_vector + .global _tx_nmi_vector_processing +_tx_nmi_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_nmi_vector_processing,B3 + MVKH _tx_nmi_vector_processing,B3 + NOP 3 +_tx_nmi_vector_processing: + CALLP tx_nmi_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int4_vector +_tx_int4_vector: + ADDK.S2 -288,SP ; Allocate stack space + STW B3,*+SP(96) ; Save B3 + STW A0,*+SP(20) ; Save A0 + STW A1,*+SP(24) ; Save A1 + STW A2,*+SP(28) ; Save A2 + STW A3,*+SP(32) ; Save A3 + STW A4,*+SP(36) ; Save A4 + NOP + +;_tx_timer_interrupt_preamble: + + MVK_LH TMR8_INTCTLSTAT_ADDR,A0 ; Build address of Timer Interrupt Control Register + MVK_LH INTCTLSTAT_VAL,A1 ; Build value of Timer Interrupt Control Register + STW A1,*A0 ; Clear Timer Interrupts + +; Clear DSP Event flag - DSP events are not self-cleared + MVK_LH EVTCLR2_ADDR,A0 ; Build address of Event Clear 2 Register + MVK_LH EVTCLR2_TMR8_VAL,A1 ; Build value of Event Clear 2 Register + STW A1,*A0 ; Clear Timer Event + + MVK_LH _tx_timer_interrupt,A0 + B A0 ; Branch ThreadX timer ISR routine + NOP 5 ; Delay slots + NOP + + + + .global _tx_int5_vector + .global _tx_int5_vector_processing +_tx_int5_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int5_vector_processing,B3 + MVKH _tx_int5_vector_processing,B3 + NOP 3 +_tx_int5_vector_processing: + CALLP tx_int5_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int6_vector + .global _tx_int6_vector_processing +_tx_int6_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int6_vector_processing,B3 + MVKH _tx_int6_vector_processing,B3 + NOP 3 +_tx_int6_vector_processing: + CALLP tx_int6_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int7_vector + .global _tx_int7_vector_processing +_tx_int7_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int7_vector_processing,B3 + MVKH _tx_int7_vector_processing,B3 + NOP 3 +_tx_int7_vector_processing: + CALLP tx_int7_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int8_vector + .global _tx_int8_vector_processing +_tx_int8_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int8_vector_processing,B3 + MVKH _tx_int8_vector_processing,B3 + NOP 3 +_tx_int8_vector_processing: + CALLP tx_int8_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int9_vector + .global _tx_int9_vector_processing +_tx_int9_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int9_vector_processing,B3 + MVKH _tx_int9_vector_processing,B3 + NOP 3 +_tx_int9_vector_processing: + CALLP tx_int9_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int10_vector + .global _tx_int10_vector_processing +_tx_int10_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int10_vector_processing,B3 + MVKH _tx_int10_vector_processing,B3 + NOP 3 +_tx_int10_vector_processing: + CALLP tx_int10_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int11_vector + .global _tx_int11_vector_processing +_tx_int11_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int11_vector_processing,B3 + MVKH _tx_int11_vector_processing,B3 + NOP 3 +_tx_int11_vector_processing: + CALLP tx_int11_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int12_vector + .global _tx_int12_vector_processing +_tx_int12_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int12_vector_processing,B3 + MVKH _tx_int12_vector_processing,B3 + NOP 3 +_tx_int12_vector_processing: + CALLP tx_int12_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int13_vector + .global _tx_int13_vector_processing +_tx_int13_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int13_vector_processing,B3 + MVKH _tx_int13_vector_processing,B3 + NOP 3 +_tx_int13_vector_processing: + CALLP tx_int13_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int14_vector + .global _tx_int14_vector_processing +_tx_int14_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int14_vector_processing,B3 + MVKH _tx_int14_vector_processing,B3 + NOP 3 +_tx_int14_vector_processing: + CALLP tx_int14_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int15_vector + .global _tx_int15_vector_processing +_tx_int15_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int15_vector_processing,B3 + MVKH _tx_int15_vector_processing,B3 + NOP 3 +_tx_int15_vector_processing: + CALLP tx_int15_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.ccsproject b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.ccsproject new file mode 100644 index 00000000..d9b816a4 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.ccsproject @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.cproject b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.cproject new file mode 100644 index 00000000..ee74925b --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.cproject @@ -0,0 +1,168 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.project b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.project new file mode 100644 index 00000000..cbdff31c --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.project @@ -0,0 +1,89 @@ + + + sample_threadx_ta6678fmc + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -k + + + org.eclipse.cdt.make.core.buildCommand + ${CCS_UTILS_DIR}/bin/gmake + + + org.eclipse.cdt.make.core.buildLocation + ${BuildDirectory} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + true + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + false + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + ORIGINAL_PROJECT_ROOT + file:/C:/release/threadx/sample_threadx_ta6678fmc + + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.cdt.codan.core.prefs b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 00000000..f653028c --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.cdt.debug.core.prefs b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 00000000..2adc7b1d --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.core.resources.prefs b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..093dbb95 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,6 @@ +eclipse.preferences.version=1 +encoding//Debug/makefile=UTF-8 +encoding//Debug/objects.mk=UTF-8 +encoding//Debug/sources.mk=UTF-8 +encoding//Debug/subdir_rules.mk=UTF-8 +encoding//Debug/subdir_vars.mk=UTF-8 diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.c b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.c new file mode 100644 index 00000000..e5b8a0bf --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.c @@ -0,0 +1,329 @@ +/* + * board_setup.c + * + */ + + +#include "board_setup.h" +#include + + +//============================================================================= +//============ General definitions ============================================ +//============================================================================= +// DSP Timer-8 definition +#define C66XX_DSP_TIMER C66XX_TIMER_8 +// DSP Timer-8 output frequency in Hz +#define C66XX_DSP_TIMER_FREQ 100 +/* DSP Timer-8 interrupt event ID */ +#define C66XX_DSP_TIMER_EVENT_ID 67 +//============================================================================= + + +//============================================================================= +//============ Global functions =============================================== +//============================================================================= +void _tx_nmi_vector(void); +void _tx_int4_vector(void); +void _tx_int5_vector(void); +void _tx_int6_vector(void); +void _tx_int7_vector(void); +void _tx_int8_vector(void); +void _tx_int9_vector(void); +void _tx_int10_vector(void); +void _tx_int11_vector(void); +void _tx_int12_vector(void); +void _tx_int13_vector(void); +void _tx_int14_vector(void); +void _tx_int15_vector(void); +//============================================================================= + + +//============================================================================= +//============ Static functions =============================================== +//============================================================================= +static int32_t tx_timer_init(C66XX_TIMER timer, uint32_t frequency); +static int32_t tx_interrupt_init(void); +//============================================================================= + + +/*------------ init_output_timer() function ----------------------------------- + * DESCRIPTION: Function initializes Timer64 module + * ARGUMENTS: + * None + * RETURNED VALUE: Error code +-----------------------------------------------------------------------------*/ +static int32_t tx_timer_init(C66XX_TIMER timer, uint32_t frequency) +{ + int32_t r; + C66XX_TIMER_CFG_DD cfg_dd; + + // Reset 64-bit timer + if ((r = C66XX_TIMER_reset(timer, C66XX_TIMER_HW_CFG_64BIT)) != C66XX_OK) + goto exit; + + // Fill configuration data descriptor + memset(&cfg_dd, 0, C66XX_TIMER_CFG_DD_LEN); + cfg_dd.timer_mode = C66XX_TIMER_MODE_32BIT_UNCHAINED; + cfg_dd.timer_high.clk_src_output_mode = C66XX_TIMER_CLK_OUTPUT_MODE_CLK; + // Init DSP Timer64 module + if ((r = C66XX_TIMER_init(timer, frequency, &cfg_dd)) != C66XX_OK) + goto exit; + + // Enable timer interrupt + if ((r = C66XX_TIMER_enable_interrupts(timer, C66XX_TIMER_HW_CFG_32BIT_HIGH)) != C66XX_OK) + goto exit; + + // Start 32-bit timer high to enable continuously + if ((r = C66XX_TIMER_start(timer, C66XX_TIMER_HW_CFG_32BIT_HIGH, C66XX_TIMER_COUNT_MODE_CONTINUOUSLY)) != C66XX_OK) + goto exit; + + // TIMER module configuration is completed + printf("Timer #%u configuration is completed\n", timer); + +exit: + return (r); +} +//----------------------------------------------------------------------------- + + +/*------------ tx_interrupt_init() function ----------------------------------- + * DESCRIPTION: Function initializes CorePack interrupt module + * ARGUMENTS: + * None + * RETURNED VALUE: Error code +-----------------------------------------------------------------------------*/ +static int32_t tx_interrupt_init(void) +{ + int32_t r; + + // Set DSP interrupt handlers to the ones defined in tx_initialize_low_level.asm + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_NMI, _tx_nmi_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_4, _tx_int4_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_5, _tx_int5_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_6, _tx_int6_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_7, _tx_int7_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_8, _tx_int8_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_9, _tx_int9_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_10, _tx_int10_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_11, _tx_int11_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_12, _tx_int12_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_13, _tx_int13_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_14, _tx_int14_vector)) != C66XX_OK) + goto exit; + if ((r = C66XX_INT_set_core_dsp_interrupt_handler(C66XX_DSP_VECTID_15, _tx_int15_vector)) != C66XX_OK) + goto exit; + + /* CorePack interrupt module configuration is completed */ + printf("INTC configuration is completed\n"); + // Exit without errors + r = TASDK_OK; + +exit: + return (r); +} +//----------------------------------------------------------------------------- + + +/*------------ hardware_setup() function -------------------------------------- + * DESCRIPTION: Function intializes board hardware + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +int hardware_setup() +{ + int r; + + /* Init DSP */ + if ((r = TA66XX_BC_init()) != TASDK_OK) + goto exit; + + // Initialize UART + if ((r = TA66XX_BC_init_uart(C66XX_UART_BAUD_RATE_115200, C66XX_UART_DATA_BITS_8BITS, C66XX_UART_PARITY_NONE, C66XX_UART_STOP_BITS_1BIT)) != TASDK_OK) + goto exit; + + // Init DSP Timer + if ((r = tx_timer_init(C66XX_DSP_TIMER, C66XX_DSP_TIMER_FREQ)) != TASDK_OK) + goto exit; + + // Init DSP interrupt controller + if ((r = tx_interrupt_init()) != TASDK_OK) + goto exit; + + printf("Board is initialized\n"); + /* Exit with no errors */ + +exit: + return (r); +} +//----------------------------------------------------------------------------- + + +/*------------ tx_nmi_handler() function -------------------------------------- + * DESCRIPTION: Function handles NMI interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_nmi_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int4_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT4 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int4_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int5_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT5 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int5_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int6_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT6 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int6_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int7_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT7 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int7_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int8_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT8 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int8_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int9_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT9 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int9_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int10_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT10 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int10_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int11_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT11 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int11_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int12_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT12 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int12_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int13_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT13 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int13_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int14_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT14 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int14_handler(void) +{ +} +//----------------------------------------------------------------------------- + + +/*------------ tx_int15_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT15 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int15_handler(void) +{ +} +//----------------------------------------------------------------------------- + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.h b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.h new file mode 100644 index 00000000..a65e3b9d --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/board_setup.h @@ -0,0 +1,151 @@ +/* + * board_setup.h + * + */ + + +#ifndef BOARD_SETUP_H // check for this file has been already included +#define BOARD_SETUP_H 1 + + +/* Include T-AMC DSP API */ +#include "TA66XX_DSP_BC.h" + + +//============================================================================= +//============ Printf output definitions ====================================== +//============================================================================= +#define printf TA66XX_BC_uart_printf +//============================================================================= + + +/*------------ hardware_setup() function -------------------------------------- + * DESCRIPTION: Function intializes board hardware + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +int hardware_setup(); + + +/*------------ tx_nmi_handler() function -------------------------------------- + * DESCRIPTION: Function handles NMI interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_nmi_handler(void); + + +/*------------ tx_int4_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT4 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int4_handler(void); + + +/*------------ tx_int5_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT5 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int5_handler(void); + + +/*------------ tx_int6_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT6 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int6_handler(void); + + +/*------------ tx_int7_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT7 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int7_handler(void); + + +/*------------ tx_int8_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT8 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int8_handler(void); + + +/*------------ tx_int9_handler() function ------------------------------------- + * DESCRIPTION: Function handles INT9 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int9_handler(void); + + +/*------------ tx_int10_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT10 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int10_handler(void); + + +/*------------ tx_int11_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT11 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int11_handler(void); + + +/*------------ tx_int12_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT12 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int12_handler(void); + + +/*------------ tx_int13_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT13 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int13_handler(void); + + +/*------------ tx_int14_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT14 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int14_handler(void); + + +/*------------ tx_int15_handler() function ------------------------------------ + * DESCRIPTION: Function handles INT15 interrupt + * ARGUMENTS: + * None + * RETURNED VALUE: None +-----------------------------------------------------------------------------*/ +void tx_int15_handler(void); + + +//============================================================================= +#endif /* BOARD_SETUP_H */ + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.c b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.c new file mode 100644 index 00000000..18bad8de --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.c @@ -0,0 +1,528 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include "board_setup.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define TraceX trace oblects */ +#define TRACE_BUFFER_SIZE (4 * 1024) +#define TRACE_OBJECTS_COUNT 20 +/* Define TraceX trace buffer */ +UCHAR tx_trace_buffer[TRACE_BUFFER_SIZE]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define demo timer */ +#define DEMO_TIMER_PERIOD 10 +#define DEMO_TIMER_VALUE 0xaaaaaaaa +TX_TIMER timer_0; +ULONG timer_0_counter; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); +void my_stack_error_handler(TX_THREAD *thread_ptr); +void my_timer_function(ULONG timer_input); + + +/* Define main entry point. */ + +void main() +{ + /* Setup the hardware. */ + hardware_setup(); + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; +UINT status; + + /* Enable event tracing using the global “trace_buffer” memory and supporting + a maximum of TRACE_OBJECTS_COUNT ThreadX objects in the registry. */ + if ((status = tx_trace_enable(tx_trace_buffer, TRACE_BUFFER_SIZE, TRACE_OBJECTS_COUNT)) != TX_SUCCESS) + { + while (1); + } + + /* Register thread stack error notification callback */ + if ((status = tx_thread_stack_error_notify(my_stack_error_handler)) != TX_SUCCESS) + { + while (1); + } + + /* Create a byte memory pool from which to allocate the thread stacks. */ + status = tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the main thread. */ + status = tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 1. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + status = tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 2. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + status = tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 3. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + status = tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 4. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + status = tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 5. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + status = tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 6. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + status = tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the stack for thread 7. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + status = tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the message queue. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the message queue shared by threads 1 and 2. */ + status = tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the semaphore used by threads 3 and 4. */ + status = tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the event flags group used by threads 1 and 5. */ + status = tx_event_flags_create(&event_flags_0, "event flags 0"); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + status = tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate the memory for a small block pool. */ + status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create a block memory pool to allocate a message buffer from. */ + status = tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Allocate a block and release the block memory. */ + status = tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Release the block back to the pool. */ + status = tx_block_release(pointer); + if (status != TX_SUCCESS) + { + while (1); + } + + /* Create the periodic timer. */ + status = tx_timer_create(&timer_0, "timer 0", my_timer_function, (ULONG) DEMO_TIMER_VALUE, DEMO_TIMER_PERIOD, DEMO_TIMER_PERIOD, TX_AUTO_ACTIVATE); + if (status != TX_SUCCESS) + { + while (1); + } +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void my_stack_error_handler(TX_THREAD *thread_ptr) +{ + while(1); +} + + +void my_timer_function(ULONG timer_input) +{ + /* Increment the thread counter. */ + timer_0_counter++; + + if (timer_input != DEMO_TIMER_VALUE) + while(1); +} + diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.cmd b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.cmd new file mode 100644 index 00000000..b03e87b5 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/sample_threadx.cmd @@ -0,0 +1,53 @@ +-c +-heap 0x400 +-stack 0x1000 +-l C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\lib\ti.csl.ae66 +-l C:\ti\pdk_C6678_1_1_2_6\packages\ti\csl\lib\ti.csl.intc.ae66 + +/* Memory Map */ +MEMORY +{ + L1PSRAM (RWX) : org = 0x00E00000, len = 0x00008000 + L1DSRAM (RWX) : org = 0x00F00000, len = 0x00008000 + CODE_RAM (RWX) : org = 0x00800000, len = 0x00020000 + DATA_RAM (RWX) : org = 0x00820000, len = 0x00060000 + MSMCSRAM (RWX) : org = 0x0c000000, len = 0x00400000 + DDR3 (RWX) : org = 0x80000000, len = 0x80000000 +} + +SECTIONS +{ + .text > CODE_RAM + .stack > CODE_RAM + .cio > CODE_RAM + .const > CODE_RAM + .data > CODE_RAM + .switch > CODE_RAM + .sysmem > CODE_RAM + .far > CODE_RAM + .args > CODE_RAM + .ppinfo > CODE_RAM + .ppdata > CODE_RAM + .csl_vect > CODE_RAM + + GROUP + { + .neardata + .rodata + .bss + } > CODE_RAM + + /* COFF sections */ + .pinit > CODE_RAM + .cinit > CODE_RAM + + /* EABI sections */ + .binit > CODE_RAM + .init_array > CODE_RAM + .fardata > CODE_RAM + .c6xabi.exidx > CODE_RAM + .c6xabi.extab > CODE_RAM + + /* ThreadX section which should be the last RAM section loaded */ + .zend > DATA_RAM +} diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/TMS320C6678.ccxml b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/TMS320C6678.ccxml new file mode 100644 index 00000000..b7147d7f --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/TMS320C6678.ccxml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/readme.txt b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/readme.txt new file mode 100644 index 00000000..d783fef4 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/tx_initialize_low_level.asm b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/tx_initialize_low_level.asm new file mode 100644 index 00000000..de902350 --- /dev/null +++ b/ports/c667x/ccs/example_build/sample_threadx_ta6678fmc/tx_initialize_low_level.asm @@ -0,0 +1,406 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; + +SP .set B15 +ADDRESS_MSK .set 0xFFFFFFF0 ; Ensure 16-byte alignment + +; Use Timer 8 as it's available for all DSP cores at C6678 +; Timer 8 interrupt high event (TINT8H) ID is 67 +; Assume DSP core clock 1250 MHz +; Timer is clocked at DSP core clock / 6 = 208 MHz +; Timer frequency will set to 100 Hz +TMR8_INTCTLSTAT_ADDR .set 0x02280044 ; Timer 8 Interrupt Control and Status Register +INTCTLSTAT_VAL .set 0x00010000 ; Enable TIMHI interrupt + +EVTCLR2_ADDR .set 0x01800048 ; Event Clear register 2 address +EVTCLR2_TMR8_VAL .set 0x00000008 ; Clear event 67 - TINT8H + +EVTMASK2_ADDR .set 0x01800088 ; Event Mask register 2 address +EVTMASK2_TMR8_VAL .set 0x00000008 ; Mask event 67 - TINT8H + +INTMUX1_ADDR .set 0x01800104 ; Interrupt Mux Register 1 address +INTMUX1_TMR8_VAL .set 0x43 ; Tie in Event 67 (TINT8H) to INT4 +; +; + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + + +; External interrupt handlers - should be defined by user + .global tx_nmi_handler + .global tx_int5_handler + .global tx_int6_handler + .global tx_int7_handler + .global tx_int8_handler + .global tx_int9_handler + .global tx_int10_handler + .global tx_int11_handler + .global tx_int12_handler + .global tx_int13_handler + .global tx_int14_handler + .global tx_int15_handler + +; +; +;/* Define the first available address in memory, which is typically just the last +; RAM section loaded. */ + .sect ".zend" + .space 20 + .global _tx_first_free_memory + .align 16 +_tx_first_free_memory: + .space 4 + +; Useful macro definitions +; Load 32-bit integer into register +MVK_LH .macro val,reg + MVKL val,reg + MVKH val,reg + .endm +; Interrupt entry - allocate stack space, save A0-A4 and B3 registers to stack, +; build return address in B3 register for context save function and +; call context save function +TX_INTERRUPT_ENTRY .macro + ADDK.S2 -288,SP + STW B3,*+SP(96) + STW A0,*+SP(20) + STW A1,*+SP(24) + STW A2,*+SP(28) + STW A3,*+SP(32) + STW A4,*+SP(36) + B _tx_thread_context_save + .endm +; Interrupt exit - jump to context restore function +TX_INTERRUPT_EXIT .macro + B _tx_thread_context_restore + NOP 5 + .endm + + + .sect ".text" +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level C667x+/TI */ +;/* 6.0 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + .global _tx_initialize_low_level +_tx_initialize_low_level: +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (SP); +; + MVK_LH _tx_thread_system_stack_ptr,A0 ; Build address of system stack + STW SP,*A0 ; Save system stack address +; +; /* Pickup the first available memory address. */ +; + MVK_LH ADDRESS_MSK,A0 ; Build address mask + MVK_LH _tx_first_free_memory,A1 ; Build address of free memory + AND A0,A1,A1 ; Ensure alignment +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) end; +; + MVK_LH _tx_initialize_unused_memory,A0 ; Build address of variable + STW A1,*A0 ; Save free memory address +; +; /* Setup Timer 8 HIGH interrupt event */ +; + MVK_LH INTMUX1_ADDR,A0 ; Select event 67 to send through INT4 + MVK_LH INTMUX1_TMR8_VAL,A1 + STW A1,*A0 + + MVK_LH EVTMASK2_ADDR,A0 ; Build address of Event Mask 2 Register + MVK_LH EVTMASK2_TMR8_VAL,A1 ; Build value of Event Mask 2 Register + STW A1,*A0 +; +; /* Done, return to caller. */ +; + B B3 ; Return to caller + NOP 5 ; Delay slots +;} +; + + + .global _tx_nmi_vector + .global _tx_nmi_vector_processing +_tx_nmi_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_nmi_vector_processing,B3 + MVKH _tx_nmi_vector_processing,B3 + NOP 3 +_tx_nmi_vector_processing: + CALLP tx_nmi_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int4_vector +_tx_int4_vector: + ADDK.S2 -288,SP ; Allocate stack space + STW B3,*+SP(96) ; Save B3 + STW A0,*+SP(20) ; Save A0 + STW A1,*+SP(24) ; Save A1 + STW A2,*+SP(28) ; Save A2 + STW A3,*+SP(32) ; Save A3 + STW A4,*+SP(36) ; Save A4 + NOP + +;_tx_timer_interrupt_preamble: + + MVK_LH TMR8_INTCTLSTAT_ADDR,A0 ; Build address of Timer Interrupt Control Register + MVK_LH INTCTLSTAT_VAL,A1 ; Build value of Timer Interrupt Control Register + STW A1,*A0 ; Clear Timer Interrupts + +; Clear DSP Event flag - DSP events are not self-cleared + MVK_LH EVTCLR2_ADDR,A0 ; Build address of Event Clear 2 Register + MVK_LH EVTCLR2_TMR8_VAL,A1 ; Build value of Event Clear 2 Register + STW A1,*A0 ; Clear Timer Event + + + MVK_LH _tx_timer_interrupt,A0 + B A0 ; Branch ThreadX timer ISR routine + NOP 5 ; Delay slots + NOP + + + + .global _tx_int5_vector + .global _tx_int5_vector_processing +_tx_int5_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int5_vector_processing,B3 + MVKH _tx_int5_vector_processing,B3 + NOP 3 +_tx_int5_vector_processing: + CALLP tx_int5_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int6_vector + .global _tx_int6_vector_processing +_tx_int6_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int6_vector_processing,B3 + MVKH _tx_int6_vector_processing,B3 + NOP 3 +_tx_int6_vector_processing: + CALLP tx_int6_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int7_vector + .global _tx_int7_vector_processing +_tx_int7_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int7_vector_processing,B3 + MVKH _tx_int7_vector_processing,B3 + NOP 3 +_tx_int7_vector_processing: + CALLP tx_int7_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int8_vector + .global _tx_int8_vector_processing +_tx_int8_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int8_vector_processing,B3 + MVKH _tx_int8_vector_processing,B3 + NOP 3 +_tx_int8_vector_processing: + CALLP tx_int8_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int9_vector + .global _tx_int9_vector_processing +_tx_int9_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int9_vector_processing,B3 + MVKH _tx_int9_vector_processing,B3 + NOP 3 +_tx_int9_vector_processing: + CALLP tx_int9_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int10_vector + .global _tx_int10_vector_processing +_tx_int10_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int10_vector_processing,B3 + MVKH _tx_int10_vector_processing,B3 + NOP 3 +_tx_int10_vector_processing: + CALLP tx_int10_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int11_vector + .global _tx_int11_vector_processing +_tx_int11_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int11_vector_processing,B3 + MVKH _tx_int11_vector_processing,B3 + NOP 3 +_tx_int11_vector_processing: + CALLP tx_int11_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int12_vector + .global _tx_int12_vector_processing +_tx_int12_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int12_vector_processing,B3 + MVKH _tx_int12_vector_processing,B3 + NOP 3 +_tx_int12_vector_processing: + CALLP tx_int12_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int13_vector + .global _tx_int13_vector_processing +_tx_int13_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int13_vector_processing,B3 + MVKH _tx_int13_vector_processing,B3 + NOP 3 +_tx_int13_vector_processing: + CALLP tx_int13_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int14_vector + .global _tx_int14_vector_processing +_tx_int14_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int14_vector_processing,B3 + MVKH _tx_int14_vector_processing,B3 + NOP 3 +_tx_int14_vector_processing: + CALLP tx_int14_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + + .global _tx_int15_vector + .global _tx_int15_vector_processing +_tx_int15_vector: + TX_INTERRUPT_ENTRY +; +; /* Application specific processing goes here! */ +; + MVKL _tx_int15_vector_processing,B3 + MVKH _tx_int15_vector_processing,B3 + NOP 3 +_tx_int15_vector_processing: + CALLP tx_int15_handler,B3 ; CALLP instruction should be used here to call handler and save return address to B3 + TX_INTERRUPT_EXIT + + diff --git a/ports/c667x/ccs/example_build/tx/.ccsproject b/ports/c667x/ccs/example_build/tx/.ccsproject new file mode 100644 index 00000000..bed925d4 --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.ccsproject @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/ports/c667x/ccs/example_build/tx/.cproject b/ports/c667x/ccs/example_build/tx/.cproject new file mode 100644 index 00000000..6fb6150d --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.cproject @@ -0,0 +1,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/c667x/ccs/example_build/tx/.project b/ports/c667x/ccs/example_build/tx/.project new file mode 100644 index 00000000..23e7d5ff --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.project @@ -0,0 +1,105 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -k + + + org.eclipse.cdt.make.core.buildCommand + ${CCS_UTILS_DIR}/bin/gmake + + + org.eclipse.cdt.make.core.buildLocation + ${BuildDirectory} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + true + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + false + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.codan.core.prefs b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 00000000..f653028c --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.core.prefs b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 00000000..d9be20e1 --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,5 @@ +eclipse.preferences.version=1 +environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.832256006/append=true +environment/project/com.ti.ccstudio.buildDefinitions.C6000.Debug.832256006/appendContributed=true +environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.758214915/append=true +environment/project/com.ti.ccstudio.buildDefinitions.C6000.Release.758214915/appendContributed=true diff --git a/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.debug.core.prefs b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 00000000..2adc7b1d --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 00000000..71fde590 --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,6 @@ +#Fri Aug 03 15:02:35 PDT 2012 +com.ti.ccstudio.buildDefinitions.C6000.Debug.2070078368/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Debug.2070078368/internalBuilder/ignoreErr=true +com.ti.ccstudio.buildDefinitions.C6000.Release.664540310/internalBuilder/enabled=false +com.ti.ccstudio.buildDefinitions.C6000.Release.664540310/internalBuilder/ignoreErr=true +eclipse.preferences.version=1 diff --git a/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.core.resources.prefs b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..094412e7 --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,15 @@ +eclipse.preferences.version=1 +encoding//Debug/makefile=UTF-8 +encoding//Debug/objects.mk=UTF-8 +encoding//Debug/sources.mk=UTF-8 +encoding//Debug/src_generic/subdir_rules.mk=UTF-8 +encoding//Debug/src_generic/subdir_vars.mk=UTF-8 +encoding//Debug/src_port/subdir_rules.mk=UTF-8 +encoding//Debug/src_port/subdir_vars.mk=UTF-8 +encoding//Debug/subdir_rules.mk=UTF-8 +encoding//Debug/subdir_vars.mk=UTF-8 +encoding//Release/makefile=UTF-8 +encoding//Release/objects.mk=UTF-8 +encoding//Release/sources.mk=UTF-8 +encoding//Release/subdir_rules.mk=UTF-8 +encoding//Release/subdir_vars.mk=UTF-8 diff --git a/ports/c667x/ccs/example_build/tx/Release/ccsObjs.opt b/ports/c667x/ccs/example_build/tx/Release/ccsObjs.opt new file mode 100644 index 00000000..e954d96e --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/Release/ccsObjs.opt @@ -0,0 +1 @@ +"./tx_block_allocate.obj" "./tx_block_pool_cleanup.obj" "./tx_block_pool_create.obj" "./tx_block_pool_delete.obj" "./tx_block_pool_info_get.obj" "./tx_block_pool_initialize.obj" "./tx_block_pool_performance_info_get.obj" "./tx_block_pool_performance_system_info_get.obj" "./tx_block_pool_prioritize.obj" "./tx_block_release.obj" "./tx_byte_allocate.obj" "./tx_byte_pool_cleanup.obj" "./tx_byte_pool_create.obj" "./tx_byte_pool_delete.obj" "./tx_byte_pool_info_get.obj" "./tx_byte_pool_initialize.obj" "./tx_byte_pool_performance_info_get.obj" "./tx_byte_pool_performance_system_info_get.obj" "./tx_byte_pool_prioritize.obj" "./tx_byte_pool_search.obj" "./tx_byte_release.obj" "./tx_event_flags_cleanup.obj" "./tx_event_flags_create.obj" "./tx_event_flags_delete.obj" "./tx_event_flags_get.obj" "./tx_event_flags_info_get.obj" "./tx_event_flags_initialize.obj" "./tx_event_flags_performance_info_get.obj" "./tx_event_flags_performance_system_info_get.obj" "./tx_event_flags_set.obj" "./tx_event_flags_set_notify.obj" "./tx_initialize_high_level.obj" "./tx_initialize_kernel_enter.obj" "./tx_initialize_kernel_setup.obj" "./tx_mutex_cleanup.obj" "./tx_mutex_create.obj" "./tx_mutex_delete.obj" "./tx_mutex_get.obj" "./tx_mutex_info_get.obj" "./tx_mutex_initialize.obj" "./tx_mutex_performance_info_get.obj" "./tx_mutex_performance_system_info_get.obj" "./tx_mutex_prioritize.obj" "./tx_mutex_priority_change.obj" "./tx_mutex_put.obj" "./tx_queue_cleanup.obj" "./tx_queue_create.obj" "./tx_queue_delete.obj" "./tx_queue_flush.obj" "./tx_queue_front_send.obj" "./tx_queue_info_get.obj" "./tx_queue_initialize.obj" "./tx_queue_performance_info_get.obj" "./tx_queue_performance_system_info_get.obj" "./tx_queue_prioritize.obj" "./tx_queue_receive.obj" "./tx_queue_send.obj" "./tx_queue_send_notify.obj" "./tx_semaphore_ceiling_put.obj" "./tx_semaphore_cleanup.obj" "./tx_semaphore_create.obj" "./tx_semaphore_delete.obj" "./tx_semaphore_get.obj" "./tx_semaphore_info_get.obj" "./tx_semaphore_initialize.obj" "./tx_semaphore_performance_info_get.obj" "./tx_semaphore_performance_system_info_get.obj" "./tx_semaphore_prioritize.obj" "./tx_semaphore_put.obj" "./tx_semaphore_put_notify.obj" "./tx_thread_context_restore.obj" "./tx_thread_context_save.obj" "./tx_thread_create.obj" "./tx_thread_delete.obj" "./tx_thread_entry_exit_notify.obj" "./tx_thread_identify.obj" "./tx_thread_info_get.obj" "./tx_thread_initialize.obj" "./tx_thread_interrupt_control.obj" "./tx_thread_performance_info_get.obj" "./tx_thread_performance_system_info_get.obj" "./tx_thread_preemption_change.obj" "./tx_thread_priority_change.obj" "./tx_thread_relinquish.obj" "./tx_thread_reset.obj" "./tx_thread_resume.obj" "./tx_thread_schedule.obj" "./tx_thread_shell_entry.obj" "./tx_thread_sleep.obj" "./tx_thread_stack_analyze.obj" "./tx_thread_stack_build.obj" "./tx_thread_stack_error_handler.obj" "./tx_thread_stack_error_notify.obj" "./tx_thread_suspend.obj" "./tx_thread_system_preempt_check.obj" "./tx_thread_system_resume.obj" "./tx_thread_system_return.obj" "./tx_thread_system_suspend.obj" "./tx_thread_terminate.obj" "./tx_thread_time_slice.obj" "./tx_thread_time_slice_change.obj" "./tx_thread_timeout.obj" "./tx_thread_wait_abort.obj" "./tx_time_get.obj" "./tx_time_set.obj" "./tx_timer_activate.obj" "./tx_timer_change.obj" "./tx_timer_create.obj" "./tx_timer_deactivate.obj" "./tx_timer_delete.obj" "./tx_timer_expiration_process.obj" "./tx_timer_info_get.obj" "./tx_timer_initialize.obj" "./tx_timer_interrupt.obj" "./tx_timer_performance_info_get.obj" "./tx_timer_performance_system_info_get.obj" "./tx_timer_system_activate.obj" "./tx_timer_system_deactivate.obj" "./tx_timer_thread_entry.obj" "./tx_trace_buffer_full_notify.obj" "./tx_trace_disable.obj" "./tx_trace_enable.obj" "./tx_trace_event_filter.obj" "./tx_trace_event_unfilter.obj" "./tx_trace_initialize.obj" "./tx_trace_interrupt_control.obj" "./tx_trace_isr_enter_insert.obj" "./tx_trace_isr_exit_insert.obj" "./tx_trace_object_register.obj" "./tx_trace_object_unregister.obj" "./tx_trace_user_event_insert.obj" "./txe_block_allocate.obj" "./txe_block_pool_create.obj" "./txe_block_pool_delete.obj" "./txe_block_pool_info_get.obj" "./txe_block_pool_prioritize.obj" "./txe_block_release.obj" "./txe_byte_allocate.obj" "./txe_byte_pool_create.obj" "./txe_byte_pool_delete.obj" "./txe_byte_pool_info_get.obj" "./txe_byte_pool_prioritize.obj" "./txe_byte_release.obj" "./txe_event_flags_create.obj" "./txe_event_flags_delete.obj" "./txe_event_flags_get.obj" "./txe_event_flags_info_get.obj" "./txe_event_flags_set.obj" "./txe_event_flags_set_notify.obj" "./txe_mutex_create.obj" "./txe_mutex_delete.obj" "./txe_mutex_get.obj" "./txe_mutex_info_get.obj" "./txe_mutex_prioritize.obj" "./txe_mutex_put.obj" "./txe_queue_create.obj" "./txe_queue_delete.obj" "./txe_queue_flush.obj" "./txe_queue_front_send.obj" "./txe_queue_info_get.obj" "./txe_queue_prioritize.obj" "./txe_queue_receive.obj" "./txe_queue_send.obj" "./txe_queue_send_notify.obj" "./txe_semaphore_ceiling_put.obj" "./txe_semaphore_create.obj" "./txe_semaphore_delete.obj" "./txe_semaphore_get.obj" "./txe_semaphore_info_get.obj" "./txe_semaphore_prioritize.obj" "./txe_semaphore_put.obj" "./txe_semaphore_put_notify.obj" "./txe_thread_create.obj" "./txe_thread_delete.obj" "./txe_thread_entry_exit_notify.obj" "./txe_thread_info_get.obj" "./txe_thread_preemption_change.obj" "./txe_thread_priority_change.obj" "./txe_thread_relinquish.obj" "./txe_thread_reset.obj" "./txe_thread_resume.obj" "./txe_thread_suspend.obj" "./txe_thread_terminate.obj" "./txe_thread_time_slice_change.obj" "./txe_thread_wait_abort.obj" "./txe_timer_activate.obj" "./txe_timer_change.obj" "./txe_timer_create.obj" "./txe_timer_deactivate.obj" "./txe_timer_delete.obj" "./txe_timer_info_get.obj" \ No newline at end of file diff --git a/ports/c667x/ccs/example_build/tx/Release/objects.mk b/ports/c667x/ccs/example_build/tx/Release/objects.mk new file mode 100644 index 00000000..742c2da0 --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/Release/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/ports/c667x/ccs/example_build/tx/Release/sources.mk b/ports/c667x/ccs/example_build/tx/Release/sources.mk new file mode 100644 index 00000000..9cbc2a26 --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/Release/sources.mk @@ -0,0 +1,110 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +K_DEPS := +C_DEPS := +LIB_OUTPUTS := +CC_DEPS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +LIB_OUTPUTS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ + diff --git a/ports/c667x/ccs/example_build/tx/Release/subdir_rules.mk b/ports/c667x/ccs/example_build/tx/Release/subdir_rules.mk new file mode 100644 index 00000000..6ceea2dd --- /dev/null +++ b/ports/c667x/ccs/example_build/tx/Release/subdir_rules.mk @@ -0,0 +1,22 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: C6000 Compiler' + "C:/ti/ccsv8/tools/compiler/ti-cgt-c6000_8.2.4/bin/cl6x" -mv6600 --abi=eabi -O2 --include_path="C:/ti/ccsv8/tools/compiler/ti-cgt-c6000_8.2.4/include" --display_error_number --diag_warning=225 --preproc_with_compile --preproc_dependency="$(basename $( +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef int LONG; +typedef unsigned int ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 400 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 2048 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX C6xxx port. */ + +#define TX_INT_DISABLE 0x00 /* Disable interrupts */ +#define TX_INT_ENABLE 0x01 /* Enable interrupts */ + + +#ifndef TX_TIMER_TICKS_PER_SECOND +#define TX_TIMER_TICKS_PER_SECOND ((ULONG) 100) +#endif + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ +/* +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x01f0c014) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif +*/ + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION +/* +#define TX_TIMER_INTERNAL_EXTENSION ULONG tx_timer_internal_padding; +*/ + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#ifdef TX_SKIP_INTRINSICS +unsigned int _tx_thread_interrupt_control(unsigned int); + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); +#else +#define TX_DISABLE interrupt_save = _disable_interrupts(); +#define TX_RESTORE _restore_interrupts(interrupt_save); +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX C667x/TI Version 6.0 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + diff --git a/ports/c667x/ccs/readme_threadx.txt b/ports/c667x/ccs/readme_threadx.txt new file mode 100644 index 00000000..d78707c7 --- /dev/null +++ b/ports/c667x/ccs/readme_threadx.txt @@ -0,0 +1,248 @@ + Microsoft's Azure RTOS ThreadX for TMS320C667x + + Using the TI Code Composer Tools + +1. Installation + +TI Code Composer Studio and the TI MCSDK must be installed prior to +building ThreadX. The following links can be used to download these +packages: + + +http://processors.wiki.ti.com/index.php/Download_CCS +http://software-dl.ti.com/sdoemb/sdoemb_public_sw/bios_mcsdk/latest/index_FDS.html + +It is assumed the tools are installed in the default directories: + +CCS path by default - c:\ti\ccsv(version number) +MCSDK path by default - c:\ti + +If the packages are installed in different directories, the ThreadX project +settings must be adjusted. + +2. Open the Azure RTOS Workspace + +In order to build the ThreadX library and the ThreadX demonstration first open +the Azure RTOS Workspace inside your ThreadX installation directory. + + +3. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply import the CCS project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.lib. + + +4. Demonstration System + +The ThreadX demonstration is designed to execute on the C6678EVM evaluation board. + +Building the demonstration is easy; simply import the "sample_threadx_c6678evm" project. +Now select "Project -> Build Active Project" to build the ThreadX demonstration, +which produces the sample_threadx.out file in the "Debug" directory. You are now +ready to run the ThreadX demonstration on the C6678EVM evaluation board. + +Please refer to Chapter 6 of the ThreadX User Guide for a complete description +of this demonstration. + + +5. System Initialization + +The entry point in ThreadX for the TMS320C667x using the TI tools is at label +_c_int00. This is defined within the TI library. In addition, this is +where all static and global pre-set C variable initialization processing +takes place. + +The ThreadX initialization file tx_initialize_low_level.asm is responsible +for setting up various system data structures, the vector area, and a periodic +timer interrupt source. By default, the vector area is defined to be located in +the "vectors" section, which is defined at the top of tx_initialize_low_level.asm. +This area is located at address 0 for the demonstration. + +tx_initialize_low_level.asm is also where initialization of a periodic timer +interrupt source should take place. + +In addition, _tx_initialize_low_level determines the first available address +for use by the application. By default, free memory is assumed to start after +the .zend section in RAM (defined in tx_initialize_low_level). This section +must be placed at the end of your other RAM sections. Please see sample_threadx.cmd +for an example. The address of this section is passed to the application definition +function, tx_application_define. + + +6. Register Usage and Stack Frames + +The TI TMS320C667x compiler assumes that registers A0-A9, A16-A31, B0-B9, and +B16-B31 are scratch registers for each function. All other registers used by +a C function must be preserved by the function. ThreadX takes advantage of this +in situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved context +of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x04 1 0 + 0x08 CSR CSR + 0x0C IPR B3 + 0x10 AMR AMR + 0x14 A0 A10 + 0x18 A1 A11 + 0x1C A2 A12 + 0x20 A3 A13 + 0x24 A4 A14 + 0x28 A5 A15 + 0x2C A6 B10 + 0x30 A7 B11 + 0x34 A8 B12 + 0x38 A9 B13 + 0x3C A10 ILC + 0x40 A11 RILC + 0x44 A12 + 0x48 A13 + 0x4C A14 + 0x50 A15 + 0x54 B0 + 0x58 B1 + 0x5C B2 + 0x60 B3 + 0x64 B4 + 0x68 B5 + 0x6C B6 + 0x70 B7 + 0x74 B8 + 0x78 B9 + 0x7C B10 + 0x80 B11 + 0x84 B12 + 0x88 B13 + 0x8C A16 + 0x90 A17 + 0x94 A18 + 0x98 A19 + 0x9C A20 + 0xA0 A21 + 0xA4 A22 + 0xA8 A23 + 0xAC A24 + 0xB0 A25 + 0xB4 A26 + 0xB8 A27 + 0xBC A28 + 0xC0 A29 + 0xC4 A30 + 0xC8 A31 + 0xCC B16 + 0xD0 B17 + 0xD4 B18 + 0xD8 B19 + 0xDC B20 + 0xE0 B21 + 0xE4 B22 + 0xE8 B23 + 0xEC B24 + 0xF0 B25 + 0xF4 B26 + 0xF8 B27 + 0xFC B28 + 0x100 B29 + 0x104 B30 + 0x108 B31 + 0x10C ILC + 0x110 RILC + 0x114 ITSR + + +7. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some performance. +To make it run faster, you can replace the -g compiler option +to a -O3 in the ThreadX project file to enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +8. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for +TMS320C667x targets. There are a certain set of requirements that are +defined in the following sub-sections: + + +8.1 Vector Area + +The TMS320C667x interrupt vectors at in the section "vectors" and is defined at +the top of tx_initialize_low_level.asm. Each interrupt vector entry contains +a jump to a template interrupt processing shell. + + +8.2 Interrupt Service Routine Shells + +The following interrupt processing shells are defined at the bottom of +tx_initialize_low_level.asm: + + + __tx_int4_ISR + __tx_int5_ISR + __tx_int6_ISR + __tx_int7_ISR + __tx_int8_ISR + __tx_int9_ISR + __tx_int10_ISR + __tx_int11_ISR + __tx_int12_ISR + __tx_int13_ISR + __tx_int14_ISR + __tx_int15_ISR + +Each interrupt ISR is entered with B3, A0-A4 is available (these registers are +saved in the initial vector processing). The default interrupt handling +includes calls to __tx_thread_context_save and __tx_thread_context_restore. +Application ISR processing can be added between the context save/restore +calls. Note that only the compiler scratch registers are available for use +after context save return to the ISR. + +High-frequency interrupt handlers might not want to perform context +save/restore processing on each interrupt. If this is the case, any +additional registers used must be saved and restored by the ISR and +the interrupt return processing must restore the registers saved by the +initial vector processing. This can be accomplished by adding the +following code to the end of the custom ISR handling: + + LDW *+SP(20),A0 ; Recover A0 + LDW *+SP(24),A1 ; Recover A1 + LDW *+SP(28),A2 ; Recover A2 + LDW *+SP(32),A3 ; Recover A3 + B IRP ; Return to point of interrupt +|| LDW *+SP(36),A4 ; Recover A4 + LDW *+SP(96),B3 ; Recover B3 + ADDK.S2 288,SP ; Recover stack space + NOP 3 ; Delay slots + + +9. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for TMS320C667x using TI Code Composer tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/c667x/ccs/src/tx_thread_context_restore.asm b/ports/c667x/ccs/src/tx_thread_context_restore.asm new file mode 100644 index 00000000..58861b58 --- /dev/null +++ b/ports/c667x/ccs/src/tx_thread_context_restore.asm @@ -0,0 +1,343 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +FP .set A15 +DP .set B14 +SP .set B15 +; + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +; +; + .sect ".text" +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore C667x/TI */ +;/* 6.0 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + .global _tx_thread_context_restore +_tx_thread_context_restore: +; +; /* Lockout interrupts. */ +; + MVC CSR,B0 ; Pickup CSR + AND -2,B0,B0 ; Build interrupt lockout value + MVC B0,CSR ; Lockout interrupts +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + MVKL _tx_thread_system_state,A0 ; Build address of system state + MVKH _tx_thread_system_state,A0 ; + LDW *A0,A1 ; Pickup system state variable + MVKL _tx_thread_current_ptr,A2 ; Build address of current thread ptr + NOP 3 ; Delay slots + SUB A1,1,A1 ; Decrement system state + [!A1] B _tx_thread_not_nested_restore ; If 0, not a nested restore + MVKH _tx_thread_current_ptr,A2 ; + LDW *A2,A3 ; Pickup current thread pointer + STW A1,*A0 ; Store system state + NOP 2 ; Delay slots +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDW *+SP(8),B0 ; Recover saved CSR + LDW *+SP(12),B1 ; Recover saved IRP + LDW *+SP(16),B2 ; Recover saved AMR + LDW *+SP(20),A0 ; Recover A0 + LDW *+SP(24),A1 ; Recover A1 + LDW *+SP(28),A2 ; Recover A2 + LDW *+SP(32),A3 ; Recover A3 + LDW *+SP(36),A4 ; Recover A4 + LDW *+SP(40),A5 ; Recover A5 + LDW *+SP(44),A6 ; Recover A6 + LDW *+SP(48),A7 ; Recover A7 + LDW *+SP(52),A8 ; Recover A8 + LDW *+SP(56),A9 ; Recover A9 + MVC B0,CSR ; Setup CSR + MVC B1,IRP ; Setup IRP + MVC B2,AMR ; Setup AMR + LDW *+SP(268),B0 ; Recover saved ILC + LDW *+SP(272),B1 ; Recover saved RILC + LDW *+SP(276),B2 ; Recover saved ITSR + NOP 4 + MVC B0,ILC ; Setup ILC + MVC B1,RILC ; Setup RILC + MVC B2,ITSR ; Setup ITSR + LDW *+SP(84),B0 ; Recover B0 + LDW *+SP(88),B1 ; Recover B1 + LDW *+SP(92),B2 ; Recover B2 + LDW *+SP(100),B4 ; Recover B4 + LDW *+SP(104),B5 ; Recover B5 + LDW *+SP(108),B6 ; Recover B6 + LDW *+SP(112),B7 ; Recover B7 + LDW *+SP(116),B8 ; Recover B8 + LDW *+SP(140),A16 ; Recover A16 + LDW *+SP(144),A17 ; Recover A17 + LDW *+SP(148),A18 ; Recover A18 + LDW *+SP(152),A19 ; Recover A19 + LDW *+SP(156),A20 ; Recover A20 + LDW *+SP(160),A21 ; Recover A21 + LDW *+SP(164),A22 ; Recover A22 + LDW *+SP(168),A23 ; Recover A23 + LDW *+SP(172),A24 ; Recover A24 + LDW *+SP(176),A25 ; Recover A25 + LDW *+SP(180),A26 ; Recover A26 + LDW *+SP(184),A27 ; Recover A27 + LDW *+SP(188),A28 ; Recover A28 + LDW *+SP(192),A29 ; Recover A29 + LDW *+SP(196),A30 ; Recover A30 + LDW *+SP(200),A31 ; Recover A31 + LDW *+SP(204),B16 ; Recover B16 + LDW *+SP(208),B17 ; Recover B17 + LDW *+SP(212),B18 ; Recover B18 + LDW *+SP(216),B19 ; Recover B19 + LDW *+SP(220),B20 ; Recover B20 + LDW *+SP(224),B21 ; Recover B21 + LDW *+SP(228),B22 ; Recover B22 + LDW *+SP(232),B23 ; Recover B23 + LDW *+SP(236),B24 ; Recover B24 + LDW *+SP(240),B25 ; Recover B25 + LDW *+SP(244),B26 ; Recover B26 + LDW *+SP(248),B27 ; Recover B27 + LDW *+SP(252),B28 ; Recover B28 + LDW *+SP(256),B29 ; Recover B29 + LDW *+SP(260),B30 ; Recover B30 + LDW *+SP(264),B31 ; Recover B31 + B IRP ; Return to point of interrupt +|| LDW *+SP(120),B9 ; Recover B9 + LDW *+SP(96),B3 ; Recover B3 + ADDK.S2 288,SP ; Recover stack space + NOP 3 ; Delay slots +; +; } +_tx_thread_not_nested_restore: +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + NOP ; Delay + MV A3,A1 ; Move thread pointer into A1 + [!A1] B _tx_thread_schedule ; If null, idle system restore + MVKL _tx_thread_preempt_disable,A0 ; Build preempt disable flag address + MVKH _tx_thread_preempt_disable,A0 ; + MVKL _tx_thread_execute_ptr,A4 ; Build execute thread pointer + MVKH _tx_thread_execute_ptr,A4 ; + LDW *A0,B1 ; Pickup preempt disable flag + + LDW *A4,A6 ; Pickup next thread to execute + NOP 4 ; Delay slot + CMPEQ A6,A1,A7 ; Determine if threads are the same? + ADD A7,B1,B1 ; Add results together + [B1] B _tx_thread_no_preempt_restore ; If set, skip preeemption + LDW *+A1(8),A6 ; Recover thread's stack pointer + MVKL _tx_timer_time_slice,A5 ; Build time slice address + MVKH _tx_timer_time_slice,A5 ; + LDW *A5,B1 ; Pickup current time-slice + NOP ; Delay slot +; +; +_tx_thread_preempt_restore: +; +; + MVKL 1,A0 ; Build the interrupt stack type + STW A0,*+A6(4) ; Save stack type +; +; /* Store the remaining registers on the thread's stack. */ +; + STW A10,*+A6(60) ; Save A10 + STW A11,*+A6(64) ; Save A11 + STW A12,*+A6(68) ; Save A12 + STW A13,*+A6(72) ; Save A13 + STW A14,*+A6(76) ; Save A14 + STW A15,*+A6(80) ; Save A15 (FP) + STW B10,*+A6(124) ; Save B10 + ADDK 128,A6 ; Move stack pointer + STW B11,*+A6(0) ; Save B11 + STW B12,*+A6(4) ; Save B12 + STW B13,*+A6(8) ; Save B13 +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; +; } +_tx_thread_dont_save_ts: +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler + STW B1,*+A1(24) ; Store current time-slice + ZERO A3 ; Clear value + STW A3,*A2 ; Set current thread pointer to NULL + STW A3,*A5 ; Set time slice to 0 + NOP ; Delay +; +; +_tx_thread_no_preempt_restore: +; +; /* Restore interrupted thread. */ +; +; /* Pickup the saved stack pointer. */ +; SP = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + MV A6,SP ; Setup real stack pointer + LDW *+SP(8),B0 ; Recover saved CSR + LDW *+SP(12),B1 ; Recover saved IRP + LDW *+SP(16),B2 ; Recover saved AMR + LDW *+SP(20),A0 ; Recover A0 + LDW *+SP(24),A1 ; Recover A1 + LDW *+SP(28),A2 ; Recover A2 + LDW *+SP(32),A3 ; Recover A3 + LDW *+SP(36),A4 ; Recover A4 + LDW *+SP(40),A5 ; Recover A5 + LDW *+SP(44),A6 ; Recover A6 + LDW *+SP(48),A7 ; Recover A7 + LDW *+SP(52),A8 ; Recover A8 + LDW *+SP(56),A9 ; Recover A9 + MVC B0,CSR ; Setup CSR + MVC B1,IRP ; Setup IRP + MVC B2,AMR ; Setup AMR + LDW *+SP(268),B0 ; Recover saved ILC + LDW *+SP(272),B1 ; Recover saved RILC + LDW *+SP(276),B2 ; Recover saved ITSR + NOP 4 ; Delay + MVC B0,ILC ; Setup ILC + MVC B1,RILC ; Setup RILC + MVC B2,ITSR ; Setup ITSR + LDW *+SP(84),B0 ; Recover B0 + LDW *+SP(88),B1 ; Recover B1 + LDW *+SP(92),B2 ; Recover B2 + LDW *+SP(100),B4 ; Recover B4 + LDW *+SP(104),B5 ; Recover B5 + LDW *+SP(108),B6 ; Recover B6 + LDW *+SP(112),B7 ; Recover B7 + LDW *+SP(116),B8 ; Recover B8 + LDW *+SP(140),A16 ; Recover A16 + LDW *+SP(144),A17 ; Recover A17 + LDW *+SP(148),A18 ; Recover A18 + LDW *+SP(152),A19 ; Recover A19 + LDW *+SP(156),A20 ; Recover A20 + LDW *+SP(160),A21 ; Recover A21 + LDW *+SP(164),A22 ; Recover A22 + LDW *+SP(168),A23 ; Recover A23 + LDW *+SP(172),A24 ; Recover A24 + LDW *+SP(176),A25 ; Recover A25 + LDW *+SP(180),A26 ; Recover A26 + LDW *+SP(184),A27 ; Recover A27 + LDW *+SP(188),A28 ; Recover A28 + LDW *+SP(192),A29 ; Recover A29 + LDW *+SP(196),A30 ; Recover A30 + LDW *+SP(200),A31 ; Recover A31 + LDW *+SP(204),B16 ; Recover B16 + LDW *+SP(208),B17 ; Recover B17 + LDW *+SP(212),B18 ; Recover B18 + LDW *+SP(216),B19 ; Recover B19 + LDW *+SP(220),B20 ; Recover B20 + LDW *+SP(224),B21 ; Recover B21 + LDW *+SP(228),B22 ; Recover B22 + LDW *+SP(232),B23 ; Recover B23 + LDW *+SP(236),B24 ; Recover B24 + LDW *+SP(240),B25 ; Recover B25 + LDW *+SP(244),B26 ; Recover B26 + LDW *+SP(248),B27 ; Recover B27 + LDW *+SP(252),B28 ; Recover B28 + LDW *+SP(256),B29 ; Recover B29 + LDW *+SP(260),B30 ; Recover B30 + LDW *+SP(264),B31 ; Recover B31 + B IRP ; Return to point of interrupt +|| LDW *+SP(120),B9 ; Recover B9 + LDW *+SP(96),B3 ; Recover B3 + ADDK.S2 288,SP ; Recover stack space + NOP 3 ; Delay slots +; +; } +;} + diff --git a/ports/c667x/ccs/src/tx_thread_context_save.asm b/ports/c667x/ccs/src/tx_thread_context_save.asm new file mode 100644 index 00000000..ea455f8f --- /dev/null +++ b/ports/c667x/ccs/src/tx_thread_context_save.asm @@ -0,0 +1,274 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +FP .set A15 +DP .set B14 +SP .set B15 +; + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr +; +; + .sect ".text" +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save C667x/TI */ +;/* 6.0 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + .global _tx_thread_context_save +_tx_thread_context_save: +; +; /* Upon entry to this routine, it is assumed that all interrupts are locked +; out, an initial stack frame of 288 bytes has been allocated and registers +; A0, A1, A2, A3, A4, and B3 have been saved in the frame. Additionally, +; it is assumed that register B3 contains the ISR's return address. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + MVKL _tx_thread_system_state,A0 ; Build address of system state + MVKH _tx_thread_system_state,A0 ; + LDW *A0,A1 ; Pickup current system state + STW A5,*+SP(40) ; Save A5 + STW A6,*+SP(44) ; Save A6 + STW A7,*+SP(48) ; Save A7 + STW A8,*+SP(52) ; Save A8 + [!A1] B _tx_thread_not_nested_save ; If 0, not a nested save condition + MVKL _tx_thread_current_ptr,A3 ; Build address of current thread ptr + MVKH _tx_thread_current_ptr,A3 ; + LDW *A3,A2 ; Pickup current thread pointer + ADD 1,A1,A1 ; Increment the system state (nested) counter + STW A1,*A0 ; Store system state +; +; /* Nested interrupt condition. Save remaining scratch registers, and control registers +; and return to calling ISR. */ +; + STW A9,*+SP(56) ; Save A9 + STW B0,*+SP(84) ; Save B0 + STW B1,*+SP(88) ; Save B1 + STW B2,*+SP(92) ; Save B2 + ; B3 is already saved! + STW B4,*+SP(100) ; Save B4 + STW B5,*+SP(104) ; Save B5 + STW B6,*+SP(108) ; Save B6 + STW B7,*+SP(112) ; Save B7 + STW B8,*+SP(116) ; Save B8 + STW B9,*+SP(120) ; Save B9 + MVC CSR,B0 ; Pickup CSR + B B3 ; Return to calling ISR + MVC IRP,B1 ; Pickup IRP + MVC AMR,B2 ; Pickup AMR + STW B0,*+SP(8) ; Save CSR + STW B1,*+SP(12) ; Save IRP + STW B2,*+SP(16) ; Save AMR + ZERO B0 ; Clear B0 + MVC B0,AMR ; Clear AMR for linear addressing in ISR + STW A16,*+SP(140) ; Save A16 + STW A17,*+SP(144) ; Save A17 + STW A18,*+SP(148) ; Save A18 + STW A19,*+SP(152) ; Save A19 + STW A20,*+SP(156) ; Save A20 + STW A21,*+SP(160) ; Save A21 + STW A22,*+SP(164) ; Save A22 + STW A23,*+SP(168) ; Save A23 + STW A24,*+SP(172) ; Save A24 + STW A25,*+SP(176) ; Save A25 + STW A26,*+SP(180) ; Save A26 + STW A27,*+SP(184) ; Save A27 + STW A28,*+SP(188) ; Save A28 + STW A29,*+SP(192) ; Save A29 + STW A30,*+SP(196) ; Save A30 + STW A31,*+SP(200) ; Save A31 + STW B16,*+SP(204) ; Save B16 + STW B17,*+SP(208) ; Save B17 + STW B18,*+SP(212) ; Save B18 + STW B19,*+SP(216) ; Save B19 + STW B20,*+SP(220) ; Save B20 + STW B21,*+SP(224) ; Save B21 + STW B22,*+SP(228) ; Save B22 + STW B23,*+SP(232) ; Save B23 + STW B24,*+SP(236) ; Save B24 + STW B25,*+SP(240) ; Save B25 + STW B26,*+SP(244) ; Save B26 + STW B27,*+SP(248) ; Save B27 + STW B28,*+SP(252) ; Save B28 + STW B29,*+SP(256) ; Save B29 + STW B30,*+SP(260) ; Save B30 + STW B31,*+SP(264) ; Save B31 + MVC ILC,B0 ; Pickup ILC + MVC RILC,B1 ; Pickup RILC + MVC ITSR,B2 ; Pickup ITSR + STW B0,*+SP(268) ; Save ILC + STW B1,*+SP(272) ; Save RILC + STW B2,*+SP(276) ; Save ITSR +; +_tx_thread_not_nested_save: +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + MVKL _tx_thread_system_stack_ptr,A0 ; Build address of system + MVKH _tx_thread_system_stack_ptr,A0 ; stack pointer + MV A2,A1 ; Transfer to A1 for B compare + [!A1] B _tx_thread_idle_system_save ; If Null, idle system save + STW A9,*+SP(56) ; Save A9 + STW B0,*+SP(84) ; Save B0 + STW B1,*+SP(88) ; Save B1 + STW B2,*+SP(92) ; Save B2 + NOP ; Delay slot +; +; /* At this point, a thread was interrupted and the remainder of its scratch and +; control registers must be saved. */ +; + ; B3 was already saved! + STW B4,*+SP(100) ; Save B4 + STW B5,*+SP(104) ; Save B5 + STW B6,*+SP(108) ; Save B6 + STW B7,*+SP(112) ; Save B7 + STW B8,*+SP(116) ; Save B8 + STW B9,*+SP(120) ; Save B9 + MVC CSR,B0 ; Pickup CSR + MVC IRP,B1 ; Pickup IRP + MVC AMR,B2 ; Pickup AMR + STW B0,*+SP(8) ; Save CSR + STW B1,*+SP(12) ; Save IRP + STW B2,*+SP(16) ; Save AMR + ZERO B0 ; Clear B0 + MVC B0,AMR ; Clear AMR for linear addressing in ISR + STW A16,*+SP(140) ; Save A16 + STW A17,*+SP(144) ; Save A17 + STW A18,*+SP(148) ; Save A18 + STW A19,*+SP(152) ; Save A19 + STW A20,*+SP(156) ; Save A20 + STW A21,*+SP(160) ; Save A21 + STW A22,*+SP(164) ; Save A22 + STW A23,*+SP(168) ; Save A23 + STW A24,*+SP(172) ; Save A24 + STW A25,*+SP(176) ; Save A25 + STW A26,*+SP(180) ; Save A26 + STW A27,*+SP(184) ; Save A27 + STW A28,*+SP(188) ; Save A28 + STW A29,*+SP(192) ; Save A29 + STW A30,*+SP(196) ; Save A30 + STW A31,*+SP(200) ; Save A31 + STW B16,*+SP(204) ; Save B16 + STW B17,*+SP(208) ; Save B17 + STW B18,*+SP(212) ; Save B18 + STW B19,*+SP(216) ; Save B19 + STW B20,*+SP(220) ; Save B20 + STW B21,*+SP(224) ; Save B21 + STW B22,*+SP(228) ; Save B22 + STW B23,*+SP(232) ; Save B23 + STW B24,*+SP(236) ; Save B24 + STW B25,*+SP(240) ; Save B25 + STW B26,*+SP(244) ; Save B26 + STW B27,*+SP(248) ; Save B27 + STW B28,*+SP(252) ; Save B28 + STW B29,*+SP(256) ; Save B29 + STW B30,*+SP(260) ; Save B30 + STW B31,*+SP(264) ; Save B31 + MVC ILC,B0 ; Pickup ILC + MVC RILC,B1 ; Pickup RILC + MVC ITSR,B2 ; Pickup ITSR + STW B0,*+SP(268) ; Save ILC + STW B1,*+SP(272) ; Save RILC + STW B2,*+SP(276) ; Save ITSR +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = SP; +; +; /* Switch to the system stack. */ +; SP = _tx_thread_system_stack_ptr; +; + STW SP,*+A1(8) ; Save stack pointer + B B3 ; Return to calling ISR + LDW *A0,SP ; Switch to system stack + NOP 4 ; Stack pointer is valid upon return! +; +; } +; else +; { +; +_tx_thread_idle_system_save: +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to ISR +; processing. */ +; + B B3 ; Return to ISR + ADDK.S2 288,SP ; Recover stack space + NOP 4 ; Delay slot +; +; } +;} + diff --git a/ports/c667x/ccs/src/tx_thread_interrupt_control.asm b/ports/c667x/ccs/src/tx_thread_interrupt_control.asm new file mode 100644 index 00000000..ac7d467d --- /dev/null +++ b/ports/c667x/ccs/src/tx_thread_interrupt_control.asm @@ -0,0 +1,95 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +FP .set A15 +DP .set B14 +SP .set B15 +; +; + .sect ".text" +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control C667x/TI */ +;/* 6.0 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + .global _tx_thread_interrupt_control +_tx_thread_interrupt_control: +; +; /* Pickup current interrupt lockout posture. */ +; + MVC CSR,B0 ; Pickup current CSR +; +; /* Apply the new interrupt posture. */ +; + B B3 ; Return to caller + AND -2,B0,B0 ; Clear GIE bit + OR A4,B0,B0 ; Build new interrupt posture + MVC CSR,B1 ; Return previous posture + MVC B0,CSR ; Apply new interrupt posture + AND 1,B1,A4 ; Clear non-GIE bits +; +;} + diff --git a/ports/c667x/ccs/src/tx_thread_schedule.asm b/ports/c667x/ccs/src/tx_thread_schedule.asm new file mode 100644 index 00000000..57da66d1 --- /dev/null +++ b/ports/c667x/ccs/src/tx_thread_schedule.asm @@ -0,0 +1,254 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +FP .set A15 +DP .set B14 +SP .set B15 +; +; + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice +; +; + .sect ".text" +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule C667x/TI */ +;/* 6.0 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + .global _tx_thread_schedule +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + MVC CSR,B0 ; Pickup current CSR + OR 1,B0,B0 ; Build interrupt enable value + MVC B0,CSR ; Enable interrupts + MVKL _tx_thread_execute_ptr,A0 ; Build address of execute pointer + MVKH _tx_thread_execute_ptr,A0 ; +; +; /* Wait for a thread to execute. */ +; do +; { +; +_tx_thread_schedule_loop: +; + LDW *A0,A1 ; Pickup next thread to execute + NOP 4 ; Delay slots + [!A1] B _tx_thread_schedule_loop ; If Null, just wait here for thread + ; to become ready + MV A1,A4 ; Move thread pointer to A4 + MVKL _tx_thread_current_ptr,A1 ; Build address of current thread ptr + MVKH _tx_thread_current_ptr,A1 ; + MVKL _tx_timer_time_slice,A2 ; Build address of time-slice + MVKH _tx_timer_time_slice,A2 ; +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + AND -2,B0,B0 ; Build interrupt lockout value + MVC B0,CSR ; Lockout interrupts +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDW *+A4(4),A3 ; Pickup run-count + LDW *+A4(8),SP ; Switch to thread's stack + LDW *+A4(24),B1 ; Pickup time-slice + STW A4,*A1 ; Setup current pointer + NOP ; Delay +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + ADD 1,A3,A3 ; Increment run-counter + LDW *+SP(4),B0 ; Pickup stack-type + STW A3,*+A4(4) ; Store run-counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + STW B1,*A2 ; Setup time-slice +; +; /* Switch to the thread's stack. */ +; SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + NOP 2 ; Delay slots + [B0] B _tx_thread_interrupt_stack ; Look for interrupt stack frame + LDW *+SP(8),B0 ; Pickup saved CSR + LDW *+SP(12),B3 ; Pickup saved B3/IPR + LDW *+SP(16),B1 ; Pickup saved AMR + LDW *+SP(20),A10 ; Restore A10 + LDW *+SP(24),A11 ; Restore A11 + LDW *+SP(28),A12 ; Restore A12 + LDW *+SP(32),A13 ; Restore A13 + MVC B0,CSR ; Restore CSR + MVC B1,AMR ; Restore AMR + LDW *+SP(36),A14 ; Restore A14 + LDW *+SP(40),A15 ; Restore A15 + LDW *+SP(44),B10 ; Restore B10 + LDW *+SP(48),B11 ; Restore B11 + LDW *+SP(52),B12 ; Restore B12 + LDW *+SP(56),B13 ; Restore B13 + LDW *+SP(60),B0 ; Restore ILC + LDW *+SP(64),B1 ; Restore RILC + NOP 4 ; Delay slots + MVC B0,ILC ; Restore ILC + MVC B1,RILC ; Restore RILC + B B3 ; Return to caller + ADDK 64,SP ; Recover stack space + NOP 4 ; Delay slots +; +_tx_thread_interrupt_stack: + MVC B0,CSR ; Restore CSR + MVC B3,IRP ; Restore IPR + MVC B1,AMR ; Restore AMR + LDW *+SP(268),B0 ; Recover saved ILC + LDW *+SP(272),B1 ; Recover saved RILC + LDW *+SP(276),B2 ; Recover saved ITSR + NOP 4 ; Delay + MVC B0,ILC ; Setup ILC + MVC B1,RILC ; Setup RILC + MVC B2,ITSR ; Setup ITSR + LDW *+SP(20),A0 ; Recover A0 + LDW *+SP(24),A1 ; Recover A1 + LDW *+SP(28),A2 ; Recover A2 + LDW *+SP(32),A3 ; Recover A3 + LDW *+SP(36),A4 ; Recover A4 + LDW *+SP(40),A5 ; Recover A5 + LDW *+SP(44),A6 ; Recover A6 + LDW *+SP(48),A7 ; Recover A7 + LDW *+SP(52),A8 ; Recover A8 + LDW *+SP(56),A9 ; Recover A9 + LDW *+SP(60),A10 ; Recover A10 + LDW *+SP(64),A11 ; Recover A11 + LDW *+SP(68),A12 ; Recover A12 + LDW *+SP(72),A13 ; Recover A13 + LDW *+SP(76),A14 ; Recover A14 + LDW *+SP(80),A15 ; Recover A15 (FP) + LDW *+SP(84),B0 ; Recover B0 + LDW *+SP(88),B1 ; Recover B1 + LDW *+SP(92),B2 ; Recover B2 + LDW *+SP(96),B3 ; Recover B3 + LDW *+SP(100),B4 ; Recover B4 + LDW *+SP(104),B5 ; Recover B5 + LDW *+SP(108),B6 ; Recover B6 + LDW *+SP(112),B7 ; Recover B7 + LDW *+SP(116),B8 ; Recover B8 + LDW *+SP(120),B9 ; Recover B9 + LDW *+SP(124),B10 ; Recover B10 + LDW *+SP(128),B11 ; Recover B11 + LDW *+SP(140),A16 ; Recover A16 + LDW *+SP(144),A17 ; Recover A17 + LDW *+SP(148),A18 ; Recover A18 + LDW *+SP(152),A19 ; Recover A19 + LDW *+SP(156),A20 ; Recover A20 + LDW *+SP(160),A21 ; Recover A21 + LDW *+SP(164),A22 ; Recover A22 + LDW *+SP(168),A23 ; Recover A23 + LDW *+SP(172),A24 ; Recover A24 + LDW *+SP(176),A25 ; Recover A25 + LDW *+SP(180),A26 ; Recover A26 + LDW *+SP(184),A27 ; Recover A27 + LDW *+SP(188),A28 ; Recover A28 + LDW *+SP(192),A29 ; Recover A29 + LDW *+SP(196),A30 ; Recover A30 + LDW *+SP(200),A31 ; Recover A31 + LDW *+SP(204),B16 ; Recover B16 + LDW *+SP(208),B17 ; Recover B17 + LDW *+SP(212),B18 ; Recover B18 + LDW *+SP(216),B19 ; Recover B19 + LDW *+SP(220),B20 ; Recover B20 + LDW *+SP(224),B21 ; Recover B21 + LDW *+SP(228),B22 ; Recover B22 + LDW *+SP(232),B23 ; Recover B23 + LDW *+SP(236),B24 ; Recover B24 + LDW *+SP(240),B25 ; Recover B25 + LDW *+SP(244),B26 ; Recover B26 + LDW *+SP(248),B27 ; Recover B27 + LDW *+SP(252),B28 ; Recover B28 + LDW *+SP(256),B29 ; Recover B29 + LDW *+SP(260),B30 ; Recover B30 + LDW *+SP(264),B31 ; Recover B31 + B IRP ; Return to point of interrupt +|| LDW *+SP(132),B12 ; Recover B12 + LDW *+SP(136),B13 ; Recover B13 + ADDK.S2 288,SP ; Recover stack space + NOP 3 ; Delay slots +; +;} + diff --git a/ports/c667x/ccs/src/tx_thread_stack_build.asm b/ports/c667x/ccs/src/tx_thread_stack_build.asm new file mode 100644 index 00000000..8e6c0559 --- /dev/null +++ b/ports/c667x/ccs/src/tx_thread_stack_build.asm @@ -0,0 +1,257 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +FP .set A15 +DP .set B14 +SP .set B15 +ADDRESS_MSK .set 0xFFFFFFF0 +; + .sect ".text" +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build C667x/TI */ +;/* 6.0 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + .global _tx_thread_stack_build +_tx_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the C667x should look like the following after it is built: +; +; Stack Top: N/A Available for use +; 1 Interrupt stack frame type 4 +; CSR Initial value for CSR 8 +; IRP Initial thread entry 12 +; AMR Initial thread addressing mode 16 +; A0 Initial A0 20 +; A1 Initial A1 24 +; A2 Initial A2 28 +; A3 Initial A3 32 +; A4 Initial A4 36 +; A5 Initial A5 40 +; A6 Initial A6 44 +; A7 Initial A7 48 +; A8 Initial A8 52 +; A9 Initial A9 56 +; A10 Initial A10 60 +; A11 Initial A11 64 +; A12 Initial A12 68 +; A13 Initial A13 72 +; A14 Initial A14 76 +; A15 (FP) Initial A15 (FP) 80 +; B0 Initial B0 84 +; B1 Initial B1 88 +; B2 Initial B2 92 +; B3 Initial B3 96 +; B4 Initial B4 100 +; B5 Initial B5 104 +; B6 Initial B6 108 +; B7 Initial B7 112 +; B8 Initial B8 116 +; B9 Initial B9 120 +; B10 Initial B10 124 +; B11 Initial B11 128 +; B12 Initial B12 132 +; B13 Initial B13 136 +; A16 Initial A16 140 +; A17 Initial A17 144 +; A18 Initial A18 148 +; A19 Initial A19 152 +; A20 Initial A20 156 +; A21 Initial A21 160 +; A22 Initial A22 164 +; A23 Initial A23 168 +; A24 Initial A24 172 +; A25 Initial A25 176 +; A26 Initial A26 180 +; A27 Initial A27 184 +; A28 Initial A28 188 +; A29 Initial A29 192 +; A30 Initial A30 196 +; A31 Initial A31 200 +; B16 Initial B16 204 +; B17 Initial B17 208 +; B18 Initial B18 212 +; B19 Initial B19 216 +; B20 Initial B20 220 +; B21 Initial B21 224 +; B22 Initial B22 228 +; B23 Initial B23 232 +; B24 Initial B24 236 +; B25 Initial B25 240 +; B26 Initial B26 244 +; B27 Initial B27 248 +; B28 Initial B28 252 +; B29 Initial B29 256 +; B30 Initial B30 260 +; B31 Initial B31 264 +; ILC Initial ILC 268 +; RILC Initial RILC 272 +; ITSR Initial ITSR 276 + + +; +; Stack Bottom: (higher memory address) */ +; + LDW *+A4(16),A0 ; Pickup end of stack area + MVKL ADDRESS_MSK,A1 ; Build address mask + MVKH ADDRESS_MSK,A1 ; + MVC CSR,B0 ; Pickup current CSR + AND -2,B0,B0 ; Clear GIE bit + OR 2,B0,B0 ; Set PGIE bit for interrupt return + AND A1,A0,A0 ; Ensure alignment + MVKL 288,A2 ; Calculate stack size + SUB A0,A2,A0 ; Allocate space on thread's stack +; +; /* Actually build the stack frame. */ +; + MVKL 1,A2 ; Build stack type + ZERO A3 ; Clear value + STW A2,*+A0(4) ; Interrupt stack type + STW B0,*+A0(8) ; Initial CSR + STW B4,*+A0(12) ; Thread shell entry point + STW A3,*+A0(16) ; Initial AMR + STW A3,*+A0(20) ; Initial A0 + STW A3,*+A0(24) ; Initial A1 + STW A3,*+A0(28) ; Initial A2 + STW A3,*+A0(32) ; Initial A3 + STW A3,*+A0(36) ; Initial A4 + STW A3,*+A0(40) ; Initial A5 + STW A3,*+A0(44) ; Initial A6 + STW A3,*+A0(48) ; Initial A7 + STW A3,*+A0(52) ; Initial A8 + STW A3,*+A0(56) ; Initial A9 + STW A3,*+A0(60) ; Initial A10 + STW A3,*+A0(64) ; Initial A11 + STW A3,*+A0(68) ; Initial A12 + STW A3,*+A0(72) ; Initial A13 + STW A3,*+A0(76) ; Initial A14 + STW A3,*+A0(80) ; Initial A15 + STW A3,*+A0(84) ; Initial B0 + STW A3,*+A0(88) ; Initial B1 + STW A3,*+A0(92) ; Initial B2 + STW A3,*+A0(96) ; Initial B3 + STW A3,*+A0(100) ; Initial B4 + STW A3,*+A0(104) ; Initial B5 + STW A3,*+A0(108) ; Initial B6 + STW A3,*+A0(112) ; Initial B7 + STW A3,*+A0(116) ; Initial B8 + STW A3,*+A0(120) ; Initial B9 + STW A3,*+A0(124) ; Initial B10 + MVKL 128,A2 ; Stack adjustment value + ADD A2,A0,A2 ; Adjust pointer into stack frame + STW A3,*+A2(0) ; Initial B11 + STW A3,*+A2(4) ; Initial B12 + STW A3,*+A2(8) ; Initial B13 + STW A3,*+A2(12) ; Initial A16 + STW A3,*+A2(16) ; Initial A17 + STW A3,*+A2(20) ; Initial A18 + STW A3,*+A2(24) ; Initial A19 + STW A3,*+A2(28) ; Initial A20 + STW A3,*+A2(32) ; Initial A21 + STW A3,*+A2(36) ; Initial A22 + STW A3,*+A2(40) ; Initial A23 + STW A3,*+A2(44) ; Initial A24 + STW A3,*+A2(48) ; Initial A25 + STW A3,*+A2(52) ; Initial A26 + STW A3,*+A2(56) ; Initial A27 + STW A3,*+A2(60) ; Initial A28 + STW A3,*+A2(64) ; Initial A29 + STW A3,*+A2(68) ; Initial A30 + STW A3,*+A2(72) ; Initial A31 + STW A3,*+A2(76) ; Initial B16 + STW A3,*+A2(80) ; Initial B17 + STW A3,*+A2(84) ; Initial B18 + STW A3,*+A2(88) ; Initial B19 + STW A3,*+A2(92) ; Initial B20 + STW A3,*+A2(96) ; Initial B21 + STW A3,*+A2(100) ; Initial B22 + STW A3,*+A2(104) ; Initial B23 + STW A3,*+A2(108) ; Initial B24 + STW A3,*+A2(112) ; Initial B25 + STW A3,*+A2(116) ; Initial B26 + STW A3,*+A2(120) ; Initial B27 + STW A3,*+A2(124) ; Initial B28 + ADDK 128,A2 ; Adjust stack pointer again + STW A3,*+A2(0) ; Initial B29 + STW A3,*+A2(4) ; Initial B30 + STW A3,*+A2(8) ; Initial B31 + B B3 ; Return to caller + STW A3,*+A2(12) ; Initial ILC + STW A3,*+A2(16) ; Initial RILC + MVKL 0x3,B0 ; Build initial ITSR (set GIE and SGIE bits) + STW B0,*+A2(20) ; Store ITSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = A0; +; + STW A0,*+A4(8) ; Save stack pointer in thread's + ; control block +;} + diff --git a/ports/c667x/ccs/src/tx_thread_system_return.asm b/ports/c667x/ccs/src/tx_thread_system_return.asm new file mode 100644 index 00000000..67de8e21 --- /dev/null +++ b/ports/c667x/ccs/src/tx_thread_system_return.asm @@ -0,0 +1,162 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +FP .set A15 +DP .set B14 +SP .set B15 +; +; + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_system_stack_ptr +; +; + .sect ".text" +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return C667x/TI */ +;/* 6.0 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + .global _tx_thread_system_return +_tx_thread_system_return: +; +; /* Save minimal context on the stack. */ +; + MVC CSR,B0 ; Pickup current CSR + MVC AMR,B1 ; Pickup current AMR + ADDK -64,SP ; Allocate stack space + ZERO B2 ; Build solicited stack type + STW B2,*+SP(4) ; Save stack type + STW B0,*+SP(8) ; Save CSR + STW B3,*+SP(12) ; Save B3 (return address) + STW B1,*+SP(16) ; Save AMR + STW A10,*+SP(20) ; Save A10 + STW A11,*+SP(24) ; Save A11 + STW A12,*+SP(28) ; Save A12 + STW A13,*+SP(32) ; Save A13 + STW A14,*+SP(36) ; Save A14 + STW A15,*+SP(40) ; Save A15 + STW B10,*+SP(44) ; Save B10 + STW B11,*+SP(48) ; Save B11 + STW B12,*+SP(52) ; Save B12 + STW B13,*+SP(56) ; Save B13 + MVC ILC,B0 ; Pickup ILC + MVC RILC,B1 ; Pickup RILC + STW B0,*+SP(60) ; Save ILC + STW B1,*+SP(64) ; Save RILC +; +; /* Lockout interrupts. */ +; + AND -2,B0,B0 ; Build interrupt disable value + MVC B0,CSR ; Lockout interrupts +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; SP = _tx_thread_system_stack_ptr; +; + MVKL _tx_timer_time_slice,A2 ; Pickup address of time slice + MVKH _tx_timer_time_slice,A2 ; + LDW *A2,B0 ; Pickup time slice + MVKL _tx_thread_current_ptr,A1 ; Pickup address of current thread + MVKH _tx_thread_current_ptr,A1 ; + LDW *A1,A4 ; Pickup current thread pointer + MVKL _tx_thread_system_stack_ptr,A3 ; Pickup address of system stack + MVKH _tx_thread_system_stack_ptr,A3 ; +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + [!B0] B _tx_thread_dont_save_ts ; If no-time slice, skip save + NOP ; Delay slot + STW SP,*+A4(8) ; Save thread's stack pointer + LDW *A3,SP ; Switch to system stack pointer + NOP ; Delay slot +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; + NOP ; + STW B2,*A2 ; Clear time-slice + NOP 2 ; Delay slots + STW B0,*+A4(24) ; Save time-slice +; +; +; } +_tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + B _tx_thread_schedule ; Return to scheduling loop + STW B2,*A1 ; Set current thread to NULL + NOP 4 ; Delay slots +; +;} + diff --git a/ports/c667x/ccs/src/tx_timer_interrupt.asm b/ports/c667x/ccs/src/tx_timer_interrupt.asm new file mode 100644 index 00000000..b6a2f0a1 --- /dev/null +++ b/ports/c667x/ccs/src/tx_timer_interrupt.asm @@ -0,0 +1,300 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +FP .set A15 +DP .set B14 +SP .set B15 +; +;Define Assembly language external references... +; + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_timer_expiration_process + .global _tx_thread_time_slice + .global _tx_thread_context_save + .global _tx_thread_context_restore +; +; + .sect ".text" +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt C667x/TI */ +;/* 6.0 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_context_save Context save */ +;/* _tx_thread_context_restore Context restore */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + .global _tx_timer_interrupt +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed that registers B3, A0-A4 have +; already been saved and the space for saving additional registers has +; already been reserved. In addition, interrupts are locked out and must +; remain so until context save returns. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + MVKL _tx_timer_system_clock,A0 ; Build address of system clock + MVKH _tx_timer_system_clock,A0 ; + LDW *A0,A2 ; Pickup system clock + MVKL _tx_timer_time_slice,A3 ; Build address of time slice + MVKH _tx_timer_time_slice,A3 ; + LDW *A3,A1 ; Pickup time slice + NOP 2 ; Delay + ADD 1,A2,A2 ; Increment the system clock + STW A2,*A0 ; Store it back in memory +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + [!A1] B _tx_timer_no_time_slice ; If 0, skip time slice processing + SUB A1,1,A1 ; Decrement time-slice value + NOP 4 ; Delay slots +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; +; /* Check for expiration. */ +; if (_tx_timer_time_slice == 0) +; + [A1] B _tx_timer_no_time_slice ; If non-zero, not expired yet + STW A1,*A3 ; Store new time-slice + MVKL _tx_timer_expired_time_slice,A0 ; Build address of expired flag + MVKH _tx_timer_expired_time_slice,A0 ; + MVKL 1,A4 ; Expired flag + NOP ; Delay +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + STW A4,*A0 ; Set expired flag +; } +; +_tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MVKL _tx_timer_current_ptr,A2 ; Build address of current timer pointer + MVKH _tx_timer_current_ptr,A2 ; + LDW *A2,A0 ; Pickup timer list address + MVKL _tx_timer_expired,A3 ; Build address of expired flag + MVKH _tx_timer_expired,A3 ; + NOP 2 ; Delay slots + LDW *A0,A1 ; Pickup current timer entry + ADD 4,A0,A0 ; Increment the current pointer + NOP 3 ; Delay slots + [A1] B _tx_timer_done ; If non-NULL, something has expired +; +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MVKL 1,A4 ; Build expired flag + [A1] STW A4,*A3 ; Set expired flag + NOP 3 ; Delay slots +; +; } +; else +; { +_tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MVKL _tx_timer_list_end,A3 ; Build timer list end address + MVKH _tx_timer_list_end,A3 ; + LDW *A3,A4 ; Pickup list end address + MVKL _tx_timer_list_start,A3 ; Build timer list start address + MVKH _tx_timer_list_start,A3 ; + NOP 2 ; Delay slots + CMPEQ A4,A0,A1 ; Compare current pointer with end + [A1] LDW *A3,A0 ; If at the end, pickup timer list start + NOP 4 ; Delay slots +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; +_tx_timer_skip_wrap: +; +; + STW A0,*A2 ; Store current timer pointer +; } +; +_tx_timer_done: +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MVKL _tx_timer_expired_time_slice,A3 ; Build time-slice expired flag + MVKH _tx_timer_expired_time_slice,A3 ; + LDW *A3,A4 ; Pickup time-slice expired flag + MVKL _tx_timer_expired,A0 ; Build timer expired flag + MVKH _tx_timer_expired,A0 ; + LDW *A0,A2 ; Pickup timer expired flag + NOP 4 ; Delay slots + OR A2,A4,A1 ; Combine expired flags + [!A1] B _tx_timer_nothing_expired + NOP 5 ; Delay slots +; +_tx_something_expired: +; +; +; /* Something expired, call context save. */ +; _tx_thread_context_save(); +; + B _tx_thread_context_save ; Call context save routine + MVKL _tx_timer_ISR_return,B3 ; Build return address + MVKH _tx_timer_ISR_return,B3 ; + NOP 3 ; Delay slots +_tx_timer_ISR_return: +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + MVKL _tx_timer_expired,A0 ; Build timer expired address + MVKH _tx_timer_expired,A0 ; + LDW *A0,A1 ; Pickup expired flag + NOP 4 ; Delay slots + [!A1] B _tx_timer_dont_activate ; If not set, skip timer activation + NOP 5 ; Delay slots +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + B _tx_timer_expiration_process ; Process timer expiration + MVKL _tx_timer_ISR_return_1,B3 ; Build return address + MVKH _tx_timer_ISR_return_1,B3 ; + NOP 3 ; Delay slots +_tx_timer_ISR_return_1: +; +; } +_tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MVKL _tx_timer_expired_time_slice,A0 ; Build address of expired flag + MVKH _tx_timer_expired_time_slice,A0 ; + LDW *A0,A1 ; Pickup expired flag + NOP 4 ; Delay slots + [!A1] B _tx_timer_not_ts_expiration ; If not set, skip time-slice processing + NOP 5 ; Delay slots +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); +; + B _tx_thread_time_slice ; Call time-slice processing + MVKL _tx_timer_ISR_return_2,B3 ; Build return address + MVKH _tx_timer_ISR_return_2,B3 ; + NOP 3 ; Delay slots +_tx_timer_ISR_return_2: +; +; } +; +_tx_timer_not_ts_expiration: +; +; +; /* Call context restore. */ +; _tx_thread_context_restore(); +; + B _tx_thread_context_restore ; Jump to context restore - no return! + NOP 5 ; Delay slots +; +; } +; +_tx_timer_nothing_expired: +; + LDW *+SP(20),A0 ; Recover A0 + LDW *+SP(24),A1 ; Recover A1 + LDW *+SP(28),A2 ; Recover A2 + LDW *+SP(32),A3 ; Recover A3 + B IRP ; Return to point of interrupt +|| LDW *+SP(36),A4 ; Recover A4 + LDW *+SP(96),B3 ; Recover B3 + ADDK.S2 288,SP ; Recover stack space + NOP 3 ; Delay slots +; +;} + diff --git a/ports/cortex_a15/gnu/example_build/build_threadx.bat b/ports/cortex_a15/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..38377100 --- /dev/null +++ b/ports/cortex_a15/gnu/example_build/build_threadx.bat @@ -0,0 +1,238 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_interrupt_disable.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_interrupt_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_fiq_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_fiq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_irq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_irq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_fiq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_fiq_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 ../src/tx_thread_vectored_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_start.o tx_thread_irq_nesting_start.o tx_thread_irq_nesting_end.o +arm-none-eabi-ar -r tx.a tx_thread_fiq_nesting_end.o tx_thread_fiq_context_restore.o tx_thread_vectored_context_save.o tx_initialize_low_level.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_a15/gnu/example_build/build_threadx_sample.bat b/ports/cortex_a15/gnu/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..af64fc3b --- /dev/null +++ b/ports/cortex_a15/gnu/example_build/build_threadx_sample.bat @@ -0,0 +1,6 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 reset.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 crt0.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a15 -I../../../../common/inc -I../inc sample_threadx.c +arm-none-eabi-ld -A cortex-a15 -T sample_threadx.ld reset.o crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libc.a libgcc.a -o sample_threadx.out -M > sample_threadx.map + diff --git a/ports/cortex_a15/gnu/example_build/crt0.S b/ports/cortex_a15/gnu/example_build/crt0.S new file mode 100644 index 00000000..aa0f3239 --- /dev/null +++ b/ports/cortex_a15/gnu/example_build/crt0.S @@ -0,0 +1,90 @@ + +/* .text is used instead of .section .text so it works with arm-aout too. */ + .text + .code 32 + .align 0 + + .global _mainCRTStartup + .global _start + .global start +start: +_start: +_mainCRTStartup: + +/* Start by setting up a stack */ + /* Set up the stack pointer to a fixed value */ + ldr r3, .LC0 + mov sp, r3 + /* Setup a default stack-limit in case the code has been + compiled with "-mapcs-stack-check". Hard-wiring this value + is not ideal, since there is currently no support for + checking that the heap and stack have not collided, or that + this default 64k is enough for the program being executed. + However, it ensures that this simple crt0 world will not + immediately cause an overflow event: */ + sub sl, sp, #64 << 10 /* Still assumes 256bytes below sl */ + mov a2, #0 /* Second arg: fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr a1, .LC1 /* First arg: start of memory block */ + ldr a3, .LC2 + sub a3, a3, a1 /* Third arg: length of block */ + + + + bl memset + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ +#ifdef __USES_INITFINI__ + /* Some arm/elf targets use the .init and .fini sections + to create constructors and destructors, and for these + targets we need to call the _init function and arrange + for _fini to be called at program exit. */ + mov r4, r0 + mov r5, r1 +/* ldr r0, .Lfini */ + bl atexit +/* bl init */ + mov r0, r4 + mov r1, r5 +#endif + bl main + + bl exit /* Should not return. */ + + + /* For Thumb, constants must be after the code since only + positive offsets are supported for PC relative addresses. */ + + .align 0 +.LC0: +.LC1: + .word __bss_start__ +.LC2: + .word __bss_end__ +/* +#ifdef __USES_INITFINI__ +.Lfini: + .word _fini +#endif */ + /* Return ... */ +#ifdef __APCS_26__ + movs pc, lr +#else +#ifdef __THUMB_INTERWORK + bx lr +#else + mov pc, lr +#endif +#endif + + +/* Workspace for Angel calls. */ + .data +/* Data returned by monitor SWI. */ +.global __stack_base__ +HeapBase: .word 0 +HeapLimit: .word 0 +__stack_base__: .word 0 +StackLimit: .word 0 diff --git a/ports/cortex_a15/gnu/example_build/libc.a b/ports/cortex_a15/gnu/example_build/libc.a new file mode 100644 index 0000000000000000000000000000000000000000..5b04fa4ed9b6479f70979f5577dd0705d1f6d1d7 GIT binary patch literal 2447586 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zyyk;0u~c5dm1R37av%P?23us%dHPGDpFT$0GBczAKYnN6rVuiJ<@W-;X3iNSdGtC4 zZc0Al4tY)&I-P!o0#6|ykg|z--55Au=wiVt!DWKHH_4BuyvA0+F2RcgFA>}#_#GlT dhn|!HpOEmEh$!@SiRZoRqCc?z|Ecwv{|7^Je? +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef __thumb__ + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); +#else +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) ); +#endif + +#define TX_RESTORE asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) ); + +#endif + + +/* Define VFP extension for the Cortex-A5. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/GNU Version 6.0 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a5/gnu/readme_threadx.txt b/ports/cortex_a5/gnu/readme_threadx.txt new file mode 100644 index 00000000..37a92981 --- /dev/null +++ b/ports/cortex_a5/gnu/readme_threadx.txt @@ -0,0 +1,513 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A5 + + Using the GNU Tools + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. + +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + + +2. Demonstration System + +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file +that can be downloaded and executed. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A5 using GNU tools is at label _start. +This is defined within the modified version of the GNU startup code - crt0.S. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied +to address 0. + +This is also where initialization of a periodic timer interrupt source should take +place. + +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter +to your application definition function, tx_application_define. + + +4. Assembler / Compiler Switches + +The following are compiler switches used in building the demonstration +system: + +Compiler/Assembler Meaning + Switches + + -g Specifies debug information + -c Specifies object code generation + -mcpu=cortex-a5 Specifies target cpu + +Linker Switch Meaning + + -o sample_threadx.out Specifies output file + -M > sample_threadx.map Specifies demo map file + -A cortex-a5 Specifies target architecture + -T sample_threadx.ld Specifies the loader control file + +Application Defines ( -D option) + + TX_ENABLE_FIQ_SUPPORT This assembler define enables FIQ + interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + + TX_ENABLE_IRQ_NESTING This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.S. + + TX_ENABLE_FIQ_NESTING This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.S. In addition, + IRQ nesting should also be enabled. + + TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ + interrupt handling in the ThreadX + generic C source. This define + should also be used in conjunction + with the corresponding assembler + define. + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + +5. Register Usage and Stack Frames + +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) a5 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 a5 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A5 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A5 vectors start at address zero. The demonstration system startup +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +nested IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.S: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save @ Jump to the context save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.S: + + .global __tx_irq_example_handler +__tx_irq_example_handler: +@ +@ /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} @ Save some scratch registers + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers + BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call goes here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* Enable nested IRQ interrupts. NOTE: Since this service returns +@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Disable nested IRQ interrupts. The mode is switched back to +@ IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.S. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.S: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Enable nested FIQ interrupts. NOTE: Since this service returns +@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Disable nested FIQ interrupts. The mode is switched back to +@ FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of +ThreadX will still run. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.S for the demonstration system. + + +9. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A5 using GNU tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a5/gnu/src/tx_thread_context_restore.S b/ports/cortex_a5/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..2a3f0165 --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,257 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE = 0xD3 @ Disable IRQ/FIQ, SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE = 0x93 @ Disable IRQ, SVC mode +IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode +#endif +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_restore @ Yes, idle system was interrupted +@ + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_preempt_restore @ No, preemption needs to happen +@ +@ +__tx_thread_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_preempt_restore: +@ + LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r2 @ Enter IRQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r0 @ Enter SVC mode + B _tx_thread_schedule @ Return to scheduler +@} + + + diff --git a/ports/cortex_a5/gnu/src/tx_thread_context_save.S b/ports/cortex_a5/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..d35776b6 --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_context_save.S @@ -0,0 +1,203 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_irq_processing_return + .global _tx_execution_isr_enter +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} @ Store other registers +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr@ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #16 @ Recover saved registers + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@} + + + diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S new file mode 100644 index 00000000..b7a6d9cb --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_restore.S @@ -0,0 +1,260 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ +SVC_MODE = 0xD3 @ SVC mode +FIQ_MODE = 0xD1 @ FIQ mode +MODE_MASK = 0x1F @ Mode mask +THUMB_MASK = 0x20 @ Thumb bit mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_context_restore(VOID) +@{ + .global _tx_thread_fiq_context_restore + .type _tx_thread_fiq_context_restore,function +_tx_thread_fiq_context_restore: +@ +@ /* Lockout interrupts. */ +@ + CPSID if @ Disable IRQ and FIQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_fiq_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, [sp] @ Pickup the saved SPSR + MOV r2, #MODE_MASK @ Build mask to isolate the interrupted mode + AND r1, r1, r2 @ Isolate mode bits + CMP r1, #IRQ_MODE_BITS @ Was an interrupt taken in IRQ mode before we + @ got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore @ Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore @ Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_fiq_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore @ No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_fiq_preempt_restore: +@ + LDMIA sp!, {r3, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR_c, r2 @ Reenter FIQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block */ +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_fiq_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_fiq_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + ADD sp, sp, #24 @ Recover FIQ stack space + MOV r3, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r3 @ Lockout interrupts + B _tx_thread_schedule @ Return to scheduler +@ +@} + diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S new file mode 100644 index 00000000..44dbcf7d --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_context_save.S @@ -0,0 +1,204 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_fiq_processing_return + .global _tx_execution_isr_enter +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@ VOID _tx_thread_fiq_context_save(VOID) +@{ + .global _tx_thread_fiq_context_save + .type _tx_thread_fiq_context_save,function +_tx_thread_fiq_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +__tx_thread_fiq_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, lr} @ Store other registers, Note that we don't +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested +@ @ interrupt processing does need to save +@ @ these registers. +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_fiq_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif +@ +@ /* Not much to do here, save the current SPSR and LR for possible +@ use in IRQ interrupted in idle system conditions, and return to +@ FIQ interrupt processing. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, lr} @ Store other registers that will get used +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@} + diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S new file mode 100644 index 00000000..884f3347 --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_end.S @@ -0,0 +1,116 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +FIQ_MODE_BITS = 0x11 @ FIQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_end(VOID) +@{ + .global _tx_thread_fiq_nesting_end + .type _tx_thread_fiq_nesting_end,function +_tx_thread_fiq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode + +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S new file mode 100644 index 00000000..f80d74b6 --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_fiq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +FIQ_DISABLE = 0x40 @ FIQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_start(VOID) +@{ + .global _tx_thread_fiq_nesting_start + .type _tx_thread_fiq_nesting_start,function +_tx_thread_fiq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..ff7db62d --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" */ +@ + +INT_MASK = 0x03F + +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_control +$_tx_thread_interrupt_control: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_control(UINT new_posture) +@{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r3, CPSR @ Pickup current CPSR + MOV r2, #INT_MASK @ Build interrupt mask + AND r1, r3, r2 @ Clear interrupt lockout bits + ORR r1, r1, r0 @ Or-in new interrupt lockout bits +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r1 @ Setup new CPSR + BIC r0, r3, r2 @ Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..a65b911d --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_disable.S @@ -0,0 +1,113 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_disable +$_tx_thread_interrupt_disable: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_disable(void) +@{ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r0, CPSR @ Pickup current CPSR +@ +@ /* Mask interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ +#else + CPSID i @ Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..4bea9e52 --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_interrupt_restore.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_restore +$_tx_thread_interrupt_restore: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring interrupts to the state */ +@/* returned by a previous _tx_thread_interrupt_disable call. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_restore(UINT old_posture) +@{ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r0 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..35284eed --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_end(VOID) +@{ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..6b702e93 --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +IRQ_DISABLE = 0x80 @ IRQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_start(VOID) +@{ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a5/gnu/src/tx_thread_schedule.S b/ports/cortex_a5/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..df86a053 --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_schedule.S @@ -0,0 +1,255 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_execution_thread_enter +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_schedule + .type $_tx_thread_schedule,function +$_tx_thread_schedule: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_schedule @ Call _tx_thread_schedule function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: +@ +@ /* Enable interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if @ Enable IRQ and FIQ interrupts +#else + CPSIE i @ Enable IRQ interrupts +#endif +@ +@ /* Wait for a thread to execute. */ +@ do +@ { + LDR r1, =_tx_thread_execute_ptr @ Address of thread execute ptr +@ +__tx_thread_schedule_loop: +@ + LDR r0, [r1] @ Pickup next thread to execute + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_schedule_loop @ If so, keep looking for a thread +@ +@ } +@ while(_tx_thread_execute_ptr == TX_NULL); +@ +@ /* Yes! We have a thread to execute. Lockout interrupts and +@ transfer control to it. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Setup the current thread pointer. */ +@ _tx_thread_current_ptr = _tx_thread_execute_ptr; +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + STR r0, [r1] @ Setup current thread pointer +@ +@ /* Increment the run count for this thread. */ +@ _tx_thread_current_ptr -> tx_thread_run_count++; +@ + LDR r2, [r0, #4] @ Pickup run counter + LDR r3, [r0, #24] @ Pickup time-slice for this thread + ADD r2, r2, #1 @ Increment thread run-counter + STR r2, [r0, #4] @ Store the new run counter +@ +@ /* Setup time-slice, if present. */ +@ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + @ variable + LDR sp, [r0, #8] @ Switch stack pointers + STR r3, [r2] @ Setup time-slice +@ +@ /* Switch to the thread's stack. */ +@ sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + MOV r5, r0 @ Save r0 + BL _tx_execution_thread_enter @ Call the thread execution enter function + MOV r0, r5 @ Restore r0 +#endif +@ +@ /* Determine if an interrupt frame or a synchronous task suspension frame +@ is present. */ +@ + LDMIA sp!, {r4, r5} @ Pickup the stack type and saved CPSR + CMP r4, #0 @ Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 @ Setup SPSR for return +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore @ No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} @ Recover D0-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt + +_tx_solicited_return: + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore @ No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} @ Recover D8-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 @ Recover CPSR + LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ + +#ifdef TX_ENABLE_VFP_SUPPORT + + .global tx_thread_vfp_enable + .type tx_thread_vfp_enable,function +tx_thread_vfp_enable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable + MOV r0, #1 @ Build enable value + STR r0, [r1, #144] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + + .global tx_thread_vfp_disable + .type tx_thread_vfp_disable,function +tx_thread_vfp_disable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable + MOV r0, #0 @ Build disable value + STR r0, [r1, #144] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + +#endif + diff --git a/ports/cortex_a5/gnu/src/tx_thread_stack_build.S b/ports/cortex_a5/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..90f28e0b --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,178 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ + .arm + +SVC_MODE = 0x13 @ SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ interrupts enabled +#else +CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interrupts enabled +#endif +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_thread_stack_build + .type $_tx_thread_stack_build,function +$_tx_thread_stack_build: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_stack_build @ Call _tx_thread_stack_build function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-A5 should look like the following after it is built: +@ +@ Stack Top: 1 Interrupt stack frame type +@ CPSR Initial value for CPSR +@ a1 (r0) Initial value for a1 +@ a2 (r1) Initial value for a2 +@ a3 (r2) Initial value for a3 +@ a4 (r3) Initial value for a4 +@ v1 (r4) Initial value for v1 +@ v2 (r5) Initial value for v2 +@ v3 (r6) Initial value for v3 +@ v4 (r7) Initial value for v4 +@ v5 (r8) Initial value for v5 +@ sb (r9) Initial value for sb +@ sl (r10) Initial value for sl +@ fp (r11) Initial value for fp +@ ip (r12) Initial value for ip +@ lr (r14) Initial value for lr +@ pc (r15) Initial value for pc +@ 0 For stack backtracing +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #7 @ Ensure 8-byte alignment + SUB r2, r2, #76 @ Allocate space for the stack frame +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #1 @ Build interrupt stack type + STR r3, [r2, #0] @ Store stack type + MOV r3, #0 @ Build initial register value + STR r3, [r2, #8] @ Store initial r0 + STR r3, [r2, #12] @ Store initial r1 + STR r3, [r2, #16] @ Store initial r2 + STR r3, [r2, #20] @ Store initial r3 + STR r3, [r2, #24] @ Store initial r4 + STR r3, [r2, #28] @ Store initial r5 + STR r3, [r2, #32] @ Store initial r6 + STR r3, [r2, #36] @ Store initial r7 + STR r3, [r2, #40] @ Store initial r8 + STR r3, [r2, #44] @ Store initial r9 + LDR r3, [r0, #12] @ Pickup stack starting address + STR r3, [r2, #48] @ Store initial r10 (sl) + LDR r3,=_tx_thread_schedule @ Pickup address of _tx_thread_schedule for GDB backtrace + STR r3, [r2, #60] @ Store initial r14 (lr) + MOV r3, #0 @ Build initial register value + STR r3, [r2, #52] @ Store initial r11 + STR r3, [r2, #56] @ Store initial r12 + STR r1, [r2, #64] @ Store initial pc + STR r3, [r2, #68] @ 0 for back-trace + MRS r1, CPSR @ Pickup CPSR + BIC r1, r1, #CPSR_MASK @ Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] @ Store initial CPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a5/gnu/src/tx_thread_system_return.S b/ports/cortex_a5/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..7c2878de --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_system_return.S @@ -0,0 +1,180 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm +@ +@ + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_execution_thread_exit +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_system_return + .type $_tx_thread_system_return,function +$_tx_thread_system_return: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_system_return @ Call _tx_thread_system_return function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_system_return(VOID) +@{ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: +@ +@ /* Save minimal context on the stack. */ +@ + STMDB sp!, {r4-r11, lr} @ Save minimal context + + LDR r4, =_tx_thread_current_ptr @ Pickup address of current ptr + LDR r5, [r4] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r5, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save @ No, skip VFP solicited save + VMRS r1, FPSCR @ Pickup the FPSCR + STR r1, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D8-D15} @ Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 @ Build a solicited stack type + MRS r1, CPSR @ Pickup the CPSR + STMDB sp!, {r0-r1} @ Save type and CPSR +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + BL _tx_execution_thread_exit @ Call the thread exit function +#endif + MOV r3, r4 @ Pickup address of current ptr + MOV r0, r5 @ Pickup current thread pointer + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + LDR r1, [r2] @ Pickup current time slice +@ +@ /* Save current stack and switch to system stack. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ sp = _tx_thread_system_stack_ptr; +@ + STR sp, [r0, #8] @ Save thread stack pointer +@ +@ /* Determine if the time-slice is active. */ +@ if (_tx_timer_time_slice) +@ { +@ + MOV r4, #0 @ Build clear value + CMP r1, #0 @ Is a time-slice active? + BEQ __tx_thread_dont_save_ts @ No, don't save the time-slice +@ +@ /* Save time-slice for the thread and clear the current time-slice. */ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r4, [r2] @ Clear time-slice + STR r1, [r0, #24] @ Save current time-slice +@ +@ } +__tx_thread_dont_save_ts: +@ +@ /* Clear the current thread pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + STR r4, [r3] @ Clear current thread pointer + B _tx_thread_schedule @ Jump to scheduler! +@ +@} + diff --git a/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..de6a5a7c --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_thread_vectored_context_save.S @@ -0,0 +1,190 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_execution_isr_enter +@ +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_vectored_context_save(VOID) +@{ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #32 @ Recover saved registers + MOV pc, lr @ Return to caller +@ +@ } +@} + diff --git a/ports/cortex_a5/gnu/src/tx_timer_interrupt.S b/ports/cortex_a5/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..cdecf06c --- /dev/null +++ b/ports/cortex_a5/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,279 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ + .arm + +@ +@/* Define Assembly language external references... */ +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_timer_interrupt + .type $_tx_timer_interrupt,function +$_tx_timer_interrupt: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_timer_interrupt @ Call _tx_timer_interrupt function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-A5/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1] @ Pickup current timer + LDR r2, [r0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wraparound. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup address of timer list end + LDR r2, [r3] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wraparound logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup address of timer list start + LDR r0, [r3] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + LDR r2, [r3] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup address of other expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup address of expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r2, [r3] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} + diff --git a/ports/cortex_a5/iar/example_build/azure_rtos.eww b/ports/cortex_a5/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..17e0d329 --- /dev/null +++ b/ports/cortex_a5/iar/example_build/azure_rtos.eww @@ -0,0 +1,13 @@ + + + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\tx.ewp + + + + + diff --git a/ports/cortex_a5/iar/example_build/cstartup.s b/ports/cortex_a5/iar/example_build/cstartup.s new file mode 100644 index 00000000..647de2e8 --- /dev/null +++ b/ports/cortex_a5/iar/example_build/cstartup.s @@ -0,0 +1,156 @@ + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 14520 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector + PUBLIC __vector_0x14 + PUBLIC __iar_program_start + EXTERN __tx_undefined + EXTERN __tx_swi_interrupt + EXTERN __tx_prefetch_handler + EXTERN __tx_abort_handler + EXTERN __tx_irq_handler + EXTERN __tx_fiq_handler + + ARM +__vector: + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort +__vector_0x14: + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + +Reset_Addr: DCD __iar_program_start +Undefined_Addr: DCD __tx_undefined +SWI_Addr: DCD __tx_swi_interrupt +Prefetch_Addr: DCD __tx_prefetch_handler +Abort_Addr: DCD __tx_abort_handler +IRQ_Addr: DCD __tx_irq_handler +FIQ_Addr: DCD __tx_fiq_handler + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reser execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + +; PUBLIC ?cstartup + EXTERN ?main + REQUIRE __vector + + ARM + +__iar_program_start: +?cstartup: + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR + +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + + + MRS r0, cpsr ; Original PSR value + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + +#ifdef __ARMVFP__ + MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register + ORR r1, r1, #(0xf << 20) ; Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 ; Flush prefetch buffer because of FMXR below and + ; CP 10 & 11 were only just enabled + MOV r0, #0x40000000 ; Enable VFP itself + FMXR FPEXC, r0 ; FPEXC = r0 +#endif + +; +; Add more initialization here +; + +; Continue to ?main for C-level initialization. + + B ?main + + END + + + diff --git a/ports/cortex_a5/iar/example_build/sample_threadx.c b/ports/cortex_a5/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..68cd97fe --- /dev/null +++ b/ports/cortex_a5/iar/example_build/sample_threadx.c @@ -0,0 +1,374 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define byte pool memory. */ + +UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a5/iar/example_build/sample_threadx.dep b/ports/cortex_a5/iar/example_build/sample_threadx.dep new file mode 100644 index 00000000..5846d006 --- /dev/null +++ b/ports/cortex_a5/iar/example_build/sample_threadx.dep @@ -0,0 +1,220 @@ + + + 4 + 1484414870 + + Debug + + $PROJ_DIR$\Debug\Obj\demo.r79 + $TOOLKIT_DIR$\inc\ycheck.h + $TOOLKIT_DIR$\inc\yvals.h + $PROJ_DIR$\Debug\List\sample_threadx.map + $TOOLKIT_DIR$\inc\xencoding_limits.h + $TOOLKIT_DIR$\inc\intrinsics.h + $TOOLKIT_DIR$\inc\DLib_Defaults.h + $TOOLKIT_DIR$\inc\DLib_Threads.h + $PROJ_DIR$\TX_ILL.s79 + $PROJ_DIR$\Debug\Obj\tx_initialize_low_level.o + $TOOLKIT_DIR$\inc\DLib_Product.h + $PROJ_DIR$\tx_cstartup.s79 + $PROJ_DIR$\Debug\Obj\cstartup.o + $TOOLKIT_DIR$\inc\DLib_Product_string.h + $TOOLKIT_DIR$\inc\ysizet.h + $TOOLKIT_DIR$\lib\sh7Sxs_l.a + $TOOLKIT_DIR$\inc\c\stdlib.h + $PROJ_DIR$\Debug\List\cstartup.lst + $PROJ_DIR$\DEMO.C + $PROJ_DIR$\Debug\List\tx_initialize_low_level.lst + $TOOLKIT_DIR$\inc\stdlib.h + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $PROJ_DIR$\Debug\Obj\tx_execution_profile.pbi + $PROJ_DIR$\tx_execution_profile.c + $PROJ_DIR$\sample_threadx.icf + $TOOLKIT_DIR$\inc\c\ycheck.h + $PROJ_DIR$\Debug\Obj\tx_execution_profile.o + $TOOLKIT_DIR$\inc\DLib_Config_Normal.h + $TOOLKIT_DIR$\inc\c\ysizet.h + $PROJ_DIR$\Debug\Obj\TX_ILL.r79 + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $PROJ_DIR$\Debug\Exe\tx.a + $PROJ_DIR$\tx_api.h + $PROJ_DIR$\tx_initialize_low_level.s + $PROJ_DIR$\cstartup.s79 + $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h + $TOOLKIT_DIR$\inc\c\string.h + $PROJ_DIR$\tx_initialize_low_level.s79 + $PROJ_DIR$\sample_threadx.c + $PROJ_DIR$\Debug\Obj\sample_threadx.pbd + $PROJ_DIR$\Debug\Exe\sample_threadx.out + $PROJ_DIR$\tx_port.h + $PROJ_DIR$\cstartup.s + $TOOLKIT_DIR$\inc\c\intrinsics.h + $TOOLKIT_DIR$\lib\m7Sx_tl.a + $PROJ_DIR$\Debug\Obj\sample_threadx.__cstat.et + $TOOLKIT_DIR$\lib\dl7Sx_tln.a + $PROJ_DIR$\Debug\Obj\sample_threadx.o + $TOOLKIT_DIR$\lib\rt7Sx_tl.a + $PROJ_DIR$\Debug\Obj\tx_cstartup.r79 + $TOOLKIT_DIR$\inc\string.h + $PROJ_DIR$\Debug\Obj\sample_threadx.xcl + $TOOLKIT_DIR$\inc\c\yvals.h + $TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h + $TOOLKIT_DIR$\inc\c\DLib_Product_string.h + $TOOLKIT_DIR$\inc\c\iar_intrinsics_common.h + $TOOLKIT_DIR$\inc\c\iccarm_builtin.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_api.h + $PROJ_DIR$\..\inc\tx_port.h + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_receive.c + + + [ROOT_NODE] + + + ILINK + 40 3 + + + + + $PROJ_DIR$\TX_ILL.s79 + + + AARM + 29 + + + + + $PROJ_DIR$\tx_cstartup.s79 + + + AARM + 49 + + + + + $PROJ_DIR$\DEMO.C + + + ICCARM + 0 + + + + + ICCARM + 32 41 + + + + + $PROJ_DIR$\tx_execution_profile.c + + + ICCARM + 26 + + + BICOMP + 22 + + + + + ICCARM + 32 41 20 1 2 6 27 10 4 7 14 50 13 5 + + + BICOMP + 32 41 20 1 2 6 10 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$PROJ_DIR$\tx_initialize_low_level.s + + + diff --git a/ports/cortex_a5/iar/example_build/sample_threadx.icf b/ports/cortex_a5/iar/example_build/sample_threadx.icf new file mode 100644 index 00000000..9c95e1d1 --- /dev/null +++ b/ports/cortex_a5/iar/example_build/sample_threadx.icf @@ -0,0 +1,49 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x80; +define symbol __ICFEDIT_region_ROM_end__ = 0x1FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x100000; +define symbol __ICFEDIT_region_RAM_end__ = 0x1FFFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_size_freemem__ = 0x100000; + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_freemem = mem:[from 0x200000 to 0x300000]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}; + +place in RAM_region { last section FREE_MEM}; \ No newline at end of file diff --git a/ports/cortex_a5/iar/example_build/settings/azure_rtos.wsdt b/ports/cortex_a5/iar/example_build/settings/azure_rtos.wsdt new file mode 100644 index 00000000..5d070138 --- /dev/null +++ b/ports/cortex_a5/iar/example_build/settings/azure_rtos.wsdt @@ -0,0 +1,535 @@ + + + + + sample_threadx/Debug + tx/Debug + + sample_threadx + 1 + + + + + 21 + 2518 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+ + + 34050 + 0A0000000A0000006E0000006E000000 + 0000000000000000FE0200001A000000 + 8192 + 0 + 0 + 744 + 0 + + + 1 + + + + 34048 + 34049 + 34050 + 34051 + 34052 + 34053 + 34054 + 34055 + 34056 + 34057 + 34058 + 34059 + 34060 + 34061 + 34062 + 34063 + 34064 + 34065 + + + + 01000000030000000100000000000000000000000100000001000000FFFFFFFF00000000010000000100000000000000280000002800000000000000 + + + + diff --git a/ports/cortex_a5/iar/example_build/settings/sample_threadx.Debug.cspy.bat b/ports/cortex_a5/iar/example_build/settings/sample_threadx.Debug.cspy.bat new file mode 100644 index 00000000..ad03338f --- /dev/null +++ b/ports/cortex_a5/iar/example_build/settings/sample_threadx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports/cortex_a5/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports/cortex_a5/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 new file mode 100644 index 00000000..de4f156b --- /dev/null +++ b/ports/cortex_a5/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} diff --git a/ports/cortex_a5/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports/cortex_a5/iar/example_build/settings/sample_threadx.Debug.driver.xcl new file mode 100644 index 00000000..50057893 --- /dev/null +++ b/ports/cortex_a5/iar/example_build/settings/sample_threadx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-A5" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/cortex_a5/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports/cortex_a5/iar/example_build/settings/sample_threadx.Debug.general.xcl new file mode 100644 index 00000000..22442691 --- /dev/null +++ b/ports/cortex_a5/iar/example_build/settings/sample_threadx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5\iar\example_build\Debug\Exe\sample_threadx.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports/cortex_a5/iar/example_build/settings/sample_threadx.crun b/ports/cortex_a5/iar/example_build/settings/sample_threadx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/cortex_a5/iar/example_build/settings/sample_threadx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports/cortex_a5/iar/example_build/settings/sample_threadx.dbgdt b/ports/cortex_a5/iar/example_build/settings/sample_threadx.dbgdt new file mode 100644 index 00000000..57b93b13 --- /dev/null +++ b/ports/cortex_a5/iar/example_build/settings/sample_threadx.dbgdt @@ -0,0 +1,1385 @@ + + + + + 34048 + 34049 + 34050 + 34051 + 34052 + 34053 + 34054 + 34055 + 34056 + 34057 + 34058 + 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+++ b/ports/cortex_a5/iar/example_build/settings/tx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports/cortex_a5/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports/cortex_a5/iar/example_build/settings/tx.Debug.cspy.ps1 new file mode 100644 index 00000000..6a1889c0 --- /dev/null +++ b/ports/cortex_a5/iar/example_build/settings/tx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} diff --git a/ports/cortex_a5/iar/example_build/settings/tx.Debug.driver.xcl b/ports/cortex_a5/iar/example_build/settings/tx.Debug.driver.xcl new file mode 100644 index 00000000..50057893 --- /dev/null +++ b/ports/cortex_a5/iar/example_build/settings/tx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-A5" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/cortex_a5/iar/example_build/settings/tx.Debug.general.xcl b/ports/cortex_a5/iar/example_build/settings/tx.Debug.general.xcl new file mode 100644 index 00000000..deeeb2f9 --- /dev/null +++ b/ports/cortex_a5/iar/example_build/settings/tx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armsim2.dll" + +"C:\release\threadx\Debug\Exe\tx.out" + +--plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armbat.dll" + + + + diff --git a/ports/cortex_a5/iar/example_build/settings/tx.crun b/ports/cortex_a5/iar/example_build/settings/tx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/cortex_a5/iar/example_build/settings/tx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports/cortex_a5/iar/example_build/settings/tx.dbgdt b/ports/cortex_a5/iar/example_build/settings/tx.dbgdt new file mode 100644 index 00000000..73e71f6e --- /dev/null +++ b/ports/cortex_a5/iar/example_build/settings/tx.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports/cortex_a5/iar/example_build/settings/tx.dnx b/ports/cortex_a5/iar/example_build/settings/tx.dnx new file mode 100644 index 00000000..1872e83f --- /dev/null +++ b/ports/cortex_a5/iar/example_build/settings/tx.dnx @@ -0,0 +1,58 @@ + + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports/cortex_a5/iar/example_build/tx.dep b/ports/cortex_a5/iar/example_build/tx.dep new file mode 100644 index 00000000..e9942276 --- /dev/null +++ b/ports/cortex_a5/iar/example_build/tx.dep @@ -0,0 +1,10500 @@ + + + 4 + 2746525381 + + Debug + + $PROJ_DIR$\tx_block_pool_performance_system_info_get.c + $PROJ_DIR$\tx_block_pool_prioritize.c + $PROJ_DIR$\tx_block_pool_initialize.c + $PROJ_DIR$\tx_byte_allocate.c + $PROJ_DIR$\tx_byte_pool_cleanup.c + $PROJ_DIR$\tx_api.h + $PROJ_DIR$\tx_block_pool_create.c + $PROJ_DIR$\tx_block_release.c + $PROJ_DIR$\tx_byte_pool_create.c + $PROJ_DIR$\tx_byte_pool_delete.c + $PROJ_DIR$\tx_byte_pool.h + $PROJ_DIR$\tx_block_pool_info_get.c + $PROJ_DIR$\tx_byte_pool_info_get.c + $PROJ_DIR$\tx_block_pool_performance_info_get.c + $PROJ_DIR$\tx_block_allocate.c + $PROJ_DIR$\tx_block_pool.h + $PROJ_DIR$\tx_block_pool_cleanup.c + $PROJ_DIR$\tx_block_pool_delete.c + $PROJ_DIR$\tx_mutex_get.c + $PROJ_DIR$\tx_byte_pool_performance_info_get.c + $PROJ_DIR$\tx_mutex_info_get.c + $PROJ_DIR$\tx_mutex_initialize.c + $PROJ_DIR$\tx_mutex_performance_info_get.c + $PROJ_DIR$\tx_mutex_performance_system_info_get.c + $PROJ_DIR$\tx_event_flags_info_get.c + $PROJ_DIR$\tx_byte_pool_initialize.c + $PROJ_DIR$\tx_byte_pool_prioritize.c + $PROJ_DIR$\tx_event_flags.h + $PROJ_DIR$\tx_initialize_kernel_enter.c + $PROJ_DIR$\tx_event_flags_create.c + $PROJ_DIR$\tx_event_flags_performance_system_info_get.c + $PROJ_DIR$\tx_event_flags_set_notify.c + $PROJ_DIR$\tx_event_flags_performance_info_get.c + $PROJ_DIR$\tx_event_flags_set.c + $PROJ_DIR$\tx_byte_pool_performance_system_info_get.c + $PROJ_DIR$\tx_event_flags_cleanup.c + $PROJ_DIR$\tx_event_flags_get.c + $PROJ_DIR$\tx_iar.c + $PROJ_DIR$\tx_initialize.h + $PROJ_DIR$\tx_event_flags_initialize.c + $PROJ_DIR$\tx_mutex.h + $PROJ_DIR$\tx_mutex_cleanup.c + $PROJ_DIR$\tx_byte_release.c + $PROJ_DIR$\tx_initialize_kernel_setup.c + $PROJ_DIR$\tx_byte_pool_search.c + $PROJ_DIR$\tx_event_flags_delete.c + $PROJ_DIR$\tx_initialize_high_level.c + $PROJ_DIR$\tx_mutex_create.c + $PROJ_DIR$\tx_mutex_delete.c + $PROJ_DIR$\Debug\Obj\tx_thread_stack_error_notify.__cstat.et + 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$PROJ_DIR$\..\..\..\..\common\src\txe_thread_resume.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_suspend.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_terminate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_time_slice_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c + + + diff --git a/ports/cortex_a5/iar/example_build/tx_initialize_low_level.s b/ports/cortex_a5/iar/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..5369491b --- /dev/null +++ b/ports/cortex_a5/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,327 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; Disable irq,fiq SVC mode +IRQ_MODE DEFINE 0xD2 ; Disable irq,fiq IRQ mode +FIQ_MODE DEFINE 0xD1 ; Disable irq,fiq FIQ mode +SYS_MODE DEFINE 0xDF ; Disable irq,fiq SYS mode +; +; + + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_thread_context_save +; EXTERN _tx_thread_vectored_context_save + EXTERN _tx_thread_context_restore +#ifdef TX_ENABLE_FIQ_SUPPORT + EXTERN _tx_thread_fiq_context_save + EXTERN _tx_thread_fiq_context_restore +#endif +#ifdef TX_ENABLE_IRQ_NESTING + EXTERN _tx_thread_irq_nesting_start + EXTERN _tx_thread_irq_nesting_end +#endif +#ifdef TX_ENABLE_FIQ_NESTING + EXTERN _tx_thread_fiq_nesting_start + EXTERN _tx_thread_fiq_nesting_end +#endif + EXTERN _tx_timer_interrupt + EXTERN ?cstartup + EXTERN _tx_build_options + EXTERN _tx_version_id +; +; +; +;/* Define the FREE_MEM segment that will specify where free memory is +; defined. This must also be located in at the end of other RAM segments +; in the linker control file. The value of this segment is what is passed +; to tx_application_define. */ +; + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + CODE32 + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level +; +; /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode. */ +; +; /* Remember the stack pointer, link register, and switch to SVC mode. */ +; + MOV r0, sp ; Remember the SP + MOV r1, lr ; Remember the LR + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r3 ; Switch to SVC mode + MOV sp, r0 ; Inherit the stack pointer setup by cstartup + MOV lr, r1 ; Inherit the link register +; +; /* Pickup the start of free memory. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) FREE_MEM; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Done, return to caller. */ +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +;/* Define shells for each of the interrupt vectors. */ +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt ; Software interrupt handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_prefetch_handler +__tx_prefetch_handler + B __tx_prefetch_handler ; Prefetch exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_abort_handler +__tx_abort_handler + B __tx_abort_handler ; Abort exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +; +; /* For debug purpose, execute the timer interrupt processing here. In +; a real system, some kind of status indication would have to be checked +; before the timer interrupt handler could be called. */ +; + BL _tx_timer_interrupt ; Timer interrupt handler +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; +; RSEG .text:CODE:NOROOT(2) +; PUBLIC __tx_example_vectored_irq_handler +;__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +;#endif +; +; /* Application IRQ handler is called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +;#endif +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; +#else + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler +#endif +; +; +BUILD_OPTIONS + DC32 _tx_build_options ; Reference to ensure it comes in +VERSION_ID + DC32 _tx_version_id ; Reference to ensure it comes in + END + diff --git a/ports/cortex_a5/iar/inc/tx_port.h b/ports/cortex_a5/iar/inc/tx_port.h new file mode 100644 index 00000000..7c107cdf --- /dev/null +++ b/ports/cortex_a5/iar/inc/tx_port.h @@ -0,0 +1,397 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A5/IAR */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#if __CORE__ > __ARM4TM__ + +#if __CPU_MODE__ == 2 + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (UINT) __CLZ(m); \ + b = 31 - b; +#endif +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +/* First, check and see what mode the file is being compiled in. The IAR compiler + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros + are available. Otherwise, if Thumb mode is present, we must use function calls. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else +#if __CPU_MODE__ == 2 + +#if (__VER__ < 8002000) +__intrinsic unsigned long __get_CPSR(); +__intrinsic void __set_CPSR( unsigned long ); +#endif + + +#if (__VER__ < 8002000) +#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#else +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#endif + +#define TX_DISABLE interrupt_save = __get_CPSR(); \ + __set_CPSR(interrupt_save | TX_INT_DISABLE); +#define TX_RESTORE __set_CPSR(interrupt_save); + +#else + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#endif +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A9. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/IAR Version 6.0 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + + diff --git a/ports/cortex_a5/iar/readme_threadx.txt b/ports/cortex_a5/iar/readme_threadx.txt new file mode 100644 index 00000000..b3b9f85c --- /dev/null +++ b/ports/cortex_a5/iar/readme_threadx.txt @@ -0,0 +1,544 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A5 + + Thumb & 32-bit Mode + + Using the IAR Tools + +1. Building the ThreadX run-time Library + +Building the ThreadX library is easy. First, open the Azure RTOS workspace +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by +the application. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the IAR +Windows-based Cortex-A5 simulator. + +Building the demonstration is easy; simply make the sample_threadx.ewp project +the "active project" in the IAR Embedded Workbench and select the +"Make" button. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a +binary file that can be downloaded and executed on IAR's Cortex-A5 simulator. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A5 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. +By default, the vector area is defined at the top of cstartup.s, which is +a slightly modified from the base IAR file. + +The _tx_initialize_low_level function inside of tx_initialize_low_level.s +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all +other RAM sections in memory. + + +4. Register Usage and Stack Frames + +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +5. Conditional Compilation Switches + +The following are conditional compilation options for building the ThreadX library +and application: + + + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + FIQ interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + + TX_ENABLE_IRQ_NESTING This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. + + TX_ENABLE_FIQ_NESTING This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. In addition, + IRQ nesting should also be enabled. + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + TX_THUMB Defined, this option enables the BX LR calling return sequence + in assembly files, to ensure correct operation on systems that + use both ARM and Thumb mode. By default, this option is + not defined + + + + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the ThreadX library +project to enable various compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A5 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A5 vectors start at address zero. The demonstration system startup +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + PUBLIC __tx_irq_handler + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR dispatch call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_example_vectored_irq_handler +__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers + BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR dispatch call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +; + BL _tx_thread_irq_nesting_start + +; /* Application ISR dispatch call goes here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +; + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ dispatch call goes here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in +preparation for the FIQ context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ dispatch call goes here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +in the IRQ processing. + + +9. Thumb/Cortex-A5 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire +ThreadX assembly source should be built with TX_THUMB defined. + + +10. IAR Thread-safe Library Support + +Thread-safe support for the IAR tools is easily enabled by building the ThreadX library +and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file +should have the following line added (if not already in place): + +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application + +The project options "General Options -> Library Configuration" should also have the +"Enable thread support in library" box selected. + + +11. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + + +12. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX version 6.0.1 for Cortex-A5 using IAR's ARM tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a5/iar/src/tx_iar.c b/ports/cortex_a5/iar/src/tx_iar.c new file mode 100644 index 00000000..11fcefb3 --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports/cortex_a5/iar/src/tx_thread_context_restore.s b/ports/cortex_a5/iar/src/tx_thread_context_restore.s new file mode 100644 index 00000000..b212254e --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_context_restore.s @@ -0,0 +1,261 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +SVC_MODE DEFINE 0xD3 ; SVC mode +IRQ_MODE DEFINE 0xD2 ; IRQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +THUMB_MASK DEFINE 0x20 ; Thumb bit mask +SVC_MODE_BITS DEFINE 0x13 ; SVC mode value + +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_restore + CODE32 +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + MRS r3, CPSR ; Pickup current CPSR + ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value + MSR CPSR_cxsf, r0 ; Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR +#ifdef __D32__ + VSTMDB sp!, {D16-D31} ; Save D16-D31 +#endif + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block + BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS ; Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 ; Lockout interrupts +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r3, r3, #MODE_MASK ; Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +;} +; +; + END + diff --git a/ports/cortex_a5/iar/src/tx_thread_context_save.s b/ports/cortex_a5/iar/src/tx_thread_context_save.s new file mode 100644 index 00000000..63733553 --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_context_save.s @@ -0,0 +1,210 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif + + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_irq_processing_return + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_save + CODE32 +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r0 ; Disable interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + +; +; + END + diff --git a/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..64a1a9eb --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,272 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; SVC mode +FIQ_MODE DEFINE 0xD1 ; FIQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +THUMB_MASK DEFINE 0x20 ; Thumb bit mask +IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits +SVC_MODE_BITS DEFINE 0x13 ; SVC mode value + +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_restore + CODE32 +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + MRS r3, CPSR ; Pickup current CPSR + ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value + MSR CPSR_cxsf, r0 ; Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_cxsf, r2 ; Re-enter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR +#ifdef __D32__ + VSTMDB sp!, {D16-D31} ; Save D16-D31 +#endif + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block */ + BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS ; Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 ; Lockout interrupts +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MRS r3, CPSR ; Pickup current CPSR + BIC r3, r3, #MODE_MASK ; Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +; +;} +; +; + END + diff --git a/ports/cortex_a5/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a5/iar/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..22e2d0c7 --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_fiq_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_fiq_processing_return + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_save + CODE32 +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} +; +; + END + diff --git a/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..368cec31 --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,109 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_end + CODE32 +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_cxsf, r0 ; Disable interrupts + LDR lr, [sp] ; Pickup saved lr + ADD sp, sp, #4 ; Adjust stack pointer + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_cxsf, r0 ; Re-enter IRQ mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..00f81c4e --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit +MODE_MASK DEFINE 0x1F ; Mode mask +SYS_MODE_BITS DEFINE 0x1F ; System mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_start + CODE32 +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + STR lr, [sp, #-4]! ; Push the system mode lr on the system mode stack + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a5/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a5/iar/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..76b0d89c --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_interrupt_control.s @@ -0,0 +1,103 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +INT_MASK DEFINE 0xC0 ; Interrupt bit mask +#else +INT_MASK DEFINE 0x80 ; Interrupt bit mask +#endif +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_control + CODE32 +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} +; +; + END diff --git a/ports/cortex_a5/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a5/iar/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..b892e436 --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_interrupt_disable.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_disable + CODE32 +_tx_thread_interrupt_disable??rA +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + ORR r1, r0, #DISABLE_INTS ; Mask interrupts + MSR CPSR_cxsf, r1 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +; + END diff --git a/ports/cortex_a5/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a5/iar/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..84827bbd --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;void _tx_thread_interrupt_restore(UINT old_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_restore + CODE32 +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r0 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; + END diff --git a/ports/cortex_a5/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a5/iar/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..755d2280 --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_end + CODE32 +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_cxsf, r0 ; Disable interrupts + LDR lr, [sp] ; Pickup saved lr + ADD sp, sp, #4 ; Adjust stack pointer + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_cxsf, r0 ; Re-enter IRQ mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a5/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a5/iar/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..66ff64dd --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +IRQ_DISABLE DEFINE 0x80 ; IRQ disable bit +MODE_MASK DEFINE 0x1F ; Mode mask +SYS_MODE_BITS DEFINE 0x1F ; System mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_start + CODE32 +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + STR lr, [sp, #-4]! ; Push the system mode lr on the system mode stack + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a5/iar/src/tx_thread_schedule.s b/ports/cortex_a5/iar/src/tx_thread_schedule.s new file mode 100644 index 00000000..6c07f922 --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_schedule.s @@ -0,0 +1,243 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask +#else +ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask +#endif +; +; + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_execution_thread_enter +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_schedule + CODE32 +_tx_thread_schedule??rA +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + MRS r2, CPSR ; Pickup CPSR + BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s) + MSR CPSR_cxsf, r0 ; Enable interrupts +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + MSR CPSR_cxsf, r2 ; Disable interrupts +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ; variable + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 +#endif +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 ; Setup SPSR for return +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 +#ifdef __D32__ + VLDMIA sp!, {D16-D31} ; Recover D16-D31 +#endif + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + +_tx_solicited_return: +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 +#ifdef __D32__ + VLDMIA sp!, {D16-D31} ; Recover D16-D31 +#endif + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 ; Recover CPSR + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} +; + +#ifdef __ARMVFP__ + PUBLIC tx_thread_vfp_enable + CODE32 +tx_thread_vfp_enable??rA +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if ; Enable IRQ and FIQ interrupts +#else + CPSIE i ; Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + PUBLIC tx_thread_vfp_disable + CODE32 +tx_thread_vfp_disable??rA +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if ; Enable IRQ and FIQ interrupts +#else + CPSIE i ; Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller +#endif + + END + diff --git a/ports/cortex_a5/iar/src/tx_thread_stack_build.s b/ports/cortex_a5/iar/src/tx_thread_stack_build.s new file mode 100644 index 00000000..efa63ed9 --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_stack_build.s @@ -0,0 +1,158 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE DEFINE 0x13 ; SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK DEFINE 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled +#else +CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled +#endif +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_stack_build + + CODE32 +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A5 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure long-word alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + MRS r1, CPSR ; Pickup CPSR + BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} + END + diff --git a/ports/cortex_a5/iar/src/tx_thread_system_return.s b/ports/cortex_a5/iar/src/tx_thread_system_return.s new file mode 100644 index 00000000..457af6d0 --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_system_return.s @@ -0,0 +1,164 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif +; +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_execution_thread_exit +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_system_return + CODE32 +_tx_thread_system_return??rA +_tx_thread_system_return +; +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context + LDR r5, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r6, [r5, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r0, [r6, #144] ; Pickup the VFP enabled flag + CMP r0, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR +#ifdef __D32__ + VSTMDB sp!, {D16-D31} ; Save D16-D31 +#endif + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 ; Build a solicited stack type + MRS r1, CPSR ; Pickup the CPSR + STMDB sp!, {r0-r1} ; Save type and CPSR +; +; /* Lockout interrupts. */ +; + ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r2 ; Disable interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function +#endif + + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r6, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r6, #24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r5, #0] ; Clear current thread pointer + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports/cortex_a5/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a5/iar/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..1f363c90 --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_thread_vectored_context_save.s @@ -0,0 +1,195 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_vectored_context_save + CODE32 +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, the minimal context is already saved, and the +; lr register contains the return ISR address. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; +#ifdef TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r0 ; Disable interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + MOV pc, lr ; Return to caller +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + MOV pc, lr ; Return to caller +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #32 ; Recover saved registers + MOV pc, lr ; Return to caller +; +; } +;} + END + diff --git a/ports/cortex_a5/iar/src/tx_timer_interrupt.s b/ports/cortex_a5/iar/src/tx_timer_interrupt.s new file mode 100644 index 00000000..d4b8b35f --- /dev/null +++ b/ports/cortex_a5/iar/src/tx_timer_interrupt.s @@ -0,0 +1,260 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A5/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_timer_interrupt + CODE32 +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} + END + diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a5x/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..5ed0406b --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,118 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/.project b/ports/cortex_a5x/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..a1b15572 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/.project @@ -0,0 +1,26 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_a5x/ac6/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..dd0920bb --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/armv8_aarch64_SystemTimer.S b/ports/cortex_a5x/ac6/example_build/sample_threadx/armv8_aarch64_SystemTimer.S new file mode 100644 index 00000000..aaf0f7f8 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/armv8_aarch64_SystemTimer.S @@ -0,0 +1,431 @@ +// ------------------------------------------------------------ +// ARMv8-A AArch64 Generic Timer Access Functions +// +// Copyright ARM Ltd 2013. All rights reserved. +// ------------------------------------------------------------ + + + .section AArch64_GenericTimer,"ax" + .align 3 + +// ------------------------------------------------------------ + + .global getCNTFRQ + // uint32_t getCNTFRQ(void) + // Returns the value of CNTFRQ_EL0 + .type getCNTFRQ, @function +getCNTFRQ: + MRS x0, CNTFRQ_EL0 + RET + + +// ------------------------------------------------------------ + + .global setCNTFRQ + // void setCNTFRQ(uint32_t freq) + // Sets the value of CNTFRQ_EL0 (only possible at EL3) + // w0 - freq - The value to be written into CNTFRQ_EL0 + .type setCNTFRQ, @function +setCNTFRQ: + MSR CNTFRQ_EL0, x0 + RET + + +// ------------------------------------------------------------ + + .global getPhysicalCount + // uint64_t getPhysicalCount(void) + // Returns the current value of physical count (CNTPCT_EL0) + .type getPhysicalCount, @function +getPhysicalCount: + MRS x0, CNTPCT_EL0 + RET + + +// ------------------------------------------------------------ + + .global getVirtualCount + // uint64_t getVirtualCount(void) + // Returns the current value of the virtual count register (CNTVCT_EL0) + .type getVirtualCount, @function +getVirtualCount: + MRS x0, CNTVCT_EL0 + RET + + +// ------------------------------------------------------------ + + .global getEL1Ctrl + // uint32_t getEL1Ctrl(void) + // Returns the value of EL1 Timer Control Register (CNTKCTL_EL1) + .type getEL1Ctrl, @function +getEL1Ctrl: + MRS x0, CNTKCTL_EL1 + RET + + +// ------------------------------------------------------------ + + .global setEL1Ctrl + // void setEL1Ctrl(uint32_t value) + // Sets the value of Counter Non-secure EL1 Control Register (CNTKCTL_EL1) + // 0 - value - The value to be written into CNTKCTL_EL1 + .type setEL1Ctrl, @function +setEL1Ctrl: + MSR CNTKCTL_EL1, x0 + RET + + +// ------------------------------------------------------------ + + .global getEL2Ctrl + // uint32_t getEL2Ctrl(void) + // Returns the value of the EL2 Timer Control Register (CNTHCTL_EL2) + .type getEL2Ctrl, @function +getEL2Ctrl: + MRS x0, CNTHCTL_EL2 + RET + + +// ------------------------------------------------------------ + + .global setEL2Ctrl + // void setEL2Ctrl(uint32_t value) + // Sets the value of the EL2 Timer Control Register (CNTHCTL_EL2) + // x0 - value - The value to be written into CNTHCTL_EL2 + .type setEL2Ctrl, @function +setEL2Ctrl: + MSR CNTHCTL_EL2, x0 + RET + + +// ------------------------------------------------------------ +// Non-Secure Physical Timer +// ------------------------------------------------------------ + + .global getNSEL1PhysicalCompValue + // uint64_t getNSEL1PhysicalCompValue(void) + // Returns the value of Non-Secure EL1 Physical Compare Value Register (CNTP_CVAL_EL0) + .type getNSEL1PhysicalCompValue, @function +getNSEL1PhysicalCompValue: + MRS x0, CNTP_CVAL_EL0 + RET + + +// ------------------------------------------------------------ + + .global setNSEL1PhysicalCompValue + // void setNSEL1PhysicalCompValue(uint64_t value) + // Sets the value of the Non-Secure EL1 Physical Compare Value Register (CNTP_CVAL_EL0) + // x0 - value - The value to be written into CNTP_CVAL_EL0 + .type setNSEL1PhysicalCompValue, @function +setNSEL1PhysicalCompValue: + MSR CNTP_CVAL_EL0, x0 + RET + + +// ------------------------------------------------------------ + + .global getNSEL1PhysicalTimerValue + // uint32_t getNSEL1PhysicalTimerValue(void) + // Returns the value of Non-Secure EL1 Physical Timer Value Register (CNTP_TVAL_EL0) + .type getNSEL1PhysicalTimerValue, @function +getNSEL1PhysicalTimerValue: + MRS x0, CNTP_TVAL_EL0 + RET + + +// ------------------------------------------------------------ + + .global setNSEL1PhysicalTimerValue + // void setNSEL1PhysicalTimerValue(uint32_t value) + // Sets the value of the Non-Secure EL1 Physical Timer Value Register (CNTP_TVAL_EL0) + // w0 - value - The value to be written into CNTP_TVAL_EL0 + .type setNSEL1PhysicalTimerValue, @function +setNSEL1PhysicalTimerValue: + MSR CNTP_TVAL_EL0, x0 + RET + + +// ------------------------------------------------------------ + + .global getNSEL1PhysicalTimerCtrl + // uint32_t getNSEL1PhysicalTimerCtrl(void) + // Returns the value of Non-Secure EL1 Physical Timer Control Register (CNTP_CTL_EL0) + .type getNSEL1PhysicalTimerCtrl, @function +getNSEL1PhysicalTimerCtrl: + MRS x0, CNTP_CTL_EL0 + RET + + +// ------------------------------------------------------------ + + .global setNSEL1PhysicalTimerCtrl + // void setNSEL1PhysicalTimerCtrl(uint32_t value) + // Sets the value of the Non-Secure EL1 Physical Timer Control Register (CNTP_CTL_EL0) + // w0 - value - The value to be written into CNTP_CTL_EL0 + .type setNSEL1PhysicalTimerCtrl, @function +setNSEL1PhysicalTimerCtrl: + MSR CNTP_CTL_EL0, x0 + RET + + +// ------------------------------------------------------------ +// Secure Physical Timer +// ------------------------------------------------------------ + + .global getSEL1PhysicalCompValue + // uint64_t getSEL1PhysicalCompValue(void) + // Returns the value of Secure EL1 Physical Compare Value Register (CNTPS_CVAL_EL1) + .type getSEL1PhysicalCompValue, @function +getSEL1PhysicalCompValue: + MRS x0, CNTPS_CVAL_EL1 + RET + + +// ------------------------------------------------------------ + + .global setSEL1PhysicalCompValue + // void setSEL1PhysicalCompValue(uint64_t value) + // Sets the value of the Secure EL1 Physical Compare Value Register (CNTPS_CVAL_EL1) + // x0 - value - The value to be written into CNTPS_CVAL_EL1 + .type setSEL1PhysicalCompValue, @function +setSEL1PhysicalCompValue: + MSR CNTPS_CVAL_EL1, x0 + RET + + + +// ------------------------------------------------------------ + + .global getSEL1PhysicalTimerValue + // uint32_t getSEL1PhysicalTimerValue(void) + // Returns the value of Secure EL1 Physical Timer Value Register (CNTPS_TVAL_EL1) + .type getSEL1PhysicalTimerValue, @function +getSEL1PhysicalTimerValue: + MRS x0, CNTPS_TVAL_EL1 + RET + + +// ------------------------------------------------------------ + + .global setSEL1PhysicalTimerValue + // void setSEL1PhysicalTimerValue(uint32_t value) + // Sets the value of the Secure EL1 Physical Timer Value Register (CNTPS_TVAL_EL1) + // w0 - value - The value to be written into CNTPS_TVAL_EL1 + .type setSEL1PhysicalTimerValue, @function +setSEL1PhysicalTimerValue: + MSR CNTPS_TVAL_EL1, x0 + RET + + +// ------------------------------------------------------------ + + .global getSEL1PhysicalTimerCtrl + // uint32_t getSEL1PhysicalTimerCtrl(void) + // Returns the value of Secure EL1 Physical Timer Control Register (CNTPS_CTL_EL1) + .type getSEL1PhysicalTimerCtrl, @function +getSEL1PhysicalTimerCtrl: + MRS x0, CNTPS_CTL_EL1 + RET + + +// ------------------------------------------------------------ + + .global setSEL1PhysicalTimerCtrl + // void setSEL1PhysicalTimerCtrl(uint32_t value) + // Sets the value of the Secure EL1 Physical Timer Control Register (CNTPS_CTL_EL1) + // w0 - value - The value to be written into CNTPS_CTL_EL1 + .type setSEL1PhysicalTimerCtrl, @function +setSEL1PhysicalTimerCtrl: + MSR CNTPS_CTL_EL1, x0 + RET + + +// ------------------------------------------------------------ + + .global configSecureEL1TimerAccess + // void configSecureEL1TimerAccess(unsigned int config)// + // Sets the values of the SCR_EL3.ST bit (bit 11) based on the value in x0 + // EL3 accessible only! + .type configSecureEL1TimerAccess, @function +configSecureEL1TimerAccess: + MRS x1, SCR_EL3 + BFI x1, x0, #11, #1 + MSR SCR_EL3, x1 + RET + + +// ------------------------------------------------------------ +// Virtual Timer +// ------------------------------------------------------------ + + .global getEL1VirtualCompValue + // uint64_t getEL1VirtualCompValue(void) + // Returns the value of EL1 Virtual Compare Value Register (CNTV_CVAL_EL0) + .type getEL1VirtualCompValue, @function +getEL1VirtualCompValue: + MRS x0, CNTV_CVAL_EL0 + RET + + +// ------------------------------------------------------------ + + .global setEL1VirtualCompValue + // void setEL1VirtualCompValue(uint64_t value) + // Sets the value of the EL1 Virtual Compare Value Register (CNTV_CVAL_EL0) + // x0 - value - The value to be written into CNTV_CVAL_EL0 + .type setEL1VirtualCompValue, @function +setEL1VirtualCompValue: + MSR CNTV_CVAL_EL0, x0 + RET + + +// ------------------------------------------------------------ + + .global getEL1VirtualTimerValue + // uint32_t getEL1VirtualTimerValue(void) + // Returns the value of EL1 Virtual Timer Value Register (CNTV_TVAL_EL0) + .type getEL1VirtualTimerValue, @function +getEL1VirtualTimerValue: + MRS x0, CNTV_TVAL_EL0 + RET + + +// ------------------------------------------------------------ + + .global setEL1VirtualTimerValue + // void setEL1VirtualTimerValue(uint32_t value) + // Sets the value of the EL1 Virtual Timer Value Register (CNTV_TVAL_EL0) + // w0 - value - The value to be written into CNTV_TVAL_EL0 + .type setEL1VirtualTimerValue, @function +setEL1VirtualTimerValue: + MSR CNTV_TVAL_EL0, x0 + RET + + +// ------------------------------------------------------------ + + .global getEL1VirtualTimerCtrl + // uint32_t getEL1VirtualTimerCtrl(void) + // Returns the value of EL1 Virtual Timer Control Register (CNTV_CTL_EL0) + .type getEL1VirtualTimerCtrl, @function +getEL1VirtualTimerCtrl: + MRS x0, CNTV_CTL_EL0 + RET + + +// ------------------------------------------------------------ + + .global setEL1VirtualTimerCtrl + // void setEL1VirtualTimerCtrl(uint32_t value) + // Sets the value of the EL1 Virtual Timer Control Register (CNTV_CTL_EL0) + // w0 - value - The value to be written into CNTV_CTL_EL0 + .type setEL1VirtualTimerCtrl, @function +setEL1VirtualTimerCtrl: + MSR CNTV_CTL_EL0, x0 + RET + + +// ------------------------------------------------------------ +// Virtual Timer functions to be called by EL2 +// ------------------------------------------------------------ + + .global getVirtualCounterOffset + // uint64_t getVirtualCounterOffset(void) + // Returns the value of the Counter Virtual Offset Register (CNTVOFF_EL2) + // EL2 and EL3 only + .type getVirtualCounterOffset, @function +getVirtualCounterOffset: + MRS x0, CNTVOFF_EL2 + RET + + +// ------------------------------------------------------------ + + .global setVirtualCounterOffset + // void setVirtualCounterOffset(uint64_t offset) + // Sets the value of the Counter Virtual Offset Register (CNTVOFF_EL2) + // x0 - offset - The value to be written into CNTVOFF_EL2 + // EL2 and EL3 only + .type setVirtualCounterOffset, @function +setVirtualCounterOffset: + MSR CNTVOFF_EL2, x0 + RET + + +// ------------------------------------------------------------ +// EL2 Physical Timer +// ------------------------------------------------------------ + + .global getEL2PhysicalCompValue + // uint64_t getEL2PhysicalCompValue(void) + // Returns the value of EL2 Physical Compare Value Register (CNTHP_CVAL_EL2) + .type getEL2PhysicalCompValue, @function +getEL2PhysicalCompValue: + MRS x0, CNTHP_CVAL_EL2 + RET + + +// ------------------------------------------------------------ + + .global setEL2PhysicalCompValue + // void setEL2PhysicalCompValue(uint64_t value) + // Sets the value of the EL2 Physical Compare Value Register (CNTHP_CVAL_EL2) + // x0 - value - The value to be written into CNTHP_CVAL_EL2 + .type setEL2PhysicalCompValue, @function +setEL2PhysicalCompValue: + MSR CNTHP_CVAL_EL2, x0 + RET + + + +// ------------------------------------------------------------ + + .global getEL2PhysicalTimerValue + // uint32_t getEL2PhysicalTimerValue(void) + // Returns the value of EL2 Physical Timer Value Register (CNTHP_TVAL_EL2) + .type getEL2PhysicalTimerValue, @function +getEL2PhysicalTimerValue: + MRS x0, CNTHP_TVAL_EL2 + RET + + +// ------------------------------------------------------------ + + .global setEL2PhysicalTimerValue + // void setEL2PhysicalTimerValue(uint32_t value) + // Sets the value of the EL2 Physical Timer Value Register (CNTHP_TVAL_EL2) + // w0 - value - The value to be written into CNTHP_TVAL_EL2 + .type setEL2PhysicalTimerValue, @function +setEL2PhysicalTimerValue: + MSR CNTHP_TVAL_EL2, x0 + RET + + +// ------------------------------------------------------------ + + .global getEL2PhysicalTimerCtrl + // uint32_t getEL2PhysicalTimerCtrl(void) + // Returns the value of EL2 Physical Timer Control Register (CNTHP_CTL_EL2) + .type getEL2PhysicalTimerCtrl, @function +getEL2PhysicalTimerCtrl: + MRS x0, CNTHP_CTL_EL2 + RET + + +// ------------------------------------------------------------ + + .global setEL2PhysicalTimerCtrl + // void setEL2PhysicalTimerCtrl(uint32_t value) + // Sets the value of the EL2 Physical Timer Control Register (CNTHP_CTL_EL2) + // w0 - value - The value to be written into CNTHP_CTL_EL2 + .type setEL2PhysicalTimerCtrl, @function +setEL2PhysicalTimerCtrl: + MSR CNTHP_CTL_EL2, x0 + RET + + +// ------------------------------------------------------------ +// End of code +// ------------------------------------------------------------ diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/armv8_aarch64_SystemTimer.h b/ports/cortex_a5x/ac6/example_build/sample_threadx/armv8_aarch64_SystemTimer.h new file mode 100644 index 00000000..63474ac8 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/armv8_aarch64_SystemTimer.h @@ -0,0 +1,206 @@ +// ------------------------------------------------------------ +// ARMv8-A AArch64 System Timer +// Header Filer +// +// Copyright ARM Ltd 2013. All rights reserved. +// ------------------------------------------------------------ + +#ifndef _ARMV8A_SYSTEM_TIMER_H +#define _ARMV8A_SYSTEM_TIMER_H + +// ------------------------------------------------------------ +// CNTFRQ holds the frequency of the system counter +// Readable in all ELs +// Writable only by EL3 + +// Returns the value of CNTFRQ_EL0 +unsigned int getCNTFRQ(void); + +// Sets the value of CNTFRQ_EL0 (EL3 only!) +// freq - The value to be written into CNTFRQ_EL3 +void setCNTFRQ(unsigned int freq); + +// ------------------------------------------------------------ +// CNTPCT_EL0 and CNTVCT_EL0 hold the physical and virtual counts +// Always accessable in Hpy and Secure EL1 +// Access from EL2 and Non-Secure EL1 is configurable + +// Returns the current value of physical count (CNTPCT_EL0) +unsigned long long getPhysicalCount(void); + +// Returns the current value of the virtual count register (CNTVCT_EL0) +unsigned long long getVirtualCount(void); + +// ------------------------------------------------------------ +// The CNTKCTL register controls whether CNTPCT can be accessed from EL0 +// Only acceable from EL1 and EL2 + +#define CNTKCTL_PCTEN (1 << 0) // Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 +#define CNTKCTL_VCTEN (1 << 1) // Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from +#define CNTKCTL_EVNTEN (1 << 2) // Enables the generation of an event stream from the virtual counter +#define CNTKCTL_EVNTDIR (1 << 3) // Controls which transition of the CNTVCT trigger bit, defined by EVNTI, generates an event + +// Returns the value of EL1 Timer Control Register (CNTKCTL_EL1) +unsigned int getEL1Ctrl(void); + +// Sets the value of EL1 Timer Control Register (CNTKCTL_EL1) +// value - The value to be written into CNTKCTL_EL1 +void setEL1Ctrl(unsigned int value); + +// ------------------------------------------------------------ +// The CNTHCTL_EL2 register controls whether CNTPCT_EL0 can be accessed from EL1 +// Only accessable from EL2 and EL3 + +#define CNTHCTL_CNTPCT (1 << 0) +#define CNTHCTL_EVNTEN (1 << 2) +#define CNTHCTL_EVNTDIR (1 << 3) + +// Returns the value of the EL2 Timer Control Register (CNTHCTL_EL2) +unsigned int getEL2Ctrl(void); + +// Sets the value of EL2 Timer Control Register (CNTHCTL_EL2) +// value - The value to be written into CNTHCTL_EL2 +void setEL2Ctrl(unsigned int value); + +// ------------------------------------------------------------ +// Non-Secure Physical Timer +// ------------------------------------------------------------ +// Accessible from EL3, EL2 and EL1 + +// Returns the value of Non-Secure EL1 Physical Compare Value Register (CNTP_CVAL_EL0) +unsigned long long getNSEL1PhysicalCompValue(void); + +// Sets the value of the Non-Secure EL1 Physical Compare Value Register (CNTP_CVAL_EL0) +// value - The value to be written into CNTP_CVAL_EL0 +void setNSEL1PhysicalCompValue(unsigned long long value); + +// Returns the value of Non-Secure EL1 Physical Timer Value Register (CNTP_TVAL_EL0) +unsigned int getNSEL1PhysicalTimerValue(void); + +// Sets the value of the Non-Secure EL1 Physical Timer Value Register (CNTP_TVAL_EL0) +// value - The value to be written into CNTP_TVAL_EL0 +void setNSEL1PhysicalTimerValue(unsigned int value); + +#define CNTP_CTL_ENABLE (1 << 0) +#define CNTP_CTL_MASK (1 << 1) +#define CNTP_CTL_STATUS (1 << 2) + +// Returns the value of Non-Secure EL1 Physical Timer Control Register (CNTP_CTL_EL0) +unsigned int getNSEL1PhysicalTimerCtrl(void); + +// Sets the value of the Non-Secure EL1 Physical Timer Control Register (CNTP_CTL_EL0) +// value - The value to be written into CNTP_CTL_EL0 +void setNSEL1PhysicalTimerCtrl(unsigned int value); + +// ------------------------------------------------------------ +// Secure Physical Timer +// ------------------------------------------------------------ +// Accessible from EL3, and configurably from secure EL1 + +// Returns the value of Secure EL1 Physical Compare Value Register (CNTPS_CVAL_EL1) +unsigned long long getSEL1PhysicalCompValue(void); + +// Sets the value of the Secure EL1 Physical Compare Value Register (CNTPS_CVAL_EL1) +// value - The value to be written into CNTPS_CVAL_EL1 +void setSEL1PhysicalCompValue(unsigned long long value); + +// Returns the value of Secure EL1 Physical Timer Value Register (CNTPS_TVAL_EL1) +unsigned int getSEL1PhysicalTimerValue(void); + +// Sets the value of the Secure EL1 Physical Timer Value Register (CNTPS_TVAL_EL1) +// value - The value to be written into CNTPS_TVAL_EL1 +void setSEL1PhysicalTimerValue(unsigned int value); + +#define CNTPS_CTL_ENABLE (1 << 0) +#define CNTPS_CTL_MASK (1 << 1) +#define CNTPS_CTL_STATUS (1 << 2) + +// Returns the value of Secure EL1 Physical Timer Control Register (CNTPS_CTL_EL1) +unsigned int getSEL1PhysicalTimerCtrl(void); + +// Sets the value of the Secure EL1 Physical Timer Control Register (CNTPS_CTL_EL1) +// value - The value to be written into CNTPS_CTL_EL1 +void setSEL1PhysicalTimerCtrl(unsigned int value); + +// The SCR_EL3 register controls whether CNTPS_TVAL_EL1, +// CNTPS_CTL_EL1, and CNTPS_CVAL_EL1 can be accessed by secure +// EL1. +// Only accessible from EL3 + +#define SCR_ENABLE_SECURE_EL1_ACCESS (1) +#define SCR_DISABLE_SECURE_EL1_ACCESS (0) + +// Sets the values of the SCR_EL3.ST bit (bit 11) based on the value passed in 'config' +void configSecureEL1TimerAccess(unsigned int config); + +// ------------------------------------------------------------ +// Virtual Timer +// ------------------------------------------------------------ +// Accessible from Non-Secure EL1 and EL2 + +// Returns the value of EL1 Virtual Compare Value Register (CNTV_CVAL) +unsigned long long getEL1VirtualCompValue(void); + +// Sets the value of the EL1 Virtual Compare Value Register (CNTV_CVAL) +// value - The value to be written into CNTV_CVAL +void setEL1VirtualCompValue(unsigned long long value); + +// Returns the value of EL1 Virtual Timer Value Register (CNTV_TVAL) +unsigned int getEL1VirtualTimerValue(void); + +// Sets the value of the EL1 Virtual Timer Value Register (CNTV_TVAL) +// value - The value to be written into CNTV_TVAL +void setEL1VirtualTimerValue(unsigned int value); + +#define CNTV_CTL_ENABLE (1 << 0) +#define CNTV_CTL_MASK (1 << 1) +#define CNTV_CTL_STATUS (1 << 2) + +// Returns the value of EL1 Virtual Timer Control Register (CNTV_CTL) +unsigned int getEL1VirtualTimerCtrl(void); + +// Sets the value of the EL1 Virtual Timer Control Register (CNTV_CTL) +// value - The value to be written into CNTV_CTL +void setEL1VirtualTimerCtrl(unsigned int value); + +// +// Virtual timer functions to be called by EL2 +// + +// CNTVCT_EL2 holds the offset the virtual count is from the physical count +// Only accessable from EL2 and EL3 + +// Returns the value of the Counter Virtual Offset Register (CNTVOFF_EL2) +unsigned long long getVirtualCounterOffset(void); + +// Sets the value of the Counter Virtual Offset Register (CNTVOFF_EL2) +// offset - The value to be written into CNTVOFF_EL2 +void setVirtualCounterOffset(unsigned long long offset); + +// ------------------------------------------------------------ +// Hypervisor (EL2) Timer +// ------------------------------------------------------------ + +// Returns the value of EL2 Physical Compare Value Register (CNTHP_CVAL_EL2) +unsigned long long getEL2PhysicalCompValue(void); + +// Sets the value of the EL2 Physical Compare Value Register (CNTHP_CVAL_EL2) +// value - The value to be written into CNTHP_CVAL_EL2 +void setEL2PhysicalCompValue(unsigned long long value); + +// Returns the value of EL2 Physical Timer Value Register (CNTHP_TVAL_EL2) +unsigned int getEL2PhysicalTimerValue(void); + +#define CNTHP_CTL_ENABLE (1 << 0) +#define CNTHP_CTL_MASK (1 << 1) +#define CNTHP_CTL_STATUS (1 << 2) + +// Sets the value of the EL2 Physical Timer Value Register (CNTHP_TVAL_EL2) +// value - The value to be written into CNTHP_TVAL_EL2 +void setEL2PhysicalTimerValue(unsigned int value); + +#endif + +// ------------------------------------------------------------ +// End of armv8_aarch64_SystemTimer.h +// ------------------------------------------------------------ diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/el3_vectors.S b/ports/cortex_a5x/ac6/example_build/sample_threadx/el3_vectors.S new file mode 100644 index 00000000..7f4effe7 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/el3_vectors.S @@ -0,0 +1,138 @@ +// ------------------------------------------------------------ +// Exceptions workbook exercise +// +// Copyright ARM LTD, 2012 +// ------------------------------------------------------------ + + .section VECTORS,"ax" + .align 12 + + + .global el3_vectors +el3_vectors: + + .global fiqHandler + .global irqHandler + +// ------------------------------------------------------------ +// Current EL with SP0 +// ------------------------------------------------------------ + .balign 128 +sync_current_el_sp0: + B . // Synchronous + + .balign 128 +irq_current_el_sp0: + B irqFirstLevelHandler // IRQ + + .balign 128 +fiq_current_el_sp0: + B fiqFirstLevelHandler // FIQ + + .balign 128 +serror_current_el_sp0: + B . // SError + +// ------------------------------------------------------------ +// Current EL with SPx +// ------------------------------------------------------------ + + .balign 128 +sync_current_el_spx: + B . // Synchronous + + .balign 128 +irq_current_el_spx: + B irqFirstLevelHandler // IRQ + + .balign 128 +fiq_current_el_spx: + B fiqFirstLevelHandler // FIQ + + .balign 128 +serror_current_el_spx: + B . // SError + +// ------------------------------------------------------------ +// Lower EL using AArch64 +// ------------------------------------------------------------ + + .balign 128 +sync_lower_el_aarch64: + B . + + .balign 128 +irq_lower_el_aarch64: + B irqFirstLevelHandler // IRQ + + .balign 128 +fiq_lower_el_aarch64: + B fiqFirstLevelHandler // FIQ + + .balign 128 +serror_lower_el_aarch64: + B . // SError + +// ------------------------------------------------------------ +// Lower EL using AArch32 +// ------------------------------------------------------------ + + .balign 128 +sync_lower_el_aarch32: + B . + + .balign 128 +irq_lower_el_aarch32: + B irqFirstLevelHandler // IRQ + + .balign 128 +fiq_lower_el_aarch32: + B fiqFirstLevelHandler // FIQ + + .balign 128 +serror_lower_el_aarch32: + B . // SError + + +// ------------------------------------------------------------ + +irqFirstLevelHandler: + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + + BL irqHandler + + B _tx_thread_context_restore + +fiqFirstLevelHandler: + STP x29, x30, [sp, #-16]! + STP x18, x19, [sp, #-16]! + STP x16, x17, [sp, #-16]! + STP x14, x15, [sp, #-16]! + STP x12, x13, [sp, #-16]! + STP x10, x11, [sp, #-16]! + STP x8, x9, [sp, #-16]! + STP x6, x7, [sp, #-16]! + STP x4, x5, [sp, #-16]! + STP x2, x3, [sp, #-16]! + STP x0, x1, [sp, #-16]! + + BL fiqHandler + + LDP x0, x1, [sp], #16 + LDP x2, x3, [sp], #16 + LDP x4, x5, [sp], #16 + LDP x6, x7, [sp], #16 + LDP x8, x9, [sp], #16 + LDP x10, x11, [sp], #16 + LDP x12, x13, [sp], #16 + LDP x14, x15, [sp], #16 + LDP x16, x17, [sp], #16 + LDP x18, x19, [sp], #16 + LDP x29, x30, [sp], #16 + ERET + +// ------------------------------------------------------------ +// End of file +// ------------------------------------------------------------ + diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c b/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c new file mode 100644 index 00000000..1ecd5f33 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.c @@ -0,0 +1,419 @@ +// ---------------------------------------------------------- +// GIC400 - Generic Interrupt Controller +// +// GIC Exercise +// ---------------------------------------------------------- + +#include "gic400_gic.h" + +struct gic400_dist_if +{ + volatile unsigned int GICD_CTLR; // +0x000 - RW - Distributor Control Register + const volatile unsigned int GICD_TYPRE; // +0x004 - RO - Interrupt Controller Type Register + const volatile unsigned int GICD_IIDR; // +0x008 - RO - Distributor Implementer Identification Register + + const volatile unsigned int padding0[29]; + + volatile unsigned int GICD_IGROUPR[32]; // +0x080 - RW - Interrupt Groupt Registers (Security Registers in GICv1) + + volatile unsigned int GICD_ISENABLER[32]; // +0x100 - RW - Interrupt Set-Enable Registers + volatile unsigned int GICD_ICENABLER[32]; // +0x180 - RW - Interrupt Clear-Enable Registers + volatile unsigned int GICD_ISPENDR[32]; // +0x200 - RW - Interrupt Set-Pending Registers + volatile unsigned int GICD_ICPENDR[32]; // +0x280 - RW - Interrupt Clear-Pending Registers + volatile unsigned int GICD_ISACTIVER[32]; // +0x300 - RW - Interrupt Set-Active Register + volatile unsigned int GICD_ICACTIVER[32]; // +0x380 - RW - Interrupt Clear-Active Register + + volatile unsigned char GICD_IPRIORITYR[1024]; // +0x400 - RW - Interrupt Priority Registers + volatile unsigned int GICD_ITARGETSR[256]; // +0x800 - RW - Interrupt Processor Targets Registers + volatile unsigned int GICD_ICFGR[64]; // +0xC00 - RW - Interrupt Configuration Registers + + const volatile unsigned int padding2[128]; + + volatile unsigned int GICD_SGIR; // +0xF00 - WO - Software Generated Interrupt Register + +}; + +struct gic400_physical_cpu_if +{ + volatile unsigned int GICC_CTLR; // +0x000 - RW - CPU Interface Control Register + volatile unsigned int GICC_PMR; // +0x004 - RW - Interrupt Priority Mask Register + volatile unsigned int GICC_BPR; // +0x008 - RW - Binary Point Register + const volatile unsigned int GICC_IAR; // +0x00C - RO - Interrupt Acknowledge Register + volatile unsigned int GICC_EOIR; // +0x010 - WO - End of Interrupt Register + const volatile unsigned int GICC_RPR; // +0x014 - RO - Running Priority Register + const volatile unsigned int GICC_HPPIR; // +0x018 - RO - Highest Pending Interrupt Register + volatile unsigned int GICC_ABPR; // +0x01C - RW - Aliased Binary Point Register + const volatile unsigned int GICC_AIAR; // +0x020 - RO - Aliased Interrupt Acknowledge Register + volatile unsigned int GICC_AEOIR; // +0x024 - WO - Aliased End of Interrupt Register + const volatile unsigned int GICC_AHPPIR; // +0x028 - RO - Aliased Highest Pending Interrupt Register + + const volatile unsigned int padding0[52]; + + const volatile unsigned int GICC_IIDR; // +0x0FC - RO - CPU Interface Identification Register +}; + +struct gic400_dist_if* gic_dist; +struct gic400_physical_cpu_if* gic_cpu; + + +// ------------------------------------------------------------ + +void setGICAddr(void* dist, void* cpu) +{ + gic_dist = (struct gic400_dist_if*)dist; + gic_cpu = (struct gic400_physical_cpu_if*)cpu; + return; +} + +// ------------------------------------------------------------ + +// Global enable of the Interrupt Distributor +void enableGIC(void) +{ + gic_dist->GICD_CTLR = 3; + return; +} + +// Global disable of the Interrupt Distributor +void disableGIC(void) +{ + gic_dist->GICD_CTLR = 0; + return; +} + +// ------------------------------------------------------------ + +// Enables the interrupt source number ID +void enableIntID(unsigned int ID) +{ + unsigned int bank; + + bank = ID/32; // There are 32 IDs per register, need to work out which register to access + ID = ID & 0x1f; // ... and which bit within the register + + ID = 1 << ID; // Move a '1' into the correct bit position + + gic_dist->GICD_ISENABLER[bank] = ID; + + return; +} + +// Disables the interrupt source number ID +void disableIntID(unsigned int ID) +{ + unsigned int bank; + + bank = ID/32; // There are 32 IDs per register, need to work out which register to access + ID = ID & 0x1f; // ... and which bit within the register + + ID = 1 << ID; // Move a '1' into the correct bit position + + gic_dist->GICD_ICENABLER[bank] = ID; + + return; +} + +// ------------------------------------------------------------ + +// Sets the priority of the specified ID +void setIntPriority(unsigned int ID, unsigned int priority) +{ + if (ID > 1020) // Check ID in range + return; + + // The priority registers allows byte accesses + // meaning using a char array we can directly + // reference the correct entry + gic_dist->GICD_IPRIORITYR[ID] = priority; + + return; +} + +// Returns the priority of the specified ID +unsigned int getIntPriority(unsigned int ID) +{ + if (ID > 1020) // Check ID in range + return 0; + + return gic_dist->GICD_IPRIORITYR[ID]; +} + +// ------------------------------------------------------------ + +// Sets the target CPUs of the specified ID +// For 'target' use one of the above defines +void setIntTarget(unsigned int ID, unsigned int target) +{ + unsigned int bank, tmp; + + target = target & 0xFF; // Target field is 8-bits, mask off unused bit + bank = ID/4; // There are 4 IDs per register, need to work out which register to access + ID = ID & 0x3; // ... and which field within the register + ID = ID * 8; // Convert from which field to a bit offset (8-bits per field) + + target = target << ID; // Move prioity value into correct bit position + + tmp = gic_dist->GICD_ITARGETSR[bank]; // Read the current value in the register + tmp = tmp & ~(0xFF << ID); // Blank out the field holding the value we're modifying + tmp = tmp | target; // OR in the new target + gic_dist->GICD_ITARGETSR[bank] = tmp; + + return; +} + +// Returns the target CPUs of the specified ID +unsigned int getIntTarget(unsigned int ID) +{ + unsigned int bank, tmp; + + bank = ID/4; // There are 4 IDs per register, need to work out which register to access + ID = ID & 0x3; // ... and which field within the register + ID = ID * 8; // Convert from which field to a bit offset (8-bits per field) + + tmp = gic_dist->GICD_ITARGETSR[bank]; + + tmp = tmp >> ID; // Shift desired field to bit position 0 + tmp = tmp & 0xFF; // Mask off the other bits + + return tmp; +} + +// ---------------------------------------------------------- + +// Configures the specified ID as being level or edge triggered +void configureSPI(unsigned int ID, unsigned int conf) +{ + unsigned int bank, tmp; + + conf = conf & 0x3; // Mask out unused bits + + bank = ID/16; // There are 16 IDs per register, need to work out which register to access + ID = ID & 0xF; // ... and which field within the register + ID = ID * 2; // Convert from which field to a bit offset (2-bits per field) + + conf = conf << ID; // Move configuration value into correct bit position + + tmp = gic_dist-> GICD_ICFGR[bank]; // Read current vlase + tmp = tmp & ~(0x3 << ID); // Clear the bits for the specified field + tmp = tmp | conf; // OR in new configuration + gic_dist-> GICD_ICFGR[bank] = tmp; // Write updated value back + + return; +} + +// ---------------------------------------------------------- + +// Sets the pending bit of the specified ID +void setIntPending(unsigned int ID) +{ + unsigned int bank; + + bank = ID/32; // There are 32 IDs per register, need to work out which register to access + ID = ID & 0x1f; // ... and which bit within the register + + ID = 1 << ID; // Move a '1' into the correct bit position + + gic_dist->GICD_ISPENDR[bank] = ID; + + return; +} + +// Clears the pending bit of the specified ID +void clearIntPending(unsigned int ID) +{ + unsigned int bank; + + bank = ID/32; // There are 32 IDs per register, need to work out which register to access + ID = ID & 0x1f; // ... and which bit within the register + + ID = 1 << ID; // Move a '1' into the correct bit position + + gic_dist->GICD_ICPENDR[bank] = ID; + + return; +} + +// Returns the value of the status bit of the specifed ID +unsigned int getIntPending(unsigned int ID) +{ + unsigned int bank, tmp; + + bank = ID/32; // There are 32 IDs per register, need to work out which register to access + ID = ID & 0x1f; // ... and which bit within the register + + tmp = gic_dist->GICD_ICPENDR[bank]; // Read the register containing the ID we are interested in + tmp = tmp >> ID; // Shift the status bit for specified ID to position 0 + tmp = tmp & 0x1; // Mask off the rest of the register + + return tmp; +} + +// ------------------------------------------------------------ + +// Send a software generate interrupt +void sendSGI(unsigned int ID, unsigned int cpu_list, unsigned int filter_list, unsigned int SATT) +{ + // Ensure unused bits are clear, and shift into correct bit position + ID = ID & 0xF; + SATT = (SATT & 0x1) << 15; + cpu_list = (cpu_list & 0xFF) << 16; + filter_list = (filter_list & 0x3) << 24; + + // Combine fields + ID = ID | SATT | cpu_list | filter_list; + + gic_dist->GICD_SGIR = ID; + + return; +} + +// ------------------------------------------------------------ + +// Sets the specified ID as secure +void makeIntGroup0(unsigned int ID) +{ + unsigned int bank, tmp; + + bank = ID/32; // There are 32 IDs per register, need to work out which register to access + ID = ID & 0x1f; // ... and which bit within the register + + ID = 1 << ID; // Move a '1' into the correct bit position + ID = ~ID; // Invert to get mask + + tmp = gic_dist->GICD_IGROUPR[bank]; // Read current value + tmp = tmp & ID; + gic_dist->GICD_IGROUPR[bank] = tmp; + + return; +} + +// Set the specified ID as non-secure +void makeIntGroup1(unsigned int ID) +{ + unsigned int bank, tmp; + + bank = ID/32; // There are 32 IDs per register, need to work out which register to access + ID = ID & 0x1f; // ... and which bit within the register + + ID = 1 << ID; // Move a '1' into the correct bit position + + tmp = gic_dist->GICD_IGROUPR[bank]; // Read current value + tmp = tmp | ID; // Or with bit mask to set the bit + gic_dist->GICD_IGROUPR[bank] = tmp; // Write-back +} + +// Returns the security of the specified ID +unsigned int getIntGroup(unsigned int ID) +{ + // TBD + return 0; +} + +// ------------------------------------------------------------ +// CPU Interface functions +// ------------------------------------------------------------ + +// Enables the CPU interface +// Must been done one each core seperately +void enableCPUInterface(void) +{ + unsigned int tmp; + + tmp = gic_cpu->GICC_CTLR; + tmp = tmp | 0x1; // Set bit 0 + gic_cpu->GICC_CTLR = tmp; +} + +// Enables the group 1 (non-secure) CPU interface +// This function can only be called from the Secure world +// Must been done one each core seperately +void enableNonSecureCPUInterface(void) +{ + unsigned int tmp; + + tmp = gic_cpu->GICC_CTLR; + tmp = tmp | 0x2; // Set bit 1 + gic_cpu->GICC_CTLR = tmp; +} + +// Disables the processor interface +void disableCPUInterface(void) +{ + unsigned int tmp; + + tmp = gic_cpu->GICC_CTLR; + tmp = tmp & 0xFFFFFFFFE; // Clear bit 0 + gic_cpu->GICC_CTLR = tmp; +} + +// Enables the sending of secure interrupts as FIQs +void enableSecureFIQs(void) +{ + unsigned int tmp; + + tmp = gic_cpu->GICC_CTLR; + tmp = tmp | 0x8; // Set bit 3 + gic_cpu->GICC_CTLR = tmp; +} + +// Disables the sending of secure interrupts as FIQs +void disableSecureFIQs(void) +{ + unsigned int tmp; + + tmp = gic_cpu->GICC_CTLR; + tmp = tmp | 0xFFFFFFFF7; // Clear bit 3 + gic_cpu->GICC_CTLR = tmp; +} + +// Returns the value of the Interrupt Acknowledge Register +unsigned int readIntAck(void) +{ + return gic_cpu->GICC_IAR; +} + +// Writes ID to the End Of Interrupt register +void writeEOI(unsigned int ID) +{ + gic_cpu->GICC_EOIR = ID; + return; +} + +// Returns the value of the Aliased Interrupt Acknowledge Register +unsigned int readAliasedIntAck(void) +{ + return gic_cpu->GICC_AIAR; +} + +// Writes ID to the Aliased End Of Interrupt register +void writeAliasedEOI(unsigned int ID) +{ + gic_cpu->GICC_AEOIR = ID; + return; +} + +// Sets the Priority mask register for the core run on +// The reset value masks ALL interrupts! +void setPriorityMask(unsigned int priority) +{ + gic_cpu->GICC_PMR = (priority & 0xFF); + return; +} + +// Sets the Binary Point Register for the core run on +void setBinaryPoint(unsigned int priority) +{ + gic_cpu->GICC_BPR = (priority & 0xFF); + return; +} + +// Sets the Aliased Binary Point Register for the core run on +void setAliasedBinaryPoint(unsigned int priority) +{ + gic_cpu->GICC_ABPR = (priority & 0xFF); + return; +} + +// ------------------------------------------------------------ +// End of gic400_gic.c +// ------------------------------------------------------------ diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.h b/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.h new file mode 100644 index 00000000..aca064c3 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/gic400_gic.h @@ -0,0 +1,192 @@ +// ---------------------------------------------------------- +// GIC400 - Generic Interrupt Controller +// Header +// +// Martin Weidmann Dec 2011 +// ---------------------------------------------------------- + +#ifndef __gic400_gic_h +#define __gic400_gic_h + +#define GIC_GIC400_PPI0 (0) +#define GIC_GIC400_PPI1 (1) +#define GIC_GIC400_PPI2 (2) +#define GIC_GIC400_PPI3 (3) +#define GIC_GIC400_PPI4 (4) +#define GIC_GIC400_PPI5 (5) +#define GIC_GIC400_PPI6 (6) +#define GIC_GIC400_PPI7 (7) +#define GIC_GIC400_PPI8 (8) +#define GIC_GIC400_PPI9 (9) +#define GIC_GIC400_PPI10 (10) +#define GIC_GIC400_PPI11 (11) +#define GIC_GIC400_PPI12 (12) +#define GIC_GIC400_PPI13 (13) +#define GIC_GIC400_PPI14 (14) +#define GIC_GIC400_PPI15 (15) +#define GIC_GIC400_PPI16 (16) +#define GIC_GIC400_PPI17 (17) +#define GIC_GIC400_PPI18 (18) +#define GIC_GIC400_PPI19 (19) +#define GIC_GIC400_PPI20 (20) +#define GIC_GIC400_PPI21 (21) +#define GIC_GIC400_PPI22 (22) +#define GIC_GIC400_PPI23 (23) +#define GIC_GIC400_PPI24 (24) +#define GIC_GIC400_PPI25 (25) +#define GIC_GIC400_PPI26 (26) +#define GIC_GIC400_PPI27 (27) +#define GIC_GIC400_PPI28 (28) +#define GIC_GIC400_PPI29 (29) +#define GIC_GIC400_PPI30 (30) +#define GIC_GIC400_PPI31 (31) + +// ---------------------------------------------------------- + +// Sets the address of the GIC's distributor and CPU interfaces +void setGICAddr(void* dist, void* cpu); + +// ---------------------------------------------------------- + +// Global enable of the Interrupt Distributor +void enableGIC(void); + +// Global disable of the Interrupt Distributor +void disableGIC(void); + +// ---------------------------------------------------------- + +// Enables the interrupt source number ID +void enableIntID(unsigned int ID); + +// Disables the interrupt source number ID +void disableIntID(unsigned int ID); + +// ---------------------------------------------------------- + +// Sets the priority of the specified ID +void setIntPriority(unsigned int ID, unsigned int priority); + +// Returns the priority of the specified ID +unsigned int getIntPriority(unsigned int ID); + +// ---------------------------------------------------------- + +#define GIC_GIC400_TARGET_CPU0 (0x01) +#define GIC_GIC400_TARGET_CPU1 (0x02) +#define GIC_GIC400_TARGET_CPU2 (0x04) +#define GIC_GIC400_TARGET_CPU3 (0x08) +#define GIC_GIC400_TARGET_CPU4 (0x10) +#define GIC_GIC400_TARGET_CPU5 (0x20) +#define GIC_GIC400_TARGET_CPU6 (0x40) +#define GIC_GIC400_TARGET_CPU7 (0x80) + +// Sets the target CPUs of the specified ID +// For 'target' use one of the above defines +void setIntTarget(unsigned int ID, unsigned int target); + +// Returns the target CPUs of the specified ID +unsigned int getIntTarget(unsigned int ID); + +// ---------------------------------------------------------- + +#define GIC_GIC400_CONFIG_LEVEL (0) +#define GIC_GIC400_CONFIG_EDGE (2) + +// Configures the specified ID as being level or edge triggered + +void configureSPI(unsigned int ID, unsigned int conf); + +// ---------------------------------------------------------- + +// Sets the pending bit of the specified ID +void setIntPending(unsigned int ID); + +// Clears the pending bit of the specified ID +void clearIntPending(unsigned int ID); + +#define GIC_GIC400_PENDING_IS_SET (1) +#define GIC_GIC400_PENDING_IS_CLEAR (0) + +// Returns the value of the status bit of the specified ID +unsigned int getIntPending(unsigned int ID); + +// ---------------------------------------------------------- + +#define GIC_GIC400_SGI_SECURE (0) +#define GIC_GIC400_SGI_NONSECURE (1) +#define GIC_GIC400_SGI_FILTER_USE_LIST (0) +#define GIC_GIC400_SGI_FILTER_NOT_THIS_CPU (1) +#define GIC_GIC400_SGI_FILTER_THIS_CPU (2) +#define GIC_GIC400_SGI_CPU0 (0x01) +#define GIC_GIC400_SGI_CPU1 (0x02) +#define GIC_GIC400_SGI_CPU2 (0x04) +#define GIC_GIC400_SGI_CPU3 (0x08) +#define GIC_GIC400_SGI_CPU4 (0x10) +#define GIC_GIC400_SGI_CPU5 (0x20) +#define GIC_GIC400_SGI_CPU6 (0x40) +#define GIC_GIC400_SGI_CPU7 (0x80) + +// Send a software generate interrupt +void sendSGI(unsigned int ID, unsigned int cpu_list, unsigned int filter_list, unsigned int SATT); + +// ---------------------------------------------------------- + +// Sets the specified ID as secure +void makeIntGroup0(unsigned int ID); + +// Set the specified ID as non-secure +void makeIntGroup1(unsigned int ID); + +// Returns the security of the specified ID +unsigned int getIntGroup(unsigned int ID); + +// ------------------------------------------------------------ +// CPU Interface functions +// ------------------------------------------------------------ + +// Enables the processor interface +// Must been done one each core seperately +void enableCPUInterface(void); + +// Enables the group 1 (non-secure) CPU interface +// This function can only be called from the Secure world +// Must been done one each core seperately +void enableNonSecureCPUInterface(void); + +// Disables the processor interface +void disableCPUInterface(void); + +// Enables the sending of secure interrupts as FIQs +void enableSecureFIQs(void); + +// Disables the sending of secure interrupts as FIQs +void disableSecureFIQs(void); + +// Returns the value of the Interrupt Acknowledge Register +unsigned int readIntAck(void); + +// Writes ID to the End Of Interrupt register +void writeEOI(unsigned int ID); + +// Returns the value of the Aliased Interrupt Acknowledge Register +unsigned int readAliasedIntAck(void); + +// Writes ID to the Aliased End Of Interrupt register +void writeAliasedEOI(unsigned int ID); + +// Sets the Priority mask register for the core run on +// The reset value masks ALL interrupts! +void setPriorityMask(unsigned int priority); + +// Sets the Binary Point Register for the core run on +void setBinaryPoint(unsigned int priority); + +// Sets the Aliased Binary Point Register for the core run on +void setAliasedBinaryPoint(unsigned int priority); + +#endif + +// ---------------------------------------------------------- +// End of gic400_gic.h +// ---------------------------------------------------------- diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/hw_setup.c b/ports/cortex_a5x/ac6/example_build/sample_threadx/hw_setup.c new file mode 100644 index 00000000..dc19cd3b --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/hw_setup.c @@ -0,0 +1,104 @@ +// +// Copyright ARM LTD, 2013 + +#include +#include "gic400_gic.h" +#include "armv8_aarch64_SystemTimer.h" +#include "tx_api.h" + + +void _tx_timer_interrupt(void); + + + +// -------------------------------------------------------- + +void hw_setup(void) +{ + long long current_time; + + + setGICAddr((void*)0x2C001000, (void*)0x2C002000); + + // + // Configure interrupt controller (GICv2 assumed) + // + enableGIC(); + enableCPUInterface(); + enableNonSecureCPUInterface(); + setPriorityMask(0xFF); + enableSecureFIQs(); + + // Secure Physical Timer (ID 29) + enableIntID(29); + setIntPriority(29, 0); + makeIntGroup0(29); + + // Non-Secure Physical Timer (ID 30) + enableIntID(30); + setIntPriority(30, 0); + makeIntGroup1(30); + + + // + // Configure timer + // + configSecureEL1TimerAccess(SCR_ENABLE_SECURE_EL1_ACCESS); + + current_time = getPhysicalCount(); + + // Configure the Secure Physical Timer + setSEL1PhysicalCompValue(current_time + 10000); + setSEL1PhysicalTimerCtrl(CNTPS_CTL_ENABLE); + + // Configure the Non-Secure Physical Timer + setNSEL1PhysicalCompValue(current_time + 20000); + setNSEL1PhysicalTimerCtrl(CNTP_CTL_ENABLE); + + + // NOTE: + // This code assumes that the IRQ and FIQ exceptions + // have been routed to the appropriate EL. In this + // example that is done in the startup.s file +} + + +// -------------------------------------------------------- + +void fiqHandler(void) +{ + unsigned int ID; + +// printf("Hello from the FIQ handler\n"); + + ID = readIntAck(); + setSEL1PhysicalTimerCtrl(0); // Disable timer to clear interrupt + writeEOI(ID); + + return; +} + +// -------------------------------------------------------- + +void irqHandler(void) +{ + unsigned int ID; + unsigned long long current_time; + +// printf("Hello from the IRQ handler\n"); + + ID = readAliasedIntAck(); + setNSEL1PhysicalTimerCtrl(0); // Disable timer to clear interrupt + writeAliasedEOI(ID); + + current_time = getPhysicalCount(); + setNSEL1PhysicalCompValue(current_time + 20000); + setNSEL1PhysicalTimerCtrl(CNTP_CTL_ENABLE); + + //tx_thread_resume(&thread_1); + _tx_timer_interrupt(); + + return; +} + +// -------------------------------------------------------- diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..db5318f0 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,381 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include + +#define DEMO_STACK_SIZE 2048 +#define DEMO_BYTE_POOL_SIZE 64000 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +UCHAR memory_pool[DEMO_BYTE_POOL_SIZE]; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define board-specific hardware setup. */ + +void hw_setup(void); + + +/* Define main entry point. */ + +int main() +{ + + /* Setup hardware. */ + hw_setup(); + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +UCHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_pool, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.txt b/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.txt new file mode 100644 index 00000000..90c80d28 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/sample_threadx.txt @@ -0,0 +1,15 @@ +LOAD 0x80000000 +{ + BASE 0x80000000 + { + * (+RO) + } + + RAM +0x0 + { + * (+RW, +ZI) + } + + ARM_LIB_STACKHEAP 0x80090000 EMPTY -0x00040000 + {} +} \ No newline at end of file diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/startup.S b/ports/cortex_a5x/ac6/example_build/sample_threadx/startup.S new file mode 100644 index 00000000..8b1f8f3b --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/startup.S @@ -0,0 +1,199 @@ +//================================================================== +// Copyright ARM Ltd 2012. All rights reserved. +// +// ARMv8 example - Startup Code +//================================================================== + + .section BOOT,"ax" + .align 3 + +// ------------------------------------------------------------ + +.equ Mode_USR, 0x10 + +.equ AArch32_Mode_USR, 0x10 +.equ AArch32_Mode_FIQ, 0x11 +.equ AArch32_Mode_IRQ, 0x12 +.equ AArch32_Mode_SVC, 0x13 +.equ AArch32_Mode_ABT, 0x17 +.equ AArch32_Mode_UNDEF, 0x1B +.equ AArch32_Mode_SYS, 0x1F +.equ AArch32_Mode_HYP, 0x1A +.equ AArch32_Mode_MON, 0x16 + +.equ AArch64_EL2_SP2, 0x09 // EL2h +.equ AArch64_EL2_SP0, 0x08 // EL2t +.equ AArch64_EL1_SP1, 0x05 // EL1h +.equ AArch64_EL1_SP0, 0x04 // EL1t +.equ AArch64_EL0_SP0, 0x00 + +.equ AArch32_State_Thumb, 0x20 +.equ AArch32_State_ARM, 0x00 + +// ------------------------------------------------------------ + +.equ TT_S1_TABLE, 0x00000000000000003 // NSTable=0, PXNTable=0, UXNTable=0, APTable=0 + +// TT block entries templates (L1 and L2, NOT L3) +// Assuming table contents: +// 0 = b01000100 = Normal, Inner/Outer Non-Cacheable +// 1 = b11111111 = Normal, Inner/Outer WB/WA/RA +// 2 = b00000000 = Device-nGnRnE +.equ TT_S1_FAULT, 0x0 +.equ TT_S1_NORMAL_NO_CACHE, 0x00000000000000401 // Index = 0, AF=1 +.equ TT_S1_NORMAL_WBWA, 0x00000000000000405 // Index = 1, AF=1 +.equ TT_S1_DEVICE_nGnRnE, 0x00000000000000409 // Index = 2, AF=1 + +.equ TT_S1_UXN, (1 << 54) +.equ TT_S1_PXN, (1 << 53) +.equ TT_S1_nG, (1 << 11) +.equ TT_S1_NS, (1 << 5) + +.equ TT_S1_NON_SHARED, (0 << 8) // Non-shareable +.equ TT_S1_INNER_SHARED, (3 << 8) // Inner-shareable +.equ TT_S1_OUTER_SHARED, (2 << 8) // Outer-shareable + +.equ TT_S1_PRIV_RW, (0x0) +.equ TT_S1_PRIV_RO, (0x2 << 6) +.equ TT_S1_USER_RW, (0x1 << 6) +.equ TT_S1_USER_RO, (0x3 << 6) + +// ------------------------------------------------------------ + + .global start64 + .type start64, @function +start64: + + // Clear registers + // --------------- + // This is primarily for RTL simulators, to avoid + // possibility of X propergation + MOV x0, #0 + MOV x1, #0 + MOV x2, #0 + MOV x3, #0 + MOV x4, #0 + MOV x5, #0 + MOV x6, #0 + MOV x7, #0 + MOV x8, #0 + MOV x9, #0 + MOV x10, #0 + MOV x11, #0 + MOV x12, #0 + MOV x13, #0 + MOV x14, #0 + MOV x15, #0 + MOV x16, #0 + MOV x17, #0 + MOV x18, #0 + MOV x19, #0 + MOV x20, #0 + MOV x21, #0 + MOV x22, #0 + MOV x23, #0 + MOV x24, #0 + MOV x25, #0 + MOV x26, #0 + MOV x27, #0 + MOV x28, #0 + MOV x29, #0 + MOV x30, #0 + + // Which core am I + // ---------------- + MRS x0, MPIDR_EL1 + AND x0, x0, #0xFF // Mask off to leave Aff0 + CBZ x0, boot // If core 0, run the primary init code +sleep: + WFI + B sleep +boot: + + + // Disable trapping of CPTR_EL3 accesses or use of Adv.SIMD/FPU + // ------------------------------------------------------------- + MOV x0, #0 // Clear all trap bits + MSR CPTR_EL3, x0 + + + // Install vector table + // --------------------- + LDR x0, vector_table_address + MSR VBAR_EL3, x0 + + + // Configure SCR_EL3 + // ------------------ + MOV w1, #0 // Initial value of register is unknown + ORR w1, w1, #(1 << 11) // Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1) + ORR w1, w1, #(1 << 10) // Set RW bit (EL1 is AArch64, as this is the Secure world) + ORR w1, w1, #(1 << 3) // Set EA bit (SError routed to EL3) + ORR w1, w1, #(1 << 2) // Set FIQ bit (FIQs routed to EL3) + ORR w1, w1, #(1 << 1) // Set IRQ bit (IRQs routed to EL3) + MSR SCR_EL3, x1 + + + // + // Cortex-A series specified configuration + // + .ifdef CORTEXA + // Configure ACTLR_EL1 + // -------------------- + // These bits are IMP DEF, so need to different for different + // processors + //MRS x1, ACTLR_EL1 + //ORR x1, x1, #1 // Enable EL1 access to ACTLR_EL1 + //ORR x1, x1, #(1 << 1) // Enable EL1 access to CPUECTLR_EL1 + //ORR x1, x1, #(1 << 4) // Enable EL1 access to L2CTLR_EL1 + //ORR x1, x1, #(1 << 5) // Enable EL1 access to L2ECTLR_EL1 + //ORR x1, x1, #(1 << 6) // Enable EL1 access to L2ACTLR_EL1 + //MSR ACTLR_EL1, x1 + + // Configure CPUECTLR_EL1 + // ----------------------- + // These bits are IMP DEF, so need to different for different + // processors + // SMPEN - bit 6 - Enables the processor to receive cache + // and TLB maintenance operations + // + // NOTE: For Cortex-A57/53 CPUEN should be set beforebefore + // enabling the caches and MMU, or performing any cache + // and TLB maintenance operations. + //MRS x0, S3_1_c15_c2_1 // Read EL1 CPU Extended Control Register + //ORR x0, x0, #(1 << 6) // Set the SMPEN bit + //MSR S3_1_c15_c2_1, x0 // Write EL1 CPU Extended Control Register + //ISB + .endif + + + // Ensure changes to system register are visible before MMU enabled + ISB + + + // Enable Interrupts + // ------------------ + MSR DAIFClr, 0x3 + + + // Branch to scatter loading and C library init code + .global __main + B __main + +//================================================================== +// Manually created literals pool +//================================================================== + .align 3 + +lit_stackheap_limit: + .global Image$$ARM_LIB_STACKHEAP$$ZI$$Limit // Linker symbol from scatter file + .quad (Image$$ARM_LIB_STACKHEAP$$ZI$$Limit) + +vector_table_address: + .global el3_vectors + .quad el3_vectors + +// ------------------------------------------------------------ +// End of file +// ------------------------------------------------------------ + diff --git a/ports/cortex_a5x/ac6/example_build/tx/.cproject b/ports/cortex_a5x/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..11f9c6c9 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/tx/.cproject @@ -0,0 +1,129 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a5x/ac6/example_build/tx/.project b/ports/cortex_a5x/ac6/example_build/tx/.project new file mode 100644 index 00000000..863ca5cb --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/cortex_a5x/ac6/example_build/tx/.settings/language.settings.xml b/ports/cortex_a5x/ac6/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..118220fc --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a5x/ac6/inc/tx_port.h b/ports/cortex_a5x/ac6/inc/tx_port.h new file mode 100644 index 00000000..33a029ff --- /dev/null +++ b/ports/cortex_a5x/ac6/inc/tx_port.h @@ -0,0 +1,367 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A5x/ARM */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef int LONG; +typedef unsigned int ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Override the alignment type to use 64-bit alignment and storage for pointers. */ + +#define ALIGN_TYPE_DEFINED +typedef unsigned long long ALIGN_TYPE; + + +/* Override the free block marker for byte pools to be a 64-bit constant. */ + +#define TX_BYTE_BLOCK_FREE ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEE) + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_fp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) b = (UINT) __builtin_ctz((unsigned int) m); + +#endif + + +/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout + can figure out what thread timeout to process. */ + +#define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_thread_timeout_ptr; + + +/* Define the thread timeout setup logic in _tx_thread_create. */ + +#define TX_THREAD_CREATE_TIMEOUT_SETUP(t) (t) -> tx_thread_timer.tx_timer_internal_timeout_function = &(_tx_thread_timeout); \ + (t) -> tx_thread_timer.tx_timer_internal_timeout_param = 0; \ + (t) -> tx_thread_timer.tx_timer_internal_thread_timeout_ptr = (VOID *) (t); + + +/* Define the thread timeout pointer setup in _tx_thread_timeout. */ + +#define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_thread_timeout_ptr; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifndef TX_DISABLE_INLINE + +/* Define macros, with in-line assembly for performance. */ + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned long long daif_value; + + __asm__ volatile (" MRS %0, DAIF ": "=r" (daif_value) ); + __asm__ volatile (" MSR DAIFSet, 0x3" : : : "memory" ); + return((unsigned int) daif_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int daif_value) +{ + +unsigned long long temp; + + temp = (unsigned long long) daif_value; + __asm__ volatile (" MSR DAIF,%0": : "r" (temp): "memory" ); +} + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + +#else + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); +#endif + + +/* Define FP extension for the Cortex-A5x. Each is assumed to be called in the context of the executing + thread. */ + +#ifndef TX_SOURCE_CODE +#define tx_thread_fp_enable _tx_thread_fp_enable +#define tx_thread_fp_disable _tx_thread_fp_disable +#endif + +VOID tx_thread_fp_enable(VOID); +VOID tx_thread_fp_disable(VOID); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x/ARM Version 6.0 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + diff --git a/ports/cortex_a5x/ac6/readme_threadx.txt b/ports/cortex_a5x/ac6/readme_threadx.txt new file mode 100644 index 00000000..6907bd0f --- /dev/null +++ b/ports/cortex_a5x/ac6/readme_threadx.txt @@ -0,0 +1,255 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A5x + + Using the ARM Compiler 6 & DS + +1. Open the Azure RTOS Workspace + +In order to build the ThreadX library and the ThreadX demonstration first load +the Azure RTOS Workspace, which is located inside your ThreadX installation +directory. + +Note: the workspace and projects were made using DS-5, so DS will prompt you +to migrate the projects. This is expected, so please do so. + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the DS debugger on the +VE-AEMv8x1 Bare Metal simulator. + +Building the demonstration is easy; simply open the workspace file, select the +sample_threadx project, and select the build button. Next, right-click on the +project and select "Debug As -> Debug Configurations". The debugger is setup +for VE_AEMv8x1 Bare Metal Debug, so selecting "Debug" will launch the simulator, +load the sample_threadx.axf ELF file and run to main. You are now ready to +execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-A5x using ARM tools is at label +start64. This is defined within the ARM compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing +takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the +sole input parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The 64-bit ARM compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a context +switch happens as a result of making a ThreadX service call (which is itself a +C function). In such cases, the saved context of a thread is only the +non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + +FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 x28 x27 + 0x018 reserved x28 + 0x020 x26 x25 + 0x028 x27 x26 + 0x030 x24 x23 + 0x038 x25 x24 + 0x040 x22 x21 + 0x048 x23 x22 + 0x050 x20 x19 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 + 0x078 x17 + 0x080 x14 + 0x088 x15 + 0x090 x12 + 0x098 x13 + 0x0A0 x10 + 0x0A8 x11 + 0x0B0 x8 + 0x0B8 x9 + 0x0C0 x6 + 0x0C8 x7 + 0x0D0 x4 + 0x0D8 x5 + 0x0E0 x2 + 0x0E8 x3 + 0x0F0 x0 + 0x0F8 x1 + 0x100 x29 + 0x108 x30 + + +FP enabled and TX_THREAD.tx_thread_fp_enable == 1: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 FPSR FPSR + 0x018 FPCR FPCR + 0x020 q30 q14 + 0x030 q31 q15 + 0x040 q28 q12 + 0x050 q29 q13 + 0x060 q26 q10 + 0x070 q27 q11 + 0x080 q24 q8 + 0x090 q25 q9 + 0x0A0 q22 x27 + 0x0A8 x28 + 0x0B0 q23 x25 + 0x0B8 x26 + 0x0C0 q20 x23 + 0x0C8 x24 + 0x0D0 q21 x21 + 0x0D8 x22 + 0x0E0 q18 x19 + 0x0E8 x20 + 0x0F0 q19 x29 + 0x0F8 x30 + 0x100 q16 + 0x110 q17 + 0x120 q14 + 0x130 q15 + 0x140 q12 + 0x150 q13 + 0x160 q10 + 0x170 q11 + 0x180 q8 + 0x190 q9 + 0x1A0 q6 + 0x1B0 q7 + 0x1C0 q4 + 0x1D0 q5 + 0x1E0 q2 + 0x1F0 q3 + 0x200 q0 + 0x210 q1 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 + 0x288 x17 + 0x290 x14 + 0x298 x15 + 0x2A0 x12 + 0x2A8 x13 + 0x2B0 x10 + 0x2B8 x11 + 0x2C0 x8 + 0x2C8 x9 + 0x2D0 x6 + 0x2D8 x7 + 0x2E0 x4 + 0x2E8 x5 + 0x2F0 x2 + 0x2F8 x3 + 0x300 x0 + 0x308 x1 + 0x310 x29 + 0x318 x30 + + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the project settings to the desired compiler optimization level. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A5x +targets. Interrupts handlers for the 64-bit mode of the Cortex-A5x have the following +format: + + .global irq_handler +irq_handler: + + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + + /* Your ISR call goes here! */ + BL application_isr_handler + + B _tx_thread_context_restore + +By default, ThreadX assumes EL3 level of execution. Running and taking exceptions in EL1 +and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a +periodic timer source. + + +9. ARM FP Support + +By default, FP support is disabled for each thread. If saving the context of the FP registers +is needed, the following API call must be made from the context of the application thread - before +the FP usage: + +void tx_thread_fp_enable(void); + +After this API is called in the application, FP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the FP registers +to be saved/restored. + +To disable FP register context saving, simply call the following API: + +void tx_thread_fp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A5x using ARM tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a5x/ac6/src/tx_initialize_low_level.S b/ports/cortex_a5x/ac6/src/tx_initialize_low_level.S new file mode 100644 index 00000000..699a819a --- /dev/null +++ b/ports/cortex_a5x/ac6/src/tx_initialize_low_level.S @@ -0,0 +1,112 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A5x/ARM */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level + .type _tx_initialize_low_level, @function +_tx_initialize_low_level: + + MSR DAIFSet, 0x3 // Lockout interrupts + + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + MOV x1, sp // Pickup SP + BIC x1, x1, #0xF // Get 16-bit alignment + STR x1, [x0] // Store system stack + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) Image$$ZI$$Limit; */ + + LDR x0, =_tx_initialize_unused_memory // Pickup address of unused memory ptr + LDR x1, =zi_limit // Pickup unused memory address + LDR x1, [x1] // + STR x1, [x0] // Store unused memory address + + /* Done, return to caller. */ + + RET // Return to caller +/* } */ + + +zi_limit: + .quad (Image$$ARM_LIB_STACKHEAP$$ZI$$Limit) + diff --git a/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S b/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S new file mode 100644 index 00000000..b8de07ac --- /dev/null +++ b/ports/cortex_a5x/ac6/src/tx_thread_context_restore.S @@ -0,0 +1,302 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* .set ENABLE_ARM_FP,1 */ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-A5x/ARM */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .global _tx_thread_context_restore + .type _tx_thread_context_restore, @function +_tx_thread_context_restore: + + /* Lockout interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + +.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit // Call the ISR exit function +.endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, #0] // Pickup system state + SUB w2, w2, #1 // Decrement the counter + STR w2, [x3, #0] // Store the counter + CMP w2, #0 // Was this the first interrupt? + BEQ __tx_thread_not_nested_restore // If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL +.ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +.else +.ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +.else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +.endif +.endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x1, #0] // Pickup actual current thread pointer + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_restore // Yes, idle system was interrupted + + LDR x3, =_tx_thread_preempt_disable // Pickup preempt disable address + LDR w2, [x3, #0] // Pickup actual preempt disable flag + CMP w2, #0 // Is it set? + BNE __tx_thread_no_preempt_restore // Yes, don't preempt this thread + LDR x3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr + LDR x2, [x3, #0] // Pickup actual execute thread pointer + CMP x0, x2 // Is the same thread highest priority? + BNE __tx_thread_preempt_restore // No, preemption needs to happen + + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + /* Recover the saved context and return to the point of interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 +.ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +.else +.ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +.else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +.endif +.endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + STP x20, x21, [sp, #-16]! // Save x20, x21 + STP x22, x23, [sp, #-16]! // Save x22, x23 + STP x24, x25, [sp, #-16]! // Save x24, x25 + STP x26, x27, [sp, #-16]! // Save x26, x27 + STP x28, x29, [sp, #-16]! // Save x28, x29 +.ifdef ENABLE_ARM_FP + LDR w3, [x0, #248] // Pickup FP enable flag + CMP w3, #0 // Is FP enabled? + BEQ _skip_fp_save // No, skip FP save + STP q0, q1, [sp, #-32]! // Save q0, q1 + STP q2, q3, [sp, #-32]! // Save q2, q3 + STP q4, q5, [sp, #-32]! // Save q4, q5 + STP q6, q7, [sp, #-32]! // Save q6, q7 + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + STP q16, q17, [sp, #-32]! // Save q16, q17 + STP q18, q19, [sp, #-32]! // Save q18, q19 + STP q20, q21, [sp, #-32]! // Save q20, q21 + STP q22, q23, [sp, #-32]! // Save q22, q23 + STP q24, q25, [sp, #-32]! // Save q24, q25 + STP q26, q27, [sp, #-32]! // Save q26, q27 + STP q28, q29, [sp, #-32]! // Save q28, q29 + STP q30, q31, [sp, #-32]! // Save q30, q31 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +.endif + STP x4, x5, [sp, #-16]! // Save x4 (SPSR_EL3), x5 (ELR_E3) + + MOV x3, sp // Move sp into x3 + STR x3, [x0, #8] // Save stack pointer in thread control + // block + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, #0] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR x3, =_tx_timer_time_slice // Pickup time-slice variable address + LDR w2, [x3, #0] // Pickup time-slice + CMP w2, #0 // Is it active? + BEQ __tx_thread_dont_save_ts // No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w2, [x0, #36] // Save thread's time-slice + MOV w2, #0 // Clear value + STR w2, [x3, #0] // Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV x0, #0 // NULL value + STR x0, [x1, #0] // Clear current thread pointer + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + LDR x1, =_tx_thread_schedule // Build address for _tx_thread_schedule +.ifdef EL1 + MSR ELR_EL1, x1 // Setup point of interrupt + MOV x1, #0x5 // Setup EL1 return + MSR spsr_el1, x1 // Move into SPSR +.else +.ifdef EL2 + MSR ELR_EL2, x1 // Setup point of interrupt + MOV x1, #0x9 // Setup EL2 return + MSR spsr_el2, x1 // Move into SPSR +.else + MSR ELR_EL3, x1 // Setup point of interrupt + MOV x1, #0xD // Setup EL3 return + MSR spsr_el3, x1 // Move into SPSR +.endif +.endif + ERET // Return to scheduler +/* } */ + + diff --git a/ports/cortex_a5x/ac6/src/tx_thread_context_save.S b/ports/cortex_a5x/ac6/src/tx_thread_context_save.S new file mode 100644 index 00000000..88774af3 --- /dev/null +++ b/ports/cortex_a5x/ac6/src/tx_thread_context_save.S @@ -0,0 +1,228 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-A5x/ARM */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .global _tx_thread_context_save + .type _tx_thread_context_save, @function +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked + out, x29 (frame pointer), x30 (link register) are saved, we are in EL1, + and all other registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STP x0, x1, [sp, #-16]! // Save x0, x1 + STP x2, x3, [sp, #-16]! // Save x2, x3 + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, #0] // Pickup system state + CMP w2, #0 // Is this the first interrupt? + BEQ __tx_thread_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD w2, w2, #1 // Increment the nested interrupt counter + STR w2, [x3, #0] // Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +.ifdef EL1 + MRS x0, SPSR_EL1 // Pickup SPSR + MRS x1, ELR_EL1 // Pickup ELR (point of interrupt) +.else +.ifdef EL2 + MRS x0, SPSR_EL2 // Pickup SPSR + MRS x1, ELR_EL2 // Pickup ELR (point of interrupt) +.else + MRS x0, SPSR_EL3 // Pickup SPSR + MRS x1, ELR_EL3 // Pickup ELR (point of interrupt) +.endif +.endif + STP x0, x1, [sp, #-16]! // Save SPSR, ELR + +.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +.endif + + /* Return to the ISR. */ + + RET // Return to ISR + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD w2, w2, #1 // Increment the interrupt counter + STR w2, [x3, #0] // Store it back in the variable + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x1, #0] // Pickup current thread pointer + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Save minimal context of interrupted thread. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +.ifdef EL1 + MRS x4, SPSR_EL1 // Pickup SPSR + MRS x5, ELR_EL1 // Pickup ELR (point of interrupt) +.else +.ifdef EL2 + MRS x4, SPSR_EL2 // Pickup SPSR + MRS x5, ELR_EL2 // Pickup ELR (point of interrupt) +.else + MRS x4, SPSR_EL3 // Pickup SPSR + MRS x5, ELR_EL3 // Pickup ELR (point of interrupt) +.endif +.endif + STP x4, x5, [sp, #-16]! // Save SPSR, ELR + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + MOV x4, sp // + STR x4, [x0, #8] // Save thread stack pointer + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, #0] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + +.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +.endif + + RET // Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + +.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +.endif + + ADD sp, sp, #48 // Recover saved registers + RET // Continue IRQ processing + + /* } +} */ + + diff --git a/ports/cortex_a5x/ac6/src/tx_thread_fp_disable.c b/ports/cortex_a5x/ac6/src/tx_thread_fp_disable.c new file mode 100644 index 00000000..8a921e86 --- /dev/null +++ b/ports/cortex_a5x/ac6/src/tx_thread_fp_disable.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_disable Cortex-A5x/ARM */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_disable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_FALSE; + } + } +} + diff --git a/ports/cortex_a5x/ac6/src/tx_thread_fp_enable.c b/ports/cortex_a5x/ac6/src/tx_thread_fp_enable.c new file mode 100644 index 00000000..818b3e8a --- /dev/null +++ b/ports/cortex_a5x/ac6/src/tx_thread_fp_enable.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_enable Cortex-A5x/ARM */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enabled the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_enable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_TRUE; + } + } +} + diff --git a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..1096b0b8 --- /dev/null +++ b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_control.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/*#define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-A5x/ARM */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control, @function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS x1, DAIF // Pickup current interrupt posture + + /* Apply the new interrupt posture. */ + + MSR DAIF, x0 // Set new interrupt posture + MOV x0, x1 // Setup return value + RET // Return to caller +/* } */ + diff --git a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..fb865d66 --- /dev/null +++ b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_disable.S @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-A5x/ARM */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable, @function +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS x0, DAIF // Pickup current interrupt lockout posture + + /* Mask interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + RET // Return to caller +/* } */ + diff --git a/ports/cortex_a5x/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..336f54f8 --- /dev/null +++ b/ports/cortex_a5x/ac6/src/tx_thread_interrupt_restore.S @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-A5x/ARM */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_restore(UINT old_posture) +{ */ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore, @function +_tx_thread_interrupt_restore: + + /* Restore the old interrupt posture. */ + + MSR DAIF, x0 // Setup the old posture + RET // Return to caller + +/* } */ + diff --git a/ports/cortex_a5x/ac6/src/tx_thread_schedule.S b/ports/cortex_a5x/ac6/src/tx_thread_schedule.S new file mode 100644 index 00000000..7b4e7ff4 --- /dev/null +++ b/ports/cortex_a5x/ac6/src/tx_thread_schedule.S @@ -0,0 +1,240 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* .set ENABLE_ARM_FP,1 */ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A5x/ARM */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .global _tx_thread_schedule + .type _tx_thread_schedule, @function +_tx_thread_schedule: + + /* Enable interrupts. */ + + MSR DAIFClr, 0x3 // Enable interrupts + + /* Wait for a thread to execute. */ + /* do + { */ + + LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr + +.ifdef TX_ENABLE_WFI +__tx_thread_schedule_loop: + LDR x0, [x1, #0] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + BNE _tx_thread_schedule_thread // + WFI // + B __tx_thread_schedule_loop // Keep looking for a thread +_tx_thread_schedule_thread: +.else +__tx_thread_schedule_loop: + LDR x0, [x1, #0] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_schedule_loop // If so, keep looking for a thread +.endif + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Yes! We have a thread to execute. Lockout interrupts and + transfer control to it. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread + STR x0, [x1, #0] // Setup current thread pointer + + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR w2, [x0, #4] // Pickup run counter + LDR w3, [x0, #36] // Pickup time-slice for this thread + ADD w2, w2, #1 // Increment thread run-counter + STR w2, [x0, #4] // Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + // variable + LDR x4, [x0, #8] // Switch stack pointers + MOV sp, x4 // + STR w3, [x2, #0] // Setup time-slice + +.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV x19, x0 // Save x0 + BL _tx_execution_thread_enter // Call the thread execution enter function + MOV x0, x19 // Restore x0 +.endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + CMP x5, #0 // Check for synchronous context switch (ELR_EL1 = NULL) + BEQ _tx_solicited_return +.ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +.else +.ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +.else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +.endif +.endif +.ifdef ENABLE_ARM_FP + LDR w1, [x0, #248] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + BEQ _skip_interrupt_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q30, q31, [sp], #32 // Recover q30, q31 + LDP q28, q29, [sp], #32 // Recover q28, q29 + LDP q26, q27, [sp], #32 // Recover q26, q27 + LDP q24, q25, [sp], #32 // Recover q24, q25 + LDP q22, q23, [sp], #32 // Recover q22, q23 + LDP q20, q21, [sp], #32 // Recover q20, q21 + LDP q18, q19, [sp], #32 // Recover q18, q19 + LDP q16, q17, [sp], #32 // Recover q16, q17 + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 + LDP q6, q7, [sp], #32 // Recover q6, q7 + LDP q4, q5, [sp], #32 // Recover q4, q5 + LDP q2, q3, [sp], #32 // Recover q2, q3 + LDP q0, q1, [sp], #32 // Recover q0, q1 +_skip_interrupt_fp_restore: +.endif + LDP x28, x29, [sp], #16 // Recover x28 + LDP x26, x27, [sp], #16 // Recover x26, x27 + LDP x24, x25, [sp], #16 // Recover x24, x25 + LDP x22, x23, [sp], #16 // Recover x22, x23 + LDP x20, x21, [sp], #16 // Recover x20, x21 + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + +_tx_solicited_return: + +.ifdef ENABLE_ARM_FP + LDR w1, [x0, #248] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + BEQ _skip_solicited_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 +_skip_solicited_fp_restore: +.endif + LDP x27, x28, [sp], #16 // Recover x27, x28 + LDP x25, x26, [sp], #16 // Recover x25, x26 + LDP x23, x24, [sp], #16 // Recover x23, x24 + LDP x21, x22, [sp], #16 // Recover x21, x22 + LDP x19, x20, [sp], #16 // Recover x19, x20 + LDP x29, x30, [sp], #16 // Recover x29, x30 + MSR DAIF, x4 // Recover DAIF + RET // Return to caller +/* } */ + + diff --git a/ports/cortex_a5x/ac6/src/tx_thread_stack_build.S b/ports/cortex_a5x/ac6/src/tx_thread_stack_build.S new file mode 100644 index 00000000..cd8609f2 --- /dev/null +++ b/ports/cortex_a5x/ac6/src/tx_thread_stack_build.S @@ -0,0 +1,170 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-A5x/ARM */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .global _tx_thread_stack_build + .type _tx_thread_stack_build, @function +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-A5x should look like the following after it is built: + + Stack Top: SSPR Initial SSPR + ELR Point of interrupt + x28 Initial value for x28 + not used Not used + x26 Initial value for x26 + x27 Initial value for x27 + x24 Initial value for x24 + x25 Initial value for x25 + x22 Initial value for x22 + x23 Initial value for x23 + x20 Initial value for x20 + x21 Initial value for x21 + x18 Initial value for x18 + x19 Initial value for x19 + x16 Initial value for x16 + x17 Initial value for x17 + x14 Initial value for x14 + x15 Initial value for x15 + x12 Initial value for x12 + x13 Initial value for x13 + x10 Initial value for x10 + x11 Initial value for x11 + x8 Initial value for x8 + x9 Initial value for x9 + x6 Initial value for x6 + x7 Initial value for x7 + x4 Initial value for x4 + x5 Initial value for x5 + x2 Initial value for x2 + x3 Initial value for x3 + x0 Initial value for x0 + x1 Initial value for x1 + x29 Initial value for x29 (frame pointer) + x30 Initial value for x30 (link register) + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR x4, [x0, #24] // Pickup end of stack area + BIC x4, x4, #0xF // Ensure 16-byte alignment + + /* Actually build the stack frame. */ + + MOV x2, #0 // Build clear value + MOV x3, #0 // + + STP x2, x3, [x4, #-16]! // Set backtrace to 0 + STP x2, x3, [x4, #-16]! // Set initial x29, x30 + STP x2, x3, [x4, #-16]! // Set initial x0, x1 + STP x2, x3, [x4, #-16]! // Set initial x2, x3 + STP x2, x3, [x4, #-16]! // Set initial x4, x5 + STP x2, x3, [x4, #-16]! // Set initial x6, x7 + STP x2, x3, [x4, #-16]! // Set initial x8, x9 + STP x2, x3, [x4, #-16]! // Set initial x10, x11 + STP x2, x3, [x4, #-16]! // Set initial x12, x13 + STP x2, x3, [x4, #-16]! // Set initial x14, x15 + STP x2, x3, [x4, #-16]! // Set initial x16, x17 + STP x2, x3, [x4, #-16]! // Set initial x18, x19 + STP x2, x3, [x4, #-16]! // Set initial x20, x21 + STP x2, x3, [x4, #-16]! // Set initial x22, x23 + STP x2, x3, [x4, #-16]! // Set initial x24, x25 + STP x2, x3, [x4, #-16]! // Set initial x26, x27 + STP x2, x3, [x4, #-16]! // Set initial x28 +.ifdef EL1 + MOV x2, #0x5 // Build initial SPSR (EL1) +.else +.ifdef EL2 + MOV x2, #0x9 // Build initial SPSR (EL2) +.else + MOV x2, #0xD // Build initial SPSR (EL3) +.endif +.endif + MOV x3, x1 // Build initial ELR + STP x2, x3, [x4, #-16]! // Set initial SPSR & ELR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = x2; */ + + STR x4, [x0, #8] // Save stack pointer in thread's + RET // Return to caller + +/* } */ + + diff --git a/ports/cortex_a5x/ac6/src/tx_thread_system_return.S b/ports/cortex_a5x/ac6/src/tx_thread_system_return.S new file mode 100644 index 00000000..5106a801 --- /dev/null +++ b/ports/cortex_a5x/ac6/src/tx_thread_system_return.S @@ -0,0 +1,165 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* .set ENABLE_ARM_FP,1 */ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-A5x/ARM */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .global _tx_thread_system_return + .type _tx_thread_system_return, @function +_tx_thread_system_return: +; +; /* Save minimal context on the stack. */ +; + MRS x0, DAIF // Pickup DAIF + MSR DAIFSet, 0x3 // Lockout interrupts + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + STP x19, x20, [sp, #-16]! // Save x19, x20 + STP x21, x22, [sp, #-16]! // Save x21, x22 + STP x23, x24, [sp, #-16]! // Save x23, x24 + STP x25, x26, [sp, #-16]! // Save x25, x26 + STP x27, x28, [sp, #-16]! // Save x27, x28 + LDR x5, =_tx_thread_current_ptr // Pickup address of current ptr + LDR x6, [x5, #0] // Pickup current thread pointer + +.ifdef ENABLE_ARM_FP + LDR w7, [x6, #248] // Pickup FP enable flag + CMP w7, #0 // Is FP enabled? + BEQ _skip_fp_save // No, skip FP save + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +.endif + + MOV x1, #0 // Clear x1 + STP x0, x1, [sp, #-16]! // Save DAIF and clear value for ELR_EK1 + +.ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + MOV x19, x5 // Save x5 + MOV x20, x6 // Save x6 + BL _tx_execution_thread_exit // Call the thread exit function + MOV x5, x19 // Restore x5 + MOV x6, x20 // Restore x6 +.endif + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + LDR w1, [x2, #0] // Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + /* sp = _tx_thread_system_stack_ptr; */ + + MOV x4, sp // + STR x4, [x6, #8] // Save thread stack pointer + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, #0] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice) + { */ + + MOV x4, #0 // Build clear value + CMP w1, #0 // Is a time-slice active? + BEQ __tx_thread_dont_save_ts // No, don't save the time-slice + + /* Save the current remaining time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w4, [x2, #0] // Clear time-slice + STR w1, [x6, #36] // Store current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR x4, [x5, #0] // Clear current thread pointer + + B _tx_thread_schedule // Jump to scheduler! + +/* } */ + + diff --git a/ports/cortex_a5x/ac6/src/tx_timer_interrupt.S b/ports/cortex_a5x/ac6/src/tx_timer_interrupt.S new file mode 100644 index 00000000..1559352e --- /dev/null +++ b/ports/cortex_a5x/ac6/src/tx_timer_interrupt.S @@ -0,0 +1,240 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-A5x/ARM */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .global _tx_timer_interrupt + .type _tx_timer_interrupt, @function +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR x1, =_tx_timer_system_clock // Pickup address of system clock + LDR w0, [x1, #0] // Pickup system clock + ADD w0, w0, #1 // Increment system clock + STR w0, [x1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + /* if (_tx_timer_time_slice) + { */ + + LDR x3, =_tx_timer_time_slice // Pickup address of time-slice + LDR w2, [x3, #0] // Pickup time-slice + CMP w2, #0 // Is it non-active? + BEQ __tx_timer_no_time_slice // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + /* _tx_timer_time_slice--; */ + + SUB w2, w2, #1 // Decrement the time-slice + STR w2, [x3, #0] // Store new time-slice value + + /* Check for expiration. */ + /* if (__tx_timer_time_slice == 0) */ + + CMP w2, #0 // Has it expired? + BNE __tx_timer_no_time_slice // No, skip expiration processing + + /* Set the time-slice expired flag. */ + /* _tx_timer_expired_time_slice = TX_TRUE; */ + + LDR x3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV w0, #1 // Build expired value + STR w0, [x3, #0] // Set time-slice expiration flag + + /* } */ + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR x1, =_tx_timer_current_ptr // Pickup current timer pointer addr + LDR x0, [x1, #0] // Pickup current timer + LDR x2, [x0, #0] // Pickup timer list entry + CMP x2, #0 // Is there anything in the list? + BEQ __tx_timer_no_timer // No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR x3, =_tx_timer_expired // Pickup expiration flag address + MOV w2, #1 // Build expired value + STR w2, [x3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD x0, x0, #8 // Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR x3, =_tx_timer_list_end // Pickup addr of timer list end + LDR x2, [x3, #0] // Pickup list end + CMP x0, x2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR x3, =_tx_timer_list_start // Pickup addr of timer list start + LDR x0, [x3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR x0, [x1, #0] // Store new current timer pointer + /* } */ + +__tx_timer_done: + + + /* See if anything has expired. */ + /* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + { */ + + LDR x3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR w2, [x3, #0] // Pickup time-slice expired flag + CMP w2, #0 // Did a time-slice expire? + BNE __tx_something_expired // If non-zero, time-slice expired + LDR x1, =_tx_timer_expired // Pickup addr of other expired flag + LDR w0, [x1, #0] // Pickup timer expired flag + CMP w0, #0 // Did a timer expire? + BEQ __tx_timer_nothing_expired // No, nothing expired + +__tx_something_expired: + + + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR x1, =_tx_timer_expired // Pickup addr of expired flag + LDR w0, [x1, #0] // Pickup timer expired flag + CMP w0, #0 // Check for timer expiration + BEQ __tx_timer_dont_activate // If not set, skip timer activation + + /* Process timer expiration. */ + /* _tx_timer_expiration_process(); */ + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Did time slice expire? */ + /* if (_tx_timer_expired_time_slice) + { */ + + LDR x3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR w2, [x3, #0] // Pickup the actual flag + CMP w2, #0 // See if the flag is set + BEQ __tx_timer_not_ts_expiration // No, skip time-slice processing + + /* Time slice interrupted thread. */ + /* _tx_thread_time_slice(); */ + + BL _tx_thread_time_slice // Call time-slice processing + + /* } */ + +__tx_timer_not_ts_expiration: + + LDP x29, x30, [sp], #16 // Recover x29, x30 + /* } */ + +__tx_timer_nothing_expired: + + RET // Return to caller + +/* } */ + + diff --git a/ports/cortex_a7/ac5/example_build/build_threadx.bat b/ports/cortex_a7/ac5/example_build/build_threadx.bat new file mode 100644 index 00000000..bca9317b --- /dev/null +++ b/ports/cortex_a7/ac5/example_build/build_threadx.bat @@ -0,0 +1,238 @@ +del tx.a +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork tx_initialize_low_level.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_stack_build.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_schedule.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_system_return.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_context_save.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_context_restore.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_interrupt_control.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_timer_interrupt.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_fiq_context_restore.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_fiq_context_save.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_fiq_nesting_end.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_fiq_nesting_start.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_interrupt_disable.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_interrupt_restore.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_irq_nesting_end.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_irq_nesting_start.s +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_vectored_context_save.s +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +armar -r tx.a tx_initialize_low_level.o tx_thread_fiq_context_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_end.o tx_thread_fiq_nesting_start.o tx_thread_interrupt_disable.o +armar -r tx.a tx_thread_interrupt_restore.o tx_thread_irq_nesting_end.o tx_thread_irq_nesting_start.o +armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_a7/ac5/example_build/build_threadx_sample.bat b/ports/cortex_a7/ac5/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..a3429108 --- /dev/null +++ b/ports/cortex_a7/ac5/example_build/build_threadx_sample.bat @@ -0,0 +1,4 @@ +armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork tx_initialize_low_level.s +armcc -c -g --cpu=cortex-a7.no_neon --fpu=softvfp -I../../../../common/inc -I../inc sample_threadx.c +armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --first tx_initialize_low_level.o(Init) --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a + diff --git a/ports/cortex_a7/ac5/example_build/sample_threadx.c b/ports/cortex_a7/ac5/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_a7/ac5/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a7/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_a7/ac5/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..f137555a --- /dev/null +++ b/ports/cortex_a7/ac5/example_build/tx_initialize_low_level.s @@ -0,0 +1,414 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +FIQ_MODE EQU 0xD1 ; FIQ mode +IRQ_MODE EQU 0xD2 ; IRQ mode +SVC_MODE EQU 0xD3 ; SVC mode +SYS_MODE EQU 0xDF ; SYS mode + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +FIQ_MODE EQU 0x91 ; FIQ mode +IRQ_MODE EQU 0x92 ; IRQ mode +SVC_MODE EQU 0x93 ; SVC mode +SYS_MODE EQU 0x9F ; SYS mode + ENDIF +HEAP_SIZE EQU 4096 ; Heap size +FIQ_STACK_SIZE EQU 512 ; FIQ stack size +SYS_STACK_SIZE EQU 1024 ; SYS stack size (used for nested interrupts) +IRQ_STACK_SIZE EQU 1024 ; IRQ stack size + +VFPEnable EQU 0x40000000 ; VFP enable value + +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IF :DEF:TX_ENABLE_FIQ_SUPPORT + IMPORT _tx_thread_fiq_context_save + IMPORT _tx_thread_fiq_context_restore + ENDIF + IF :DEF:TX_ENABLE_IRQ_NESTING + IMPORT _tx_thread_irq_nesting_start + IMPORT _tx_thread_irq_nesting_end + ENDIF + IF :DEF:TX_ENABLE_FIQ_NESTING + IMPORT _tx_thread_fiq_nesting_start + IMPORT _tx_thread_fiq_nesting_end + ENDIF + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT _tx_version_id + IMPORT _tx_build_options + IMPORT |Image$$ZI$$Limit| +; +; + AREA Init, CODE, READONLY +; +;/* Define the default Cortex-A7 vector area. This should be located or copied to 0. */ +; + EXPORT __vectors +__vectors + LDR pc,=Reset_Vector ; Reset goes to startup function + LDR pc,=__tx_undefined ; Undefined handler + LDR pc,=__tx_swi_interrupt ; Software interrupt handler + LDR pc,=__tx_prefetch_handler ; Prefetch exception handler + LDR pc,=__tx_abort_handler ; Abort exception handler + LDR pc,=__tx_reserved_handler ; Reserved exception handler + LDR pc,=__tx_irq_handler ; IRQ interrupt handler + LDR pc,=__tx_fiq_handler ; FIQ interrupt handler +; +; + EXPORT Reset_Vector +Reset_Vector + + IF {TARGET_FPU_VFP} = {TRUE} + MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register + ORR r1, r1, #(0xf << 20) ; Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 ; Flush prefetch buffer because of FMXR below and + ; CP 10 & 11 were only just enabled + MOV r0, #VFPEnable ; Enable VFP itself + FMXR FPEXC, r0 ; FPEXC = r0 + ENDIF + + B __main +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; +; /****** NOTE ****** We must be in SVC MODE at this point. Some monitors +; enter this routine in USER mode and require a software interrupt to +; change into SVC mode. */ +; + LDR r1, =|Image$$ZI$$Limit| ; Get end of non-initialized RAM area + LDR r2, =HEAP_SIZE ; Pickup the heap size + ADD r1, r2, r1 ; Setup heap limit + ADD r1, r1, #4 ; Setup stack limit +; + IF :DEF:TX_ENABLE_IRQ_NESTING +; /* Setup the system mode stack for nested interrupt support */ + LDR r2, =SYS_STACK_SIZE ; Pickup stack size + MOV r3, #SYS_MODE ; Build SYS mode CPSR + MSR CPSR_c, r3 ; Enter SYS mode + ADD r1, r1, r2 ; Calculate start of SYS stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup SYS stack pointer + ENDIF +; + LDR r2, =FIQ_STACK_SIZE ; Pickup stack size + MOV r0, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_c, r0 ; Enter FIQ mode + ADD r1, r1, r2 ; Calculate start of FIQ stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup FIQ stack pointer + MOV sl, #0 ; Clear sl + MOV fp, #0 ; Clear fp + LDR r2, =IRQ_STACK_SIZE ; Pickup IRQ (system stack size) + MOV r0, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Enter IRQ mode + ADD r1, r1, r2 ; Calculate start of IRQ stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup IRQ stack pointer + MOV r0, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r0 ; Enter SVC mode + LDR r3, =_tx_thread_system_stack_ptr ; Pickup stack pointer + STR r1, [r3, #0] ; Save the system stack +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; + LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr + LDR r0, [r1, #0] ; Pickup system stack + ADD r0, r0, #4 ; Increment to next free word +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) |Image$$ZI$$Limit| + HEAP + [SYS_STACK] + FIQ_STACK + IRQ_STACK; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Done, return to caller. */ +; + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; +; +;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This +; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; (optionally SYS) stack areas. */ +; + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR r0, =|Image$$ZI$$Limit| ; Get end of non-initialized RAM area + LDR r2, =HEAP_SIZE ; Pickup the heap size + ADD r2, r2, r0 ; Setup heap limit + ADD r3, r2, #4 ; Setup stack limit + MOV r1, r3 ; Setup start of stack + IF :DEF:TX_ENABLE_IRQ_NESTING + LDR r12, =SYS_STACK_SIZE ; Pickup IRQ system stack + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + ENDIF + LDR r12, =FIQ_STACK_SIZE ; Pickup FIQ stack size + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + LDR r12, =IRQ_STACK_SIZE ; Pickup IRQ system stack + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; +;/* Define shells for each of the interrupt vectors. */ +; + EXPORT __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + EXPORT __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt ; Software interrupt handler +; + EXPORT __tx_prefetch_handler +__tx_prefetch_handler + B __tx_prefetch_handler ; Prefetch exception handler +; + EXPORT __tx_abort_handler +__tx_abort_handler + B __tx_abort_handler ; Abort exception handler +; + EXPORT __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; +; + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; + BL _tx_timer_interrupt ; Timer interrupt handler +_tx_not_timer_interrupt +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ + IF :DEF:TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start + ENDIF +; +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ + IF :DEF:TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end + ENDIF +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; + EXPORT __tx_example_vectored_irq_handler +__tx_example_vectored_irq_handler +; +; +; /* Save initial context and call context save to prepare for +; vectored ISR execution. */ +; +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers +; BL _tx_thread_vectored_context_save ; Vectored context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +; IF :DEF:TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +; ENDIF +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +; IF :DEF:TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +; ENDIF +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ + IF :DEF:TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start + ENDIF +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ + IF :DEF:TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end + ENDIF +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; + ELSE + EXPORT __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler + ENDIF +; +; /* Reference build options and version ID to ensure they come in. */ +; + LDR r2, =_tx_build_options ; Pickup build options variable address + LDR r0, [r2, #0] ; Pickup build options content + LDR r2, =_tx_version_id ; Pickup version ID variable address + LDR r0, [r2, #0] ; Pickup version ID content +; +; + END + diff --git a/ports/cortex_a7/ac5/inc/tx_port.h b/ports/cortex_a7/ac5/inc/tx_port.h new file mode 100644 index 00000000..9ba22c77 --- /dev/null +++ b/ports/cortex_a7/ac5/inc/tx_port.h @@ -0,0 +1,334 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A7/AC5 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef __thumb + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (ULONG) __clz((unsigned int) m); \ + b = 31 - b; +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifndef __thumb + +#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; + +#ifdef TX_ENABLE_FIQ_SUPPORT + +/* IRQ and FIQ support. */ + +#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); \ + __disable_fiq(); + +#define TX_RESTORE if (!interrupt_save_disabled) \ + { \ + __enable_irq(); \ + __enable_fiq(); \ + } + +#else + +#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); + +#define TX_RESTORE if (!interrupt_save_disabled) \ + { \ + __enable_irq(); \ + } +#endif + +#else + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); +#endif + + +/* Define VFP extension for the Cortex-A5. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.0 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a7/ac5/readme_threadx.txt b/ports/cortex_a7/ac5/readme_threadx.txt new file mode 100644 index 00000000..4423047b --- /dev/null +++ b/ports/cortex_a7/ac5/readme_threadx.txt @@ -0,0 +1,544 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A7 + + Thumb & 32-bit Mode + + Using ARM Compiler 5 (AC5) + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the AC5 +Compiler. At this point you may run the build_threadx.bat batch file. This will +build the ThreadX run-time environment in the "example_build" directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + +1.1 Building with Project Files + +The ThreadX library can also be built via project files. Simply open +the tx.mcp file with project builder and select make. This will place +the tx.a library file into the Debug sub-directory. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the ARM +Windows-based simulator. + +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf +is a binary file that can be downloaded and executed on the ARM simulator. + +2.0.1 Building with Project Files + +The ThreadX demonstration can also be built via project files. Simply open +the sample_threadx.mcp file with project builder and select make. This will place +the sample_threadx.axf output image into the Debug sub-directory. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A7 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning +of the Init area should be copied to address 0. + +This is also where initialization of a periodic timer interrupt source +should take place. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Assembler / Compiler Switches + +The following are compiler switches used in building the demonstration +system: + +Compiler Switch Meaning + + -g Specifies debug information + -c Specifies object code generation + --cpu Cortex-A7 Specifies Cortex-A7 instruction set + --apcs /interwork Specifies Thumb/32-bit compatibility + +Linker Switch Meaning + + -d Specifies to retain debug information in output file + -o demo.axf Specifies demo output file name + --elf Specifies elf output file format + --ro Specifies that Read-Only memory starts at address 0 + --first tx_initialize_low_level.o(Init) + Specifies that the first area loaded is Init + --remove Remove unused areas + --list Specifies map file name + --symbols Specifies symbols for map file + --map Creates a map file + +Application Defines + + --PD "TX_ENABLE_FIQ_SUPPORT SETL {TRUE}" This assembler define enables FIQ + interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}" This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. + --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}" This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. In addition, + IRQ nesting should also be enabled. + -DTX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ + interrupt handling in the ThreadX + generic C source. This define + should also be used in conjunction + with the corresponding assembler + define. + -DTX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + -DTX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + + +5. Register Usage and Stack Frames + +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A7 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A7 vectors start at address zero. The demonstration system startup +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save ; Jump to the context save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call(s) go here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + EXPORT __tx_irq_example_handler +__tx_irq_example_handler +; +; /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers + BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, +calling the _tx_thread_irq_nesting_end service disables nesting by disabling +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* Enable nested IRQ interrupts. NOTE: Since this service returns +; with IRQ interrupts enabled, all IRQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +; +; /* Application ISR call(s) go here! */ +; +; /* Disable nested IRQ interrupts. The mode is switched back to +; IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ handlers can be called here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ handlers can be called here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.s in the Integrator sub-directories. + + +9. Thumb/Cortex-A7 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A7 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built +with the "-apcs /interwork" option. + +10. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +11. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A7 using AC5 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a7/ac5/src/tx_thread_context_restore.s b/ports/cortex_a7/ac5/src/tx_thread_context_restore.s new file mode 100644 index 00000000..0d03b49c --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_context_restore.s @@ -0,0 +1,256 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +IRQ_MODE EQU 0xD2 ; IRQ mode +SVC_MODE EQU 0xD3 ; SVC mode + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +IRQ_MODE EQU 0x92 ; IRQ mode +SVC_MODE EQU 0x93 ; SVC mode + ENDIF +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save + ENDIF + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MOV r3, #SVC_MODE ; Build SVC mode with interrupts disabled + MSR CPSR_c, r3 ; Change to SVC mode + B _tx_thread_schedule ; Return to scheduler +;} +; + END + diff --git a/ports/cortex_a7/ac5/src/tx_thread_context_save.s b/ports/cortex_a7/ac5/src/tx_thread_context_save.s new file mode 100644 index 00000000..93f1fc52 --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_context_save.s @@ -0,0 +1,199 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_irq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable FIQ interrupts + ENDIF + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + END + diff --git a/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..fc1c0dfc --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,258 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE EQU 0xD3 ; SVC mode +FIQ_MODE EQU 0xD1 ; FIQ mode +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + EXPORT _tx_thread_fiq_context_restore +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + CPSID if ; Disable IRQ and FIQ interrupts + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_c, r2 ; Re-enter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save ; No, skip VFP FIQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_fiq_vfp_save + ENDIF + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r3 ; Enter SVC mode + B _tx_thread_schedule ; Return to scheduler +; +;} +; + END + diff --git a/ports/cortex_a7/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_a7/ac5/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..45b0d4cb --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_fiq_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_fiq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + EXPORT _tx_thread_fiq_context_save +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} +; + END + diff --git a/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..ce1d8ae2 --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,111 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + EXPORT _tx_thread_fiq_nesting_end +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..84c344a7 --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +FIQ_DISABLE EQU 0x40 ; FIQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + EXPORT _tx_thread_fiq_nesting_start +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_c, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a7/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_a7/ac5/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..717606de --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_interrupt_control.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +INT_MASK EQU 0xC0 ; Interrupt bit mask + ELSE +INT_MASK EQU 0x80 ; Interrupt bit mask + ENDIF +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} +; + END + diff --git a/ports/cortex_a7/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_a7/ac5/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..70c49171 --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_interrupt_disable.s @@ -0,0 +1,95 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(void) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ + ELSE + CPSID i ; Disable IRQ + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a7/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_a7/ac5/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..5dcb28e6 --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_restore(UINT old_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r0 ; Setup new CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..3af929a5 --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + EXPORT _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} + END + diff --git a/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..c1083df4 --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +IRQ_DISABLE EQU 0x80 ; IRQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + EXPORT _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_c, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a7/ac5/src/tx_thread_schedule.s b/ports/cortex_a7/ac5/src/tx_thread_schedule.s new file mode 100644 index 00000000..76ea630f --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_schedule.s @@ -0,0 +1,236 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_execute_ptr + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSIE if ; Enable IRQ and FIQ interrupts + ELSE + CPSIE i ; Enable IRQ interrupts + ENDIF +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Enable IRQ and FIQ interrupts + ELSE + CPSID i ; Enable IRQ interrupts + ENDIF +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ; variable + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 + ENDIF +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 ; Setup SPSR for return + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_interrupt_vfp_restore + ENDIF + LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + +_tx_solicited_return + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore + ENDIF + MSR CPSR_cxsf, r5 ; Recover CPSR + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} +; + + IF {TARGET_FPU_VFP} = {TRUE} + EXPORT tx_thread_vfp_enable +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + EXPORT tx_thread_vfp_disable +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + ENDIF + + END + diff --git a/ports/cortex_a7/ac5/src/tx_thread_stack_build.s b/ports/cortex_a7/ac5/src/tx_thread_stack_build.s new file mode 100644 index 00000000..965582ab --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_stack_build.s @@ -0,0 +1,165 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE EQU 0x13 ; SVC mode + IF :DEF:TX_ENABLE_FIQ_SUPPORT +CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled + ELSE +CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled + ENDIF + +THUMB_BIT EQU 0x20 ; Thumb-bit + +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A7 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + + MRS r3, CPSR ; Pickup CPSR + BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r3, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT ; Clear Thumb-bit by default + AND r1, r1, #1 ; Determine if the entry function is in Thumb mode + CMP r1, #1 ; Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT ; Yes, set the Thumb-bit + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + +;} + END + diff --git a/ports/cortex_a7/ac5/src/tx_thread_system_return.s b/ports/cortex_a7/ac5/src/tx_thread_system_return.s new file mode 100644 index 00000000..95eed654 --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_system_return.s @@ -0,0 +1,159 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context + LDR r5, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r6, [r5, #0] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r0, [r6, #144] ; Pickup the VFP enabled flag + CMP r0, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save + ENDIF + + MOV r0, #0 ; Build a solicited stack type + MRS r1, CPSR ; Pickup the CPSR + STMDB sp!, {r0-r1} ; Save type and CPSR +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function + ENDIF + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r6, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save the current remaining time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r6, #24] ; Store current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r5, #0] ; Clear current thread pointer + + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports/cortex_a7/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_a7/ac5/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..6237775e --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_thread_vectored_context_save.s @@ -0,0 +1,200 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + EXPORT _tx_thread_vectored_context_save +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ENDIF + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + ADD sp, sp, #32 ; Recover saved registers + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +;} +; + END + diff --git a/ports/cortex_a7/ac5/src/tx_timer_interrupt.s b/ports/cortex_a7/ac5/src/tx_timer_interrupt.s new file mode 100644 index 00000000..eb23279f --- /dev/null +++ b/ports/cortex_a7/ac5/src/tx_timer_interrupt.s @@ -0,0 +1,258 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} + END + diff --git a/ports/cortex_a7/gnu/example_build/build_threadx.bat b/ports/cortex_a7/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..856fcc92 --- /dev/null +++ b/ports/cortex_a7/gnu/example_build/build_threadx.bat @@ -0,0 +1,238 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_interrupt_disable.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_interrupt_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_fiq_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_fiq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_irq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_irq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_fiq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_fiq_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_vectored_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +arm-none-eabi-gcc -c -g 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../../../../common/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_start.o tx_thread_irq_nesting_start.o tx_thread_irq_nesting_end.o +arm-none-eabi-ar -r tx.a tx_thread_fiq_nesting_end.o tx_thread_fiq_context_restore.o tx_thread_vectored_context_save.o tx_initialize_low_level.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_a7/gnu/example_build/build_threadx_sample.bat b/ports/cortex_a7/gnu/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..561bab52 --- /dev/null +++ b/ports/cortex_a7/gnu/example_build/build_threadx_sample.bat @@ -0,0 +1,6 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 reset.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 crt0.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common/inc -I../inc sample_threadx.c +arm-none-eabi-ld -A cortex-a7 -T sample_threadx.ld reset.o crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libc.a libgcc.a -o sample_threadx.out -M > sample_threadx.map + diff --git a/ports/cortex_a7/gnu/example_build/crt0.S b/ports/cortex_a7/gnu/example_build/crt0.S new file mode 100644 index 00000000..aa0f3239 --- /dev/null +++ b/ports/cortex_a7/gnu/example_build/crt0.S @@ -0,0 +1,90 @@ + +/* .text is used instead of .section .text so it works with arm-aout too. */ + .text + .code 32 + .align 0 + + .global _mainCRTStartup + .global _start + .global start +start: +_start: +_mainCRTStartup: + +/* Start by setting up a stack */ + /* Set up the stack pointer to a fixed value */ + ldr r3, .LC0 + mov sp, r3 + /* Setup a default stack-limit in case the code has been + compiled with "-mapcs-stack-check". Hard-wiring this value + is not ideal, since there is currently no support for + checking that the heap and stack have not collided, or that + this default 64k is enough for the program being executed. + However, it ensures that this simple crt0 world will not + immediately cause an overflow event: */ + sub sl, sp, #64 << 10 /* Still assumes 256bytes below sl */ + mov a2, #0 /* Second arg: fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr a1, .LC1 /* First arg: start of memory block */ + ldr a3, .LC2 + sub a3, a3, a1 /* Third arg: length of block */ + + + + bl memset + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ +#ifdef __USES_INITFINI__ + /* Some arm/elf targets use the .init and .fini sections + to create constructors and destructors, and for these + targets we need to call the _init function and arrange + for _fini to be called at program exit. */ + mov r4, r0 + mov r5, r1 +/* ldr r0, .Lfini */ + bl atexit +/* bl init */ + mov r0, r4 + mov r1, r5 +#endif + bl main + + bl exit /* Should not return. */ + + + /* For Thumb, constants must be after the code since only + positive offsets are supported for PC relative addresses. */ + + .align 0 +.LC0: +.LC1: + .word __bss_start__ +.LC2: + .word __bss_end__ +/* +#ifdef __USES_INITFINI__ +.Lfini: + .word _fini +#endif */ + /* Return ... */ +#ifdef __APCS_26__ + movs pc, lr +#else +#ifdef __THUMB_INTERWORK + bx lr +#else + mov pc, lr +#endif +#endif + + +/* Workspace for Angel calls. */ + .data +/* Data returned by monitor SWI. */ +.global __stack_base__ +HeapBase: .word 0 +HeapLimit: .word 0 +__stack_base__: .word 0 +StackLimit: .word 0 diff --git a/ports/cortex_a7/gnu/example_build/libc.a b/ports/cortex_a7/gnu/example_build/libc.a new file mode 100644 index 0000000000000000000000000000000000000000..5b04fa4ed9b6479f70979f5577dd0705d1f6d1d7 GIT binary patch literal 2447586 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zyyk;0u~c5dm1R37av%P?23us%dHPGDpFT$0GBczAKYnN6rVuiJ<@W-;X3iNSdGtC4 zZc0Al4tY)&I-P!o0#6|ykg|z--55Au=wiVt!DWKHH_4BuyvA0+F2RcgFA>}#_#GlT dhn|!HpOEmEh$!@SiRZoRqCc?z|Ecwv{|7^Je? +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef __thumb__ + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); +#else +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) ); +#endif + +#define TX_RESTORE asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) ); + +#endif + + +/* Define VFP extension for the Cortex-A7. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/GNU Version 6.0 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a7/gnu/readme_threadx.txt b/ports/cortex_a7/gnu/readme_threadx.txt new file mode 100644 index 00000000..f56a131e --- /dev/null +++ b/ports/cortex_a7/gnu/readme_threadx.txt @@ -0,0 +1,513 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A7 + + Using the GNU Tools + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. + +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + + +2. Demonstration System + +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file +that can be downloaded and executed. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A7 using GNU tools is at label _start. +This is defined within the modified version of the GNU startup code - crt0.S. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied +to address 0. + +This is also where initialization of a periodic timer interrupt source should take +place. + +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter +to your application definition function, tx_application_define. + + +4. Assembler / Compiler Switches + +The following are compiler switches used in building the demonstration +system: + +Compiler/Assembler Meaning + Switches + + -g Specifies debug information + -c Specifies object code generation + -mcpu=cortex-a7 Specifies target cpu + +Linker Switch Meaning + + -o sample_threadx.out Specifies output file + -M > sample_threadx.map Specifies demo map file + -A cortex-a7 Specifies target architecture + -T sample_threadx.ld Specifies the loader control file + +Application Defines ( -D option) + + TX_ENABLE_FIQ_SUPPORT This assembler define enables FIQ + interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + + TX_ENABLE_IRQ_NESTING This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.S. + + TX_ENABLE_FIQ_NESTING This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.S. In addition, + IRQ nesting should also be enabled. + + TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ + interrupt handling in the ThreadX + generic C source. This define + should also be used in conjunction + with the corresponding assembler + define. + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + +5. Register Usage and Stack Frames + +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A7 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A7 vectors start at address zero. The demonstration system startup +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +nested IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.S: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save @ Jump to the context save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.S: + + .global __tx_irq_example_handler +__tx_irq_example_handler: +@ +@ /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} @ Save some scratch registers + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers + BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call goes here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* Enable nested IRQ interrupts. NOTE: Since this service returns +@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Disable nested IRQ interrupts. The mode is switched back to +@ IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.S. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.S: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Enable nested FIQ interrupts. NOTE: Since this service returns +@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Disable nested FIQ interrupts. The mode is switched back to +@ FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of +ThreadX will still run. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.S for the demonstration system. + + +9. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A7 using GNU tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a7/gnu/src/tx_thread_context_restore.S b/ports/cortex_a7/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..1a90baaf --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,257 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE = 0xD3 @ Disable IRQ/FIQ, SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE = 0x93 @ Disable IRQ, SVC mode +IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode +#endif +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_restore @ Yes, idle system was interrupted +@ + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_preempt_restore @ No, preemption needs to happen +@ +@ +__tx_thread_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_preempt_restore: +@ + LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r2 @ Enter IRQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r0 @ Enter SVC mode + B _tx_thread_schedule @ Return to scheduler +@} + + + diff --git a/ports/cortex_a7/gnu/src/tx_thread_context_save.S b/ports/cortex_a7/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..0535151c --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_context_save.S @@ -0,0 +1,203 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_irq_processing_return + .global _tx_execution_isr_enter +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} @ Store other registers +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr@ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #16 @ Recover saved registers + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@} + + + diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S new file mode 100644 index 00000000..b7ce5f4e --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_restore.S @@ -0,0 +1,260 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ +SVC_MODE = 0xD3 @ SVC mode +FIQ_MODE = 0xD1 @ FIQ mode +MODE_MASK = 0x1F @ Mode mask +THUMB_MASK = 0x20 @ Thumb bit mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_context_restore(VOID) +@{ + .global _tx_thread_fiq_context_restore + .type _tx_thread_fiq_context_restore,function +_tx_thread_fiq_context_restore: +@ +@ /* Lockout interrupts. */ +@ + CPSID if @ Disable IRQ and FIQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_fiq_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, [sp] @ Pickup the saved SPSR + MOV r2, #MODE_MASK @ Build mask to isolate the interrupted mode + AND r1, r1, r2 @ Isolate mode bits + CMP r1, #IRQ_MODE_BITS @ Was an interrupt taken in IRQ mode before we + @ got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore @ Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore @ Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_fiq_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore @ No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_fiq_preempt_restore: +@ + LDMIA sp!, {r3, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR_c, r2 @ Reenter FIQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block */ +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_fiq_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_fiq_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + ADD sp, sp, #24 @ Recover FIQ stack space + MOV r3, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r3 @ Lockout interrupts + B _tx_thread_schedule @ Return to scheduler +@ +@} + diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S new file mode 100644 index 00000000..16ff6eb6 --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_context_save.S @@ -0,0 +1,204 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_fiq_processing_return + .global _tx_execution_isr_enter +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@ VOID _tx_thread_fiq_context_save(VOID) +@{ + .global _tx_thread_fiq_context_save + .type _tx_thread_fiq_context_save,function +_tx_thread_fiq_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +__tx_thread_fiq_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, lr} @ Store other registers, Note that we don't +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested +@ @ interrupt processing does need to save +@ @ these registers. +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_fiq_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif +@ +@ /* Not much to do here, save the current SPSR and LR for possible +@ use in IRQ interrupted in idle system conditions, and return to +@ FIQ interrupt processing. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, lr} @ Store other registers that will get used +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@} + diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S new file mode 100644 index 00000000..f4dbedda --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_end.S @@ -0,0 +1,116 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +FIQ_MODE_BITS = 0x11 @ FIQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_end(VOID) +@{ + .global _tx_thread_fiq_nesting_end + .type _tx_thread_fiq_nesting_end,function +_tx_thread_fiq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode + +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S new file mode 100644 index 00000000..ac18c99a --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_fiq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +FIQ_DISABLE = 0x40 @ FIQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_start(VOID) +@{ + .global _tx_thread_fiq_nesting_start + .type _tx_thread_fiq_nesting_start,function +_tx_thread_fiq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..453a6b43 --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" */ +@ + +INT_MASK = 0x03F + +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_control +$_tx_thread_interrupt_control: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_control(UINT new_posture) +@{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r3, CPSR @ Pickup current CPSR + MOV r2, #INT_MASK @ Build interrupt mask + AND r1, r3, r2 @ Clear interrupt lockout bits + ORR r1, r1, r0 @ Or-in new interrupt lockout bits +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r1 @ Setup new CPSR + BIC r0, r3, r2 @ Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..64721b51 --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_disable.S @@ -0,0 +1,113 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_disable +$_tx_thread_interrupt_disable: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_disable(void) +@{ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r0, CPSR @ Pickup current CPSR +@ +@ /* Mask interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ +#else + CPSID i @ Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..8bae905a --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_interrupt_restore.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_restore +$_tx_thread_interrupt_restore: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring interrupts to the state */ +@/* returned by a previous _tx_thread_interrupt_disable call. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_restore(UINT old_posture) +@{ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r0 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..c62e38e1 --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_end(VOID) +@{ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..4e2fd962 --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +IRQ_DISABLE = 0x80 @ IRQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_start(VOID) +@{ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a7/gnu/src/tx_thread_schedule.S b/ports/cortex_a7/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..f0e20b7e --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_schedule.S @@ -0,0 +1,255 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_execution_thread_enter +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_schedule + .type $_tx_thread_schedule,function +$_tx_thread_schedule: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_schedule @ Call _tx_thread_schedule function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: +@ +@ /* Enable interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if @ Enable IRQ and FIQ interrupts +#else + CPSIE i @ Enable IRQ interrupts +#endif +@ +@ /* Wait for a thread to execute. */ +@ do +@ { + LDR r1, =_tx_thread_execute_ptr @ Address of thread execute ptr +@ +__tx_thread_schedule_loop: +@ + LDR r0, [r1] @ Pickup next thread to execute + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_schedule_loop @ If so, keep looking for a thread +@ +@ } +@ while(_tx_thread_execute_ptr == TX_NULL); +@ +@ /* Yes! We have a thread to execute. Lockout interrupts and +@ transfer control to it. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Setup the current thread pointer. */ +@ _tx_thread_current_ptr = _tx_thread_execute_ptr; +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + STR r0, [r1] @ Setup current thread pointer +@ +@ /* Increment the run count for this thread. */ +@ _tx_thread_current_ptr -> tx_thread_run_count++; +@ + LDR r2, [r0, #4] @ Pickup run counter + LDR r3, [r0, #24] @ Pickup time-slice for this thread + ADD r2, r2, #1 @ Increment thread run-counter + STR r2, [r0, #4] @ Store the new run counter +@ +@ /* Setup time-slice, if present. */ +@ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + @ variable + LDR sp, [r0, #8] @ Switch stack pointers + STR r3, [r2] @ Setup time-slice +@ +@ /* Switch to the thread's stack. */ +@ sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + MOV r5, r0 @ Save r0 + BL _tx_execution_thread_enter @ Call the thread execution enter function + MOV r0, r5 @ Restore r0 +#endif +@ +@ /* Determine if an interrupt frame or a synchronous task suspension frame +@ is present. */ +@ + LDMIA sp!, {r4, r5} @ Pickup the stack type and saved CPSR + CMP r4, #0 @ Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 @ Setup SPSR for return +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore @ No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} @ Recover D0-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt + +_tx_solicited_return: + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore @ No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} @ Recover D8-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 @ Recover CPSR + LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ + +#ifdef TX_ENABLE_VFP_SUPPORT + + .global tx_thread_vfp_enable + .type tx_thread_vfp_enable,function +tx_thread_vfp_enable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable + MOV r0, #1 @ Build enable value + STR r0, [r1, #144] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + + .global tx_thread_vfp_disable + .type tx_thread_vfp_disable,function +tx_thread_vfp_disable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable + MOV r0, #0 @ Build disable value + STR r0, [r1, #144] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + +#endif + diff --git a/ports/cortex_a7/gnu/src/tx_thread_stack_build.S b/ports/cortex_a7/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..6c89ae45 --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,178 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ + .arm + +SVC_MODE = 0x13 @ SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ interrupts enabled +#else +CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interrupts enabled +#endif +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_thread_stack_build + .type $_tx_thread_stack_build,function +$_tx_thread_stack_build: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_stack_build @ Call _tx_thread_stack_build function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-A7 should look like the following after it is built: +@ +@ Stack Top: 1 Interrupt stack frame type +@ CPSR Initial value for CPSR +@ a1 (r0) Initial value for a1 +@ a2 (r1) Initial value for a2 +@ a3 (r2) Initial value for a3 +@ a4 (r3) Initial value for a4 +@ v1 (r4) Initial value for v1 +@ v2 (r5) Initial value for v2 +@ v3 (r6) Initial value for v3 +@ v4 (r7) Initial value for v4 +@ v5 (r8) Initial value for v5 +@ sb (r9) Initial value for sb +@ sl (r10) Initial value for sl +@ fp (r11) Initial value for fp +@ ip (r12) Initial value for ip +@ lr (r14) Initial value for lr +@ pc (r15) Initial value for pc +@ 0 For stack backtracing +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #7 @ Ensure 8-byte alignment + SUB r2, r2, #76 @ Allocate space for the stack frame +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #1 @ Build interrupt stack type + STR r3, [r2, #0] @ Store stack type + MOV r3, #0 @ Build initial register value + STR r3, [r2, #8] @ Store initial r0 + STR r3, [r2, #12] @ Store initial r1 + STR r3, [r2, #16] @ Store initial r2 + STR r3, [r2, #20] @ Store initial r3 + STR r3, [r2, #24] @ Store initial r4 + STR r3, [r2, #28] @ Store initial r5 + STR r3, [r2, #32] @ Store initial r6 + STR r3, [r2, #36] @ Store initial r7 + STR r3, [r2, #40] @ Store initial r8 + STR r3, [r2, #44] @ Store initial r9 + LDR r3, [r0, #12] @ Pickup stack starting address + STR r3, [r2, #48] @ Store initial r10 (sl) + LDR r3,=_tx_thread_schedule @ Pickup address of _tx_thread_schedule for GDB backtrace + STR r3, [r2, #60] @ Store initial r14 (lr) + MOV r3, #0 @ Build initial register value + STR r3, [r2, #52] @ Store initial r11 + STR r3, [r2, #56] @ Store initial r12 + STR r1, [r2, #64] @ Store initial pc + STR r3, [r2, #68] @ 0 for back-trace + MRS r1, CPSR @ Pickup CPSR + BIC r1, r1, #CPSR_MASK @ Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] @ Store initial CPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a7/gnu/src/tx_thread_system_return.S b/ports/cortex_a7/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..5c2047b4 --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_system_return.S @@ -0,0 +1,180 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm +@ +@ + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_execution_thread_exit +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_system_return + .type $_tx_thread_system_return,function +$_tx_thread_system_return: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_system_return @ Call _tx_thread_system_return function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_system_return(VOID) +@{ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: +@ +@ /* Save minimal context on the stack. */ +@ + STMDB sp!, {r4-r11, lr} @ Save minimal context + + LDR r4, =_tx_thread_current_ptr @ Pickup address of current ptr + LDR r5, [r4] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r5, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save @ No, skip VFP solicited save + VMRS r1, FPSCR @ Pickup the FPSCR + STR r1, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D8-D15} @ Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 @ Build a solicited stack type + MRS r1, CPSR @ Pickup the CPSR + STMDB sp!, {r0-r1} @ Save type and CPSR +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + BL _tx_execution_thread_exit @ Call the thread exit function +#endif + MOV r3, r4 @ Pickup address of current ptr + MOV r0, r5 @ Pickup current thread pointer + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + LDR r1, [r2] @ Pickup current time slice +@ +@ /* Save current stack and switch to system stack. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ sp = _tx_thread_system_stack_ptr; +@ + STR sp, [r0, #8] @ Save thread stack pointer +@ +@ /* Determine if the time-slice is active. */ +@ if (_tx_timer_time_slice) +@ { +@ + MOV r4, #0 @ Build clear value + CMP r1, #0 @ Is a time-slice active? + BEQ __tx_thread_dont_save_ts @ No, don't save the time-slice +@ +@ /* Save time-slice for the thread and clear the current time-slice. */ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r4, [r2] @ Clear time-slice + STR r1, [r0, #24] @ Save current time-slice +@ +@ } +__tx_thread_dont_save_ts: +@ +@ /* Clear the current thread pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + STR r4, [r3] @ Clear current thread pointer + B _tx_thread_schedule @ Jump to scheduler! +@ +@} + diff --git a/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..b01f9190 --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_thread_vectored_context_save.S @@ -0,0 +1,190 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_execution_isr_enter +@ +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_vectored_context_save(VOID) +@{ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #32 @ Recover saved registers + MOV pc, lr @ Return to caller +@ +@ } +@} + diff --git a/ports/cortex_a7/gnu/src/tx_timer_interrupt.S b/ports/cortex_a7/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..bf58c2ee --- /dev/null +++ b/ports/cortex_a7/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,279 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ + .arm + +@ +@/* Define Assembly language external references... */ +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_timer_interrupt + .type $_tx_timer_interrupt,function +$_tx_timer_interrupt: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_timer_interrupt @ Call _tx_timer_interrupt function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1] @ Pickup current timer + LDR r2, [r0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wraparound. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup address of timer list end + LDR r2, [r3] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wraparound logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup address of timer list start + LDR r0, [r3] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + LDR r2, [r3] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup address of other expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup address of expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r2, [r3] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} + diff --git a/ports/cortex_a7/iar/example_build/azure_rtos.eww b/ports/cortex_a7/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..17e0d329 --- /dev/null +++ b/ports/cortex_a7/iar/example_build/azure_rtos.eww @@ -0,0 +1,13 @@ + + + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\tx.ewp + + + + + diff --git a/ports/cortex_a7/iar/example_build/cstartup.s b/ports/cortex_a7/iar/example_build/cstartup.s new file mode 100644 index 00000000..647de2e8 --- /dev/null +++ b/ports/cortex_a7/iar/example_build/cstartup.s @@ -0,0 +1,156 @@ + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 14520 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector + PUBLIC __vector_0x14 + PUBLIC __iar_program_start + EXTERN __tx_undefined + EXTERN __tx_swi_interrupt + EXTERN __tx_prefetch_handler + EXTERN __tx_abort_handler + EXTERN __tx_irq_handler + EXTERN __tx_fiq_handler + + ARM +__vector: + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort +__vector_0x14: + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + +Reset_Addr: DCD __iar_program_start +Undefined_Addr: DCD __tx_undefined +SWI_Addr: DCD __tx_swi_interrupt +Prefetch_Addr: DCD __tx_prefetch_handler +Abort_Addr: DCD __tx_abort_handler +IRQ_Addr: DCD __tx_irq_handler +FIQ_Addr: DCD __tx_fiq_handler + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reser execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + +; PUBLIC ?cstartup + EXTERN ?main + REQUIRE __vector + + ARM + +__iar_program_start: +?cstartup: + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR + +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + + + MRS r0, cpsr ; Original PSR value + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + +#ifdef __ARMVFP__ + MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register + ORR r1, r1, #(0xf << 20) ; Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 ; Flush prefetch buffer because of FMXR below and + ; CP 10 & 11 were only just enabled + MOV r0, #0x40000000 ; Enable VFP itself + FMXR FPEXC, r0 ; FPEXC = r0 +#endif + +; +; Add more initialization here +; + +; Continue to ?main for C-level initialization. + + B ?main + + END + + + diff --git a/ports/cortex_a7/iar/example_build/sample_threadx.c b/ports/cortex_a7/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..c2cc9886 --- /dev/null +++ b/ports/cortex_a7/iar/example_build/sample_threadx.c @@ -0,0 +1,372 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +UCHAR memory_pool[DEMO_BYTE_POOL_SIZE]; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_pool, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a7/iar/example_build/sample_threadx.dep b/ports/cortex_a7/iar/example_build/sample_threadx.dep new file mode 100644 index 00000000..1a307303 --- /dev/null +++ b/ports/cortex_a7/iar/example_build/sample_threadx.dep @@ -0,0 +1,219 @@ + + + 4 + 3543161750 + + Debug + + $TOOLKIT_DIR$\inc\stdlib.h + $PROJ_DIR$\Debug\Obj\tx_cstartup.r79 + $TOOLKIT_DIR$\inc\xencoding_limits.h + $PROJ_DIR$\Debug\Obj\tx_initialize_low_level.o + $TOOLKIT_DIR$\inc\c\ysizet.h + $PROJ_DIR$\tx_port.h + $TOOLKIT_DIR$\inc\string.h + $PROJ_DIR$\Debug\List\tx_initialize_low_level.lst + $TOOLKIT_DIR$\inc\DLib_Product_string.h + $PROJ_DIR$\Debug\Obj\sample_threadx.pbd + $PROJ_DIR$\Debug\Obj\sample_threadx.o + $TOOLKIT_DIR$\inc\ysizet.h + $TOOLKIT_DIR$\inc\c\iccarm_builtin.h + $TOOLKIT_DIR$\inc\c\string.h + $PROJ_DIR$\sample_threadx.icf + $PROJ_DIR$\cstartup.s79 + $PROJ_DIR$\Debug\Exe\sample_threadx.out + $TOOLKIT_DIR$\inc\DLib_Config_Normal.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_api.h + $PROJ_DIR$\Debug\Obj\TX_ILL.r79 + $PROJ_DIR$\Debug\Obj\sample_threadx.xcl + $TOOLKIT_DIR$\lib\m7Sx_tlv.a + $TOOLKIT_DIR$\inc\yvals.h + $PROJ_DIR$\Debug\List\cstartup.lst + $TOOLKIT_DIR$\inc\ycheck.h + $PROJ_DIR$\Debug\Obj\sample_threadx.__cstat.et + $PROJ_DIR$\Debug\List\sample_threadx.map + $TOOLKIT_DIR$\inc\c\DLib_Product_string.h + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $PROJ_DIR$\Debug\Obj\tx_execution_profile.o + $TOOLKIT_DIR$\inc\c\yvals.h + $PROJ_DIR$\Debug\Obj\cstartup.o + $PROJ_DIR$\sample_threadx.c + $PROJ_DIR$\cstartup.s + $TOOLKIT_DIR$\inc\c\intrinsics.h + $PROJ_DIR$\tx_initialize_low_level.s + $PROJ_DIR$\Debug\Obj\demo.r79 + $PROJ_DIR$\Debug\Obj\tx_execution_profile.pbi + $TOOLKIT_DIR$\inc\c\ycheck.h + $TOOLKIT_DIR$\inc\DLib_Threads.h + $TOOLKIT_DIR$\inc\c\stdlib.h + $PROJ_DIR$\Debug\Exe\tx.a + $TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h + $TOOLKIT_DIR$\inc\intrinsics.h + $TOOLKIT_DIR$\lib\dl7Sx_tln.a + $TOOLKIT_DIR$\inc\DLib_Product.h + $TOOLKIT_DIR$\inc\DLib_Defaults.h + $PROJ_DIR$\tx_api.h + $PROJ_DIR$\TX_ILL.s79 + $PROJ_DIR$\tx_initialize_low_level.s79 + $PROJ_DIR$\tx_execution_profile.c + $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h + $TOOLKIT_DIR$\lib\rt7Sx_tl.a + $TOOLKIT_DIR$\inc\c\iar_intrinsics_common.h + $PROJ_DIR$\DEMO.C + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $PROJ_DIR$\tx_cstartup.s79 + $PROJ_DIR$\..\inc\tx_port.h + $TOOLKIT_DIR$\lib\sh7Sxs_l.a + + + [ROOT_NODE] + + + ILINK + 16 26 + + + + + $PROJ_DIR$\cstartup.s79 + + + AARM + 31 + + + + + $PROJ_DIR$\Debug\Exe\sample_threadx.out + + + ILINK + 26 + + + + + ILINK + 14 31 10 41 3 58 52 21 44 + + + + + $PROJ_DIR$\sample_threadx.c + + + ICCARM + 10 + + + __cstat + 25 + + + BICOMP + 20 + + + + + ICCARM + 18 57 40 38 30 28 51 55 4 42 13 27 34 12 53 + + + + + $PROJ_DIR$\cstartup.s + + + AARM + 31 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$PROJ_DIR$\tx_initialize_low_level.s + + + diff --git a/ports/cortex_a7/iar/example_build/sample_threadx.icf b/ports/cortex_a7/iar/example_build/sample_threadx.icf new file mode 100644 index 00000000..9c95e1d1 --- /dev/null +++ b/ports/cortex_a7/iar/example_build/sample_threadx.icf @@ -0,0 +1,49 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x80; +define symbol __ICFEDIT_region_ROM_end__ = 0x1FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x100000; +define symbol __ICFEDIT_region_RAM_end__ = 0x1FFFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_size_freemem__ = 0x100000; + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_freemem = mem:[from 0x200000 to 0x300000]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}; + +place in RAM_region { last section FREE_MEM}; \ No newline at end of file diff --git a/ports/cortex_a7/iar/example_build/settings/azure_rtos.wsdt b/ports/cortex_a7/iar/example_build/settings/azure_rtos.wsdt new file mode 100644 index 00000000..31789f29 --- /dev/null +++ b/ports/cortex_a7/iar/example_build/settings/azure_rtos.wsdt @@ -0,0 +1,535 @@ + + + + + sample_threadx/Debug + tx/Debug + + sample_threadx + 1 + + + + + 21 + 2518 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+ + + 34050 + 0A0000000A0000006E0000006E000000 + 0000000000000000FE0200001A000000 + 8192 + 0 + 0 + 744 + 0 + + + 1 + + + + 34048 + 34049 + 34050 + 34051 + 34052 + 34053 + 34054 + 34055 + 34056 + 34057 + 34058 + 34059 + 34060 + 34061 + 34062 + 34063 + 34064 + 34065 + + + + 010000000300000001000000000000000000000001000000010000000200000000000000010000000100000000000000280000002800000000000000 + + + + diff --git a/ports/cortex_a7/iar/example_build/settings/sample_threadx.Debug.cspy.bat b/ports/cortex_a7/iar/example_build/settings/sample_threadx.Debug.cspy.bat new file mode 100644 index 00000000..00e828be --- /dev/null +++ b/ports/cortex_a7/iar/example_build/settings/sample_threadx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a7\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a7\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a7\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a7\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports/cortex_a7/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports/cortex_a7/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 new file mode 100644 index 00000000..7e660a93 --- /dev/null +++ b/ports/cortex_a7/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a7\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a7\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a7\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a7\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} diff --git a/ports/cortex_a7/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports/cortex_a7/iar/example_build/settings/sample_threadx.Debug.driver.xcl new file mode 100644 index 00000000..ddc3572b --- /dev/null +++ b/ports/cortex_a7/iar/example_build/settings/sample_threadx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-A7" + +"--fpu=VFPv4Neon" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/cortex_a7/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports/cortex_a7/iar/example_build/settings/sample_threadx.Debug.general.xcl new file mode 100644 index 00000000..6bf922a5 --- /dev/null +++ b/ports/cortex_a7/iar/example_build/settings/sample_threadx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a7\iar\example_build\Debug\Exe\sample_threadx.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports/cortex_a7/iar/example_build/settings/sample_threadx.crun b/ports/cortex_a7/iar/example_build/settings/sample_threadx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/cortex_a7/iar/example_build/settings/sample_threadx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports/cortex_a7/iar/example_build/settings/sample_threadx.dbgdt b/ports/cortex_a7/iar/example_build/settings/sample_threadx.dbgdt new file mode 100644 index 00000000..4dee51e4 --- /dev/null +++ b/ports/cortex_a7/iar/example_build/settings/sample_threadx.dbgdt @@ -0,0 +1,1632 @@ + + + + + + 20 + 1186 + + + 20 + 889 + 237 + 59 + + + + 124 + 27 + 27 + 27 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+++ b/ports/cortex_a7/iar/example_build/settings/tx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports/cortex_a7/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports/cortex_a7/iar/example_build/settings/tx.Debug.cspy.ps1 new file mode 100644 index 00000000..6a1889c0 --- /dev/null +++ b/ports/cortex_a7/iar/example_build/settings/tx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} diff --git a/ports/cortex_a7/iar/example_build/settings/tx.Debug.driver.xcl b/ports/cortex_a7/iar/example_build/settings/tx.Debug.driver.xcl new file mode 100644 index 00000000..ddc3572b --- /dev/null +++ b/ports/cortex_a7/iar/example_build/settings/tx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-A7" + +"--fpu=VFPv4Neon" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/cortex_a7/iar/example_build/settings/tx.Debug.general.xcl b/ports/cortex_a7/iar/example_build/settings/tx.Debug.general.xcl new file mode 100644 index 00000000..deeeb2f9 --- /dev/null +++ b/ports/cortex_a7/iar/example_build/settings/tx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armsim2.dll" + +"C:\release\threadx\Debug\Exe\tx.out" + +--plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armbat.dll" + + + + diff --git a/ports/cortex_a7/iar/example_build/settings/tx.crun b/ports/cortex_a7/iar/example_build/settings/tx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/cortex_a7/iar/example_build/settings/tx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports/cortex_a7/iar/example_build/settings/tx.dbgdt b/ports/cortex_a7/iar/example_build/settings/tx.dbgdt new file mode 100644 index 00000000..73e71f6e --- /dev/null +++ b/ports/cortex_a7/iar/example_build/settings/tx.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports/cortex_a7/iar/example_build/settings/tx.dnx b/ports/cortex_a7/iar/example_build/settings/tx.dnx new file mode 100644 index 00000000..1872e83f --- /dev/null +++ b/ports/cortex_a7/iar/example_build/settings/tx.dnx @@ -0,0 +1,58 @@ + + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports/cortex_a7/iar/example_build/tx.dep b/ports/cortex_a7/iar/example_build/tx.dep new file mode 100644 index 00000000..90ec9672 --- /dev/null +++ b/ports/cortex_a7/iar/example_build/tx.dep @@ -0,0 +1,10516 @@ + + + 4 + 3156940391 + + Debug + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_performance_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_set_notify.c + $PROJ_DIR$\..\src\tx_iar.c + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\tx_initialize_high_level.c + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_prioritize.c + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_release.c + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_delete.c + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_set.c + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_allocate.c + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_cleanup.c + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_initialize.c + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_performance_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_performance_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_initialize.c + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_search.c + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_create.c + $PROJ_DIR$\..\..\..\..\common\src\tx_block_release.c + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_cleanup.c + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_create.c + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_prioritize.c + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_create.c + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_cleanup.c + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_delete.c + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_get.c + 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$PROJ_DIR$\..\..\..\..\common\src\txe_thread_resume.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_suspend.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_terminate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_time_slice_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c + + + diff --git a/ports/cortex_a7/iar/example_build/tx_initialize_low_level.s b/ports/cortex_a7/iar/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..c8eabf0c --- /dev/null +++ b/ports/cortex_a7/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,327 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; Disable irq,fiq SVC mode +IRQ_MODE DEFINE 0xD2 ; Disable irq,fiq IRQ mode +FIQ_MODE DEFINE 0xD1 ; Disable irq,fiq FIQ mode +SYS_MODE DEFINE 0xDF ; Disable irq,fiq SYS mode +; +; + + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_thread_context_save +; EXTERN _tx_thread_vectored_context_save + EXTERN _tx_thread_context_restore +#ifdef TX_ENABLE_FIQ_SUPPORT + EXTERN _tx_thread_fiq_context_save + EXTERN _tx_thread_fiq_context_restore +#endif +#ifdef TX_ENABLE_IRQ_NESTING + EXTERN _tx_thread_irq_nesting_start + EXTERN _tx_thread_irq_nesting_end +#endif +#ifdef TX_ENABLE_FIQ_NESTING + EXTERN _tx_thread_fiq_nesting_start + EXTERN _tx_thread_fiq_nesting_end +#endif + EXTERN _tx_timer_interrupt + EXTERN ?cstartup + EXTERN _tx_build_options + EXTERN _tx_version_id +; +; +; +;/* Define the FREE_MEM segment that will specify where free memory is +; defined. This must also be located in at the end of other RAM segments +; in the linker control file. The value of this segment is what is passed +; to tx_application_define. */ +; + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + CODE32 + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level +; +; /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode. */ +; +; /* Remember the stack pointer, link register, and switch to SVC mode. */ +; + MOV r0, sp ; Remember the SP + MOV r1, lr ; Remember the LR + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r3 ; Switch to SVC mode + MOV sp, r0 ; Inherit the stack pointer setup by cstartup + MOV lr, r1 ; Inherit the link register +; +; /* Pickup the start of free memory. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) FREE_MEM; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Done, return to caller. */ +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +;/* Define shells for each of the interrupt vectors. */ +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt ; Software interrupt handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_prefetch_handler +__tx_prefetch_handler + B __tx_prefetch_handler ; Prefetch exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_abort_handler +__tx_abort_handler + B __tx_abort_handler ; Abort exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +; +; /* For debug purpose, execute the timer interrupt processing here. In +; a real system, some kind of status indication would have to be checked +; before the timer interrupt handler could be called. */ +; + BL _tx_timer_interrupt ; Timer interrupt handler +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; +; RSEG .text:CODE:NOROOT(2) +; PUBLIC __tx_example_vectored_irq_handler +;__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +;#endif +; +; /* Application IRQ handler is called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +;#endif +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; +#else + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler +#endif +; +; +BUILD_OPTIONS + DC32 _tx_build_options ; Reference to ensure it comes in +VERSION_ID + DC32 _tx_version_id ; Reference to ensure it comes in + END + diff --git a/ports/cortex_a7/iar/inc/tx_port.h b/ports/cortex_a7/iar/inc/tx_port.h new file mode 100644 index 00000000..73ea8e18 --- /dev/null +++ b/ports/cortex_a7/iar/inc/tx_port.h @@ -0,0 +1,393 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A7/IAR */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#if __CORE__ > __ARM4TM__ + +#if __CPU_MODE__ == 2 + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (UINT) __CLZ(m); \ + b = 31 - b; +#endif +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +/* First, check and see what mode the file is being compiled in. The IAR compiler + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros + are available. Otherwise, if Thumb mode is present, we must use function calls. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else +#if __CPU_MODE__ == 2 + +#if (__VER__ < 8002000) +__intrinsic unsigned long __get_CPSR(); +__intrinsic void __set_CPSR( unsigned long ); +#endif + + +#if (__VER__ < 8002000) +#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#else +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#endif + +#define TX_DISABLE interrupt_save = __get_CPSR(); \ + __set_CPSR(interrupt_save | TX_INT_DISABLE); +#define TX_RESTORE __set_CPSR(interrupt_save); + +#else + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#endif +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A9. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/IAR Version 6.0 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + diff --git a/ports/cortex_a7/iar/readme_threadx.txt b/ports/cortex_a7/iar/readme_threadx.txt new file mode 100644 index 00000000..0b12c22c --- /dev/null +++ b/ports/cortex_a7/iar/readme_threadx.txt @@ -0,0 +1,544 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A7 + + Thumb & 32-bit Mode + + Using the IAR Tools + +1. Building the ThreadX run-time Library + +Building the ThreadX library is easy. First, open the Azure RTOS workspace +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by +the application. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the IAR +Windows-based Cortex-A7 simulator. + +Building the demonstration is easy; simply make the sample_threadx.ewp project +the "active project" in the IAR Embedded Workbench and select the +"Make" button. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a +binary file that can be downloaded and executed on IAR's Cortex-A7 simulator. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A7 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. +By default, the vector area is defined at the top of cstartup.s, which is +a slightly modified from the base IAR file. + +The _tx_initialize_low_level function inside of tx_initialize_low_level.s +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all +other RAM sections in memory. + + +4. Register Usage and Stack Frames + +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +5. Conditional Compilation Switches + +The following are conditional compilation options for building the ThreadX library +and application: + + + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + FIQ interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + + TX_ENABLE_IRQ_NESTING This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. + + TX_ENABLE_FIQ_NESTING This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. In addition, + IRQ nesting should also be enabled. + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + TX_THUMB Defined, this option enables the BX LR calling return sequence + in assembly files, to ensure correct operation on systems that + use both ARM and Thumb mode. By default, this option is + not defined + + + + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the ThreadX library +project to enable various compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A7 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A7 vectors start at address zero. The demonstration system startup +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + PUBLIC __tx_irq_handler + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR dispatch call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_example_vectored_irq_handler +__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers + BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR dispatch call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +; + BL _tx_thread_irq_nesting_start + +; /* Application ISR dispatch call goes here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +; + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ dispatch call goes here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in +preparation for the FIQ context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ dispatch call goes here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +in the IRQ processing. + + +9. Thumb/Cortex-A7 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A7 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire +ThreadX assembly source should be built with TX_THUMB defined. + + +10. IAR Thread-safe Library Support + +Thread-safe support for the IAR tools is easily enabled by building the ThreadX library +and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file +should have the following line added (if not already in place): + +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application + +The project options "General Options -> Library Configuration" should also have the +"Enable thread support in library" box selected. + + +11. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + + +12. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX version 6.0.1 for Cortex-A7 using IAR's ARM tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a7/iar/src/tx_iar.c b/ports/cortex_a7/iar/src/tx_iar.c new file mode 100644 index 00000000..11fcefb3 --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports/cortex_a7/iar/src/tx_thread_context_restore.s b/ports/cortex_a7/iar/src/tx_thread_context_restore.s new file mode 100644 index 00000000..559c05bf --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_context_restore.s @@ -0,0 +1,259 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +SVC_MODE DEFINE 0xD3 ; SVC mode +IRQ_MODE DEFINE 0xD2 ; IRQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +THUMB_MASK DEFINE 0x20 ; Thumb bit mask +SVC_MODE_BITS DEFINE 0x13 ; SVC mode value + +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_restore + CODE32 +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + MRS r3, CPSR ; Pickup current CPSR + ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value + MSR CPSR_cxsf, r0 ; Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block + BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS ; Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 ; Lockout interrupts +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r3, r3, #MODE_MASK ; Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +;} +; +; + END + diff --git a/ports/cortex_a7/iar/src/tx_thread_context_save.s b/ports/cortex_a7/iar/src/tx_thread_context_save.s new file mode 100644 index 00000000..0751e98a --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_context_save.s @@ -0,0 +1,210 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif + + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_irq_processing_return + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_save + CODE32 +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r0 ; Disable interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + +; +; + END + diff --git a/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..03fb04b5 --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,270 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; SVC mode +FIQ_MODE DEFINE 0xD1 ; FIQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +THUMB_MASK DEFINE 0x20 ; Thumb bit mask +IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits +SVC_MODE_BITS DEFINE 0x13 ; SVC mode value + +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_restore + CODE32 +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + MRS r3, CPSR ; Pickup current CPSR + ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value + MSR CPSR_cxsf, r0 ; Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_cxsf, r2 ; Re-enter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block */ + BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS ; Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 ; Lockout interrupts +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MRS r3, CPSR ; Pickup current CPSR + BIC r3, r3, #MODE_MASK ; Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +; +;} +; +; + END + diff --git a/ports/cortex_a7/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a7/iar/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..339e227b --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_fiq_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_fiq_processing_return + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_save + CODE32 +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} +; +; + END + diff --git a/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..87088021 --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,109 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_end + CODE32 +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_cxsf, r0 ; Disable interrupts + LDR lr, [sp] ; Pickup saved lr + ADD sp, sp, #4 ; Adjust stack pointer + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_cxsf, r0 ; Re-enter IRQ mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..671cb6f9 --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit +MODE_MASK DEFINE 0x1F ; Mode mask +SYS_MODE_BITS DEFINE 0x1F ; System mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_start + CODE32 +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + STR lr, [sp, #-4]! ; Push the system mode lr on the system mode stack + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a7/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a7/iar/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..61d091d0 --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_interrupt_control.s @@ -0,0 +1,103 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +INT_MASK DEFINE 0xC0 ; Interrupt bit mask +#else +INT_MASK DEFINE 0x80 ; Interrupt bit mask +#endif +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_control + CODE32 +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} +; +; + END diff --git a/ports/cortex_a7/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a7/iar/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..27911f58 --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_interrupt_disable.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_disable + CODE32 +_tx_thread_interrupt_disable??rA +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + ORR r1, r0, #DISABLE_INTS ; Mask interrupts + MSR CPSR_cxsf, r1 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +; + END diff --git a/ports/cortex_a7/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a7/iar/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..80028df8 --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;void _tx_thread_interrupt_restore(UINT old_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_restore + CODE32 +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r0 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; + END diff --git a/ports/cortex_a7/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a7/iar/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..72b794b6 --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_end + CODE32 +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_cxsf, r0 ; Disable interrupts + LDR lr, [sp] ; Pickup saved lr + ADD sp, sp, #4 ; Adjust stack pointer + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_cxsf, r0 ; Re-enter IRQ mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a7/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a7/iar/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..ceed092b --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +IRQ_DISABLE DEFINE 0x80 ; IRQ disable bit +MODE_MASK DEFINE 0x1F ; Mode mask +SYS_MODE_BITS DEFINE 0x1F ; System mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_start + CODE32 +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + STR lr, [sp, #-4]! ; Push the system mode lr on the system mode stack + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a7/iar/src/tx_thread_schedule.s b/ports/cortex_a7/iar/src/tx_thread_schedule.s new file mode 100644 index 00000000..fb11bd10 --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_schedule.s @@ -0,0 +1,239 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask +#else +ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask +#endif +; +; + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_execution_thread_enter +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_schedule + CODE32 +_tx_thread_schedule??rA +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + MRS r2, CPSR ; Pickup CPSR + BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s) + MSR CPSR_cxsf, r0 ; Enable interrupts +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + MSR CPSR_cxsf, r2 ; Disable interrupts +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ; variable + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 +#endif +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 ; Setup SPSR for return +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + +_tx_solicited_return: +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 ; Recover CPSR + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} +; + +#ifdef __ARMVFP__ + PUBLIC tx_thread_vfp_enable + CODE32 +tx_thread_vfp_enable??rA +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if ; Enable IRQ and FIQ interrupts +#else + CPSIE i ; Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + PUBLIC tx_thread_vfp_disable + CODE32 +tx_thread_vfp_disable??rA +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if ; Enable IRQ and FIQ interrupts +#else + CPSIE i ; Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller +#endif + + END + diff --git a/ports/cortex_a7/iar/src/tx_thread_stack_build.s b/ports/cortex_a7/iar/src/tx_thread_stack_build.s new file mode 100644 index 00000000..2ed9f538 --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_stack_build.s @@ -0,0 +1,158 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE DEFINE 0x13 ; SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK DEFINE 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled +#else +CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled +#endif +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_stack_build + + CODE32 +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A7 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure long-word alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + MRS r1, CPSR ; Pickup CPSR + BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} + END + diff --git a/ports/cortex_a7/iar/src/tx_thread_system_return.s b/ports/cortex_a7/iar/src/tx_thread_system_return.s new file mode 100644 index 00000000..09d927db --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_system_return.s @@ -0,0 +1,162 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif +; +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_execution_thread_exit +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_system_return + CODE32 +_tx_thread_system_return??rA +_tx_thread_system_return +; +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context + LDR r5, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r6, [r5, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r0, [r6, #144] ; Pickup the VFP enabled flag + CMP r0, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 ; Build a solicited stack type + MRS r1, CPSR ; Pickup the CPSR + STMDB sp!, {r0-r1} ; Save type and CPSR +; +; /* Lockout interrupts. */ +; + ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r2 ; Disable interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function +#endif + + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r6, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r6, #24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r5, #0] ; Clear current thread pointer + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports/cortex_a7/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a7/iar/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..e73b7385 --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_thread_vectored_context_save.s @@ -0,0 +1,195 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_vectored_context_save + CODE32 +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, the minimal context is already saved, and the +; lr register contains the return ISR address. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; +#ifdef TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r0 ; Disable interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + MOV pc, lr ; Return to caller +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + MOV pc, lr ; Return to caller +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #32 ; Recover saved registers + MOV pc, lr ; Return to caller +; +; } +;} + END + diff --git a/ports/cortex_a7/iar/src/tx_timer_interrupt.s b/ports/cortex_a7/iar/src/tx_timer_interrupt.s new file mode 100644 index 00000000..1603243f --- /dev/null +++ b/ports/cortex_a7/iar/src/tx_timer_interrupt.s @@ -0,0 +1,260 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_timer_interrupt + CODE32 +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} + END + diff --git a/ports/cortex_a8/ac5/example_build/build_threadx.bat b/ports/cortex_a8/ac5/example_build/build_threadx.bat new file mode 100644 index 00000000..6cfc7e66 --- /dev/null +++ b/ports/cortex_a8/ac5/example_build/build_threadx.bat @@ -0,0 +1,238 @@ +del tx.a +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork tx_initialize_low_level.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_stack_build.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_schedule.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_system_return.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_context_save.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_context_restore.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_interrupt_control.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_timer_interrupt.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_fiq_context_restore.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_fiq_context_save.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_fiq_nesting_end.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_fiq_nesting_start.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_interrupt_disable.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_interrupt_restore.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_irq_nesting_end.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_irq_nesting_start.s +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork ../src/tx_thread_vectored_context_save.s +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +armcc -g --cpu=cortex-a8.no_neon -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +armar -r tx.a tx_initialize_low_level.o tx_thread_fiq_context_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_end.o tx_thread_fiq_nesting_start.o tx_thread_interrupt_disable.o +armar -r tx.a tx_thread_interrupt_restore.o tx_thread_irq_nesting_end.o tx_thread_irq_nesting_start.o +armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_a8/ac5/example_build/build_threadx_sample.bat b/ports/cortex_a8/ac5/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..34540967 --- /dev/null +++ b/ports/cortex_a8/ac5/example_build/build_threadx_sample.bat @@ -0,0 +1,4 @@ +armasm -g --cpu=cortex-a8.no_neon --apcs=interwork tx_initialize_low_level.s +armcc -c -g --cpu=cortex-a8.no_neon -I../../../../common/inc -I../inc sample_threadx.c +armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --first tx_initialize_low_level.o(Init) --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a + diff --git a/ports/cortex_a8/ac5/example_build/sample_threadx.c b/ports/cortex_a8/ac5/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_a8/ac5/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a8/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_a8/ac5/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..580d5042 --- /dev/null +++ b/ports/cortex_a8/ac5/example_build/tx_initialize_low_level.s @@ -0,0 +1,394 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +FIQ_MODE EQU 0xD1 ; FIQ mode +IRQ_MODE EQU 0xD2 ; IRQ mode +SVC_MODE EQU 0xD3 ; SVC mode +SYS_MODE EQU 0xDF ; SYS mode + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +FIQ_MODE EQU 0x91 ; FIQ mode +IRQ_MODE EQU 0x92 ; IRQ mode +SVC_MODE EQU 0x93 ; SVC mode +SYS_MODE EQU 0x9F ; SYS mode + ENDIF +HEAP_SIZE EQU 4096 ; Heap size +FIQ_STACK_SIZE EQU 512 ; FIQ stack size +SYS_STACK_SIZE EQU 1024 ; SYS stack size (used for nested interrupts) +IRQ_STACK_SIZE EQU 1024 ; IRQ stack size +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IF :DEF:TX_ENABLE_FIQ_SUPPORT + IMPORT _tx_thread_fiq_context_save + IMPORT _tx_thread_fiq_context_restore + ENDIF + IF :DEF:TX_ENABLE_IRQ_NESTING + IMPORT _tx_thread_irq_nesting_start + IMPORT _tx_thread_irq_nesting_end + ENDIF + IF :DEF:TX_ENABLE_FIQ_NESTING + IMPORT _tx_thread_fiq_nesting_start + IMPORT _tx_thread_fiq_nesting_end + ENDIF + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT _tx_version_id + IMPORT _tx_build_options + IMPORT |Image$$ZI$$Limit| +; +; + AREA Init, CODE, READONLY +; +;/* Define the default Cortex-A8 vector area. This should be located or copied to 0. */ +; + EXPORT __vectors +__vectors + LDR pc,=__main ; Reset goes to startup function + LDR pc,=__tx_undefined ; Undefined handler + LDR pc,=__tx_swi_interrupt ; Software interrupt handler + LDR pc,=__tx_prefetch_handler ; Prefetch exception handler + LDR pc,=__tx_abort_handler ; Abort exception handler + LDR pc,=__tx_reserved_handler ; Reserved exception handler + LDR pc,=__tx_irq_handler ; IRQ interrupt handler + LDR pc,=__tx_fiq_handler ; FIQ interrupt handler +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; +; /****** NOTE ****** We must be in SVC MODE at this point. Some monitors +; enter this routine in USER mode and require a software interrupt to +; change into SVC mode. */ +; + LDR r1, =|Image$$ZI$$Limit| ; Get end of non-initialized RAM area + LDR r2, =HEAP_SIZE ; Pickup the heap size + ADD r1, r2, r1 ; Setup heap limit + ADD r1, r1, #4 ; Setup stack limit +; + IF :DEF:TX_ENABLE_IRQ_NESTING +; /* Setup the system mode stack for nested interrupt support */ + LDR r2, =SYS_STACK_SIZE ; Pickup stack size + MOV r3, #SYS_MODE ; Build SYS mode CPSR + MSR CPSR_c, r3 ; Enter SYS mode + ADD r1, r1, r2 ; Calculate start of SYS stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup SYS stack pointer + ENDIF +; + LDR r2, =FIQ_STACK_SIZE ; Pickup stack size + MOV r0, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_c, r0 ; Enter FIQ mode + ADD r1, r1, r2 ; Calculate start of FIQ stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup FIQ stack pointer + MOV sl, #0 ; Clear sl + MOV fp, #0 ; Clear fp + LDR r2, =IRQ_STACK_SIZE ; Pickup IRQ (system stack size) + MOV r0, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Enter IRQ mode + ADD r1, r1, r2 ; Calculate start of IRQ stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup IRQ stack pointer + MOV r0, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r0 ; Enter SVC mode + LDR r3, =_tx_thread_system_stack_ptr ; Pickup stack pointer + STR r1, [r3, #0] ; Save the system stack +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; + LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr + LDR r0, [r1, #0] ; Pickup system stack + ADD r0, r0, #4 ; Increment to next free word +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) |Image$$ZI$$Limit| + HEAP + [SYS_STACK] + FIQ_STACK + IRQ_STACK; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Done, return to caller. */ +; + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; +; +;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This +; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; (optionally SYS) stack areas. */ +; + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR r0, =|Image$$ZI$$Limit| ; Get end of non-initialized RAM area + LDR r2, =HEAP_SIZE ; Pickup the heap size + ADD r2, r2, r0 ; Setup heap limit + ADD r3, r2, #4 ; Setup stack limit + MOV r1, r3 ; Setup start of stack + IF :DEF:TX_ENABLE_IRQ_NESTING + LDR r12, =SYS_STACK_SIZE ; Pickup IRQ system stack + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + ENDIF + LDR r12, =FIQ_STACK_SIZE ; Pickup FIQ stack size + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + LDR r12, =IRQ_STACK_SIZE ; Pickup IRQ system stack + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; +;/* Define shells for each of the interrupt vectors. */ +; + EXPORT __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + EXPORT __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt ; Software interrupt handler +; + EXPORT __tx_prefetch_handler +__tx_prefetch_handler + B __tx_prefetch_handler ; Prefetch exception handler +; + EXPORT __tx_abort_handler +__tx_abort_handler + B __tx_abort_handler ; Abort exception handler +; + EXPORT __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; +; + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; + BL _tx_timer_interrupt ; Timer interrupt handler +_tx_not_timer_interrupt +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ + IF :DEF:TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start + ENDIF +; +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ + IF :DEF:TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end + ENDIF +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; + EXPORT __tx_example_vectored_irq_handler +__tx_example_vectored_irq_handler +; +; +; /* Save initial context and call context save to prepare for +; vectored ISR execution. */ +; +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers +; BL _tx_thread_vectored_context_save ; Vectored context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +; IF :DEF:TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +; ENDIF +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +; IF :DEF:TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +; ENDIF +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ + IF :DEF:TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start + ENDIF +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ + IF :DEF:TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end + ENDIF +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; + ELSE + EXPORT __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler + ENDIF +; +; /* Reference build options and version ID to ensure they come in. */ +; + LDR r2, =_tx_build_options ; Pickup build options variable address + LDR r0, [r2, #0] ; Pickup build options content + LDR r2, =_tx_version_id ; Pickup version ID variable address + LDR r0, [r2, #0] ; Pickup version ID content +; +; + END + diff --git a/ports/cortex_a8/ac5/inc/tx_port.h b/ports/cortex_a8/ac5/inc/tx_port.h new file mode 100644 index 00000000..4fb4e180 --- /dev/null +++ b/ports/cortex_a8/ac5/inc/tx_port.h @@ -0,0 +1,334 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A8/AC5 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef __thumb + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (ULONG) __clz((unsigned int) m); \ + b = 31 - b; +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifndef __thumb + +#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; + +#ifdef TX_ENABLE_FIQ_SUPPORT + +/* IRQ and FIQ support. */ + +#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); \ + __disable_fiq(); + +#define TX_RESTORE if (!interrupt_save_disabled) \ + { \ + __enable_irq(); \ + __enable_fiq(); \ + } + +#else + +#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); + +#define TX_RESTORE if (!interrupt_save_disabled) \ + { \ + __enable_irq(); \ + } +#endif + +#else + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); +#endif + + +/* Define VFP extension for the Cortex-A8. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/AC5 Version 6.0 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a8/ac5/readme_threadx.txt b/ports/cortex_a8/ac5/readme_threadx.txt new file mode 100644 index 00000000..ac883521 --- /dev/null +++ b/ports/cortex_a8/ac5/readme_threadx.txt @@ -0,0 +1,547 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A8 + + Thumb & 32-bit Mode + + Using ARM Compiler 5 (AC5) + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +AC5 development environment. At this point you may run the build_threadx.bat +batch file. This will build the ThreadX run-time environment in the +"example_build" directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + +1.1 Building with Project Files + +The ThreadX library can also be built via project files. Simply open +the tx.mcp file with project builder and select make. This will place +the tx.a library file into the Debug sub-directory. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the ARM +Windows-based simulator. + +Building the demonstration is easy; simply execute the build_threadx_demo.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf +is a binary file that can be downloaded and executed on the ARM simulator. + +2.0.1 Building with Project Files + +The ThreadX demonstration can also be built via project files. Simply open +the sample_threadx.mcp file with project builder and select make. This will place +the sample_threadx.axf output image into the Debug sub-directory. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A8 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning +of the Init area should be copied to address 0. + +This is also where initialization of a periodic timer interrupt source +should take place. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Assembler / Compiler Switches + +The following are compiler switches used in building the demonstration +system: + +Compiler Switch Meaning + + -g Specifies debug information + -c Specifies object code generation + --cpu Cortex-A8 Specifies Cortex-A8 instruction set + --apcs /interwork Specifies Thumb/32-bit compatibility + +Linker Switch Meaning + + -d Specifies to retain debug information in output file + -o demo.axf Specifies demo output file name + --elf Specifies elf output file format + --ro Specifies that Read-Only memory starts at address 0 + --first tx_initialize_low_level.o(Init) + Specifies that the first area loaded is Init + --remove Remove unused areas + --list Specifies map file name + --symbols Specifies symbols for map file + --map Creates a map file + +Application Defines + + --PD "TX_ENABLE_FIQ_SUPPORT SETL {TRUE}" This assembler define enables FIQ + interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}" This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. + --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}" This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. In addition, + IRQ nesting should also be enabled. + -DTX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ + interrupt handling in the ThreadX + generic C source. This define + should also be used in conjunction + with the corresponding assembler + define. + -DTX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + -DTX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + + +5. Register Usage and Stack Frames + +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A8 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A8 vectors start at address zero. The demonstration system startup +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save ; Jump to the context save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call(s) go here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + EXPORT __tx_irq_example_handler +__tx_irq_example_handler +; +; /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers + BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, +calling the _tx_thread_irq_nesting_end service disables nesting by disabling +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* Enable nested IRQ interrupts. NOTE: Since this service returns +; with IRQ interrupts enabled, all IRQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +; +; /* Application ISR call(s) go here! */ +; +; /* Disable nested IRQ interrupts. The mode is switched back to +; IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, Cortex-A8 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ handlers can be called here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ handlers can be called here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.s in the Integrator sub-directories. + + +9. Thumb/Cortex-A8 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A8 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built +with the "-apcs /interwork" option. + + +10. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + + +11. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A8 using AC5 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a8/ac5/src/tx_thread_context_restore.s b/ports/cortex_a8/ac5/src/tx_thread_context_restore.s new file mode 100644 index 00000000..905651b4 --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_context_restore.s @@ -0,0 +1,256 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +IRQ_MODE EQU 0xD2 ; IRQ mode +SVC_MODE EQU 0xD3 ; SVC mode + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +IRQ_MODE EQU 0x92 ; IRQ mode +SVC_MODE EQU 0x93 ; SVC mode + ENDIF +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save + ENDIF + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MOV r3, #SVC_MODE ; Build SVC mode with interrupts disabled + MSR CPSR_c, r3 ; Change to SVC mode + B _tx_thread_schedule ; Return to scheduler +;} +; + END + diff --git a/ports/cortex_a8/ac5/src/tx_thread_context_save.s b/ports/cortex_a8/ac5/src/tx_thread_context_save.s new file mode 100644 index 00000000..ff1d228f --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_context_save.s @@ -0,0 +1,200 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_irq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable FIQ interrupts + ENDIF + + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + END + diff --git a/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..f41ee539 --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,259 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE EQU 0xD3 ; SVC mode +FIQ_MODE EQU 0xD1 ; FIQ mode +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + EXPORT _tx_thread_fiq_context_restore +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + CPSID if ; Disable IRQ and FIQ interrupts + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore + +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_c, r2 ; Re-enter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save ; No, skip VFP FIQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_fiq_vfp_save + ENDIF + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r3 ; Enter SVC mode + B _tx_thread_schedule ; Return to scheduler +; +;} +; + END + diff --git a/ports/cortex_a8/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_a8/ac5/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..e31b7ef3 --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_fiq_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_fiq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + EXPORT _tx_thread_fiq_context_save +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} +; + END + diff --git a/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..a1204696 --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,111 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + EXPORT _tx_thread_fiq_nesting_end +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..f2fbf4f9 --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +FIQ_DISABLE EQU 0x40 ; FIQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + EXPORT _tx_thread_fiq_nesting_start +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_c, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a8/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_a8/ac5/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..c743a36d --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_interrupt_control.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +INT_MASK EQU 0xC0 ; Interrupt bit mask + ELSE +INT_MASK EQU 0x80 ; Interrupt bit mask + ENDIF +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} +; + END + diff --git a/ports/cortex_a8/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_a8/ac5/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..02439931 --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_interrupt_disable.s @@ -0,0 +1,95 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(void) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ + ELSE + CPSID i ; Disable IRQ + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a8/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_a8/ac5/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..9d328f1c --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_restore(UINT old_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r0 ; Setup new CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..1999adc1 --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + EXPORT _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} + END + diff --git a/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..5e1071aa --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +IRQ_DISABLE EQU 0x80 ; IRQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + EXPORT _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_c, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a8/ac5/src/tx_thread_schedule.s b/ports/cortex_a8/ac5/src/tx_thread_schedule.s new file mode 100644 index 00000000..0e888c7e --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_schedule.s @@ -0,0 +1,236 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_execute_ptr + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSIE if ; Enable IRQ and FIQ interrupts + ELSE + CPSIE i ; Enable IRQ interrupts + ENDIF +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Enable IRQ and FIQ interrupts + ELSE + CPSID i ; Enable IRQ interrupts + ENDIF +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ; variable + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 + ENDIF +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 ; Setup SPSR for return + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_interrupt_vfp_restore + ENDIF + LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + +_tx_solicited_return + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore + ENDIF + MSR CPSR_cxsf, r5 ; Recover CPSR + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} +; + + IF {TARGET_FPU_VFP} = {TRUE} + EXPORT tx_thread_vfp_enable +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + EXPORT tx_thread_vfp_disable +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + ENDIF + + END + diff --git a/ports/cortex_a8/ac5/src/tx_thread_stack_build.s b/ports/cortex_a8/ac5/src/tx_thread_stack_build.s new file mode 100644 index 00000000..7f7975f2 --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_stack_build.s @@ -0,0 +1,164 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE EQU 0x13 ; SVC mode + IF :DEF:TX_ENABLE_FIQ_SUPPORT +CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled + ELSE +CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled + ENDIF + +THUMB_BIT EQU 0x20 ; Thumb-bit + +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A8 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + + MRS r3, CPSR ; Pickup CPSR + BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r3, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT ; Clear Thumb-bit by default + AND r1, r1, #1 ; Determine if the entry function is in Thumb mode + CMP r1, #1 ; Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT ; Yes, set the Thumb-bit + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} + END + diff --git a/ports/cortex_a8/ac5/src/tx_thread_system_return.s b/ports/cortex_a8/ac5/src/tx_thread_system_return.s new file mode 100644 index 00000000..3812aa90 --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_system_return.s @@ -0,0 +1,159 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context + LDR r5, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r6, [r5, #0] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r0, [r6, #144] ; Pickup the VFP enabled flag + CMP r0, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save + ENDIF + + MOV r0, #0 ; Build a solicited stack type + MRS r1, CPSR ; Pickup the CPSR + STMDB sp!, {r0-r1} ; Save type and CPSR +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function + ENDIF + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r6, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save the current remaining time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r6, #24] ; Store current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r5, #0] ; Clear current thread pointer + + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports/cortex_a8/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_a8/ac5/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..342e8ba7 --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_thread_vectored_context_save.s @@ -0,0 +1,200 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + EXPORT _tx_thread_vectored_context_save +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ENDIF + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + ADD sp, sp, #32 ; Recover saved registers + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +;} +; + END + diff --git a/ports/cortex_a8/ac5/src/tx_timer_interrupt.s b/ports/cortex_a8/ac5/src/tx_timer_interrupt.s new file mode 100644 index 00000000..b71d49b7 --- /dev/null +++ b/ports/cortex_a8/ac5/src/tx_timer_interrupt.s @@ -0,0 +1,258 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A8/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} + END + diff --git a/ports/cortex_a8/gnu/example_build/build_threadx.bat b/ports/cortex_a8/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..a37a3eab --- /dev/null +++ b/ports/cortex_a8/gnu/example_build/build_threadx.bat @@ -0,0 +1,238 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_interrupt_disable.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_interrupt_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_fiq_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_fiq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_irq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_irq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_fiq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_fiq_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 ../src/tx_thread_vectored_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_start.o tx_thread_irq_nesting_start.o tx_thread_irq_nesting_end.o +arm-none-eabi-ar -r tx.a tx_thread_fiq_nesting_end.o tx_thread_fiq_context_restore.o tx_thread_vectored_context_save.o tx_initialize_low_level.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_a8/gnu/example_build/build_threadx_sample.bat b/ports/cortex_a8/gnu/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..aa8c8006 --- /dev/null +++ b/ports/cortex_a8/gnu/example_build/build_threadx_sample.bat @@ -0,0 +1,6 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 reset.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 crt0.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a8 -I../../../../common/inc -I../inc sample_threadx.c +arm-none-eabi-ld -A cortex-a8 -T sample_threadx.ld reset.o crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libc.a libgcc.a -o sample_threadx.out -M > sample_threadx.map + diff --git a/ports/cortex_a8/gnu/example_build/crt0.S b/ports/cortex_a8/gnu/example_build/crt0.S new file mode 100644 index 00000000..aa0f3239 --- /dev/null +++ b/ports/cortex_a8/gnu/example_build/crt0.S @@ -0,0 +1,90 @@ + +/* .text is used instead of .section .text so it works with arm-aout too. */ + .text + .code 32 + .align 0 + + .global _mainCRTStartup + .global _start + .global start +start: +_start: +_mainCRTStartup: + +/* Start by setting up a stack */ + /* Set up the stack pointer to a fixed value */ + ldr r3, .LC0 + mov sp, r3 + /* Setup a default stack-limit in case the code has been + compiled with "-mapcs-stack-check". Hard-wiring this value + is not ideal, since there is currently no support for + checking that the heap and stack have not collided, or that + this default 64k is enough for the program being executed. + However, it ensures that this simple crt0 world will not + immediately cause an overflow event: */ + sub sl, sp, #64 << 10 /* Still assumes 256bytes below sl */ + mov a2, #0 /* Second arg: fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr a1, .LC1 /* First arg: start of memory block */ + ldr a3, .LC2 + sub a3, a3, a1 /* Third arg: length of block */ + + + + bl memset + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ +#ifdef __USES_INITFINI__ + /* Some arm/elf targets use the .init and .fini sections + to create constructors and destructors, and for these + targets we need to call the _init function and arrange + for _fini to be called at program exit. */ + mov r4, r0 + mov r5, r1 +/* ldr r0, .Lfini */ + bl atexit +/* bl init */ + mov r0, r4 + mov r1, r5 +#endif + bl main + + bl exit /* Should not return. */ + + + /* For Thumb, constants must be after the code since only + positive offsets are supported for PC relative addresses. */ + + .align 0 +.LC0: +.LC1: + .word __bss_start__ +.LC2: + .word __bss_end__ +/* +#ifdef __USES_INITFINI__ +.Lfini: + .word _fini +#endif */ + /* Return ... */ +#ifdef __APCS_26__ + movs pc, lr +#else +#ifdef __THUMB_INTERWORK + bx lr +#else + mov pc, lr +#endif +#endif + + +/* Workspace for Angel calls. */ + .data +/* Data returned by monitor SWI. */ +.global __stack_base__ +HeapBase: .word 0 +HeapLimit: .word 0 +__stack_base__: .word 0 +StackLimit: .word 0 diff --git a/ports/cortex_a8/gnu/example_build/libc.a b/ports/cortex_a8/gnu/example_build/libc.a new file mode 100644 index 0000000000000000000000000000000000000000..5b04fa4ed9b6479f70979f5577dd0705d1f6d1d7 GIT binary patch literal 2447586 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zyyk;0u~c5dm1R37av%P?23us%dHPGDpFT$0GBczAKYnN6rVuiJ<@W-;X3iNSdGtC4 zZc0Al4tY)&I-P!o0#6|ykg|z--55Au=wiVt!DWKHH_4BuyvA0+F2RcgFA>}#_#GlT dhn|!HpOEmEh$!@SiRZoRqCc?z|Ecwv{|7^Je? +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef __thumb__ + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); +#else +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) ); +#endif + +#define TX_RESTORE asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) ); + +#endif + + +/* Define VFP extension for the Cortex-A8. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/GNU Version 6.0 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a8/gnu/readme_threadx.txt b/ports/cortex_a8/gnu/readme_threadx.txt new file mode 100644 index 00000000..bc4d709a --- /dev/null +++ b/ports/cortex_a8/gnu/readme_threadx.txt @@ -0,0 +1,513 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A8 + + Using the GNU Tools + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. + +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + + +2. Demonstration System + +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file +that can be downloaded and executed. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A8 using GNU tools is at label _start. +This is defined within the modified version of the GNU startup code - crt0.S. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied +to address 0. + +This is also where initialization of a periodic timer interrupt source should take +place. + +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter +to your application definition function, tx_application_define. + + +4. Assembler / Compiler Switches + +The following are compiler switches used in building the demonstration +system: + +Compiler/Assembler Meaning + Switches + + -g Specifies debug information + -c Specifies object code generation + -mcpu=cortex-a8 Specifies target cpu + +Linker Switch Meaning + + -o sample_threadx.out Specifies output file + -M > sample_threadx.map Specifies demo map file + -A cortex-a8 Specifies target architecture + -T sample_threadx.ld Specifies the loader control file + +Application Defines ( -D option) + + TX_ENABLE_FIQ_SUPPORT This assembler define enables FIQ + interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + + TX_ENABLE_IRQ_NESTING This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.S. + + TX_ENABLE_FIQ_NESTING This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.S. In addition, + IRQ nesting should also be enabled. + + TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ + interrupt handling in the ThreadX + generic C source. This define + should also be used in conjunction + with the corresponding assembler + define. + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + +5. Register Usage and Stack Frames + +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) a8 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 a8 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A8 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A8 vectors start at address zero. The demonstration system startup +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +nested IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.S: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save @ Jump to the context save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.S: + + .global __tx_irq_example_handler +__tx_irq_example_handler: +@ +@ /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} @ Save some scratch registers + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers + BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call goes here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* Enable nested IRQ interrupts. NOTE: Since this service returns +@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Disable nested IRQ interrupts. The mode is switched back to +@ IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.S. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.S: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Enable nested FIQ interrupts. NOTE: Since this service returns +@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Disable nested FIQ interrupts. The mode is switched back to +@ FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of +ThreadX will still run. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.S for the demonstration system. + + +9. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A8 using GNU tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a8/gnu/src/tx_thread_context_restore.S b/ports/cortex_a8/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..91b1c150 --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,257 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE = 0xD3 @ Disable IRQ/FIQ, SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE = 0x93 @ Disable IRQ, SVC mode +IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode +#endif +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_restore @ Yes, idle system was interrupted +@ + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_preempt_restore @ No, preemption needs to happen +@ +@ +__tx_thread_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_preempt_restore: +@ + LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r2 @ Enter IRQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r0 @ Enter SVC mode + B _tx_thread_schedule @ Return to scheduler +@} + + + diff --git a/ports/cortex_a8/gnu/src/tx_thread_context_save.S b/ports/cortex_a8/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..8c55a18b --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_context_save.S @@ -0,0 +1,203 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_irq_processing_return + .global _tx_execution_isr_enter +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} @ Store other registers +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr@ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #16 @ Recover saved registers + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@} + + + diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S new file mode 100644 index 00000000..ee677edf --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_restore.S @@ -0,0 +1,260 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ +SVC_MODE = 0xD3 @ SVC mode +FIQ_MODE = 0xD1 @ FIQ mode +MODE_MASK = 0x1F @ Mode mask +THUMB_MASK = 0x20 @ Thumb bit mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_context_restore(VOID) +@{ + .global _tx_thread_fiq_context_restore + .type _tx_thread_fiq_context_restore,function +_tx_thread_fiq_context_restore: +@ +@ /* Lockout interrupts. */ +@ + CPSID if @ Disable IRQ and FIQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_fiq_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, [sp] @ Pickup the saved SPSR + MOV r2, #MODE_MASK @ Build mask to isolate the interrupted mode + AND r1, r1, r2 @ Isolate mode bits + CMP r1, #IRQ_MODE_BITS @ Was an interrupt taken in IRQ mode before we + @ got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore @ Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore @ Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_fiq_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore @ No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_fiq_preempt_restore: +@ + LDMIA sp!, {r3, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR_c, r2 @ Reenter FIQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block */ +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_fiq_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_fiq_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + ADD sp, sp, #24 @ Recover FIQ stack space + MOV r3, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r3 @ Lockout interrupts + B _tx_thread_schedule @ Return to scheduler +@ +@} + diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S new file mode 100644 index 00000000..3a3eda70 --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_context_save.S @@ -0,0 +1,204 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_fiq_processing_return + .global _tx_execution_isr_enter +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@ VOID _tx_thread_fiq_context_save(VOID) +@{ + .global _tx_thread_fiq_context_save + .type _tx_thread_fiq_context_save,function +_tx_thread_fiq_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +__tx_thread_fiq_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, lr} @ Store other registers, Note that we don't +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested +@ @ interrupt processing does need to save +@ @ these registers. +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_fiq_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif +@ +@ /* Not much to do here, save the current SPSR and LR for possible +@ use in IRQ interrupted in idle system conditions, and return to +@ FIQ interrupt processing. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, lr} @ Store other registers that will get used +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@} + diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S new file mode 100644 index 00000000..71ac82b3 --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_end.S @@ -0,0 +1,116 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +FIQ_MODE_BITS = 0x11 @ FIQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_end(VOID) +@{ + .global _tx_thread_fiq_nesting_end + .type _tx_thread_fiq_nesting_end,function +_tx_thread_fiq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode + +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S new file mode 100644 index 00000000..f4ae9a78 --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_fiq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +FIQ_DISABLE = 0x40 @ FIQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_start(VOID) +@{ + .global _tx_thread_fiq_nesting_start + .type _tx_thread_fiq_nesting_start,function +_tx_thread_fiq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..ce0949ec --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" */ +@ + +INT_MASK = 0x03F + +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_control +$_tx_thread_interrupt_control: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_control(UINT new_posture) +@{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r3, CPSR @ Pickup current CPSR + MOV r2, #INT_MASK @ Build interrupt mask + AND r1, r3, r2 @ Clear interrupt lockout bits + ORR r1, r1, r0 @ Or-in new interrupt lockout bits +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r1 @ Setup new CPSR + BIC r0, r3, r2 @ Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..ea6f1193 --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_disable.S @@ -0,0 +1,113 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_disable +$_tx_thread_interrupt_disable: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_disable(void) +@{ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r0, CPSR @ Pickup current CPSR +@ +@ /* Mask interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ +#else + CPSID i @ Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..63ca62d9 --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_interrupt_restore.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_restore +$_tx_thread_interrupt_restore: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring interrupts to the state */ +@/* returned by a previous _tx_thread_interrupt_disable call. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_restore(UINT old_posture) +@{ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r0 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..b892370b --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_end(VOID) +@{ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..f8cd2efd --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +IRQ_DISABLE = 0x80 @ IRQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_start(VOID) +@{ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a8/gnu/src/tx_thread_schedule.S b/ports/cortex_a8/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..a6e0293f --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_schedule.S @@ -0,0 +1,255 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_execution_thread_enter +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_schedule + .type $_tx_thread_schedule,function +$_tx_thread_schedule: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_schedule @ Call _tx_thread_schedule function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: +@ +@ /* Enable interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if @ Enable IRQ and FIQ interrupts +#else + CPSIE i @ Enable IRQ interrupts +#endif +@ +@ /* Wait for a thread to execute. */ +@ do +@ { + LDR r1, =_tx_thread_execute_ptr @ Address of thread execute ptr +@ +__tx_thread_schedule_loop: +@ + LDR r0, [r1] @ Pickup next thread to execute + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_schedule_loop @ If so, keep looking for a thread +@ +@ } +@ while(_tx_thread_execute_ptr == TX_NULL); +@ +@ /* Yes! We have a thread to execute. Lockout interrupts and +@ transfer control to it. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Setup the current thread pointer. */ +@ _tx_thread_current_ptr = _tx_thread_execute_ptr; +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + STR r0, [r1] @ Setup current thread pointer +@ +@ /* Increment the run count for this thread. */ +@ _tx_thread_current_ptr -> tx_thread_run_count++; +@ + LDR r2, [r0, #4] @ Pickup run counter + LDR r3, [r0, #24] @ Pickup time-slice for this thread + ADD r2, r2, #1 @ Increment thread run-counter + STR r2, [r0, #4] @ Store the new run counter +@ +@ /* Setup time-slice, if present. */ +@ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + @ variable + LDR sp, [r0, #8] @ Switch stack pointers + STR r3, [r2] @ Setup time-slice +@ +@ /* Switch to the thread's stack. */ +@ sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + MOV r5, r0 @ Save r0 + BL _tx_execution_thread_enter @ Call the thread execution enter function + MOV r0, r5 @ Restore r0 +#endif +@ +@ /* Determine if an interrupt frame or a synchronous task suspension frame +@ is present. */ +@ + LDMIA sp!, {r4, r5} @ Pickup the stack type and saved CPSR + CMP r4, #0 @ Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 @ Setup SPSR for return +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore @ No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} @ Recover D0-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt + +_tx_solicited_return: + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore @ No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} @ Recover D8-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 @ Recover CPSR + LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ + +#ifdef TX_ENABLE_VFP_SUPPORT + + .global tx_thread_vfp_enable + .type tx_thread_vfp_enable,function +tx_thread_vfp_enable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable + MOV r0, #1 @ Build enable value + STR r0, [r1, #144] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + + .global tx_thread_vfp_disable + .type tx_thread_vfp_disable,function +tx_thread_vfp_disable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable + MOV r0, #0 @ Build disable value + STR r0, [r1, #144] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + +#endif + diff --git a/ports/cortex_a8/gnu/src/tx_thread_stack_build.S b/ports/cortex_a8/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..4de92045 --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,178 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ + .arm + +SVC_MODE = 0x13 @ SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ interrupts enabled +#else +CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interrupts enabled +#endif +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_thread_stack_build + .type $_tx_thread_stack_build,function +$_tx_thread_stack_build: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_stack_build @ Call _tx_thread_stack_build function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-A8 should look like the following after it is built: +@ +@ Stack Top: 1 Interrupt stack frame type +@ CPSR Initial value for CPSR +@ a1 (r0) Initial value for a1 +@ a2 (r1) Initial value for a2 +@ a3 (r2) Initial value for a3 +@ a4 (r3) Initial value for a4 +@ v1 (r4) Initial value for v1 +@ v2 (r5) Initial value for v2 +@ v3 (r6) Initial value for v3 +@ v4 (r7) Initial value for v4 +@ v5 (r8) Initial value for v5 +@ sb (r9) Initial value for sb +@ sl (r10) Initial value for sl +@ fp (r11) Initial value for fp +@ ip (r12) Initial value for ip +@ lr (r14) Initial value for lr +@ pc (r15) Initial value for pc +@ 0 For stack backtracing +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #7 @ Ensure 8-byte alignment + SUB r2, r2, #76 @ Allocate space for the stack frame +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #1 @ Build interrupt stack type + STR r3, [r2, #0] @ Store stack type + MOV r3, #0 @ Build initial register value + STR r3, [r2, #8] @ Store initial r0 + STR r3, [r2, #12] @ Store initial r1 + STR r3, [r2, #16] @ Store initial r2 + STR r3, [r2, #20] @ Store initial r3 + STR r3, [r2, #24] @ Store initial r4 + STR r3, [r2, #28] @ Store initial r5 + STR r3, [r2, #32] @ Store initial r6 + STR r3, [r2, #36] @ Store initial r7 + STR r3, [r2, #40] @ Store initial r8 + STR r3, [r2, #44] @ Store initial r9 + LDR r3, [r0, #12] @ Pickup stack starting address + STR r3, [r2, #48] @ Store initial r10 (sl) + LDR r3,=_tx_thread_schedule @ Pickup address of _tx_thread_schedule for GDB backtrace + STR r3, [r2, #60] @ Store initial r14 (lr) + MOV r3, #0 @ Build initial register value + STR r3, [r2, #52] @ Store initial r11 + STR r3, [r2, #56] @ Store initial r12 + STR r1, [r2, #64] @ Store initial pc + STR r3, [r2, #68] @ 0 for back-trace + MRS r1, CPSR @ Pickup CPSR + BIC r1, r1, #CPSR_MASK @ Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] @ Store initial CPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a8/gnu/src/tx_thread_system_return.S b/ports/cortex_a8/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..28c756e5 --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_system_return.S @@ -0,0 +1,180 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm +@ +@ + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_execution_thread_exit +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_system_return + .type $_tx_thread_system_return,function +$_tx_thread_system_return: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_system_return @ Call _tx_thread_system_return function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_system_return(VOID) +@{ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: +@ +@ /* Save minimal context on the stack. */ +@ + STMDB sp!, {r4-r11, lr} @ Save minimal context + + LDR r4, =_tx_thread_current_ptr @ Pickup address of current ptr + LDR r5, [r4] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r5, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save @ No, skip VFP solicited save + VMRS r1, FPSCR @ Pickup the FPSCR + STR r1, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D8-D15} @ Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 @ Build a solicited stack type + MRS r1, CPSR @ Pickup the CPSR + STMDB sp!, {r0-r1} @ Save type and CPSR +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + BL _tx_execution_thread_exit @ Call the thread exit function +#endif + MOV r3, r4 @ Pickup address of current ptr + MOV r0, r5 @ Pickup current thread pointer + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + LDR r1, [r2] @ Pickup current time slice +@ +@ /* Save current stack and switch to system stack. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ sp = _tx_thread_system_stack_ptr; +@ + STR sp, [r0, #8] @ Save thread stack pointer +@ +@ /* Determine if the time-slice is active. */ +@ if (_tx_timer_time_slice) +@ { +@ + MOV r4, #0 @ Build clear value + CMP r1, #0 @ Is a time-slice active? + BEQ __tx_thread_dont_save_ts @ No, don't save the time-slice +@ +@ /* Save time-slice for the thread and clear the current time-slice. */ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r4, [r2] @ Clear time-slice + STR r1, [r0, #24] @ Save current time-slice +@ +@ } +__tx_thread_dont_save_ts: +@ +@ /* Clear the current thread pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + STR r4, [r3] @ Clear current thread pointer + B _tx_thread_schedule @ Jump to scheduler! +@ +@} + diff --git a/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..96f8d0eb --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_thread_vectored_context_save.S @@ -0,0 +1,190 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_execution_isr_enter +@ +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_vectored_context_save(VOID) +@{ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #32 @ Recover saved registers + MOV pc, lr @ Return to caller +@ +@ } +@} + diff --git a/ports/cortex_a8/gnu/src/tx_timer_interrupt.S b/ports/cortex_a8/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..501b2771 --- /dev/null +++ b/ports/cortex_a8/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,279 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ + .arm + +@ +@/* Define Assembly language external references... */ +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_timer_interrupt + .type $_tx_timer_interrupt,function +$_tx_timer_interrupt: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_timer_interrupt @ Call _tx_timer_interrupt function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-A8/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1] @ Pickup current timer + LDR r2, [r0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wraparound. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup address of timer list end + LDR r2, [r3] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wraparound logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup address of timer list start + LDR r0, [r3] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + LDR r2, [r3] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup address of other expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup address of expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r2, [r3] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} + diff --git a/ports/cortex_a8/iar/example_build/azure_rtos.eww b/ports/cortex_a8/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..17e0d329 --- /dev/null +++ b/ports/cortex_a8/iar/example_build/azure_rtos.eww @@ -0,0 +1,13 @@ + + + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\tx.ewp + + + + + diff --git a/ports/cortex_a8/iar/example_build/cstartup.s b/ports/cortex_a8/iar/example_build/cstartup.s new file mode 100644 index 00000000..b95efc0e --- /dev/null +++ b/ports/cortex_a8/iar/example_build/cstartup.s @@ -0,0 +1,161 @@ + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 14520 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector + PUBLIC __vector_0x14 + PUBLIC __iar_program_start + EXTERN __tx_undefined + EXTERN __tx_swi_interrupt + EXTERN __tx_prefetch_handler + EXTERN __tx_abort_handler + EXTERN __tx_irq_handler + EXTERN __tx_fiq_handler + + ARM +__vector: + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort +__vector_0x14: + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + +Reset_Addr: DCD __iar_program_start +Undefined_Addr: DCD __tx_undefined +SWI_Addr: DCD __tx_swi_interrupt +Prefetch_Addr: DCD __tx_prefetch_handler +Abort_Addr: DCD __tx_abort_handler +IRQ_Addr: DCD __tx_irq_handler +FIQ_Addr: DCD __tx_fiq_handler + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reser execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + +; PUBLIC ?cstartup + EXTERN ?main + REQUIRE __vector + + ARM + +__iar_program_start: +?cstartup: + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR + +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + + + MRS r0, cpsr ; Original PSR value + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + +#ifdef __ARMVFP__ + ;; Enable the VFP coprocessor. + + MOV r0, #0x40000000 ; Set EN bit in VFP + FMXR fpexc, r0 ; FPEXC, clear others. + +; +; Disable underflow exceptions by setting flush to zero mode. +; For full IEEE 754 underflow compliance this code should be removed +; and the appropriate exception handler installed. +; + + MOV r0, #0x01000000 ; Set FZ bit in VFP + FMXR fpscr, r0 ; FPSCR, clear others. +#endif + +; +; Add more initialization here +; + +; Continue to ?main for C-level initialization. + + B ?main + + END + + + diff --git a/ports/cortex_a8/iar/example_build/sample_threadx.c b/ports/cortex_a8/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..c7c300cb --- /dev/null +++ b/ports/cortex_a8/iar/example_build/sample_threadx.c @@ -0,0 +1,372 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +UCHAR memory_pool[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_pool, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a8/iar/example_build/sample_threadx.dep b/ports/cortex_a8/iar/example_build/sample_threadx.dep new file mode 100644 index 00000000..fcb0bb93 --- /dev/null +++ b/ports/cortex_a8/iar/example_build/sample_threadx.dep @@ -0,0 +1,222 @@ + + + 4 + 1829555607 + + Debug + + $PROJ_DIR$\sample_threadx.c + $TOOLKIT_DIR$\inc\ycheck.h + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $PROJ_DIR$\Debug\Exe\tx.a + $TOOLKIT_DIR$\inc\string.h + $PROJ_DIR$\Debug\List\cstartup.lst + $PROJ_DIR$\sample_threadx.icf + $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h + $PROJ_DIR$\tx_api.h + $PROJ_DIR$\tx_port.h + $PROJ_DIR$\cstartup.s + $PROJ_DIR$\tx_initialize_low_level.s + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $PROJ_DIR$\Debug\Obj\tx_initialize_low_level.o + $PROJ_DIR$\Debug\Obj\demo.r79 + $TOOLKIT_DIR$\inc\c\yvals.h + $TOOLKIT_DIR$\inc\c\DLib_Product_string.h + $PROJ_DIR$\Debug\Obj\tx_execution_profile.o + $PROJ_DIR$\Debug\Obj\tx_execution_profile.pbi + $PROJ_DIR$\Debug\Obj\tx_cstartup.r79 + $PROJ_DIR$\tx_execution_profile.c + $TOOLKIT_DIR$\inc\yvals.h + $TOOLKIT_DIR$\inc\c\ysizet.h + $TOOLKIT_DIR$\inc\stdlib.h + $TOOLKIT_DIR$\inc\c\stdlib.h + $TOOLKIT_DIR$\inc\c\intrinsics.h + $PROJ_DIR$\tx_initialize_low_level.s79 + $TOOLKIT_DIR$\inc\c\string.h + $TOOLKIT_DIR$\inc\DLib_Defaults.h + $PROJ_DIR$\DEMO.C + $PROJ_DIR$\Debug\Obj\sample_threadx.o + $TOOLKIT_DIR$\inc\DLib_Config_Normal.h + $PROJ_DIR$\cstartup.s79 + $PROJ_DIR$\Debug\List\tx_initialize_low_level.lst + $PROJ_DIR$\Debug\Obj\cstartup.o + $PROJ_DIR$\tx_cstartup.s79 + $PROJ_DIR$\Debug\List\sample_threadx.map + $TOOLKIT_DIR$\inc\ysizet.h + $PROJ_DIR$\Debug\Obj\TX_ILL.r79 + $TOOLKIT_DIR$\inc\c\ycheck.h + $TOOLKIT_DIR$\inc\DLib_Product.h + $PROJ_DIR$\TX_ILL.s79 + $PROJ_DIR$\Debug\Obj\sample_threadx.pbd + $TOOLKIT_DIR$\inc\intrinsics.h + $TOOLKIT_DIR$\lib\rt7Sx_tl.a + $TOOLKIT_DIR$\inc\xencoding_limits.h + $TOOLKIT_DIR$\lib\m7Sx_tl.a + $TOOLKIT_DIR$\lib\sh7Sxs_l.a + $TOOLKIT_DIR$\lib\dl7Sx_tln.a + $PROJ_DIR$\Debug\Obj\sample_threadx.xcl + $TOOLKIT_DIR$\inc\DLib_Product_string.h + $TOOLKIT_DIR$\inc\DLib_Threads.h + $PROJ_DIR$\Debug\Exe\sample_threadx.out + $TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_api.h + $TOOLKIT_DIR$\inc\c\iccarm_builtin.h + $PROJ_DIR$\..\inc\tx_port.h + $TOOLKIT_DIR$\inc\c\iar_intrinsics_common.h + $PROJ_DIR$\Debug\Obj\sample_threadx.__cstat.et + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_receive.c + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_receive.c + $PROJ_DIR$\..\..\..\..\common\src\tx_queue_send.c + + + [ROOT_NODE] + + + ILINK + 52 36 + + + + + $PROJ_DIR$\sample_threadx.c + + + ICCARM + 30 + + + BICOMP + 49 + + + __cstat + 58 + + + + + ICCARM + 54 56 24 39 15 12 7 2 22 53 27 16 25 55 57 + + + + + $PROJ_DIR$\cstartup.s + + + AARM + 34 5 + + + + + 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+ + + + + Common sources + + $PROJ_DIR$\cstartup.s + + + $PROJ_DIR$\sample_threadx.c + + + $PROJ_DIR$\Debug\Exe\tx.a + + + $PROJ_DIR$\tx_initialize_low_level.s + + + diff --git a/ports/cortex_a8/iar/example_build/sample_threadx.icf b/ports/cortex_a8/iar/example_build/sample_threadx.icf new file mode 100644 index 00000000..9c95e1d1 --- /dev/null +++ b/ports/cortex_a8/iar/example_build/sample_threadx.icf @@ -0,0 +1,49 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x80; +define symbol __ICFEDIT_region_ROM_end__ = 0x1FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x100000; +define symbol __ICFEDIT_region_RAM_end__ = 0x1FFFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_size_freemem__ = 0x100000; + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_freemem = mem:[from 0x200000 to 0x300000]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}; + +place in RAM_region { last section FREE_MEM}; \ No newline at end of file diff --git a/ports/cortex_a8/iar/example_build/settings/azure_rtos.wsdt b/ports/cortex_a8/iar/example_build/settings/azure_rtos.wsdt new file mode 100644 index 00000000..8c984b82 --- /dev/null +++ b/ports/cortex_a8/iar/example_build/settings/azure_rtos.wsdt @@ -0,0 +1,535 @@ + + + + + sample_threadx/Debug + tx/Debug + + sample_threadx + 1 + + + + + 21 + 2518 + 2 + + 0 + -1 + + + + 34001 + 0 + + + + + 57600 + 57601 + 57603 + 33024 + 0 + 57607 + 0 + 57635 + 57634 + 57637 + 0 + 57643 + 57644 + 0 + 33090 + 33057 + 57636 + 57640 + 57641 + 33026 + 33065 + 33063 + 33064 + 33053 + 33054 + 0 + 33035 + 33036 + 34399 + 0 + 33038 + 33039 + 0 + + + + + 288 + 30 + 30 + 30 + + + <ws> + + + + 14 + 25 + + + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 010000000900259600000200000010860000120000000C8100000A000000048600000200000017810000040000000E8100000100000011860000120000004681000003000000E880000003000000 + + + 0A000D8400000F84000008840000FFFFFFFF54840000328100001C810000098400000E84000030840000 + 0400048400004C000000068400004E0000000B8100001B0000000D8100001D000000 + + + 0 + 0A0000000A0000006E0000006E000000 + 000000004E050000000A000061050000 + 4096 + 0 + 0 + 32767 + 0 + + + 1 + + + 34051 + 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+ + + 34050 + 0A0000000A0000006E0000006E000000 + 0000000000000000FE0200001A000000 + 8192 + 0 + 0 + 744 + 0 + + + 1 + + + + 34048 + 34049 + 34050 + 34051 + 34052 + 34053 + 34054 + 34055 + 34056 + 34057 + 34058 + 34059 + 34060 + 34061 + 34062 + 34063 + 34064 + 34065 + + + + 01000000030000000100000000000000000000000100000001000000FFFFFFFF00000000010000000100000000000000280000002800000000000000 + + + + diff --git a/ports/cortex_a8/iar/example_build/settings/sample_threadx.Debug.cspy.bat b/ports/cortex_a8/iar/example_build/settings/sample_threadx.Debug.cspy.bat new file mode 100644 index 00000000..daca6403 --- /dev/null +++ b/ports/cortex_a8/iar/example_build/settings/sample_threadx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a8\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a8\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a8\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a8\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports/cortex_a8/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports/cortex_a8/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 new file mode 100644 index 00000000..6103fd44 --- /dev/null +++ b/ports/cortex_a8/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a8\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a8\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a8\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a8\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} diff --git a/ports/cortex_a8/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports/cortex_a8/iar/example_build/settings/sample_threadx.Debug.driver.xcl new file mode 100644 index 00000000..36278b8c --- /dev/null +++ b/ports/cortex_a8/iar/example_build/settings/sample_threadx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-A8" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/cortex_a8/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports/cortex_a8/iar/example_build/settings/sample_threadx.Debug.general.xcl new file mode 100644 index 00000000..66d13c65 --- /dev/null +++ b/ports/cortex_a8/iar/example_build/settings/sample_threadx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files 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+ + + 34124 + 0A0000000A0000006E0000006E000000 + 0000000000000000150300001A000000 + 8192 + 0 + 0 + 32767 + 0 + + + 1 + + + + diff --git a/ports/cortex_a8/iar/example_build/settings/sample_threadx.dnx b/ports/cortex_a8/iar/example_build/settings/sample_threadx.dnx new file mode 100644 index 00000000..d4670025 --- /dev/null +++ b/ports/cortex_a8/iar/example_build/settings/sample_threadx.dnx @@ -0,0 +1,99 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + 1 + + + 1043574536 + + + 0 + 0 + 0 + + + 0 + + + _ 0 + _ 0 + + + 0 + + + 0 + 1 + 0 + 0 + + + 0 + + + 1 + + + _ 0 + _ "" + + + _ 0 + _ "" + _ 0 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + _ 0 9999 0 9999 1 0 0 100 0 1 "IRQ 1 0x18 CPSR.I" + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports/cortex_a8/iar/example_build/settings/tx.Debug.cspy.bat b/ports/cortex_a8/iar/example_build/settings/tx.Debug.cspy.bat new file mode 100644 index 00000000..256ebf4d --- /dev/null +++ b/ports/cortex_a8/iar/example_build/settings/tx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports/cortex_a8/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports/cortex_a8/iar/example_build/settings/tx.Debug.cspy.ps1 new file mode 100644 index 00000000..6a1889c0 --- /dev/null +++ b/ports/cortex_a8/iar/example_build/settings/tx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} diff --git a/ports/cortex_a8/iar/example_build/settings/tx.Debug.driver.xcl b/ports/cortex_a8/iar/example_build/settings/tx.Debug.driver.xcl new file mode 100644 index 00000000..36278b8c --- /dev/null +++ b/ports/cortex_a8/iar/example_build/settings/tx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-A8" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/cortex_a8/iar/example_build/settings/tx.Debug.general.xcl b/ports/cortex_a8/iar/example_build/settings/tx.Debug.general.xcl new file mode 100644 index 00000000..deeeb2f9 --- /dev/null +++ b/ports/cortex_a8/iar/example_build/settings/tx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armsim2.dll" + +"C:\release\threadx\Debug\Exe\tx.out" + +--plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armbat.dll" + + + + diff --git a/ports/cortex_a8/iar/example_build/settings/tx.crun b/ports/cortex_a8/iar/example_build/settings/tx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/cortex_a8/iar/example_build/settings/tx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports/cortex_a8/iar/example_build/settings/tx.dbgdt b/ports/cortex_a8/iar/example_build/settings/tx.dbgdt new file mode 100644 index 00000000..73e71f6e --- /dev/null +++ b/ports/cortex_a8/iar/example_build/settings/tx.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports/cortex_a8/iar/example_build/settings/tx.dnx b/ports/cortex_a8/iar/example_build/settings/tx.dnx new file mode 100644 index 00000000..1872e83f --- /dev/null +++ b/ports/cortex_a8/iar/example_build/settings/tx.dnx @@ -0,0 +1,58 @@ + + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports/cortex_a8/iar/example_build/tx.dep b/ports/cortex_a8/iar/example_build/tx.dep new file mode 100644 index 00000000..d3f1fdc6 --- /dev/null +++ b/ports/cortex_a8/iar/example_build/tx.dep @@ -0,0 +1,9603 @@ + + + 4 + 2050279214 + + Debug + + $PROJ_DIR$\Debug\Obj\tx_queue_create.o + $PROJ_DIR$\Debug\Obj\tx_thread_irq_nesting_start.o + $PROJ_DIR$\Debug\Obj\txe_timer_delete.pbi + $PROJ_DIR$\Debug\Obj\tx_semaphore_prioritize.pbi + $PROJ_DIR$\Debug\Obj\txe_thread_time_slice_change.o + $PROJ_DIR$\Debug\Obj\tx_mutex_performance_system_info_get.pbi + $PROJ_DIR$\Debug\Obj\tx_mutex_put.pbi + $PROJ_DIR$\Debug\Obj\txe_queue_front_send.o + $PROJ_DIR$\Debug\Obj\tx_timer_thread_entry.pbi + $PROJ_DIR$\Debug\Obj\tx_thread_time_slice_change.pbi + $PROJ_DIR$\Debug\Obj\tx_semaphore_initialize.o + $PROJ_DIR$\Debug\Obj\txe_thread_preemption_change.pbi + $PROJ_DIR$\Debug\Obj\tx.pbd + $PROJ_DIR$\Debug\Obj\tx_event_flags_performance_info_get.pbi + $PROJ_DIR$\Debug\Obj\tx_thread_identify.o + $PROJ_DIR$\Debug\Obj\txe_event_flags_get.pbi + $PROJ_DIR$\Debug\Obj\tx_thread_time_slice.pbi + $PROJ_DIR$\Txe_bpc.c + $PROJ_DIR$\Txe_qfs.c + $PROJ_DIR$\Debug\Obj\tx_semaphore_info_get.pbi + $PROJ_DIR$\Tx_efd.c + $PROJ_DIR$\Debug\Obj\txe_semaphore_ceiling_put.pbi + $PROJ_DIR$\Debug\Obj\tx_timer_thread_entry.o + $PROJ_DIR$\Debug\Exe\tx.a + $PROJ_DIR$\Txe_tda.c + $PROJ_DIR$\Debug\Obj\tx_byte_pool_performance_info_get.pbi + $PROJ_DIR$\Debug\Obj\tx_mutex_create.pbi + $PROJ_DIR$\Txe_qd.c + $PROJ_DIR$\Tx_bpc.c + $PROJ_DIR$\Txe_tdel.c + $PROJ_DIR$\Debug\Obj\tx_initialize_kernel_setup.pbi + $PROJ_DIR$\Debug\Obj\tx_event_flags_set_notify.o + $PROJ_DIR$\Debug\Obj\tx_time_set.o + $PROJ_DIR$\Debug\Obj\tx_event_flags_get.o + $PROJ_DIR$\Debug\Obj\tx_byte_pool_performance_system_info_get.pbi + $PROJ_DIR$\Debug\Obj\tx_block_release.pbi + $PROJ_DIR$\Debug\Obj\txe_event_flags_set_notify.o + $PROJ_DIR$\Debug\Obj\tx_mutex_performance_system_info_get.o + $PROJ_DIR$\Txe_mg.c + $PROJ_DIR$\Debug\Obj\tx_thread_system_suspend.pbi + $PROJ_DIR$\Debug\Obj\tx_queue_delete.pbi + $PROJ_DIR$\Debug\Obj\tx_block_pool_delete.pbi + $PROJ_DIR$\Debug\Obj\tx_block_pool_cleanup.o + $PROJ_DIR$\Debug\Obj\tx_semaphore_put_notify.pbi + $PROJ_DIR$\Debug\Obj\tx_thread_stack_error_handler.pbi + $PROJ_DIR$\Debug\Obj\txe_thread_reset.pbi + $PROJ_DIR$\Debug\Obj\tx_thread_reset.pbi + $PROJ_DIR$\Debug\Obj\tx_time_get.o + $PROJ_DIR$\Debug\Obj\tx_timer_performance_info_get.o + $PROJ_DIR$\Debug\Obj\tx_mutex_delete.o + $PROJ_DIR$\Tx_tsa.c + $PROJ_DIR$\Debug\Obj\tx_timer_expiration_process.o + $PROJ_DIR$\Debug\Obj\tx_trace_isr_enter_insert.pbi + $PROJ_DIR$\Tx_qc.c + $PROJ_DIR$\Debug\Obj\tx_mutex_prioritize.o + $PROJ_DIR$\Debug\Obj\txe_mutex_info_get.o + $PROJ_DIR$\Tx_trel.c + $PROJ_DIR$\Tx_tdel.c + $PROJ_DIR$\Debug\Obj\tx_timer_delete.pbi + $PROJ_DIR$\Txe_mig.c + $PROJ_DIR$\Debug\Obj\txe_byte_pool_prioritize.o + $PROJ_DIR$\Debug\Obj\tx_queue_initialize.pbi + $PROJ_DIR$\Txe_trel.c + $PROJ_DIR$\Tx_mpri.c + $PROJ_DIR$\Debug\Obj\txe_semaphore_create.pbi + $PROJ_DIR$\Debug\Obj\tx_trace_initialize.o + $PROJ_DIR$\Debug\Obj\tx_trace_initialize.pbi + $PROJ_DIR$\Debug\Obj\tx_initialize_kernel_enter.pbi + $PROJ_DIR$\Debug\Obj\tx_thread_stack_error_notify.pbi + $PROJ_DIR$\Txe_bytp.c + $PROJ_DIR$\Debug\Obj\tx_iar.o + $PROJ_DIR$\Tx_byts.c + $PROJ_DIR$\Debug\Obj\txe_queue_front_send.pbi + $PROJ_DIR$\Debug\Obj\tx_timer_performance_system_info_get.pbi + $PROJ_DIR$\Debug\Obj\tx_thread_vectored_context_save.o + $PROJ_DIR$\Tx_qp.c + $PROJ_DIR$\Txe_twa.c + $PROJ_DIR$\Debug\Obj\tx_timer_create.pbi + $PROJ_DIR$\Debug\Obj\tx_byte_pool_initialize.o + $PROJ_DIR$\Debug\Obj\tx_semaphore_performance_system_info_get.o + $PROJ_DIR$\Txe_byta.c + $PROJ_DIR$\Tx_qig.c + $PROJ_DIR$\Tx_td.c + $PROJ_DIR$\Debug\Obj\txe_queue_prioritize.pbi + $PROJ_DIR$\Tx_tsle.c + $PROJ_DIR$\Debug\Obj\tx_queue_cleanup.pbi + $PROJ_DIR$\Debug\Obj\txe_queue_receive.pbi + $PROJ_DIR$\Debug\Obj\txe_mutex_put.pbi + $PROJ_DIR$\Tx_efi.c + $PROJ_DIR$\Debug\Obj\tx_semaphore_put_notify.o + $PROJ_DIR$\Debug\Obj\tx_mutex_cleanup.pbi + $PROJ_DIR$\Debug\Obj\tx_byte_pool_prioritize.o + $PROJ_DIR$\Debug\Obj\txe_thread_priority_change.o + $PROJ_DIR$\Tx_tte.c + $PROJ_DIR$\Debug\Obj\txe_mutex_create.pbi + $PROJ_DIR$\Debug\Obj\tx_timer_interrupt.o + $PROJ_DIR$\Debug\Obj\tx_timer_info_get.pbi + $PROJ_DIR$\Debug\Obj\tx_mutex_performance_info_get.o + $PROJ_DIR$\Txe_sc.c + $PROJ_DIR$\Debug\Obj\tx_block_pool_performance_system_info_get.pbi + $PROJ_DIR$\Tx_qcle.c + $PROJ_DIR$\Debug\Obj\txe_thread_terminate.o + $PROJ_DIR$\Debug\Obj\txe_thread_delete.o + $PROJ_DIR$\Debug\Obj\tx_thread_sleep.o + $PROJ_DIR$\Debug\Obj\tx_queue_receive.pbi + $PROJ_DIR$\Debug\Obj\txe_thread_entry_exit_notify.pbi + $PROJ_DIR$\Debug\Obj\txe_byte_pool_info_get.o + $PROJ_DIR$\Debug\Obj\tx_byte_pool_cleanup.pbi + $PROJ_DIR$\Txe_mp.c + $PROJ_DIR$\Debug\Obj\txe_thread_priority_change.pbi + $PROJ_DIR$\Debug\Obj\txe_byte_release.pbi + $PROJ_DIR$\Debug\Obj\tx_byte_pool_initialize.pbi + $PROJ_DIR$\Tx_twa.c + $PROJ_DIR$\Tx_qd.c + $PROJ_DIR$\Txe_md.c + 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$PROJ_DIR$\tx_byte_allocate.c + $PROJ_DIR$\tx_byte_pool.h + $PROJ_DIR$\tx_block_pool.h + $PROJ_DIR$\tx_byte_pool_create.c + $PROJ_DIR$\tx_block_pool_performance_system_info_get.c + $PROJ_DIR$\tx_mutex_create.c + $PROJ_DIR$\tx_mutex_info_get.c + $PROJ_DIR$\tx_event_flags_set_notify.c + $PROJ_DIR$\tx_event_flags_set.c + $PROJ_DIR$\tx_event_flags_initialize.c + $PROJ_DIR$\tx_initialize_kernel_setup.c + $PROJ_DIR$\tx_mutex_initialize.c + $PROJ_DIR$\tx_byte_pool_search.c + $PROJ_DIR$\tx_event_flags_cleanup.c + $PROJ_DIR$\tx_byte_pool_performance_system_info_get.c + $PROJ_DIR$\tx_event_flags.h + $PROJ_DIR$\tx_iar.c + $PROJ_DIR$\tx_initialize.h + $PROJ_DIR$\tx_initialize_high_level.c + $PROJ_DIR$\tx_event_flags_info_get.c + $PROJ_DIR$\tx_mutex_delete.c + $PROJ_DIR$\tx_mutex_performance_info_get.c + $PROJ_DIR$\tx_event_flags_get.c + $PROJ_DIR$\tx_byte_pool_performance_info_get.c + $PROJ_DIR$\tx_mutex_performance_system_info_get.c + $PROJ_DIR$\tx_mutex_prioritize.c + $PROJ_DIR$\tx_event_flags_create.c + $PROJ_DIR$\tx_byte_release.c + $PROJ_DIR$\tx_event_flags_performance_system_info_get.c + $PROJ_DIR$\tx_mutex.h + $PROJ_DIR$\tx_byte_pool_prioritize.c + $PROJ_DIR$\tx_mutex_get.c + $PROJ_DIR$\tx_event_flags_performance_info_get.c + $PROJ_DIR$\tx_event_flags_delete.c + $PROJ_DIR$\tx_initialize_kernel_enter.c + $PROJ_DIR$\tx_mutex_cleanup.c + $PROJ_DIR$\tx_thread_shell_entry.c + $PROJ_DIR$\tx_thread_stack_analyze.c + $PROJ_DIR$\tx_thread_sleep.c + $PROJ_DIR$\tx_thread_performance_system_info_get.c + $PROJ_DIR$\tx_thread_stack_build.s + $PROJ_DIR$\tx_thread_preemption_change.c + $PROJ_DIR$\tx_thread_priority_change.c + $PROJ_DIR$\tx_thread_context_save.s + $PROJ_DIR$\tx_thread_fiq_context_save.s + $PROJ_DIR$\tx_thread_initialize.c + $PROJ_DIR$\tx_thread_delete.c + $PROJ_DIR$\tx_thread_stack_error_handler.c + $PROJ_DIR$\tx_thread_stack_error_notify.c + $PROJ_DIR$\tx_thread_suspend.c + $PROJ_DIR$\tx_thread_entry_exit_notify.c + $PROJ_DIR$\tx_thread_fiq_context_restore.s + $PROJ_DIR$\tx_thread_create.c + $PROJ_DIR$\tx_thread_irq_nesting_start.s + $PROJ_DIR$\tx_thread_info_get.c + $PROJ_DIR$\tx_thread_performance_info_get.c + $PROJ_DIR$\tx_thread_reset.c + $PROJ_DIR$\tx_thread_fiq_nesting_start.s + $PROJ_DIR$\tx_thread_context_restore.s + $PROJ_DIR$\tx_thread_identify.c + $PROJ_DIR$\tx_thread_interrupt_control.s + $PROJ_DIR$\tx_thread_interrupt_disable.s + $PROJ_DIR$\tx_thread_interrupt_restore.s + $PROJ_DIR$\tx_thread_relinquish.c + $PROJ_DIR$\tx_thread_resume.c + $PROJ_DIR$\tx_thread_fiq_nesting_end.s + $PROJ_DIR$\tx_thread_irq_nesting_end.s + $PROJ_DIR$\tx_thread_schedule.s + $PROJ_DIR$\tx_semaphore_info_get.c + $PROJ_DIR$\tx_queue_create.c + $PROJ_DIR$\tx_semaphore_performance_system_info_get.c + $PROJ_DIR$\tx_semaphore_put.c + $PROJ_DIR$\tx_semaphore_prioritize.c + $PROJ_DIR$\tx_semaphore_put_notify.c + $PROJ_DIR$\tx_port.h + $PROJ_DIR$\tx_thread.h + $PROJ_DIR$\tx_queue_prioritize.c + $PROJ_DIR$\tx_queue_send_notify.c + $PROJ_DIR$\tx_queue_initialize.c + $PROJ_DIR$\tx_semaphore_initialize.c + $PROJ_DIR$\tx_mutex_put.c + $PROJ_DIR$\tx_queue.h + $PROJ_DIR$\tx_queue_flush.c + $PROJ_DIR$\tx_queue_receive.c + $PROJ_DIR$\tx_semaphore_get.c + $PROJ_DIR$\tx_queue_front_send.c + $PROJ_DIR$\tx_mutex_priority_change.c + $PROJ_DIR$\tx_queue_performance_info_get.c + $PROJ_DIR$\tx_queue_delete.c + $PROJ_DIR$\tx_queue_info_get.c + $PROJ_DIR$\tx_queue_send.c + $PROJ_DIR$\tx_queue_cleanup.c + $PROJ_DIR$\tx_semaphore_cleanup.c + $PROJ_DIR$\tx_semaphore.h + $PROJ_DIR$\tx_semaphore_delete.c + $PROJ_DIR$\tx_semaphore_performance_info_get.c + $PROJ_DIR$\tx_queue_performance_system_info_get.c + $PROJ_DIR$\tx_semaphore_ceiling_put.c + $PROJ_DIR$\tx_semaphore_create.c + $PROJ_DIR$\txe_event_flags_info_get.c + $PROJ_DIR$\txe_mutex_get.c + $PROJ_DIR$\txe_mutex_info_get.c + $PROJ_DIR$\txe_byte_pool_delete.c + $PROJ_DIR$\tx_trace_object_register.c + $PROJ_DIR$\tx_trace_user_event_insert.c + $PROJ_DIR$\tx_trace_interrupt_control.c + $PROJ_DIR$\tx_trace_event_unfilter.c + $PROJ_DIR$\txe_event_flags_get.c + $PROJ_DIR$\tx_trace_event_filter.c + $PROJ_DIR$\txe_byte_release.c + $PROJ_DIR$\txe_event_flags_set.c + $PROJ_DIR$\txe_byte_allocate.c + $PROJ_DIR$\tx_trace_isr_exit_insert.c + $PROJ_DIR$\txe_block_pool_create.c + $PROJ_DIR$\txe_block_pool_info_get.c + $PROJ_DIR$\txe_block_pool_delete.c + $PROJ_DIR$\txe_event_flags_set_notify.c + $PROJ_DIR$\txe_mutex_create.c + $PROJ_DIR$\txe_mutex_delete.c + $PROJ_DIR$\txe_block_release.c + $PROJ_DIR$\txe_block_pool_prioritize.c + $PROJ_DIR$\txe_byte_pool_prioritize.c + $PROJ_DIR$\txe_byte_pool_info_get.c + $PROJ_DIR$\tx_trace_isr_enter_insert.c + $PROJ_DIR$\tx_trace_object_unregister.c + $PROJ_DIR$\txe_event_flags_create.c + $PROJ_DIR$\tx_trace_initialize.c + $PROJ_DIR$\tx_user.h + $PROJ_DIR$\txe_block_allocate.c + $PROJ_DIR$\txe_byte_pool_create.c + $PROJ_DIR$\txe_event_flags_delete.c + $PROJ_DIR$\tx_thread_system_suspend.c + $PROJ_DIR$\tx_thread_system_preempt_check.c + $PROJ_DIR$\tx_thread_timeout.c + $PROJ_DIR$\tx_thread_vectored_context_save.s + $PROJ_DIR$\tx_thread_wait_abort.c + $PROJ_DIR$\tx_time_get.c + $PROJ_DIR$\tx_time_set.c + $PROJ_DIR$\tx_timer.h + $PROJ_DIR$\tx_timer_change.c + $PROJ_DIR$\tx_timer_initialize.c + $PROJ_DIR$\tx_timer_interrupt.s + $PROJ_DIR$\tx_thread_time_slice.c + $PROJ_DIR$\tx_timer_performance_info_get.c + $PROJ_DIR$\tx_timer_info_get.c + $PROJ_DIR$\tx_thread_system_resume.c + $PROJ_DIR$\tx_timer_performance_system_info_get.c + $PROJ_DIR$\tx_timer_system_activate.c + $PROJ_DIR$\tx_timer_thread_entry.c + $PROJ_DIR$\tx_thread_system_return.s + $PROJ_DIR$\tx_timer_system_deactivate.c + $PROJ_DIR$\tx_thread_terminate.c + $PROJ_DIR$\tx_timer_delete.c + $PROJ_DIR$\tx_timer_create.c + $PROJ_DIR$\tx_timer_deactivate.c + $PROJ_DIR$\tx_timer_expiration_process.c + $PROJ_DIR$\tx_trace.h + $PROJ_DIR$\tx_trace_buffer_full_notify.c + $PROJ_DIR$\tx_trace_disable.c + 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+;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; Disable irq,fiq SVC mode +IRQ_MODE DEFINE 0xD2 ; Disable irq,fiq IRQ mode +FIQ_MODE DEFINE 0xD1 ; Disable irq,fiq FIQ mode +SYS_MODE DEFINE 0xDF ; Disable irq,fiq SYS mode +; +; + + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_thread_context_save +; EXTERN _tx_thread_vectored_context_save + EXTERN _tx_thread_context_restore +#ifdef TX_ENABLE_FIQ_SUPPORT + EXTERN _tx_thread_fiq_context_save + EXTERN _tx_thread_fiq_context_restore +#endif +#ifdef TX_ENABLE_IRQ_NESTING + EXTERN _tx_thread_irq_nesting_start + EXTERN _tx_thread_irq_nesting_end +#endif +#ifdef TX_ENABLE_FIQ_NESTING + EXTERN _tx_thread_fiq_nesting_start + EXTERN _tx_thread_fiq_nesting_end +#endif + EXTERN _tx_timer_interrupt + EXTERN ?cstartup + EXTERN _tx_build_options + EXTERN _tx_version_id +; +; +; +;/* Define the FREE_MEM segment that will specify where free memory is +; defined. This must also be located in at the end of other RAM segments +; in the linker control file. The value of this segment is what is passed +; to tx_application_define. */ +; + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + CODE32 + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level +; +; /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode. */ +; +; /* Remember the stack pointer, link register, and switch to SVC mode. */ +; + MOV r0, sp ; Remember the SP + MOV r1, lr ; Remember the LR + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r3 ; Switch to SVC mode + MOV sp, r0 ; Inherit the stack pointer setup by cstartup + MOV lr, r1 ; Inherit the link register +; +; /* Pickup the start of free memory. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) FREE_MEM; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Done, return to caller. */ +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +;/* Define shells for each of the interrupt vectors. */ +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt ; Software interrupt handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_prefetch_handler +__tx_prefetch_handler + B __tx_prefetch_handler ; Prefetch exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_abort_handler +__tx_abort_handler + B __tx_abort_handler ; Abort exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +; +; /* For debug purpose, execute the timer interrupt processing here. In +; a real system, some kind of status indication would have to be checked +; before the timer interrupt handler could be called. */ +; + BL _tx_timer_interrupt ; Timer interrupt handler +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; +; RSEG .text:CODE:NOROOT(2) +; PUBLIC __tx_example_vectored_irq_handler +;__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +;#endif +; +; /* Application IRQ handler is called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +;#endif +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; +#else + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler +#endif +; +; +BUILD_OPTIONS + DC32 _tx_build_options ; Reference to ensure it comes in +VERSION_ID + DC32 _tx_version_id ; Reference to ensure it comes in + END + diff --git a/ports/cortex_a8/iar/inc/tx_port.h b/ports/cortex_a8/iar/inc/tx_port.h new file mode 100644 index 00000000..3ff8ef9b --- /dev/null +++ b/ports/cortex_a8/iar/inc/tx_port.h @@ -0,0 +1,397 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A8/IAR */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#if __CORE__ > __ARM4TM__ + +#if __CPU_MODE__ == 2 + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (UINT) __CLZ(m); \ + b = 31 - b; +#endif +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +/* First, check and see what mode the file is being compiled in. The IAR compiler + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros + are available. Otherwise, if Thumb mode is present, we must use function calls. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else +#if __CPU_MODE__ == 2 + +#if (__VER__ < 8002000) +__intrinsic unsigned long __get_CPSR(); +__intrinsic void __set_CPSR( unsigned long ); +#endif + + +#if (__VER__ < 8002000) +#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#else +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#endif + + +#define TX_DISABLE interrupt_save = __get_CPSR(); \ + __set_CPSR(interrupt_save | TX_INT_DISABLE); +#define TX_RESTORE __set_CPSR(interrupt_save); + +#else + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#endif +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A8. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/IAR Version 6.0 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + diff --git a/ports/cortex_a8/iar/readme_threadx.txt b/ports/cortex_a8/iar/readme_threadx.txt new file mode 100644 index 00000000..e46fdee8 --- /dev/null +++ b/ports/cortex_a8/iar/readme_threadx.txt @@ -0,0 +1,544 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A8 + + Thumb & 32-bit Mode + + Using the IAR Tools + +1. Building the ThreadX run-time Library + +Building the ThreadX library is easy. First, open the Azure RTOS workspace +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by +the application. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the IAR +Windows-based Cortex-A8 simulator. + +Building the demonstration is easy; simply make the sample_threadx.ewp project +the "active project" in the IAR Embedded Workbench and select the +"Make" button. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a +binary file that can be downloaded and executed on IAR's Cortex-A8 simulator. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A8 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. +By default, the vector area is defined at the top of cstartup.s, which is +a slightly modified from the base IAR file. + +The _tx_initialize_low_level function inside of tx_initialize_low_level.s +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all +other RAM sections in memory. + + +4. Register Usage and Stack Frames + +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +5. Conditional Compilation Switches + +The following are conditional compilation options for building the ThreadX library +and application: + + + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + FIQ interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + + TX_ENABLE_IRQ_NESTING This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. + + TX_ENABLE_FIQ_NESTING This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. In addition, + IRQ nesting should also be enabled. + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + TX_THUMB Defined, this option enables the BX LR calling return sequence + in assembly files, to ensure correct operation on systems that + use both ARM and Thumb mode. By default, this option is + not defined + + + + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the ThreadX library +project to enable various compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A8 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A8 vectors start at address zero. The demonstration system startup +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + PUBLIC __tx_irq_handler + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR dispatch call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_example_vectored_irq_handler +__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers + BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR dispatch call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +; + BL _tx_thread_irq_nesting_start + +; /* Application ISR dispatch call goes here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +; + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, Cortex-A8 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ dispatch call goes here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in +preparation for the FIQ context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ dispatch call goes here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +in the IRQ processing. + + +9. Thumb/Cortex-A8 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A8 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire +ThreadX assembly source should be built with TX_THUMB defined. + + +10. IAR Thread-safe Library Support + +Thread-safe support for the IAR tools is easily enabled by building the ThreadX library +and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file +should have the following line added (if not already in place): + +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application + +The project options "General Options -> Library Configuration" should also have the +"Enable thread support in library" box selected. + + +11. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + + +12. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX version 6.0.1 for Cortex-A8 using IAR's ARM tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a8/iar/src/tx_iar.c b/ports/cortex_a8/iar/src/tx_iar.c new file mode 100644 index 00000000..11fcefb3 --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports/cortex_a8/iar/src/tx_thread_context_restore.s b/ports/cortex_a8/iar/src/tx_thread_context_restore.s new file mode 100644 index 00000000..4a66c503 --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_context_restore.s @@ -0,0 +1,259 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +SVC_MODE DEFINE 0xD3 ; SVC mode +IRQ_MODE DEFINE 0xD2 ; IRQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +THUMB_MASK DEFINE 0x20 ; Thumb bit mask +SVC_MODE_BITS DEFINE 0x13 ; SVC mode value + +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_restore + CODE32 +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + MRS r3, CPSR ; Pickup current CPSR + ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value + MSR CPSR_cxsf, r0 ; Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block + BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS ; Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 ; Lockout interrupts +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r3, r3, #MODE_MASK ; Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +;} +; +; + END + diff --git a/ports/cortex_a8/iar/src/tx_thread_context_save.s b/ports/cortex_a8/iar/src/tx_thread_context_save.s new file mode 100644 index 00000000..0d4256ea --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_context_save.s @@ -0,0 +1,210 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif + + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_irq_processing_return + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_save + CODE32 +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r0 ; Disable interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + +; +; + END + diff --git a/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..3036be83 --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,270 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; SVC mode +FIQ_MODE DEFINE 0xD1 ; FIQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +THUMB_MASK DEFINE 0x20 ; Thumb bit mask +IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits +SVC_MODE_BITS DEFINE 0x13 ; SVC mode value + +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_restore + CODE32 +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + MRS r3, CPSR ; Pickup current CPSR + ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value + MSR CPSR_cxsf, r0 ; Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_cxsf, r2 ; Re-enter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block */ + BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS ; Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 ; Lockout interrupts +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MRS r3, CPSR ; Pickup current CPSR + BIC r3, r3, #MODE_MASK ; Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +; +;} +; +; + END + diff --git a/ports/cortex_a8/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a8/iar/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..fb54ea4c --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_fiq_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_fiq_processing_return + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_save + CODE32 +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} +; +; + END + diff --git a/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..cc8bb560 --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,109 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_end + CODE32 +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_cxsf, r0 ; Disable interrupts + LDR lr, [sp] ; Pickup saved lr + ADD sp, sp, #4 ; Adjust stack pointer + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_cxsf, r0 ; Re-enter IRQ mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..7d1ef512 --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit +MODE_MASK DEFINE 0x1F ; Mode mask +SYS_MODE_BITS DEFINE 0x1F ; System mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_start + CODE32 +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + STR lr, [sp, #-4]! ; Push the system mode lr on the system mode stack + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a8/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a8/iar/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..4a409e4b --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_interrupt_control.s @@ -0,0 +1,103 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +INT_MASK DEFINE 0xC0 ; Interrupt bit mask +#else +INT_MASK DEFINE 0x80 ; Interrupt bit mask +#endif +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_control + CODE32 +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} +; +; + END diff --git a/ports/cortex_a8/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a8/iar/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..552ebed1 --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_interrupt_disable.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_disable + CODE32 +_tx_thread_interrupt_disable??rA +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + ORR r1, r0, #DISABLE_INTS ; Mask interrupts + MSR CPSR_cxsf, r1 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +; + END diff --git a/ports/cortex_a8/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a8/iar/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..7d0750c1 --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;void _tx_thread_interrupt_restore(UINT old_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_restore + CODE32 +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r0 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; + END diff --git a/ports/cortex_a8/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a8/iar/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..6da2fdcb --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_end + CODE32 +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_cxsf, r0 ; Disable interrupts + LDR lr, [sp] ; Pickup saved lr + ADD sp, sp, #4 ; Adjust stack pointer + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_cxsf, r0 ; Re-enter IRQ mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a8/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a8/iar/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..8d9efeff --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +IRQ_DISABLE DEFINE 0x80 ; IRQ disable bit +MODE_MASK DEFINE 0x1F ; Mode mask +SYS_MODE_BITS DEFINE 0x1F ; System mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_start + CODE32 +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + STR lr, [sp, #-4]! ; Push the system mode lr on the system mode stack + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a8/iar/src/tx_thread_schedule.s b/ports/cortex_a8/iar/src/tx_thread_schedule.s new file mode 100644 index 00000000..865fb9dd --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_schedule.s @@ -0,0 +1,239 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask +#else +ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask +#endif +; +; + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_execution_thread_enter +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_schedule + CODE32 +_tx_thread_schedule??rA +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + MRS r2, CPSR ; Pickup CPSR + BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s) + MSR CPSR_cxsf, r0 ; Enable interrupts +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + MSR CPSR_cxsf, r2 ; Disable interrupts +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ; variable + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 +#endif +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 ; Setup SPSR for return +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + +_tx_solicited_return: +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 ; Recover CPSR + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} +; + +#ifdef __ARMVFP__ + PUBLIC tx_thread_vfp_enable + CODE32 +tx_thread_vfp_enable??rA +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if ; Enable IRQ and FIQ interrupts +#else + CPSIE i ; Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + PUBLIC tx_thread_vfp_disable + CODE32 +tx_thread_vfp_disable??rA +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if ; Enable IRQ and FIQ interrupts +#else + CPSIE i ; Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller +#endif + + END + diff --git a/ports/cortex_a8/iar/src/tx_thread_stack_build.s b/ports/cortex_a8/iar/src/tx_thread_stack_build.s new file mode 100644 index 00000000..f5f4da77 --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_stack_build.s @@ -0,0 +1,158 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE DEFINE 0x13 ; SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK DEFINE 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled +#else +CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled +#endif +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_stack_build + + CODE32 +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A8 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure long-word alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + MRS r1, CPSR ; Pickup CPSR + BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} + END + diff --git a/ports/cortex_a8/iar/src/tx_thread_system_return.s b/ports/cortex_a8/iar/src/tx_thread_system_return.s new file mode 100644 index 00000000..814bc727 --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_system_return.s @@ -0,0 +1,162 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif +; +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_execution_thread_exit +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_system_return + CODE32 +_tx_thread_system_return??rA +_tx_thread_system_return +; +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context + LDR r5, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r6, [r5, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r0, [r6, #144] ; Pickup the VFP enabled flag + CMP r0, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 ; Build a solicited stack type + MRS r1, CPSR ; Pickup the CPSR + STMDB sp!, {r0-r1} ; Save type and CPSR +; +; /* Lockout interrupts. */ +; + ORR r2, r1, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r2 ; Disable interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function +#endif + + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r6, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r6, #24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r5, #0] ; Clear current thread pointer + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports/cortex_a8/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a8/iar/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..efd958c2 --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_thread_vectored_context_save.s @@ -0,0 +1,195 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_vectored_context_save + CODE32 +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, the minimal context is already saved, and the +; lr register contains the return ISR address. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; +#ifdef TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r0 ; Disable interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + MOV pc, lr ; Return to caller +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + MOV pc, lr ; Return to caller +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #32 ; Recover saved registers + MOV pc, lr ; Return to caller +; +; } +;} + END + diff --git a/ports/cortex_a8/iar/src/tx_timer_interrupt.s b/ports/cortex_a8/iar/src/tx_timer_interrupt.s new file mode 100644 index 00000000..d7a98738 --- /dev/null +++ b/ports/cortex_a8/iar/src/tx_timer_interrupt.s @@ -0,0 +1,260 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A8/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_timer_interrupt + CODE32 +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} + END + diff --git a/ports/cortex_a9/ac5/example_build/build_threadx.bat b/ports/cortex_a9/ac5/example_build/build_threadx.bat new file mode 100644 index 00000000..328e013b --- /dev/null +++ b/ports/cortex_a9/ac5/example_build/build_threadx.bat @@ -0,0 +1,238 @@ +del tx.a +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork tx_initialize_low_level.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_stack_build.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_schedule.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_system_return.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_context_save.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_context_restore.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_interrupt_control.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_timer_interrupt.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_fiq_context_restore.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_fiq_context_save.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_fiq_nesting_end.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_fiq_nesting_start.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_interrupt_disable.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_interrupt_restore.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_irq_nesting_end.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_irq_nesting_start.s +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork ../src/tx_thread_vectored_context_save.s +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +armcc -g --cpu=cortex-a9.no_neon --fpu=softvfp -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +armar -r tx.a tx_initialize_low_level.o tx_thread_fiq_context_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_end.o tx_thread_fiq_nesting_start.o tx_thread_interrupt_disable.o +armar -r tx.a tx_thread_interrupt_restore.o tx_thread_irq_nesting_end.o tx_thread_irq_nesting_start.o +armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_a9/ac5/example_build/build_threadx_sample.bat b/ports/cortex_a9/ac5/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..0350727e --- /dev/null +++ b/ports/cortex_a9/ac5/example_build/build_threadx_sample.bat @@ -0,0 +1,4 @@ +armasm -g --cpu=cortex-a9.no_neon --fpu=softvfp --apcs=interwork tx_initialize_low_level.s +armcc -c -g --cpu=cortex-a9.no_neon --fpu=softvfp -I../../../../common/inc -I../inc sample_threadx.c +armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --first tx_initialize_low_level.o(Init) --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a + diff --git a/ports/cortex_a9/ac5/example_build/sample_threadx.c b/ports/cortex_a9/ac5/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_a9/ac5/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a9/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_a9/ac5/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..4bec5bf9 --- /dev/null +++ b/ports/cortex_a9/ac5/example_build/tx_initialize_low_level.s @@ -0,0 +1,414 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +FIQ_MODE EQU 0xD1 ; FIQ mode +IRQ_MODE EQU 0xD2 ; IRQ mode +SVC_MODE EQU 0xD3 ; SVC mode +SYS_MODE EQU 0xDF ; SYS mode + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +FIQ_MODE EQU 0x91 ; FIQ mode +IRQ_MODE EQU 0x92 ; IRQ mode +SVC_MODE EQU 0x93 ; SVC mode +SYS_MODE EQU 0x9F ; SYS mode + ENDIF +HEAP_SIZE EQU 4096 ; Heap size +FIQ_STACK_SIZE EQU 512 ; FIQ stack size +SYS_STACK_SIZE EQU 1024 ; SYS stack size (used for nested interrupts) +IRQ_STACK_SIZE EQU 1024 ; IRQ stack size + +VFPEnable EQU 0x40000000 ; VFP enable value + +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IF :DEF:TX_ENABLE_FIQ_SUPPORT + IMPORT _tx_thread_fiq_context_save + IMPORT _tx_thread_fiq_context_restore + ENDIF + IF :DEF:TX_ENABLE_IRQ_NESTING + IMPORT _tx_thread_irq_nesting_start + IMPORT _tx_thread_irq_nesting_end + ENDIF + IF :DEF:TX_ENABLE_FIQ_NESTING + IMPORT _tx_thread_fiq_nesting_start + IMPORT _tx_thread_fiq_nesting_end + ENDIF + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT _tx_version_id + IMPORT _tx_build_options + IMPORT |Image$$ZI$$Limit| +; +; + AREA Init, CODE, READONLY +; +;/* Define the default Cortex-A9 vector area. This should be located or copied to 0. */ +; + EXPORT __vectors +__vectors + LDR pc,=Reset_Vector ; Reset goes to startup function + LDR pc,=__tx_undefined ; Undefined handler + LDR pc,=__tx_swi_interrupt ; Software interrupt handler + LDR pc,=__tx_prefetch_handler ; Prefetch exception handler + LDR pc,=__tx_abort_handler ; Abort exception handler + LDR pc,=__tx_reserved_handler ; Reserved exception handler + LDR pc,=__tx_irq_handler ; IRQ interrupt handler + LDR pc,=__tx_fiq_handler ; FIQ interrupt handler +; +; + EXPORT Reset_Vector +Reset_Vector + + IF {TARGET_FPU_VFP} = {TRUE} + MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register + ORR r1, r1, #(0xf << 20) ; Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 ; Flush prefetch buffer because of FMXR below and + ; CP 10 & 11 were only just enabled + MOV r0, #VFPEnable ; Enable VFP itself + FMXR FPEXC, r0 ; FPEXC = r0 + ENDIF + + B __main +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; +; /****** NOTE ****** We must be in SVC MODE at this point. Some monitors +; enter this routine in USER mode and require a software interrupt to +; change into SVC mode. */ +; + LDR r1, =|Image$$ZI$$Limit| ; Get end of non-initialized RAM area + LDR r2, =HEAP_SIZE ; Pickup the heap size + ADD r1, r2, r1 ; Setup heap limit + ADD r1, r1, #4 ; Setup stack limit +; + IF :DEF:TX_ENABLE_IRQ_NESTING +; /* Setup the system mode stack for nested interrupt support */ + LDR r2, =SYS_STACK_SIZE ; Pickup stack size + MOV r3, #SYS_MODE ; Build SYS mode CPSR + MSR CPSR_c, r3 ; Enter SYS mode + ADD r1, r1, r2 ; Calculate start of SYS stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup SYS stack pointer + ENDIF +; + LDR r2, =FIQ_STACK_SIZE ; Pickup stack size + MOV r0, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_c, r0 ; Enter FIQ mode + ADD r1, r1, r2 ; Calculate start of FIQ stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup FIQ stack pointer + MOV sl, #0 ; Clear sl + MOV fp, #0 ; Clear fp + LDR r2, =IRQ_STACK_SIZE ; Pickup IRQ (system stack size) + MOV r0, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Enter IRQ mode + ADD r1, r1, r2 ; Calculate start of IRQ stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup IRQ stack pointer + MOV r0, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r0 ; Enter SVC mode + LDR r3, =_tx_thread_system_stack_ptr ; Pickup stack pointer + STR r1, [r3, #0] ; Save the system stack +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; + LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr + LDR r0, [r1, #0] ; Pickup system stack + ADD r0, r0, #4 ; Increment to next free word +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) |Image$$ZI$$Limit| + HEAP + [SYS_STACK] + FIQ_STACK + IRQ_STACK; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Done, return to caller. */ +; + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; +; +;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This +; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; (optionally SYS) stack areas. */ +; + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR r0, =|Image$$ZI$$Limit| ; Get end of non-initialized RAM area + LDR r2, =HEAP_SIZE ; Pickup the heap size + ADD r2, r2, r0 ; Setup heap limit + ADD r3, r2, #4 ; Setup stack limit + MOV r1, r3 ; Setup start of stack + IF :DEF:TX_ENABLE_IRQ_NESTING + LDR r12, =SYS_STACK_SIZE ; Pickup IRQ system stack + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + ENDIF + LDR r12, =FIQ_STACK_SIZE ; Pickup FIQ stack size + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + LDR r12, =IRQ_STACK_SIZE ; Pickup IRQ system stack + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; +;/* Define shells for each of the interrupt vectors. */ +; + EXPORT __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + EXPORT __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt ; Software interrupt handler +; + EXPORT __tx_prefetch_handler +__tx_prefetch_handler + B __tx_prefetch_handler ; Prefetch exception handler +; + EXPORT __tx_abort_handler +__tx_abort_handler + B __tx_abort_handler ; Abort exception handler +; + EXPORT __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; +; + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; + BL _tx_timer_interrupt ; Timer interrupt handler +_tx_not_timer_interrupt +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ + IF :DEF:TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start + ENDIF +; +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ + IF :DEF:TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end + ENDIF +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; + EXPORT __tx_example_vectored_irq_handler +__tx_example_vectored_irq_handler +; +; +; /* Save initial context and call context save to prepare for +; vectored ISR execution. */ +; +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers +; BL _tx_thread_vectored_context_save ; Vectored context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +; IF :DEF:TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +; ENDIF +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +; IF :DEF:TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +; ENDIF +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ + IF :DEF:TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start + ENDIF +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ + IF :DEF:TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end + ENDIF +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; + ELSE + EXPORT __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler + ENDIF +; +; /* Reference build options and version ID to ensure they come in. */ +; + LDR r2, =_tx_build_options ; Pickup build options variable address + LDR r0, [r2, #0] ; Pickup build options content + LDR r2, =_tx_version_id ; Pickup version ID variable address + LDR r0, [r2, #0] ; Pickup version ID content +; +; + END + diff --git a/ports/cortex_a9/ac5/inc/tx_port.h b/ports/cortex_a9/ac5/inc/tx_port.h new file mode 100644 index 00000000..bc92b621 --- /dev/null +++ b/ports/cortex_a9/ac5/inc/tx_port.h @@ -0,0 +1,334 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A9/AC5 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef __thumb + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (ULONG) __clz((unsigned int) m); \ + b = 31 - b; +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifndef __thumb + +#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; + +#ifdef TX_ENABLE_FIQ_SUPPORT + +/* IRQ and FIQ support. */ + +#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); \ + __disable_fiq(); + +#define TX_RESTORE if (!interrupt_save_disabled) \ + { \ + __enable_irq(); \ + __enable_fiq(); \ + } + +#else + +#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); + +#define TX_RESTORE if (!interrupt_save_disabled) \ + { \ + __enable_irq(); \ + } +#endif + +#else + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); +#endif + + +/* Define VFP extension for the Cortex-A5. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/AC5 Version 6.0 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a9/ac5/readme_threadx.txt b/ports/cortex_a9/ac5/readme_threadx.txt new file mode 100644 index 00000000..b05b8f73 --- /dev/null +++ b/ports/cortex_a9/ac5/readme_threadx.txt @@ -0,0 +1,545 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A9 + + Thumb & 32-bit Mode + + Using ARM Compiler 5 (AC5) + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +AC5 development environment. At this point you may run the build_threadx.bat +batch file. This will build the ThreadX run-time environment in the +"example_build" directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + +1.1 Building with Project Files + +The ThreadX library can also be built via project files. Simply open +the tx.mcp file with project builder and select make. This will place +the tx.a library file into the Debug sub-directory. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the ARM +Windows-based simulator. + +Building the demonstration is easy; simply execute the build_threadx_demo.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf +is a binary file that can be downloaded and executed on the ARM simulator. + +2.0.1 Building with Project Files + +The ThreadX demonstration can also be built via project files. Simply open +the sample_threadx.mcp file with project builder and select make. This will place +the sample_threadx.axf output image into the Debug sub-directory. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A9 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning +of the Init area should be copied to address 0. + +This is also where initialization of a periodic timer interrupt source +should take place. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Assembler / Compiler Switches + +The following are compiler switches used in building the demonstration +system: + +Compiler Switch Meaning + + -g Specifies debug information + -c Specifies object code generation + --cpu Cortex-A9 Specifies Cortex-A9 instruction set + --apcs /interwork Specifies Thumb/32-bit compatibility + +Linker Switch Meaning + + -d Specifies to retain debug information in output file + -o demo.axf Specifies demo output file name + --elf Specifies elf output file format + --ro Specifies that Read-Only memory starts at address 0 + --first tx_initialize_low_level.o(Init) + Specifies that the first area loaded is Init + --remove Remove unused areas + --list Specifies map file name + --symbols Specifies symbols for map file + --map Creates a map file + +Application Defines + + --PD "TX_ENABLE_FIQ_SUPPORT SETL {TRUE}" This assembler define enables FIQ + interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}" This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. + --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}" This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. In addition, + IRQ nesting should also be enabled. + -DTX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ + interrupt handling in the ThreadX + generic C source. This define + should also be used in conjunction + with the corresponding assembler + define. + -DTX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + -DTX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + + +5. Register Usage and Stack Frames + +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A9 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A9 vectors start at address zero. The demonstration system startup +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save ; Jump to the context save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call(s) go here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + EXPORT __tx_irq_example_handler +__tx_irq_example_handler +; +; /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers + BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, +calling the _tx_thread_irq_nesting_end service disables nesting by disabling +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* Enable nested IRQ interrupts. NOTE: Since this service returns +; with IRQ interrupts enabled, all IRQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +; +; /* Application ISR call(s) go here! */ +; +; /* Disable nested IRQ interrupts. The mode is switched back to +; IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ handlers can be called here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ handlers can be called here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.s in the Integrator sub-directories. + + +9. Thumb/Cortex-A9 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built +with the "-apcs /interwork" option. + +10. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +11. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A9 using AC5 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a9/ac5/src/tx_thread_context_restore.s b/ports/cortex_a9/ac5/src/tx_thread_context_restore.s new file mode 100644 index 00000000..5c5259a7 --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_context_restore.s @@ -0,0 +1,256 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +IRQ_MODE EQU 0xD2 ; IRQ mode +SVC_MODE EQU 0xD3 ; SVC mode + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +IRQ_MODE EQU 0x92 ; IRQ mode +SVC_MODE EQU 0x93 ; SVC mode + ENDIF +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save + ENDIF + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MOV r3, #SVC_MODE ; Build SVC mode with interrupts disabled + MSR CPSR_c, r3 ; Change to SVC mode + B _tx_thread_schedule ; Return to scheduler +;} +; + END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_context_save.s b/ports/cortex_a9/ac5/src/tx_thread_context_save.s new file mode 100644 index 00000000..ec7710aa --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_context_save.s @@ -0,0 +1,199 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_irq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable FIQ interrupts + ENDIF + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..a5484af5 --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,258 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE EQU 0xD3 ; SVC mode +FIQ_MODE EQU 0xD1 ; FIQ mode +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + EXPORT _tx_thread_fiq_context_restore +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + CPSID if ; Disable IRQ and FIQ interrupts + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_c, r2 ; Re-enter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save ; No, skip VFP FIQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_fiq_vfp_save + ENDIF + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r3 ; Enter SVC mode + B _tx_thread_schedule ; Return to scheduler +; +;} +; + END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_a9/ac5/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..371ac248 --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_fiq_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_fiq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + EXPORT _tx_thread_fiq_context_save +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} +; + END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..a3b20759 --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,111 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + EXPORT _tx_thread_fiq_nesting_end +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..221258d5 --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +FIQ_DISABLE EQU 0x40 ; FIQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + EXPORT _tx_thread_fiq_nesting_start +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_c, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_a9/ac5/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..4c4a7c38 --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_interrupt_control.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +INT_MASK EQU 0xC0 ; Interrupt bit mask + ELSE +INT_MASK EQU 0x80 ; Interrupt bit mask + ENDIF +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} +; + END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_a9/ac5/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..c15f0bdf --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_interrupt_disable.s @@ -0,0 +1,95 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(void) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ + ELSE + CPSID i ; Disable IRQ + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_a9/ac5/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..955544e7 --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_restore(UINT old_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r0 ; Setup new CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..7b91c316 --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + EXPORT _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} + END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..d1a25514 --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +IRQ_DISABLE EQU 0x80 ; IRQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + EXPORT _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_c, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_schedule.s b/ports/cortex_a9/ac5/src/tx_thread_schedule.s new file mode 100644 index 00000000..10bbe36a --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_schedule.s @@ -0,0 +1,236 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_execute_ptr + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSIE if ; Enable IRQ and FIQ interrupts + ELSE + CPSIE i ; Enable IRQ interrupts + ENDIF +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Enable IRQ and FIQ interrupts + ELSE + CPSID i ; Enable IRQ interrupts + ENDIF +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ; variable + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 + ENDIF +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 ; Setup SPSR for return + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_interrupt_vfp_restore + ENDIF + LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + +_tx_solicited_return + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore + ENDIF + MSR CPSR_cxsf, r5 ; Recover CPSR + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} +; + + IF {TARGET_FPU_VFP} = {TRUE} + EXPORT tx_thread_vfp_enable +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + EXPORT tx_thread_vfp_disable +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + ENDIF + + END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_stack_build.s b/ports/cortex_a9/ac5/src/tx_thread_stack_build.s new file mode 100644 index 00000000..0364ba18 --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_stack_build.s @@ -0,0 +1,165 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE EQU 0x13 ; SVC mode + IF :DEF:TX_ENABLE_FIQ_SUPPORT +CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled + ELSE +CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled + ENDIF + +THUMB_BIT EQU 0x20 ; Thumb-bit + +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A9 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + + MRS r3, CPSR ; Pickup CPSR + BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r3, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT ; Clear Thumb-bit by default + AND r1, r1, #1 ; Determine if the entry function is in Thumb mode + CMP r1, #1 ; Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT ; Yes, set the Thumb-bit + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + +;} + END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_system_return.s b/ports/cortex_a9/ac5/src/tx_thread_system_return.s new file mode 100644 index 00000000..c4ae7a15 --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_system_return.s @@ -0,0 +1,159 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context + LDR r5, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r6, [r5, #0] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r0, [r6, #144] ; Pickup the VFP enabled flag + CMP r0, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save + ENDIF + + MOV r0, #0 ; Build a solicited stack type + MRS r1, CPSR ; Pickup the CPSR + STMDB sp!, {r0-r1} ; Save type and CPSR +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function + ENDIF + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r6, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save the current remaining time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r6, #24] ; Store current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r5, #0] ; Clear current thread pointer + + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports/cortex_a9/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_a9/ac5/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..c74480a5 --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_thread_vectored_context_save.s @@ -0,0 +1,200 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + EXPORT _tx_thread_vectored_context_save +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ENDIF + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + ADD sp, sp, #32 ; Recover saved registers + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +;} +; + END + diff --git a/ports/cortex_a9/ac5/src/tx_timer_interrupt.s b/ports/cortex_a9/ac5/src/tx_timer_interrupt.s new file mode 100644 index 00000000..1fdec243 --- /dev/null +++ b/ports/cortex_a9/ac5/src/tx_timer_interrupt.s @@ -0,0 +1,258 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} + END + diff --git a/ports/cortex_a9/gnu/example_build/build_threadx.bat b/ports/cortex_a9/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..668eb5c7 --- /dev/null +++ b/ports/cortex_a9/gnu/example_build/build_threadx.bat @@ -0,0 +1,238 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_interrupt_disable.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_interrupt_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_fiq_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_fiq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_irq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_irq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_fiq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_fiq_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 ../src/tx_thread_vectored_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_start.o tx_thread_irq_nesting_start.o tx_thread_irq_nesting_end.o +arm-none-eabi-ar -r tx.a tx_thread_fiq_nesting_end.o tx_thread_fiq_context_restore.o tx_thread_vectored_context_save.o tx_initialize_low_level.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_a9/gnu/example_build/build_threadx_sample.bat b/ports/cortex_a9/gnu/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..e6ddefad --- /dev/null +++ b/ports/cortex_a9/gnu/example_build/build_threadx_sample.bat @@ -0,0 +1,6 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 reset.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 crt0.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a9 -I../../../../common/inc -I../inc sample_threadx.c +arm-none-eabi-ld -A cortex-a9 -T sample_threadx.ld reset.o crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libc.a libgcc.a -o sample_threadx.out -M > sample_threadx.map + diff --git a/ports/cortex_a9/gnu/example_build/crt0.S b/ports/cortex_a9/gnu/example_build/crt0.S new file mode 100644 index 00000000..aa0f3239 --- /dev/null +++ b/ports/cortex_a9/gnu/example_build/crt0.S @@ -0,0 +1,90 @@ + +/* .text is used instead of .section .text so it works with arm-aout too. */ + .text + .code 32 + .align 0 + + .global _mainCRTStartup + .global _start + .global start +start: +_start: +_mainCRTStartup: + +/* Start by setting up a stack */ + /* Set up the stack pointer to a fixed value */ + ldr r3, .LC0 + mov sp, r3 + /* Setup a default stack-limit in case the code has been + compiled with "-mapcs-stack-check". Hard-wiring this value + is not ideal, since there is currently no support for + checking that the heap and stack have not collided, or that + this default 64k is enough for the program being executed. + However, it ensures that this simple crt0 world will not + immediately cause an overflow event: */ + sub sl, sp, #64 << 10 /* Still assumes 256bytes below sl */ + mov a2, #0 /* Second arg: fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr a1, .LC1 /* First arg: start of memory block */ + ldr a3, .LC2 + sub a3, a3, a1 /* Third arg: length of block */ + + + + bl memset + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ +#ifdef __USES_INITFINI__ + /* Some arm/elf targets use the .init and .fini sections + to create constructors and destructors, and for these + targets we need to call the _init function and arrange + for _fini to be called at program exit. */ + mov r4, r0 + mov r5, r1 +/* ldr r0, .Lfini */ + bl atexit +/* bl init */ + mov r0, r4 + mov r1, r5 +#endif + bl main + + bl exit /* Should not return. */ + + + /* For Thumb, constants must be after the code since only + positive offsets are supported for PC relative addresses. */ + + .align 0 +.LC0: +.LC1: + .word __bss_start__ +.LC2: + .word __bss_end__ +/* +#ifdef __USES_INITFINI__ +.Lfini: + .word _fini +#endif */ + /* Return ... */ +#ifdef __APCS_26__ + movs pc, lr +#else +#ifdef __THUMB_INTERWORK + bx lr +#else + mov pc, lr +#endif +#endif + + +/* Workspace for Angel calls. */ + .data +/* Data returned by monitor SWI. */ +.global __stack_base__ +HeapBase: .word 0 +HeapLimit: .word 0 +__stack_base__: .word 0 +StackLimit: .word 0 diff --git a/ports/cortex_a9/gnu/example_build/libc.a b/ports/cortex_a9/gnu/example_build/libc.a new file mode 100644 index 0000000000000000000000000000000000000000..5b04fa4ed9b6479f70979f5577dd0705d1f6d1d7 GIT binary patch literal 2447586 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zyyk;0u~c5dm1R37av%P?23us%dHPGDpFT$0GBczAKYnN6rVuiJ<@W-;X3iNSdGtC4 zZc0Al4tY)&I-P!o0#6|ykg|z--55Au=wiVt!DWKHH_4BuyvA0+F2RcgFA>}#_#GlT dhn|!HpOEmEh$!@SiRZoRqCc?z|Ecwv{|7^Je? +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef __thumb__ + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); +#else +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) ); +#endif + +#define TX_RESTORE asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) ); + +#endif + + +/* Define VFP extension for the Cortex-A9. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/GNU Version 6.0 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a9/gnu/readme_threadx.txt b/ports/cortex_a9/gnu/readme_threadx.txt new file mode 100644 index 00000000..684e996f --- /dev/null +++ b/ports/cortex_a9/gnu/readme_threadx.txt @@ -0,0 +1,513 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A9 + + Using the GNU Tools + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. + +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + + +2. Demonstration System + +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file +that can be downloaded and executed. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A9 using GNU tools is at label _start. +This is defined within the modified version of the GNU startup code - crt0.S. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied +to address 0. + +This is also where initialization of a periodic timer interrupt source should take +place. + +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter +to your application definition function, tx_application_define. + + +4. Assembler / Compiler Switches + +The following are compiler switches used in building the demonstration +system: + +Compiler/Assembler Meaning + Switches + + -g Specifies debug information + -c Specifies object code generation + -mcpu=cortex-a9 Specifies target cpu + +Linker Switch Meaning + + -o sample_threadx.out Specifies output file + -M > sample_threadx.map Specifies demo map file + -A cortex-a9 Specifies target architecture + -T sample_threadx.ld Specifies the loader control file + +Application Defines ( -D option) + + TX_ENABLE_FIQ_SUPPORT This assembler define enables FIQ + interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + + TX_ENABLE_IRQ_NESTING This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.S. + + TX_ENABLE_FIQ_NESTING This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.S. In addition, + IRQ nesting should also be enabled. + + TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ + interrupt handling in the ThreadX + generic C source. This define + should also be used in conjunction + with the corresponding assembler + define. + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + +5. Register Usage and Stack Frames + +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) a9 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 a9 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A9 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A9 vectors start at address zero. The demonstration system startup +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +nested IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.S: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save @ Jump to the context save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.S: + + .global __tx_irq_example_handler +__tx_irq_example_handler: +@ +@ /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} @ Save some scratch registers + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers + BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call goes here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* Enable nested IRQ interrupts. NOTE: Since this service returns +@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Disable nested IRQ interrupts. The mode is switched back to +@ IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.S. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.S: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Enable nested FIQ interrupts. NOTE: Since this service returns +@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Disable nested FIQ interrupts. The mode is switched back to +@ FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of +ThreadX will still run. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.S for the demonstration system. + + +9. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A9 using GNU tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a9/gnu/src/tx_thread_context_restore.S b/ports/cortex_a9/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..3e85f010 --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,257 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE = 0xD3 @ Disable IRQ/FIQ, SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE = 0x93 @ Disable IRQ, SVC mode +IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode +#endif +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_restore @ Yes, idle system was interrupted +@ + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_preempt_restore @ No, preemption needs to happen +@ +@ +__tx_thread_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_preempt_restore: +@ + LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r2 @ Enter IRQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r0 @ Enter SVC mode + B _tx_thread_schedule @ Return to scheduler +@} + + + diff --git a/ports/cortex_a9/gnu/src/tx_thread_context_save.S b/ports/cortex_a9/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..59370609 --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_context_save.S @@ -0,0 +1,203 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_irq_processing_return + .global _tx_execution_isr_enter +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} @ Store other registers +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr@ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #16 @ Recover saved registers + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@} + + + diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S new file mode 100644 index 00000000..2aa3606b --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_restore.S @@ -0,0 +1,260 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ +SVC_MODE = 0xD3 @ SVC mode +FIQ_MODE = 0xD1 @ FIQ mode +MODE_MASK = 0x1F @ Mode mask +THUMB_MASK = 0x20 @ Thumb bit mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_context_restore(VOID) +@{ + .global _tx_thread_fiq_context_restore + .type _tx_thread_fiq_context_restore,function +_tx_thread_fiq_context_restore: +@ +@ /* Lockout interrupts. */ +@ + CPSID if @ Disable IRQ and FIQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_fiq_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, [sp] @ Pickup the saved SPSR + MOV r2, #MODE_MASK @ Build mask to isolate the interrupted mode + AND r1, r1, r2 @ Isolate mode bits + CMP r1, #IRQ_MODE_BITS @ Was an interrupt taken in IRQ mode before we + @ got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore @ Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore @ Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_fiq_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore @ No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_fiq_preempt_restore: +@ + LDMIA sp!, {r3, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR_c, r2 @ Reenter FIQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block */ +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_fiq_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_fiq_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + ADD sp, sp, #24 @ Recover FIQ stack space + MOV r3, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r3 @ Lockout interrupts + B _tx_thread_schedule @ Return to scheduler +@ +@} + diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S new file mode 100644 index 00000000..970ddfd0 --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_context_save.S @@ -0,0 +1,204 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_fiq_processing_return + .global _tx_execution_isr_enter +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@ VOID _tx_thread_fiq_context_save(VOID) +@{ + .global _tx_thread_fiq_context_save + .type _tx_thread_fiq_context_save,function +_tx_thread_fiq_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +__tx_thread_fiq_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, lr} @ Store other registers, Note that we don't +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested +@ @ interrupt processing does need to save +@ @ these registers. +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_fiq_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif +@ +@ /* Not much to do here, save the current SPSR and LR for possible +@ use in IRQ interrupted in idle system conditions, and return to +@ FIQ interrupt processing. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, lr} @ Store other registers that will get used +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@} + diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S new file mode 100644 index 00000000..a9e545bc --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_end.S @@ -0,0 +1,116 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +FIQ_MODE_BITS = 0x11 @ FIQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_end(VOID) +@{ + .global _tx_thread_fiq_nesting_end + .type _tx_thread_fiq_nesting_end,function +_tx_thread_fiq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode + +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S new file mode 100644 index 00000000..85bbbb41 --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_fiq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +FIQ_DISABLE = 0x40 @ FIQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_start(VOID) +@{ + .global _tx_thread_fiq_nesting_start + .type _tx_thread_fiq_nesting_start,function +_tx_thread_fiq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..54557d55 --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" */ +@ + +INT_MASK = 0x03F + +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_control +$_tx_thread_interrupt_control: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_control(UINT new_posture) +@{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r3, CPSR @ Pickup current CPSR + MOV r2, #INT_MASK @ Build interrupt mask + AND r1, r3, r2 @ Clear interrupt lockout bits + ORR r1, r1, r0 @ Or-in new interrupt lockout bits +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r1 @ Setup new CPSR + BIC r0, r3, r2 @ Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..3f6b5de5 --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_disable.S @@ -0,0 +1,113 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_disable +$_tx_thread_interrupt_disable: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_disable(void) +@{ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r0, CPSR @ Pickup current CPSR +@ +@ /* Mask interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ +#else + CPSID i @ Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..b4469688 --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_interrupt_restore.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_restore +$_tx_thread_interrupt_restore: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring interrupts to the state */ +@/* returned by a previous _tx_thread_interrupt_disable call. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_restore(UINT old_posture) +@{ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r0 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..955667ca --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_end(VOID) +@{ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..65a24d7f --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +IRQ_DISABLE = 0x80 @ IRQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_start(VOID) +@{ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a9/gnu/src/tx_thread_schedule.S b/ports/cortex_a9/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..78d18a2e --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_schedule.S @@ -0,0 +1,255 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_execution_thread_enter +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_schedule + .type $_tx_thread_schedule,function +$_tx_thread_schedule: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_schedule @ Call _tx_thread_schedule function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: +@ +@ /* Enable interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if @ Enable IRQ and FIQ interrupts +#else + CPSIE i @ Enable IRQ interrupts +#endif +@ +@ /* Wait for a thread to execute. */ +@ do +@ { + LDR r1, =_tx_thread_execute_ptr @ Address of thread execute ptr +@ +__tx_thread_schedule_loop: +@ + LDR r0, [r1] @ Pickup next thread to execute + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_schedule_loop @ If so, keep looking for a thread +@ +@ } +@ while(_tx_thread_execute_ptr == TX_NULL); +@ +@ /* Yes! We have a thread to execute. Lockout interrupts and +@ transfer control to it. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Setup the current thread pointer. */ +@ _tx_thread_current_ptr = _tx_thread_execute_ptr; +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + STR r0, [r1] @ Setup current thread pointer +@ +@ /* Increment the run count for this thread. */ +@ _tx_thread_current_ptr -> tx_thread_run_count++; +@ + LDR r2, [r0, #4] @ Pickup run counter + LDR r3, [r0, #24] @ Pickup time-slice for this thread + ADD r2, r2, #1 @ Increment thread run-counter + STR r2, [r0, #4] @ Store the new run counter +@ +@ /* Setup time-slice, if present. */ +@ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + @ variable + LDR sp, [r0, #8] @ Switch stack pointers + STR r3, [r2] @ Setup time-slice +@ +@ /* Switch to the thread's stack. */ +@ sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + MOV r5, r0 @ Save r0 + BL _tx_execution_thread_enter @ Call the thread execution enter function + MOV r0, r5 @ Restore r0 +#endif +@ +@ /* Determine if an interrupt frame or a synchronous task suspension frame +@ is present. */ +@ + LDMIA sp!, {r4, r5} @ Pickup the stack type and saved CPSR + CMP r4, #0 @ Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 @ Setup SPSR for return +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore @ No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} @ Recover D0-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt + +_tx_solicited_return: + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore @ No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} @ Recover D8-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 @ Recover CPSR + LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ + +#ifdef TX_ENABLE_VFP_SUPPORT + + .global tx_thread_vfp_enable + .type tx_thread_vfp_enable,function +tx_thread_vfp_enable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable + MOV r0, #1 @ Build enable value + STR r0, [r1, #144] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + + .global tx_thread_vfp_disable + .type tx_thread_vfp_disable,function +tx_thread_vfp_disable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable + MOV r0, #0 @ Build disable value + STR r0, [r1, #144] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + +#endif + diff --git a/ports/cortex_a9/gnu/src/tx_thread_stack_build.S b/ports/cortex_a9/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..e4724f6e --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,178 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ + .arm + +SVC_MODE = 0x13 @ SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ interrupts enabled +#else +CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interrupts enabled +#endif +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_thread_stack_build + .type $_tx_thread_stack_build,function +$_tx_thread_stack_build: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_stack_build @ Call _tx_thread_stack_build function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-A9 should look like the following after it is built: +@ +@ Stack Top: 1 Interrupt stack frame type +@ CPSR Initial value for CPSR +@ a1 (r0) Initial value for a1 +@ a2 (r1) Initial value for a2 +@ a3 (r2) Initial value for a3 +@ a4 (r3) Initial value for a4 +@ v1 (r4) Initial value for v1 +@ v2 (r5) Initial value for v2 +@ v3 (r6) Initial value for v3 +@ v4 (r7) Initial value for v4 +@ v5 (r8) Initial value for v5 +@ sb (r9) Initial value for sb +@ sl (r10) Initial value for sl +@ fp (r11) Initial value for fp +@ ip (r12) Initial value for ip +@ lr (r14) Initial value for lr +@ pc (r15) Initial value for pc +@ 0 For stack backtracing +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #7 @ Ensure 8-byte alignment + SUB r2, r2, #76 @ Allocate space for the stack frame +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #1 @ Build interrupt stack type + STR r3, [r2, #0] @ Store stack type + MOV r3, #0 @ Build initial register value + STR r3, [r2, #8] @ Store initial r0 + STR r3, [r2, #12] @ Store initial r1 + STR r3, [r2, #16] @ Store initial r2 + STR r3, [r2, #20] @ Store initial r3 + STR r3, [r2, #24] @ Store initial r4 + STR r3, [r2, #28] @ Store initial r5 + STR r3, [r2, #32] @ Store initial r6 + STR r3, [r2, #36] @ Store initial r7 + STR r3, [r2, #40] @ Store initial r8 + STR r3, [r2, #44] @ Store initial r9 + LDR r3, [r0, #12] @ Pickup stack starting address + STR r3, [r2, #48] @ Store initial r10 (sl) + LDR r3,=_tx_thread_schedule @ Pickup address of _tx_thread_schedule for GDB backtrace + STR r3, [r2, #60] @ Store initial r14 (lr) + MOV r3, #0 @ Build initial register value + STR r3, [r2, #52] @ Store initial r11 + STR r3, [r2, #56] @ Store initial r12 + STR r1, [r2, #64] @ Store initial pc + STR r3, [r2, #68] @ 0 for back-trace + MRS r1, CPSR @ Pickup CPSR + BIC r1, r1, #CPSR_MASK @ Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] @ Store initial CPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a9/gnu/src/tx_thread_system_return.S b/ports/cortex_a9/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..c7123974 --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_system_return.S @@ -0,0 +1,180 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm +@ +@ + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_execution_thread_exit +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_system_return + .type $_tx_thread_system_return,function +$_tx_thread_system_return: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_system_return @ Call _tx_thread_system_return function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_system_return(VOID) +@{ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: +@ +@ /* Save minimal context on the stack. */ +@ + STMDB sp!, {r4-r11, lr} @ Save minimal context + + LDR r4, =_tx_thread_current_ptr @ Pickup address of current ptr + LDR r5, [r4] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r5, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save @ No, skip VFP solicited save + VMRS r1, FPSCR @ Pickup the FPSCR + STR r1, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D8-D15} @ Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 @ Build a solicited stack type + MRS r1, CPSR @ Pickup the CPSR + STMDB sp!, {r0-r1} @ Save type and CPSR +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + BL _tx_execution_thread_exit @ Call the thread exit function +#endif + MOV r3, r4 @ Pickup address of current ptr + MOV r0, r5 @ Pickup current thread pointer + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + LDR r1, [r2] @ Pickup current time slice +@ +@ /* Save current stack and switch to system stack. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ sp = _tx_thread_system_stack_ptr; +@ + STR sp, [r0, #8] @ Save thread stack pointer +@ +@ /* Determine if the time-slice is active. */ +@ if (_tx_timer_time_slice) +@ { +@ + MOV r4, #0 @ Build clear value + CMP r1, #0 @ Is a time-slice active? + BEQ __tx_thread_dont_save_ts @ No, don't save the time-slice +@ +@ /* Save time-slice for the thread and clear the current time-slice. */ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r4, [r2] @ Clear time-slice + STR r1, [r0, #24] @ Save current time-slice +@ +@ } +__tx_thread_dont_save_ts: +@ +@ /* Clear the current thread pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + STR r4, [r3] @ Clear current thread pointer + B _tx_thread_schedule @ Jump to scheduler! +@ +@} + diff --git a/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..7c588776 --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_thread_vectored_context_save.S @@ -0,0 +1,190 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_execution_isr_enter +@ +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_vectored_context_save(VOID) +@{ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #32 @ Recover saved registers + MOV pc, lr @ Return to caller +@ +@ } +@} + diff --git a/ports/cortex_a9/gnu/src/tx_timer_interrupt.S b/ports/cortex_a9/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..00512a4d --- /dev/null +++ b/ports/cortex_a9/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,279 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ + .arm + +@ +@/* Define Assembly language external references... */ +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_timer_interrupt + .type $_tx_timer_interrupt,function +$_tx_timer_interrupt: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_timer_interrupt @ Call _tx_timer_interrupt function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-A9/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1] @ Pickup current timer + LDR r2, [r0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wraparound. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup address of timer list end + LDR r2, [r3] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wraparound logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup address of timer list start + LDR r0, [r3] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + LDR r2, [r3] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup address of other expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup address of expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r2, [r3] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} + diff --git a/ports/cortex_a9/iar/example_build/azure_rtos.eww b/ports/cortex_a9/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..17e0d329 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/azure_rtos.eww @@ -0,0 +1,13 @@ + + + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\tx.ewp + + + + + diff --git a/ports/cortex_a9/iar/example_build/cstartup.s b/ports/cortex_a9/iar/example_build/cstartup.s new file mode 100644 index 00000000..647de2e8 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/cstartup.s @@ -0,0 +1,156 @@ + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 14520 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector + PUBLIC __vector_0x14 + PUBLIC __iar_program_start + EXTERN __tx_undefined + EXTERN __tx_swi_interrupt + EXTERN __tx_prefetch_handler + EXTERN __tx_abort_handler + EXTERN __tx_irq_handler + EXTERN __tx_fiq_handler + + ARM +__vector: + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort +__vector_0x14: + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + +Reset_Addr: DCD __iar_program_start +Undefined_Addr: DCD __tx_undefined +SWI_Addr: DCD __tx_swi_interrupt +Prefetch_Addr: DCD __tx_prefetch_handler +Abort_Addr: DCD __tx_abort_handler +IRQ_Addr: DCD __tx_irq_handler +FIQ_Addr: DCD __tx_fiq_handler + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reser execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + +; PUBLIC ?cstartup + EXTERN ?main + REQUIRE __vector + + ARM + +__iar_program_start: +?cstartup: + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR + +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + + + MRS r0, cpsr ; Original PSR value + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + +#ifdef __ARMVFP__ + MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register + ORR r1, r1, #(0xf << 20) ; Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 ; Flush prefetch buffer because of FMXR below and + ; CP 10 & 11 were only just enabled + MOV r0, #0x40000000 ; Enable VFP itself + FMXR FPEXC, r0 ; FPEXC = r0 +#endif + +; +; Add more initialization here +; + +; Continue to ?main for C-level initialization. + + B ?main + + END + + + diff --git a/ports/cortex_a9/iar/example_build/sample_threadx.c b/ports/cortex_a9/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..c7c300cb --- /dev/null +++ b/ports/cortex_a9/iar/example_build/sample_threadx.c @@ -0,0 +1,372 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +UCHAR memory_pool[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_pool, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a9/iar/example_build/sample_threadx.dep b/ports/cortex_a9/iar/example_build/sample_threadx.dep new file mode 100644 index 00000000..714728f2 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/sample_threadx.dep @@ -0,0 +1,220 @@ + + + 4 + 512928594 + + Debug + + $PROJ_DIR$\tx_api.h + $PROJ_DIR$\tx_port.h + $PROJ_DIR$\Debug\Obj\TX_ILL.r79 + $PROJ_DIR$\tx_initialize_low_level.s + $PROJ_DIR$\sample_threadx.c + $TOOLKIT_DIR$\inc\c\ycheck.h + $TOOLKIT_DIR$\inc\xencoding_limits.h + $PROJ_DIR$\TX_ILL.s79 + $TOOLKIT_DIR$\inc\string.h + $PROJ_DIR$\DEMO.C + $PROJ_DIR$\cstartup.s + $PROJ_DIR$\Debug\Obj\tx_initialize_low_level.o + $PROJ_DIR$\Debug\Exe\tx.a + $PROJ_DIR$\Debug\Obj\sample_threadx.pbd + $TOOLKIT_DIR$\inc\stdlib.h + $PROJ_DIR$\Debug\Exe\sample_threadx.out + $PROJ_DIR$\Debug\List\cstartup.lst + $PROJ_DIR$\Debug\Obj\tx_cstartup.r79 + $TOOLKIT_DIR$\inc\DLib_Defaults.h + $PROJ_DIR$\Debug\List\tx_initialize_low_level.lst + $TOOLKIT_DIR$\inc\c\string.h + $TOOLKIT_DIR$\inc\c\stdlib.h + $TOOLKIT_DIR$\inc\DLib_Product_string.h + $TOOLKIT_DIR$\lib\m7Sx_tlv.a + $TOOLKIT_DIR$\inc\DLib_Threads.h + $TOOLKIT_DIR$\inc\DLib_Config_Normal.h + $TOOLKIT_DIR$\inc\ysizet.h + $PROJ_DIR$\sample_threadx.icf + $PROJ_DIR$\tx_initialize_low_level.s79 + $PROJ_DIR$\Debug\Obj\demo.r79 + $TOOLKIT_DIR$\inc\DLib_Product.h + $TOOLKIT_DIR$\lib\dl7Sx_tln.a + $TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h + $TOOLKIT_DIR$\inc\yvals.h + $PROJ_DIR$\tx_execution_profile.c + $TOOLKIT_DIR$\inc\c\yvals.h + $TOOLKIT_DIR$\lib\rt7Sx_tl.a + $TOOLKIT_DIR$\lib\sh7Sxs_l.a + $TOOLKIT_DIR$\inc\ycheck.h + $PROJ_DIR$\Debug\Obj\tx_execution_profile.pbi + $PROJ_DIR$\Debug\List\sample_threadx.map + $TOOLKIT_DIR$\inc\c\ysizet.h + $PROJ_DIR$\Debug\Obj\cstartup.o + $PROJ_DIR$\Debug\Obj\sample_threadx.o + $PROJ_DIR$\tx_cstartup.s79 + $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $PROJ_DIR$\Debug\Obj\tx_execution_profile.o + $TOOLKIT_DIR$\inc\intrinsics.h + $TOOLKIT_DIR$\inc\c\intrinsics.h + $PROJ_DIR$\Debug\Obj\sample_threadx.xcl + $TOOLKIT_DIR$\inc\c\DLib_Product_string.h + $PROJ_DIR$\cstartup.s79 + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send.c + $PROJ_DIR$\Debug\Obj\sample_threadx.__cstat.et + $PROJ_DIR$\..\inc\tx_port.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_api.h + $TOOLKIT_DIR$\inc\c\iar_intrinsics_common.h + $TOOLKIT_DIR$\inc\c\iccarm_builtin.h + + + [ROOT_NODE] + + + ILINK + 15 40 + + + + + $PROJ_DIR$\tx_initialize_low_level.s + + + AARM + 11 19 + + + + + $PROJ_DIR$\sample_threadx.c + + + ICCARM + 43 + + + __cstat + 55 + + + BICOMP + 50 + + + + + ICCARM + 57 56 21 5 35 53 45 46 41 32 20 51 49 59 58 + + + + + $PROJ_DIR$\TX_ILL.s79 + + + AARM + 2 + + + + + $PROJ_DIR$\DEMO.C + + + ICCARM + 29 + + + + + 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$PROJ_DIR$\sample_threadx.c + + + $PROJ_DIR$\Debug\Exe\tx.a + + + $PROJ_DIR$\tx_api.h + + + $PROJ_DIR$\tx_initialize_low_level.s + + + $PROJ_DIR$\tx_port.h + + + diff --git a/ports/cortex_a9/iar/example_build/sample_threadx.icf b/ports/cortex_a9/iar/example_build/sample_threadx.icf new file mode 100644 index 00000000..9c95e1d1 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/sample_threadx.icf @@ -0,0 +1,49 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x80; +define symbol __ICFEDIT_region_ROM_end__ = 0x1FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x100000; +define symbol __ICFEDIT_region_RAM_end__ = 0x1FFFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_size_freemem__ = 0x100000; + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_freemem = mem:[from 0x200000 to 0x300000]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP}; + +place in RAM_region { last section FREE_MEM}; \ No newline at end of file diff --git a/ports/cortex_a9/iar/example_build/settings/azure_rtos.wsdt b/ports/cortex_a9/iar/example_build/settings/azure_rtos.wsdt new file mode 100644 index 00000000..b0ed62eb --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/azure_rtos.wsdt @@ -0,0 +1,535 @@ + + + + + sample_threadx/Debug + tx/Debug + + sample_threadx + 1 + + + + + 21 + 2518 + 2 + + 0 + -1 + + + + 34001 + 0 + + + + + 57600 + 57601 + 57603 + 33024 + 0 + 57607 + 0 + 57635 + 57634 + 57637 + 0 + 57643 + 57644 + 0 + 33090 + 33057 + 57636 + 57640 + 57641 + 33026 + 33065 + 33063 + 33064 + 33053 + 33054 + 0 + 33035 + 33036 + 34399 + 0 + 33038 + 33039 + 0 + + + + + 248 + 30 + 30 + 30 + + + <ws> + + + + 14 + 25 + + + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 0100000009002596000002000000108600001F0000000C8100000E000000048600000200000017810000070000000E81000001000000118600001F0000004681000003000000E880000004000000 + + + 0A000D8400000F84000008840000FFFFFFFF54840000328100001C810000098400000E84000030840000 + 0400048400004C000000068400004E0000000B8100001B0000000D8100001D000000 + + + 0 + 0A0000000A0000006E0000006E000000 + 000000004E050000000A000061050000 + 4096 + 0 + 0 + 32767 + 0 + + + 1 + + + 34051 + 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+ + + 34050 + 0A0000000A0000006E0000006E000000 + 0000000000000000FE0200001A000000 + 8192 + 0 + 0 + 744 + 0 + + + 1 + + + + 34048 + 34049 + 34050 + 34051 + 34052 + 34053 + 34054 + 34055 + 34056 + 34057 + 34058 + 34059 + 34060 + 34061 + 34062 + 34063 + 34064 + 34065 + + + + 01000000030000000100000000000000000000000100000001000000FFFFFFFF00000000010000000100000000000000280000002800000000000000 + + + + diff --git a/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.cspy.bat b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.cspy.bat new file mode 100644 index 00000000..94aadadb --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 new file mode 100644 index 00000000..63278961 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} diff --git a/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.driver.xcl new file mode 100644 index 00000000..a969962f --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-A9" + +"--fpu=VFPv3Neon" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.general.xcl new file mode 100644 index 00000000..1f2b1698 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/sample_threadx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a9\iar\example_build\Debug\Exe\sample_threadx.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports/cortex_a9/iar/example_build/settings/sample_threadx.crun b/ports/cortex_a9/iar/example_build/settings/sample_threadx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/sample_threadx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports/cortex_a9/iar/example_build/settings/sample_threadx.dbgdt b/ports/cortex_a9/iar/example_build/settings/sample_threadx.dbgdt new file mode 100644 index 00000000..cd1843d2 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/sample_threadx.dbgdt @@ -0,0 +1,1397 @@ + + + + + 34048 + 34049 + 34050 + 34051 + 34052 + 34053 + 34054 + 34055 + 34056 + 34057 + 34058 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/dev/null +++ b/ports/cortex_a9/iar/example_build/settings/tx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports/cortex_a9/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports/cortex_a9/iar/example_build/settings/tx.Debug.cspy.ps1 new file mode 100644 index 00000000..6a1889c0 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/tx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} diff --git a/ports/cortex_a9/iar/example_build/settings/tx.Debug.driver.xcl b/ports/cortex_a9/iar/example_build/settings/tx.Debug.driver.xcl new file mode 100644 index 00000000..a969962f --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/tx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-A9" + +"--fpu=VFPv3Neon" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/cortex_a9/iar/example_build/settings/tx.Debug.general.xcl b/ports/cortex_a9/iar/example_build/settings/tx.Debug.general.xcl new file mode 100644 index 00000000..deeeb2f9 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/tx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armsim2.dll" + +"C:\release\threadx\Debug\Exe\tx.out" + +--plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0_2\arm\bin\armbat.dll" + + + + diff --git a/ports/cortex_a9/iar/example_build/settings/tx.crun b/ports/cortex_a9/iar/example_build/settings/tx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/tx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports/cortex_a9/iar/example_build/settings/tx.dbgdt b/ports/cortex_a9/iar/example_build/settings/tx.dbgdt new file mode 100644 index 00000000..73e71f6e --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/tx.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports/cortex_a9/iar/example_build/settings/tx.dnx b/ports/cortex_a9/iar/example_build/settings/tx.dnx new file mode 100644 index 00000000..1872e83f --- /dev/null +++ b/ports/cortex_a9/iar/example_build/settings/tx.dnx @@ -0,0 +1,58 @@ + + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports/cortex_a9/iar/example_build/tx.dep b/ports/cortex_a9/iar/example_build/tx.dep new file mode 100644 index 00000000..a1dc2578 --- /dev/null +++ b/ports/cortex_a9/iar/example_build/tx.dep @@ -0,0 +1,9593 @@ + + + 4 + 607583892 + + Debug + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_put.c + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_create.c + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_relinquish.c + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_delete.c + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_prioritize.c + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_get.c + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_flush.c + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_prioritize.c + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_ceiling_put.c + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_prioritize.c + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_receive.c + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send_notify.c + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_create.c + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_create.c + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_delete.c + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_preemption_change.c + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set_notify.c + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_create.c + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_priority_change.c + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_front_send.c + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put.c + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put_notify.c + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_delete.c + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_delete.c + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_get.c + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_entry_exit_notify.c + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send.c + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set.c + $PROJ_DIR$\..\..\..\..\common\src\txe_block_allocate.c + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_initialize.c + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_enter_insert.c + $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_delete.c + $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_delete.c + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_register.c + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_disable.c + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_buffer_full_notify.c + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_filter.c + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_interrupt_control.c + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_user_event_insert.c + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_unfilter.c + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_system_deactivate.c + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_enable.c + $PROJ_DIR$\..\..\..\..\common\src\txe_block_release.c + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_exit_insert.c + $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_unregister.c + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_allocate.c + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_prioritize.c + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_create.c + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_release.c + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_create.c + $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_prioritize.c + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_delete.c + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_thread_entry.c + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_get.c + $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_create.c + $PROJ_DIR$\tx_api.h + $PROJ_DIR$\tx_block_pool_cleanup.c + $PROJ_DIR$\tx_block_pool_prioritize.c + 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+++ b/ports/cortex_a9/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,327 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; Disable irq,fiq SVC mode +IRQ_MODE DEFINE 0xD2 ; Disable irq,fiq IRQ mode +FIQ_MODE DEFINE 0xD1 ; Disable irq,fiq FIQ mode +SYS_MODE DEFINE 0xDF ; Disable irq,fiq SYS mode +; +; + + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_thread_context_save +; EXTERN _tx_thread_vectored_context_save + EXTERN _tx_thread_context_restore +#ifdef TX_ENABLE_FIQ_SUPPORT + EXTERN _tx_thread_fiq_context_save + EXTERN _tx_thread_fiq_context_restore +#endif +#ifdef TX_ENABLE_IRQ_NESTING + EXTERN _tx_thread_irq_nesting_start + EXTERN _tx_thread_irq_nesting_end +#endif +#ifdef TX_ENABLE_FIQ_NESTING + EXTERN _tx_thread_fiq_nesting_start + EXTERN _tx_thread_fiq_nesting_end +#endif + EXTERN _tx_timer_interrupt + EXTERN ?cstartup + EXTERN _tx_build_options + EXTERN _tx_version_id +; +; +; +;/* Define the FREE_MEM segment that will specify where free memory is +; defined. This must also be located in at the end of other RAM segments +; in the linker control file. The value of this segment is what is passed +; to tx_application_define. */ +; + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + CODE32 + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level +; +; /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode. */ +; +; /* Remember the stack pointer, link register, and switch to SVC mode. */ +; + MOV r0, sp ; Remember the SP + MOV r1, lr ; Remember the LR + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r3 ; Switch to SVC mode + MOV sp, r0 ; Inherit the stack pointer setup by cstartup + MOV lr, r1 ; Inherit the link register +; +; /* Pickup the start of free memory. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) FREE_MEM; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Done, return to caller. */ +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +;/* Define shells for each of the interrupt vectors. */ +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt ; Software interrupt handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_prefetch_handler +__tx_prefetch_handler + B __tx_prefetch_handler ; Prefetch exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_abort_handler +__tx_abort_handler + B __tx_abort_handler ; Abort exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +; +; /* For debug purpose, execute the timer interrupt processing here. In +; a real system, some kind of status indication would have to be checked +; before the timer interrupt handler could be called. */ +; + BL _tx_timer_interrupt ; Timer interrupt handler +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; +; RSEG .text:CODE:NOROOT(2) +; PUBLIC __tx_example_vectored_irq_handler +;__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +;#endif +; +; /* Application IRQ handler is called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +;#ifdef TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +;#endif +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; +#else + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler +#endif +; +; +BUILD_OPTIONS + DC32 _tx_build_options ; Reference to ensure it comes in +VERSION_ID + DC32 _tx_version_id ; Reference to ensure it comes in + END + diff --git a/ports/cortex_a9/iar/inc/tx_port.h b/ports/cortex_a9/iar/inc/tx_port.h new file mode 100644 index 00000000..4d6d1537 --- /dev/null +++ b/ports/cortex_a9/iar/inc/tx_port.h @@ -0,0 +1,398 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A9/IAR */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \ + VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#if __CORE__ > __ARM4TM__ + +#if __CPU_MODE__ == 2 + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (UINT) __CLZ(m); \ + b = 31 - b; +#endif +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + + +/* First, check and see what mode the file is being compiled in. The IAR compiler + defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode + is present. If ARM 32-bit mode is present, the fast CPSR manipulation macros + are available. Otherwise, if Thumb mode is present, we must use function calls. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else +#if __CPU_MODE__ == 2 + +#if (__VER__ < 8002000) +__intrinsic unsigned long __get_CPSR(); +__intrinsic void __set_CPSR( unsigned long ); +#endif + + +#if (__VER__ < 8002000) +#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#else +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#endif + + +#define TX_DISABLE interrupt_save = __get_CPSR(); \ + __set_CPSR(interrupt_save | TX_INT_DISABLE); +#define TX_RESTORE __set_CPSR(interrupt_save); + +#else + +UINT _tx_thread_interrupt_disable(void); +void _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#endif +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A9. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/IAR Version 6.0 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + diff --git a/ports/cortex_a9/iar/readme_threadx.txt b/ports/cortex_a9/iar/readme_threadx.txt new file mode 100644 index 00000000..f2221ee0 --- /dev/null +++ b/ports/cortex_a9/iar/readme_threadx.txt @@ -0,0 +1,544 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A9 + + Thumb & 32-bit Mode + + Using the IAR Tools + +1. Building the ThreadX run-time Library + +Building the ThreadX library is easy. First, open the Azure RTOS workspace +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by +the application. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the IAR +Windows-based Cortex-A9 simulator. + +Building the demonstration is easy; simply make the sample_threadx.ewp project +the "active project" in the IAR Embedded Workbench and select the +"Make" button. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a +binary file that can be downloaded and executed on IAR's Cortex-A9 simulator. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A9 using IAR tools is at label +?cstartup. This is defined within the IAR compiler's startup code. In +addition, this is where all static and global preset C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. +By default, the vector area is defined at the top of cstartup.s, which is +a slightly modified from the base IAR file. + +The _tx_initialize_low_level function inside of tx_initialize_low_level.s +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all +other RAM sections in memory. + + +4. Register Usage and Stack Frames + +The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are +scratch registers for each function. All other registers used by a C function +must be preserved by the function. ThreadX takes advantage of this in +situations where a context switch happens as a result of making a ThreadX +service call (which is itself a C function). In such cases, the saved +context of a thread is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +5. Conditional Compilation Switches + +The following are conditional compilation options for building the ThreadX library +and application: + + + TX_ENABLE_FIQ_SUPPORT This assembler/compiler define enables + FIQ interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + + TX_ENABLE_IRQ_NESTING This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. + + TX_ENABLE_FIQ_NESTING This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. In addition, + IRQ nesting should also be enabled. + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + TX_THUMB Defined, this option enables the BX LR calling return sequence + in assembly files, to ensure correct operation on systems that + use both ARM and Thumb mode. By default, this option is + not defined + + + + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the ThreadX library +project to enable various compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A9 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A9 vectors start at address zero. The demonstration system startup +cstartup.s file contains the vectors and is loaded at address zero. +On actual hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + PUBLIC __tx_irq_handler + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR dispatch call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_example_vectored_irq_handler +__tx_example_vectored_irq_handler +; +; /* Jump to context save to save system context. */ + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers + BL _tx_thread_vectored_context_save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR dispatch call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +; + BL _tx_thread_irq_nesting_start + +; /* Application ISR dispatch call goes here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +; + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ dispatch call goes here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no +longer required, calling the _tx_thread_fiq_nesting_end service disables +nesting by disabling FIQ interrupts and switching back to FIQ mode in +preparation for the FIQ context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_handler + RSEG .text:CODE:NOROOT(2) + PUBLIC __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ dispatch call goes here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to _tx_timer_interrupt +in the IRQ processing. + + +9. Thumb/Cortex-A9 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. The only exception +to this is the file tx_thread_shell_entry.c. This file must always be +built in 32-bit mode. In addition, if any Thumb code is used the entire +ThreadX assembly source should be built with TX_THUMB defined. + + +10. IAR Thread-safe Library Support + +Thread-safe support for the IAR tools is easily enabled by building the ThreadX library +and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file +should have the following line added (if not already in place): + +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application + +The project options "General Options -> Library Configuration" should also have the +"Enable thread support in library" box selected. + + +11. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + + +12. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX version 6.0.1 for Cortex-A9 using IAR's ARM tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a9/iar/src/tx_iar.c b/ports/cortex_a9/iar/src/tx_iar.c new file mode 100644 index 00000000..11fcefb3 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports/cortex_a9/iar/src/tx_thread_context_restore.s b/ports/cortex_a9/iar/src/tx_thread_context_restore.s new file mode 100644 index 00000000..fbdffc78 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_context_restore.s @@ -0,0 +1,259 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +SVC_MODE DEFINE 0xD3 ; SVC mode +IRQ_MODE DEFINE 0xD2 ; IRQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +THUMB_MASK DEFINE 0x20 ; Thumb bit mask +SVC_MODE_BITS DEFINE 0x13 ; SVC mode value + +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_restore + CODE32 +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + MRS r3, CPSR ; Pickup current CPSR + ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value + MSR CPSR_cxsf, r0 ; Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block + BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS ; Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 ; Lockout interrupts +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r3, r3, #MODE_MASK ; Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +;} +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_context_save.s b/ports/cortex_a9/iar/src/tx_thread_context_save.s new file mode 100644 index 00000000..63f4792a --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_context_save.s @@ -0,0 +1,210 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif + + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_irq_processing_return + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_context_save + CODE32 +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r0 ; Disable interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s b/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..566dcd15 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,270 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE DEFINE 0xD3 ; SVC mode +FIQ_MODE DEFINE 0xD1 ; FIQ mode +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +THUMB_MASK DEFINE 0x20 ; Thumb bit mask +IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits +SVC_MODE_BITS DEFINE 0x13 ; SVC mode value + +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_restore + CODE32 +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + MRS r3, CPSR ; Pickup current CPSR + ORR r0, r3, #DISABLE_INTS ; Build interrupt disable value + MSR CPSR_cxsf, r0 ; Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_cxsf, r2 ; Re-enter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_cxsf, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block */ + BIC r4, r4, #THUMB_MASK ; Clear the Thumb bit of CPSR + ORR r3, r4, #DISABLE_INTS ; Or-in interrupt lockout bit(s) + MSR CPSR_cxsf, r3 ; Lockout interrupts +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MRS r3, CPSR ; Pickup current CPSR + BIC r3, r3, #MODE_MASK ; Clear the mode portion of the CPSR + ORR r3, r3, #SVC_MODE_BITS ; Or-in new interrupt lockout bit + MSR CPSR_cxsf, r3 ; Lockout interrupts + B _tx_thread_schedule ; Return to scheduler +; +;} +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_context_save.s b/ports/cortex_a9/iar/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..c60ea9a4 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN __tx_fiq_processing_return + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_context_save + CODE32 +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..15350c38 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,109 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_end + CODE32 +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_cxsf, r0 ; Disable interrupts + LDR lr, [sp] ; Pickup saved lr + ADD sp, sp, #4 ; Adjust stack pointer + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_cxsf, r0 ; Re-enter IRQ mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..75cb6a98 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +FIQ_DISABLE DEFINE 0x40 ; FIQ disable bit +MODE_MASK DEFINE 0x1F ; Mode mask +SYS_MODE_BITS DEFINE 0x1F ; System mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_fiq_nesting_start + CODE32 +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + STR lr, [sp, #-4]! ; Push the system mode lr on the system mode stack + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_interrupt_control.s b/ports/cortex_a9/iar/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..4ad92728 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_interrupt_control.s @@ -0,0 +1,103 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +INT_MASK DEFINE 0xC0 ; Interrupt bit mask +#else +INT_MASK DEFINE 0x80 ; Interrupt bit mask +#endif +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_control + CODE32 +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} +; +; + END diff --git a/ports/cortex_a9/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_a9/iar/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..31680cbb --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_interrupt_disable.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_disable + CODE32 +_tx_thread_interrupt_disable??rA +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + ORR r1, r0, #DISABLE_INTS ; Mask interrupts + MSR CPSR_cxsf, r1 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; +; + END diff --git a/ports/cortex_a9/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_a9/iar/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..78eeeb68 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;void _tx_thread_interrupt_restore(UINT old_posture) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_interrupt_restore + CODE32 +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_cxsf, r0 ; Setup new CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} +; + END diff --git a/ports/cortex_a9/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..cb0976d2 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts +#else +DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts +#endif +MODE_MASK DEFINE 0x1F ; Mode mask +IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_end + CODE32 +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_cxsf, r0 ; Disable interrupts + LDR lr, [sp] ; Pickup saved lr + ADD sp, sp, #4 ; Adjust stack pointer + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_cxsf, r0 ; Re-enter IRQ mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..512ef7f2 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +IRQ_DISABLE DEFINE 0x80 ; IRQ disable bit +MODE_MASK DEFINE 0x1F ; Mode mask +SYS_MODE_BITS DEFINE 0x1F ; System mode bits +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s79). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_irq_nesting_start + CODE32 +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + STR lr, [sp, #-4]! ; Push the system mode lr on the system mode stack + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_cxsf, r0 ; Enter system mode + MOV pc, r3 ; Return to ISR +;} +; +; + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_schedule.s b/ports/cortex_a9/iar/src/tx_thread_schedule.s new file mode 100644 index 00000000..4c8eabbf --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_schedule.s @@ -0,0 +1,240 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask +#else +ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask +#endif +; +; + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_execution_thread_enter +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_schedule + CODE32 +_tx_thread_schedule??rA +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + MRS r2, CPSR ; Pickup CPSR + BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s) + MSR CPSR_cxsf, r0 ; Enable interrupts +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + MSR CPSR_cxsf, r2 ; Disable interrupts +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ; variable + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 +#endif +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 ; Setup SPSR for return +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + +_tx_solicited_return: +#ifdef __ARMVFP__ + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MOV r0, r5 ; Move CPSR to scratch register + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously + MSR CPSR_cxsf, r0 ; Recover CPSR +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} +; + +#ifdef __ARMVFP__ + PUBLIC tx_thread_vfp_enable + CODE32 +tx_thread_vfp_enable??rA +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + PUBLIC tx_thread_vfp_disable + CODE32 +tx_thread_vfp_disable??rA +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller +#endif + + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_stack_build.s b/ports/cortex_a9/iar/src/tx_thread_stack_build.s new file mode 100644 index 00000000..04876d27 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_stack_build.s @@ -0,0 +1,158 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE DEFINE 0x13 ; SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK DEFINE 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled +#else +CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled +#endif +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_stack_build + + CODE32 +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A9 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure long-word alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + MRS r1, CPSR ; Pickup CPSR + BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +;} + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_system_return.s b/ports/cortex_a9/iar/src/tx_thread_system_return.s new file mode 100644 index 00000000..2e4e661d --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_system_return.s @@ -0,0 +1,166 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif +; +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_execution_thread_exit +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_system_return + CODE32 +_tx_thread_system_return??rA +_tx_thread_system_return +; +; /* Lockout interrupts. */ +; + MRS r1, CPSR ; Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts +#else + CPSID i ; Disable IRQ interrupts +#endif +; +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context + LDR r5, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r6, [r5, #0] ; Pickup current thread pointer + +#ifdef __ARMVFP__ + LDR r0, [r6, #144] ; Pickup the VFP enabled flag + CMP r0, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 ; Build a solicited stack type + STMDB sp!, {r0-r1} ; Save type and CPSR +; +; +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function +#endif + + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r6, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r6, #24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r5, #0] ; Clear current thread pointer + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports/cortex_a9/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_a9/iar/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..54bf3ea3 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_thread_vectored_context_save.s @@ -0,0 +1,195 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled +#else +DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled +#endif + + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_execution_isr_enter +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_thread_vectored_context_save + CODE32 +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, the minimal context is already saved, and the +; lr register contains the return ISR address. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; +#ifdef TX_ENABLE_FIQ_SUPPORT + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt CPSR + MSR CPSR_cxsf, r0 ; Disable interrupts +#endif + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + MOV pc, lr ; Return to caller +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occured in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + MOV pc, lr ; Return to caller +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr +#endif + + ADD sp, sp, #32 ; Recover saved registers + MOV pc, lr ; Return to caller +; +; } +;} + END + diff --git a/ports/cortex_a9/iar/src/tx_timer_interrupt.s b/ports/cortex_a9/iar/src/tx_timer_interrupt.s new file mode 100644 index 00000000..629a76c5 --- /dev/null +++ b/ports/cortex_a9/iar/src/tx_timer_interrupt.s @@ -0,0 +1,260 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process +; +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A9/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time-slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + RSEG .text:CODE:NOROOT(2) + PUBLIC _tx_timer_interrupt + CODE32 +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; +#ifdef TX_THUMB + BX lr ; Return to caller +#else + MOV pc, lr ; Return to caller +#endif +; +;} + END + diff --git a/ports/cortex_m0/ac5/example_build/build_threadx.bat b/ports/cortex_m0/ac5/example_build/build_threadx.bat new file mode 100644 index 00000000..8018092d --- /dev/null +++ b/ports/cortex_m0/ac5/example_build/build_threadx.bat @@ -0,0 +1,230 @@ +del tx.a +armasm -g --cpu=cortex-m0 --apcs=interwork tx_initialize_low_level.s +armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_stack_build.s +armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_schedule.s +armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_system_return.s +armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_context_save.s +armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_context_restore.s +armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_interrupt_control.s +armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_interrupt_disable.s +armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_thread_interrupt_restore.s +armasm -g --cpu=cortex-m0 --apcs=interwork ../src/tx_timer_interrupt.s +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_allocate.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_cleanup.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_initialize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_prioritize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_block_release.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_allocate.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_cleanup.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_initialize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_prioritize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_search.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_release.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_cleanup.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_initialize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set_notify.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_high_level.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_enter.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_setup.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_cleanup.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_initialize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_system_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_prioritize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_priority_change.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_put.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_cleanup.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_flush.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_front_send.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_initialize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_system_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_prioritize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_receive.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send_notify.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_ceiling_put.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_cleanup.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_initialize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_prioritize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put_notify.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_entry_exit_notify.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_identify.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_initialize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_system_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_preemption_change.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_priority_change.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_relinquish.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_reset.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_resume.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_shell_entry.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_sleep.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_analyze.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_handler.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_notify.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_suspend.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_preempt_check.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_resume.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_suspend.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_terminate.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice_change.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_timeout.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_wait_abort.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_time_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_time_set.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_activate.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_change.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_deactivate.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_expiration_process.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_initialize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_system_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_activate.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_deactivate.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_thread_entry.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_buffer_full_notify.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_enable.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_filter.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_unfilter.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_disable.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_initialize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_interrupt_control.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_enter_insert.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_exit_insert.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_register.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_unregister.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_user_event_insert.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_block_allocate.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_prioritize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_block_release.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_allocate.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_prioritize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_release.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set_notify.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_prioritize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_put.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_flush.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_front_send.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_prioritize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_receive.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send_notify.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_ceiling_put.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_prioritize.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put_notify.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_entry_exit_notify.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_info_get.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_preemption_change.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_priority_change.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_relinquish.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_reset.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_resume.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_suspend.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_terminate.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_time_slice_change.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_wait_abort.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_activate.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_change.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_create.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_deactivate.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_delete.c +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_info_get.c +armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +armar -r tx.a tx_initialize_low_level.o tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o +armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_m0/ac5/example_build/build_threadx_sample.bat b/ports/cortex_m0/ac5/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..a213bc79 --- /dev/null +++ b/ports/cortex_m0/ac5/example_build/build_threadx_sample.bat @@ -0,0 +1,4 @@ +armasm -g --cpu=cortex-m0 --apcs=interwork tx_initialize_low_level.s +armcc -c -g --cpu=cortex-m0 -I../inc -I../../../../common/inc sample_threadx.c +armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --rw-base=0x20000000 --first __tx_vectors --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a + diff --git a/ports/cortex_m0/ac5/example_build/sample_threadx.c b/ports/cortex_m0/ac5/example_build/sample_threadx.c new file mode 100644 index 00000000..4d95c2ed --- /dev/null +++ b/ports/cortex_m0/ac5/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..61c57b5f --- /dev/null +++ b/ports/cortex_m0/ac5/example_build/tx_initialize_low_level.s @@ -0,0 +1,284 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT |Image$$RO$$Limit| + IMPORT |Image$$RW$$Base| + IMPORT |Image$$ZI$$Base| + IMPORT |Image$$ZI$$Limit| + IMPORT __tx_PendSVHandler +; +; +SYSTEM_CLOCK EQU 6000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) +; +; +;/* Setup the stack and heap areas. */ +; +STACK_SIZE EQU 0x00000400 +HEAP_SIZE EQU 0x00000000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE STACK_SIZE +__initial_sp + + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE HEAP_SIZE +__heap_limit + + + AREA RESET, CODE, READONLY +; + EXPORT __tx_vectors +__tx_vectors + DCD __initial_sp ; Reset and system stack ptr + DCD Reset_Handler ; Reset goes to startup function + DCD __tx_NMIHandler ; NMI + DCD __tx_BadHandler ; HardFault + DCD 0 ; MemManage + DCD 0 ; BusFault + DCD 0 ; UsageFault + DCD 0 ; 7 + DCD 0 ; 8 + DCD 0 ; 9 + DCD 0 ; 10 + DCD __tx_SVCallHandler ; SVCall + DCD __tx_DBGHandler ; Monitor + DCD 0 ; 13 + DCD __tx_PendSVHandler ; PendSV + DCD __tx_SysTickHandler ; SysTick + DCD __tx_IntHandler ; Int 0 + DCD __tx_IntHandler ; Int 1 + DCD __tx_IntHandler ; Int 2 + DCD __tx_IntHandler ; Int 3 +; +; + AREA ||.text||, CODE, READONLY + EXPORT Reset_Handler +Reset_Handler + CPSID i + LDR R0, =__main + BX R0 + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; /* Ensure that interrupts are disabled. */ +; + CPSID i ; Disable interrupts +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer + LDR r1, =|Image$$ZI$$Limit| ; Build first free address + ADDS r1, r1, #4 ; + STR r1, [r0] ; Setup first unused memory pointer +; +; /* Setup Vector Table Offset Register. */ +; + LDR r0, =0xE000ED08 ; Build address of NVIC registers + LDR r1, =__tx_vectors ; Pickup address of vector table + STR r1, [r0] ; Set vector table address +; +; /* Enable the cycle count register. */ +; +; LDR r0, =0xE0001000 ; Build address of DWT register +; LDR r1, [r0] ; Pickup the current value +; MOVS r2, #1 +; ORRS r1, r1, r2 ; Set the CYCCNTENA bit +; STR r1, [r0] ; Enable the cycle count register +; +; /* Setup Vector Table Offset Register. */ +; + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD08 ; Offset to vector base register + ADD r0, r0, r2 ; Build vector base register + LDR r1, =__tx_vectors ; Pickup address of vector table + STR r1, [r0] ; Set vector table address +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__tx_vectors ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOVS r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD18 ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD1C ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD20 ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; +; +;/* Define initial heap/stack routine for the ARM RVCT startup code. +; This routine will set the initial stack and heap locations */ +; + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, =HeapMem + LDR R1, =(StackMem + STACK_SIZE) + LDR R2, =(HeapMem + HEAP_SIZE) + LDR R3, =StackMem + BX LR +; +; +;/* Define shells for each of the unused vectors. */ +; + EXPORT __tx_BadHandler +__tx_BadHandler + B __tx_BadHandler + + EXPORT __tx_SVCallHandler +__tx_SVCallHandler + B __tx_SVCallHandler + + EXPORT __tx_IntHandler +__tx_IntHandler +; VOID InterruptHandler (VOID) +; { + PUSH {r0, lr} + +; /* Do interrupt handler work here */ +; /* .... */ + + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + EXPORT SysTick_Handler + EXPORT __tx_SysTickHandler +__tx_SysTickHandler +SysTick_Handler +; VOID TimerInterruptHandler (VOID) +; { +; + PUSH {r0, lr} + BL _tx_timer_interrupt + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + EXPORT __tx_NMIHandler +__tx_NMIHandler + B __tx_NMIHandler + + EXPORT __tx_DBGHandler +__tx_DBGHandler + B __tx_DBGHandler + + ALIGN + LTORG + END + + diff --git a/ports/cortex_m0/ac5/inc/tx_port.h b/ports/cortex_m0/ac5/inc/tx_port.h new file mode 100644 index 00000000..31bb6d4d --- /dev/null +++ b/ports/cortex_m0/ac5/inc/tx_port.h @@ -0,0 +1,335 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M0/AC5 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M0 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +#ifndef TX_MISRA_ENABLE + +register unsigned int _ipsr __asm("ipsr"); + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _ipsr) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_DISABLE was_masked = __disable_irq(); +#define TX_RESTORE if (was_masked == 0) __enable_irq(); + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +static void _tx_thread_system_return_inline(void) +{ +unsigned int was_masked; + + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (_ipsr == 0) + { + was_masked = __disable_irq(); + __enable_irq(); + if (was_masked != 0) + __disable_irq(); + } +} +#endif + + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.0 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + + diff --git a/ports/cortex_m0/ac5/readme_threadx.txt b/ports/cortex_m0/ac5/readme_threadx.txt new file mode 100644 index 00000000..fb2f95c3 --- /dev/null +++ b/ports/cortex_m0/ac5/readme_threadx.txt @@ -0,0 +1,143 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M0 + + Using ARM Compiler 5 (AC5) + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the AC5 +development environment. At this point you may run the build_threadx.bat batch +file. This will build the ThreadX run-time environment in the "example_build" +directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the ARM +Windows-based simulator. + +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf +is a binary file that can be downloaded and executed on the ARM simulator. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-M0 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M0 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + + Stack Offset Stack Contents + + 0x00 r8 + 0x04 r9 + 0x08 r10 + 0x0C r11 + 0x10 r4 + 0x14 r5 + 0x18 r6 + 0x1C r7 + 0x20 r0 (Hardware stack starts here!!) + 0x24 r1 + 0x28 r2 + 0x2C r3 + 0x30 r12 + 0x34 lr + 0x38 pc + 0x3C xPSR + + +5. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +6. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M0 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +6.1 Vector Area + +The Cortex-M0 vectors start at the label __tx_vectors. The application may modify +the vector area according to its needs. + +6.2 Managed Interrupts + +ISRs for Cortex-M can be written completely in C (or assembly language) without any +calls to _tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed +access to the ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + EXPORT your_assembly_isr +your_assembly_isr + + PUSH {r0, lr} + + ; ISR processing goes here, including any needed function calls. + + POP {r0, r1} + MOV lr, r1 + BX lr + + +7. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using AC5 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m0/ac5/src/tx_thread_context_restore.s b/ports/cortex_m0/ac5/src/tx_thread_context_restore.s new file mode 100644 index 00000000..4ef66308 --- /dev/null +++ b/ports/cortex_m0/ac5/src/tx_thread_context_restore.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF +; +; /* Preemption has already been addressed - just return! */ +; + POP {r0} + MOV lr, r0 + BX lr +;} + ALIGN + LTORG + END + diff --git a/ports/cortex_m0/ac5/src/tx_thread_context_save.s b/ports/cortex_m0/ac5/src/tx_thread_context_save.s new file mode 100644 index 00000000..52fd2828 --- /dev/null +++ b/ports/cortex_m0/ac5/src/tx_thread_context_save.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r0, lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, r1} ; Recover ISR lr + MOV lr, r1 + ENDIF +; +; /* Return to interrupt processing. */ +; + BX lr ; Return to interrupt processing caller +;} + ALIGN + LTORG + END + diff --git a/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..7b360417 --- /dev/null +++ b/ports/cortex_m0/ac5/src/tx_thread_interrupt_control.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + ALIGN + LTORG + END + diff --git a/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..b28496d6 --- /dev/null +++ b/ports/cortex_m0/ac5/src/tx_thread_interrupt_disable.s @@ -0,0 +1,83 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + END diff --git a/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..29d0f590 --- /dev/null +++ b/ports/cortex_m0/ac5/src/tx_thread_interrupt_restore.s @@ -0,0 +1,82 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + END diff --git a/ports/cortex_m0/ac5/src/tx_thread_schedule.s b/ports/cortex_m0/ac5/src/tx_thread_schedule.s new file mode 100644 index 00000000..abcb7c2c --- /dev/null +++ b/ports/cortex_m0/ac5/src/tx_thread_schedule.s @@ -0,0 +1,278 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + IMPORT _tx_execution_thread_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule +; +; /* This function should only ever be called on Cortex-M0 +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOVS r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + LDR r0, =0x10000000 ; Load PENDSVSET bit + LDR r1, =0xE000ED04 ; Load ICSR address + STR r0, [r1] ; Set PENDSVBIT in ICSR + DSB ; Complete all memory accesses + ISB ; Flush pipeline +; +; /* Wait here for the PendSV to take place. */ +; +__tx_wait_here + B __tx_wait_here ; Wait for the PendSV to happen +;} +; +; /* Generic context switch-out switch-in handler... Note that this handler is +; common for both PendSV and SVCall. */ +; + EXPORT PendSV_Handler + EXPORT __tx_PendSVHandler +PendSV_Handler +__tx_PendSVHandler +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, r1} ; Recover LR + MOV lr, r1 ; + CPSIE i ; Enable interrupts + ENDIF + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address + MOVS r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CMP r1,#0 ; If NULL, skip preservation + BEQ __tx_ts_new ; +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer) + SUBS r3, r3, #16 ; Allocate stack space + STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) + MOV r4,r8 ; + MOV r5,r9 ; + MOV r6,r10 ; + MOV r7,r11 ; + SUBS r3, r3, #32 ; Allocate stack space + STM r3!, {r4-r7} ; + SUBS r3, r3, #20 ; Allocate stack space + MOV r5, LR ; + STR r5, [r3] ; Save LR on the stack + STR r3, [r1, #8] ; Save its stack pointer +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r4] ; Pickup current time-slice + CMP r5, #0 ; If not active, skip processing + BEQ __tx_ts_new ; +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + MOVS r5, #0 ; Build clear value + STR r5, [r4] ; Clear time-slice +; +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CMP r1, #0 ; + BEQ __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore + LDR r7, [r1, #4] ; Pickup the current thread run count + LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADDS r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0/r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r0/r1 + ENDIF +; +; /* Restore the thread context and PSP. */ +; + LDR r3, [r1, #8] ; Pickup thread's stack pointer + LDR r5, [r3] ; Recover saved LR + ADDS r3, r3, #4 ; Position past LR + MOV lr, r5 ; Restore LR + LDM r3!,{r4-r7} ; Recover thread's registers (r4-r11) + MOV r11,r7 ; + MOV r10,r6 ; + MOV r9,r5 ; + MOV r8,r4 ; + LDM r3!,{r4-r7} ; + MSR PSP, r3 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CMP r1, #0 ; If non-NULL, a new thread is ready! + BNE __tx_ts_ready ; + IF :DEF:TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed + ENDIF +__tx_ts_ISB + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready + LDR r7, =0x08000000 ; Build clear PendSV value + LDR r5, =0xE000ED04 ; Build base NVIC address + STR r7, [r5] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread + + ALIGN + LTORG + END + diff --git a/ports/cortex_m0/ac5/src/tx_thread_stack_build.s b/ports/cortex_m0/ac5/src/tx_thread_stack_build.s new file mode 100644 index 00000000..524eb9f5 --- /dev/null +++ b/ports/cortex_m0/ac5/src/tx_thread_stack_build.s @@ -0,0 +1,146 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M0 should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + MOVS r3, #0x7 ; + BICS r2, r2, r3 ; Align frame for 8-byte alignment + SUBS r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOVS r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r8 + STR r3, [r2, #8] ; Store initial r9 + STR r3, [r2, #12] ; Store initial r10 + STR r3, [r2, #16] ; Store initial r11 + STR r3, [r2, #20] ; Store initial r4 + STR r3, [r2, #24] ; Store initial r5 + STR r3, [r2, #28] ; Store initial r6 + STR r3, [r2, #32] ; Store initial r7 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + LDR r3, =0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + LDR r3, =0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + ALIGN + LTORG + END + diff --git a/ports/cortex_m0/ac5/src/tx_thread_system_return.s b/ports/cortex_m0/ac5/src/tx_thread_system_return.s new file mode 100644 index 00000000..a1e11054 --- /dev/null +++ b/ports/cortex_m0/ac5/src/tx_thread_system_return.s @@ -0,0 +1,97 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + LDR r0, =0x10000000 ; Load PENDSVSET bit + LDR r1, =0xE000ED04 ; Load NVIC base + STR r0, [r1] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context + BX lr ; Return to caller + NOP +;} + END + diff --git a/ports/cortex_m0/ac5/src/tx_timer_interrupt.s b/ports/cortex_m0/ac5/src/tx_timer_interrupt.s new file mode 100644 index 00000000..d5844d9c --- /dev/null +++ b/ports/cortex_m0/ac5/src/tx_timer_interrupt.s @@ -0,0 +1,274 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_thread_preempt_disable +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADDS r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUBS r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOVS r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOVS r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADDS r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + PUSH {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); +; + BL _tx_thread_time_slice ; Call time-slice processing + LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CMP r1, #0 ; + BNE __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + LDR r0, =0xE000ED04 ; Build address of control register + LDR r2, =0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice +; +; } +; +__tx_timer_not_ts_expiration +; + POP {r0, r1} ; Recover lr register (r0 is just there for + MOV lr, r1 ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + ALIGN + LTORG + END + diff --git a/ports/cortex_m0/gnu/example_build/build_threadx.bat b/ports/cortex_m0/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..c74b194e --- /dev/null +++ b/ports/cortex_m0/gnu/example_build/build_threadx.bat @@ -0,0 +1,229 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_m0/gnu/example_build/build_threadx_sample.bat b/ports/cortex_m0/gnu/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..96c754d5 --- /dev/null +++ b/ports/cortex_m0/gnu/example_build/build_threadx_sample.bat @@ -0,0 +1,7 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb tx_vectors.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb cortexm0_crt0.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m0 -mthumb -I../../../../common/inc -I../inc sample_threadx.c +arm-none-eabi-ld -A cortex-m0 -ereset_handler -T sample_threadx.ld tx_vectors.o cortexm0_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libgcc.a -o sample_threadx.out -M > sample_threadx.map + + diff --git a/ports/cortex_m0/gnu/example_build/cortexm0_crt0.s b/ports/cortex_m0/gnu/example_build/cortexm0_crt0.s new file mode 100644 index 00000000..d4cb1636 --- /dev/null +++ b/ports/cortex_m0/gnu/example_build/cortexm0_crt0.s @@ -0,0 +1,127 @@ + .global _start + .extern main + + + .section .init, "ax" + .code 16 + .align 2 + .thumb_func + + +_start: + CPSID i + ldr r1, =__stack_end__ + mov sp, r1 + + + /* Copy initialised sections into RAM if required. */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl crt0_memory_copy + ldr r0, =__text_load_start__ + ldr r1, =__text_start__ + ldr r2, =__text_end__ + bl crt0_memory_copy + ldr r0, =__fast_load_start__ + ldr r1, =__fast_start__ + ldr r2, =__fast_end__ + bl crt0_memory_copy + ldr r0, =__ctors_load_start__ + ldr r1, =__ctors_start__ + ldr r2, =__ctors_end__ + bl crt0_memory_copy + ldr r0, =__dtors_load_start__ + ldr r1, =__dtors_start__ + ldr r2, =__dtors_end__ + bl crt0_memory_copy + ldr r0, =__rodata_load_start__ + ldr r1, =__rodata_start__ + ldr r2, =__rodata_end__ + bl crt0_memory_copy + + + /* Zero bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + mov r2, #0 + bl crt0_memory_set + + + /* Setup heap - not recommended for Threadx but here for compatibility reasons */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + sub r1, r1, r0 + mov r2, #0 + str r2, [r0] + add r0, r0, #4 + str r1, [r0] + + + /* constructors in case of using C++ */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +crt0_ctor_loop: + cmp r0, r1 + beq crt0_ctor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b crt0_ctor_loop +crt0_ctor_end: + + + /* Setup call frame for main() */ + mov r0, #0 + mov lr, r0 + mov r12, sp + + +start: + /* Jump to main() */ + mov r0, #0 + mov r1, #0 + ldr r2, =main + blx r2 + /* when main returns, loop forever. */ +crt0_exit_loop: + b crt0_exit_loop + + + + /* Startup helper functions. */ + + +crt0_memory_copy: + cmp r0, r1 + beq memory_copy_done + sub r2, r2, r1 + beq memory_copy_done +memory_copy_loop: + ldrb r3, [r0] + add r0, r0, #1 + strb r3, [r1] + add r1, r1, #1 + sub r2, r2, #1 + bne memory_copy_loop +memory_copy_done: + bx lr + + +crt0_memory_set: + cmp r0, r1 + beq memory_set_done + strb r2, [r0] + add r0, r0, #1 + b crt0_memory_set +memory_set_done: + bx lr + + + /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ + .section .stack, "wa", %nobits + .section .stack_process, "wa", %nobits + .section .heap, "wa", %nobits + \ No newline at end of file diff --git a/ports/cortex_m0/gnu/example_build/libgcc.a b/ports/cortex_m0/gnu/example_build/libgcc.a new file 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z{c%?}b(tTg_SC$q=|G1=;E6pMu%1v#EHy`Ks$<&&%85XY;`N?-9S>|DG<@c}eW3Af4eX0GH)p>yQH-O+VE;E9PyW@$kZiBg zu#9NTV@R%nvVX8_WnDP&Y#u|hjT;SlY0P8D!T1;l{pigV=eFqCU}SjaF(mms_(^w} z5AzsO#lVq#%*Q}uNLXv;J^VL_XA&9S0z4bXe6taVA9f6n= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .vectors is too large to fit in FLASH memory segment"); + + __init_load_start__ = ALIGN(__vectors_end__ , 4); + .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4)) + { + __init_start__ = .; + *(.init .init.*) + } + __init_end__ = __init_start__ + SIZEOF(.init); + + . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .init is too large to fit in FLASH memory segment"); + + __text_load_start__ = ALIGN(__init_end__ , 4); + .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4)) + { + __text_start__ = .; + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) + } + __text_end__ = __text_start__ + SIZEOF(.text); + + . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .text is too large to fit in FLASH memory segment"); + + __dtors_load_start__ = ALIGN(__text_end__ , 4); + .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4)) + { + __dtors_start__ = .; + KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) + } + __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); + + . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .dtors is too large to fit in FLASH memory segment"); + + __ctors_load_start__ = ALIGN(__dtors_end__ , 4); + .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4)) + { + __ctors_start__ = .; + KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) + } + __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); + + . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .ctors is too large to fit in FLASH memory segment"); + + __rodata_load_start__ = ALIGN(__ctors_end__ , 4); + .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4)) + { + __rodata_start__ = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); + + . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .rodata is too large to fit in FLASH memory segment"); + + __fast_load_start__ = ALIGN(__rodata_end__ , 4); + .fast ALIGN(__RAM_segment_start__ , 4) : AT(ALIGN(__rodata_end__ , 4)) + { + __fast_start__ = .; + *(.fast .fast.*) + } + __fast_end__ = __fast_start__ + SIZEOF(.fast); + + __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); + + . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .fast is too large to fit in FLASH memory segment"); + + .fast_run ALIGN(__RAM_segment_start__ , 4) (NOLOAD) : + { + __fast_run_start__ = .; + . = MAX(__fast_run_start__ + SIZEOF(.fast), .); + } + __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); + + . = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .fast_run is too large to fit in RAM memory segment"); + + __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); + .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) + { + __data_start__ = .; + *(.data .data.* .gnu.linkonce.d.*) + } + __data_end__ = __data_start__ + SIZEOF(.data); + + __data_load_end__ = __data_load_start__ + SIZEOF(.data); + + __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); + + . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .data is too large to fit in FLASH memory segment"); + + .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : + { + __data_run_start__ = .; + . = MAX(__data_run_start__ + SIZEOF(.data), .); + } + __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); + + . = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .data_run is too large to fit in RAM memory segment"); + + __bss_load_start__ = ALIGN(__data_run_end__ , 4); + .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4)) + { + __bss_start__ = .; + *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) + } + __bss_end__ = __bss_start__ + SIZEOF(.bss); + + . = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .bss is too large to fit in RAM memory segment"); + + __non_init_load_start__ = ALIGN(__bss_end__ , 4); + .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4)) + { + __non_init_start__ = .; + *(.non_init .non_init.*) + } + __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); + + . = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .non_init is too large to fit in RAM memory segment"); + + __heap_load_start__ = ALIGN(__non_init_end__ , 4); + .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4)) + { + __heap_start__ = .; + *(.heap) + . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); + } + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + . = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .heap is too large to fit in RAM memory segment"); + + __stack_load_start__ = ALIGN(__heap_end__ , 4); + .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4)) + { + __stack_start__ = .; + *(.stack) + . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4); + } + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + . = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack is too large to fit in RAM memory segment"); + + __stack_process_load_start__ = ALIGN(__stack_end__ , 4); + .stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4)) + { + __stack_process_start__ = .; + *(.stack_process) + . = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4); + } + __stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process); + + __RAM_segment_used_end__ = ALIGN(__stack_end__ , 4) + SIZEOF(.stack_process); + + . = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack_process is too large to fit in RAM memory segment"); + +} + diff --git a/ports/cortex_m0/gnu/src/tx_initialize_low_level_sample.S b/ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S old mode 100755 new mode 100644 similarity index 100% rename from ports/cortex_m0/gnu/src/tx_initialize_low_level_sample.S rename to ports/cortex_m0/gnu/example_build/tx_initialize_low_level.S diff --git a/ports/cortex_m0/gnu/src/tx_vector_table_sample.S b/ports/cortex_m0/gnu/example_build/tx_vectors.s similarity index 100% rename from ports/cortex_m0/gnu/src/tx_vector_table_sample.S rename to ports/cortex_m0/gnu/example_build/tx_vectors.s diff --git a/ports/cortex_m0/gnu/readme_threadx.txt b/ports/cortex_m0/gnu/readme_threadx.txt new file mode 100644 index 00000000..3dd7fbf1 --- /dev/null +++ b/ports/cortex_m0/gnu/readme_threadx.txt @@ -0,0 +1,155 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M0 + + Using the GNU Tools + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +gnu (GNU) compiler. At this point you may run the build_threadx.bat batch file. +This will build the ThreadX run-time environment in the "example_build" +directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + + +2. Demonstration System for Cortex-M0 + +The ThreadX demonstration is designed to execute on Cortex-M0 evaluation boards +or on a dedicated simulator. + +Building the demonstration is easy, simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a binary +file that can be downloaded and executed on the a simulator, or downloaded to a board. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-M0 using gnu tools uses the standard GNU +Cortex-M0 reset sequence. From the reset vector the C runtime will be initialized. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M0 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + + Stack Offset Stack Contents + + 0x00 r8 + 0x04 r9 + 0x08 r10 + 0x0C r11 + 0x10 r4 + 0x14 r5 + 0x18 r6 + 0x1C r7 + 0x20 r0 (Hardware stack starts here!!) + 0x24 r1 + 0x28 r2 + 0x2C r3 + 0x30 r12 + 0x34 lr + 0x38 pc + 0x3C xPSR + + +5. Improving Performance + +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the build_threadx.bat file to remove the -g option and enable +all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +6. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M0 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +6.1 Vector Area + +The Cortex-M0 vectors start at the label __tx_vectors or similar. The application may modify +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. + + +6.2 Managed Interrupts + +ISRs can be written completely in C (or assembly language) without any calls to +_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the +ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + + .global your_assembly_isr + .thumb_func +your_assembly_isr: +; VOID your_assembly_isr(VOID) +; { + PUSH {r0, lr} +; +; /* Do interrupt handler work here */ +; /* BL */ + + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + +Note: the Cortex-M0 requires exception handlers to be thumb labels, this implies bit 0 set. +To accomplish this, the declaration of the label has to be preceded by the assembler directive +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically +located in either your runtime startup file or in the tx_initialize_low_level.S file. + + +7. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +05/19/2020 Initial ThreadX 6.0 version for Cortex-M0 using GNU tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m0/gnu/src/tx_thread_stack_build.S b/ports/cortex_m0/gnu/src/tx_thread_stack_build.S index ca66e1d5..85dbba6f 100755 --- a/ports/cortex_m0/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m0/gnu/src/tx_thread_stack_build.S @@ -38,7 +38,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M0/GNU */ -@/* 6.0 */ +@/* 6.0.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,11 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 06-30-2020 William E. Lamie Modified Comment(s), setting */ +@/* R10 to top of stack is not */ +@/* needed. Removed references */ +@/* to stack frame, resulting */ +@/* in version 6.0.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -85,14 +90,14 @@ _tx_thread_stack_build: @ @ Stack Top: @ LR Interrupted LR (LR at time of PENDSV) +@ r8 Initial value for r8 +@ r9 Initial value for r9 +@ r10 Initial value for r10 +@ r11 Initial value for r11 @ r4 Initial value for r4 @ r5 Initial value for r5 @ r6 Initial value for r6 @ r7 Initial value for r7 -@ r8 Initial value for r8 -@ r9 Initial value for r9 -@ r10 (sl) Initial value for r10 (sl) -@ r11 Initial value for r11 @ r0 Initial value for r0 (Hardware stack starts here!!) @ r1 Initial value for r1 @ r2 Initial value for r2 @@ -114,16 +119,14 @@ _tx_thread_stack_build: @ /* Actually build the stack frame. */ @ MOVS r3, #0 @ Build initial register value - STR r3, [r2, #4] @ Store initial r4 - STR r3, [r2, #8] @ Store initial r5 - STR r3, [r2, #12] @ Store initial r6 - STR r3, [r2, #16] @ Store initial r7 - STR r3, [r2, #20] @ Store initial r8 - STR r3, [r2, #24] @ Store initial r9 - LDR r3, [r0, #12] @ Pickup stack starting address - STR r3, [r2, #28] @ Store initial r10 (sl) - MOVS r3, #0 @ Build initial register value - STR r3, [r2, #32] @ Store initial r11 + STR r3, [r2, #4] @ Store initial r8 + STR r3, [r2, #8] @ Store initial r9 + STR r3, [r2, #12] @ Store initial r10 + STR r3, [r2, #16] @ Store initial r11 + STR r3, [r2, #20] @ Store initial r4 + STR r3, [r2, #24] @ Store initial r5 + STR r3, [r2, #28] @ Store initial r6 + STR r3, [r2, #32] @ Store initial r7 @ @ /* Hardware stack follows. */ @ diff --git a/ports/cortex_m0/iar/example_build/azure_rtos.eww b/ports/cortex_m0/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..17e0d329 --- /dev/null +++ b/ports/cortex_m0/iar/example_build/azure_rtos.eww @@ -0,0 +1,13 @@ + + + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\tx.ewp + + + + + diff --git a/ports/cortex_m0/iar/example_build/cstartup_M.s b/ports/cortex_m0/iar/example_build/cstartup_M.s new file mode 100644 index 00000000..a498443c --- /dev/null +++ b/ports/cortex_m0/iar/example_build/cstartup_M.s @@ -0,0 +1,73 @@ + EXTERN __iar_program_start + PUBLIC __vector_table + + SECTION .text:CODE:REORDER(1) + + ;; Keep vector table even if it's not referenced + REQUIRE __vector_table + + THUMB + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD __Reset_Vector + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + + SECTION .text:CODE:REORDER:NOROOT(2) + THUMB +__Reset_Vector: + CPSID i ; Disable interrupts + LDR r0, =__iar_program_start + BX r0 + +NMI_Handler +HardFault_Handler +MemManage_Handler +BusFault_Handler +UsageFault_Handler +SVC_Handler +DebugMon_Handler +PendSV_Handler +SysTick_Handler +Default_Handler +__default_handler + CALL_GRAPH_ROOT __default_handler, "interrupt" + NOCALL __default_handler + B __default_handler + + END diff --git a/ports/cortex_m0/iar/example_build/sample_threadx.c b/ports/cortex_m0/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..95ff3a47 --- /dev/null +++ b/ports/cortex_m0/iar/example_build/sample_threadx.c @@ -0,0 +1,385 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define byte pool memory. */ + +UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE]; + + +/* Define event buffer. */ + +#ifdef TX_ENABLE_EVENT_TRACE +UCHAR trace_buffer[0x10000]; +#endif + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer; + + +#ifdef TX_ENABLE_EVENT_TRACE + tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m0/iar/example_build/sample_threadx.dep b/ports/cortex_m0/iar/example_build/sample_threadx.dep new file mode 100644 index 00000000..1b9970a4 --- /dev/null +++ b/ports/cortex_m0/iar/example_build/sample_threadx.dep @@ -0,0 +1,118 @@ + + + 4 + 90173316 + + Debug + + $PROJ_DIR$\Debug\Obj\sample_threadx.pbd + $PROJ_DIR$\cstartup_M.s + $PROJ_DIR$\sample_threadx.c + $PROJ_DIR$\tx_initialize_low_level.s + $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h + $PROJ_DIR$\Debug\Exe\tx.a + $PROJ_DIR$\Debug\Obj\tx_initialize_low_level.o + $PROJ_DIR$\Debug\Exe\sample_threadx.out + $TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h + $TOOLKIT_DIR$\lib\rt6M_tl.a + $PROJ_DIR$\Debug\Obj\cstartup_M.o + $TOOLKIT_DIR$\inc\c\intrinsics.h + $TOOLKIT_DIR$\inc\c\iccarm_builtin.h + $PROJ_DIR$\Debug\Obj\sample_threadx.o + $TOOLKIT_DIR$\inc\c\DLib_Product_string.h + $PROJ_DIR$\sample_threadx.icf + $PROJ_DIR$\Debug\Obj\sample_threadx.__cstat.et + $TOOLKIT_DIR$\inc\c\iar_intrinsics_common.h + $TOOLKIT_DIR$\lib\shb_l.a + $PROJ_DIR$\..\..\..\..\common\inc\tx_api.h + $TOOLKIT_DIR$\inc\c\yvals.h + $PROJ_DIR$\Debug\List\sample_threadx.map + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $TOOLKIT_DIR$\inc\c\string.h + $PROJ_DIR$\..\inc\tx_port.h + $TOOLKIT_DIR$\inc\c\stdlib.h + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $TOOLKIT_DIR$\inc\c\ycheck.h + $TOOLKIT_DIR$\inc\c\ysizet.h + $TOOLKIT_DIR$\lib\dl6M_tln.a + $TOOLKIT_DIR$\lib\m6M_tl.a + $PROJ_DIR$\Debug\Obj\sample_threadx.xcl + + + [ROOT_NODE] + + + ILINK + 7 21 + + + + + $PROJ_DIR$\cstartup_M.s + + + AARM + 10 + + + + + $PROJ_DIR$\sample_threadx.c + + + ICCARM + 13 + + + __cstat + 16 + + + BICOMP + 31 + + + + + ICCARM + 19 24 25 27 20 26 4 22 28 8 23 14 11 12 17 + + + + + $PROJ_DIR$\tx_initialize_low_level.s + + + AARM + 6 + + + + + $PROJ_DIR$\Debug\Exe\sample_threadx.out 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__ICFEDIT_region_RAM_end__ = 0x1FFFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_size_freemem__ = 0x100000; + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_freemem = mem:[from 0x200000 to 0x300000]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP}; + +place in RAM_region { last section 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+ + + 34050 + 0A0000000A0000006E0000006E000000 + 0000000000000000FE0200001A000000 + 8192 + 0 + 0 + 744 + 0 + + + 1 + + + + 34048 + 34049 + 34050 + 34051 + 34052 + 34053 + 34054 + 34055 + 34056 + 34057 + 34058 + 34059 + 34060 + 34061 + 34062 + 34063 + 34064 + 34065 + + + + 01000000030000000100000000000000000000000100000001000000FFFFFFFF00000000010000000100000000000000280000002800000000000000 + + + + diff --git a/ports/cortex_m0/iar/example_build/settings/sample_threadx.Debug.cspy.bat b/ports/cortex_m0/iar/example_build/settings/sample_threadx.Debug.cspy.bat new file mode 100644 index 00000000..4fed2f46 --- /dev/null +++ b/ports/cortex_m0/iar/example_build/settings/sample_threadx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m0\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m0\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m0\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m0\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports/cortex_m0/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports/cortex_m0/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 new file mode 100644 index 00000000..1fadebf4 --- /dev/null +++ b/ports/cortex_m0/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m0\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m0\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m0\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m0\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} diff --git a/ports/cortex_m0/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports/cortex_m0/iar/example_build/settings/sample_threadx.Debug.driver.xcl new file mode 100644 index 00000000..a7aa9bbc --- /dev/null +++ b/ports/cortex_m0/iar/example_build/settings/sample_threadx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M0" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/cortex_m0/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports/cortex_m0/iar/example_build/settings/sample_threadx.Debug.general.xcl new file mode 100644 index 00000000..aa4f02d3 --- /dev/null +++ b/ports/cortex_m0/iar/example_build/settings/sample_threadx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m0\iar\example_build\Debug\Exe\sample_threadx.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports/cortex_m0/iar/example_build/settings/sample_threadx.crun b/ports/cortex_m0/iar/example_build/settings/sample_threadx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/cortex_m0/iar/example_build/settings/sample_threadx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports/cortex_m0/iar/example_build/settings/sample_threadx.dbgdt b/ports/cortex_m0/iar/example_build/settings/sample_threadx.dbgdt new file mode 100644 index 00000000..26d198e0 --- /dev/null +++ b/ports/cortex_m0/iar/example_build/settings/sample_threadx.dbgdt @@ -0,0 +1,1940 @@ + + + + + + + 3 + 0 + 0 + + + 20 + 1725 + + + 20 + 1293 + 345 + 86 + + 3 + 0 + 0 + + + Debug-Log + + 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--- /dev/null +++ b/ports/cortex_m0/iar/example_build/settings/sample_threadx.reggroups @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/ports/cortex_m0/iar/example_build/settings/tx.Debug.cspy.bat b/ports/cortex_m0/iar/example_build/settings/tx.Debug.cspy.bat new file mode 100644 index 00000000..d76cfad9 --- /dev/null +++ b/ports/cortex_m0/iar/example_build/settings/tx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports/cortex_m0/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports/cortex_m0/iar/example_build/settings/tx.Debug.cspy.ps1 new file mode 100644 index 00000000..1c1ba13b --- /dev/null +++ b/ports/cortex_m0/iar/example_build/settings/tx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} diff --git a/ports/cortex_m0/iar/example_build/settings/tx.Debug.driver.xcl b/ports/cortex_m0/iar/example_build/settings/tx.Debug.driver.xcl new file mode 100644 index 00000000..a7aa9bbc --- /dev/null +++ b/ports/cortex_m0/iar/example_build/settings/tx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M0" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/cortex_m0/iar/example_build/settings/tx.Debug.general.xcl b/ports/cortex_m0/iar/example_build/settings/tx.Debug.general.xcl new file mode 100644 index 00000000..ef6d6dd5 --- /dev/null +++ b/ports/cortex_m0/iar/example_build/settings/tx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armsim2.dll" + +"C:\release\threadx\Debug\Exe\tx.out" + +--plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armbat.dll" + + + + diff --git a/ports/cortex_m0/iar/example_build/settings/tx.crun b/ports/cortex_m0/iar/example_build/settings/tx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/cortex_m0/iar/example_build/settings/tx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports/cortex_m0/iar/example_build/settings/tx.dbgdt b/ports/cortex_m0/iar/example_build/settings/tx.dbgdt new file mode 100644 index 00000000..9e08d965 --- /dev/null +++ b/ports/cortex_m0/iar/example_build/settings/tx.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports/cortex_m0/iar/example_build/settings/tx.dnx b/ports/cortex_m0/iar/example_build/settings/tx.dnx new file mode 100644 index 00000000..25e4c4ba --- /dev/null +++ b/ports/cortex_m0/iar/example_build/settings/tx.dnx @@ -0,0 +1,58 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + 1 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports/cortex_m0/iar/example_build/tx.dep b/ports/cortex_m0/iar/example_build/tx.dep new file mode 100644 index 00000000..f75ac03e --- /dev/null +++ b/ports/cortex_m0/iar/example_build/tx.dep @@ -0,0 +1,11975 @@ + + + 4 + 3548978476 + + Debug + + $PROJ_DIR$\..\..\..\..\common\inc\tx_queue.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_semaphore.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_api.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_event_flags.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_initialize.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_mutex.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_block_pool.h + $PROJ_DIR$\..\inc\tx_port.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_byte_pool.h + $PROJ_DIR$\Debug\Obj\tx_thread_wait_abort.__cstat.et + $PROJ_DIR$\Debug\Obj\tx_mutex_initialize.__cstat.et + $PROJ_DIR$\Debug\Obj\tx_semaphore_ceiling_put.__cstat.et + $PROJ_DIR$\Debug\Obj\tx_thread_terminate.__cstat.et + $PROJ_DIR$\Debug\Obj\tx_thread_system_suspend.__cstat.et + $PROJ_DIR$\Debug\Obj\tx_block_release.o + $PROJ_DIR$\Debug\Obj\tx_queue_send_notify.__cstat.et + $PROJ_DIR$\Debug\Obj\txe_timer_info_get.__cstat.et + $PROJ_DIR$\Debug\Obj\tx_block_pool_prioritize.o + $PROJ_DIR$\Debug\Obj\tx_block_pool_cleanup.o + $PROJ_DIR$\Debug\Obj\tx_initialize_kernel_enter.o + $PROJ_DIR$\Debug\Obj\tx_iar.pbi + $PROJ_DIR$\Debug\Obj\tx_semaphore_put_notify.o + $PROJ_DIR$\Debug\Obj\txe_queue_flush.__cstat.et + $PROJ_DIR$\Debug\Obj\tx_thread_reset.pbi + $PROJ_DIR$\Debug\Obj\txe_queue_delete.__cstat.et + $PROJ_DIR$\Debug\Obj\txe_mutex_prioritize.pbi + $PROJ_DIR$\Debug\Obj\tx_mutex_get.__cstat.et + $PROJ_DIR$\Debug\Obj\tx_thread_stack_analyze.__cstat.et + $PROJ_DIR$\Debug\Obj\txe_byte_allocate.__cstat.et + $PROJ_DIR$\Debug\Obj\tx_timer_expiration_process.o + $PROJ_DIR$\Debug\Obj\tx_timer_delete.__cstat.et + $PROJ_DIR$\Debug\Obj\txe_queue_receive.pbi + $PROJ_DIR$\Debug\Obj\tx_semaphore_info_get.__cstat.et + $PROJ_DIR$\Debug\Obj\tx_timer_info_get.o + $PROJ_DIR$\Debug\Obj\tx_timer_initialize.__cstat.et + $PROJ_DIR$\Debug\Obj\tx_timer_deactivate.__cstat.et + $PROJ_DIR$\Debug\Obj\txe_semaphore_put.pbi + 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@@ -0,0 +1,190 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_timer_interrupt + EXTERN __vector_table + EXTERN _tx_execution_isr_enter + EXTERN _tx_execution_isr_exit +; +; +SYSTEM_CLOCK EQU 50000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) + + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M0/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level: + +; +; /* Ensure that interrupts are disabled. */ +; + CPSID i ; Disable interrupts +; +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer + STR r0, [r2, #0] ; Save first free memory address +; +; /* Enable the cycle count register. */ +; + LDR r0, =0xE0001000 ; Build address of DWT register + LDR r1, [r0] ; Pickup the current value + MOVS r2, #1 + ORRS r1, r1, r2 ; Set the CYCCNTENA bit + STR r1, [r0] ; Enable the cycle count register +; +; /* Setup Vector Table Offset Register. */ +; + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD08 ; Offset to vector base register + ADD r0, r0, r2 ; Build vector base register + LDR r1, =__vector_table ; Pickup address of vector table + STR r1, [r0] ; Set vector table address +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__vector_table ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOVS r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD18 ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD1C ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD20 ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; +; + PUBLIC SysTick_Handler + PUBLIC __tx_SysTickHandler +__tx_SysTickHandler: +SysTick_Handler: +; VOID SysTick_Handler (VOID) +; { +; + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter ; Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif + POP {r0, r1} + MOV lr, r1 + BX lr +; } + END diff --git a/ports/cortex_m0/iar/inc/tx_port.h b/ports/cortex_m0/iar/inc/tx_port.h new file mode 100644 index 00000000..d4501e76 --- /dev/null +++ b/ports/cortex_m0/iar/inc/tx_port.h @@ -0,0 +1,365 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M0/IAR */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M0 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif +#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#define TX_THREAD_EXTENSION_3 +#else +#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long long tx_thread_execution_time_last_start; +#endif + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_IPSR()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA __istate_t interrupt_save; +#define TX_DISABLE {interrupt_save = __get_interrupt_state();__disable_interrupt();}; +#define TX_RESTORE {__set_interrupt_state(interrupt_save);}; + +#define _tx_thread_system_return _tx_thread_system_return_inline + +static void _tx_thread_system_return_inline(void) +{ +__istate_t interrupt_save; + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_IPSR() == 0) + { + interrupt_save = __get_interrupt_state(); + __enable_interrupt(); + __set_interrupt_state(interrupt_save); + } +} + +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/IAR Version 6.0 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + diff --git a/ports/cortex_m0/iar/readme_threadx.txt b/ports/cortex_m0/iar/readme_threadx.txt new file mode 100644 index 00000000..4b6e3f6c --- /dev/null +++ b/ports/cortex_m0/iar/readme_threadx.txt @@ -0,0 +1,158 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M0 + + Using the IAR Tools + +1. Building the ThreadX run-time Library + +Building the ThreadX library is easy. First, open the Azure RTOS workspace +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by +the application. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the IAR +Windows-based Cortex-M0 simulator. + +Building the demonstration is easy; simply make the sample_threadx.ewp project +the "active project" in the IAR Embedded Workbench and select the +"Make" button. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a +binary file that can be downloaded and executed on IAR's Cortex-M0 simulator. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-M0 using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. +In addition, this is where all static and global preset C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. +By default, the vector area is defined at the top of cstartup_M.s, which is +a slightly modified from the base IAR file. + +The _tx_initialize_low_level function inside of tx_initialize_low_level.s +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all +other RAM sections in memory. + + +4. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M0 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 (sl) + 0x20 r11 + 0x24 r0 (Hardware stack starts here!!) + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR + + +5. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the ThreadX library +project to enable various compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +6. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M3 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +6.1 Vector Area + +The Cortex-M3 vectors start at the label __vector_table and is defined in cstartup_M.s. +The application may modify the vector area according to its needs. + + +6.2 Managed Interrupts + +ISRs for Cortex-M using the IAR tools can be written completely in C (or assembly +language) without any calls to _tx_thread_context_save or _tx_thread_context_restore. +These ISRs are allowed access to the ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + PUBLIC your_assembly_isr +your_assembly_isr: + + PUSH {lr} + + ; ISR processing goes here, including any needed function calls. + + POP {r0} + MOV lr, r0 + BX lr + + +7. IAR Thread-safe Library Support + +Thread-safe support for the IAR tools is easily enabled by building the ThreadX library +and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file +should have the following line added (if not already in place): + +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application + +The project options "General Options -> Library Configuration" should also have the +"Enable thread support in library" box selected. + + +8. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX version 6.0.1 for Cortex-M0 using IAR's ARM tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m0/iar/src/tx_iar.c b/ports/cortex_m0/iar/src/tx_iar.c new file mode 100644 index 00000000..dd719370 --- /dev/null +++ b/ports/cortex_m0/iar/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports/cortex_m0/iar/src/tx_thread_context_restore.s b/ports/cortex_m0/iar/src/tx_thread_context_restore.s new file mode 100644 index 00000000..9191562a --- /dev/null +++ b/ports/cortex_m0/iar/src/tx_thread_context_restore.s @@ -0,0 +1,106 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M0/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + PUBLIC _tx_thread_context_restore +_tx_thread_context_restore: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif +; +; /* Preemption has already been addressed - just return! */ +; + POP {r0} + MOV lr, r0 + BX lr +; +;} + END + diff --git a/ports/cortex_m0/iar/src/tx_thread_context_save.s b/ports/cortex_m0/iar/src/tx_thread_context_save.s new file mode 100644 index 00000000..c598b3fe --- /dev/null +++ b/ports/cortex_m0/iar/src/tx_thread_context_save.s @@ -0,0 +1,98 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_execution_isr_enter +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M0/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + PUBLIC _tx_thread_context_save +_tx_thread_context_save: +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is starting. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, r1} ; Recover return address + MOV lr, r1 ; +#endif +; +; /* Context is already saved - just return! */ +; + BX lr +;} + END diff --git a/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..6f870e9b --- /dev/null +++ b/ports/cortex_m0/iar/src/tx_thread_interrupt_control.s @@ -0,0 +1,86 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M0/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_control +_tx_thread_interrupt_control: +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + END + diff --git a/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..32f155cb --- /dev/null +++ b/ports/cortex_m0/iar/src/tx_thread_interrupt_disable.s @@ -0,0 +1,84 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M0/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + END diff --git a/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..cadf01e4 --- /dev/null +++ b/ports/cortex_m0/iar/src/tx_thread_interrupt_restore.s @@ -0,0 +1,83 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M0/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + END diff --git a/ports/cortex_m0/iar/src/tx_thread_schedule.s b/ports/cortex_m0/iar/src/tx_thread_schedule.s new file mode 100644 index 00000000..6b9830cf --- /dev/null +++ b/ports/cortex_m0/iar/src/tx_thread_schedule.s @@ -0,0 +1,272 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M0/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + PUBLIC _tx_thread_schedule +_tx_thread_schedule: +; +; /* This function should only ever be called on Cortex-M0 +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOVS r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + LDR r0, =0x10000000 ; Load PENDSVSET bit + LDR r1, =0xE000ED04 ; Load ICSR address + STR r0, [r1] ; Set PENDSVBIT in ICSR + DSB ; Complete all memory accesses + ISB ; Flush pipeline +; +; /* Wait here for the PendSV to take place. */ +; +__tx_wait_here: + B __tx_wait_here ; Wait for the PendSV to happen +;} +; +; /* Generic context switch-out switch-in handler... */ +; + PUBLIC PendSV_Handler + PUBLIC __tx_PendSVHandler +PendSV_Handler: +__tx_PendSVHandler: +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, r1} ; Recover LR + MOV lr, r1 ; + CPSIE i ; Enable interrupts +#endif + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address + MOVS r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CMP r1,#0 ; If NULL, skip preservation + BEQ __tx_ts_new ; +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer) + SUBS r3, r3, #16 ; Allocate stack space + STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) + MOV r4,r8 ; + MOV r5,r9 ; + MOV r6,r10 ; + MOV r7,r11 ; + SUBS r3, r3, #32 ; Allocate stack space + STM r3!, {r4-r7} ; + SUBS r3, r3, #20 ; Allocate stack space + MOV r5, LR ; + STR r5, [r3] ; Save LR on the stack + STR r3, [r1, #8] ; Save its stack pointer +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r4] ; Pickup current time-slice + CMP r5, #0 ; If not active, skip processing + BEQ __tx_ts_new ; +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + MOVS r5, #0 ; Build clear value + STR r5, [r4] ; Clear time-slice +; +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new: +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CMP r1, #0 ; + BEQ __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore: + LDR r7, [r1, #4] ; Pickup the current thread run count + LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADDS r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0/r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r3 +#endif +; +; /* Restore the thread context and PSP. */ +; + LDR r3, [r1, #8] ; Pickup thread's stack pointer + LDR r5, [r3] ; Recover saved LR + ADDS r3, r3, #4 ; Position past LR + MOV lr, r5 ; Restore LR + LDM r3!,{r4-r7} ; Recover thread's registers (r4-r11) + MOV r11,r7 ; + MOV r10,r6 ; + MOV r9,r5 ; + MOV r8,r4 ; + LDM r3!,{r4-r7} ; + MSR PSP, r3 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait: + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CMP r1, #0 ; If non-NULL, a new thread is ready! + BNE __tx_ts_ready ; +#ifdef TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed +#endif + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready: + LDR r7, =0x08000000 ; Build clear PendSV value + LDR r5, =0xE000ED04 ; Build base NVIC address + STR r7, [r5] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread + + END + diff --git a/ports/cortex_m0/iar/src/tx_thread_stack_build.s b/ports/cortex_m0/iar/src/tx_thread_stack_build.s new file mode 100644 index 00000000..f1073d54 --- /dev/null +++ b/ports/cortex_m0/iar/src/tx_thread_stack_build.s @@ -0,0 +1,145 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M0/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + PUBLIC _tx_thread_stack_build +_tx_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M0 should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + MOVS r3, #0x7 ; + BICS r2, r2, r3 ; Align frame for 8-byte alignment + SUBS r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOVS r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r8 + STR r3, [r2, #8] ; Store initial r9 + STR r3, [r2, #12] ; Store initial r10 + STR r3, [r2, #16] ; Store initial r11 + STR r3, [r2, #20] ; Store initial r4 + STR r3, [r2, #24] ; Store initial r5 + STR r3, [r2, #28] ; Store initial r6 + STR r3, [r2, #32] ; Store initial r7 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + LDR r3, =0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + LDR r3, =0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END + diff --git a/ports/cortex_m0/iar/src/tx_thread_system_return.s b/ports/cortex_m0/iar/src/tx_thread_system_return.s new file mode 100644 index 00000000..3035fd25 --- /dev/null +++ b/ports/cortex_m0/iar/src/tx_thread_system_return.s @@ -0,0 +1,98 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M0/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + PUBLIC _tx_thread_system_return +_tx_thread_system_return??rA: +_tx_thread_system_return: +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + LDR r0, =0x10000000 ; Load PENDSVSET bit + LDR r1, =0xE000ED04 ; Load NVIC base + STR r0, [r1] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context: + BX lr ; Return to caller +;} + END + diff --git a/ports/cortex_m0/iar/src/tx_timer_interrupt.s b/ports/cortex_m0/iar/src/tx_timer_interrupt.s new file mode 100644 index 00000000..a04ccf59 --- /dev/null +++ b/ports/cortex_m0/iar/src/tx_timer_interrupt.s @@ -0,0 +1,271 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_preempt_disable +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M0/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + PUBLIC _tx_timer_interrupt +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADDS r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUBS r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOVS r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOVS r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADDS r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap: +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done: +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired: +; +; + PUSH {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CMP r1, #0 ; + BNE __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + LDR r0, =0xE000ED04 ; Build address of control register + LDR r2, =0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +; +; } +; +__tx_timer_not_ts_expiration: +; + POP {r0, r1} ; Recover lr register (r0 is just there for + MOV lr, r1 ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired: + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + END + diff --git a/ports/cortex_m3/ac5/example_build/build_threadx.bat b/ports/cortex_m3/ac5/example_build/build_threadx.bat new file mode 100644 index 00000000..8fc64ee9 --- /dev/null +++ b/ports/cortex_m3/ac5/example_build/build_threadx.bat @@ -0,0 +1,230 @@ +del tx.a +armasm -g --cpu=cortex-m3 --apcs=interwork tx_initialize_low_level.s +armasm -g --cpu=cortex-m3 --apcs=interwork ../src/tx_thread_stack_build.s +armasm -g --cpu=cortex-m3 --apcs=interwork ../src/tx_thread_schedule.s +armasm -g --cpu=cortex-m3 --apcs=interwork ../src/tx_thread_system_return.s +armasm -g --cpu=cortex-m3 --apcs=interwork ../src/tx_thread_context_save.s +armasm -g --cpu=cortex-m3 --apcs=interwork ../src/tx_thread_context_restore.s +armasm -g --cpu=cortex-m3 --apcs=interwork ../src/tx_thread_interrupt_control.s +armasm -g --cpu=cortex-m3 --apcs=interwork ../src/tx_thread_interrupt_disable.s +armasm -g --cpu=cortex-m3 --apcs=interwork ../src/tx_thread_interrupt_restore.s +armasm -g --cpu=cortex-m3 --apcs=interwork ../src/tx_timer_interrupt.s +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +armcc -g --cpu=cortex-m3 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +armar -r tx.a tx_initialize_low_level.o tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o +armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_m3/ac5/example_build/build_threadx_sample.bat b/ports/cortex_m3/ac5/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..f1f517c4 --- /dev/null +++ b/ports/cortex_m3/ac5/example_build/build_threadx_sample.bat @@ -0,0 +1,4 @@ +armasm -g --cpu=cortex-m3 --apcs=interwork tx_initialize_low_level.s +armcc -c -g --cpu=cortex-m3 -O2 -I../../../../common/inc -I../inc sample_threadx.c +armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --rw-base=0x20000000 --first __tx_vectors --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a + diff --git a/ports/cortex_m3/ac5/example_build/sample_threadx.c b/ports/cortex_m3/ac5/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_m3/ac5/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..3e92d7ca --- /dev/null +++ b/ports/cortex_m3/ac5/example_build/tx_initialize_low_level.s @@ -0,0 +1,259 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT |Image$$RO$$Limit| + IMPORT |Image$$RW$$Base| + IMPORT |Image$$ZI$$Base| + IMPORT |Image$$ZI$$Limit| + IMPORT __tx_PendSVHandler +; +; +SYSTEM_CLOCK EQU 6000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) +; +; +;/* Setup the stack and heap areas. */ +; +STACK_SIZE EQU 0x00000400 +HEAP_SIZE EQU 0x00000000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE STACK_SIZE +__initial_sp + + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE HEAP_SIZE +__heap_limit + + + AREA RESET, CODE, READONLY +; + EXPORT __tx_vectors +__tx_vectors + DCD __initial_sp ; Reset and system stack ptr + DCD Reset_Handler ; Reset goes to startup function + DCD __tx_NMIHandler ; NMI + DCD __tx_BadHandler ; HardFault + DCD 0 ; MemManage + DCD 0 ; BusFault + DCD 0 ; UsageFault + DCD 0 ; 7 + DCD 0 ; 8 + DCD 0 ; 9 + DCD 0 ; 10 + DCD __tx_SVCallHandler ; SVCall + DCD __tx_DBGHandler ; Monitor + DCD 0 ; 13 + DCD __tx_PendSVHandler ; PendSV + DCD __tx_SysTickHandler ; SysTick + DCD __tx_IntHandler ; Int 0 + DCD __tx_IntHandler ; Int 1 + DCD __tx_IntHandler ; Int 2 + DCD __tx_IntHandler ; Int 3 + +; +; + AREA ||.text||, CODE, READONLY + EXPORT Reset_Handler +Reset_Handler + CPSID i + LDR R0, =__main + BX R0 + + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M3/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; /* Disable interrupts during ThreadX initialization. */ +; + CPSID i +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer + LDR r1, =|Image$$ZI$$Limit| ; Build first free address + ADD r1, r1, #4 ; + STR r1, [r0] ; Setup first unused memory pointer +; +; /* Setup Vector Table Offset Register. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =__tx_vectors ; Pickup address of vector table + STR r1, [r0, #0xD08] ; Set vector table address +; +; /* Enable the cycle count register. */ +; +; LDR r0, =0xE0001000 ; Build address of DWT register +; LDR r1, [r0] ; Pickup the current value +; ORR r1, r1, #1 ; Set the CYCCNTENA bit +; STR r1, [r0] ; Enable the cycle count register +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__tx_vectors ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; +; +;/* Define initial heap/stack routine for the ARM RVCT startup code. +; This routine will set the initial stack and heap locations */ +; + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, =HeapMem + LDR R1, =(StackMem + STACK_SIZE) + LDR R2, =(HeapMem + HEAP_SIZE) + LDR R3, =StackMem + BX LR +; +; +;/* Define shells for each of the unused vectors. */ +; + EXPORT __tx_BadHandler +__tx_BadHandler + B __tx_BadHandler + + + EXPORT __tx_SVCallHandler +__tx_SVCallHandler + B __tx_SVCallHandler + + + EXPORT __tx_IntHandler +__tx_IntHandler +; VOID InterruptHandler (VOID) +; { + PUSH {r0, lr} + +; /* Do interrupt handler work here */ +; /* .... */ + + POP {r0, lr} + BX LR +; } + + EXPORT __tx_SysTickHandler +__tx_SysTickHandler +; VOID TimerInterruptHandler (VOID) +; { +; + PUSH {r0, lr} + BL _tx_timer_interrupt + POP {r0, lr} + BX LR +; } + + EXPORT __tx_NMIHandler +__tx_NMIHandler + B __tx_NMIHandler + + EXPORT __tx_DBGHandler +__tx_DBGHandler + B __tx_DBGHandler + + ALIGN + LTORG + END diff --git a/ports/cortex_m3/ac5/inc/tx_port.h b/ports/cortex_m3/ac5/inc/tx_port.h new file mode 100644 index 00000000..259deceb --- /dev/null +++ b/ports/cortex_m3/ac5/inc/tx_port.h @@ -0,0 +1,342 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M3/AC5 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M3 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +#ifndef TX_MISRA_ENABLE + +register unsigned int _ipsr __asm("ipsr"); + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _ipsr) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_DISABLE was_masked = __disable_irq(); +#define TX_RESTORE if (was_masked == 0) __enable_irq(); + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +static void _tx_thread_system_return_inline(void) +{ +unsigned int was_masked; + + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (_ipsr == 0) + { + was_masked = __disable_irq(); + __enable_irq(); + if (was_masked != 0) + __disable_irq(); + } +} +#endif + + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.0 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif diff --git a/ports/cortex_m3/ac5/readme_threadx.txt b/ports/cortex_m3/ac5/readme_threadx.txt new file mode 100644 index 00000000..523279a3 --- /dev/null +++ b/ports/cortex_m3/ac5/readme_threadx.txt @@ -0,0 +1,145 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M3 + + Using ARM Compiler 5 (AC5) + + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the AC5 +development environment. At this point you may run the build_threadx.bat batch +file. This will build the ThreadX run-time environment in the "example_build" +directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the ARM +Windows-based simulator. + +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf +is a binary file that can be downloaded and executed on the ARM simulator. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-M3 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M3 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + + Stack Offset Stack Contents + + 0x00 r4 + 0x04 r5 + 0x08 r6 + 0x0C r7 + 0x10 r8 + 0x14 r9 + 0x18 r10 + 0x1C r11 + 0x20 r0 (Hardware stack starts here!!) + 0x24 r1 + 0x28 r2 + 0x2C r3 + 0x30 r12 + 0x34 lr + 0x38 pc + 0x3C xPSR + + +5. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the ThreadX_Library.Uv2 +project to debugging and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +6. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M3 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +6.1 Vector Area + +The Cortex-M3 vectors start at the label __tx_vectors. The application may modify +the vector area according to its needs. + + +6.2 Managed Interrupts + +ISRs for Cortex-M can be written completely in C (or assembly language) without any +calls to _tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed +access to the ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + EXPORT your_assembly_isr +your_assembly_isr + + PUSH {r0, lr} + + ; ISR processing goes here, including any needed function calls. + + POP {r0, lr} + BX lr + + + +7. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M3 using AC5 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m3/ac5/src/tx_thread_context_restore.s b/ports/cortex_m3/ac5/src/tx_thread_context_restore.s new file mode 100644 index 00000000..eb6c205f --- /dev/null +++ b/ports/cortex_m3/ac5/src/tx_thread_context_restore.s @@ -0,0 +1,94 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M3/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + PUSH {r0,lr} ; Save ISR lr + BL _tx_execution_isr_exit ; Call the ISR exit function + POP {r0,lr} ; Restore ISR lr + ENDIF +; + POP {lr} + BX lr +;} + ALIGN + LTORG + END diff --git a/ports/cortex_m3/ac5/src/tx_thread_context_save.s b/ports/cortex_m3/ac5/src/tx_thread_context_save.s new file mode 100644 index 00000000..4dfc3352 --- /dev/null +++ b/ports/cortex_m3/ac5/src/tx_thread_context_save.s @@ -0,0 +1,94 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M3/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r0, lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, lr} ; Recover ISR lr + ENDIF +; +; /* Return to interrupt processing. */ +; + BX lr ; Return to interrupt processing caller +;} + ALIGN + LTORG + END diff --git a/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..8951fc9d --- /dev/null +++ b/ports/cortex_m3/ac5/src/tx_thread_interrupt_control.s @@ -0,0 +1,80 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M3/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + END + diff --git a/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..d7fd0951 --- /dev/null +++ b/ports/cortex_m3/ac5/src/tx_thread_interrupt_disable.s @@ -0,0 +1,78 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-M3/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + END diff --git a/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..f5c6d3ba --- /dev/null +++ b/ports/cortex_m3/ac5/src/tx_thread_interrupt_restore.s @@ -0,0 +1,77 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M3/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + END diff --git a/ports/cortex_m3/ac5/src/tx_thread_schedule.s b/ports/cortex_m3/ac5/src/tx_thread_schedule.s new file mode 100644 index 00000000..a0cbd6a7 --- /dev/null +++ b/ports/cortex_m3/ac5/src/tx_thread_schedule.s @@ -0,0 +1,248 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + IMPORT _tx_execution_thread_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M3/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Enable the interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + DSB ; Complete all memory accesses + ISB ; Flush pipeline +; +; /* Wait here for the PendSV to take place. */ +; +__tx_wait_here + B __tx_wait_here ; Wait for the PendSV to happen +;} +; +; /* Generic context switching PendSV handler. */ +; + EXPORT __tx_PendSVHandler + EXPORT PendSV_Handler +__tx_PendSVHandler +PendSV_Handler +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR + CPSIE i ; Enable interrupts + ENDIF + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} ; Save its remaining registers + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + STMDB r12!, {LR} ; Save LR on the stack +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r5, [r4] ; Pickup current time-slice + STR r12, [r1, #8] ; Save the thread stack pointer + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + STR r3, [r4] ; Clear time-slice +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore + LDR r7, [r1, #4] ; Pickup the current thread run count + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADD r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0/r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r3 + ENDIF +; +; /* Restore the thread context and PSP. */ +; + LDR r12, [r1, #8] ; Pickup thread's stack pointer + LDMIA r12!, {LR} ; Pickup LR + LDMIA r12!, {r4-r11} ; Recover thread's registers + MSR PSP, r12 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + IF :DEF:TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed + ENDIF + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready + MOV r7, #0x08000000 ; Build clear PendSV value + MOV r8, #0xE000E000 ; Build base NVIC address + STR r7, [r8, #0xD04] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread + + ALIGN + LTORG + END + diff --git a/ports/cortex_m3/ac5/src/tx_thread_stack_build.s b/ports/cortex_m3/ac5/src/tx_thread_stack_build.s new file mode 100644 index 00000000..023e14c4 --- /dev/null +++ b/ports/cortex_m3/ac5/src/tx_thread_stack_build.s @@ -0,0 +1,138 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M3/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M3 should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame for 8-byte alignment + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #24] ; Store initial r9 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. / +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END + diff --git a/ports/cortex_m3/ac5/src/tx_thread_system_return.s b/ports/cortex_m3/ac5/src/tx_thread_system_return.s new file mode 100644 index 00000000..0e88b617 --- /dev/null +++ b/ports/cortex_m3/ac5/src/tx_thread_system_return.s @@ -0,0 +1,91 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M3/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context + BX lr ; Return to caller +;} + END + diff --git a/ports/cortex_m3/ac5/src/tx_timer_interrupt.s b/ports/cortex_m3/ac5/src/tx_timer_interrupt.s new file mode 100644 index 00000000..e9a43031 --- /dev/null +++ b/ports/cortex_m3/ac5/src/tx_timer_interrupt.s @@ -0,0 +1,266 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process + IMPORT _tx_thread_preempt_disable + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M3/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MOV32 r3, _tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + MOV32 r0, 0xE000ED04 ; Build address of control register + MOV32 r2, 0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice +; +; } +; +__tx_timer_not_ts_expiration +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for +; +; } +; +__tx_timer_nothing_expired + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + ALIGN + LTORG + END + diff --git a/ports/cortex_m3/gnu/CMakeLists.txt b/ports/cortex_m3/gnu/CMakeLists.txt index cb3091b9..71e2d4f2 100644 --- a/ports/cortex_m3/gnu/CMakeLists.txt +++ b/ports/cortex_m3/gnu/CMakeLists.txt @@ -9,7 +9,6 @@ target_sources(${PROJECT_NAME} ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S ${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S - # {{END_TARGET_SOURCES}} ) diff --git a/ports/cortex_m3/gnu/example_build/build_threadx.bat b/ports/cortex_m3/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..79f240b0 --- /dev/null +++ b/ports/cortex_m3/gnu/example_build/build_threadx.bat @@ -0,0 +1,229 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g 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-I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c 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../../../../common/src/txe_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_control.o tx_initialize_low_level.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_m3/gnu/example_build/build_threadx_sample.bat b/ports/cortex_m3/gnu/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..cc93371f --- /dev/null +++ b/ports/cortex_m3/gnu/example_build/build_threadx_sample.bat @@ -0,0 +1,7 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb tx_simulator_startup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb cortexm3_crt0.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m3 -mthumb -I../../../../common/inc -I../inc sample_threadx.c +arm-none-eabi-ld -A cortex-m3 -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm3_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libc.a -o sample_threadx.out -M > sample_threadx.map + + diff --git a/ports/cortex_m3/gnu/example_build/cortexm3_crt0.s b/ports/cortex_m3/gnu/example_build/cortexm3_crt0.s new file mode 100644 index 00000000..d4cb1636 --- /dev/null +++ b/ports/cortex_m3/gnu/example_build/cortexm3_crt0.s @@ -0,0 +1,127 @@ + .global _start + .extern main + + + .section .init, "ax" + .code 16 + .align 2 + .thumb_func + + +_start: + CPSID i + ldr r1, =__stack_end__ + mov sp, r1 + + + /* Copy initialised sections into RAM if required. */ + ldr r0, =__data_load_start__ + ldr r1, =__data_start__ + ldr r2, =__data_end__ + bl crt0_memory_copy + ldr r0, =__text_load_start__ + ldr r1, =__text_start__ + ldr r2, =__text_end__ + bl crt0_memory_copy + ldr r0, =__fast_load_start__ + ldr r1, =__fast_start__ + ldr r2, =__fast_end__ + bl crt0_memory_copy + ldr r0, =__ctors_load_start__ + ldr r1, =__ctors_start__ + ldr r2, =__ctors_end__ + bl crt0_memory_copy + ldr r0, =__dtors_load_start__ + ldr r1, =__dtors_start__ + ldr r2, =__dtors_end__ + bl crt0_memory_copy + ldr r0, =__rodata_load_start__ + ldr r1, =__rodata_start__ + ldr r2, =__rodata_end__ + bl crt0_memory_copy + + + /* Zero bss. */ + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + mov r2, #0 + bl crt0_memory_set + + + /* Setup heap - not recommended for Threadx but here for compatibility reasons */ + ldr r0, = __heap_start__ + ldr r1, = __heap_end__ + sub r1, r1, r0 + mov r2, #0 + str r2, [r0] + add r0, r0, #4 + str r1, [r0] + + + /* constructors in case of using C++ */ + ldr r0, =__ctors_start__ + ldr r1, =__ctors_end__ +crt0_ctor_loop: + cmp r0, r1 + beq crt0_ctor_end + ldr r2, [r0] + add r0, #4 + push {r0-r1} + blx r2 + pop {r0-r1} + b crt0_ctor_loop +crt0_ctor_end: + + + /* Setup call frame for main() */ + mov r0, #0 + mov lr, r0 + mov r12, sp + + +start: + /* Jump to main() */ + mov r0, #0 + mov r1, #0 + ldr r2, =main + blx r2 + /* when main returns, loop forever. */ +crt0_exit_loop: + b crt0_exit_loop + + + + /* Startup helper functions. */ + + +crt0_memory_copy: + cmp r0, r1 + beq memory_copy_done + sub r2, r2, r1 + beq memory_copy_done +memory_copy_loop: + ldrb r3, [r0] + add r0, r0, #1 + strb r3, [r1] + add r1, r1, #1 + sub r2, r2, #1 + bne memory_copy_loop +memory_copy_done: + bx lr + + +crt0_memory_set: + cmp r0, r1 + beq memory_set_done + strb r2, [r0] + add r0, r0, #1 + b crt0_memory_set +memory_set_done: + bx lr + + + /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */ + .section .stack, "wa", %nobits + .section .stack_process, "wa", %nobits + .section .heap, "wa", %nobits + \ No newline at end of file diff --git a/ports/cortex_m3/gnu/example_build/libc.a b/ports/cortex_m3/gnu/example_build/libc.a new file mode 100644 index 0000000000000000000000000000000000000000..6c1567d15e3b2f049d1acd9038ac4fcd28005c18 GIT binary patch literal 743432 zcmeFa4V+v>nJ-*D-90mz48sgW7(#%~mxd%HJxK@?WN|W?bP}9=7zPQ-wWsGR-O@AD z&PP6wca4IIifa^BBe2RUcQ1O8JJDocV8LV;ek*sy-3g)s;%?UE8WgT3%EE}e7MD6n80S2=hxL$&r?s;sj5@YQ%`-IbEaRG8t6=4UbQfm4-JbhzW9=cMGZ?A z$6|3EW&g)w4GovX8#TSXN~v&Msms2pRMSSKT7It7n%^q50r>mhu2k|>rMjAxN}r|F zb-z-oAN0ZNmD=)*QrADI)SrIAb07OFrNn*WKBdHc`nyVr`?G&k>ee%q`cj`#cYIo@ zub!{e*T1IJJ-<-uTklnB_xqIk>&umT;2)IQ_Z6icS)|nWZdd9DR~Yw1LMghRAPwEK zuNwESC^Ow5f_zlYY+b4{B`E{k}{xH|LqaRSA@L4KU{)`G$eOrZ2A5ft)x2Vur zzfhs6KUbj(rmE1)8WnoS>nb$w3F8*NszQFZoSD{zmu3ee>fYL7VYgJbHs&O?Ps_e{!Dyv^$-1)Do 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b/ports/cortex_m3/gnu/example_build/sample_threadx.c @@ -0,0 +1,370 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m3/gnu/example_build/sample_threadx.ld b/ports/cortex_m3/gnu/example_build/sample_threadx.ld new file mode 100644 index 00000000..28f203fd --- /dev/null +++ b/ports/cortex_m3/gnu/example_build/sample_threadx.ld @@ -0,0 +1,206 @@ +MEMORY +{ + UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0 + CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000 + AHB_Peripherals (wx) : ORIGIN = 0x50000000, LENGTH = 0x00200000 + APB1_Peripherals (wx) : ORIGIN = 0x40080000, LENGTH = 0x00080000 + APB0_Peripherals (wx) : ORIGIN = 0x40000000, LENGTH = 0x00080000 + GPIO (wx) : ORIGIN = 0x2009c000, LENGTH = 0x00004000 + AHBSRAM1 (wx) : ORIGIN = 0x20080000, LENGTH = 0x00004000 + AHBSRAM0 (wx) : ORIGIN = 0x2007c000, LENGTH = 0x00004000 + RAM (wx) : ORIGIN = 0x10000000, LENGTH = 0x00008000 + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 +} + + +SECTIONS +{ + __CM3_System_Control_Space_segment_start__ = 0xe000e000; + __CM3_System_Control_Space_segment_end__ = 0xe000f000; + __AHB_Peripherals_segment_start__ = 0x50000000; + __AHB_Peripherals_segment_end__ = 0x50200000; + __APB1_Peripherals_segment_start__ = 0x40080000; + __APB1_Peripherals_segment_end__ = 0x40100000; + __APB0_Peripherals_segment_start__ = 0x40000000; + __APB0_Peripherals_segment_end__ = 0x40080000; + __GPIO_segment_start__ = 0x2009c000; + __GPIO_segment_end__ = 0x200a0000; + __AHBSRAM1_segment_start__ = 0x20080000; + __AHBSRAM1_segment_end__ = 0x20084000; + __AHBSRAM0_segment_start__ = 0x2007c000; + __AHBSRAM0_segment_end__ = 0x20080000; + __RAM_segment_start__ = 0x10000000; + __RAM_segment_end__ = 0x10008000; + __FLASH_segment_start__ = 0x00000000; + __FLASH_segment_end__ = 0x00080000; + + __STACKSIZE__ = 1024; + __STACKSIZE_PROCESS__ = 0; + __STACKSIZE_IRQ__ = 0; + __STACKSIZE_FIQ__ = 0; + __STACKSIZE_SVC__ = 0; + __STACKSIZE_ABT__ = 0; + __STACKSIZE_UND__ = 0; + __HEAPSIZE__ = 128; + + __vectors_load_start__ = __FLASH_segment_start__; + .vectors __FLASH_segment_start__ : AT(__FLASH_segment_start__) + { + __vectors_start__ = .; + *(.vectors .vectors.*) + } + __vectors_end__ = __vectors_start__ + SIZEOF(.vectors); + + . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .vectors is too large to fit in FLASH memory segment"); + + __init_load_start__ = ALIGN(__vectors_end__ , 4); + .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4)) + { + __init_start__ = .; + *(.init .init.*) + } + __init_end__ = __init_start__ + SIZEOF(.init); + + . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .init is too large to fit in FLASH memory segment"); + + __text_load_start__ = ALIGN(__init_end__ , 4); + .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4)) + { + __text_start__ = .; + *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table) + } + __text_end__ = __text_start__ + SIZEOF(.text); + + . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .text is too large to fit in FLASH memory segment"); + + __dtors_load_start__ = ALIGN(__text_end__ , 4); + .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4)) + { + __dtors_start__ = .; + KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) + } + __dtors_end__ = __dtors_start__ + SIZEOF(.dtors); + + . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .dtors is too large to fit in FLASH memory segment"); + + __ctors_load_start__ = ALIGN(__dtors_end__ , 4); + .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4)) + { + __ctors_start__ = .; + KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) + } + __ctors_end__ = __ctors_start__ + SIZEOF(.ctors); + + . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .ctors is too large to fit in FLASH memory segment"); + + __rodata_load_start__ = ALIGN(__ctors_end__ , 4); + .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4)) + { + __rodata_start__ = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + __rodata_end__ = __rodata_start__ + SIZEOF(.rodata); + + . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .rodata is too large to fit in FLASH memory segment"); + + __fast_load_start__ = ALIGN(__rodata_end__ , 4); + .fast ALIGN(__RAM_segment_start__ , 4) : AT(ALIGN(__rodata_end__ , 4)) + { + __fast_start__ = .; + *(.fast .fast.*) + } + __fast_end__ = __fast_start__ + SIZEOF(.fast); + + __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast); + + . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .fast is too large to fit in FLASH memory segment"); + + .fast_run ALIGN(__RAM_segment_start__ , 4) (NOLOAD) : + { + __fast_run_start__ = .; + . = MAX(__fast_run_start__ + SIZEOF(.fast), .); + } + __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run); + + . = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .fast_run is too large to fit in RAM memory segment"); + + __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4); + .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4)) + { + __data_start__ = .; + *(.data .data.* .gnu.linkonce.d.*) + } + __data_end__ = __data_start__ + SIZEOF(.data); + + __data_load_end__ = __data_load_start__ + SIZEOF(.data); + + __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data); + + . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .data is too large to fit in FLASH memory segment"); + + .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) : + { + __data_run_start__ = .; + . = MAX(__data_run_start__ + SIZEOF(.data), .); + } + __data_run_end__ = __data_run_start__ + SIZEOF(.data_run); + + . = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .data_run is too large to fit in RAM memory segment"); + + __bss_load_start__ = ALIGN(__data_run_end__ , 4); + .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4)) + { + __bss_start__ = .; + *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) + } + __bss_end__ = __bss_start__ + SIZEOF(.bss); + + . = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .bss is too large to fit in RAM memory segment"); + + __non_init_load_start__ = ALIGN(__bss_end__ , 4); + .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4)) + { + __non_init_start__ = .; + *(.non_init .non_init.*) + } + __non_init_end__ = __non_init_start__ + SIZEOF(.non_init); + + . = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .non_init is too large to fit in RAM memory segment"); + + __heap_load_start__ = ALIGN(__non_init_end__ , 4); + .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4)) + { + __heap_start__ = .; + *(.heap) + . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4); + } + __heap_end__ = __heap_start__ + SIZEOF(.heap); + + . = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .heap is too large to fit in RAM memory segment"); + + __stack_load_start__ = ALIGN(__heap_end__ , 4); + .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4)) + { + __stack_start__ = .; + *(.stack) + . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4); + } + __stack_end__ = __stack_start__ + SIZEOF(.stack); + + . = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack is too large to fit in RAM memory segment"); + + __stack_process_load_start__ = ALIGN(__stack_end__ , 4); + .stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4)) + { + __stack_process_start__ = .; + *(.stack_process) + . = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4); + } + __stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process); + + __RAM_segment_used_end__ = ALIGN(__stack_end__ , 4) + SIZEOF(.stack_process); + + . = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack_process is too large to fit in RAM memory segment"); + +} + diff --git a/ports/cortex_m3/gnu/src/tx_initialize_low_level_sample.S b/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S similarity index 95% rename from ports/cortex_m3/gnu/src/tx_initialize_low_level_sample.S rename to ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S index bfa6e423..3eaf5731 100644 --- a/ports/cortex_m3/gnu/src/tx_initialize_low_level_sample.S +++ b/ports/cortex_m3/gnu/example_build/tx_initialize_low_level.S @@ -59,7 +59,7 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* FUNCTION RELEASE */ @/* */ @/* _tx_initialize_low_level Cortex-M3/GNU */ -@/* 6.0 */ +@/* 6.0.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -93,6 +93,9 @@ SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 06-30-2020 William E. Lamie Modified Comment(s), fixed */ +@/* GNU assembly comment, */ +@/* resulting in version 6.0.1 */ @/* */ @/**************************************************************************/ @VOID _tx_initialize_low_level(VOID) @@ -191,14 +194,14 @@ __tx_IntHandler: @ { PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_enter ; Call the ISR enter function + BL _tx_execution_isr_enter @ Call the ISR enter function #endif @ /* Do interrupt handler work here */ @ /* BL .... */ #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_exit ; Call the ISR exit function + BL _tx_execution_isr_exit @ Call the ISR exit function #endif POP {r0, lr} BX LR @@ -216,11 +219,11 @@ SysTick_Handler: @ PUSH {r0, lr} #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_enter ; Call the ISR enter function + BL _tx_execution_isr_enter @ Call the ISR enter function #endif BL _tx_timer_interrupt #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY - BL _tx_execution_isr_exit ; Call the ISR exit function + BL _tx_execution_isr_exit @ Call the ISR exit function #endif POP {r0, lr} BX LR diff --git a/ports/cortex_m3/gnu/src/tx_vector_table_sample.S b/ports/cortex_m3/gnu/example_build/tx_simulator_startup.s similarity index 100% rename from ports/cortex_m3/gnu/src/tx_vector_table_sample.S rename to ports/cortex_m3/gnu/example_build/tx_simulator_startup.s diff --git a/ports/cortex_m3/gnu/readme_threadx.txt b/ports/cortex_m3/gnu/readme_threadx.txt new file mode 100644 index 00000000..92c2045d --- /dev/null +++ b/ports/cortex_m3/gnu/readme_threadx.txt @@ -0,0 +1,153 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M3 + + Using the GNU Tools + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +gnu (GNU) compiler. At this point you may run the build_threadx.bat batch file. +This will build the ThreadX run-time environment in the "example_build" +directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + + +2. Demonstration System for Cortex-M3 + +The ThreadX demonstration is designed to execute on Cortex-M3 evaluation boards +or on a dedicated simulator. + +Building the demonstration is easy, simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a binary +file that can be downloaded and executed on the a simulator, or downloaded to a board. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-M3 using gnu tools uses the standard GNU +Cortex-M3 reset sequence. From the reset vector the C runtime will be initialized. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M3 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + + Stack Offset Stack Contents + + 0x00 r4 + 0x04 r5 + 0x08 r6 + 0x0C r7 + 0x10 r8 + 0x14 r9 + 0x18 r10 + 0x1C r11 + 0x20 r0 (Hardware stack starts here!!) + 0x24 r1 + 0x28 r2 + 0x2C r3 + 0x30 r12 + 0x34 lr + 0x38 pc + 0x3C xPSR + + +5. Improving Performance + +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the build_threadx.bat file to remove the -g option and enable +all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +6. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M3 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +6.1 Vector Area + +The Cortex-M3 vectors start at the label __tx_vectors or similar. The application may modify +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. + + +6.2 Managed Interrupts + +ISRs can be written completely in C (or assembly language) without any calls to +_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the +ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + + .global your_assembly_isr + .thumb_func +your_assembly_isr: +; VOID your_assembly_isr(VOID) +; { + PUSH {r0, lr} +; +; /* Do interrupt handler work here */ +; /* BL */ + + POP {r0, lr} + BX lr +; } + +Note: the Cortex-M3 requires exception handlers to be thumb labels, this implies bit 0 set. +To accomplish this, the declaration of the label has to be preceded by the assembler directive +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically +located in either your runtime startup file or in the tx_initialize_low_level.S file. + + +7. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +05/19/2020 Initial ThreadX 6.0 version for Cortex-M3 using GNU tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m3/gnu/src/tx_thread_stack_build.S b/ports/cortex_m3/gnu/src/tx_thread_stack_build.S index bec56d45..35d6e2ca 100644 --- a/ports/cortex_m3/gnu/src/tx_thread_stack_build.S +++ b/ports/cortex_m3/gnu/src/tx_thread_stack_build.S @@ -38,7 +38,7 @@ @/* FUNCTION RELEASE */ @/* */ @/* _tx_thread_stack_build Cortex-M3/GNU */ -@/* 6.0 */ +@/* 6.0.1 */ @/* AUTHOR */ @/* */ @/* William E. Lamie, Microsoft Corporation */ @@ -71,6 +71,11 @@ @/* DATE NAME DESCRIPTION */ @/* */ @/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +@/* 06-30-2020 William E. Lamie Modified Comment(s), setting */ +@/* R10 to top of stack is not */ +@/* needed. Removed references */ +@/* to stack frame, resulting */ +@/* in version 6.0.1 */ @/* */ @/**************************************************************************/ @VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -91,7 +96,7 @@ _tx_thread_stack_build: @ r7 Initial value for r7 @ r8 Initial value for r8 @ r9 Initial value for r9 -@ r10 (sl) Initial value for r10 (sl) +@ r10 Initial value for r10 @ r11 Initial value for r11 @ r0 Initial value for r0 (Hardware stack starts here!!) @ r1 Initial value for r1 @@ -119,9 +124,7 @@ _tx_thread_stack_build: STR r3, [r2, #16] @ Store initial r7 STR r3, [r2, #20] @ Store initial r8 STR r3, [r2, #24] @ Store initial r9 - LDR r3, [r0, #12] @ Pickup stack starting address - STR r3, [r2, #28] @ Store initial r10 (sl) - MOV r3, #0 @ Build initial register value + STR r3, [r2, #28] @ Store initial r10 STR r3, [r2, #32] @ Store initial r11 @ @ /* Hardware stack follows. */ diff --git a/ports/cortex_m3/iar/example_build/azure_rtos.eww b/ports/cortex_m3/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..17e0d329 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/azure_rtos.eww @@ -0,0 +1,13 @@ + + + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\tx.ewp + + + + + diff --git a/ports/cortex_m3/iar/example_build/cstartup_M.s b/ports/cortex_m3/iar/example_build/cstartup_M.s new file mode 100644 index 00000000..75d9369b --- /dev/null +++ b/ports/cortex_m3/iar/example_build/cstartup_M.s @@ -0,0 +1,73 @@ + EXTERN __iar_program_start + PUBLIC __vector_table + + SECTION .text:CODE:REORDER(1) + + ;; Keep vector table even if it's not referenced + REQUIRE __vector_table + + THUMB + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD __Reset_Vector + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB +__Reset_Vector: + CPSID i ; Disable interrupts + B __iar_program_start + + +NMI_Handler +HardFault_Handler +MemManage_Handler +BusFault_Handler +UsageFault_Handler +SVC_Handler +DebugMon_Handler +PendSV_Handler +SysTick_Handler +Default_Handler +__default_handler + CALL_GRAPH_ROOT __default_handler, "interrupt" + NOCALL __default_handler + B __default_handler + + END diff --git a/ports/cortex_m3/iar/example_build/sample_threadx.c b/ports/cortex_m3/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..c67d75d0 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/sample_threadx.c @@ -0,0 +1,385 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define byte pool memory. */ + +UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE]; + + +/* Define event buffer. */ + +#ifdef TX_ENABLE_EVENT_TRACE +UCHAR trace_buffer[0x10000]; +#endif + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + +#ifdef TX_ENABLE_EVENT_TRACE + tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m3/iar/example_build/sample_threadx.dep b/ports/cortex_m3/iar/example_build/sample_threadx.dep new file mode 100644 index 00000000..55bb03a6 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/sample_threadx.dep @@ -0,0 +1,128 @@ + + + 4 + 3533065436 + + Debug + + $PROJ_DIR$\Debug\Obj\sample_threadx.__cstat.et + $TOOLKIT_DIR$\inc\c\iccarm_builtin.h + $TOOLKIT_DIR$\inc\c\stdlib.h + $TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h + $TOOLKIT_DIR$\inc\c\ycheck.h + $TOOLKIT_DIR$\inc\c\intrinsics.h + $PROJ_DIR$\tx_initialize_low_level.s + $PROJ_DIR$\Debug\Obj\tx_initialize_low_level.o + $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h + $PROJ_DIR$\..\inc\tx_port.h + $PROJ_DIR$\..\src\tx_initialize_low_level.s + $TOOLKIT_DIR$\inc\c\DLib_Product.h + $TOOLKIT_DIR$\inc\c\DLib_Defaults.h + $PROJ_DIR$\Debug\Obj\sample_threadx.xcl + $PROJ_DIR$\Debug\Obj\sample_threadx.o + $PROJ_DIR$\Debug\Exe\sample_threadx.out + $TOOLKIT_DIR$\inc\c\string.h + $TOOLKIT_DIR$\inc\c\yvals.h + $TOOLKIT_DIR$\inc\c\DLib_Product_string.h + $PROJ_DIR$\sample_threadx.icf + $TOOLKIT_DIR$\inc\c\iar_intrinsics_common.h + $TOOLKIT_DIR$\inc\c\ysizet.h + $PROJ_DIR$\Debug\Obj\sample_threadx.pbd + $PROJ_DIR$\Debug\Obj\cstartup_M.o + $PROJ_DIR$\..\..\..\..\common\inc\tx_api.h + $PROJ_DIR$\cstartup_M.s + $PROJ_DIR$\sample_threadx.c + $PROJ_DIR$\Debug\Exe\tx.a + $TOOLKIT_DIR$\lib\shb_l.a + $TOOLKIT_DIR$\lib\rt7M_tl.a + $TOOLKIT_DIR$\lib\dl7M_tln.a + $PROJ_DIR$\Debug\List\sample_threadx.map + $TOOLKIT_DIR$\lib\m7M_tl.a + + + [ROOT_NODE] + + + ILINK + 15 31 + + + + + $PROJ_DIR$\tx_initialize_low_level.s + + + AARM + 7 + + + + + $PROJ_DIR$\..\src\tx_initialize_low_level.s + + + AARM + 7 + + + + + $PROJ_DIR$\Debug\Exe\sample_threadx.out + + + ILINK + 31 + + + + + ILINK + 19 23 14 27 7 28 29 32 30 + + + + + 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__ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x80; +define symbol __ICFEDIT_region_ROM_end__ = 0x1FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x100000; +define symbol __ICFEDIT_region_RAM_end__ = 0x1FFFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_size_freemem__ = 0x100000; + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_freemem = mem:[from 0x200000 to 0x300000]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP}; + +place in RAM_region { last section FREE_MEM}; \ No newline at end of file diff --git a/ports/cortex_m3/iar/example_build/settings/azure_rtos.wsdt b/ports/cortex_m3/iar/example_build/settings/azure_rtos.wsdt new file mode 100644 index 00000000..97c89213 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/azure_rtos.wsdt @@ -0,0 +1,535 @@ + + + + + sample_threadx/Debug + tx/Debug + + sample_threadx + 1 + + + + + 21 + 2518 + 2 + + 0 + -1 + + + + 34001 + 0 + + + + + 57600 + 57601 + 57603 + 33024 + 0 + 57607 + 0 + 57635 + 57634 + 57637 + 0 + 57643 + 57644 + 0 + 33090 + 33057 + 57636 + 57640 + 57641 + 33026 + 33065 + 33063 + 33064 + 33053 + 33054 + 0 + 33035 + 33036 + 34399 + 0 + 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+ + + 34050 + 0A0000000A0000006E0000006E000000 + 0000000000000000FE0200001A000000 + 8192 + 0 + 0 + 744 + 0 + + + 1 + + + + 34048 + 34049 + 34050 + 34051 + 34052 + 34053 + 34054 + 34055 + 34056 + 34057 + 34058 + 34059 + 34060 + 34061 + 34062 + 34063 + 34064 + 34065 + + + + 01000000030000000100000000000000000000000100000001000000FFFFFFFF00000000010000000100000000000000280000002800000000000000 + + + + diff --git a/ports/cortex_m3/iar/example_build/settings/sample_threadx.Debug.cspy.bat b/ports/cortex_m3/iar/example_build/settings/sample_threadx.Debug.cspy.bat new file mode 100644 index 00000000..00208544 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/sample_threadx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_m3\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_m3\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_m3\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_m3\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports/cortex_m3/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports/cortex_m3/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 new file mode 100644 index 00000000..2894c7df --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_m3\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_m3\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_m3\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_m3\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} diff --git a/ports/cortex_m3/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports/cortex_m3/iar/example_build/settings/sample_threadx.Debug.driver.xcl new file mode 100644 index 00000000..11a77ea1 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/sample_threadx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M3" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/cortex_m3/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports/cortex_m3/iar/example_build/settings/sample_threadx.Debug.general.xcl new file mode 100644 index 00000000..ce257367 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/sample_threadx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_m3\iar\example_build\Debug\Exe\sample_threadx.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports/cortex_m3/iar/example_build/settings/sample_threadx.crun b/ports/cortex_m3/iar/example_build/settings/sample_threadx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/sample_threadx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports/cortex_m3/iar/example_build/settings/sample_threadx.dbgdt b/ports/cortex_m3/iar/example_build/settings/sample_threadx.dbgdt new file mode 100644 index 00000000..aebcbbc8 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/sample_threadx.dbgdt @@ -0,0 +1,1623 @@ + + + + + + + 3 + 0 + 0 + + + Build + + + + 20 + 1725 + + + 20 + 1293 + 345 + 86 + + 3 + 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+ + + 34123 + 0A0000000A0000006E0000006E000000 + 0000000000000000150300001A000000 + 8192 + 0 + 0 + 32767 + 0 + + + 1 + + + + diff --git a/ports/cortex_m3/iar/example_build/settings/sample_threadx.dnx b/ports/cortex_m3/iar/example_build/settings/sample_threadx.dnx new file mode 100644 index 00000000..0fa79328 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/sample_threadx.dnx @@ -0,0 +1,99 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + 1 + + + 1618778298 + + + 0 + 0 + 0 + + + 0 + + + _ 0 + _ 0 + + + 0 + + + 0 + 1 + 0 + 0 + + + 0 + + + 1 + + + _ 0 + _ "" + + + _ 0 + _ "" + _ 0 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + _ 0 9999 0 9999 1 0 0 100 0 1 "SysTick 1 0x3C" + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports/cortex_m3/iar/example_build/settings/tx.Debug.cspy.bat b/ports/cortex_m3/iar/example_build/settings/tx.Debug.cspy.bat new file mode 100644 index 00000000..d76cfad9 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/tx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports/cortex_m3/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports/cortex_m3/iar/example_build/settings/tx.Debug.cspy.ps1 new file mode 100644 index 00000000..1c1ba13b --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/tx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} diff --git a/ports/cortex_m3/iar/example_build/settings/tx.Debug.driver.xcl b/ports/cortex_m3/iar/example_build/settings/tx.Debug.driver.xcl new file mode 100644 index 00000000..11a77ea1 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/tx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M3" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports/cortex_m3/iar/example_build/settings/tx.Debug.general.xcl b/ports/cortex_m3/iar/example_build/settings/tx.Debug.general.xcl new file mode 100644 index 00000000..ef6d6dd5 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/tx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armsim2.dll" + +"C:\release\threadx\Debug\Exe\tx.out" + +--plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armbat.dll" + + + + diff --git a/ports/cortex_m3/iar/example_build/settings/tx.crun b/ports/cortex_m3/iar/example_build/settings/tx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/tx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports/cortex_m3/iar/example_build/settings/tx.dbgdt b/ports/cortex_m3/iar/example_build/settings/tx.dbgdt new file mode 100644 index 00000000..9e08d965 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/tx.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports/cortex_m3/iar/example_build/settings/tx.dnx b/ports/cortex_m3/iar/example_build/settings/tx.dnx new file mode 100644 index 00000000..25e4c4ba --- /dev/null +++ b/ports/cortex_m3/iar/example_build/settings/tx.dnx @@ -0,0 +1,58 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + 1 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports/cortex_m3/iar/example_build/tx.dep b/ports/cortex_m3/iar/example_build/tx.dep new file mode 100644 index 00000000..1bcebb99 --- /dev/null +++ b/ports/cortex_m3/iar/example_build/tx.dep @@ -0,0 +1,9780 @@ + + + 4 + 1228130052 + + Debug + + $PROJ_DIR$\..\..\..\..\common\inc\tx_api.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_block_pool.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_byte_pool.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_event_flags.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_initialize.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_trace.h + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_search.c + $PROJ_DIR$\..\..\..\..\common\inc\tx_mutex.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_queue.h + $PROJ_DIR$\..\..\..\..\common\inc\tx_thread.h + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_cleanup.c + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_info_get.c + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_release.c + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_create.c + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_create.c + $PROJ_DIR$\..\inc\tx_port.h + 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$PROJ_DIR$\..\..\..\..\common\src\tx_thread_initialize.c + + + $PROJ_DIR$\..\src\tx_thread_interrupt_control.s + + + $PROJ_DIR$\..\src\tx_thread_interrupt_disable.s + + + $PROJ_DIR$\..\src\tx_thread_interrupt_restore.s + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_preemption_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_priority_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_relinquish.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_reset.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_resume.c + + + $PROJ_DIR$\..\src\tx_thread_schedule.s + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_shell_entry.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_sleep.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_analyze.c + + + $PROJ_DIR$\..\src\tx_thread_stack_build.s + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_error_handler.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_error_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_suspend.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_preempt_check.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_resume.c + + + $PROJ_DIR$\..\src\tx_thread_system_return.s + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_suspend.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_terminate.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_time_slice.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_time_slice_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_timeout.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_thread_wait_abort.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_time_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_time_set.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_activate.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_timer_change.c + + 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$PROJ_DIR$\..\..\..\..\common\src\txe_byte_allocate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_byte_release.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_put.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_flush.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_front_send.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_receive.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_ceiling_put.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_entry_exit_notify.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_preemption_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_priority_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_relinquish.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_reset.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_resume.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_suspend.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_terminate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_time_slice_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c + + + diff --git a/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..ab6a346c --- /dev/null +++ b/ports/cortex_m3/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,181 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_timer_interrupt + EXTERN __vector_table + EXTERN _tx_execution_isr_enter + EXTERN _tx_execution_isr_exit +; +; +SYSTEM_CLOCK EQU 7200000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) + + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level: +; +; /* Ensure that interrupts are disabled. */ +; + CPSID i ; Disable interrupts +; +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer + STR r0, [r2, #0] ; Save first free memory address +; +; /* Enable the cycle count register. */ +; + LDR r0, =0xE0001000 ; Build address of DWT register + LDR r1, [r0] ; Pickup the current value + ORR r1, r1, #1 ; Set the CYCCNTENA bit + STR r1, [r0] ; Enable the cycle count register +; +; /* Setup Vector Table Offset Register. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =__vector_table ; Pickup address of vector table + STR r1, [r0, #0xD08] ; Set vector table address +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__vector_table ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; +; +;/* Define SystTick Handler. */ +; + + PUBLIC SysTick_Handler + PUBLIC __tx_SysTickHandler +SysTick_Handler: +__tx_SysTickHandler: +; VOID SysTickHandler (VOID) +; { +; + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter ; Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif + POP {r0, lr} + BX LR +; } + + END + + diff --git a/ports/cortex_m3/iar/inc/tx_port.h b/ports/cortex_m3/iar/inc/tx_port.h new file mode 100644 index 00000000..538187c6 --- /dev/null +++ b/ports/cortex_m3/iar/inc/tx_port.h @@ -0,0 +1,375 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M3/IAR */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef signed int INT; +typedef unsigned int UINT; +typedef signed long LONG; +typedef unsigned long ULONG; +typedef signed short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M3 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024UL) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif +#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#define TX_THREAD_EXTENSION_3 +#else +#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long long tx_thread_execution_time_last_start; +#endif + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_IPSR()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT)__CLZ(__RBIT((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA __istate_t interrupt_save; +#define TX_DISABLE {interrupt_save = __get_interrupt_state();__disable_interrupt();}; +#define TX_RESTORE {__set_interrupt_state(interrupt_save);}; + +#define _tx_thread_system_return _tx_thread_system_return_inline + +static void _tx_thread_system_return_inline(void) +{ +__istate_t interrupt_save; + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_IPSR() == 0) + { + interrupt_save = __get_interrupt_state(); + __enable_interrupt(); + __set_interrupt_state(interrupt_save); + } +} + +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/IAR Version 6.0 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + + + diff --git a/ports/cortex_m3/iar/readme_threadx.txt b/ports/cortex_m3/iar/readme_threadx.txt new file mode 100644 index 00000000..22a46139 --- /dev/null +++ b/ports/cortex_m3/iar/readme_threadx.txt @@ -0,0 +1,158 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M3 + + Using the IAR Tools + +1. Building the ThreadX run-time Library + +Building the ThreadX library is easy. First, open the Azure RTOS workspace +azure_rtos.eww. Next, make the TX project the "active project" in the +IAR Embedded Workbench and select the "Make" button. You should observe +assembly and compilation of a series of ThreadX source files. This +results in the ThreadX run-time library file tx.a, which is needed by +the application. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the IAR +Windows-based Cortex-M3 simulator. + +Building the demonstration is easy; simply make the sample_threadx.ewp project +the "active project" in the IAR Embedded Workbench and select the +"Make" button. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.out is a +binary file that can be downloaded and executed on IAR's Cortex-M3 simulator. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-M3 using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. +In addition, this is where all static and global preset C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. +By default, the vector area is defined at the top of cstartup_M.s, which is +a slightly modified from the base IAR file. + +The _tx_initialize_low_level function inside of tx_initialize_low_level.s +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all +other RAM sections in memory. + + +4. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M3 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 (sl) + 0x20 r11 + 0x24 r0 (Hardware stack starts here!!) + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR + + +5. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the ThreadX library +project to enable various compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +6. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M3 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +6.1 Vector Area + +The Cortex-M3 vectors start at the label __vector_table and is defined in cstartup_M.s. +The application may modify the vector area according to its needs. + + +6.2 Managed Interrupts + +ISRs for Cortex-M using the IAR tools can be written completely in C (or assembly +language) without any calls to _tx_thread_context_save or _tx_thread_context_restore. +These ISRs are allowed access to the ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + PUBLIC your_assembly_isr +your_assembly_isr: + + PUSH {lr} + + ; ISR processing goes here, including any needed function calls. + + POP {lr} + BX lr + + + +7. IAR Thread-safe Library Support + +Thread-safe support for the IAR tools is easily enabled by building the ThreadX library +and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file +should have the following line added (if not already in place): + +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application + +The project options "General Options -> Library Configuration" should also have the +"Enable thread support in library" box selected. + + +8. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX version 6.0.1 for Cortex-M3 using IAR's ARM tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m3/iar/src/tx_iar.c b/ports/cortex_m3/iar/src/tx_iar.c new file mode 100644 index 00000000..dd719370 --- /dev/null +++ b/ports/cortex_m3/iar/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports/cortex_m3/iar/src/tx_misra.s b/ports/cortex_m3/iar/src/tx_misra.s new file mode 100644 index 00000000..62559a05 --- /dev/null +++ b/ports/cortex_m3/iar/src/tx_misra.s @@ -0,0 +1,1003 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX MISRA Compliance */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + #define SHT_PROGBITS 0x1 + + EXTERN __aeabi_memset + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_interrupt_disable + EXTERN _tx_thread_interrupt_restore + EXTERN _tx_thread_stack_analyze + EXTERN _tx_thread_stack_error_handler + EXTERN _tx_thread_system_state +#ifdef TX_ENABLE_EVENT_TRACE + EXTERN _tx_trace_buffer_current_ptr + EXTERN _tx_trace_buffer_end_ptr + EXTERN _tx_trace_buffer_start_ptr + EXTERN _tx_trace_event_enable_bits + EXTERN _tx_trace_full_notify_function + EXTERN _tx_trace_header_ptr +#endif + + PUBLIC _tx_misra_always_true + PUBLIC _tx_misra_block_pool_to_uchar_pointer_convert + PUBLIC _tx_misra_byte_pool_to_uchar_pointer_convert + PUBLIC _tx_misra_char_to_uchar_pointer_convert + PUBLIC _tx_misra_const_char_to_char_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_entry_to_uchar_pointer_convert +#endif + PUBLIC _tx_misra_indirect_void_to_uchar_pointer_convert + PUBLIC _tx_misra_memset + PUBLIC _tx_misra_message_copy +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_object_to_uchar_pointer_convert +#endif + PUBLIC _tx_misra_pointer_to_ulong_convert + PUBLIC _tx_misra_status_get + PUBLIC _tx_misra_thread_stack_check +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_time_stamp_get +#endif + PUBLIC _tx_misra_timer_indirect_to_void_pointer_convert + PUBLIC _tx_misra_timer_pointer_add + PUBLIC _tx_misra_timer_pointer_dif +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_trace_event_insert +#endif + PUBLIC _tx_misra_uchar_pointer_add + PUBLIC _tx_misra_uchar_pointer_dif + PUBLIC _tx_misra_uchar_pointer_sub + PUBLIC _tx_misra_uchar_to_align_type_pointer_convert + PUBLIC _tx_misra_uchar_to_block_pool_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_uchar_to_entry_pointer_convert + PUBLIC _tx_misra_uchar_to_header_pointer_convert +#endif + PUBLIC _tx_misra_uchar_to_indirect_byte_pool_pointer_convert + PUBLIC _tx_misra_uchar_to_indirect_uchar_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_uchar_to_object_pointer_convert +#endif + PUBLIC _tx_misra_uchar_to_void_pointer_convert + PUBLIC _tx_misra_ulong_pointer_add + PUBLIC _tx_misra_ulong_pointer_dif + PUBLIC _tx_misra_ulong_pointer_sub + PUBLIC _tx_misra_ulong_to_pointer_convert + PUBLIC _tx_misra_ulong_to_thread_pointer_convert + PUBLIC _tx_misra_user_timer_pointer_get + PUBLIC _tx_misra_void_to_block_pool_pointer_convert + PUBLIC _tx_misra_void_to_byte_pool_pointer_convert + PUBLIC _tx_misra_void_to_event_flags_pointer_convert + PUBLIC _tx_misra_void_to_indirect_uchar_pointer_convert + PUBLIC _tx_misra_void_to_mutex_pointer_convert + PUBLIC _tx_misra_void_to_queue_pointer_convert + PUBLIC _tx_misra_void_to_semaphore_pointer_convert + PUBLIC _tx_misra_void_to_thread_pointer_convert + PUBLIC _tx_misra_void_to_uchar_pointer_convert + PUBLIC _tx_misra_void_to_ulong_pointer_convert + PUBLIC _tx_misra_ipsr_get + PUBLIC _tx_version_id + + + SECTION `.data`:DATA:REORDER:NOROOT(2) + DATA +// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0 MISRA C Compliant *"; +_tx_version_id: + DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H + DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H + DC8 39H, 36H, 2DH, 32H, 30H, 31H, 38H, 20H + DC8 45H, 78H, 70H, 72H, 65H, 73H, 73H, 20H + DC8 4CH, 6FH, 67H, 69H, 63H, 20H, 49H, 6EH + DC8 63H, 2EH, 20H, 2AH, 20H, 54H, 68H, 72H + DC8 65H, 61H, 64H, 58H, 20H, 35H, 2EH, 38H + DC8 20H, 4DH, 49H, 53H, 52H, 41H, 20H, 43H + DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H + DC8 6EH, 74H, 20H, 2AH, 0 + DC8 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_memset: + PUSH {R4,LR} + MOVS R4,R0 + MOVS R0,R2 + MOVS R2,R1 + MOVS R1,R0 + MOVS R0,R4 + BL __aeabi_memset + POP {R4,PC} ;; return + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_add: + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_sub: + RSBS R1,R1,#+0 + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_dif: + SUBS R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_pointer_to_ulong_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_sub: + MVNS R2,#+3 + MULS R1,R2,R1 + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_to_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, */ +/** UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_message_copy: + PUSH {R4,R5} + LDR R3,[R0, #+0] + LDR R4,[R1, #+0] + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + CMP R2,#+2 + BCC.N ??_tx_misra_message_copy_0 + SUBS R2,R2,#+1 + B.N ??_tx_misra_message_copy_1 +??_tx_misra_message_copy_2: + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + SUBS R2,R2,#+1 +??_tx_misra_message_copy_1: + CMP R2,#+0 + BNE.N ??_tx_misra_message_copy_2 +??_tx_misra_message_copy_0: + STR R3,[R0, #+0] + STR R4,[R1, #+0] + POP {R4,R5} + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, */ +/** TX_TIMER_INTERNAL **ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL */ +/** **ptr1, ULONG size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL */ +/** *internal_timer, TX_TIMER **user_timer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_user_timer_pointer_get: + ADDS R2,R0,#+8 + SUBS R2,R2,R0 + RSBS R2,R2,#+0 + ADD R0,R0,R2 + STR R0,[R1, #+0] + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, */ +/** VOID **highest_stack); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_thread_stack_check: + PUSH {R3-R5,LR} + MOVS R4,R0 + MOVS R5,R1 + BL _tx_thread_interrupt_disable + CMP R4,#+0 + BEQ.N ??_tx_misra_thread_stack_check_0 + LDR R1,[R4, #+0] + LDR.N R2,??DataTable2 ;; 0x54485244 + CMP R1,R2 + BNE.N ??_tx_misra_thread_stack_check_0 + LDR R1,[R4, #+8] + LDR R2,[R5, #+0] + CMP R1,R2 + BCS.N ??_tx_misra_thread_stack_check_1 + LDR R1,[R4, #+8] + STR R1,[R5, #+0] +??_tx_misra_thread_stack_check_1: + LDR R1,[R4, #+12] + LDR R1,[R1, #+0] + CMP R1,#-269488145 + BNE.N ??_tx_misra_thread_stack_check_2 + LDR R1,[R4, #+16] + LDR R1,[R1, #+1] + CMP R1,#-269488145 + BNE.N ??_tx_misra_thread_stack_check_2 + LDR R1,[R5, #+0] + LDR R2,[R4, #+12] + CMP R1,R2 + BCS.N ??_tx_misra_thread_stack_check_3 +??_tx_misra_thread_stack_check_2: + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_error_handler + BL _tx_thread_interrupt_disable +??_tx_misra_thread_stack_check_3: + LDR R1,[R5, #+0] + LDR R1,[R1, #-4] + CMP R1,#-269488145 + BEQ.N ??_tx_misra_thread_stack_check_0 + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_analyze + BL _tx_thread_interrupt_disable +??_tx_misra_thread_stack_check_0: + BL _tx_thread_interrupt_restore + POP {R0,R4,R5,PC} ;; return + +#ifdef TX_ENABLE_EVENT_TRACE + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_trace_event_insert(ULONG event_id, */ +/** VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */ +/** ULONG info_field_4, ULONG filter, ULONG time_stamp); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_trace_event_insert: + PUSH {R3-R7,LR} + LDR.N R4,??DataTable2_1 + LDR R4,[R4, #+0] + CMP R4,#+0 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R5,??DataTable2_2 + LDR R5,[R5, #+0] + LDR R6,[SP, #+28] + TST R5,R6 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R5,??DataTable2_3 + LDR R5,[R5, #+0] + LDR.N R6,??DataTable2_4 + LDR R6,[R6, #+0] + CMP R5,#+0 + BNE.N ??_tx_misra_trace_event_insert_1 + LDR R5,[R6, #+44] + LDR R7,[R6, #+60] + LSLS R7,R7,#+16 + ORRS R7,R7,#0x80000000 + ORRS R5,R7,R5 + B.N ??_tx_misra_trace_event_insert_2 +??_tx_misra_trace_event_insert_1: + CMP R5,#-252645136 + BCS.N ??_tx_misra_trace_event_insert_3 + MOVS R5,R6 + MOVS R6,#-1 + B.N ??_tx_misra_trace_event_insert_2 +??_tx_misra_trace_event_insert_3: + MOVS R6,#-252645136 + MOVS R5,#+0 +??_tx_misra_trace_event_insert_2: + STR R6,[R4, #+0] + STR R5,[R4, #+4] + STR R0,[R4, #+8] + LDR R0,[SP, #+32] + STR R0,[R4, #+12] + STR R1,[R4, #+16] + STR R2,[R4, #+20] + STR R3,[R4, #+24] + LDR R0,[SP, #+24] + STR R0,[R4, #+28] + ADDS R4,R4,#+32 + LDR.N R0,??DataTable2_5 + LDR R0,[R0, #+0] + CMP R4,R0 + BCC.N ??_tx_misra_trace_event_insert_4 + LDR.N R0,??DataTable2_6 + LDR R4,[R0, #+0] + LDR.N R0,??DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] + LDR.N R0,??DataTable2_8 + LDR R0,[R0, #+0] + CMP R0,#+0 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + LDR.N R1,??DataTable2_8 + LDR R1,[R1, #+0] + BLX R1 + B.N ??_tx_misra_trace_event_insert_0 +??_tx_misra_trace_event_insert_4: + LDR.N R0,??DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] +??_tx_misra_trace_event_insert_0: + POP {R0,R4-R7,PC} ;; return + + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_1: + DC32 _tx_trace_buffer_current_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_2: + DC32 _tx_trace_event_enable_bits + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_5: + DC32 _tx_trace_buffer_end_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_6: + DC32 _tx_trace_buffer_start_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_7: + DC32 _tx_trace_header_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_8: + DC32 _tx_trace_full_notify_function + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_time_stamp_get(VOID); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_time_stamp_get: + MOVS R0,#+0 + BX LR ;; return + +#endif + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2: + DC32 0x54485244 + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_3: + DC32 _tx_thread_system_state + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_4: + DC32 _tx_thread_current_ptr + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_always_true(void); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_always_true: + MOVS R0,#+1 + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_indirect_void_to_uchar_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_indirect_uchar_pointer_convert: + BX LR ;; return + + +/***********************************************************************************/ +/***********************************************************************************/ +/** */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** */ +/***********************************************************************************/ +/***********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_block_pool_to_uchar_pointer_convert: + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_block_pool_pointer_convert: + BX LR ;; return + + +/*****************************************************************************/ +/*****************************************************************************/ +/** */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************/ +/*****************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_uchar_pointer_convert: + BX LR ;; return + + +/************************************************************************************/ +/************************************************************************************/ +/** */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** */ +/************************************************************************************/ +/************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_block_pool_pointer_convert: + BX LR ;; return + + +/**************************************************************************************/ +/**************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** */ +/**************************************************************************************/ +/**************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_indirect_uchar_pointer_convert: + BX LR ;; return + + +/*****************************************************************************************/ +/*****************************************************************************************/ +/** */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************************/ +/*****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_byte_pool_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_byte_pool_to_uchar_pointer_convert: + BX LR ;; return + + +/*****************************************************************************************/ +/*****************************************************************************************/ +/** */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** */ +/*****************************************************************************************/ +/*****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_align_type_pointer_convert: + BX LR ;; return + + +/****************************************************************************************************/ +/****************************************************************************************************/ +/** */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** */ +/****************************************************************************************************/ +/****************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: + BX LR ;; return + + +/**************************************************************************************************/ +/**************************************************************************************************/ +/** */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** */ +/**************************************************************************************************/ +/**************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_event_flags_pointer_convert: + BX LR ;; return + + +/*****************************************************************************/ +/*****************************************************************************/ +/** */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************/ +/*****************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_ulong_pointer_convert: + BX LR ;; return + + +/********************************************************************************/ +/********************************************************************************/ +/** */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** */ +/********************************************************************************/ +/********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_mutex_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_status_get(UINT status); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_status_get: + MOVS R0,#+0 + BX LR ;; return + + +/********************************************************************************/ +/********************************************************************************/ +/** */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** */ +/********************************************************************************/ +/********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_queue_pointer_convert: + BX LR ;; return + + +/****************************************************************************************/ +/****************************************************************************************/ +/** */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** */ +/****************************************************************************************/ +/****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_semaphore_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_void_pointer_convert: + BX LR ;; return + + +/*********************************************************************************/ +/*********************************************************************************/ +/** */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** */ +/*********************************************************************************/ +/*********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_to_thread_pointer_convert: + BX LR ;; return + + +/***************************************************************************************************/ +/***************************************************************************************************/ +/** */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** */ +/***************************************************************************************************/ +/***************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_indirect_to_void_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_const_char_to_char_pointer_convert: + BX LR ;; return + + +/**********************************************************************************/ +/**********************************************************************************/ +/** */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** */ +/**********************************************************************************/ +/**********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_thread_pointer_convert: + BX LR ;; return + + +#ifdef TX_ENABLE_EVENT_TRACE + +/************************************************************************************************/ +/************************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** */ +/************************************************************************************************/ +/************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_object_to_uchar_pointer_convert: + BX LR ;; return + + +/************************************************************************************************/ +/************************************************************************************************/ +/** */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** */ +/************************************************************************************************/ +/************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_object_pointer_convert: + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_header_pointer_convert: + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_entry_pointer_convert: + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_entry_to_uchar_pointer_convert: + BX LR ;; return +#endif + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_char_to_uchar_pointer_convert: + BX LR ;; return + + +***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_ipsr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ipsr_get: + MRS R0, IPSR + BX LR ;; return + + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA + DC32 0 + + END diff --git a/ports/cortex_m3/iar/src/tx_thread_context_restore.s b/ports/cortex_m3/iar/src/tx_thread_context_restore.s new file mode 100644 index 00000000..e3e42286 --- /dev/null +++ b/ports/cortex_m3/iar/src/tx_thread_context_restore.s @@ -0,0 +1,97 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_execution_isr_exit +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* [_tx_execution_isr_exit] Execution profiling ISR exit */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + PUBLIC _tx_thread_context_restore +_tx_thread_context_restore: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + PUSH {r0,lr} ; Save ISR lr + BL _tx_execution_isr_exit ; Call the ISR exit function + POP {r0,lr} ; Restore ISR lr +#endif +; + POP {lr} + BX lr +; +;} + END diff --git a/ports/cortex_m3/iar/src/tx_thread_context_save.s b/ports/cortex_m3/iar/src/tx_thread_context_save.s new file mode 100644 index 00000000..49e11d68 --- /dev/null +++ b/ports/cortex_m3/iar/src/tx_thread_context_save.s @@ -0,0 +1,96 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_execution_isr_enter +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* [_tx_execution_isr_enter] Execution profiling ISR enter */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + PUBLIC _tx_thread_context_save +_tx_thread_context_save: +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is starting. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, lr} ; Recover return address +#endif +; +; /* Context is already saved - just return! */ +; + BX lr +;} + END + diff --git a/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..d956fd6d --- /dev/null +++ b/ports/cortex_m3/iar/src/tx_thread_interrupt_control.s @@ -0,0 +1,86 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_control +_tx_thread_interrupt_control: +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + END + diff --git a/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..38a2083d --- /dev/null +++ b/ports/cortex_m3/iar/src/tx_thread_interrupt_disable.s @@ -0,0 +1,84 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + END diff --git a/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..356c8aac --- /dev/null +++ b/ports/cortex_m3/iar/src/tx_thread_interrupt_restore.s @@ -0,0 +1,83 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + END diff --git a/ports/cortex_m3/iar/src/tx_thread_schedule.s b/ports/cortex_m3/iar/src/tx_thread_schedule.s new file mode 100644 index 00000000..aa5f7764 --- /dev/null +++ b/ports/cortex_m3/iar/src/tx_thread_schedule.s @@ -0,0 +1,250 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_preempt_disable +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + PUBLIC _tx_thread_schedule +_tx_thread_schedule: +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + DSB ; Complete all memory accesses + ISB ; Flush pipeline +; +; /* Wait here for the PendSV to take place. */ +; +__tx_wait_here: + B __tx_wait_here ; Wait for the PendSV to happen +;} +; +; /* Generic context PendSV handler. */ +; + PUBLIC PendSV_Handler + PUBLIC __tx_PendSVHandler +PendSV_Handler: +__tx_PendSVHandler: +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR + CPSIE i ; Enable interrupts +#endif + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} ; Save its remaining registers + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + STMDB r12!, {LR} ; Save LR on the stack +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r5, [r4] ; Pickup current time-slice + STR r12, [r1, #8] ; Save the thread stack pointer + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + STR r3, [r4] ; Clear time-slice +; +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new: +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore: + LDR r7, [r1, #4] ; Pickup the current thread run count + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADD r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0/r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r3 +#endif +; +; /* Restore the thread context and PSP. */ +; + LDR r12, [r1, #8] ; Pickup thread's stack pointer + LDMIA r12!, {LR} ; Pickup LR + LDMIA r12!, {r4-r11} ; Recover thread's registers + MSR PSP, r12 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait: + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed +#endif + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready: + MOV r7, #0x08000000 ; Build clear PendSV value + MOV r8, #0xE000E000 ; Build base NVIC address + STR r7, [r8, #0xD04] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread +;} + END + diff --git a/ports/cortex_m3/iar/src/tx_thread_stack_build.s b/ports/cortex_m3/iar/src/tx_thread_stack_build.s new file mode 100644 index 00000000..96526cc1 --- /dev/null +++ b/ports/cortex_m3/iar/src/tx_thread_stack_build.s @@ -0,0 +1,144 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + PUBLIC _tx_thread_stack_build +_tx_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame for 8-byte alignment + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #24] ; Store initial r9 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. / +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END + diff --git a/ports/cortex_m3/iar/src/tx_thread_system_return.s b/ports/cortex_m3/iar/src/tx_thread_system_return.s new file mode 100644 index 00000000..fa0ef7a3 --- /dev/null +++ b/ports/cortex_m3/iar/src/tx_thread_system_return.s @@ -0,0 +1,98 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + PUBLIC _tx_thread_system_return +_tx_thread_system_return??rA: +_tx_thread_system_return: +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context: + BX lr ; Return to caller +;} + END + diff --git a/ports/cortex_m3/iar/src/tx_timer_interrupt.s b/ports/cortex_m3/iar/src/tx_timer_interrupt.s new file mode 100644 index 00000000..94af5d87 --- /dev/null +++ b/ports/cortex_m3/iar/src/tx_timer_interrupt.s @@ -0,0 +1,268 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_preempt_disable +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* expiration functions are called. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + PUBLIC _tx_timer_interrupt +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MOV32 r3, _tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap: +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done: +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired: +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + MOV32 r0, 0xE000ED04 ; Build address of control register + MOV32 r2, 0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +; +; } +; +__tx_timer_not_ts_expiration: +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired: + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + END + diff --git a/ports/cortex_m3/keil/example_build/ThreadX_Demo.uvopt b/ports/cortex_m3/keil/example_build/ThreadX_Demo.uvopt new file mode 100644 index 00000000..5fcedc85 --- /dev/null +++ b/ports/cortex_m3/keil/example_build/ThreadX_Demo.uvopt @@ -0,0 +1,300 @@ + + + + 1.0 + +

### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ThreadX_Demo + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + -1 + + + + + + + + + + + + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T5F + + + 0 + UL2CM3 + -UV0289BJE -O14 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_16 -FS00 -FL04000 + + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group + 0 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + .\tx_initialize_low_level.s + tx_initialize_low_level.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\sample_threadx.c + sample_threadx.c + 0 + 0 + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 56 + 12 + 1633 + 671 + + + + + + + Library_Group + 0 + 0 + 0 + 0 + + 2 + 3 + 4 + 0 + 0 + 0 + .\ThreadX_Library.lib + ThreadX_Library.lib + 0 + 0 + + + + diff --git a/ports/cortex_m3/keil/example_build/ThreadX_Demo.uvproj b/ports/cortex_m3/keil/example_build/ThreadX_Demo.uvproj new file mode 100644 index 00000000..3847190f --- /dev/null +++ b/ports/cortex_m3/keil/example_build/ThreadX_Demo.uvproj @@ -0,0 +1,573 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + ThreadX_Demo + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + Cortex-M3 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE + + + + 4349 + + + + + + + + + + + + 0 + 0 + + + + Luminary\ + Luminary\ + + 0 + 0 + 0 + 0 + 1 + + .\ + ThreadX_Demo + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + -1 + + + + + + + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 0 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ../inc;../../../../common/inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x00000000 + 0x20000000 + + + + + --first __tx_vectors --entry=__main + + + + + + + + Source Group + + + 0 + 1 + 1 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 0 + + + + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + tx_initialize_low_level.s + 2 + .\tx_initialize_low_level.s + + + 2 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 2 + 2 + 1 + 2 + 2 + 2 + 2 + 2 + 0 + + + + + + + + + + + + sample_threadx.c + 1 + .\sample_threadx.c + + + + + Library_Group + + + ThreadX_Library.lib + 4 + .\ThreadX_Library.lib + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m3/keil/example_build/ThreadX_Library.plg b/ports/cortex_m3/keil/example_build/ThreadX_Library.plg new file mode 100644 index 00000000..6b87c5cf --- /dev/null +++ b/ports/cortex_m3/keil/example_build/ThreadX_Library.plg @@ -0,0 +1,9 @@ + + +
+
µVision Build Log

+
Project:

+C:\threadx\cortex-m3\keil\ThreadX_Library.uvproj
+Project File Date:  07/19/2012
+
+
Output:

diff --git a/ports/cortex_m3/keil/example_build/ThreadX_Library.uvopt b/ports/cortex_m3/keil/example_build/ThreadX_Library.uvopt
new file mode 100644
index 00000000..ac554f54
--- /dev/null
+++ b/ports/cortex_m3/keil/example_build/ThreadX_Library.uvopt
@@ -0,0 +1,2664 @@
+
+
+
+  1.0
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### uVision Project, (C) Keil Software

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diff --git a/ports/cortex_m3/keil/example_build/ThreadX_Library.uvproj b/ports/cortex_m3/keil/example_build/ThreadX_Library.uvproj
new file mode 100644
index 00000000..222522d0
--- /dev/null
+++ b/ports/cortex_m3/keil/example_build/ThreadX_Library.uvproj
@@ -0,0 +1,1550 @@
+
+
+
+  1.1
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+  
### uVision Project, (C) Keil Software

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+            
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+            
+            
+              tx_initialize_high_level.c
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+              ..\..\..\..\common\src\tx_initialize_high_level.c
+            
+            
+              tx_initialize_kernel_enter.c
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+            
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+            
+              tx_mutex_priority_change.c
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+            
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+            
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+            
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+            
+              tx_queue_delete.c
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+            
+              tx_queue_flush.c
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+              tx_queue_front_send.c
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+            
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+            
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+            
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+            
+              tx_queue_send_notify.c
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+            
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+            
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+              tx_thread_identify.c
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+            
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+            
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+            
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+            
+              tx_thread_priority_change.c
+              1
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+            
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+            
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+            
+              tx_thread_resume.c
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+            
+              tx_thread_shell_entry.c
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+            
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+            
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+            
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+            
+            
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+            
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+              1
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+            
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+            
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+            
+              tx_thread_terminate.c
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+            
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+            
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+            
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+            
+            
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+            
+            
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+            
+            
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+            
+            
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+            
+            
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+              1
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+            
+            
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+              1
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+            
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+              1
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+            
+            
+              tx_trace_user_event_insert.c
+              1
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+            
+            
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+            
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+            
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+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
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+              1
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+            
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+              1
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+            
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+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
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+            
+            
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+              1
+              ..\..\..\..\common\src\txe_event_flags_set.c
+            
+            
+              txe_event_flags_set_notify.c
+              1
+              ..\..\..\..\common\src\txe_event_flags_set_notify.c
+            
+            
+              txe_mutex_create.c
+              1
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+            
+            
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+              1
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+            
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+            
+            
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+            
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+              1
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+            
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+              1
+              ..\..\..\..\common\src\txe_mutex_put.c
+            
+            
+              txe_queue_create.c
+              1
+              ..\..\..\..\common\src\txe_queue_create.c
+            
+            
+              txe_queue_delete.c
+              1
+              ..\..\..\..\common\src\txe_queue_delete.c
+            
+            
+              txe_queue_flush.c
+              1
+              ..\..\..\..\common\src\txe_queue_flush.c
+            
+            
+              txe_queue_front_send.c
+              1
+              ..\..\..\..\common\src\txe_queue_front_send.c
+            
+            
+              txe_queue_info_get.c
+              1
+              ..\..\..\..\common\src\txe_queue_info_get.c
+            
+            
+              txe_queue_prioritize.c
+              1
+              ..\..\..\..\common\src\txe_queue_prioritize.c
+            
+            
+              txe_queue_receive.c
+              1
+              ..\..\..\..\common\src\txe_queue_receive.c
+            
+            
+              txe_queue_send.c
+              1
+              ..\..\..\..\common\src\txe_queue_send.c
+            
+            
+              txe_queue_send_notify.c
+              1
+              ..\..\..\..\common\src\txe_queue_send_notify.c
+            
+            
+              txe_semaphore_ceiling_put.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_ceiling_put.c
+            
+            
+              txe_semaphore_create.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_create.c
+            
+            
+              txe_semaphore_delete.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_delete.c
+            
+            
+              txe_semaphore_get.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_get.c
+            
+            
+              txe_semaphore_info_get.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_info_get.c
+            
+            
+              txe_semaphore_prioritize.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_prioritize.c
+            
+            
+              txe_semaphore_put.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_put.c
+            
+            
+              txe_semaphore_put_notify.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_put_notify.c
+            
+            
+              txe_thread_create.c
+              1
+              ..\..\..\..\common\src\txe_thread_create.c
+            
+            
+              txe_thread_delete.c
+              1
+              ..\..\..\..\common\src\txe_thread_delete.c
+            
+            
+              txe_thread_entry_exit_notify.c
+              1
+              ..\..\..\..\common\src\txe_thread_entry_exit_notify.c
+            
+            
+              txe_thread_info_get.c
+              1
+              ..\..\..\..\common\src\txe_thread_info_get.c
+            
+            
+              txe_thread_preemption_change.c
+              1
+              ..\..\..\..\common\src\txe_thread_preemption_change.c
+            
+            
+              txe_thread_priority_change.c
+              1
+              ..\..\..\..\common\src\txe_thread_priority_change.c
+            
+            
+              txe_thread_relinquish.c
+              1
+              ..\..\..\..\common\src\txe_thread_relinquish.c
+            
+            
+              txe_thread_reset.c
+              1
+              ..\..\..\..\common\src\txe_thread_reset.c
+            
+            
+              txe_thread_resume.c
+              1
+              ..\..\..\..\common\src\txe_thread_resume.c
+            
+            
+              txe_thread_suspend.c
+              1
+              ..\..\..\..\common\src\txe_thread_suspend.c
+            
+            
+              txe_thread_terminate.c
+              1
+              ..\..\..\..\common\src\txe_thread_terminate.c
+            
+            
+              txe_thread_time_slice_change.c
+              1
+              ..\..\..\..\common\src\txe_thread_time_slice_change.c
+            
+            
+              txe_thread_wait_abort.c
+              1
+              ..\..\..\..\common\src\txe_thread_wait_abort.c
+            
+            
+              txe_timer_activate.c
+              1
+              ..\..\..\..\common\src\txe_timer_activate.c
+            
+            
+              txe_timer_change.c
+              1
+              ..\..\..\..\common\src\txe_timer_change.c
+            
+            
+              txe_timer_create.c
+              1
+              ..\..\..\..\common\src\txe_timer_create.c
+            
+            
+              txe_timer_deactivate.c
+              1
+              ..\..\..\..\common\src\txe_timer_deactivate.c
+            
+            
+              txe_timer_delete.c
+              1
+              ..\..\..\..\common\src\txe_timer_delete.c
+            
+            
+              txe_timer_info_get.c
+              1
+              ..\..\..\..\common\src\txe_timer_info_get.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+      
+        <Project Info>
+        
+        
+        
+        
+        
+        0
+        1
+      
+    
+  
+
+
diff --git a/ports/cortex_m3/keil/example_build/sample_threadx.c b/ports/cortex_m3/keil/example_build/sample_threadx.c
new file mode 100644
index 00000000..9b94bcd4
--- /dev/null
+++ b/ports/cortex_m3/keil/example_build/sample_threadx.c
@@ -0,0 +1,262 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of six
+   threads of different priorities, using a message queue, semaphore, and an event flags group.  */
+
+#include "tx_api.h"
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_QUEUE_SIZE         10
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+
+
+/* Define the thread stacks.  */
+
+UCHAR                   thread_0_stack[DEMO_STACK_SIZE];
+UCHAR                   thread_1_stack[DEMO_STACK_SIZE];
+UCHAR                   thread_2_stack[DEMO_STACK_SIZE];
+UCHAR                   thread_3_stack[DEMO_STACK_SIZE];
+UCHAR                   thread_4_stack[DEMO_STACK_SIZE];
+UCHAR                   thread_5_stack[DEMO_STACK_SIZE];
+
+
+/* Define the queue area.  */
+
+UCHAR					queue_0_area[DEMO_QUEUE_SIZE*sizeof(ULONG)];
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+
+
+volatile unsigned int bootloop;
+
+/* Define main entry point.  */
+
+
+
+int main()
+{
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            thread_0_stack, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            thread_1_stack, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            thread_2_stack, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            thread_3_stack, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            thread_4_stack, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            thread_5_stack, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, queue_0_area, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
diff --git a/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s
new file mode 100644
index 00000000..4b55621a
--- /dev/null
+++ b/ports/cortex_m3/keil/example_build/tx_initialize_low_level.s
@@ -0,0 +1,266 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Initialize                                                          */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_initialize.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IMPORT  _tx_thread_system_stack_ptr
+    IMPORT  _tx_initialize_unused_memory
+    IMPORT  _tx_timer_interrupt
+    IMPORT  __main
+    IMPORT  |Image$$RO$$Limit|
+    IMPORT  |Image$$RW$$Base|
+    IMPORT  |Image$$ZI$$Base|
+    IMPORT  |Image$$ZI$$Limit|
+    IMPORT  __tx_PendSVHandler
+;
+;
+SYSTEM_CLOCK        EQU     6000000
+SYSTICK_CYCLES      EQU     ((SYSTEM_CLOCK / 100) -1)
+;
+;
+;/* Setup the stack and heap areas.  */
+;
+STACK_SIZE          EQU     0x00000400
+HEAP_SIZE           EQU     0x00000000
+
+    AREA    STACK, NOINIT, READWRITE, ALIGN=3
+StackMem
+    SPACE   STACK_SIZE
+__initial_sp
+
+
+    AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+HeapMem
+    SPACE   HEAP_SIZE
+__heap_limit
+
+
+    AREA    RESET, CODE, READONLY
+;
+    EXPORT  __tx_vectors
+__tx_vectors
+    DCD     __initial_sp                            ; Reset and system stack ptr
+    DCD     Reset_Handler                           ; Reset goes to startup function
+    DCD     __tx_NMIHandler                         ; NMI
+    DCD     __tx_BadHandler                         ; HardFault
+    DCD     0                                       ; MemManage
+    DCD     0                                       ; BusFault
+    DCD     0                                       ; UsageFault
+    DCD     0                                       ; 7
+    DCD     0                                       ; 8
+    DCD     0                                       ; 9
+    DCD     0                                       ; 10
+    DCD     __tx_SVCallHandler                      ; SVCall
+    DCD     __tx_DBGHandler                         ; Monitor
+    DCD     0                                       ; 13
+    DCD     __tx_PendSVHandler                      ; PendSV
+    DCD     __tx_SysTickHandler                     ; SysTick
+    DCD     __tx_IntHandler                         ; Int 0
+    DCD     __tx_IntHandler                         ; Int 1
+    DCD     __tx_IntHandler                         ; Int 2
+    DCD     __tx_IntHandler                         ; Int 3
+        
+;
+;
+    AREA ||.text||, CODE, READONLY
+    EXPORT  Reset_Handler
+Reset_Handler
+    CPSID   i
+    LDR     R0, =__main
+    BX      R0
+
+
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_initialize_low_level                          Cortex-M3/RVDS    */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for any low-level processor            */
+;/*    initialization, including setting up interrupt vectors, setting     */
+;/*    up a periodic timer interrupt source, saving the system stack       */
+;/*    pointer for use in ISR processing later, and finding the first      */
+;/*    available RAM memory address for tx_application_define.             */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_initialize_low_level(VOID)
+;{
+    EXPORT  _tx_initialize_low_level
+_tx_initialize_low_level
+;
+;    /* Disable interrupts during ThreadX initialization.  */
+;
+    CPSID   i
+;
+;    /* Set base of available memory to end of non-initialised RAM area.  */
+;     
+    LDR     r0, =_tx_initialize_unused_memory   ; Build address of unused memory pointer
+    LDR     r1, =|Image$$ZI$$Limit|             ; Build first free address
+    ADD     r1, r1, #4                          ; 
+    STR     r1, [r0]                            ; Setup first unused memory pointer
+;
+;    /* Setup Vector Table Offset Register.  */
+;    
+    MOV     r0, #0xE000E000                     ; Build address of NVIC registers
+    LDR     r1, =__tx_vectors                   ; Pickup address of vector table
+    STR     r1, [r0, #0xD08]                    ; Set vector table address   
+;
+;    /* Enable the cycle count register.  */
+;
+;    LDR     r0, =0xE0001000                     ; Build address of DWT register
+;    LDR     r1, [r0]                            ; Pickup the current value
+;    ORR     r1, r1, #1                          ; Set the CYCCNTENA bit
+;    STR     r1, [r0]                            ; Enable the cycle count register 
+;
+;    /* Set system stack pointer from vector value.  */
+;
+    LDR     r0, =_tx_thread_system_stack_ptr    ; Build address of system stack pointer
+    LDR     r1, =__tx_vectors                   ; Pickup address of vector table
+    LDR     r1, [r1]                            ; Pickup reset stack pointer
+    STR     r1, [r0]                            ; Save system stack pointer
+;
+;    /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference.  */
+;
+    MOV     r0, #0xE000E000                     ; Build address of NVIC registers
+    LDR     r1, =SYSTICK_CYCLES
+    STR     r1, [r0, #0x14]                     ; Setup SysTick Reload Value
+    MOV     r1, #0x7                            ; Build SysTick Control Enable Value
+    STR     r1, [r0, #0x10]                     ; Setup SysTick Control
+;
+;    /* Configure handler priorities.  */
+;
+    LDR     r1, =0x00000000                     ; Rsrv, UsgF, BusF, MemM
+    STR     r1, [r0, #0xD18]                    ; Setup System Handlers 4-7 Priority Registers
+
+    LDR     r1, =0xFF000000                     ; SVCl, Rsrv, Rsrv, Rsrv
+    STR     r1, [r0, #0xD1C]                    ; Setup System Handlers 8-11 Priority Registers
+                                                ; Note: SVC must be lowest priority, which is 0xFF
+
+    LDR     r1, =0x40FF0000                     ; SysT, PnSV, Rsrv, DbgM
+    STR     r1, [r0, #0xD20]                    ; Setup System Handlers 12-15 Priority Registers
+                                                ; Note: PnSV must be lowest priority, which is 0xFF
+;
+;    /* Return to caller.  */
+;    
+    BX      lr 
+;}
+;
+;       
+;/* Define initial heap/stack routine for the ARM RVCT startup code.
+;   This routine will set the initial stack and heap locations */
+;
+    EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+    LDR     R0, =HeapMem
+    LDR     R1, =(StackMem + STACK_SIZE)
+    LDR     R2, =(HeapMem + HEAP_SIZE)
+    LDR     R3, =StackMem
+    BX      LR
+;
+;
+;/* Define shells for each of the unused vectors.  */
+;
+    EXPORT  __tx_BadHandler
+__tx_BadHandler 
+    B   __tx_BadHandler
+
+
+    EXPORT  __tx_SVCallHandler
+__tx_SVCallHandler
+    B       __tx_SVCallHandler 
+
+
+    EXPORT  __tx_IntHandler
+__tx_IntHandler
+; VOID InterruptHandler (VOID)
+; {
+    PUSH    {r0, lr}
+        
+;    /* Do interrupt handler work here */
+;    /* .... */
+
+    POP     {r0, lr}
+    BX      LR
+; }
+
+    EXPORT  __tx_SysTickHandler
+__tx_SysTickHandler
+; VOID TimerInterruptHandler (VOID)
+; {
+;
+    PUSH    {r0, lr}
+    BL      _tx_timer_interrupt
+    POP     {r0, lr}
+    BX      LR
+; }
+
+    EXPORT  __tx_NMIHandler 
+__tx_NMIHandler
+    B       __tx_NMIHandler
+
+    EXPORT  __tx_DBGHandler
+__tx_DBGHandler
+    B       __tx_DBGHandler
+
+    ALIGN
+    LTORG
+    END
+                
+
diff --git a/ports/cortex_m3/keil/inc/tx_port.h b/ports/cortex_m3/keil/inc/tx_port.h
new file mode 100644
index 00000000..6b0adb0d
--- /dev/null
+++ b/ports/cortex_m3/keil/inc/tx_port.h
@@ -0,0 +1,346 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */
+/*                                                                        */
+/*    tx_port.h                                         Cortex-M3/Keil    */
+/*                                                           6.0.1        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file contains data type definitions that make the ThreadX      */
+/*    real-time kernel function identically on a variety of different     */
+/*    processor architectures.  For example, the size or number of bits   */
+/*    in an "int" data type vary between microprocessor architectures and */
+/*    even C compilers for the same microprocessor.  ThreadX does not     */
+/*    directly use native C data types.  Instead, ThreadX creates its     */
+/*    own special types that can be mapped to actual data types by this   */
+/*    file to guarantee consistency in the interface and functionality.   */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include 
+#include 
+
+
+/* Define ThreadX basic types for this port.  */
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */
+#endif
+
+
+/* Define various constants for the ThreadX Cortex-M3 port.  */
+
+#define TX_INT_DISABLE                          1           /* Disable interrupts               */
+#define TX_INT_ENABLE                           0           /* Enable interrupts                */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_MISRA_ENABLE
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0xE0001004)  
+#endif
+#else
+ULONG   _tx_misra_time_stamp_get(VOID);
+#define TX_TRACE_TIME_SOURCE                    _tx_misra_time_stamp_get()
+#endif
+
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          (0)
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#ifdef TX_MISRA_ENABLE
+#define TX_DISABLE_INLINE
+#else
+#define TX_INLINE_INITIALIZATION
+#endif
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifndef TX_MISRA_ENABLE
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#define TX_THREAD_EXTENSION_2                   
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  
+
+
+#ifndef TX_MISRA_ENABLE
+
+register unsigned int _ipsr __asm("ipsr");
+
+#endif
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Define the get system state macro.   */
+   
+#ifndef TX_THREAD_GET_SYSTEM_STATE
+#ifndef TX_MISRA_ENABLE
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | _ipsr)
+#else
+ULONG   _tx_misra_ipsr_get(VOID);
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | _tx_misra_ipsr_get())
+#endif
+#endif
+
+
+/* Define the check for whether or not to call the _tx_thread_system_return function.  A non-zero value
+   indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h
+   for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always
+   zero after initialization for Cortex-M ports. */
+
+#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
+#define TX_THREAD_SYSTEM_RETURN_CHECK(c)    (c) = ((ULONG) _tx_thread_preempt_disable); 
+#endif
+
+
+/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to 
+   prevent early scheduling on Cortex-M parts.  */
+   
+#define TX_PORT_SPECIFIC_POST_INITIALIZATION    _tx_thread_preempt_disable++;
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef TX_DISABLE_INLINE
+   
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       (b) =  (UINT) __clz(__rbit((m)));
+
+#endif
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifdef TX_DISABLE_INLINE
+
+UINT                                            _tx_thread_interrupt_disable(VOID);
+VOID                                            _tx_thread_interrupt_restore(UINT previous_posture);
+
+#define TX_INTERRUPT_SAVE_AREA                  register UINT interrupt_save;
+
+#define TX_DISABLE                              interrupt_save = _tx_thread_interrupt_disable();
+
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+
+#else
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int  was_masked;
+#define TX_DISABLE                              was_masked = __disable_irq();
+#define TX_RESTORE                              if (was_masked == 0) __enable_irq();
+
+#define _tx_thread_system_return                _tx_thread_system_return_inline
+
+
+static void _tx_thread_system_return_inline(void)
+{
+unsigned int          was_masked;
+
+
+    /* Set PendSV to invoke ThreadX scheduler.  */
+    *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    if (_ipsr == 0)
+    {
+        was_masked = __disable_irq();
+        __enable_irq();
+        if (was_masked != 0)
+            __disable_irq();
+    }
+}
+#endif
+
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Cortex-M3/Keil Version 6.0 *";
+#else
+#ifdef TX_MISRA_ENABLE
+extern  CHAR                    _tx_version_id[100];
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+#endif
+
+
+#endif
+
+
+
+
diff --git a/ports/cortex_m3/keil/readme_threadx.txt b/ports/cortex_m3/keil/readme_threadx.txt
new file mode 100644
index 00000000..e0c99485
--- /dev/null
+++ b/ports/cortex_m3/keil/readme_threadx.txt
@@ -0,0 +1,152 @@
+                     Microsoft's Azure RTOS ThreadX for Cortex-M3 
+
+                               Thumb & 32-bit Mode
+
+                    Using the Keil Microcontroller Development Kit
+
+1.  Building the ThreadX run-time Library
+
+Building the ThreadX library is easy, simply load the project file 
+ThreadX_Library.Uv2, which is located inside the "example_build" directory. 
+
+Once the ThreadX library files are displayed in the project window,
+select the "Build Target" operation and observe the compilation and assembly
+of the ThreadX library. This project build produces the ThreadX library 
+file ThreadX_Library.lib.
+
+
+2.  Demonstration System
+
+The ThreadX demonstration is designed to execute under the Keil simulator or
+Cortex-M3 hardware. This demonstration is slightly smaller than typical ThreadX 
+demonstrations, and thus requires less than 7KB of Flash and less than 4KB of RAM.
+
+Building the demonstration is easy; simply open the ThreadX demonstration 
+project file ThreadX_Demo.Uv2, which is located inside the "example_build" 
+directory. 
+
+Once open, select the "Build Target" operation and observe the compilation of 
+sample_threadx.c (which is the demonstration application) and linking with 
+ThreadX_Library.lib. The resulting file ThreadX_Demo.axf is a binary file that 
+can be downloaded and executed under the uVision simulator or Cortex-M3 hardware. 
+
+For simulator execution, the following memory regions need to be defined via
+the "Debug -> Memory Map" dialog:
+
+0x20000000, 0x20080000 [check read and write access]
+0xE0000000, 0xE8000000 [check read and write access]
+
+
+3.  System Initialization
+
+The entry point in ThreadX for the Cortex-M3 using Keil tools is at label 
+__main. This is defined within the Keil compiler's startup code. In 
+addition, this is where all static and global pre-set C variable 
+initialization processing takes place.
+
+The ThreadX tx_initialize_low_level.s file is responsible for setting up 
+various system data structures, the vector area, and a periodic timer interrupt 
+source. 
+
+In addition, _tx_initialize_low_level determines the first available 
+address for use by the application, which is supplied as the sole input 
+parameter to your application definition function, tx_application_define.
+
+
+4.  Register Usage and Stack Frames
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have the same stack frame in the Cortex-M3 version of
+ThreadX. The top of the suspended thread's stack is pointed to by 
+tx_thread_stack_ptr in the associated thread control block TX_THREAD.
+
+
+  Stack Offset     Stack Contents 
+
+     0x00               r4
+     0x04               r5
+     0x08               r6
+     0x0C               r7
+     0x10               r8
+     0x14               r9
+     0x18               r10
+     0x1C               r11
+     0x20               r0          (Hardware stack starts here!!)
+     0x24               r1
+     0x28               r2
+     0x2C               r3
+     0x30               r12
+     0x34               lr
+     0x38               pc
+     0x3C               xPSR
+
+
+5.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+breakpoints inside of ThreadX itself. Of course, this costs some 
+performance. To make it run faster, you can change the ThreadX_Library.Uv2 
+project to debugging and enable all compiler optimizations. 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+6.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-M3
+targets. There are a certain set of requirements that are defined in the 
+following sub-sections:
+
+
+6.1  Vector Area
+
+The Cortex-M3 vectors start at the label __tx_vectors. The application may modify
+the vector area according to its needs.
+
+
+6.2 Managed Interrupts
+
+ISRs for Cortex-M can be written completely in C (or assembly language) without any
+calls to _tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed
+access to the ThreadX API that is available to ISRs.
+
+ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
+
+void    your_C_isr(void)
+{
+
+    /* ISR processing goes here, including any needed function calls.  */
+}
+
+ISRs written in assembly language will take the form:
+
+    EXPORT  your_assembly_isr
+your_assembly_isr
+
+    PUSH    {r0, lr}
+
+    ; ISR processing goes here, including any needed function calls.
+
+    POP     {r0, lr}
+    BX      lr
+
+
+
+7.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX 6.0.1 version for Cortex-M3 using Keil tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_m3/keil/src/tx_thread_context_restore.s b/ports/cortex_m3/keil/src/tx_thread_context_restore.s
new file mode 100644
index 00000000..d78da55e
--- /dev/null
+++ b/ports/cortex_m3/keil/src/tx_thread_context_restore.s
@@ -0,0 +1,99 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT  _tx_execution_isr_exit
+    ENDIF
+;
+;
+    AREA    ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_context_restore                        Cortex-M3/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function restores the interrupt context if it is processing a  */
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */
+;/*    if no thread was running, the function returns to the scheduler.    */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_schedule                   Thread scheduling routine     */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ISRs                                  Interrupt Service Routines    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_restore(VOID)
+;{
+    EXPORT  _tx_thread_context_restore
+_tx_thread_context_restore
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR exit function to indicate an ISR is complete.  */
+;
+    PUSH    {r0,lr}                                 ; Save ISR lr
+    BL      _tx_execution_isr_exit                  ; Call the ISR exit function
+    POP     {r0,lr}                                 ; Restore ISR lr
+    ENDIF
+;
+    POP     {lr}
+    BX      lr
+;}
+    ALIGN
+    LTORG
+    END
diff --git a/ports/cortex_m3/keil/src/tx_thread_context_save.s b/ports/cortex_m3/keil/src/tx_thread_context_save.s
new file mode 100644
index 00000000..5645d361
--- /dev/null
+++ b/ports/cortex_m3/keil/src/tx_thread_context_save.s
@@ -0,0 +1,99 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT  _tx_execution_isr_enter
+    ENDIF
+;
+;
+    AREA    ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_context_save                           Cortex-M3/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function saves the context of an executing thread in the       */
+;/*    beginning of interrupt processing.  The function also ensures that  */
+;/*    the system stack is used upon return to the calling ISR.            */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ISRs                                                                */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_save(VOID)
+;{
+    EXPORT  _tx_thread_context_save
+_tx_thread_context_save
+   IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {r0, lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter                 ; Call the ISR enter function
+    POP     {r0, lr}                                ; Recover ISR lr
+    ENDIF
+;
+;    /* Return to interrupt processing.  */
+;     
+    BX      lr                                      ; Return to interrupt processing caller
+;}
+    ALIGN
+    LTORG
+    END
diff --git a/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s b/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s
new file mode 100644
index 00000000..de8f1029
--- /dev/null
+++ b/ports/cortex_m3/keil/src/tx_thread_interrupt_control.s
@@ -0,0 +1,85 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_control                      Cortex-M3/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for changing the interrupt lockout     */
+;/*    posture of the system.                                              */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    new_posture                           New interrupt lockout posture */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    old_posture                           Old interrupt lockout posture */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_control(UINT new_posture)
+;{
+    EXPORT  _tx_thread_interrupt_control
+_tx_thread_interrupt_control
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    MRS     r1, PRIMASK
+    MSR     PRIMASK, r0
+    MOV     r0, r1
+    BX      lr
+;
+;}
+    END
+    
diff --git a/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s b/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s
new file mode 100644
index 00000000..2ff46cad
--- /dev/null
+++ b/ports/cortex_m3/keil/src/tx_thread_interrupt_disable.s
@@ -0,0 +1,83 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_disable                      Cortex-M3/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for disabling interrupts and returning */
+;/*    the previous interrupt lockout posture.                             */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    old_posture                           Old interrupt lockout posture */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_disable(UINT new_posture)
+;{
+    EXPORT  _tx_thread_interrupt_disable
+_tx_thread_interrupt_disable
+;
+;    /* Return current interrupt lockout posture.  */
+;
+    MRS     r0, PRIMASK
+    CPSID   i
+    BX      lr
+;
+;}
+    END
diff --git a/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s b/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s
new file mode 100644
index 00000000..43c20a0f
--- /dev/null
+++ b/ports/cortex_m3/keil/src/tx_thread_interrupt_restore.s
@@ -0,0 +1,82 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_restore                      Cortex-M3/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for restoring the previous             */
+;/*    interrupt lockout posture.                                          */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    previous_posture                      Previous interrupt posture    */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_interrupt_restore(UINT new_posture)
+;{
+    EXPORT  _tx_thread_interrupt_restore
+_tx_thread_interrupt_restore
+;
+;    /* Restore previous interrupt lockout posture.  */
+;
+    MSR     PRIMASK, r0
+    BX      lr
+;
+;}
+    END
diff --git a/ports/cortex_m3/keil/src/tx_thread_schedule.s b/ports/cortex_m3/keil/src/tx_thread_schedule.s
new file mode 100644
index 00000000..3b9f2cda
--- /dev/null
+++ b/ports/cortex_m3/keil/src/tx_thread_schedule.s
@@ -0,0 +1,253 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;   
+    IMPORT  _tx_thread_current_ptr
+    IMPORT  _tx_thread_execute_ptr
+    IMPORT  _tx_timer_time_slice
+    IMPORT  _tx_thread_system_stack_ptr
+    IMPORT  _tx_thread_preempt_disable
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT  _tx_execution_thread_enter
+    IMPORT  _tx_execution_thread_exit        
+    ENDIF
+;
+;
+    AREA    ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_schedule                               Cortex-M3/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function waits for a thread control block pointer to appear in */
+;/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
+;/*    in the variable, the corresponding thread is resumed.               */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter          ThreadX entry function         */
+;/*    _tx_thread_system_return             Return to system from thread   */
+;/*    _tx_thread_context_restore           Restore thread's context       */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_schedule(VOID)
+;{
+        EXPORT  _tx_thread_schedule
+_tx_thread_schedule
+;
+;    /* This function should only ever be called on Cortex-M
+;       from the first schedule request. Subsequent scheduling occurs
+;       from the PendSV handling routines below. */
+;
+;    /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets.  */
+;     
+    MOV     r0, #0                                  ; Build value for TX_FALSE
+    LDR     r2, =_tx_thread_preempt_disable         ; Build address of preempt disable flag
+    STR     r0, [r2, #0]                            ; Clear preempt disable flag
+;
+;    /* Enable the interrupts */
+;
+    CPSIE   i
+;       
+;    /* Enter the scheduler for the first time.  */
+;
+    MOV     r0, #0x10000000                         ; Load PENDSVSET bit
+    MOV     r1, #0xE000E000                         ; Load NVIC base
+    STR     r0, [r1, #0xD04]                        ; Set PENDSVBIT in ICSR
+    DSB                                             ; Complete all memory accesses
+    ISB                                             ; Flush pipeline
+;
+;    /* Wait here for the PendSV to take place.  */
+;     
+__tx_wait_here
+    B       __tx_wait_here                          ; Wait for the PendSV to happen
+;}
+;
+;    /* Generic context switching PendSV handler.  */
+;     
+    EXPORT  __tx_PendSVHandler
+    EXPORT  PendSV_Handler
+__tx_PendSVHandler  
+PendSV_Handler
+;
+;    /* Get current thread value and new thread pointer.  */
+;       
+__tx_ts_handler 
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread exit function to indicate the thread is no longer executing.  */
+;
+    CPSID   i                                       ; Disable interrupts
+    PUSH    {r0, lr}                                ; Save LR (and r0 just for alignment)
+    BL      _tx_execution_thread_exit               ; Call the thread exit function
+    POP     {r0, lr}                                ; Recover LR
+    CPSIE   i                                       ; Enable interrupts
+    ENDIF
+    MOV32   r0, _tx_thread_current_ptr              ; Build current thread pointer address
+    MOV32   r2, _tx_thread_execute_ptr              ; Build execute thread pointer address
+    MOV     r3, #0                                  ; Build NULL value
+    LDR     r1, [r0]                                ; Pickup current thread pointer
+;
+;    /* Determine if there is a current thread to finish preserving.  */
+;       
+    CBZ     r1, __tx_ts_new                         ; If NULL, skip preservation
+;
+;    /* Recover PSP and preserve current thread context.  */
+;
+    STR     r3, [r0]                                ; Set _tx_thread_current_ptr to NULL
+    MRS     r12, PSP                                ; Pickup PSP pointer (thread's stack pointer)
+    STMDB   r12!, {r4-r11}                          ; Save its remaining registers
+    MOV32   r4, _tx_timer_time_slice                ; Build address of time-slice variable
+    STMDB   r12!, {LR}                              ; Save LR on the stack
+;
+;    /* Determine if time-slice is active. If it isn't, skip time handling processing.  */
+;
+    LDR     r5, [r4]                                ; Pickup current time-slice
+    STR     r12, [r1, #8]                           ; Save the thread stack pointer
+    CBZ     r5, __tx_ts_new                         ; If not active, skip processing
+;
+;    /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable.  */
+;
+    STR     r5, [r1, #24]                           ; Save current time-slice
+;
+;    /* Clear the global time-slice.  */
+;
+    STR     r3, [r4]                                ; Clear time-slice
+;       
+;    /* Executing thread is now completely preserved!!!  */
+;
+__tx_ts_new 
+;
+;    /* Now we are looking for a new thread to execute!  */
+;
+    CPSID   i                                       ; Disable interrupts
+    LDR     r1, [r2]                                ; Is there another thread ready to execute?
+    CBZ     r1, __tx_ts_wait                        ; No, skip to the wait processing
+;
+;    /* Yes, another thread is ready for else, make the current thread the new thread.  */
+;
+    STR     r1, [r0]                                ; Setup the current thread pointer to the new thread
+    CPSIE   i                                       ; Enable interrupts
+;
+;    /* Increment the thread run count.  */
+;
+__tx_ts_restore 
+    LDR     r7, [r1, #4]                            ; Pickup the current thread run count
+    MOV32   r4, _tx_timer_time_slice                ; Build address of time-slice variable
+    LDR     r5, [r1, #24]                           ; Pickup thread's current time-slice
+    ADD     r7, r7, #1                              ; Increment the thread run count
+    STR     r7, [r1, #4]                            ; Store the new run count
+;
+;    /* Setup global time-slice with thread's current time-slice.  */
+;
+    STR     r5, [r4]                                ; Setup global time-slice
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread entry function to indicate the thread is executing.  */
+;
+    PUSH    {r0, r1}                                ; Save r0/r1
+    BL      _tx_execution_thread_enter              ; Call the thread execution enter function
+    POP     {r0, r1}                                ; Recover r3
+    ENDIF
+;
+;    /* Restore the thread context and PSP.  */
+;
+    LDR     r12, [r1, #8]                           ; Pickup thread's stack pointer
+    LDMIA   r12!, {LR}                              ; Pickup LR
+    LDMIA   r12!, {r4-r11}                          ; Recover thread's registers
+    MSR     PSP, r12                                ; Setup the thread's stack pointer
+;
+;    /* Return to thread.  */
+;       
+        BX      lr                                  ; Return to thread!
+;
+;    /* The following is the idle wait processing... in this case, no threads are ready for execution and the
+;       system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts 
+;       are disabled to allow use of WFI for waiting for a thread to arrive.  */
+;
+__tx_ts_wait    
+    CPSID   i                                       ; Disable interrupts
+    LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
+    STR     r1, [r0]                                ; Store it in the current pointer
+    CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+    IF :DEF:TX_ENABLE_WFI
+    DSB                                             ; Ensure no outstanding memory transactions
+    WFI                                             ; Wait for interrupt
+    ISB                                             ; Ensure pipeline is flushed
+    ENDIF
+    CPSIE   i                                       ; Enable interrupts
+    B       __tx_ts_wait                            ; Loop to continue waiting
+;
+;    /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are 
+;       already in the handler!  */
+;
+__tx_ts_ready   
+    MOV     r7, #0x08000000                         ; Build clear PendSV value
+    MOV     r8, #0xE000E000                         ; Build base NVIC address
+    STR     r7, [r8, #0xD04]                        ; Clear any PendSV 
+;
+;    /* Re-enable interrupts and restore new thread.  */
+;       
+    CPSIE   i                                       ; Enable interrupts
+    B       __tx_ts_restore                         ; Restore the thread
+
+    ALIGN
+    LTORG
+    END
+    
diff --git a/ports/cortex_m3/keil/src/tx_thread_stack_build.s b/ports/cortex_m3/keil/src/tx_thread_stack_build.s
new file mode 100644
index 00000000..bfc38038
--- /dev/null
+++ b/ports/cortex_m3/keil/src/tx_thread_stack_build.s
@@ -0,0 +1,143 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_stack_build                            Cortex-M3/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function builds a stack frame on the supplied thread's stack.  */
+;/*    The stack frame results in a fake interrupt return to the supplied  */
+;/*    function pointer.                                                   */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    thread_ptr                            Pointer to thread control blk */
+;/*    function_ptr                          Pointer to return function    */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_thread_create                     Create thread service         */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+;{
+    EXPORT  _tx_thread_stack_build
+_tx_thread_stack_build
+;
+;       
+;    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+;       on the Cortex-M3 should look like the following after it is built:
+;       
+;       Stack Top:      
+;                       LR          Interrupted LR (LR at time of PENDSV)
+;                       r4          Initial value for r4
+;                       r5          Initial value for r5
+;                       r6          Initial value for r6
+;                       r7          Initial value for r7
+;                       r8          Initial value for r8
+;                       r9          Initial value for r9
+;                       r10         Initial value for r10
+;                       r11         Initial value for r11
+;                       r0          Initial value for r0    (Hardware stack starts here!!)
+;                       r1          Initial value for r1
+;                       r2          Initial value for r2
+;                       r3          Initial value for r3
+;                       r12         Initial value for r12
+;                       lr          Initial value for lr
+;                       pc          Initial value for pc
+;                       xPSR        Initial value for xPSR
+;
+;    Stack Bottom: (higher memory address)  */
+;
+    LDR     r2, [r0, #16]                           ; Pickup end of stack area
+    BIC     r2, r2, #0x7                            ; Align frame for 8-byte alignment
+    SUB     r2, r2, #68                             ; Subtract frame size
+    LDR     r3, =0xFFFFFFFD                         ; Build initial LR value
+    STR     r3, [r2, #0]                            ; Save on the stack
+;
+;    /* Actually build the stack frame.  */
+;
+    MOV     r3, #0                                  ; Build initial register value
+    STR     r3, [r2, #4]                            ; Store initial r4
+    STR     r3, [r2, #8]                            ; Store initial r5
+    STR     r3, [r2, #12]                           ; Store initial r6
+    STR     r3, [r2, #16]                           ; Store initial r7
+    STR     r3, [r2, #20]                           ; Store initial r8
+    STR     r3, [r2, #24]                           ; Store initial r9
+    STR     r3, [r2, #28]                           ; Store initial r10
+    STR     r3, [r2, #32]                           ; Store initial r11
+;
+;    /* Hardware stack follows.  /
+;
+    STR     r3, [r2, #36]                           ; Store initial r0
+    STR     r3, [r2, #40]                           ; Store initial r1
+    STR     r3, [r2, #44]                           ; Store initial r2
+    STR     r3, [r2, #48]                           ; Store initial r3
+    STR     r3, [r2, #52]                           ; Store initial r12
+    MOV     r3, #0xFFFFFFFF                         ; Poison EXC_RETURN value
+    STR     r3, [r2, #56]                           ; Store initial lr
+    STR     r1, [r2, #60]                           ; Store initial pc
+    MOV     r3, #0x01000000                         ; Only T-bit need be set
+    STR     r3, [r2, #64]                           ; Store initial xPSR
+;
+;    /* Setup stack pointer.  */
+;    thread_ptr -> tx_thread_stack_ptr =  r2;
+;
+    STR     r2, [r0, #8]                            ; Save stack pointer in thread's
+                                                    ;   control block
+    BX      lr                                      ; Return to caller
+;}
+    END
+
diff --git a/ports/cortex_m3/keil/src/tx_thread_system_return.s b/ports/cortex_m3/keil/src/tx_thread_system_return.s
new file mode 100644
index 00000000..59d59bc6
--- /dev/null
+++ b/ports/cortex_m3/keil/src/tx_thread_system_return.s
@@ -0,0 +1,96 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+;
+    AREA    ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_system_return                          Cortex-M3/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is target processor specific.  It is used to transfer */
+;/*    control from a thread back to the ThreadX system.  Only a           */
+;/*    minimal context is saved since the compiler assumes temp registers  */
+;/*    are going to get slicked by a function call anyway.                 */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_schedule                   Thread scheduling loop        */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ThreadX components                                                  */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_system_return(VOID)
+;{
+    EXPORT  _tx_thread_system_return
+_tx_thread_system_return
+;
+;    /* Return to real scheduler via PendSV. Note that this routine is often 
+;       replaced with in-line assembly in tx_port.h to improved performance.  */
+;     
+    MOV     r0, #0x10000000                         ; Load PENDSVSET bit
+    MOV     r1, #0xE000E000                         ; Load NVIC base
+    STR     r0, [r1, #0xD04]                        ; Set PENDSVBIT in ICSR
+    MRS     r0, IPSR                                ; Pickup IPSR
+    CMP     r0, #0                                  ; Is it a thread returning?
+    BNE     _isr_context                            ; If ISR, skip interrupt enable
+    MRS     r1, PRIMASK                             ; Thread context returning, pickup PRIMASK
+    CPSIE   i                                       ; Enable interrupts
+    MSR     PRIMASK, r1                             ; Restore original interrupt posture
+_isr_context
+    BX      lr                                      ; Return to caller 
+;}
+    END  
+    
diff --git a/ports/cortex_m3/keil/src/tx_timer_interrupt.s b/ports/cortex_m3/keil/src/tx_timer_interrupt.s
new file mode 100644
index 00000000..e8c34551
--- /dev/null
+++ b/ports/cortex_m3/keil/src/tx_timer_interrupt.s
@@ -0,0 +1,271 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Timer                                                               */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_timer.h"
+;#include "tx_thread.h"
+;
+;
+;Define Assembly language external references...
+;
+    IMPORT      _tx_timer_time_slice
+    IMPORT      _tx_timer_system_clock
+    IMPORT      _tx_timer_current_ptr
+    IMPORT      _tx_timer_list_start
+    IMPORT      _tx_timer_list_end
+    IMPORT      _tx_timer_expired_time_slice
+    IMPORT      _tx_timer_expired
+    IMPORT      _tx_thread_time_slice
+    IMPORT      _tx_timer_expiration_process
+    IMPORT      _tx_thread_preempt_disable
+    IMPORT      _tx_thread_current_ptr
+    IMPORT      _tx_thread_execute_ptr
+;
+;
+    AREA ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_timer_interrupt                               Cortex-M3/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function processes the hardware timer interrupt.  This         */
+;/*    processing includes incrementing the system clock and checking for  */
+;/*    time slice and/or timer expiration.  If either is found, the        */
+;/*    interrupt context save/restore functions are called along with the  */
+;/*    expiration functions.                                               */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_timer_expiration_process          Timer expiration processing   */
+;/*    _tx_thread_time_slice                 Time slice interrupted thread */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    interrupt vector                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_timer_interrupt(VOID)
+;{
+    EXPORT  _tx_timer_interrupt
+_tx_timer_interrupt
+;
+;    /* Upon entry to this routine, it is assumed that context save has already
+;       been called, and therefore the compiler scratch registers are available
+;       for use.  */
+;
+;    /* Increment the system clock.  */
+;    _tx_timer_system_clock++;
+;
+    MOV32   r1, _tx_timer_system_clock              ; Pickup address of system clock
+    LDR     r0, [r1, #0]                            ; Pickup system clock
+    ADD     r0, r0, #1                              ; Increment system clock
+    STR     r0, [r1, #0]                            ; Store new system clock
+;
+;    /* Test for time-slice expiration.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    MOV32   r3, _tx_timer_time_slice                ; Pickup address of time-slice 
+    LDR     r2, [r3, #0]                            ; Pickup time-slice
+    CBZ     r2,  __tx_timer_no_time_slice           ; Is it non-active?
+                                                    ; Yes, skip time-slice processing
+;
+;       /* Decrement the time_slice.  */
+;       _tx_timer_time_slice--;
+;
+    SUB     r2, r2, #1                              ; Decrement the time-slice
+    STR     r2, [r3, #0]                            ; Store new time-slice value
+;
+;       /* Check for expiration.  */
+;       if (__tx_timer_time_slice == 0)
+;
+    CBNZ    r2, __tx_timer_no_time_slice            ; Has it expired?
+;
+;       /* Set the time-slice expired flag.  */
+;       _tx_timer_expired_time_slice =  TX_TRUE;
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup address of expired flag
+    MOV     r0, #1                                  ; Build expired value
+    STR     r0, [r3, #0]                            ; Set time-slice expiration flag
+;
+;    }
+;
+__tx_timer_no_time_slice
+;
+;    /* Test for timer expiration.  */
+;    if (*_tx_timer_current_ptr)
+;    {
+;
+    MOV32   r1, _tx_timer_current_ptr               ; Pickup current timer pointer address
+    LDR     r0, [r1, #0]                            ; Pickup current timer
+    LDR     r2, [r0, #0]                            ; Pickup timer list entry
+    CBZ     r2, __tx_timer_no_timer                 ; Is there anything in the list?
+                                                    ; No, just increment the timer
+;
+;        /* Set expiration flag.  */
+;        _tx_timer_expired =  TX_TRUE;
+;
+    MOV32   r3, _tx_timer_expired                   ; Pickup expiration flag address
+    MOV     r2, #1                                  ; Build expired value
+    STR     r2, [r3, #0]                            ; Set expired flag
+    B       __tx_timer_done                         ; Finished timer processing
+;
+;    }
+;    else
+;    {
+__tx_timer_no_timer
+;
+;        /* No timer expired, increment the timer pointer.  */
+;        _tx_timer_current_ptr++;
+;
+    ADD     r0, r0, #4                              ; Move to next timer
+;
+;        /* Check for wrap-around.  */
+;        if (_tx_timer_current_ptr == _tx_timer_list_end)
+;
+    MOV32   r3, _tx_timer_list_end                  ; Pickup addr of timer list end
+    LDR     r2, [r3, #0]                            ; Pickup list end
+    CMP     r0, r2                                  ; Are we at list end?
+    BNE     __tx_timer_skip_wrap                    ; No, skip wrap-around logic
+;
+;            /* Wrap to beginning of list.  */
+;            _tx_timer_current_ptr =  _tx_timer_list_start;
+;
+    MOV32   r3, _tx_timer_list_start                ; Pickup addr of timer list start
+    LDR     r0, [r3, #0]                            ; Set current pointer to list start
+;
+__tx_timer_skip_wrap
+;
+    STR     r0, [r1, #0]                            ; Store new current timer pointer
+;    }
+;
+__tx_timer_done
+;
+;
+;    /* See if anything has expired.  */
+;    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+;    {
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup addr of expired flag
+    LDR     r2, [r3, #0]                            ; Pickup time-slice expired flag
+    CBNZ    r2, __tx_something_expired              ; Did a time-slice expire?
+                                                    ; If non-zero, time-slice expired
+    MOV32   r1, _tx_timer_expired                   ; Pickup addr of other expired flag
+    LDR     r0, [r1, #0]                            ; Pickup timer expired flag
+    CBZ     r0, __tx_timer_nothing_expired          ; Did a timer expire?
+                                                    ; No, nothing expired
+;
+__tx_something_expired
+;
+;
+    STMDB   sp!, {r0, lr}                           ; Save the lr register on the stack
+                                                    ;   and save r0 just to keep 8-byte alignment
+;
+;    /* Did a timer expire?  */
+;    if (_tx_timer_expired)
+;    {
+;
+    MOV32   r1, _tx_timer_expired                   ; Pickup addr of expired flag
+    LDR     r0, [r1, #0]                            ; Pickup timer expired flag
+    CBZ     r0, __tx_timer_dont_activate            ; Check for timer expiration
+                                                    ; If not set, skip timer activation
+;
+;        /* Process timer expiration.  */
+;        _tx_timer_expiration_process();
+;
+    BL      _tx_timer_expiration_process            ; Call the timer expiration handling routine
+;
+;    }
+__tx_timer_dont_activate
+;
+;    /* Did time slice expire?  */
+;    if (_tx_timer_expired_time_slice)
+;    {
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup addr of time-slice expired 
+    LDR     r2, [r3, #0]                            ; Pickup the actual flag
+    CBZ     r2, __tx_timer_not_ts_expiration        ; See if the flag is set
+                                                    ; No, skip time-slice processing
+;
+;        /* Time slice interrupted thread.  */
+;        _tx_thread_time_slice(); 
+
+    BL      _tx_thread_time_slice                   ; Call time-slice processing
+    MOV32   r0, _tx_thread_preempt_disable          ; Build address of preempt disable flag
+    LDR     r1, [r0]                                ; Is the preempt disable flag set?
+    CBNZ    r1, __tx_timer_skip_time_slice          ; Yes, skip the PendSV logic
+    MOV32   r0, _tx_thread_current_ptr              ; Build current thread pointer address
+    LDR     r1, [r0]                                ; Pickup the current thread pointer
+    MOV32   r2, _tx_thread_execute_ptr              ; Build execute thread pointer address
+    LDR     r3, [r2]                                ; Pickup the execute thread pointer
+    MOV32   r0, 0xE000ED04                          ; Build address of control register
+    MOV32   r2, 0x10000000                          ; Build value for PendSV bit
+    CMP     r1, r3                                  ; Are they the same?
+    BEQ     __tx_timer_skip_time_slice              ; If the same, there was no time-slice performed
+    STR     r2, [r0]                                ; Not the same, issue the PendSV for preemption
+__tx_timer_skip_time_slice
+;
+;    }
+;
+__tx_timer_not_ts_expiration
+;
+    LDMIA   sp!, {r0, lr}                           ; Recover lr register (r0 is just there for
+;
+;    }
+;
+__tx_timer_nothing_expired
+
+    DSB                                             ; Complete all memory access
+    BX      lr                                      ; Return to caller
+;
+;}
+    ALIGN
+    LTORG
+    END
+
diff --git a/ports/cortex_m4/ac5/example_build/build_threadx.bat b/ports/cortex_m4/ac5/example_build/build_threadx.bat
new file mode 100644
index 00000000..8971b7fa
--- /dev/null
+++ b/ports/cortex_m4/ac5/example_build/build_threadx.bat
@@ -0,0 +1,230 @@
+del tx.a
+armasm -g --cpu=cortex-m4 --apcs=interwork tx_initialize_low_level.s
+armasm -g --cpu=cortex-m4 --apcs=interwork ../src/tx_thread_stack_build.s
+armasm -g --cpu=cortex-m4 --apcs=interwork ../src/tx_thread_schedule.s
+armasm -g --cpu=cortex-m4 --apcs=interwork ../src/tx_thread_system_return.s
+armasm -g --cpu=cortex-m4 --apcs=interwork ../src/tx_thread_context_save.s
+armasm -g --cpu=cortex-m4 --apcs=interwork ../src/tx_thread_context_restore.s
+armasm -g --cpu=cortex-m4 --apcs=interwork ../src/tx_thread_interrupt_control.s
+armasm -g --cpu=cortex-m4 --apcs=interwork ../src/tx_thread_interrupt_disable.s
+armasm -g --cpu=cortex-m4 --apcs=interwork ../src/tx_thread_interrupt_restore.s
+armasm -g --cpu=cortex-m4 --apcs=interwork ../src/tx_timer_interrupt.s
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c
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+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c
+armcc -g --cpu=cortex-m4 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c
+armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
+armar -r tx.a tx_initialize_low_level.o tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o
+armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
+armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
+armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
+armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
+armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
+armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
+armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
+armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
+armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
+armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o 
+armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
+armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
+armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
+armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
+armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
+armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
+armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
+armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
+armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
+armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
+armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o 
+armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
+armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
+armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o 
+armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o 
+armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o 
+armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
+armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
+armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
+armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
+armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o 
+armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
+armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o
diff --git a/ports/cortex_m4/ac5/example_build/build_threadx_sample.bat b/ports/cortex_m4/ac5/example_build/build_threadx_sample.bat
new file mode 100644
index 00000000..cf7a2d50
--- /dev/null
+++ b/ports/cortex_m4/ac5/example_build/build_threadx_sample.bat
@@ -0,0 +1,4 @@
+armasm -g --cpu=cortex-m4 --apcs=interwork tx_initialize_low_level.s
+armcc -c -g --cpu=cortex-m4 -O2 -I../../../../common/inc -I../inc sample_threadx.c
+armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --rw-base=0x20000000 --first __tx_vectors --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a
+
diff --git a/ports/cortex_m4/ac5/example_build/sample_threadx.c b/ports/cortex_m4/ac5/example_build/sample_threadx.c
new file mode 100644
index 00000000..418ec634
--- /dev/null
+++ b/ports/cortex_m4/ac5/example_build/sample_threadx.c
@@ -0,0 +1,369 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include "tx_api.h"
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_BYTE_POOL_SIZE     9120
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+/* Define main entry point.  */
+
+int main()
+{
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s
new file mode 100644
index 00000000..dc0fdd8b
--- /dev/null
+++ b/ports/cortex_m4/ac5/example_build/tx_initialize_low_level.s
@@ -0,0 +1,267 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Initialize                                                          */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_initialize.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IMPORT  _tx_thread_system_stack_ptr
+    IMPORT  _tx_initialize_unused_memory
+    IMPORT  _tx_thread_context_save
+    IMPORT  _tx_thread_context_restore
+    IMPORT  _tx_timer_interrupt
+    IMPORT  __main
+    IMPORT  |Image$$RO$$Limit|
+    IMPORT  |Image$$RW$$Base|
+    IMPORT  |Image$$ZI$$Base|
+    IMPORT  |Image$$ZI$$Limit|
+    IMPORT  __tx_PendSVHandler
+;
+;
+SYSTEM_CLOCK        EQU     6000000
+SYSTICK_CYCLES      EQU     ((SYSTEM_CLOCK / 100) -1)
+;
+;
+;/* Setup the stack and heap areas.  */
+;
+STACK_SIZE          EQU     0x00000400
+HEAP_SIZE           EQU     0x00000000
+
+    AREA    STACK, NOINIT, READWRITE, ALIGN=3
+StackMem
+    SPACE   STACK_SIZE
+__initial_sp
+
+
+    AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+HeapMem
+    SPACE   HEAP_SIZE
+__heap_limit
+
+
+    AREA    RESET, CODE, READONLY
+;
+    EXPORT  __tx_vectors
+__tx_vectors
+    DCD     __initial_sp                            ; Reset and system stack ptr
+    DCD     Reset_Handler                           ; Reset goes to startup function
+    DCD     __tx_NMIHandler                         ; NMI
+    DCD     __tx_BadHandler                         ; HardFault
+    DCD     0                                       ; MemManage
+    DCD     0                                       ; BusFault
+    DCD     0                                       ; UsageFault
+    DCD     0                                       ; 7
+    DCD     0                                       ; 8
+    DCD     0                                       ; 9
+    DCD     0                                       ; 10
+    DCD     __tx_SVCallHandler                      ; SVCall
+    DCD     __tx_DBGHandler                         ; Monitor
+    DCD     0                                       ; 13
+    DCD     __tx_PendSVHandler                      ; PendSV
+    DCD     __tx_SysTickHandler                     ; SysTick
+    DCD     __tx_IntHandler                         ; Int 0
+    DCD     __tx_IntHandler                         ; Int 1
+    DCD     __tx_IntHandler                         ; Int 2
+    DCD     __tx_IntHandler                         ; Int 3
+        
+;
+;
+    AREA ||.text||, CODE, READONLY
+    EXPORT  Reset_Handler
+Reset_Handler
+    CPSID   i
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    LDR     r0, =0xE000ED88                         ; Pickup address of CPACR
+    LDR     r1, [r0]                                ; Pickup CPACR
+    MOV32   r2, 0x00F00000                          ; Build enable value
+    ORR     r1, r1, r2                              ; Or in enable value
+    STR     r1, [r0]                                ; Setup CPACR
+    ENDIF
+    LDR     r0, =__main
+    BX      r0
+
+
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_initialize_low_level                          Cortex-M4/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation.                            */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for any low-level processor            */
+;/*    initialization, including setting up interrupt vectors, setting     */
+;/*    up a periodic timer interrupt source, saving the system stack       */
+;/*    pointer for use in ISR processing later, and finding the first      */
+;/*    available RAM memory address for tx_application_define.             */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_initialize_low_level(VOID)
+;{
+    EXPORT  _tx_initialize_low_level
+_tx_initialize_low_level
+;
+;    /* Disable interrupts during ThreadX initialization.  */
+;
+    CPSID   i
+;
+;    /* Set base of available memory to end of non-initialised RAM area.  */
+;     
+    LDR     r0, =_tx_initialize_unused_memory       ; Build address of unused memory pointer
+    LDR     r1, =|Image$$ZI$$Limit|                 ; Build first free address
+    ADD     r1, r1, #4                              ; 
+    STR     r1, [r0]                                ; Setup first unused memory pointer
+;
+;    /* Setup Vector Table Offset Register.  */
+;    
+    MOV     r0, #0xE000E000                         ; Build address of NVIC registers
+    LDR     r1, =__tx_vectors                       ; Pickup address of vector table
+    STR     r1, [r0, #0xD08]                        ; Set vector table address   
+;
+;    /* Enable the cycle count register.  */
+;
+;    LDR     r0, =0xE0001000                         ; Build address of DWT register
+;    LDR     r1, [r0]                                ; Pickup the current value
+;    ORR     r1, r1, #1                              ; Set the CYCCNTENA bit
+;    STR     r1, [r0]                                ; Enable the cycle count register 
+;
+;    /* Set system stack pointer from vector value.  */
+;
+    LDR     r0, =_tx_thread_system_stack_ptr        ; Build address of system stack pointer
+    LDR     r1, =__tx_vectors                       ; Pickup address of vector table
+    LDR     r1, [r1]                                ; Pickup reset stack pointer
+    STR     r1, [r0]                                ; Save system stack pointer
+;
+;    /* Configure SysTick.  */
+;
+    MOV     r0, #0xE000E000                         ; Build address of NVIC registers
+    LDR     r1, =SYSTICK_CYCLES
+    STR     r1, [r0, #0x14]                         ; Setup SysTick Reload Value
+    MOV     r1, #0x7                                ; Build SysTick Control Enable Value
+    STR     r1, [r0, #0x10]                         ; Setup SysTick Control
+;
+;    /* Configure handler priorities.  */
+;
+    LDR     r1, =0x00000000                         ; Rsrv, UsgF, BusF, MemM
+    STR     r1, [r0, #0xD18]                        ; Setup System Handlers 4-7 Priority Registers
+
+    LDR     r1, =0xFF000000                         ; SVCl, Rsrv, Rsrv, Rsrv
+    STR     r1, [r0, #0xD1C]                        ; Setup System Handlers 8-11 Priority Registers
+                                                    ; Note: SVC must be lowest priority, which is 0xFF
+
+    LDR     r1, =0x40FF0000                         ; SysT, PnSV, Rsrv, DbgM
+    STR     r1, [r0, #0xD20]                        ; Setup System Handlers 12-15 Priority Registers
+                                                    ; Note: PnSV must be lowest priority, which is 0xFF
+;
+;    /* Return to caller.  */
+;    
+    BX      lr 
+;}
+;
+;       
+;/* Define initial heap/stack routine for the ARM RVCT startup code.
+;   This routine will set the initial stack and heap locations */
+;
+    EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+    LDR     r0, =HeapMem
+    LDR     r1, =(StackMem + STACK_SIZE)
+    LDR     r2, =(HeapMem + HEAP_SIZE)
+    LDR     r3, =StackMem
+    BX      lr
+;
+;
+;/* Define shells for each of the unused vectors.  */
+;
+    EXPORT  __tx_BadHandler
+__tx_BadHandler 
+    B       __tx_BadHandler
+
+    EXPORT  __tx_SVCallHandler
+__tx_SVCallHandler
+    B       __tx_SVCallHandler 
+
+    EXPORT  __tx_IntHandler
+__tx_IntHandler
+; VOID InterruptHandler (VOID)
+; {
+    PUSH    {r0, lr}
+        
+;    /* Do interrupt handler work here */
+;    /* .... */
+
+    POP     {r0, lr}
+    BX      LR
+; }
+
+        EXPORT  __tx_SysTickHandler
+__tx_SysTickHandler
+; VOID TimerInterruptHandler (VOID)
+; {
+;
+    PUSH    {r0, lr}
+    BL      _tx_timer_interrupt
+    POP     {r0, lr}
+    BX      LR
+; }
+
+    EXPORT  __tx_NMIHandler 
+__tx_NMIHandler
+    B       __tx_NMIHandler
+
+    EXPORT  __tx_DBGHandler
+__tx_DBGHandler
+    B       __tx_DBGHandler
+
+    ALIGN
+    LTORG
+    END
+
diff --git a/ports/cortex_m4/ac5/inc/tx_port.h b/ports/cortex_m4/ac5/inc/tx_port.h
new file mode 100644
index 00000000..76bccfa6
--- /dev/null
+++ b/ports/cortex_m4/ac5/inc/tx_port.h
@@ -0,0 +1,471 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */
+/*                                                                        */
+/*    tx_port.h                                         Cortex-M4/AC5     */
+/*                                                           6.0.1        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file contains data type definitions that make the ThreadX      */
+/*    real-time kernel function identically on a variety of different     */
+/*    processor architectures.  For example, the size or number of bits   */
+/*    in an "int" data type vary between microprocessor architectures and */
+/*    even C compilers for the same microprocessor.  ThreadX does not     */
+/*    directly use native C data types.  Instead, ThreadX creates its     */
+/*    own special types that can be mapped to actual data types by this   */
+/*    file to guarantee consistency in the interface and functionality.   */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include 
+#include 
+
+
+/* Define ThreadX basic types for this port.  */
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */
+#endif
+
+
+/* Define various constants for the ThreadX Cortex-M3 port.  */
+
+#define TX_INT_DISABLE                          1           /* Disable interrupts               */
+#define TX_INT_ENABLE                           0           /* Enable interrupts                */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_MISRA_ENABLE
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0xE0001004)  
+#endif
+#else
+ULONG   _tx_misra_time_stamp_get(VOID);
+#define TX_TRACE_TIME_SOURCE                    _tx_misra_time_stamp_get()
+#endif
+
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          (0)
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#ifdef TX_MISRA_ENABLE
+#define TX_DISABLE_INLINE
+#else
+#define TX_INLINE_INITIALIZATION
+#endif
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifndef TX_MISRA_ENABLE
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#define TX_THREAD_EXTENSION_2                   
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+
+
+#ifndef TX_MISRA_ENABLE
+
+register unsigned int _ipsr __asm("ipsr");
+
+#endif
+
+
+#ifdef __TARGET_FPU_VFP
+
+#ifdef TX_MISRA_ENABLE
+
+ULONG  _tx_misra_control_get(void);
+void   _tx_misra_control_set(ULONG value);
+ULONG  _tx_misra_fpccr_get(void);
+void   _tx_misra_vfp_touch(void);
+
+#else
+
+#ifdef TX_SOURCE_CODE
+
+register ULONG  _control __asm("control");
+
+#endif
+#endif
+
+/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA
+   in order to ensure no lazy stacking will occur. */
+
+#ifndef TX_MISRA_ENABLE
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)                   {                                                                                             \
+                                                                    ULONG  _tx_vfp_state;                                                                         \
+                                                                        _tx_vfp_state =  _control;                                                                \
+                                                                        _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                          \
+                                                                        _control =       _tx_vfp_state;                                                           \
+                                                                    }
+#else
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)                   {                                                                                             \
+                                                                    ULONG  _tx_vfp_state;                                                                         \
+                                                                        _tx_vfp_state =  _tx_misra_control_get();                                                 \
+                                                                        _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                          \
+                                                                        _tx_misra_control_set(_tx_vfp_state);                                                     \
+                                                                    }
+                                                                    
+#endif
+
+/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR.
+   If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating
+   this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush 
+   the lazy FPU save, then restore the CONTROL.FPCA state. */
+
+#ifndef TX_MISRA_ENABLE
+
+void _tx_vfp_access(void);
+
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  {                                                                                             \
+                                                                    ULONG  _tx_system_state;                                                                      \
+                                                                        _tx_system_state =  TX_THREAD_GET_SYSTEM_STATE();                                         \
+                                                                        if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr))        \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_vfp_state;                                                                     \
+                                                                            _tx_vfp_state =  _control;                                                            \
+                                                                            _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                      \
+                                                                            _control =       _tx_vfp_state;                                                       \
+                                                                        }                                                                                         \
+                                                                        else                                                                                      \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_fpccr;                                                                         \
+                                                                            _tx_fpccr =  *((ULONG *) 0xE000EF34);                                                 \
+                                                                            _tx_fpccr =  _tx_fpccr & ((ULONG) 0x01);                                              \
+                                                                            if (_tx_fpccr == ((ULONG) 0x01))                                                      \
+                                                                            {                                                                                     \
+                                                                            ULONG _tx_vfp_state;                                                                  \
+                                                                                _tx_vfp_state =  _control;                                                        \
+                                                                                _tx_vfp_state =  _tx_vfp_state & ((ULONG) 0x4);                                   \
+                                                                                _tx_vfp_access();                                                                 \
+                                                                                if (_tx_vfp_state == ((ULONG) 0))                                                 \
+                                                                                {                                                                                 \
+                                                                                    _tx_vfp_state =  _control;                                                    \
+                                                                                    _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                              \
+                                                                                    _control =       _tx_vfp_state;                                               \
+                                                                                }                                                                                 \
+                                                                            }                                                                                     \
+                                                                        }                                                                                         \
+                                                                    }
+#else
+
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  {                                                                                             \
+                                                                    ULONG  _tx_system_state;                                                                      \
+                                                                        _tx_system_state =  TX_THREAD_GET_SYSTEM_STATE();                                         \
+                                                                        if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr))        \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_vfp_state;                                                                     \
+                                                                            _tx_vfp_state =  _tx_misra_control_get();                                             \
+                                                                            _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                      \
+                                                                            _tx_misra_control_set(_tx_vfp_state);                                                 \
+                                                                        }                                                                                         \
+                                                                        else                                                                                      \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_fpccr;                                                                         \
+                                                                            _tx_fpccr =  _tx_misra_fpccr_get();                                                   \
+                                                                            _tx_fpccr =  _tx_fpccr & ((ULONG) 0x01);                                              \
+                                                                            if (_tx_fpccr == ((ULONG) 0x01))                                                      \
+                                                                            {                                                                                     \
+                                                                            ULONG _tx_vfp_state;                                                                  \
+                                                                                _tx_vfp_state = _tx_misra_control_get();                                          \
+                                                                                _tx_vfp_state =  _tx_vfp_state & ((ULONG) 0x4);                                   \
+                                                                                _tx_misra_vfp_touch();                                                            \
+                                                                                if (_tx_vfp_state == ((ULONG) 0))                                                 \
+                                                                                {                                                                                 \
+                                                                                    _tx_vfp_state =  _tx_misra_control_get();                                     \
+                                                                                    _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                              \
+                                                                                    _tx_misra_control_set(_tx_vfp_state);                                         \
+                                                                                }                                                                                 \
+                                                                            }                                                                                     \
+                                                                        }                                                                                         \
+                                                                    }
+#endif
+
+#else
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  
+
+#endif
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Define the get system state macro.   */
+   
+#ifndef TX_THREAD_GET_SYSTEM_STATE
+#ifndef TX_MISRA_ENABLE
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | _ipsr)
+#else
+ULONG   _tx_misra_ipsr_get(VOID);
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | _tx_misra_ipsr_get())
+#endif
+#endif
+
+
+/* Define the check for whether or not to call the _tx_thread_system_return function.  A non-zero value
+   indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h
+   for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always
+   zero after initialization for Cortex-M ports. */
+
+#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
+#define TX_THREAD_SYSTEM_RETURN_CHECK(c)    (c) = ((ULONG) _tx_thread_preempt_disable); 
+#endif
+
+
+/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to 
+   prevent early scheduling on Cortex-M parts.  */
+   
+#define TX_PORT_SPECIFIC_POST_INITIALIZATION    _tx_thread_preempt_disable++;
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef TX_DISABLE_INLINE
+   
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       (b) =  (UINT) __clz(__rbit((m)));
+
+#endif
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifdef TX_DISABLE_INLINE
+
+UINT                                            _tx_thread_interrupt_disable(VOID);
+VOID                                            _tx_thread_interrupt_restore(UINT previous_posture);
+
+#define TX_INTERRUPT_SAVE_AREA                  register UINT interrupt_save;
+
+#define TX_DISABLE                              interrupt_save = _tx_thread_interrupt_disable();
+
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+
+#else
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int  was_masked;
+#define TX_DISABLE                              was_masked = __disable_irq();
+#define TX_RESTORE                              if (was_masked == 0) __enable_irq();
+
+#define _tx_thread_system_return                _tx_thread_system_return_inline
+
+
+static void _tx_thread_system_return_inline(void)
+{
+unsigned int          was_masked;
+
+
+    /* Set PendSV to invoke ThreadX scheduler.  */
+    *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    if (_ipsr == 0)
+    {
+        was_masked = __disable_irq();
+        __enable_irq();
+        if (was_masked != 0)
+            __disable_irq();
+    }
+}
+#endif
+
+
+/* Define FPU extension for the Cortex-M4.  Each is assumed to be called in the context of the executing
+   thread. These are no longer needed, but are preserved for backward compatibility only.  */
+
+void    tx_thread_fpu_enable(void);
+void    tx_thread_fpu_disable(void);
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  * ThreadX Cortex-M4/AC5 Version 6.0 *";
+#else
+#ifdef TX_MISRA_ENABLE
+extern  CHAR                    _tx_version_id[100];
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+#endif
+
+
+#endif
+
+
+
+
diff --git a/ports/cortex_m4/ac5/readme_threadx.txt b/ports/cortex_m4/ac5/readme_threadx.txt
new file mode 100644
index 00000000..cfd9ae0b
--- /dev/null
+++ b/ports/cortex_m4/ac5/readme_threadx.txt
@@ -0,0 +1,207 @@
+                     Microsoft's Azure RTOS ThreadX for Cortex-M4 
+
+                            Using ARM Compiler 5 (AC5)
+
+
+1.  Building the ThreadX run-time Library
+
+First make sure you are in the "example_build" directory. Also, make sure that 
+you have setup your path and other environment variables necessary for the AC5 
+development environment. At this point you may run the build_threadx.bat batch
+file. This will build the ThreadX run-time environment in the "example_build"
+directory. 
+
+You should observe assembly and compilation of a series of ThreadX source 
+files. At the end of the batch file, they are all combined into the 
+run-time library file: tx.a. This file must be linked with your 
+application in order to use ThreadX.
+
+
+2.  Demonstration System
+
+The ThreadX demonstration is designed to execute under the ARM
+Windows-based simulator.
+
+Building the demonstration is easy; simply execute the build_threadx_sample.bat 
+batch file while inside the "example_build" directory. 
+
+You should observe the compilation of sample_threadx.c (which is the demonstration 
+application) and linking with tx.a. The resulting file sample_threadx.axf 
+is a binary file that can be downloaded and executed on the ARM simulator.
+
+
+3.  System Initialization
+
+The entry point in ThreadX for the Cortex-M4 using AC5 tools is at label 
+__main. This is defined within the AC5 compiler's startup code. In 
+addition, this is where all static and global pre-set C variable 
+initialization processing takes place.
+
+The ThreadX tx_initialize_low_level.s file is responsible for setting up 
+various system data structures, the vector area, and a periodic timer interrupt 
+source. 
+
+In addition, _tx_initialize_low_level determines the first available 
+address for use by the application, which is supplied as the sole input 
+parameter to your application definition function, tx_application_define.
+
+
+4.  Register Usage and Stack Frames
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have the same stack frame in the Cortex-M4 version of
+ThreadX. The top of the suspended thread's stack is pointed to by 
+tx_thread_stack_ptr in the associated thread control block TX_THREAD.
+
+Non-FPU Stack Frame:
+
+  Stack Offset     Stack Contents 
+
+     0x00               r4
+     0x04               r5
+     0x08               r6
+     0x0C               r7
+     0x10               r8
+     0x14               r9
+     0x18               r10
+     0x1C               r11
+     0x20               r0          (Hardware stack starts here!!)
+     0x24               r1
+     0x28               r2
+     0x2C               r3
+     0x30               r12
+     0x34               lr
+     0x38               pc
+     0x3C               xPSR
+
+FPU Stack Frame (only interrupted thread with FPU enabled):
+
+  Stack Offset     Stack Contents 
+
+     0x00               s0
+     0x04               s1
+     0x08               s2
+     0x0C               s3
+     0x10               s4
+     0x14               s5
+     0x18               s6
+     0x1C               s7
+     0x20               s8
+     0x24               s9
+     0x28               s10
+     0x2C               s11
+     0x30               s12
+     0x34               s13
+     0x38               s14
+     0x3C               s15
+     0x40               s16
+     0x44               s17
+     0x48               s18
+     0x4C               s19
+     0x50               s20
+     0x54               s21
+     0x58               s22
+     0x5C               s23
+     0x60               s24
+     0x64               s25
+     0x68               s26
+     0x6C               s27
+     0x70               s28
+     0x74               s29
+     0x78               s30
+     0x7C               s31
+     0x80               fpscr
+     0x84               r4          
+     0x88               r5          
+     0x8C               r6          
+     0x90               r7          
+     0x94               r8          
+     0x98               r9          
+     0x9C               r10 (sl)    
+     0xA0               r11         
+     0xA4               r0          (Hardware stack starts here!!)
+     0xA8               r1          
+     0xAC               r2          
+     0xB0               r3          
+     0xB4               r12         
+     0xB8               lr          
+     0xBC               pc          
+     0xC0               xPSR        
+
+
+5.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+breakpoints inside of ThreadX itself. Of course, this costs some 
+performance. To make it run faster, you can change the ThreadX_Library.Uv2 
+project to debugging and enable all compiler optimizations. 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+6.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-M4
+targets. There are a certain set of requirements that are defined in the 
+following sub-sections:
+
+
+6.1  Vector Area
+
+The Cortex-M4 vectors start at the label __tx_vectors. The application may modify
+the vector area according to its needs.
+
+
+6.2 Managed Interrupts
+
+ISRs for Cortex-M can be written completely in C (or assembly language) without any
+calls to _tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed
+access to the ThreadX API that is available to ISRs.
+
+ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
+
+void    your_C_isr(void)
+{
+
+    /* ISR processing goes here, including any needed function calls.  */
+}
+
+ISRs written in assembly language will take the form:
+
+    EXPORT  your_assembly_isr
+your_assembly_isr
+
+    PUSH    {r0, lr}
+
+    ; ISR processing goes here, including any needed function calls.
+
+    POP     {r0, lr}
+    BX      lr
+
+
+7. FPU Support
+
+ThreadX for Cortex-M4 supports automatic ("lazy") VFP support, which means that applications threads 
+can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread 
+context - no additional setup by the application.
+
+
+
+8.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX 6.0.1 version for Cortex-M4 using AC5 tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_m4/ac5/src/tx_thread_context_restore.s b/ports/cortex_m4/ac5/src/tx_thread_context_restore.s
new file mode 100644
index 00000000..6d310a17
--- /dev/null
+++ b/ports/cortex_m4/ac5/src/tx_thread_context_restore.s
@@ -0,0 +1,94 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT  _tx_execution_isr_exit
+    ENDIF
+;
+;
+    AREA    ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_context_restore                        Cortex-M4/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function restores the interrupt context if it is processing a  */
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */
+;/*    if no thread was running, the function returns to the scheduler.    */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_schedule                   Thread scheduling routine     */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ISRs                                  Interrupt Service Routines    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_restore(VOID)
+;{
+    EXPORT  _tx_thread_context_restore
+_tx_thread_context_restore
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR exit function to indicate an ISR is complete.  */
+;
+    PUSH    {r0,lr}                                 ; Save ISR lr
+    BL      _tx_execution_isr_exit                  ; Call the ISR exit function
+    POP     {r0,lr}                                 ; Restore ISR lr
+    ENDIF
+;
+    POP     {lr}
+    BX      lr
+;}
+    ALIGN
+    LTORG
+    END
diff --git a/ports/cortex_m4/ac5/src/tx_thread_context_save.s b/ports/cortex_m4/ac5/src/tx_thread_context_save.s
new file mode 100644
index 00000000..052c3e5a
--- /dev/null
+++ b/ports/cortex_m4/ac5/src/tx_thread_context_save.s
@@ -0,0 +1,94 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT  _tx_execution_isr_enter
+    ENDIF
+;
+;
+    AREA    ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_context_save                           Cortex-M4/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function saves the context of an executing thread in the       */
+;/*    beginning of interrupt processing.  The function also ensures that  */
+;/*    the system stack is used upon return to the calling ISR.            */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ISRs                                                                */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_save(VOID)
+;{
+    EXPORT  _tx_thread_context_save
+_tx_thread_context_save
+   IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {r0, lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter                 ; Call the ISR enter function
+    POP     {lr0, r}                                ; Recover ISR lr
+    ENDIF
+;
+;    /* Return to interrupt processing.  */
+;     
+    BX      lr                                      ; Return to interrupt processing caller
+;}
+    ALIGN
+    LTORG
+    END
diff --git a/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s
new file mode 100644
index 00000000..e97c7a47
--- /dev/null
+++ b/ports/cortex_m4/ac5/src/tx_thread_interrupt_control.s
@@ -0,0 +1,80 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_control                      Cortex-M4/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for changing the interrupt lockout     */
+;/*    posture of the system.                                              */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    new_posture                           New interrupt lockout posture */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    old_posture                           Old interrupt lockout posture */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_control(UINT new_posture)
+;{
+    EXPORT  _tx_thread_interrupt_control
+_tx_thread_interrupt_control
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    MRS     r1, PRIMASK
+    MSR     PRIMASK, r0
+    MOV     r0, r1
+    BX      lr
+;
+;}
+    END
+    
diff --git a/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s
new file mode 100644
index 00000000..e366e44b
--- /dev/null
+++ b/ports/cortex_m4/ac5/src/tx_thread_interrupt_disable.s
@@ -0,0 +1,78 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_disable                      Cortex-M4/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation.                            */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for disabling interrupts and returning */
+;/*    the previous interrupt lockout posture.                             */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    old_posture                           Old interrupt lockout posture */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_disable(UINT new_posture)
+;{
+    EXPORT  _tx_thread_interrupt_disable
+_tx_thread_interrupt_disable
+;
+;    /* Return current interrupt lockout posture.  */
+;
+    MRS     r0, PRIMASK
+    CPSID   i
+    BX      lr
+;
+;}
+    END
diff --git a/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s
new file mode 100644
index 00000000..1d0bffb6
--- /dev/null
+++ b/ports/cortex_m4/ac5/src/tx_thread_interrupt_restore.s
@@ -0,0 +1,77 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_restore                      Cortex-M4/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation.                            */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for restoring the previous             */
+;/*    interrupt lockout posture.                                          */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    previous_posture                      Previous interrupt posture    */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_interrupt_restore(UINT new_posture)
+;{
+    EXPORT  _tx_thread_interrupt_restore
+_tx_thread_interrupt_restore
+;
+;    /* Restore previous interrupt lockout posture.  */
+;
+    MSR     PRIMASK, r0
+    BX      lr
+;
+;}
+    END
diff --git a/ports/cortex_m4/ac5/src/tx_thread_schedule.s b/ports/cortex_m4/ac5/src/tx_thread_schedule.s
new file mode 100644
index 00000000..e78a040d
--- /dev/null
+++ b/ports/cortex_m4/ac5/src/tx_thread_schedule.s
@@ -0,0 +1,293 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;   
+    IMPORT  _tx_thread_current_ptr
+    IMPORT  _tx_thread_execute_ptr
+    IMPORT  _tx_timer_time_slice
+    IMPORT  _tx_thread_system_stack_ptr
+    IMPORT  _tx_thread_preempt_disable
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT  _tx_execution_thread_enter
+    IMPORT  _tx_execution_thread_exit        
+    ENDIF
+;
+;
+    AREA    ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_schedule                               Cortex-M4/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function waits for a thread control block pointer to appear in */
+;/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
+;/*    in the variable, the corresponding thread is resumed.               */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter          ThreadX entry function         */
+;/*    _tx_thread_system_return             Return to system from thread   */
+;/*    _tx_thread_context_restore           Restore thread's context       */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_schedule(VOID)
+;{
+        EXPORT  _tx_thread_schedule
+_tx_thread_schedule
+;
+;    /* This function should only ever be called on Cortex-M
+;       from the first schedule request. Subsequent scheduling occurs
+;       from the PendSV handling routines below. */
+;
+;    /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets.  */
+;     
+    MOV     r0, #0                                  ; Build value for TX_FALSE
+    LDR     r2, =_tx_thread_preempt_disable         ; Build address of preempt disable flag
+    STR     r0, [r2, #0]                            ; Clear preempt disable flag
+;
+;    /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked.  */
+;
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    MRS     r0, CONTROL                             ; Pickup current CONTROL register
+    BIC     r0, r0, #4                              ; Clear the FPCA bit 
+    MSR     CONTROL, r0                             ; Setup new CONTROL register
+    ENDIF
+;
+;    /* Enable the interrupts */
+;
+    CPSIE   i
+;       
+;    /* Enter the scheduler for the first time.  */
+;
+    MOV     r0, #0x10000000                         ; Load PENDSVSET bit
+    MOV     r1, #0xE000E000                         ; Load NVIC base
+    STR     r0, [r1, #0xD04]                        ; Set PENDSVBIT in ICSR
+    DSB                                             ; Complete all memory accesses
+    ISB                                             ; Flush pipeline
+;
+;    /* Wait here for the PendSV to take place.  */
+;     
+__tx_wait_here
+    B       __tx_wait_here                          ; Wait for the PendSV to happen
+;}
+;
+;    /* Generic context switching PendSV handler.  */
+;     
+        EXPORT  __tx_PendSVHandler
+        EXPORT  PendSV_Handler
+__tx_PendSVHandler  
+PendSV_Handler
+;
+;    /* Get current thread value and new thread pointer.  */
+;       
+__tx_ts_handler 
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread exit function to indicate the thread is no longer executing.  */
+;
+    CPSID   i                                       ; Disable interrupts
+    PUSH    {r0, lr}                                ; Save LR (and r0 just for alignment)
+    BL      _tx_execution_thread_exit               ; Call the thread exit function
+    POP     {r0, lr}                                ; Recover LR
+    CPSIE   i                                       ; Enable interrupts
+    ENDIF
+    MOV32   r0, _tx_thread_current_ptr              ; Build current thread pointer address
+    MOV32   r2, _tx_thread_execute_ptr              ; Build execute thread pointer address
+    MOV     r3, #0                                  ; Build NULL value
+    LDR     r1, [r0]                                ; Pickup current thread pointer
+;
+;    /* Determine if there is a current thread to finish preserving.  */
+;       
+    CBZ     r1, __tx_ts_new                         ; If NULL, skip preservation
+;
+;    /* Recover PSP and preserve current thread context.  */
+;
+    STR     r3, [r0]                                ; Set _tx_thread_current_ptr to NULL
+    MRS     r12, PSP                                ; Pickup PSP pointer (thread's stack pointer)
+    STMDB   r12!, {r4-r11}                          ; Save its remaining registers
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    TST     LR, #0x10                               ; Determine if the VFP extended frame is present
+    BNE     _skip_vfp_save
+    VSTMDB  r12!,{s16-s31}                          ; Yes, save additional VFP registers
+_skip_vfp_save
+    ENDIF
+    MOV32   r4, _tx_timer_time_slice                ; Build address of time-slice variable
+    STMDB   r12!, {LR}                              ; Save LR on the stack
+;
+;    /* Determine if time-slice is active. If it isn't, skip time handling processing.  */
+;
+    LDR     r5, [r4]                                ; Pickup current time-slice
+    STR     r12, [r1, #8]                           ; Save the thread stack pointer
+    CBZ     r5, __tx_ts_new                         ; If not active, skip processing
+;
+;    /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable.  */
+;
+    STR     r5, [r1, #24]                           ; Save current time-slice
+;
+;    /* Clear the global time-slice.  */
+;
+    STR     r3, [r4]                                ; Clear time-slice
+;       
+;    /* Executing thread is now completely preserved!!!  */
+;
+__tx_ts_new 
+;
+;    /* Now we are looking for a new thread to execute!  */
+;
+    CPSID   i                                       ; Disable interrupts
+    LDR     r1, [r2]                                ; Is there another thread ready to execute?
+    CBZ     r1, __tx_ts_wait                        ; No, skip to the wait processing
+;
+;    /* Yes, another thread is ready for else, make the current thread the new thread.  */
+;
+    STR     r1, [r0]                                ; Setup the current thread pointer to the new thread
+    CPSIE   i                                       ; Enable interrupts
+;
+;    /* Increment the thread run count.  */
+;
+__tx_ts_restore 
+    LDR     r7, [r1, #4]                            ; Pickup the current thread run count
+    MOV32   r4, _tx_timer_time_slice                ; Build address of time-slice variable
+    LDR     r5, [r1, #24]                           ; Pickup thread's current time-slice
+    ADD     r7, r7, #1                              ; Increment the thread run count
+    STR     r7, [r1, #4]                            ; Store the new run count
+;
+;    /* Setup global time-slice with thread's current time-slice.  */
+;
+    STR     r5, [r4]                                ; Setup global time-slice
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread entry function to indicate the thread is executing.  */
+;
+    PUSH    {r0, r1}                                ; Save r0/r1
+    BL      _tx_execution_thread_enter              ; Call the thread execution enter function
+    POP     {r0, r1}                                ; Recover r3
+    ENDIF
+;
+;    /* Restore the thread context and PSP.  */
+;
+    LDR     r12, [r1, #8]                           ; Pickup thread's stack pointer
+    LDMIA   r12!, {LR}                              ; Pickup LR
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    TST     LR, #0x10                               ; Determine if the VFP extended frame is present
+    BNE     _skip_vfp_restore                       ; If not, skip VFP restore 
+    VLDMIA  r12!, {s16-s31}                         ; Yes, restore additional VFP registers
+_skip_vfp_restore
+    ENDIF
+    LDMIA   r12!, {r4-r11}                          ; Recover thread's registers
+    MSR     PSP, r12                                ; Setup the thread's stack pointer
+;
+;    /* Return to thread.  */
+;       
+        BX      lr                                  ; Return to thread!
+;
+;    /* The following is the idle wait processing... in this case, no threads are ready for execution and the
+;       system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts 
+;       are disabled to allow use of WFI for waiting for a thread to arrive.  */
+;
+__tx_ts_wait    
+    CPSID   i                                       ; Disable interrupts
+    LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
+    STR     r1, [r0]                                ; Store it in the current pointer
+    CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+    IF :DEF:TX_ENABLE_WFI
+    DSB                                             ; Ensure no outstanding memory transactions
+    WFI                                             ; Wait for interrupt
+    ISB                                             ; Ensure pipeline is flushed
+    ENDIF
+    CPSIE   i                                       ; Enable interrupts
+    B       __tx_ts_wait                            ; Loop to continue waiting
+;
+;    /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are 
+;       already in the handler!  */
+;
+__tx_ts_ready   
+    MOV     r7, #0x08000000                         ; Build clear PendSV value
+    MOV     r8, #0xE000E000                         ; Build base NVIC address
+    STR     r7, [r8, #0xD04]                        ; Clear any PendSV 
+;
+;    /* Re-enable interrupts and restore new thread.  */
+;       
+    CPSIE   i                                       ; Enable interrupts
+    B       __tx_ts_restore                         ; Restore the thread
+
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    EXPORT  tx_thread_fpu_enable
+tx_thread_fpu_enable
+;
+;    /* Automatic VPF logic is supported, this function is present only for 
+;       backward compatibility purposes and therefore simply returns.  */
+;
+    BX      LR                                      ; Return to caller
+
+    EXPORT  tx_thread_fpu_disable
+tx_thread_fpu_disable
+;
+;    /* Automatic VPF logic is supported, this function is present only for 
+;       backward compatibility purposes and therefore simply returns.  */
+;
+    BX      LR                                      ; Return to caller
+
+    EXPORT  _tx_vfp_access
+_tx_vfp_access
+    VMOV.F32 s0, s0                                 ; Simply access the VFP
+    BX       lr                                     ; Return to caller
+
+
+    ENDIF
+
+    ALIGN
+    LTORG
+    END
+    
diff --git a/ports/cortex_m4/ac5/src/tx_thread_stack_build.s b/ports/cortex_m4/ac5/src/tx_thread_stack_build.s
new file mode 100644
index 00000000..d9cf2a1f
--- /dev/null
+++ b/ports/cortex_m4/ac5/src/tx_thread_stack_build.s
@@ -0,0 +1,138 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_stack_build                            Cortex-M4/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function builds a stack frame on the supplied thread's stack.  */
+;/*    The stack frame results in a fake interrupt return to the supplied  */
+;/*    function pointer.                                                   */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    thread_ptr                            Pointer to thread control blk */
+;/*    function_ptr                          Pointer to return function    */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_thread_create                     Create thread service         */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+;{
+    EXPORT  _tx_thread_stack_build
+_tx_thread_stack_build
+;
+;       
+;    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+;       on the Cortex-M4 should look like the following after it is built:
+;       
+;       Stack Top:      
+;                       LR          Interrupted LR (LR at time of PENDSV)
+;                       r4          Initial value for r4
+;                       r5          Initial value for r5
+;                       r6          Initial value for r6
+;                       r7          Initial value for r7
+;                       r8          Initial value for r8
+;                       r9          Initial value for r9
+;                       r10         Initial value for r10
+;                       r11         Initial value for r11
+;                       r0          Initial value for r0    (Hardware stack starts here!!)
+;                       r1          Initial value for r1
+;                       r2          Initial value for r2
+;                       r3          Initial value for r3
+;                       r12         Initial value for r12
+;                       lr          Initial value for lr
+;                       pc          Initial value for pc
+;                       xPSR        Initial value for xPSR
+;
+;    Stack Bottom: (higher memory address)  */
+;
+    LDR     r2, [r0, #16]                           ; Pickup end of stack area
+    BIC     r2, r2, #0x7                            ; Align frame for 8-byte alignment
+    SUB     r2, r2, #68                             ; Subtract frame size
+    LDR     r3, =0xFFFFFFFD                         ; Build initial LR value
+    STR     r3, [r2, #0]                            ; Save on the stack
+;
+;    /* Actually build the stack frame.  */
+;
+    MOV     r3, #0                                  ; Build initial register value
+    STR     r3, [r2, #4]                            ; Store initial r4
+    STR     r3, [r2, #8]                            ; Store initial r5
+    STR     r3, [r2, #12]                           ; Store initial r6
+    STR     r3, [r2, #16]                           ; Store initial r7
+    STR     r3, [r2, #20]                           ; Store initial r8
+    STR     r3, [r2, #24]                           ; Store initial r9
+    STR     r3, [r2, #28]                           ; Store initial r10
+    STR     r3, [r2, #32]                           ; Store initial r11
+;
+;    /* Hardware stack follows.  /
+;
+    STR     r3, [r2, #36]                           ; Store initial r0
+    STR     r3, [r2, #40]                           ; Store initial r1
+    STR     r3, [r2, #44]                           ; Store initial r2
+    STR     r3, [r2, #48]                           ; Store initial r3
+    STR     r3, [r2, #52]                           ; Store initial r12
+    MOV     r3, #0xFFFFFFFF                         ; Poison EXC_RETURN value
+    STR     r3, [r2, #56]                           ; Store initial lr
+    STR     r1, [r2, #60]                           ; Store initial pc
+    MOV     r3, #0x01000000                         ; Only T-bit need be set
+    STR     r3, [r2, #64]                           ; Store initial xPSR
+;
+;    /* Setup stack pointer.  */
+;    thread_ptr -> tx_thread_stack_ptr =  r2;
+;
+    STR     r2, [r0, #8]                            ; Save stack pointer in thread's
+                                                    ;   control block
+    BX      lr                                      ; Return to caller
+;}
+    END
+
diff --git a/ports/cortex_m4/ac5/src/tx_thread_system_return.s b/ports/cortex_m4/ac5/src/tx_thread_system_return.s
new file mode 100644
index 00000000..c61d0e53
--- /dev/null
+++ b/ports/cortex_m4/ac5/src/tx_thread_system_return.s
@@ -0,0 +1,91 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+;
+    AREA    ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_system_return                          Cortex-M4/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is target processor specific.  It is used to transfer */
+;/*    control from a thread back to the ThreadX system.  Only a           */
+;/*    minimal context is saved since the compiler assumes temp registers  */
+;/*    are going to get slicked by a function call anyway.                 */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_schedule                   Thread scheduling loop        */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ThreadX components                                                  */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_system_return(VOID)
+;{
+    EXPORT  _tx_thread_system_return
+_tx_thread_system_return
+;
+;    /* Return to real scheduler via PendSV. Note that this routine is often 
+;       replaced with in-line assembly in tx_port.h to improved performance.  */
+;     
+    MOV     r0, #0x10000000                         ; Load PENDSVSET bit
+    MOV     r1, #0xE000E000                         ; Load NVIC base
+    STR     r0, [r1, #0xD04]                        ; Set PENDSVBIT in ICSR
+    MRS     r0, IPSR                                ; Pickup IPSR
+    CMP     r0, #0                                  ; Is it a thread returning?
+    BNE     _isr_context                            ; If ISR, skip interrupt enable
+    MRS     r1, PRIMASK                             ; Thread context returning, pickup PRIMASK
+    CPSIE   i                                       ; Enable interrupts
+    MSR     PRIMASK, r1                             ; Restore original interrupt posture
+_isr_context
+    BX      lr                                      ; Return to caller 
+;}
+    END  
+    
diff --git a/ports/cortex_m4/ac5/src/tx_timer_interrupt.s b/ports/cortex_m4/ac5/src/tx_timer_interrupt.s
new file mode 100644
index 00000000..af94c70c
--- /dev/null
+++ b/ports/cortex_m4/ac5/src/tx_timer_interrupt.s
@@ -0,0 +1,266 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Timer                                                               */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_timer.h"
+;#include "tx_thread.h"
+;
+;
+;Define Assembly language external references...
+;
+    IMPORT      _tx_timer_time_slice
+    IMPORT      _tx_timer_system_clock
+    IMPORT      _tx_timer_current_ptr
+    IMPORT      _tx_timer_list_start
+    IMPORT      _tx_timer_list_end
+    IMPORT      _tx_timer_expired_time_slice
+    IMPORT      _tx_timer_expired
+    IMPORT      _tx_thread_time_slice
+    IMPORT      _tx_timer_expiration_process
+    IMPORT      _tx_thread_preempt_disable
+    IMPORT      _tx_thread_current_ptr
+    IMPORT      _tx_thread_execute_ptr
+;
+;
+    AREA ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_timer_interrupt                               Cortex-M4/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function processes the hardware timer interrupt.  This         */
+;/*    processing includes incrementing the system clock and checking for  */
+;/*    time slice and/or timer expiration.  If either is found, the        */
+;/*    interrupt context save/restore functions are called along with the  */
+;/*    expiration functions.                                               */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_timer_expiration_process          Timer expiration processing   */
+;/*    _tx_thread_time_slice                 Time slice interrupted thread */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    interrupt vector                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_timer_interrupt(VOID)
+;{
+    EXPORT  _tx_timer_interrupt
+_tx_timer_interrupt
+;
+;    /* Upon entry to this routine, it is assumed that context save has already
+;       been called, and therefore the compiler scratch registers are available
+;       for use.  */
+;
+;    /* Increment the system clock.  */
+;    _tx_timer_system_clock++;
+;
+    MOV32   r1, _tx_timer_system_clock              ; Pickup address of system clock
+    LDR     r0, [r1, #0]                            ; Pickup system clock
+    ADD     r0, r0, #1                              ; Increment system clock
+    STR     r0, [r1, #0]                            ; Store new system clock
+;
+;    /* Test for time-slice expiration.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    MOV32   r3, _tx_timer_time_slice                ; Pickup address of time-slice 
+    LDR     r2, [r3, #0]                            ; Pickup time-slice
+    CBZ     r2,  __tx_timer_no_time_slice           ; Is it non-active?
+                                                    ; Yes, skip time-slice processing
+;
+;       /* Decrement the time_slice.  */
+;       _tx_timer_time_slice--;
+;
+    SUB     r2, r2, #1                              ; Decrement the time-slice
+    STR     r2, [r3, #0]                            ; Store new time-slice value
+;
+;       /* Check for expiration.  */
+;       if (__tx_timer_time_slice == 0)
+;
+    CBNZ    r2, __tx_timer_no_time_slice            ; Has it expired?
+;
+;       /* Set the time-slice expired flag.  */
+;       _tx_timer_expired_time_slice =  TX_TRUE;
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup address of expired flag
+    MOV     r0, #1                                  ; Build expired value
+    STR     r0, [r3, #0]                            ; Set time-slice expiration flag
+;
+;    }
+;
+__tx_timer_no_time_slice
+;
+;    /* Test for timer expiration.  */
+;    if (*_tx_timer_current_ptr)
+;    {
+;
+    MOV32   r1, _tx_timer_current_ptr               ; Pickup current timer pointer address
+    LDR     r0, [r1, #0]                            ; Pickup current timer
+    LDR     r2, [r0, #0]                            ; Pickup timer list entry
+    CBZ     r2, __tx_timer_no_timer                 ; Is there anything in the list?
+                                                    ; No, just increment the timer
+;
+;        /* Set expiration flag.  */
+;        _tx_timer_expired =  TX_TRUE;
+;
+    MOV32   r3, _tx_timer_expired                   ; Pickup expiration flag address
+    MOV     r2, #1                                  ; Build expired value
+    STR     r2, [r3, #0]                            ; Set expired flag
+    B       __tx_timer_done                         ; Finished timer processing
+;
+;    }
+;    else
+;    {
+__tx_timer_no_timer
+;
+;        /* No timer expired, increment the timer pointer.  */
+;        _tx_timer_current_ptr++;
+;
+    ADD     r0, r0, #4                              ; Move to next timer
+;
+;        /* Check for wrap-around.  */
+;        if (_tx_timer_current_ptr == _tx_timer_list_end)
+;
+    MOV32   r3, _tx_timer_list_end                  ; Pickup addr of timer list end
+    LDR     r2, [r3, #0]                            ; Pickup list end
+    CMP     r0, r2                                  ; Are we at list end?
+    BNE     __tx_timer_skip_wrap                    ; No, skip wrap-around logic
+;
+;            /* Wrap to beginning of list.  */
+;            _tx_timer_current_ptr =  _tx_timer_list_start;
+;
+    MOV32   r3, _tx_timer_list_start                ; Pickup addr of timer list start
+    LDR     r0, [r3, #0]                            ; Set current pointer to list start
+;
+__tx_timer_skip_wrap
+;
+    STR     r0, [r1, #0]                            ; Store new current timer pointer
+;    }
+;
+__tx_timer_done
+;
+;
+;    /* See if anything has expired.  */
+;    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+;    {
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup addr of expired flag
+    LDR     r2, [r3, #0]                            ; Pickup time-slice expired flag
+    CBNZ    r2, __tx_something_expired              ; Did a time-slice expire?
+                                                    ; If non-zero, time-slice expired
+    MOV32   r1, _tx_timer_expired                   ; Pickup addr of other expired flag
+    LDR     r0, [r1, #0]                            ; Pickup timer expired flag
+    CBZ     r0, __tx_timer_nothing_expired          ; Did a timer expire?
+                                                    ; No, nothing expired
+;
+__tx_something_expired
+;
+;
+    STMDB   sp!, {r0, lr}                           ; Save the lr register on the stack
+                                                    ;   and save r0 just to keep 8-byte alignment
+;
+;    /* Did a timer expire?  */
+;    if (_tx_timer_expired)
+;    {
+;
+    MOV32   r1, _tx_timer_expired                   ; Pickup addr of expired flag
+    LDR     r0, [r1, #0]                            ; Pickup timer expired flag
+    CBZ     r0, __tx_timer_dont_activate            ; Check for timer expiration
+                                                    ; If not set, skip timer activation
+;
+;        /* Process timer expiration.  */
+;        _tx_timer_expiration_process();
+;
+    BL      _tx_timer_expiration_process            ; Call the timer expiration handling routine
+;
+;    }
+__tx_timer_dont_activate
+;
+;    /* Did time slice expire?  */
+;    if (_tx_timer_expired_time_slice)
+;    {
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup addr of time-slice expired 
+    LDR     r2, [r3, #0]                            ; Pickup the actual flag
+    CBZ     r2, __tx_timer_not_ts_expiration        ; See if the flag is set
+                                                    ; No, skip time-slice processing
+;
+;        /* Time slice interrupted thread.  */
+;        _tx_thread_time_slice(); 
+
+    BL      _tx_thread_time_slice                   ; Call time-slice processing
+    MOV32   r0, _tx_thread_preempt_disable          ; Build address of preempt disable flag
+    LDR     r1, [r0]                                ; Is the preempt disable flag set?
+    CBNZ    r1, __tx_timer_skip_time_slice          ; Yes, skip the PendSV logic
+    MOV32   r0, _tx_thread_current_ptr              ; Build current thread pointer address
+    LDR     r1, [r0]                                ; Pickup the current thread pointer
+    MOV32   r2, _tx_thread_execute_ptr              ; Build execute thread pointer address
+    LDR     r3, [r2]                                ; Pickup the execute thread pointer
+    MOV32   r0, 0xE000ED04                          ; Build address of control register
+    MOV32   r2, 0x10000000                          ; Build value for PendSV bit
+    CMP     r1, r3                                  ; Are they the same?
+    BEQ     __tx_timer_skip_time_slice              ; If the same, there was no time-slice performed
+    STR     r2, [r0]                                ; Not the same, issue the PendSV for preemption
+__tx_timer_skip_time_slice
+;
+;    }
+;
+__tx_timer_not_ts_expiration
+;
+    LDMIA   sp!, {r0, lr}                           ; Recover lr register (r0 is just there for
+;
+;    }
+;
+__tx_timer_nothing_expired
+
+    DSB                                             ; Complete all memory access
+    BX      lr                                      ; Return to caller
+;
+;}
+    ALIGN
+    LTORG
+    END
+
diff --git a/ports/cortex_m4/gnu/CMakeLists.txt b/ports/cortex_m4/gnu/CMakeLists.txt
index cb3091b9..71e2d4f2 100644
--- a/ports/cortex_m4/gnu/CMakeLists.txt
+++ b/ports/cortex_m4/gnu/CMakeLists.txt
@@ -9,7 +9,6 @@ target_sources(${PROJECT_NAME}
 	${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
 	${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
 	${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
-
     # {{END_TARGET_SOURCES}}
 )
 
diff --git a/ports/cortex_m4/gnu/example_build/build_threadx.bat b/ports/cortex_m4/gnu/example_build/build_threadx.bat
new file mode 100644
index 00000000..062092d3
--- /dev/null
+++ b/ports/cortex_m4/gnu/example_build/build_threadx.bat
@@ -0,0 +1,229 @@
+del tx.a
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb tx_initialize_low_level.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_thread_stack_build.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_thread_schedule.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_thread_system_return.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_thread_context_save.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_thread_context_restore.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_thread_interrupt_control.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_timer_interrupt.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb ../src/tx_thread_interrupt_control.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c
+arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
+arm-none-eabi-ar -r tx.a tx_thread_interrupt_control.o tx_initialize_low_level.o
+arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
+arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
+arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
+arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
+arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
+arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
+arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
+arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
+arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
+arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o 
+arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
+arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
+arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
+arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
+arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
+arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
+arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
+arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
+arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
+arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
+arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o 
+arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
+arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
+arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o 
+arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o 
+arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o 
+arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
+arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
+arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
+arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
+arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o 
+arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
+arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o
diff --git a/ports/cortex_m4/gnu/example_build/build_threadx_sample.bat b/ports/cortex_m4/gnu/example_build/build_threadx_sample.bat
new file mode 100644
index 00000000..fd75f7bd
--- /dev/null
+++ b/ports/cortex_m4/gnu/example_build/build_threadx_sample.bat
@@ -0,0 +1,7 @@
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb tx_simulator_startup.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb cortexm4_crt0.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb tx_initialize_low_level.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m4 -mthumb -I../../../../common/inc -I../inc sample_threadx.c
+arm-none-eabi-ld -A cortex-m4 -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm4_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a  libc.a -o sample_threadx.out -M > sample_threadx.map
+
+
diff --git a/ports/cortex_m4/gnu/example_build/cortexm4_crt0.s b/ports/cortex_m4/gnu/example_build/cortexm4_crt0.s
new file mode 100644
index 00000000..d4cb1636
--- /dev/null
+++ b/ports/cortex_m4/gnu/example_build/cortexm4_crt0.s
@@ -0,0 +1,127 @@
+ .global _start
+  .extern main
+
+
+  .section .init, "ax"
+  .code 16
+  .align 2
+  .thumb_func
+
+
+_start:
+  CPSID   i
+  ldr r1, =__stack_end__
+  mov sp, r1
+
+
+  /* Copy initialised sections into RAM if required. */
+  ldr r0, =__data_load_start__
+  ldr r1, =__data_start__
+  ldr r2, =__data_end__
+  bl crt0_memory_copy
+  ldr r0, =__text_load_start__
+  ldr r1, =__text_start__
+  ldr r2, =__text_end__
+  bl crt0_memory_copy
+  ldr r0, =__fast_load_start__
+  ldr r1, =__fast_start__
+  ldr r2, =__fast_end__
+  bl crt0_memory_copy
+  ldr r0, =__ctors_load_start__
+  ldr r1, =__ctors_start__
+  ldr r2, =__ctors_end__
+  bl crt0_memory_copy
+  ldr r0, =__dtors_load_start__
+  ldr r1, =__dtors_start__
+  ldr r2, =__dtors_end__
+  bl crt0_memory_copy
+  ldr r0, =__rodata_load_start__
+  ldr r1, =__rodata_start__
+  ldr r2, =__rodata_end__
+  bl crt0_memory_copy
+
+
+  /* Zero bss. */
+  ldr r0, =__bss_start__
+  ldr r1, =__bss_end__
+  mov r2, #0
+  bl crt0_memory_set
+
+
+  /* Setup heap - not recommended for Threadx but here for compatibility reasons */
+  ldr r0, = __heap_start__
+  ldr r1, = __heap_end__
+  sub r1, r1, r0
+  mov r2, #0
+  str r2, [r0]
+  add r0, r0, #4
+  str r1, [r0]
+
+
+  /* constructors in case of using C++ */
+  ldr r0, =__ctors_start__
+  ldr r1, =__ctors_end__
+crt0_ctor_loop:
+  cmp r0, r1
+  beq crt0_ctor_end
+  ldr r2, [r0]
+  add r0, #4
+  push {r0-r1}  
+  blx r2
+  pop {r0-r1}
+  b crt0_ctor_loop
+crt0_ctor_end:
+
+
+  /* Setup call frame for main() */
+  mov r0, #0
+  mov lr, r0
+  mov r12, sp
+
+
+start:
+  /* Jump to main() */
+  mov r0, #0
+  mov r1, #0
+  ldr r2, =main
+  blx r2
+  /*  when main returns, loop forever. */
+crt0_exit_loop:
+  b crt0_exit_loop
+  
+
+
+  /* Startup helper functions. */
+
+
+crt0_memory_copy:
+  cmp r0, r1
+  beq memory_copy_done
+  sub r2, r2, r1
+  beq memory_copy_done
+memory_copy_loop:
+  ldrb r3, [r0]
+  add r0, r0, #1
+  strb r3, [r1]
+  add r1, r1, #1
+  sub r2, r2, #1
+  bne memory_copy_loop
+memory_copy_done:
+  bx lr
+
+
+crt0_memory_set:
+  cmp r0, r1
+  beq memory_set_done
+  strb r2, [r0]
+  add r0, r0, #1
+  b crt0_memory_set
+memory_set_done:
+  bx lr
+
+
+  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
+  .section .stack, "wa", %nobits
+  .section .stack_process, "wa", %nobits
+  .section .heap, "wa", %nobits
+  
\ No newline at end of file
diff --git a/ports/cortex_m4/gnu/example_build/libc.a b/ports/cortex_m4/gnu/example_build/libc.a
new file mode 100644
index 0000000000000000000000000000000000000000..6c1567d15e3b2f049d1acd9038ac4fcd28005c18
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diff --git a/ports/cortex_m4/gnu/example_build/sample_threadx.c b/ports/cortex_m4/gnu/example_build/sample_threadx.c
new file mode 100644
index 00000000..597f373c
--- /dev/null
+++ b/ports/cortex_m4/gnu/example_build/sample_threadx.c
@@ -0,0 +1,370 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include "tx_api.h"
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_BYTE_POOL_SIZE     9120
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+UCHAR                   memory_area[DEMO_BYTE_POOL_SIZE];
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+/* Define main entry point.  */
+
+int main()
+{
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/cortex_m4/gnu/example_build/sample_threadx.ld b/ports/cortex_m4/gnu/example_build/sample_threadx.ld
new file mode 100644
index 00000000..28f203fd
--- /dev/null
+++ b/ports/cortex_m4/gnu/example_build/sample_threadx.ld
@@ -0,0 +1,206 @@
+MEMORY
+{
+  UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0
+  CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000
+  AHB_Peripherals (wx) : ORIGIN = 0x50000000, LENGTH = 0x00200000
+  APB1_Peripherals (wx) : ORIGIN = 0x40080000, LENGTH = 0x00080000
+  APB0_Peripherals (wx) : ORIGIN = 0x40000000, LENGTH = 0x00080000
+  GPIO (wx) : ORIGIN = 0x2009c000, LENGTH = 0x00004000
+  AHBSRAM1 (wx) : ORIGIN = 0x20080000, LENGTH = 0x00004000
+  AHBSRAM0 (wx) : ORIGIN = 0x2007c000, LENGTH = 0x00004000
+  RAM (wx) : ORIGIN = 0x10000000, LENGTH = 0x00008000
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
+}
+
+
+SECTIONS
+{
+  __CM3_System_Control_Space_segment_start__ = 0xe000e000;
+  __CM3_System_Control_Space_segment_end__ = 0xe000f000;
+  __AHB_Peripherals_segment_start__ = 0x50000000;
+  __AHB_Peripherals_segment_end__ = 0x50200000;
+  __APB1_Peripherals_segment_start__ = 0x40080000;
+  __APB1_Peripherals_segment_end__ = 0x40100000;
+  __APB0_Peripherals_segment_start__ = 0x40000000;
+  __APB0_Peripherals_segment_end__ = 0x40080000;
+  __GPIO_segment_start__ = 0x2009c000;
+  __GPIO_segment_end__ = 0x200a0000;
+  __AHBSRAM1_segment_start__ = 0x20080000;
+  __AHBSRAM1_segment_end__ = 0x20084000;
+  __AHBSRAM0_segment_start__ = 0x2007c000;
+  __AHBSRAM0_segment_end__ = 0x20080000;
+  __RAM_segment_start__ = 0x10000000;
+  __RAM_segment_end__ = 0x10008000;
+  __FLASH_segment_start__ = 0x00000000;
+  __FLASH_segment_end__ = 0x00080000;
+
+  __STACKSIZE__ = 1024;
+  __STACKSIZE_PROCESS__ = 0;
+  __STACKSIZE_IRQ__ = 0;
+  __STACKSIZE_FIQ__ = 0;
+  __STACKSIZE_SVC__ = 0;
+  __STACKSIZE_ABT__ = 0;
+  __STACKSIZE_UND__ = 0;
+  __HEAPSIZE__ = 128;
+
+  __vectors_load_start__ = __FLASH_segment_start__;
+  .vectors __FLASH_segment_start__ : AT(__FLASH_segment_start__)
+  {
+    __vectors_start__ = .;
+    *(.vectors .vectors.*)
+  }
+  __vectors_end__ = __vectors_start__ + SIZEOF(.vectors);
+
+  . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .vectors is too large to fit in FLASH memory segment");
+
+  __init_load_start__ = ALIGN(__vectors_end__ , 4);
+  .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4))
+  {
+    __init_start__ = .;
+    *(.init .init.*)
+  }
+  __init_end__ = __init_start__ + SIZEOF(.init);
+
+  . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .init is too large to fit in FLASH memory segment");
+
+  __text_load_start__ = ALIGN(__init_end__ , 4);
+  .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4))
+  {
+    __text_start__ = .;
+    *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table)
+  }
+  __text_end__ = __text_start__ + SIZEOF(.text);
+
+  . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .text is too large to fit in FLASH memory segment");
+
+  __dtors_load_start__ = ALIGN(__text_end__ , 4);
+  .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4))
+  {
+    __dtors_start__ = .;
+    KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors))
+  }
+  __dtors_end__ = __dtors_start__ + SIZEOF(.dtors);
+
+  . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .dtors is too large to fit in FLASH memory segment");
+
+  __ctors_load_start__ = ALIGN(__dtors_end__ , 4);
+  .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4))
+  {
+    __ctors_start__ = .;
+    KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors))
+  }
+  __ctors_end__ = __ctors_start__ + SIZEOF(.ctors);
+
+  . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .ctors is too large to fit in FLASH memory segment");
+
+  __rodata_load_start__ = ALIGN(__ctors_end__ , 4);
+  .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4))
+  {
+    __rodata_start__ = .;
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+  }
+  __rodata_end__ = __rodata_start__ + SIZEOF(.rodata);
+
+  . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .rodata is too large to fit in FLASH memory segment");
+
+  __fast_load_start__ = ALIGN(__rodata_end__ , 4);
+  .fast ALIGN(__RAM_segment_start__ , 4) : AT(ALIGN(__rodata_end__ , 4))
+  {
+    __fast_start__ = .;
+    *(.fast .fast.*)
+  }
+  __fast_end__ = __fast_start__ + SIZEOF(.fast);
+
+  __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast);
+
+  . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .fast is too large to fit in FLASH memory segment");
+
+  .fast_run ALIGN(__RAM_segment_start__ , 4) (NOLOAD) :
+  {
+    __fast_run_start__ = .;
+    . = MAX(__fast_run_start__ + SIZEOF(.fast), .);
+  }
+  __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run);
+
+  . = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .fast_run is too large to fit in RAM memory segment");
+
+  __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4);
+  .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4))
+  {
+    __data_start__ = .;
+    *(.data .data.* .gnu.linkonce.d.*)
+  }
+  __data_end__ = __data_start__ + SIZEOF(.data);
+
+  __data_load_end__ = __data_load_start__ + SIZEOF(.data);
+
+  __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data);
+
+  . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .data is too large to fit in FLASH memory segment");
+
+  .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) :
+  {
+    __data_run_start__ = .;
+    . = MAX(__data_run_start__ + SIZEOF(.data), .);
+  }
+  __data_run_end__ = __data_run_start__ + SIZEOF(.data_run);
+
+  . = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .data_run is too large to fit in RAM memory segment");
+
+  __bss_load_start__ = ALIGN(__data_run_end__ , 4);
+  .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4))
+  {
+    __bss_start__ = .;
+    *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
+  }
+  __bss_end__ = __bss_start__ + SIZEOF(.bss);
+
+  . = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .bss is too large to fit in RAM memory segment");
+
+  __non_init_load_start__ = ALIGN(__bss_end__ , 4);
+  .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4))
+  {
+    __non_init_start__ = .;
+    *(.non_init .non_init.*)
+  }
+  __non_init_end__ = __non_init_start__ + SIZEOF(.non_init);
+
+  . = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .non_init is too large to fit in RAM memory segment");
+
+  __heap_load_start__ = ALIGN(__non_init_end__ , 4);
+  .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4))
+  {
+    __heap_start__ = .;
+    *(.heap)
+    . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4);
+  }
+  __heap_end__ = __heap_start__ + SIZEOF(.heap);
+
+  . = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .heap is too large to fit in RAM memory segment");
+
+  __stack_load_start__ = ALIGN(__heap_end__ , 4);
+  .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4))
+  {
+    __stack_start__ = .;
+    *(.stack)
+    . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4);
+  }
+  __stack_end__ = __stack_start__ + SIZEOF(.stack);
+
+  . = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack is too large to fit in RAM memory segment");
+
+  __stack_process_load_start__ = ALIGN(__stack_end__ , 4);
+  .stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4))
+  {
+    __stack_process_start__ = .;
+    *(.stack_process)
+    . = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4);
+  }
+  __stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process);
+
+  __RAM_segment_used_end__ = ALIGN(__stack_end__ , 4) + SIZEOF(.stack_process);
+
+  . = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack_process is too large to fit in RAM memory segment");
+
+}
+
diff --git a/ports/cortex_m4/gnu/src/tx_initialize_low_level_sample.S b/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S
similarity index 95%
rename from ports/cortex_m4/gnu/src/tx_initialize_low_level_sample.S
rename to ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S
index ce57f6e7..00db7ac2 100644
--- a/ports/cortex_m4/gnu/src/tx_initialize_low_level_sample.S
+++ b/ports/cortex_m4/gnu/example_build/tx_initialize_low_level.S
@@ -59,7 +59,7 @@ SYSTICK_CYCLES    =   ((SYSTEM_CLOCK / 100) -1)
 @/*  FUNCTION                                               RELEASE        */
 @/*                                                                        */
 @/*    _tx_initialize_low_level                          Cortex-M4/GNU     */
-@/*                                                           6.0          */
+@/*                                                           6.0.1        */
 @/*  AUTHOR                                                                */
 @/*                                                                        */
 @/*    William E. Lamie, Microsoft Corporation                             */
@@ -93,6 +93,9 @@ SYSTICK_CYCLES    =   ((SYSTEM_CLOCK / 100) -1)
 @/*    DATE              NAME                      DESCRIPTION             */
 @/*                                                                        */
 @/*  05-19-2020     William E. Lamie         Initial Version 6.0           */
+@/*  06-30-2020     William E. Lamie         Modified Comment(s), fixed    */
+@/*                                            GNU assembly comment,       */
+@/*                                            resulting in version 6.0.1  */                
 @/*                                                                        */
 @/**************************************************************************/
 @VOID   _tx_initialize_low_level(VOID)
@@ -191,14 +194,14 @@ __tx_IntHandler:
 @ {
     PUSH    {r0, lr}
 #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
-    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
 #endif       
 
 @    /* Do interrupt handler work here */
 @    /* BL .... */
 
 #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
-    BL      _tx_execution_isr_exit              ; Call the ISR exit function
+    BL      _tx_execution_isr_exit              @ Call the ISR exit function
 #endif
     POP     {r0, lr}
     BX      LR
@@ -216,11 +219,11 @@ SysTick_Handler:
 @
     PUSH    {r0, lr}
 #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
-    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
 #endif
     BL      _tx_timer_interrupt
 #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
-    BL      _tx_execution_isr_exit              ; Call the ISR exit function
+    BL      _tx_execution_isr_exit              @ Call the ISR exit function
 #endif
     POP     {r0, lr}
     BX      LR
diff --git a/ports/cortex_m4/gnu/src/tx_vector_table_sample.S b/ports/cortex_m4/gnu/example_build/tx_simulator_startup.s
similarity index 100%
rename from ports/cortex_m4/gnu/src/tx_vector_table_sample.S
rename to ports/cortex_m4/gnu/example_build/tx_simulator_startup.s
diff --git a/ports/cortex_m4/gnu/readme_threadx.txt b/ports/cortex_m4/gnu/readme_threadx.txt
new file mode 100644
index 00000000..a8c7c684
--- /dev/null
+++ b/ports/cortex_m4/gnu/readme_threadx.txt
@@ -0,0 +1,218 @@
+                     Microsoft's Azure RTOS ThreadX for Cortex-M4 
+
+                              Using the GNU Tools
+
+1.  Building the ThreadX run-time Library
+
+First make sure you are in the "example_build" directory. Also, make sure that 
+you have setup your path and other environment variables necessary for the ARM 
+gnu (GNU) compiler. At this point you may run the build_threadx.bat batch file. 
+This will build the ThreadX run-time environment in the "example_build" 
+directory. 
+
+You should observe assembly and compilation of a series of ThreadX source 
+files. At the end of the batch file, they are all combined into the 
+run-time library file: tx.a. This file must be linked with your 
+application in order to use ThreadX.
+
+
+2.  Demonstration System for Cortex-M4
+
+The ThreadX demonstration is designed to execute on Cortex-M4 evaluation boards
+or on a dedicated simulator.
+
+Building the demonstration is easy, simply execute the build_threadx_sample.bat 
+batch file while inside the "example_build" directory. 
+
+You should observe the compilation of sample_threadx.c (which is the demonstration 
+application) and linking with tx.a. The resulting file sample_threadx.out is a binary 
+file that can be downloaded and executed on the a simulator, or downloaded to a board.
+
+
+3.  System Initialization
+
+The entry point in ThreadX for the Cortex-M4 using gnu tools uses the standard GNU 
+Cortex-M4 reset sequence. From the reset vector the C runtime will be initialized.
+
+The ThreadX tx_initialize_low_level.S file is responsible for setting up 
+various system data structures, the vector area, and a periodic timer interrupt 
+source. 
+
+In addition, _tx_initialize_low_level determines the first available 
+address for use by the application, which is supplied as the sole input 
+parameter to your application definition function, tx_application_define.
+
+
+4.  Register Usage and Stack Frames
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have the same stack frame in the Cortex-M4 version of
+ThreadX. The top of the suspended thread's stack is pointed to by 
+tx_thread_stack_ptr in the associated thread control block TX_THREAD.
+
+Non-FPU Stack Frame:
+
+  Stack Offset     Stack Contents 
+
+     0x00               LR          Interrupted LR (LR at time of PENDSV)
+     0x04               r4
+     0x08               r5
+     0x0C               r6
+     0x10               r7
+     0x14               r8
+     0x18               r9
+     0x1C               r10
+     0x20               r11
+     0x24               r0          (Hardware stack starts here!!)
+     0x28               r1
+     0x2C               r2
+     0x30               r3
+     0x34               r12
+     0x38               lr
+     0x3C               pc
+     0x40               xPSR
+
+FPU Stack Frame (only interrupted thread with FPU enabled):
+
+  Stack Offset     Stack Contents 
+
+     0x00               LR          Interrupted LR (LR at time of PENDSV)
+     0x04               s0
+     0x08               s1
+     0x0C               s2
+     0x10               s3
+     0x14               s4
+     0x18               s5
+     0x1C               s6
+     0x20               s7
+     0x24               s8
+     0x28               s9
+     0x2C               s10
+     0x30               s11
+     0x34               s12
+     0x38               s13
+     0x3C               s14
+     0x40               s15
+     0x44               s16
+     0x48               s17
+     0x4C               s18
+     0x50               s19
+     0x54               s20
+     0x58               s21
+     0x5C               s22
+     0x60               s23
+     0x64               s24
+     0x68               s25
+     0x6C               s26
+     0x70               s27
+     0x74               s28
+     0x78               s29
+     0x7C               s30
+     0x80               s31
+     0x84               fpscr
+     0x88               r4          
+     0x8C               r5          
+     0x90               r6          
+     0x94               r7          
+     0x98               r8          
+     0x9C               r9          
+     0xA0               r10 (sl)    
+     0xA4               r11         
+     0xA8               r0          (Hardware stack starts here!!)
+     0xAC               r1          
+     0xB0               r2          
+     0xB4               r3          
+     0xB8               r12         
+     0xBC               lr          
+     0xC0               pc          
+     0xC4               xPSR        
+
+
+5.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler optimizations. 
+This makes it easy to debug because you can trace or set breakpoints inside of 
+ThreadX itself. Of course, this costs some performance. To make it run faster, 
+you can change the build_threadx.bat file to remove the -g option and enable 
+all compiler optimizations. 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+6.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-M4
+targets. There are a certain set of requirements that are defined in the 
+following sub-sections:
+
+
+6.1  Vector Area
+
+The Cortex-M4 vectors start at the label __tx_vectors or similar. The application may modify
+the vector area according to its needs. There is code in tx_initialize_low_level() that will 
+configure the vector base register. 
+
+
+6.2 Managed Interrupts
+
+ISRs can be written completely in C (or assembly language) without any calls to
+_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the
+ThreadX API that is available to ISRs.
+
+ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
+
+void    your_C_isr(void)
+{
+
+    /* ISR processing goes here, including any needed function calls.  */
+}
+
+ISRs written in assembly language will take the form:
+
+
+        .global  your_assembly_isr
+        .thumb_func
+your_assembly_isr:
+; VOID your_assembly_isr(VOID)
+; {
+        PUSH    {r0, lr}
+;       
+;    /* Do interrupt handler work here */
+;    /* BL  */
+
+        POP     {r0, lr}
+        BX      lr
+; }
+
+Note: the Cortex-M4 requires exception handlers to be thumb labels, this implies bit 0 set.
+To accomplish this, the declaration of the label has to be preceded by the assembler directive
+.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to 
+be inserted in the correct location in the interrupt vector table. This table is typically 
+located in either your runtime startup file or in the tx_initialize_low_level.S file.
+
+
+7. FPU Support
+
+ThreadX for Cortex-M4 supports automatic ("lazy") VFP support, which means that applications threads 
+can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread 
+context. If saving the context of the FPU registers is needed, the ThreadX library should be re-built 
+with TX_ENABLE_FPU_SUPPORT defined.
+
+
+8.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+05/19/2020  Initial ThreadX 6.0 version for Cortex-M4 using GNU tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_m4/gnu/src/tx_thread_stack_build.S b/ports/cortex_m4/gnu/src/tx_thread_stack_build.S
index f9ca6842..9307686e 100644
--- a/ports/cortex_m4/gnu/src/tx_thread_stack_build.S
+++ b/ports/cortex_m4/gnu/src/tx_thread_stack_build.S
@@ -38,7 +38,7 @@
 @/*  FUNCTION                                               RELEASE        */
 @/*                                                                        */
 @/*    _tx_thread_stack_build                            Cortex-M4/GNU     */
-@/*                                                           6.0          */
+@/*                                                           6.0.1        */
 @/*  AUTHOR                                                                */
 @/*                                                                        */
 @/*    William E. Lamie, Microsoft Corporation                             */
@@ -71,6 +71,11 @@
 @/*    DATE              NAME                      DESCRIPTION             */
 @/*                                                                        */
 @/*  05-19-2020     William E. Lamie         Initial Version 6.0           */
+@/*  06-30-2020     William E. Lamie         Modified Comment(s), setting  */
+@/*                                             R10 to top of stack is not */
+@/*                                             needed. Removed references */
+@/*                                             to stack frame, resulting  */
+@/*                                             in version 6.0.1           */
 @/*                                                                        */
 @/**************************************************************************/
 @VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@@ -91,7 +96,7 @@ _tx_thread_stack_build:
 @                       r7          Initial value for r7
 @                       r8          Initial value for r8
 @                       r9          Initial value for r9
-@                       r10 (sl)    Initial value for r10 (sl)
+@                       r10         Initial value for r10
 @                       r11         Initial value for r11
 @                       r0          Initial value for r0    (Hardware stack starts here!!)
 @                       r1          Initial value for r1
@@ -119,9 +124,7 @@ _tx_thread_stack_build:
     STR     r3, [r2, #16]                           @ Store initial r7
     STR     r3, [r2, #20]                           @ Store initial r8
     STR     r3, [r2, #24]                           @ Store initial r9
-    LDR     r3, [r0, #12]                           @ Pickup stack starting address
-    STR     r3, [r2, #28]                           @ Store initial r10 (sl)
-    MOV     r3, #0                                  @ Build initial register value
+    STR     r3, [r2, #28]                           @ Store initial r10
     STR     r3, [r2, #32]                           @ Store initial r11
 @
 @    /* Hardware stack follows.  */
diff --git a/ports/cortex_m4/iar/example_build/azure_rtos.eww b/ports/cortex_m4/iar/example_build/azure_rtos.eww
new file mode 100644
index 00000000..17e0d329
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/azure_rtos.eww
@@ -0,0 +1,13 @@
+
+
+
+  
+    $WS_DIR$\sample_threadx.ewp
+  
+  
+    $WS_DIR$\tx.ewp
+  
+  
+
+
+
diff --git a/ports/cortex_m4/iar/example_build/cstartup_M.s b/ports/cortex_m4/iar/example_build/cstartup_M.s
new file mode 100644
index 00000000..75d9369b
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/cstartup_M.s
@@ -0,0 +1,73 @@
+        EXTERN  __iar_program_start
+        PUBLIC  __vector_table
+
+        SECTION .text:CODE:REORDER(1)
+        
+        ;; Keep vector table even if it's not referenced
+        REQUIRE __vector_table
+        
+        THUMB
+        
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+        SECTION .intvec:CODE:NOROOT(2)
+        
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     __Reset_Vector
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+
+        PUBWEAK NMI_Handler
+        PUBWEAK HardFault_Handler
+        PUBWEAK MemManage_Handler
+        PUBWEAK BusFault_Handler
+        PUBWEAK UsageFault_Handler
+        PUBWEAK SVC_Handler
+        PUBWEAK DebugMon_Handler
+        PUBWEAK PendSV_Handler
+        PUBWEAK SysTick_Handler
+
+        SECTION .text:CODE:REORDER:NOROOT(1)
+        THUMB
+__Reset_Vector:
+        CPSID   i                                       ; Disable interrupts
+        B        __iar_program_start
+
+
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+SVC_Handler
+DebugMon_Handler
+PendSV_Handler
+SysTick_Handler
+Default_Handler
+__default_handler
+        CALL_GRAPH_ROOT __default_handler, "interrupt"
+        NOCALL __default_handler
+        B __default_handler
+
+        END
diff --git a/ports/cortex_m4/iar/example_build/sample_threadx.c b/ports/cortex_m4/iar/example_build/sample_threadx.c
new file mode 100644
index 00000000..60f5a3d3
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/sample_threadx.c
@@ -0,0 +1,389 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete
+   description of this demonstration.  */
+
+#include "tx_api.h"
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_BYTE_POOL_SIZE     9120
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+/* Define byte pool memory.  */
+
+UCHAR                   byte_pool_memory[DEMO_BYTE_POOL_SIZE];
+
+
+/* Define event buffer.  */
+
+#ifdef TX_ENABLE_EVENT_TRACE
+UCHAR   trace_buffer[0x10000];
+#endif
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+/* Define main entry point.  */
+
+int main()
+{
+    
+    /* Please refer to Chapter 6 of the ThreadX User Guide for a complete
+       description of this demonstration.  */
+
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+#ifdef TX_ENABLE_EVENT_TRACE
+    tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32);
+#endif
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/cortex_m4/iar/example_build/sample_threadx.dep b/ports/cortex_m4/iar/example_build/sample_threadx.dep
new file mode 100644
index 00000000..d9c41b76
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/sample_threadx.dep
@@ -0,0 +1,112 @@
+
+
+    4
+    1715762055
+    
+        Debug
+        
+            $PROJ_DIR$\sample_threadx.c
+            $PROJ_DIR$\cstartup_M.s
+            $PROJ_DIR$\Debug\Exe\tx.a
+            $PROJ_DIR$\tx_initialize_low_level.s
+            $PROJ_DIR$\Debug\Obj\tx_initialize_low_level.o
+            $TOOLKIT_DIR$\inc\c\DLib_Product.h
+            $TOOLKIT_DIR$\inc\c\yvals.h
+            $TOOLKIT_DIR$\lib\dl7M_tln.a
+            $TOOLKIT_DIR$\lib\m7M_tl.a
+            $TOOLKIT_DIR$\inc\c\DLib_Defaults.h
+            $PROJ_DIR$\sample_threadx.icf
+            $TOOLKIT_DIR$\lib\rt7M_tl.a
+            $TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h
+            $TOOLKIT_DIR$\inc\c\ysizet.h
+            $TOOLKIT_DIR$\inc\c\intrinsics.h
+            $TOOLKIT_DIR$\lib\shb_l.a
+            $TOOLKIT_DIR$\inc\c\string.h
+            $TOOLKIT_DIR$\inc\c\ycheck.h
+            $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h
+            $PROJ_DIR$\Debug\Obj\sample_threadx.xcl
+            $TOOLKIT_DIR$\inc\c\stdlib.h
+            $PROJ_DIR$\Debug\Obj\cstartup_M.o
+            $PROJ_DIR$\Debug\Obj\sample_threadx.pbd
+            $PROJ_DIR$\Debug\Exe\sample_threadx.out
+            $TOOLKIT_DIR$\inc\c\DLib_Product_string.h
+            $PROJ_DIR$\Debug\Obj\sample_threadx.o
+            $PROJ_DIR$\Debug\Obj\sample_threadx.__cstat.et
+            $PROJ_DIR$\..\..\..\..\common\inc\tx_api.h
+            $TOOLKIT_DIR$\inc\c\iar_intrinsics_common.h
+            $PROJ_DIR$\..\inc\tx_port.h
+            $TOOLKIT_DIR$\inc\c\iccarm_builtin.h
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_send.c
+        
+        
+            [ROOT_NODE]
+            
+                
+                    ILINK
+                     23
+                
+            
+        
+        
+            $PROJ_DIR$\sample_threadx.c
+            
+                
+                    ICCARM
+                     25
+                
+                
+                    __cstat
+                     26
+                
+                
+                    BICOMP
+                     19
+                
+            
+            
+                
+                    ICCARM
+                     27 29 20 17 6 9 18 5 13 12 16 24 14 30 28
+                
+            
+        
+        
+            $PROJ_DIR$\cstartup_M.s
+            
+                
+                    AARM
+                     21
+                
+            
+        
+        
+            $PROJ_DIR$\tx_initialize_low_level.s
+            
+                
+                    AARM
+                     4
+                
+            
+        
+        
+            $PROJ_DIR$\Debug\Exe\sample_threadx.out
+            
+                
+                    ILINK
+                     10 21 25 2 4 15 11 8 7
+                
+            
+        
+    
+    
+        Release
+        
+        
+            [MULTI_TOOL]
+            ILINK
+        
+        
+            [REBUILD_ALL]
+        
+    
+
diff --git a/ports/cortex_m4/iar/example_build/sample_threadx.ewd b/ports/cortex_m4/iar/example_build/sample_threadx.ewd
new file mode 100644
index 00000000..22c813a3
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/sample_threadx.ewd
@@ -0,0 +1,2974 @@
+
+
+    3
+    
+        Debug
+        
+            ARM
+        
+        1
+        
+            C-SPY
+            2
+            
+                32
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ARMSIM_ID
+            2
+            
+                1
+                1
+                1
+                
+                
+                
+                
+            
+        
+        
+            CADI_ID
+            2
+            
+                0
+                1
+                1
+                
+                
+                
+                
+                
+            
+        
+        
+            CMSISDAP_ID
+            2
+            
+                4
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            GDBSERVER_ID
+            2
+            
+                0
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IJET_ID
+            2
+            
+                8
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            JLINK_ID
+            2
+            
+                16
+                1
+                1
+                
+                
+                
+                
+                
+                
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+                
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+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            LMIFTDI_ID
+            2
+            
+                2
+                1
+                1
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            NULINK_ID
+            2
+            
+                0
+                1
+                1
+                
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+        
+            PEMICRO_ID
+            2
+            
+                3
+                1
+                1
+                
+                
+                
+                
+            
+        
+        
+            STLINK_ID
+            2
+            
+                7
+                1
+                1
+                
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+                
+                
+                
+                
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+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            THIRDPARTY_ID
+            2
+            
+                0
+                1
+                1
+                
+                
+                
+                
+            
+        
+        
+            TIFET_ID
+            2
+            
+                1
+                1
+                1
+                
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+                
+                
+                
+                
+                
+                
+                
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+                
+                
+                
+                
+            
+        
+        
+            XDS100_ID
+            2
+            
+                8
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
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+                
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+                
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+                
+                
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+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            
+                $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin
+                1
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin
+                0
+            
+            
+                $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin
+                0
+            
+        
+    
+    
+        Release
+        
+            ARM
+        
+        0
+        
+            C-SPY
+            2
+            
+                32
+                1
+                0
+                
+                
+                
+                
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+                
+                
+                
+                
+                
+                
+                
+                
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+                
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+                
+                
+                
+                
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+                
+                
+                
+                
+                
+            
+        
+        
+            ARMSIM_ID
+            2
+            
+                1
+                1
+                0
+                
+                
+                
+                
+            
+        
+        
+            CADI_ID
+            2
+            
+                0
+                1
+                0
+                
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+                
+                
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+            
+        
+        
+            CMSISDAP_ID
+            2
+            
+                4
+                1
+                0
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+                1
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+            2
+            
+                8
+                1
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+            2
+            
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+                1
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+                
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+                
+                
+            
+        
+        
+            LMIFTDI_ID
+            2
+            
+                2
+                1
+                0
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            NULINK_ID
+            2
+            
+                0
+                1
+                0
+                
+                
+                
+            
+        
+        
+            PEMICRO_ID
+            2
+            
+                3
+                1
+                0
+                
+                
+                
+                
+            
+        
+        
+            STLINK_ID
+            2
+            
+                7
+                1
+                0
+                
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+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            THIRDPARTY_ID
+            2
+            
+                0
+                1
+                0
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+            2
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+            XDS100_ID
+            2
+            
+                8
+                1
+                0
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new file mode 100644
index 00000000..4d3848a5
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/sample_threadx.ewp
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new file mode 100644
index 00000000..24445b46
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/sample_threadx.ewt
@@ -0,0 +1,2788 @@
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+                            
+                                
+                            
+                        
+                    
+                
+            
+        
+        
+            RuntimeChecking
+            0
+            
+                2
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+    
+    
+        $PROJ_DIR$\cstartup_M.s
+    
+    
+        $PROJ_DIR$\sample_threadx.c
+    
+    
+        $PROJ_DIR$\Debug\Exe\tx.a
+    
+    
+        $PROJ_DIR$\tx_initialize_low_level.s
+    
+
diff --git a/ports/cortex_m4/iar/example_build/sample_threadx.icf b/ports/cortex_m4/iar/example_build/sample_threadx.icf
new file mode 100644
index 00000000..246d387e
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/sample_threadx.icf
@@ -0,0 +1,42 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x0007FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x2001FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x200;
+define symbol __ICFEDIT_size_heap__     = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol FlashConfig_start__= 0x00000400;
+define symbol FlashConfig_end__  = 0x0000040f;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__ to (FlashConfig_start__ - 1)] | [from (FlashConfig_end__+1)  to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+define region FlashConfig_region = mem:[from FlashConfig_start__ to FlashConfig_end__];
+
+initialize by copy { readwrite };
+initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+
+place in FlashConfig_region
+                      {section FlashConfig};
+
+place in RAM_region { last section FREE_MEM};
+
diff --git a/ports/cortex_m4/iar/example_build/settings/azure_rtos.wsdt b/ports/cortex_m4/iar/example_build/settings/azure_rtos.wsdt
new file mode 100644
index 00000000..e7b3c139
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/settings/azure_rtos.wsdt
@@ -0,0 +1,535 @@
+
+
+    
+        
+            sample_threadx/Debug
+            tx/Debug
+        
+        sample_threadx
+        1
+    
+    
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+                2518
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+                
+            
+            
+                
+                    265
+                    30
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+                
+                    <ws>
+                
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+            
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+                    <Right-click on a symbol in the editor to show a call graph>
+                
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+                    C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m4\iar\example_build\Debug\Obj\sample_threadx.pbw
+                
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+
diff --git a/ports/cortex_m4/iar/example_build/settings/sample_threadx.Debug.cspy.bat b/ports/cortex_m4/iar/example_build/settings/sample_threadx.Debug.cspy.bat
new file mode 100644
index 00000000..82a22cfe
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/settings/sample_threadx.Debug.cspy.bat
@@ -0,0 +1,40 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+@echo off 
+
+if not "%~1" == "" goto debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m4\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m4\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m4\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m4\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+
+@echo off 
+:end
\ No newline at end of file
diff --git a/ports/cortex_m4/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports/cortex_m4/iar/example_build/settings/sample_threadx.Debug.cspy.ps1
new file mode 100644
index 00000000..e2a56b8d
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/settings/sample_threadx.Debug.cspy.ps1
@@ -0,0 +1,31 @@
+param([String]$debugfile = "");
+
+# This powershell file has been generated by the IAR Embedded Workbench
+# C - SPY Debugger, as an aid to preparing a command line for running
+# the cspybat command line utility using the appropriate settings.
+#
+# Note that this file is generated every time a new debug session
+# is initialized, so you may want to move or rename the file before
+# making changes.
+#
+# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
+# by the name of the debug file (usually an ELF / DWARF or UBROF file).
+#
+# Read about available command line parameters in the C - SPY Debugging
+# Guide. Hints about additional command line parameters that may be
+# useful in specific cases :
+#   --download_only   Downloads a code image without starting a debug
+#                     session afterwards.
+#   --silent          Omits the sign - on message.
+#   --timeout         Limits the maximum allowed execution time.
+#
+
+
+if ($debugfile -eq "")
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m4\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m4\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+}
+else
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m4\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m4\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+}
diff --git a/ports/cortex_m4/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports/cortex_m4/iar/example_build/settings/sample_threadx.Debug.driver.xcl
new file mode 100644
index 00000000..22bc90ef
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/settings/sample_threadx.Debug.driver.xcl
@@ -0,0 +1,13 @@
+"--endian=little" 
+
+"--cpu=Cortex-M4" 
+
+"--fpu=None" 
+
+"--semihosting" 
+
+"--multicore_nr_of_cores=1" 
+
+
+
+
diff --git a/ports/cortex_m4/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports/cortex_m4/iar/example_build/settings/sample_threadx.Debug.general.xcl
new file mode 100644
index 00000000..bb613a13
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/settings/sample_threadx.Debug.general.xcl
@@ -0,0 +1,11 @@
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" 
+
+"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m4\iar\example_build\Debug\Exe\sample_threadx.out" 
+
+--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" 
+
+
+
+
diff --git a/ports/cortex_m4/iar/example_build/settings/sample_threadx.crun b/ports/cortex_m4/iar/example_build/settings/sample_threadx.crun
new file mode 100644
index 00000000..d71ea555
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/settings/sample_threadx.crun
@@ -0,0 +1,13 @@
+
+
+    1
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diff --git a/ports/cortex_m4/iar/example_build/settings/sample_threadx.dbgdt b/ports/cortex_m4/iar/example_build/settings/sample_threadx.dbgdt
new file mode 100644
index 00000000..d85ff638
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/settings/sample_threadx.dbgdt
@@ -0,0 +1,1701 @@
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diff --git a/ports/cortex_m4/iar/example_build/settings/tx.Debug.cspy.bat b/ports/cortex_m4/iar/example_build/settings/tx.Debug.cspy.bat
new file mode 100644
index 00000000..d76cfad9
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/settings/tx.Debug.cspy.bat
@@ -0,0 +1,40 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+@echo off 
+
+if not "%~1" == "" goto debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+
+@echo off 
+:end
\ No newline at end of file
diff --git a/ports/cortex_m4/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports/cortex_m4/iar/example_build/settings/tx.Debug.cspy.ps1
new file mode 100644
index 00000000..1c1ba13b
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/settings/tx.Debug.cspy.ps1
@@ -0,0 +1,31 @@
+param([String]$debugfile = "");
+
+# This powershell file has been generated by the IAR Embedded Workbench
+# C - SPY Debugger, as an aid to preparing a command line for running
+# the cspybat command line utility using the appropriate settings.
+#
+# Note that this file is generated every time a new debug session
+# is initialized, so you may want to move or rename the file before
+# making changes.
+#
+# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
+# by the name of the debug file (usually an ELF / DWARF or UBROF file).
+#
+# Read about available command line parameters in the C - SPY Debugging
+# Guide. Hints about additional command line parameters that may be
+# useful in specific cases :
+#   --download_only   Downloads a code image without starting a debug
+#                     session afterwards.
+#   --silent          Omits the sign - on message.
+#   --timeout         Limits the maximum allowed execution time.
+#
+
+
+if ($debugfile -eq "")
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+}
+else
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+}
diff --git a/ports/cortex_m4/iar/example_build/settings/tx.Debug.driver.xcl b/ports/cortex_m4/iar/example_build/settings/tx.Debug.driver.xcl
new file mode 100644
index 00000000..22bc90ef
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/settings/tx.Debug.driver.xcl
@@ -0,0 +1,13 @@
+"--endian=little" 
+
+"--cpu=Cortex-M4" 
+
+"--fpu=None" 
+
+"--semihosting" 
+
+"--multicore_nr_of_cores=1" 
+
+
+
+
diff --git a/ports/cortex_m4/iar/example_build/settings/tx.Debug.general.xcl b/ports/cortex_m4/iar/example_build/settings/tx.Debug.general.xcl
new file mode 100644
index 00000000..ef6d6dd5
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/settings/tx.Debug.general.xcl
@@ -0,0 +1,11 @@
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armproc.dll" 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armsim2.dll" 
+
+"C:\release\threadx\Debug\Exe\tx.out" 
+
+--plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armbat.dll" 
+
+
+
+
diff --git a/ports/cortex_m4/iar/example_build/settings/tx.crun b/ports/cortex_m4/iar/example_build/settings/tx.crun
new file mode 100644
index 00000000..d71ea555
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/settings/tx.crun
@@ -0,0 +1,13 @@
+
+
+    1
+    
+        
+            *
+            *
+            *
+            0
+            1
+        
+    
+
diff --git a/ports/cortex_m4/iar/example_build/settings/tx.dbgdt b/ports/cortex_m4/iar/example_build/settings/tx.dbgdt
new file mode 100644
index 00000000..9e08d965
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/settings/tx.dbgdt
@@ -0,0 +1,4 @@
+
+
+    
+
diff --git a/ports/cortex_m4/iar/example_build/settings/tx.dnx b/ports/cortex_m4/iar/example_build/settings/tx.dnx
new file mode 100644
index 00000000..25e4c4ba
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/settings/tx.dnx
@@ -0,0 +1,58 @@
+
+
+    
+        0
+        1
+        90
+        1
+        1
+        1
+        main
+        0
+        50
+    
+    
+        0
+        1
+    
+    
+        0
+        0
+        1
+        0
+        1
+        0
+    
+    
+        0
+        0
+        1
+        0
+        1
+    
+    
+        0
+    
+    
+        0
+    
+    
+        1
+    
+    
+        1
+        0
+        1
+        0
+        1
+    
+    
+        0
+        0
+    
+    
+        10000000
+        0
+        1
+    
+
diff --git a/ports/cortex_m4/iar/example_build/tx.dep b/ports/cortex_m4/iar/example_build/tx.dep
new file mode 100644
index 00000000..53d58a7c
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/tx.dep
@@ -0,0 +1,8968 @@
+
+
+    4
+    2672330084
+    
+        Debug
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_activate.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_suspend.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_time_slice.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_delete.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_system_deactivate.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_disable.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_buffer_full_notify.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_enable.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_change.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_timeout.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_initialize.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_unfilter.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_initialize.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_interrupt_control.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_thread_entry.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_enter_insert.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_exit_insert.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_register.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_filter.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_info_get.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_performance_info_get.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_create.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_terminate.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_deactivate.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_expiration_process.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_performance_system_info_get.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_system_activate.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_time_slice_change.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_wait_abort.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_time_get.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_time_set.c
+            $PROJ_DIR$\tx_block_pool_create.c
+            $PROJ_DIR$\tx_block_pool_delete.c
+            $PROJ_DIR$\tx_block_pool_initialize.c
+            $PROJ_DIR$\tx_block_pool_performance_info_get.c
+            $PROJ_DIR$\tx_block_pool_performance_system_info_get.c
+            $PROJ_DIR$\tx_block_pool_prioritize.c
+            $PROJ_DIR$\tx_block_release.c
+            $PROJ_DIR$\tx_byte_allocate.c
+            $PROJ_DIR$\tx_byte_pool_cleanup.c
+            $PROJ_DIR$\tx_block_pool_info_get.c
+            $PROJ_DIR$\tx_block_allocate.c
+            $PROJ_DIR$\tx_block_pool_cleanup.c
+            $PROJ_DIR$\tx_mutex_initialize.c
+            $PROJ_DIR$\tx_byte_pool_info_get.c
+            $PROJ_DIR$\tx_mutex_performance_info_get.c
+            $PROJ_DIR$\tx_mutex_performance_system_info_get.c
+            $PROJ_DIR$\tx_mutex_prioritize.c
+            $PROJ_DIR$\tx_event_flags_initialize.c
+            $PROJ_DIR$\tx_event_flags_performance_info_get.c
+            $PROJ_DIR$\tx_initialize_high_level.c
+            $PROJ_DIR$\tx_event_flags_cleanup.c
+            $PROJ_DIR$\tx_mutex_create.c
+            $PROJ_DIR$\tx_initialize_kernel_setup.c
+            $PROJ_DIR$\tx_event_flags_set_notify.c
+            $PROJ_DIR$\tx_byte_pool_performance_info_get.c
+            $PROJ_DIR$\tx_byte_pool_performance_system_info_get.c
+            $PROJ_DIR$\tx_byte_pool_prioritize.c
+            $PROJ_DIR$\tx_byte_pool_search.c
+            $PROJ_DIR$\tx_event_flags_delete.c
+            $PROJ_DIR$\tx_iar.c
+            $PROJ_DIR$\tx_initialize_kernel_enter.c
+            $PROJ_DIR$\tx_event_flags_performance_system_info_get.c
+            $PROJ_DIR$\tx_event_flags_info_get.c
+            $PROJ_DIR$\tx_mutex_cleanup.c
+            $PROJ_DIR$\tx_mutex_info_get.c
+            $PROJ_DIR$\tx_byte_pool_create.c
+            $PROJ_DIR$\tx_event_flags_set.c
+            $PROJ_DIR$\tx_byte_pool_initialize.c
+            $PROJ_DIR$\tx_event_flags_create.c
+            $PROJ_DIR$\tx_byte_release.c
+            $PROJ_DIR$\tx_byte_pool_delete.c
+            $PROJ_DIR$\tx_event_flags_get.c
+            $PROJ_DIR$\tx_mutex_delete.c
+            $PROJ_DIR$\tx_mutex_get.c
+            $PROJ_DIR$\tx_queue_flush.c
+            $PROJ_DIR$\tx_queue_front_send.c
+            $PROJ_DIR$\tx_semaphore_info_get.c
+            $PROJ_DIR$\tx_mutex_put.c
+            $PROJ_DIR$\tx_semaphore_performance_system_info_get.c
+            $PROJ_DIR$\tx_queue_prioritize.c
+            $PROJ_DIR$\tx_mutex_priority_change.c
+            $PROJ_DIR$\tx_thread_context_save.s
+            $PROJ_DIR$\tx_thread_create.c
+            $PROJ_DIR$\tx_thread_delete.c
+            $PROJ_DIR$\tx_queue_create.c
+            $PROJ_DIR$\tx_queue_send.c
+            $PROJ_DIR$\tx_semaphore_ceiling_put.c
+            $PROJ_DIR$\tx_queue_performance_system_info_get.c
+            $PROJ_DIR$\tx_queue_receive.c
+            $PROJ_DIR$\tx_semaphore_create.c
+            $PROJ_DIR$\tx_queue_delete.c
+            $PROJ_DIR$\tx_queue_info_get.c
+            $PROJ_DIR$\tx_queue_initialize.c
+            $PROJ_DIR$\tx_semaphore_delete.c
+            $PROJ_DIR$\tx_queue_performance_info_get.c
+            $PROJ_DIR$\tx_queue_send_notify.c
+            $PROJ_DIR$\tx_semaphore_cleanup.c
+            $PROJ_DIR$\tx_semaphore_get.c
+            $PROJ_DIR$\tx_semaphore_performance_info_get.c
+            $PROJ_DIR$\tx_semaphore_initialize.c
+            $PROJ_DIR$\tx_semaphore_prioritize.c
+            $PROJ_DIR$\tx_semaphore_put.c
+            $PROJ_DIR$\tx_queue_cleanup.c
+            $PROJ_DIR$\tx_semaphore_put_notify.c
+            $PROJ_DIR$\tx_thread_context_restore.s
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_create.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_prioritize.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_ceiling_put.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_create.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_get.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_info_get.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_flush.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_info_get.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_delete.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send_notify.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_receive.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_delete.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_info_get.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_get.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_create.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_delete.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_delete.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_entry_exit_notify.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put_notify.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_get.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set_notify.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_prioritize.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_info_get.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_put.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_delete.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_create.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_prioritize.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_front_send.c
+            $PROJ_DIR$\Debug\Obj\tx_mutex_cleanup.o
+            $PROJ_DIR$\Debug\Obj\txe_block_pool_prioritize.o
+            $PROJ_DIR$\tx_block_pool.h
+            $PROJ_DIR$\Debug\Obj\tx_thread_relinquish.o
+            $PROJ_DIR$\Debug\Obj\tx_trace_event_filter.pbi
+            $PROJ_DIR$\Debug\Obj\txe_mutex_delete.pbi
+            $PROJ_DIR$\Debug\Obj\txe_timer_activate.pbi
+            $PROJ_DIR$\Debug\Obj\tx_queue_performance_system_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_queue_create.o
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_create.pbi
+            $PROJ_DIR$\Debug\Obj\tx_queue_send.o
+            $PROJ_DIR$\Debug\Obj\txe_timer_activate.o
+            $PROJ_DIR$\Debug\Obj\tx_queue_receive.pbi
+            $PROJ_DIR$\Debug\Obj\tx_mutex_create.o
+            $PROJ_DIR$\Debug\Obj\tx_byte_pool_prioritize.o
+            $PROJ_DIR$\Debug\Obj\tx_thread_shell_entry.pbi
+            $PROJ_DIR$\Debug\Obj\txe_queue_receive.o
+            $PROJ_DIR$\Debug\Obj\txe_mutex_put.o
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_set.o
+            $PROJ_DIR$\Debug\Obj\txe_block_allocate.pbi
+            $PROJ_DIR$\Debug\Obj\txe_thread_reset.o
+            $PROJ_DIR$\Debug\Obj\txe_mutex_prioritize.o
+            $PROJ_DIR$\Debug\Obj\txe_queue_prioritize.o
+            $PROJ_DIR$\Debug\Obj\tx_mutex_priority_change.pbi
+            $PROJ_DIR$\Debug\Obj\tx_queue_prioritize.o
+            $PROJ_DIR$\Debug\Obj\txe_block_pool_delete.o
+            $PROJ_DIR$\Debug\Obj\tx_byte_release.pbi
+            $PROJ_DIR$\Debug\Obj\tx_trace_isr_exit_insert.o
+            $PROJ_DIR$\Debug\Obj\txe_thread_time_slice_change.pbi
+            $PROJ_DIR$\Debug\Obj\txe_byte_pool_delete.o
+            $PROJ_DIR$\Debug\Obj\txe_thread_resume.pbi
+            $PROJ_DIR$\Debug\Obj\tx_mutex_put.o
+            $PROJ_DIR$\Debug\Obj\tx_thread_system_resume.pbi
+            $PROJ_DIR$\Debug\Obj\txe_thread_entry_exit_notify.o
+            $PROJ_DIR$\Debug\Obj\tx_thread_performance_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\txe_semaphore_prioritize.o
+            $PROJ_DIR$\Debug\Obj\tx_thread_initialize.o
+            $PROJ_DIR$\Debug\Obj\txe_byte_pool_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_block_pool_create.pbi
+            $PROJ_DIR$\Debug\Obj\tx_trace_initialize.pbi
+            $PROJ_DIR$\Debug\Obj\txe_block_pool_info_get.o
+            $PROJ_DIR$\Debug\Obj\txe_thread_reset.pbi
+            $PROJ_DIR$\Debug\Obj\tx_thread_entry_exit_notify.o
+            $PROJ_DIR$\Debug\Obj\tx_mutex_get.o
+            $PROJ_DIR$\Debug\Obj\txe_thread_preemption_change.o
+            $PROJ_DIR$\Debug\Obj\tx_semaphore_get.o
+            $PROJ_DIR$\Debug\Obj\tx_time_set.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_mutex_create.pbi
+            $PROJ_DIR$\Debug\Obj\tx_byte_release.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_info_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_block_pool_initialize.o
+            $PROJ_DIR$\Debug\Obj\tx_thread_time_slice.o
+            $PROJ_DIR$\Debug\Obj\txe_thread_priority_change.pbi
+            $PROJ_DIR$\Debug\Obj\tx_semaphore_ceiling_put.o
+            $PROJ_DIR$\Debug\Obj\tx_queue_performance_info_get.o
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_set_notify.pbi
+            $PROJ_DIR$\Debug\Obj\tx_trace_event_filter.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_stack_analyze.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_semaphore_delete.pbi
+            $PROJ_DIR$\Debug\Obj\txe_mutex_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_shell_entry.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_mutex_performance_info_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_stack_error_notify.pbi
+            $PROJ_DIR$\Debug\Obj\tx_thread_suspend.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_queue_performance_system_info_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_queue_receive.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_delete.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_sleep.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_initialize_kernel_setup.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_set.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_time_slice.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_resume.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_priority_change.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_info_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_mutex_info_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_cleanup.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_mutex_delete.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_mutex_initialize.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_performance_info_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_queue_flush.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_relinquish.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_terminate.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_time_slice_change.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_timer_activate.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_byte_pool_prioritize.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_mutex_create.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_set_notify.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_system_resume.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_mutex_put.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_queue_info_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_stack_error_notify.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_system_preempt_check.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_semaphore_info_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_queue_send.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_queue_front_send.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_queue_send_notify.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_trace_user_event_insert.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_byte_pool_info_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_block_release.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_info_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_system_suspend.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_semaphore_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_stack_error_handler.__cstat.et
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+            $PROJ_DIR$\Debug\Obj\txe_byte_pool_create.__cstat.et
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diff --git a/ports/cortex_m4/iar/example_build/tx.ewd b/ports/cortex_m4/iar/example_build/tx.ewd
new file mode 100644
index 00000000..df7edfb3
--- /dev/null
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new file mode 100644
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_preemption_change.c
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_priority_change.c
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_relinquish.c
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_reset.c
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_resume.c
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_suspend.c
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_terminate.c
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_time_slice_change.c
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c
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diff --git a/ports/cortex_m4/iar/example_build/tx.ewt b/ports/cortex_m4/iar/example_build/tx.ewt
new file mode 100644
index 00000000..b13c96f7
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/tx.ewt
@@ -0,0 +1,3403 @@
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_search.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_byte_release.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_cleanup.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_initialize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_performance_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_performance_system_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_set.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_set_notify.c
+        
+        
+            $PROJ_DIR$\..\src\tx_iar.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_initialize_high_level.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_initialize_kernel_enter.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_initialize_kernel_setup.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_cleanup.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_initialize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_performance_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_performance_system_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_priority_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_mutex_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_cleanup.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_flush.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_front_send.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_initialize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_performance_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_performance_system_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_receive.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_send.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_send_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_ceiling_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_cleanup.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_initialize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_performance_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_put_notify.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_context_restore.s
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_context_save.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_entry_exit_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_identify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_initialize.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_interrupt_control.s
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_interrupt_disable.s
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_interrupt_restore.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_performance_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_performance_system_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_preemption_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_priority_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_relinquish.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_reset.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_resume.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_schedule.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_shell_entry.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_sleep.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_analyze.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_stack_build.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_error_handler.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_error_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_suspend.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_preempt_check.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_resume.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_system_return.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_suspend.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_terminate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_time_slice.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_time_slice_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_timeout.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_wait_abort.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_time_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_time_set.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_activate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_deactivate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_expiration_process.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_initialize.c
+        
+        
+            $PROJ_DIR$\..\src\tx_timer_interrupt.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_performance_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_performance_system_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_system_activate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_system_deactivate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_thread_entry.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_buffer_full_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_disable.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_enable.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_filter.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_unfilter.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_initialize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_interrupt_control.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_enter_insert.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_exit_insert.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_register.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_unregister.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_user_event_insert.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_allocate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_release.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_allocate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_release.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_flush.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_front_send.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_receive.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_ceiling_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_entry_exit_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_preemption_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_priority_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_relinquish.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_reset.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_resume.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_suspend.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_terminate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_time_slice_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c
+        
+    
+
diff --git a/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s
new file mode 100644
index 00000000..c252a33f
--- /dev/null
+++ b/ports/cortex_m4/iar/example_build/tx_initialize_low_level.s
@@ -0,0 +1,176 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Initialize                                                          */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_initialize.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+        EXTERN  _tx_thread_system_stack_ptr
+        EXTERN  _tx_initialize_unused_memory
+        EXTERN  _tx_timer_interrupt
+        EXTERN  __vector_table
+        EXTERN  _tx_execution_isr_enter
+        EXTERN  _tx_execution_isr_exit
+;
+;
+SYSTEM_CLOCK      EQU   25000000
+SYSTICK_CYCLES    EQU   ((SYSTEM_CLOCK / 100) -1)
+        
+    RSEG    FREE_MEM:DATA
+    PUBLIC  __tx_free_memory_start
+__tx_free_memory_start
+    DS32    4        
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_initialize_low_level                          Cortex-M4/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for any low-level processor            */
+;/*    initialization, including setting up interrupt vectors, setting     */
+;/*    up a periodic timer interrupt source, saving the system stack       */
+;/*    pointer for use in ISR processing later, and finding the first      */
+;/*    available RAM memory address for tx_application_define.             */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_initialize_low_level(VOID)
+;{
+    PUBLIC  _tx_initialize_low_level
+_tx_initialize_low_level:
+;       
+;    /* Ensure that interrupts are disabled.  */
+;
+    CPSID   i                                       ; Disable interrupts
+;
+;
+;    /* Set base of available memory to end of non-initialised RAM area.  */
+;     
+    LDR     r0, =__tx_free_memory_start             ; Get end of non-initialized RAM area
+    LDR     r2, =_tx_initialize_unused_memory       ; Build address of unused memory pointer
+    STR     r0, [r2, #0]                            ; Save first free memory address
+;
+;    /* Enable the cycle count register.  */
+;
+    LDR     r0, =0xE0001000                         ; Build address of DWT register
+    LDR     r1, [r0]                                ; Pickup the current value
+    ORR     r1, r1, #1                              ; Set the CYCCNTENA bit
+    STR     r1, [r0]                                ; Enable the cycle count register 
+;
+;    /* Setup Vector Table Offset Register.  */
+;    
+    MOV     r0, #0xE000E000                         ; Build address of NVIC registers
+    LDR     r1, =__vector_table                     ; Pickup address of vector table
+    STR     r1, [r0, #0xD08]                        ; Set vector table address   
+;
+;    /* Set system stack pointer from vector value.  */
+;
+    LDR     r0, =_tx_thread_system_stack_ptr        ; Build address of system stack pointer
+    LDR     r1, =__vector_table                     ; Pickup address of vector table
+    LDR     r1, [r1]                                ; Pickup reset stack pointer
+    STR     r1, [r0]                                ; Save system stack pointer
+;
+;    /* Configure SysTick.  */
+;
+    MOV     r0, #0xE000E000                         ; Build address of NVIC registers
+    LDR     r1, =SYSTICK_CYCLES
+    STR     r1, [r0, #0x14]                         ; Setup SysTick Reload Value
+    MOV     r1, #0x7                                ; Build SysTick Control Enable Value
+    STR     r1, [r0, #0x10]                         ; Setup SysTick Control
+;
+;    /* Configure handler priorities.  */
+;
+    LDR     r1, =0x00000000                         ; Rsrv, UsgF, BusF, MemM
+    STR     r1, [r0, #0xD18]                        ; Setup System Handlers 4-7 Priority Registers
+
+    LDR     r1, =0xFF000000                         ; SVCl, Rsrv, Rsrv, Rsrv
+    STR     r1, [r0, #0xD1C]                        ; Setup System Handlers 8-11 Priority Registers
+                                                    ; Note: SVC must be lowest priority, which is 0xFF
+
+    LDR     r1, =0x40FF0000                         ; SysT, PnSV, Rsrv, DbgM
+    STR     r1, [r0, #0xD20]                        ; Setup System Handlers 12-15 Priority Registers
+                                                    ; Note: PnSV must be lowest priority, which is 0xFF
+;
+;    /* Return to caller.  */
+;    
+    BX      lr 
+;}
+;
+    PUBLIC  SysTick_Handler
+    PUBLIC  __tx_SysTickHandler
+__tx_SysTickHandler:
+SysTick_Handler:
+;
+; VOID SysTick_Handler(VOID)
+; {
+;
+    PUSH    {r0, lr}
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+#endif
+    BL      _tx_timer_interrupt
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    BL      _tx_execution_isr_exit              ; Call the ISR exit function
+#endif
+    POP     {r0, lr}
+    BX      LR
+; }
+    END
+
diff --git a/ports/cortex_m4/iar/inc/tx_port.h b/ports/cortex_m4/iar/inc/tx_port.h
new file mode 100644
index 00000000..2aa60ea8
--- /dev/null
+++ b/ports/cortex_m4/iar/inc/tx_port.h
@@ -0,0 +1,493 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */
+/*                                                                        */
+/*    tx_port.h                                         Cortex-M4/IAR     */
+/*                                                           6.0.1        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file contains data type definitions that make the ThreadX      */
+/*    real-time kernel function identically on a variety of different     */
+/*    processor architectures.  For example, the size or number of bits   */
+/*    in an "int" data type vary between microprocessor architectures and */
+/*    even C compilers for the same microprocessor.  ThreadX does not     */
+/*    directly use native C data types.  Instead, ThreadX creates its     */
+/*    own special types that can be mapped to actual data types by this   */
+/*    file to guarantee consistency in the interface and functionality.   */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include 
+#include 
+#include 
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#include 
+#endif
+
+
+/* Define ThreadX basic types for this port.  */
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */
+#endif
+
+
+/* Define various constants for the ThreadX Cortex-M3 port.  */
+
+#define TX_INT_DISABLE                          1           /* Disable interrupts               */
+#define TX_INT_ENABLE                           0           /* Enable interrupts                */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_MISRA_ENABLE
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0xE0001004)  
+#endif
+#else
+ULONG   _tx_misra_time_stamp_get(VOID);
+#define TX_TRACE_TIME_SOURCE                    _tx_misra_time_stamp_get()
+#endif
+
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          (0)
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#ifdef TX_MISRA_ENABLE
+#define TX_DISABLE_INLINE
+#else
+#define TX_INLINE_INITIALIZATION
+#endif
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifndef TX_MISRA_ENABLE
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_EXTENSION_2           VOID    *tx_thread_iar_tls_pointer;          
+#else
+#define TX_THREAD_EXTENSION_2          
+#endif
+#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+#define TX_THREAD_EXTENSION_3          
+#else
+#define TX_THREAD_EXTENSION_3           unsigned long long  tx_thread_execution_time_total; \
+                                        unsigned long long  tx_thread_execution_time_last_start; 
+#endif
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#if (__VER__ < 8000000)
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  __iar_dlib_perthread_allocate();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                    thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL;            
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               __iar_dlib_perthread_access(0);
+#else
+void    *_tx_iar_create_per_thread_tls_area(void);
+void    _tx_iar_destroy_per_thread_tls_area(void *tls_ptr);
+void    __iar_Initlocks(void);
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  _tx_iar_create_per_thread_tls_area();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                        thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL; } while(0);
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               do {__iar_Initlocks();} while(0); 
+#endif
+#else
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#endif
+
+
+#ifdef __ARMVFP__
+
+#ifdef TX_MISRA_ENABLE
+
+ULONG  _tx_misra_control_get(void);
+void   _tx_misra_control_set(ULONG value);
+ULONG  _tx_misra_fpccr_get(void);
+void   _tx_misra_vfp_touch(void);
+
+#endif
+
+/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA
+   in order to ensure no lazy stacking will occur. */
+
+#ifndef TX_MISRA_ENABLE
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)                   {                                                                                             \
+                                                                    ULONG  _tx_vfp_state;                                                                         \
+                                                                        _tx_vfp_state =  __get_CONTROL();                                                         \
+                                                                        _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                          \
+                                                                        __set_CONTROL(_tx_vfp_state);                                                             \
+                                                                    }
+#else
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)                   {                                                                                             \
+                                                                    ULONG  _tx_vfp_state;                                                                         \
+                                                                        _tx_vfp_state =  _tx_misra_control_get();                                                 \
+                                                                        _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                          \
+                                                                        _tx_misra_control_set(_tx_vfp_state);                                                     \
+                                                                    }
+                                                                    
+#endif
+
+/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR.
+   If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating
+   this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush 
+   the lazy FPU save, then restore the CONTROL.FPCA state. */
+
+#ifndef TX_MISRA_ENABLE
+
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  {                                                                                             \
+                                                                    ULONG  _tx_system_state;                                                                      \
+                                                                        _tx_system_state =  TX_THREAD_GET_SYSTEM_STATE();                                         \
+                                                                        if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr))        \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_vfp_state;                                                                     \
+                                                                            _tx_vfp_state =  __get_CONTROL();                                                     \
+                                                                            _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                      \
+                                                                            __set_CONTROL(_tx_vfp_state);                                                         \
+                                                                        }                                                                                         \
+                                                                        else                                                                                      \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_fpccr;                                                                         \
+                                                                            _tx_fpccr =  *((ULONG *) 0xE000EF34);                                                 \
+                                                                            _tx_fpccr =  _tx_fpccr & ((ULONG) 0x01);                                              \
+                                                                            if (_tx_fpccr == ((ULONG) 0x01))                                                      \
+                                                                            {                                                                                     \
+                                                                            ULONG _tx_vfp_state;                                                                  \
+                                                                                _tx_vfp_state = __get_CONTROL();                                                  \
+                                                                                _tx_vfp_state =  _tx_vfp_state & ((ULONG) 0x4);                                   \
+                                                                                __asm volatile ("vmov.f32 s0, s0");                                               \
+                                                                                if (_tx_vfp_state == ((ULONG) 0))                                                 \
+                                                                                {                                                                                 \
+                                                                                    _tx_vfp_state =  __get_CONTROL();                                             \
+                                                                                    _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                              \
+                                                                                    __set_CONTROL(_tx_vfp_state);                                                 \
+                                                                                }                                                                                 \
+                                                                            }                                                                                     \
+                                                                        }                                                                                         \
+                                                                    }
+#else
+
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  {                                                                                             \
+                                                                    ULONG  _tx_system_state;                                                                      \
+                                                                        _tx_system_state =  TX_THREAD_GET_SYSTEM_STATE();                                         \
+                                                                        if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr))        \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_vfp_state;                                                                     \
+                                                                            _tx_vfp_state =  _tx_misra_control_get();                                             \
+                                                                            _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                      \
+                                                                            _tx_misra_control_set(_tx_vfp_state);                                                 \
+                                                                        }                                                                                         \
+                                                                        else                                                                                      \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_fpccr;                                                                         \
+                                                                            _tx_fpccr =  _tx_misra_fpccr_get();                                                   \
+                                                                            _tx_fpccr =  _tx_fpccr & ((ULONG) 0x01);                                              \
+                                                                            if (_tx_fpccr == ((ULONG) 0x01))                                                      \
+                                                                            {                                                                                     \
+                                                                            ULONG _tx_vfp_state;                                                                  \
+                                                                                _tx_vfp_state = _tx_misra_control_get();                                          \
+                                                                                _tx_vfp_state =  _tx_vfp_state & ((ULONG) 0x4);                                   \
+                                                                                _tx_misra_vfp_touch();                                                            \
+                                                                                if (_tx_vfp_state == ((ULONG) 0))                                                 \
+                                                                                {                                                                                 \
+                                                                                    _tx_vfp_state =  _tx_misra_control_get();                                     \
+                                                                                    _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                              \
+                                                                                    _tx_misra_control_set(_tx_vfp_state);                                         \
+                                                                                }                                                                                 \
+                                                                            }                                                                                     \
+                                                                        }                                                                                         \
+                                                                    }
+#endif
+
+#else
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  
+
+#endif
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Define the get system state macro.   */
+   
+#ifndef TX_THREAD_GET_SYSTEM_STATE
+#ifndef TX_MISRA_ENABLE
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | __get_IPSR())
+#else
+ULONG   _tx_misra_ipsr_get(VOID);
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | _tx_misra_ipsr_get())
+#endif
+#endif
+
+
+/* Define the check for whether or not to call the _tx_thread_system_return function.  A non-zero value
+   indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h
+   for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always
+   zero after initialization for Cortex-M ports. */
+
+#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
+#define TX_THREAD_SYSTEM_RETURN_CHECK(c)    (c) = ((ULONG) _tx_thread_preempt_disable); 
+#endif
+
+
+/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to 
+   prevent early scheduling on Cortex-M parts.  */
+   
+#define TX_PORT_SPECIFIC_POST_INITIALIZATION    _tx_thread_preempt_disable++;
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef TX_DISABLE_INLINE
+
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       (b) = (UINT)__CLZ(__RBIT((m)));
+
+#endif
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifdef TX_DISABLE_INLINE
+
+UINT                                            _tx_thread_interrupt_disable(VOID);
+VOID                                            _tx_thread_interrupt_restore(UINT previous_posture);
+
+#define TX_INTERRUPT_SAVE_AREA                  register UINT interrupt_save;
+
+#define TX_DISABLE                              interrupt_save = _tx_thread_interrupt_disable();
+
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+
+#else
+
+#define TX_INTERRUPT_SAVE_AREA                  __istate_t interrupt_save;
+#define TX_DISABLE                              {interrupt_save = __get_interrupt_state();__disable_interrupt();};
+#define TX_RESTORE                              {__set_interrupt_state(interrupt_save);};
+
+#define _tx_thread_system_return                _tx_thread_system_return_inline
+
+static void _tx_thread_system_return_inline(void)
+{
+__istate_t interrupt_save;
+
+    /* Set PendSV to invoke ThreadX scheduler.  */
+    *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    if (__get_IPSR() == 0)
+    {
+        interrupt_save = __get_interrupt_state();
+        __enable_interrupt();
+        __set_interrupt_state(interrupt_save);
+    }
+}
+
+#endif
+
+
+/* Define FPU extension for the Cortex-M4.  Each is assumed to be called in the context of the executing
+   thread. These are no longer needed, but are preserved for backward compatibility only.  */
+
+void    tx_thread_fpu_enable(void);
+void    tx_thread_fpu_disable(void);
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Cortex-M4/IAR Version 6.0 *";
+#else
+#ifdef TX_MISRA_ENABLE
+extern  CHAR                    _tx_version_id[100];
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+#endif
+
+
+#endif
+
+
+
diff --git a/ports/cortex_m4/iar/readme_threadx.txt b/ports/cortex_m4/iar/readme_threadx.txt
new file mode 100644
index 00000000..c6e7bb1f
--- /dev/null
+++ b/ports/cortex_m4/iar/readme_threadx.txt
@@ -0,0 +1,224 @@
+                       Microsoft's Azure RTOS ThreadX for Cortex-M4 
+
+                                   Using the IAR Tools
+
+
+1.  Building the ThreadX run-time Library
+
+Building the ThreadX library is easy. First, open the Azure RTOS workspace
+azure_rtos.eww. Next, make the TX project the "active project" in the 
+IAR Embedded Workbench and select the "Make" button. You should observe 
+assembly and compilation of a series of ThreadX source files. This 
+results in the ThreadX run-time library file tx.a, which is needed by 
+the application.
+
+
+2.  Demonstration System
+
+The ThreadX demonstration is designed to execute under the IAR debugger under 
+simulation.
+
+Building the demonstration is easy; simply open the threadx.www workspace file,
+make the sample_threadx.ewp project the "active project" in the IAR Embedded 
+Workbench, and select the "Make" button.
+
+You should observe the compilation of sample_threadx.c (which is the demonstration 
+application) and linking with tx.a. The resulting file sample_threadx.out is a 
+binary ELF file that can be downloaded and executed on the IAR Windows-based 
+Cortex-M4 simulator.
+
+
+3.  System Initialization
+
+The entry point in ThreadX for the Cortex-M4 using IAR tools is at label 
+__iar_program_start. This is defined within the IAR compiler's startup code. 
+In addition, this is where all static and global preset C variable 
+initialization processing takes place.
+
+The ThreadX tx_initialize_low_level.s file is responsible for setting up 
+various system data structures, and a periodic timer interrupt source. 
+By default, the vector area is defined at the top of cstartup_M.s, which is
+a slightly modified from the base IAR file. 
+
+The _tx_initialize_low_level function inside of tx_initialize_low_level.s
+also determines the first available address for use by the application, which 
+is supplied as the sole input parameter to your application definition function, 
+tx_application_define. To accomplish this, a section is created in 
+tx_initialize_low_level.s called FREE_MEM, which must be located after all 
+other RAM sections in memory.
+
+
+4.  Register Usage and Stack Frames
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have the same stack frame in the Cortex-M4 version of
+ThreadX. The top of the suspended thread's stack is pointed to by 
+tx_thread_stack_ptr in the associated thread control block TX_THREAD.
+
+Non-FPU Stack Frame:
+
+  Stack Offset     Stack Contents 
+
+     0x00               LR          Interrupted LR (LR at time of PENDSV)
+     0x04               r4          
+     0x08               r5          
+     0x0C               r6          
+     0x10               r7          
+     0x14               r8          
+     0x18               r9          
+     0x1C               r10 (sl)    
+     0x20               r11         
+     0x24               r0          (Hardware stack starts here!!)
+     0x28               r1          
+     0x2C               r2          
+     0x30               r3          
+     0x34               r12         
+     0x38               lr          
+     0x3C               pc          
+     0x40               xPSR        
+
+FPU Stack Frame (only interrupted thread with FPU enabled):
+
+  Stack Offset     Stack Contents 
+
+     0x00               LR          Interrupted LR (LR at time of PENDSV)
+     0x04               s0
+     0x08               s1
+     0x0C               s2
+     0x10               s3
+     0x14               s4
+     0x18               s5
+     0x1C               s6
+     0x20               s7
+     0x24               s8
+     0x28               s9
+     0x2C               s10
+     0x30               s11
+     0x34               s12
+     0x38               s13
+     0x3C               s14
+     0x40               s15
+     0x44               s16
+     0x48               s17
+     0x4C               s18
+     0x50               s19
+     0x54               s20
+     0x58               s21
+     0x5C               s22
+     0x60               s23
+     0x64               s24
+     0x68               s25
+     0x6C               s26
+     0x70               s27
+     0x74               s28
+     0x78               s29
+     0x7C               s30
+     0x80               s31
+     0x84               fpscr
+     0x88               r4          
+     0x8C               r5          
+     0x90               r6          
+     0x94               r7          
+     0x98               r8          
+     0x9C               r9          
+     0xA0               r10 (sl)    
+     0xA4               r11         
+     0xA8               r0          (Hardware stack starts here!!)
+     0xAC               r1          
+     0xB0               r2          
+     0xB4               r3          
+     0xB8               r12         
+     0xBC               lr          
+     0xC0               pc          
+     0xC4               xPSR        
+
+
+5.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+breakpoints inside of ThreadX itself. Of course, this costs some 
+performance. To make it run faster, you can change the ThreadX library
+project to enable various compiler optimizations. 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+6.  Interrupt Handling
+
+The Cortex-M4 vectors start at the label __vector_table and is defined in cstartup_M.s. 
+The application may modify the vector area according to its needs.
+
+
+6.1 Managed Interrupts
+
+ISRs for Cortex-M using the IAR tools can be written completely in C (or assembly
+language) without any calls to _tx_thread_context_save or _tx_thread_context_restore.
+These ISRs are allowed access to the ThreadX API that is available to ISRs.
+
+ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
+
+void    your_C_isr(void)
+{
+
+    /* ISR processing goes here, including any needed function calls.  */
+}
+
+ISRs written in assembly language will take the form:
+
+        PUBLIC  your_assembly_isr
+your_assembly_isr:
+
+    PUSH    {lr}
+
+    ; ISR processing goes here, including any needed function calls.
+
+    POP     {lr}
+    BX      lr
+
+
+7.  IAR Thread-safe Library Support
+
+Thread-safe support for the IAR tools is easily enabled by building the ThreadX library
+and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file
+should have the following line added (if not already in place):
+
+initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
+
+
+7.  IAR Thread-safe Library Support
+
+Thread-safe support for the IAR tools is easily enabled by building the ThreadX library
+and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file
+should have the following line added (if not already in place):
+
+initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
+
+The project options "General Options -> Library Configuration" should also have the 
+"Enable thread support in library" box selected.
+
+
+8. VFP Support
+
+ThreadX for Cortex-M4 supports automatic ("lazy") VFP support, which means that applications threads 
+can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread 
+context - no additional setup by the application.
+
+
+9.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX 6.0.1 version for Cortex-M4 using IAR's ARM tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_m4/iar/src/tx_iar.c b/ports/cortex_m4/iar/src/tx_iar.c
new file mode 100644
index 00000000..dd719370
--- /dev/null
+++ b/ports/cortex_m4/iar/src/tx_iar.c
@@ -0,0 +1,804 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   IAR Multithreaded Library Support                                   */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Define IAR library for tools prior to version 8.  */
+
+#if (__VER__ < 8000000)
+
+
+/* IAR version 7 and below.  */
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_initialize.h"
+#include "tx_thread.h"
+#include "tx_mutex.h"
+
+
+/* This implementation requires that the following macros are defined in the 
+   tx_port.h file and  is included with the following code segments:
+   
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#include 
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_EXTENSION_2           VOID    *tx_thread_iar_tls_pointer;          
+#else
+#define TX_THREAD_EXTENSION_2          
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  __iar_dlib_perthread_allocate();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                    thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL;            
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               __iar_dlib_perthread_access(0);
+#else
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#endif
+
+    This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the 
+    application.  
+
+    Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected.
+*/
+
+#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
+
+#include 
+
+
+#if _MULTI_THREAD
+
+TX_MUTEX    __tx_iar_system_lock_mutexes[_MAX_LOCK];
+UINT        __tx_iar_system_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_system_lock_no_mutexes;
+UINT        __tx_iar_system_lock_internal_errors;
+UINT        __tx_iar_system_lock_isr_caller;
+
+
+/* Define the TLS access function for the IAR library.  */
+
+void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp)
+{
+
+char _DLIB_TLS_MEMORY   *p = 0;
+    
+    /* Is there a current thread?  */
+    if (_tx_thread_current_ptr)
+      p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer;
+    else
+      p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD");
+    p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp);
+    return (void _DLIB_TLS_MEMORY *) p;
+}
+
+
+/* Define mutexes for IAR library.  */
+
+void __iar_system_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_LOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_system_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_system_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_system_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_system_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_system_Mtxlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+}
+
+void __iar_system_Mtxunlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+}
+
+
+#if _DLIB_FILE_DESCRIPTOR
+
+TX_MUTEX    __tx_iar_file_lock_mutexes[_MAX_FLOCK];
+UINT        __tx_iar_file_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_file_lock_no_mutexes;
+UINT        __tx_iar_file_lock_internal_errors;
+UINT        __tx_iar_file_lock_isr_caller;
+
+
+void __iar_file_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_FLOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_file_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_file_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_file_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_file_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_file_Mtxlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+
+void __iar_file_Mtxunlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+#endif  /* _DLIB_FILE_DESCRIPTOR */
+
+#endif  /* _MULTI_THREAD  */
+
+#endif  /* TX_ENABLE_IAR_LIBRARY_SUPPORT  */
+
+#else   /* IAR version 8 and above.  */
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_initialize.h"
+#include "tx_thread.h"
+#include "tx_mutex.h"
+
+/* This implementation requires that the following macros are defined in the 
+   tx_port.h file and  is included with the following code segments:
+   
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#include 
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_EXTENSION_2           VOID    *tx_thread_iar_tls_pointer;          
+#else
+#define TX_THREAD_EXTENSION_2          
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+void    *_tx_iar_create_per_thread_tls_area(void);
+void    _tx_iar_destroy_per_thread_tls_area(void *tls_ptr);
+void    __iar_Initlocks(void);
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  __iar_dlib_perthread_allocate();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                        thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL; } while(0);
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               do {__iar_Initlocks();} while(0);
+#else
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#endif
+
+    This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the 
+    application.  
+
+    Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected.
+*/
+
+#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
+
+#include 
+
+
+void * __aeabi_read_tp();
+
+void* _tx_iar_create_per_thread_tls_area();
+void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr);
+
+#pragma section="__iar_tls$$DATA"
+
+/* Define the TLS access function for the IAR library.  */
+void * __aeabi_read_tp(void)
+{
+  void *p = 0;
+  TX_THREAD *thread_ptr = _tx_thread_current_ptr;
+  if (thread_ptr)
+  {
+    p = thread_ptr->tx_thread_iar_tls_pointer;      
+  }
+  else
+  {
+    p = __section_begin("__iar_tls$$DATA");
+  }
+  return p;
+}
+
+/* Define the TLS creation and destruction to use malloc/free.  */
+
+void* _tx_iar_create_per_thread_tls_area()
+{
+  UINT tls_size = __iar_tls_size();  
+  
+  /* Get memory for TLS.  */  
+  void *p = malloc(tls_size);
+
+  /* Initialize TLS-area and run constructors for objects in TLS */
+  __iar_tls_init(p);
+  return p;
+}
+
+void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr)
+{
+  /* Destroy objects living in TLS */
+  __call_thread_dtors();
+  free(tls_ptr);  
+}
+
+#ifndef _MAX_LOCK
+#define _MAX_LOCK 4
+#endif
+
+static TX_MUTEX    __tx_iar_system_lock_mutexes[_MAX_LOCK];
+static UINT        __tx_iar_system_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_system_lock_no_mutexes;
+UINT        __tx_iar_system_lock_internal_errors;
+UINT        __tx_iar_system_lock_isr_caller;
+
+
+/* Define mutexes for IAR library.  */
+
+void __iar_system_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_LOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_system_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_system_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_system_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_system_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_system_Mtxlock(__iar_Rmtx *m)
+{
+  if (*m)
+  {  
+    UINT    status;
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+  }
+}
+
+void __iar_system_Mtxunlock(__iar_Rmtx *m)
+{
+  if (*m)
+  {
+    UINT    status;
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+  }
+}
+
+
+#if _DLIB_FILE_DESCRIPTOR
+
+#include                         /* Added to get access to FOPEN_MAX */
+#ifndef _MAX_FLOCK
+#define _MAX_FLOCK FOPEN_MAX              /* Define _MAX_FLOCK as the maximum number of open files */
+#endif
+
+
+TX_MUTEX    __tx_iar_file_lock_mutexes[_MAX_FLOCK];
+UINT        __tx_iar_file_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_file_lock_no_mutexes;
+UINT        __tx_iar_file_lock_internal_errors;
+UINT        __tx_iar_file_lock_isr_caller;
+
+
+void __iar_file_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_FLOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_file_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_file_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_file_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_file_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_file_Mtxlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+
+void __iar_file_Mtxunlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+#endif  /* _DLIB_FILE_DESCRIPTOR */
+
+#endif  /* TX_ENABLE_IAR_LIBRARY_SUPPORT  */
+
+#endif /* IAR version 8 and above.  */
diff --git a/ports/cortex_m4/iar/src/tx_misra.s b/ports/cortex_m4/iar/src/tx_misra.s
new file mode 100644
index 00000000..60ab3549
--- /dev/null
+++ b/ports/cortex_m4/iar/src/tx_misra.s
@@ -0,0 +1,1074 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   ThreadX MISRA Compliance                                            */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        #define SHT_PROGBITS 0x1
+
+        EXTERN __aeabi_memset
+        EXTERN _tx_thread_current_ptr
+        EXTERN _tx_thread_interrupt_disable
+        EXTERN _tx_thread_interrupt_restore
+        EXTERN _tx_thread_stack_analyze
+        EXTERN _tx_thread_stack_error_handler
+        EXTERN _tx_thread_system_state
+#ifdef TX_ENABLE_EVENT_TRACE
+        EXTERN _tx_trace_buffer_current_ptr
+        EXTERN _tx_trace_buffer_end_ptr
+        EXTERN _tx_trace_buffer_start_ptr
+        EXTERN _tx_trace_event_enable_bits
+        EXTERN _tx_trace_full_notify_function
+        EXTERN _tx_trace_header_ptr
+#endif
+
+        PUBLIC _tx_misra_always_true
+        PUBLIC _tx_misra_block_pool_to_uchar_pointer_convert
+        PUBLIC _tx_misra_byte_pool_to_uchar_pointer_convert
+        PUBLIC _tx_misra_char_to_uchar_pointer_convert
+        PUBLIC _tx_misra_const_char_to_char_pointer_convert
+#ifdef TX_ENABLE_EVENT_TRACE
+        PUBLIC _tx_misra_entry_to_uchar_pointer_convert
+#endif
+        PUBLIC _tx_misra_indirect_void_to_uchar_pointer_convert
+        PUBLIC _tx_misra_memset
+        PUBLIC _tx_misra_message_copy
+#ifdef TX_ENABLE_EVENT_TRACE
+        PUBLIC _tx_misra_object_to_uchar_pointer_convert
+#endif
+        PUBLIC _tx_misra_pointer_to_ulong_convert
+        PUBLIC _tx_misra_status_get
+        PUBLIC _tx_misra_thread_stack_check
+#ifdef TX_ENABLE_EVENT_TRACE
+        PUBLIC _tx_misra_time_stamp_get
+#endif
+        PUBLIC _tx_misra_timer_indirect_to_void_pointer_convert
+        PUBLIC _tx_misra_timer_pointer_add
+        PUBLIC _tx_misra_timer_pointer_dif
+#ifdef TX_ENABLE_EVENT_TRACE
+        PUBLIC _tx_misra_trace_event_insert
+#endif
+        PUBLIC _tx_misra_uchar_pointer_add
+        PUBLIC _tx_misra_uchar_pointer_dif
+        PUBLIC _tx_misra_uchar_pointer_sub
+        PUBLIC _tx_misra_uchar_to_align_type_pointer_convert
+        PUBLIC _tx_misra_uchar_to_block_pool_pointer_convert
+#ifdef TX_ENABLE_EVENT_TRACE
+        PUBLIC _tx_misra_uchar_to_entry_pointer_convert
+        PUBLIC _tx_misra_uchar_to_header_pointer_convert
+#endif
+        PUBLIC _tx_misra_uchar_to_indirect_byte_pool_pointer_convert
+        PUBLIC _tx_misra_uchar_to_indirect_uchar_pointer_convert
+#ifdef TX_ENABLE_EVENT_TRACE
+        PUBLIC _tx_misra_uchar_to_object_pointer_convert
+#endif
+        PUBLIC _tx_misra_uchar_to_void_pointer_convert
+        PUBLIC _tx_misra_ulong_pointer_add
+        PUBLIC _tx_misra_ulong_pointer_dif
+        PUBLIC _tx_misra_ulong_pointer_sub
+        PUBLIC _tx_misra_ulong_to_pointer_convert
+        PUBLIC _tx_misra_ulong_to_thread_pointer_convert
+        PUBLIC _tx_misra_user_timer_pointer_get
+        PUBLIC _tx_misra_void_to_block_pool_pointer_convert
+        PUBLIC _tx_misra_void_to_byte_pool_pointer_convert
+        PUBLIC _tx_misra_void_to_event_flags_pointer_convert
+        PUBLIC _tx_misra_void_to_indirect_uchar_pointer_convert
+        PUBLIC _tx_misra_void_to_mutex_pointer_convert
+        PUBLIC _tx_misra_void_to_queue_pointer_convert
+        PUBLIC _tx_misra_void_to_semaphore_pointer_convert
+        PUBLIC _tx_misra_void_to_thread_pointer_convert
+        PUBLIC _tx_misra_void_to_uchar_pointer_convert
+        PUBLIC _tx_misra_void_to_ulong_pointer_convert
+        PUBLIC _tx_misra_ipsr_get
+        PUBLIC _tx_misra_control_get
+        PUBLIC _tx_misra_control_set
+#ifdef __ARMVFP__
+        PUBLIC _tx_misra_fpccr_get
+        PUBLIC _tx_misra_vfp_touch
+#endif
+        PUBLIC _tx_version_id
+
+
+        SECTION `.data`:DATA:REORDER:NOROOT(2)
+        DATA
+//   51 CHAR  _tx_version_id[100] =  "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0       MISRA C Compliant *";
+_tx_version_id:
+        DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H
+        DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H
+        DC8 39H, 36H, 2DH, 32H, 30H, 31H, 38H, 20H
+        DC8 45H, 78H, 70H, 72H, 65H, 73H, 73H, 20H
+        DC8 4CH, 6FH, 67H, 69H, 63H, 20H, 49H, 6EH
+        DC8 63H, 2EH, 20H, 2AH, 20H, 54H, 68H, 72H
+        DC8 65H, 61H, 64H, 58H, 20H, 35H, 2EH, 38H
+        DC8 20H, 4DH, 49H, 53H, 52H, 41H, 20H, 43H
+        DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H
+        DC8 6EH, 74H, 20H, 2AH, 0
+        DC8 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  VOID  _tx_misra_memset(VOID *ptr, UINT value, UINT size);            */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_memset:
+        PUSH     {R4,LR}
+        MOVS     R4,R0
+        MOVS     R0,R2
+        MOVS     R2,R1
+        MOVS     R1,R0
+        MOVS     R0,R4
+        BL       __aeabi_memset
+        POP      {R4,PC}          ;; return
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  UCHAR  *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount);       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_pointer_add:
+        ADD      R0,R0,R1
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  UCHAR  *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount);       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_pointer_sub:
+        RSBS     R1,R1,#+0
+        ADD      R0,R0,R1
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  ULONG  _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2);        */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_pointer_dif:
+        SUBS     R0,R0,R1
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  ULONG  _tx_misra_pointer_to_ulong_convert(VOID *ptr);                */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_pointer_to_ulong_convert:
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  ULONG  *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount);       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_ulong_pointer_add:
+        ADD      R0,R0,R1, LSL #+2
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  ULONG  *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount);       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_ulong_pointer_sub:
+        MVNS     R2,#+3
+        MULS     R1,R2,R1
+        ADD      R0,R0,R1
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  ULONG  _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2);        */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_ulong_pointer_dif:
+        SUBS     R0,R0,R1
+        ASRS     R0,R0,#+2
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  VOID  *_tx_misra_ulong_to_pointer_convert(ULONG input);              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_ulong_to_pointer_convert:
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  VOID  _tx_misra_message_copy(ULONG **source, ULONG **destination,    */
+/**                                                           UINT size); */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_message_copy:
+        PUSH     {R4,R5}
+        LDR      R3,[R0, #+0]
+        LDR      R4,[R1, #+0]
+        LDR      R5,[R3, #+0]
+        STR      R5,[R4, #+0]
+        ADDS     R4,R4,#+4
+        ADDS     R3,R3,#+4
+        CMP      R2,#+2
+        BCC.N    ??_tx_misra_message_copy_0
+        SUBS     R2,R2,#+1
+        B.N      ??_tx_misra_message_copy_1
+??_tx_misra_message_copy_2:
+        LDR      R5,[R3, #+0]
+        STR      R5,[R4, #+0]
+        ADDS     R4,R4,#+4
+        ADDS     R3,R3,#+4
+        SUBS     R2,R2,#+1
+??_tx_misra_message_copy_1:
+        CMP      R2,#+0
+        BNE.N    ??_tx_misra_message_copy_2
+??_tx_misra_message_copy_0:
+        STR      R3,[R0, #+0]
+        STR      R4,[R1, #+0]
+        POP      {R4,R5}
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  ULONG  _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1,         */
+/**                                           TX_TIMER_INTERNAL **ptr2);  */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_timer_pointer_dif:
+        SUBS     R0,R0,R1
+        ASRS     R0,R0,#+2
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL    */
+/**                                                  **ptr1, ULONG size); */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_timer_pointer_add:
+        ADD      R0,R0,R1, LSL #+2
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  VOID  _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL             */
+/**                              *internal_timer, TX_TIMER **user_timer); */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_user_timer_pointer_get:
+        ADDS     R2,R0,#+8
+        SUBS     R2,R2,R0
+        RSBS     R2,R2,#+0
+        ADD      R0,R0,R2
+        STR      R0,[R1, #+0]
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  VOID  _tx_misra_thread_stack_check(TX_THREAD *thread_ptr,            */
+/**                                              VOID **highest_stack);   */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_thread_stack_check:
+        PUSH     {R3-R5,LR}
+        MOVS     R4,R0
+        MOVS     R5,R1
+        BL       _tx_thread_interrupt_disable
+        CMP      R4,#+0
+        BEQ.N    ??_tx_misra_thread_stack_check_0
+        LDR      R1,[R4, #+0]
+        LDR.N    R2,??DataTable2  ;; 0x54485244
+        CMP      R1,R2
+        BNE.N    ??_tx_misra_thread_stack_check_0
+        LDR      R1,[R4, #+8]
+        LDR      R2,[R5, #+0]
+        CMP      R1,R2
+        BCS.N    ??_tx_misra_thread_stack_check_1
+        LDR      R1,[R4, #+8]
+        STR      R1,[R5, #+0]
+??_tx_misra_thread_stack_check_1:
+        LDR      R1,[R4, #+12]
+        LDR      R1,[R1, #+0]
+        CMP      R1,#-269488145
+        BNE.N    ??_tx_misra_thread_stack_check_2
+        LDR      R1,[R4, #+16]
+        LDR      R1,[R1, #+1]
+        CMP      R1,#-269488145
+        BNE.N    ??_tx_misra_thread_stack_check_2
+        LDR      R1,[R5, #+0]
+        LDR      R2,[R4, #+12]
+        CMP      R1,R2
+        BCS.N    ??_tx_misra_thread_stack_check_3
+??_tx_misra_thread_stack_check_2:
+        BL       _tx_thread_interrupt_restore
+        MOVS     R0,R4
+        BL       _tx_thread_stack_error_handler
+        BL       _tx_thread_interrupt_disable
+??_tx_misra_thread_stack_check_3:
+        LDR      R1,[R5, #+0]
+        LDR      R1,[R1, #-4]
+        CMP      R1,#-269488145
+        BEQ.N    ??_tx_misra_thread_stack_check_0
+        BL       _tx_thread_interrupt_restore
+        MOVS     R0,R4
+        BL       _tx_thread_stack_analyze
+        BL       _tx_thread_interrupt_disable
+??_tx_misra_thread_stack_check_0:
+        BL       _tx_thread_interrupt_restore
+        POP      {R0,R4,R5,PC}    ;; return
+
+#ifdef TX_ENABLE_EVENT_TRACE
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  VOID  _tx_misra_trace_event_insert(ULONG event_id,                   */
+/**           VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */
+/**           ULONG info_field_4, ULONG filter, ULONG time_stamp);        */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_trace_event_insert:
+        PUSH     {R3-R7,LR}
+        LDR.N    R4,??DataTable2_1
+        LDR      R4,[R4, #+0]
+        CMP      R4,#+0
+        BEQ.N    ??_tx_misra_trace_event_insert_0
+        LDR.N    R5,??DataTable2_2
+        LDR      R5,[R5, #+0]
+        LDR      R6,[SP, #+28]
+        TST      R5,R6
+        BEQ.N    ??_tx_misra_trace_event_insert_0
+        LDR.N    R5,??DataTable2_3
+        LDR      R5,[R5, #+0]
+        LDR.N    R6,??DataTable2_4
+        LDR      R6,[R6, #+0]
+        CMP      R5,#+0
+        BNE.N    ??_tx_misra_trace_event_insert_1
+        LDR      R5,[R6, #+44]
+        LDR      R7,[R6, #+60]
+        LSLS     R7,R7,#+16
+        ORRS     R7,R7,#0x80000000
+        ORRS     R5,R7,R5
+        B.N      ??_tx_misra_trace_event_insert_2
+??_tx_misra_trace_event_insert_1:
+        CMP      R5,#-252645136
+        BCS.N    ??_tx_misra_trace_event_insert_3
+        MOVS     R5,R6
+        MOVS     R6,#-1
+        B.N      ??_tx_misra_trace_event_insert_2
+??_tx_misra_trace_event_insert_3:
+        MOVS     R6,#-252645136
+        MOVS     R5,#+0
+??_tx_misra_trace_event_insert_2:
+        STR      R6,[R4, #+0]
+        STR      R5,[R4, #+4]
+        STR      R0,[R4, #+8]
+        LDR      R0,[SP, #+32]
+        STR      R0,[R4, #+12]
+        STR      R1,[R4, #+16]
+        STR      R2,[R4, #+20]
+        STR      R3,[R4, #+24]
+        LDR      R0,[SP, #+24]
+        STR      R0,[R4, #+28]
+        ADDS     R4,R4,#+32
+        LDR.N    R0,??DataTable2_5
+        LDR      R0,[R0, #+0]
+        CMP      R4,R0
+        BCC.N    ??_tx_misra_trace_event_insert_4
+        LDR.N    R0,??DataTable2_6
+        LDR      R4,[R0, #+0]
+        LDR.N    R0,??DataTable2_1
+        STR      R4,[R0, #+0]
+        LDR.N    R0,??DataTable2_7
+        LDR      R0,[R0, #+0]
+        STR      R4,[R0, #+32]
+        LDR.N    R0,??DataTable2_8
+        LDR      R0,[R0, #+0]
+        CMP      R0,#+0
+        BEQ.N    ??_tx_misra_trace_event_insert_0
+        LDR.N    R0,??DataTable2_7
+        LDR      R0,[R0, #+0]
+        LDR.N    R1,??DataTable2_8
+        LDR      R1,[R1, #+0]
+        BLX      R1
+        B.N      ??_tx_misra_trace_event_insert_0
+??_tx_misra_trace_event_insert_4:
+        LDR.N    R0,??DataTable2_1
+        STR      R4,[R0, #+0]
+        LDR.N    R0,??DataTable2_7
+        LDR      R0,[R0, #+0]
+        STR      R4,[R0, #+32]
+??_tx_misra_trace_event_insert_0:
+        POP      {R0,R4-R7,PC}    ;; return
+
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_1:
+        DC32     _tx_trace_buffer_current_ptr
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_2:
+        DC32     _tx_trace_event_enable_bits
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_5:
+        DC32     _tx_trace_buffer_end_ptr
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_6:
+        DC32     _tx_trace_buffer_start_ptr
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_7:
+        DC32     _tx_trace_header_ptr
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_8:
+        DC32     _tx_trace_full_notify_function
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  ULONG  _tx_misra_time_stamp_get(VOID);                               */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_time_stamp_get:
+        MOVS     R0,#+0
+        BX       LR               ;; return
+
+#endif
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2:
+        DC32     0x54485244
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_3:
+        DC32     _tx_thread_system_state
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_4:
+        DC32     _tx_thread_current_ptr
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  UINT  _tx_misra_always_true(void);                                   */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_always_true:
+        MOVS     R0,#+1
+        BX       LR               ;; return
+
+
+/******************************************************************************************/
+/******************************************************************************************/
+/**                                                                                       */
+/**  UCHAR  **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr);        */
+/**                                                                                       */
+/******************************************************************************************/
+/******************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_indirect_void_to_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/***************************************************************************************/
+/***************************************************************************************/
+/**                                                                                    */
+/**  UCHAR  **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer);       */
+/**                                                                                    */
+/***************************************************************************************/
+/***************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_indirect_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/***********************************************************************************/
+/***********************************************************************************/
+/**                                                                                */
+/**  UCHAR  *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool);   */
+/**                                                                                */
+/***********************************************************************************/
+/***********************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_block_pool_to_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/******************************************************************************************/
+/******************************************************************************************/
+/**                                                                                       */
+/**  TX_BLOCK_POOL  *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer);         */
+/**                                                                                       */
+/******************************************************************************************/
+/******************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_block_pool_pointer_convert:
+        BX       LR               ;; return
+
+
+/*****************************************************************************/
+/*****************************************************************************/
+/**                                                                          */
+/**  UCHAR  *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer);         */
+/**                                                                          */
+/*****************************************************************************/
+/*****************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/************************************************************************************/
+/************************************************************************************/
+/**                                                                                 */
+/**  TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer);  */
+/**                                                                                 */
+/************************************************************************************/
+/************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_block_pool_pointer_convert:
+        BX       LR               ;; return
+
+
+/**************************************************************************************/
+/**************************************************************************************/
+/**                                                                                   */
+/**  UCHAR  **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer);        */
+/**                                                                                   */
+/**************************************************************************************/
+/**************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_indirect_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/*****************************************************************************************/
+/*****************************************************************************************/
+/**                                                                                      */
+/**  TX_BYTE_POOL  *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer);          */
+/**                                                                                      */
+/*****************************************************************************************/
+/*****************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_byte_pool_pointer_convert:
+        BX       LR               ;; return
+
+
+/***************************************************************************************/
+/***************************************************************************************/
+/**                                                                                    */
+/**  UCHAR  *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool);         */
+/**                                                                                    */
+/***************************************************************************************/
+/***************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_byte_pool_to_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/*****************************************************************************************/
+/*****************************************************************************************/
+/**                                                                                      */
+/**  ALIGN_TYPE  *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer);         */
+/**                                                                                      */
+/*****************************************************************************************/
+/*****************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_align_type_pointer_convert:
+        BX       LR               ;; return
+
+
+/****************************************************************************************************/
+/****************************************************************************************************/
+/**                                                                                                 */
+/**  TX_BYTE_POOL  **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer);         */
+/**                                                                                                 */
+/****************************************************************************************************/
+/****************************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_indirect_byte_pool_pointer_convert:
+        BX       LR               ;; return
+
+
+/**************************************************************************************************/
+/**************************************************************************************************/
+/**                                                                                               */
+/**  TX_EVENT_FLAGS_GROUP  *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer);         */
+/**                                                                                               */
+/**************************************************************************************************/
+/**************************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_event_flags_pointer_convert:
+        BX       LR               ;; return
+
+
+/*****************************************************************************/
+/*****************************************************************************/
+/**                                                                          */
+/**  ULONG  *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer);         */
+/**                                                                          */
+/*****************************************************************************/
+/*****************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_ulong_pointer_convert:
+        BX       LR               ;; return
+
+
+/********************************************************************************/
+/********************************************************************************/
+/**                                                                             */
+/**  TX_MUTEX  *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer);         */
+/**                                                                             */
+/********************************************************************************/
+/********************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_mutex_pointer_convert:
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  UINT  _tx_misra_status_get(UINT status);                             */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_status_get:
+        MOVS     R0,#+0
+        BX       LR               ;; return
+
+
+/********************************************************************************/
+/********************************************************************************/
+/**                                                                             */
+/**  TX_QUEUE  *_tx_misra_void_to_queue_pointer_convert(VOID *pointer);         */
+/**                                                                             */
+/********************************************************************************/
+/********************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_queue_pointer_convert:
+        BX       LR               ;; return
+
+
+/****************************************************************************************/
+/****************************************************************************************/
+/**                                                                                     */
+/**  TX_SEMAPHORE  *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer);         */
+/**                                                                                     */
+/****************************************************************************************/
+/****************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_semaphore_pointer_convert:
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  VOID  *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer);      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_void_pointer_convert:
+        BX       LR               ;; return
+
+
+/*********************************************************************************/
+/*********************************************************************************/
+/**                                                                              */
+/**  TX_THREAD  *_tx_misra_ulong_to_thread_pointer_convert(ULONG value);         */
+/**                                                                              */
+/*********************************************************************************/
+/*********************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_ulong_to_thread_pointer_convert:
+        BX       LR               ;; return
+
+
+/***************************************************************************************************/
+/***************************************************************************************************/
+/**                                                                                                */
+/**  VOID  *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer);         */
+/**                                                                                                */
+/***************************************************************************************************/
+/***************************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_timer_indirect_to_void_pointer_convert:
+        BX       LR               ;; return
+
+
+/***************************************************************************************/
+/***************************************************************************************/
+/**                                                                                    */
+/**  CHAR  *_tx_misra_const_char_to_char_pointer_convert(const char *pointer);         */
+/**                                                                                    */
+/***************************************************************************************/
+/***************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_const_char_to_char_pointer_convert:
+        BX       LR               ;; return
+
+
+/**********************************************************************************/
+/**********************************************************************************/
+/**                                                                               */
+/**  TX_THREAD  *_tx_misra_void_to_thread_pointer_convert(void *pointer);         */
+/**                                                                               */
+/**********************************************************************************/
+/**********************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_thread_pointer_convert:
+        BX       LR               ;; return
+
+
+#ifdef TX_ENABLE_EVENT_TRACE
+
+/************************************************************************************************/
+/************************************************************************************************/
+/**                                                                                             */
+/**  UCHAR  *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer);         */
+/**                                                                                             */
+/************************************************************************************************/
+/************************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_object_to_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/************************************************************************************************/
+/************************************************************************************************/
+/**                                                                                             */
+/**  TX_TRACE_OBJECT_ENTRY  *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer);         */
+/**                                                                                             */
+/************************************************************************************************/
+/************************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_object_pointer_convert:
+        BX       LR               ;; return
+
+
+/******************************************************************************************/
+/******************************************************************************************/
+/**                                                                                       */
+/**  TX_TRACE_HEADER  *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer);         */
+/**                                                                                       */
+/******************************************************************************************/
+/******************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_header_pointer_convert:
+        BX       LR               ;; return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  TX_TRACE_BUFFER_ENTRY  *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer);         */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_entry_pointer_convert:
+        BX       LR               ;; return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  UCHAR  *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer);         */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_entry_to_uchar_pointer_convert:
+        BX       LR               ;; return
+#endif
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  UCHAR  *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer);                           */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_char_to_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  ULONG  _tx_misra_ipsr_get(void);                                                          */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_ipsr_get:
+        MRS      R0, IPSR
+        BX       LR               ;; return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  ULONG  _tx_misra_control_get(void);                                                       */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_control_get:
+        MRS      R0, CONTROL
+        BX       LR               ;; return
+
+        
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  void   _tx_misra_control_set(ULONG value);                                                */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_control_set:
+        MSR      CONTROL, R0
+        BX       LR               ;; return
+
+        
+#ifdef __ARMVFP__
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  ULONG  _tx_misra_fpccr_get(void);                                                         */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+_tx_misra_fpccr_get:
+        LDR      r0, =0xE000EF34  ; Build FPCCR address
+        LDR      r0, [r0]         ; Load FPCCR value
+        BX       LR               ;; return
+        
+        
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  void   _tx_misra_vfp_touch(void);                                                         */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_vfp_touch:
+        vmov.f32 s0, s0
+        BX       LR               ;; return
+        
+#endif
+        
+        
+        SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+        DC32 0
+
+        END
diff --git a/ports/cortex_m4/iar/src/tx_thread_context_restore.s b/ports/cortex_m4/iar/src/tx_thread_context_restore.s
new file mode 100644
index 00000000..1930c870
--- /dev/null
+++ b/ports/cortex_m4/iar/src/tx_thread_context_restore.s
@@ -0,0 +1,98 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+        EXTERN  _tx_execution_isr_exit
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_context_restore                        Cortex-M4/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function restores the interrupt context if it is processing a  */
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */
+;/*    if no thread was running, the function returns to the scheduler.    */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    [_tx_execution_isr_exit]              Execution profiling ISR exit  */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ISRs                                  Interrupt Service Routines    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_restore(VOID)
+;{
+    PUBLIC  _tx_thread_context_restore
+_tx_thread_context_restore:
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR exit function to indicate an ISR is complete.  */
+;
+    PUSH    {r0, lr}                            ; Save return address
+    BL      _tx_execution_isr_exit              ; Call the ISR exit function
+    POP     {r0, lr}                            ; Save return address
+#endif
+;
+    POP     {lr}
+    BX      lr
+;
+;}
+        END
+
diff --git a/ports/cortex_m4/iar/src/tx_thread_context_save.s b/ports/cortex_m4/iar/src/tx_thread_context_save.s
new file mode 100644
index 00000000..ab563506
--- /dev/null
+++ b/ports/cortex_m4/iar/src/tx_thread_context_save.s
@@ -0,0 +1,95 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+        EXTERN  _tx_execution_isr_enter
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_context_save                           Cortex-M4/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function saves the context of an executing thread in the       */
+;/*    beginning of interrupt processing.  The function also ensures that  */
+;/*    the system stack is used upon return to the calling ISR.            */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ISRs                                                                */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_save(VOID)
+;{
+    PUBLIC  _tx_thread_context_save
+_tx_thread_context_save:
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is starting.  */
+;   
+    PUSH    {r0, lr}                                ; Save return address
+    BL      _tx_execution_isr_enter                 ; Call the ISR enter function
+    POP     {r0, lr}                                ; Recover return address
+#endif
+;
+;    /* Context is already saved - just return!  */
+;
+    BX      lr
+;}
+    END
diff --git a/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s
new file mode 100644
index 00000000..e04f8ceb
--- /dev/null
+++ b/ports/cortex_m4/iar/src/tx_thread_interrupt_control.s
@@ -0,0 +1,86 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_control                      Cortex-M4/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for changing the interrupt lockout     */
+;/*    posture of the system.                                              */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    new_posture                           New interrupt lockout posture */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    old_posture                           Old interrupt lockout posture */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_control(UINT new_posture)
+;{
+    PUBLIC  _tx_thread_interrupt_control
+_tx_thread_interrupt_control:
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    MRS     r1, PRIMASK
+    MSR     PRIMASK, r0
+    MOV     r0, r1
+    BX      lr
+;
+;}
+    END
+        
diff --git a/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s
new file mode 100644
index 00000000..7807d5c8
--- /dev/null
+++ b/ports/cortex_m4/iar/src/tx_thread_interrupt_disable.s
@@ -0,0 +1,84 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_restore                      Cortex-M4/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for disabling interrupts and returning */
+;/*    the previous interrupt lockout posture.                             */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    old_posture                           Old interrupt lockout posture */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_disable(UINT new_posture)
+;{
+    PUBLIC  _tx_thread_interrupt_disable
+_tx_thread_interrupt_disable:
+;
+;    /* Return current interrupt lockout posture.  */
+;
+    MRS     r0, PRIMASK
+    CPSID   i
+    BX      lr
+;
+;}
+    END
diff --git a/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s
new file mode 100644
index 00000000..2159ae40
--- /dev/null
+++ b/ports/cortex_m4/iar/src/tx_thread_interrupt_restore.s
@@ -0,0 +1,83 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_restore                      Cortex-M4/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for restoring the previous             */
+;/*    interrupt lockout posture.                                          */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    previous_posture                      Previous interrupt posture    */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_interrupt_restore(UINT new_posture)
+;{
+    PUBLIC  _tx_thread_interrupt_restore
+_tx_thread_interrupt_restore:
+;
+;    /* Restore previous interrupt lockout posture.  */
+;
+    MSR     PRIMASK, r0
+    BX      lr
+;
+;}
+    END
diff --git a/ports/cortex_m4/iar/src/tx_thread_schedule.s b/ports/cortex_m4/iar/src/tx_thread_schedule.s
new file mode 100644
index 00000000..df0e74b2
--- /dev/null
+++ b/ports/cortex_m4/iar/src/tx_thread_schedule.s
@@ -0,0 +1,291 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;   
+        EXTERN  _tx_thread_current_ptr
+        EXTERN  _tx_thread_execute_ptr
+        EXTERN  _tx_timer_time_slice
+        EXTERN  _tx_thread_system_stack_ptr
+        EXTERN  _tx_execution_thread_enter
+        EXTERN  _tx_execution_thread_exit
+        EXTERN  _tx_thread_preempt_disable
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_schedule                               Cortex-M4/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function waits for a thread control block pointer to appear in */
+;/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
+;/*    in the variable, the corresponding thread is resumed.               */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter          ThreadX entry function         */
+;/*    _tx_thread_system_return             Return to system from thread   */
+;/*    _tx_thread_context_restore           Restore thread's context       */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_schedule(VOID)
+;{
+    PUBLIC  _tx_thread_schedule
+_tx_thread_schedule:
+;
+;    /* This function should only ever be called on Cortex-M
+;       from the first schedule request. Subsequent scheduling occurs
+;       from the PendSV handling routines below. */
+;
+;    /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets.  */
+;     
+    MOV     r0, #0                                  ; Build value for TX_FALSE
+    LDR     r2, =_tx_thread_preempt_disable         ; Build address of preempt disable flag
+    STR     r0, [r2, #0]                            ; Clear preempt disable flag
+;
+;    /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked.  */
+;
+#ifdef __ARMVFP__
+    MRS     r0, CONTROL                             ; Pickup current CONTROL register
+    BIC     r0, r0, #4                              ; Clear the FPCA bit 
+    MSR     CONTROL, r0                             ; Setup new CONTROL register
+#endif
+;
+;    /* Enable interrupts */
+;
+    CPSIE   i
+;            
+;    /* Enter the scheduler for the first time.  */
+;
+    MOV     r0, #0x10000000                         ; Load PENDSVSET bit
+    MOV     r1, #0xE000E000                         ; Load NVIC base
+    STR     r0, [r1, #0xD04]                        ; Set PENDSVBIT in ICSR
+    DSB                                             ; Complete all memory accesses
+    ISB                                             ; Flush pipeline
+;
+;    /* Wait here for the PendSV to take place.  */
+;     
+__tx_wait_here:
+    B       __tx_wait_here                          ; Wait for the PendSV to happen
+;}
+;
+;    /* Generic context PendSV handler.  */
+;     
+    PUBLIC  PendSV_Handler
+    PUBLIC  __tx_PendSVHandler
+PendSV_Handler:
+__tx_PendSVHandler:
+;
+;    /* Get current thread value and new thread pointer.  */
+;       
+__tx_ts_handler: 
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread exit function to indicate the thread is no longer executing.  */
+;
+    CPSID   i                                       ; Disable interrupts
+    PUSH    {r0, lr}                                ; Save LR (and r0 just for alignment)
+    BL      _tx_execution_thread_exit               ; Call the thread exit function
+    POP     {r0, lr}                                ; Recover LR
+    CPSIE   i                                       ; Enable interrupts
+#endif
+    MOV32   r0, _tx_thread_current_ptr              ; Build current thread pointer address
+    MOV32   r2, _tx_thread_execute_ptr              ; Build execute thread pointer address
+    MOV     r3, #0                                  ; Build NULL value
+    LDR     r1, [r0]                                ; Pickup current thread pointer
+;
+;    /* Determine if there is a current thread to finish preserving.  */
+;       
+    CBZ     r1, __tx_ts_new                         ; If NULL, skip preservation
+;
+;    /* Recover PSP and preserve current thread context.  */
+;
+    STR     r3, [r0]                                ; Set _tx_thread_current_ptr to NULL
+    MRS     r12, PSP                                ; Pickup PSP pointer (thread's stack pointer)
+    STMDB   r12!, {r4-r11}                          ; Save its remaining registers
+#ifdef __ARMVFP__
+    TST     LR, #0x10                               ; Determine if the VFP extended frame is present
+    BNE     _skip_vfp_save
+    VSTMDB  r12!,{s16-s31}                          ; Yes, save additional VFP registers
+_skip_vfp_save:
+#endif
+    MOV32   r4, _tx_timer_time_slice                ; Build address of time-slice variable
+    STMDB   r12!, {LR}                              ; Save LR on the stack
+;
+;    /* Determine if time-slice is active. If it isn't, skip time handling processing.  */
+;
+    LDR     r5, [r4]                                ; Pickup current time-slice
+    STR     r12, [r1, #8]                           ; Save the thread stack pointer
+    CBZ     r5, __tx_ts_new                         ; If not active, skip processing
+;
+;    /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable.  */
+;
+    STR     r5, [r1, #24]                           ; Save current time-slice
+;
+;    /* Clear the global time-slice.  */
+;
+    STR     r3, [r4]                                ; Clear time-slice
+;
+;       
+;    /* Executing thread is now completely preserved!!!  */
+;
+__tx_ts_new:
+;
+;    /* Now we are looking for a new thread to execute!  */
+;
+    CPSID   i                                       ; Disable interrupts
+    LDR     r1, [r2]                                ; Is there another thread ready to execute?
+    CBZ     r1, __tx_ts_wait                        ; No, skip to the wait processing
+;
+;    /* Yes, another thread is ready for else, make the current thread the new thread.  */
+;
+    STR     r1, [r0]                                ; Setup the current thread pointer to the new thread
+    CPSIE   i                                       ; Enable interrupts
+;
+;    /* Increment the thread run count.  */
+;
+__tx_ts_restore:
+    LDR     r7, [r1, #4]                            ; Pickup the current thread run count
+    MOV32   r4, _tx_timer_time_slice                ; Build address of time-slice variable
+    LDR     r5, [r1, #24]                           ; Pickup thread's current time-slice
+    ADD     r7, r7, #1                              ; Increment the thread run count
+    STR     r7, [r1, #4]                            ; Store the new run count
+;
+;    /* Setup global time-slice with thread's current time-slice.  */
+;
+    STR     r5, [r4]                                ; Setup global time-slice
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread entry function to indicate the thread is executing.  */
+;
+    PUSH    {r0, r1}                                ; Save r0/r1
+    BL      _tx_execution_thread_enter              ; Call the thread execution enter function
+    POP     {r0, r1}                                ; Recover r3
+#endif
+;
+;    /* Restore the thread context and PSP.  */
+;
+    LDR     r12, [r1, #8]                           ; Pickup thread's stack pointer
+    LDMIA   r12!, {LR}                              ; Pickup LR
+#ifdef __ARMVFP__
+    TST     LR, #0x10                               ; Determine if the VFP extended frame is present
+    BNE     _skip_vfp_restore                       ; If not, skip VFP restore 
+    VLDMIA  r12!, {s16-s31}                         ; Yes, restore additional VFP registers
+_skip_vfp_restore:
+#endif
+    LDMIA   r12!, {r4-r11}                          ; Recover thread's registers
+    MSR     PSP, r12                                ; Setup the thread's stack pointer
+;
+;    /* Return to thread.  */
+;       
+    BX      lr                                      ; Return to thread!
+;
+;    /* The following is the idle wait processing... in this case, no threads are ready for execution and the
+;       system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts 
+;       are disabled to allow use of WFI for waiting for a thread to arrive.  */
+;
+__tx_ts_wait:
+    CPSID   i                                       ; Disable interrupts
+    LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
+    STR     r1, [r0]                                ; Store it in the current pointer
+    CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+#ifdef TX_ENABLE_WFI
+    DSB                                             ; Ensure no outstanding memory transactions
+    WFI                                             ; Wait for interrupt
+    ISB                                             ; Ensure pipeline is flushed
+#endif
+    CPSIE   i                                       ; Enable interrupts
+    B       __tx_ts_wait                            ; Loop to continue waiting
+;
+;    /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are 
+;       already in the handler!  */
+;
+__tx_ts_ready:
+    MOV     r7, #0x08000000                         ; Build clear PendSV value
+    MOV     r8, #0xE000E000                         ; Build base NVIC address
+    STR     r7, [r8, #0xD04]                        ; Clear any PendSV 
+;
+;    /* Re-enable interrupts and restore new thread.  */
+;       
+    CPSIE   i                                       ; Enable interrupts
+    B       __tx_ts_restore                         ; Restore the thread
+;}
+;
+#ifdef __ARMVFP__
+
+    PUBLIC  tx_thread_fpu_enable
+tx_thread_fpu_enable:
+;
+;    /* Automatic VPF logic is supported, this function is present only for 
+;       backward compatibility purposes and therefore simply returns.  */
+;
+    BX      LR                                      ; Return to caller
+
+    PUBLIC  tx_thread_fpu_disable
+tx_thread_fpu_disable:
+;
+;    /* Automatic VPF logic is supported, this function is present only for 
+;       backward compatibility purposes and therefore simply returns.  */
+;
+    BX      LR                                      ; Return to caller
+
+#endif
+
+    END
+        
diff --git a/ports/cortex_m4/iar/src/tx_thread_stack_build.s b/ports/cortex_m4/iar/src/tx_thread_stack_build.s
new file mode 100644
index 00000000..61b86ab9
--- /dev/null
+++ b/ports/cortex_m4/iar/src/tx_thread_stack_build.s
@@ -0,0 +1,144 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_stack_build                            Cortex-M4/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function builds a stack frame on the supplied thread's stack.  */
+;/*    The stack frame results in a fake interrupt return to the supplied  */
+;/*    function pointer.                                                   */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    thread_ptr                            Pointer to thread control blk */
+;/*    function_ptr                          Pointer to return function    */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_thread_create                     Create thread service         */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+;{
+    PUBLIC  _tx_thread_stack_build
+_tx_thread_stack_build:
+;
+;       
+;    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+;       on the Cortex-M should look like the following after it is built:
+;       
+;       Stack Top:      
+;                       LR          Interrupted LR (LR at time of PENDSV)
+;                       r4          Initial value for r4
+;                       r5          Initial value for r5
+;                       r6          Initial value for r6
+;                       r7          Initial value for r7
+;                       r8          Initial value for r8
+;                       r9          Initial value for r9
+;                       r10         Initial value for r10
+;                       r11         Initial value for r11
+;                       r0          Initial value for r0    (Hardware stack starts here!!)
+;                       r1          Initial value for r1
+;                       r2          Initial value for r2
+;                       r3          Initial value for r3
+;                       r12         Initial value for r12
+;                       lr          Initial value for lr
+;                       pc          Initial value for pc
+;                       xPSR        Initial value for xPSR
+;
+;    Stack Bottom: (higher memory address)  */
+;
+    LDR     r2, [r0, #16]                           ; Pickup end of stack area
+    BIC     r2, r2, #0x7                            ; Align frame for 8-byte alignment
+    SUB     r2, r2, #68                             ; Subtract frame size
+    LDR     r3, =0xFFFFFFFD                         ; Build initial LR value
+    STR     r3, [r2, #0]                            ; Save on the stack
+;
+;    /* Actually build the stack frame.  */
+;
+    MOV     r3, #0                                  ; Build initial register value
+    STR     r3, [r2, #4]                            ; Store initial r4
+    STR     r3, [r2, #8]                            ; Store initial r5
+    STR     r3, [r2, #12]                           ; Store initial r6
+    STR     r3, [r2, #16]                           ; Store initial r7
+    STR     r3, [r2, #20]                           ; Store initial r8
+    STR     r3, [r2, #24]                           ; Store initial r9
+    STR     r3, [r2, #28]                           ; Store initial r10
+    STR     r3, [r2, #32]                           ; Store initial r11
+;
+;    /* Hardware stack follows.  /
+;
+    STR     r3, [r2, #36]                           ; Store initial r0
+    STR     r3, [r2, #40]                           ; Store initial r1
+    STR     r3, [r2, #44]                           ; Store initial r2
+    STR     r3, [r2, #48]                           ; Store initial r3
+    STR     r3, [r2, #52]                           ; Store initial r12
+    MOV     r3, #0xFFFFFFFF                         ; Poison EXC_RETURN value
+    STR     r3, [r2, #56]                           ; Store initial lr
+    STR     r1, [r2, #60]                           ; Store initial pc
+    MOV     r3, #0x01000000                         ; Only T-bit need be set
+    STR     r3, [r2, #64]                           ; Store initial xPSR
+;
+;    /* Setup stack pointer.  */
+;    thread_ptr -> tx_thread_stack_ptr =  r2;
+;
+    STR     r2, [r0, #8]                            ; Save stack pointer in thread's
+                                                    ;   control block
+    BX      lr                                      ; Return to caller
+;}
+    END
+
diff --git a/ports/cortex_m4/iar/src/tx_thread_system_return.s b/ports/cortex_m4/iar/src/tx_thread_system_return.s
new file mode 100644
index 00000000..9820752e
--- /dev/null
+++ b/ports/cortex_m4/iar/src/tx_thread_system_return.s
@@ -0,0 +1,98 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_system_return                          Cortex-M4/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is target processor specific.  It is used to transfer */
+;/*    control from a thread back to the ThreadX system.  Only a           */
+;/*    minimal context is saved since the compiler assumes temp registers  */
+;/*    are going to get slicked by a function call anyway.                 */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_schedule                   Thread scheduling loop        */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ThreadX components                                                  */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_system_return(VOID)
+;{
+    PUBLIC  _tx_thread_system_return
+_tx_thread_system_return??rA:
+_tx_thread_system_return:
+;
+;    /* Return to real scheduler via PendSV. Note that this routine is often 
+;       replaced with in-line assembly in tx_port.h to improved performance.  */
+;     
+    MOV     r0, #0x10000000                         ; Load PENDSVSET bit
+    MOV     r1, #0xE000E000                         ; Load NVIC base
+    STR     r0, [r1, #0xD04]                        ; Set PENDSVBIT in ICSR
+    MRS     r0, IPSR                                ; Pickup IPSR
+    CMP     r0, #0                                  ; Is it a thread returning?
+    BNE     _isr_context                            ; If ISR, skip interrupt enable
+    MRS     r1, PRIMASK                             ; Thread context returning, pickup PRIMASK
+    CPSIE   i                                       ; Enable interrupts
+    MSR     PRIMASK, r1                             ; Restore original interrupt posture
+_isr_context:
+    BX      lr                                      ; Return to caller 
+;}
+    END  
+    
diff --git a/ports/cortex_m4/iar/src/tx_timer_interrupt.s b/ports/cortex_m4/iar/src/tx_timer_interrupt.s
new file mode 100644
index 00000000..0a3c3e52
--- /dev/null
+++ b/ports/cortex_m4/iar/src/tx_timer_interrupt.s
@@ -0,0 +1,268 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Timer                                                               */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_timer.h"
+;#include "tx_thread.h"
+;
+;
+;Define Assembly language external references...
+;
+    EXTERN      _tx_timer_time_slice
+    EXTERN      _tx_timer_system_clock
+    EXTERN      _tx_timer_current_ptr
+    EXTERN      _tx_timer_list_start
+    EXTERN      _tx_timer_list_end
+    EXTERN      _tx_timer_expired_time_slice
+    EXTERN      _tx_timer_expired
+    EXTERN      _tx_thread_time_slice
+    EXTERN      _tx_timer_expiration_process
+    EXTERN      _tx_thread_current_ptr
+    EXTERN      _tx_thread_execute_ptr
+    EXTERN      _tx_thread_preempt_disable
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_timer_interrupt                               Cortex-M4/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function processes the hardware timer interrupt.  This         */
+;/*    processing includes incrementing the system clock and checking for  */
+;/*    time slice and/or timer expiration.  If either is found, the        */
+;/*    expiration functions are called.                                    */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_timer_expiration_process          Timer expiration processing   */
+;/*    _tx_thread_time_slice                 Time slice interrupted thread */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    interrupt vector                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_timer_interrupt(VOID)
+;{
+    PUBLIC  _tx_timer_interrupt
+_tx_timer_interrupt:
+;
+;    /* Upon entry to this routine, it is assumed that the compiler scratch registers are available
+;       for use.  */
+;
+;    /* Increment the system clock.  */
+;    _tx_timer_system_clock++;
+;
+    MOV32   r1, _tx_timer_system_clock              ; Pickup address of system clock
+    LDR     r0, [r1, #0]                            ; Pickup system clock
+    ADD     r0, r0, #1                              ; Increment system clock
+    STR     r0, [r1, #0]                            ; Store new system clock
+;
+;    /* Test for time-slice expiration.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    MOV32   r3, _tx_timer_time_slice                ; Pickup address of time-slice 
+    LDR     r2, [r3, #0]                            ; Pickup time-slice
+    CBZ     r2,  __tx_timer_no_time_slice           ; Is it non-active?
+                                                    ; Yes, skip time-slice processing
+;
+;       /* Decrement the time_slice.  */
+;       _tx_timer_time_slice--;
+;
+    SUB     r2, r2, #1                              ; Decrement the time-slice
+    STR     r2, [r3, #0]                            ; Store new time-slice value
+;
+;       /* Check for expiration.  */
+;       if (__tx_timer_time_slice == 0)
+;
+    CBNZ    r2, __tx_timer_no_time_slice            ; Has it expired?
+;
+;       /* Set the time-slice expired flag.  */
+;       _tx_timer_expired_time_slice =  TX_TRUE;
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup address of expired flag
+    MOV     r0, #1                                  ; Build expired value
+    STR     r0, [r3, #0]                            ; Set time-slice expiration flag
+;
+;    }
+;
+__tx_timer_no_time_slice:
+;
+;    /* Test for timer expiration.  */
+;    if (*_tx_timer_current_ptr)
+;    {
+;
+    MOV32   r1, _tx_timer_current_ptr               ; Pickup current timer pointer address
+    LDR     r0, [r1, #0]                            ; Pickup current timer
+    LDR     r2, [r0, #0]                            ; Pickup timer list entry
+    CBZ     r2, __tx_timer_no_timer                 ; Is there anything in the list?
+                                                    ; No, just increment the timer
+;
+;        /* Set expiration flag.  */
+;        _tx_timer_expired =  TX_TRUE;
+;
+    MOV32   r3, _tx_timer_expired                   ; Pickup expiration flag address
+    MOV     r2, #1                                  ; Build expired value
+    STR     r2, [r3, #0]                            ; Set expired flag
+    B       __tx_timer_done                         ; Finished timer processing
+;
+;    }
+;    else
+;    {
+__tx_timer_no_timer:
+;
+;        /* No timer expired, increment the timer pointer.  */
+;        _tx_timer_current_ptr++;
+;
+    ADD     r0, r0, #4                              ; Move to next timer
+;
+;        /* Check for wrap-around.  */
+;        if (_tx_timer_current_ptr == _tx_timer_list_end)
+;
+    MOV32   r3, _tx_timer_list_end                  ; Pickup addr of timer list end
+    LDR     r2, [r3, #0]                            ; Pickup list end
+    CMP     r0, r2                                  ; Are we at list end?
+    BNE     __tx_timer_skip_wrap                    ; No, skip wrap-around logic
+;
+;            /* Wrap to beginning of list.  */
+;            _tx_timer_current_ptr =  _tx_timer_list_start;
+;
+    MOV32   r3, _tx_timer_list_start                ; Pickup addr of timer list start
+    LDR     r0, [r3, #0]                            ; Set current pointer to list start
+;
+__tx_timer_skip_wrap:
+;
+    STR     r0, [r1, #0]                            ; Store new current timer pointer
+;    }
+;
+__tx_timer_done:
+;
+;
+;    /* See if anything has expired.  */
+;    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+;    {
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup addr of expired flag
+    LDR     r2, [r3, #0]                            ; Pickup time-slice expired flag
+    CBNZ    r2, __tx_something_expired              ; Did a time-slice expire?
+                                                    ; If non-zero, time-slice expired
+    MOV32   r1, _tx_timer_expired                   ; Pickup addr of other expired flag
+    LDR     r0, [r1, #0]                            ; Pickup timer expired flag
+    CBZ     r0, __tx_timer_nothing_expired          ; Did a timer expire?
+                                                    ; No, nothing expired
+;
+__tx_something_expired:
+;
+;
+    STMDB   sp!, {r0, lr}                           ; Save the lr register on the stack
+                                                    ;   and save r0 just to keep 8-byte alignment
+;
+;    /* Did a timer expire?  */
+;    if (_tx_timer_expired)
+;    {
+;
+    MOV32   r1, _tx_timer_expired                   ; Pickup addr of expired flag
+    LDR     r0, [r1, #0]                            ; Pickup timer expired flag
+    CBZ     r0, __tx_timer_dont_activate            ; Check for timer expiration
+                                                    ; If not set, skip timer activation
+;
+;        /* Process timer expiration.  */
+;        _tx_timer_expiration_process();
+;
+    BL      _tx_timer_expiration_process            ; Call the timer expiration handling routine
+;
+;    }
+__tx_timer_dont_activate:
+;
+;    /* Did time slice expire?  */
+;    if (_tx_timer_expired_time_slice)
+;    {
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup addr of time-slice expired 
+    LDR     r2, [r3, #0]                            ; Pickup the actual flag
+    CBZ     r2, __tx_timer_not_ts_expiration        ; See if the flag is set
+                                                    ; No, skip time-slice processing
+;
+;        /* Time slice interrupted thread.  */
+;        _tx_thread_time_slice(); 
+
+    BL      _tx_thread_time_slice                   ; Call time-slice processing
+    MOV32   r0, _tx_thread_preempt_disable          ; Build address of preempt disable flag
+    LDR     r1, [r0]                                ; Is the preempt disable flag set?
+    CBNZ    r1, __tx_timer_skip_time_slice          ; Yes, skip the PendSV logic
+    MOV32   r0, _tx_thread_current_ptr              ; Build current thread pointer address
+    LDR     r1, [r0]                                ; Pickup the current thread pointer
+    MOV32   r2, _tx_thread_execute_ptr              ; Build execute thread pointer address
+    LDR     r3, [r2]                                ; Pickup the execute thread pointer
+    MOV32   r0, 0xE000ED04                          ; Build address of control register
+    MOV32   r2, 0x10000000                          ; Build value for PendSV bit
+    CMP     r1, r3                                  ; Are they the same?
+    BEQ     __tx_timer_skip_time_slice              ; If the same, there was no time-slice performed
+    STR     r2, [r0]                                ; Not the same, issue the PendSV for preemption
+__tx_timer_skip_time_slice:
+;
+;    }
+;
+__tx_timer_not_ts_expiration:
+;
+    LDMIA   sp!, {r0, lr}                           ; Recover lr register (r0 is just there for
+                                                    ;   the 8-byte stack alignment
+;
+;    }
+;
+__tx_timer_nothing_expired:
+
+    DSB                                             ; Complete all memory access
+    BX      lr                                      ; Return to caller
+;
+;}
+    END
+
diff --git a/ports/cortex_m4/keil/example_build/ThreadX_Demo.uvopt b/ports/cortex_m4/keil/example_build/ThreadX_Demo.uvopt
new file mode 100644
index 00000000..8586e313
--- /dev/null
+++ b/ports/cortex_m4/keil/example_build/ThreadX_Demo.uvopt
@@ -0,0 +1,305 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj; *.o
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+    0
+  
+
+  
+    0
+    0
+  
+
+  
+    ThreadX_Demo
+    0x4
+    ARM-ADS
+    
+      12000000
+      
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      255
+      
+        1
+        0
+        1
+        0
+        1
+        1
+        1
+        1
+        1
+        1
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+        1
+        1
+        1
+        0
+        1
+        0
+        1
+        1
+        0
+        0
+        1
+        0
+        0
+        -1
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        
+      
+      
+        
+          0
+          ARMRTXEVENTFLAGS
+          -L70 -Z18 -C0 -M0 -T1
+        
+        
+          0
+          DLGDARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)
+        
+        
+          0
+          DLGUARM
+          (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)
+        
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          -T5F
+        
+        
+          0
+          UL2CM3
+          -UV0289BJE -O14 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_16 -FS00 -FL04000
+        
+      
+      
+      
+        
+          0
+          1
+          thread_0_counter
+        
+        
+          1
+          1
+          thread_1_counter
+        
+        
+          2
+          1
+          thread_2_counter
+        
+        
+          3
+          1
+          thread_3_counter
+        
+        
+          4
+          1
+          thread_4_counter
+        
+        
+          5
+          1
+          thread_5_counter
+        
+        
+          6
+          1
+          _tx_thread_current_ptr
+        
+      
+      
+        0
+      
+      
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
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new file mode 100644
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diff --git a/ports/cortex_m4/keil/example_build/ThreadX_Library.plg b/ports/cortex_m4/keil/example_build/ThreadX_Library.plg
new file mode 100644
index 00000000..725a791b
--- /dev/null
+++ b/ports/cortex_m4/keil/example_build/ThreadX_Library.plg
@@ -0,0 +1,203 @@
+
+
+
+
µVision Build Log

+
Project:

+C:\release\threadx\ThreadX_Library.uvproj
+Project File Date:  06/28/2012
+
+
Output:

+Build target 'ThreadX_Library_Project'
+compiling txe_timer_info_get.c...
+compiling tx_block_allocate.c...
+compiling tx_block_pool_cleanup.c...
+compiling tx_block_pool_create.c...
+compiling tx_block_pool_delete.c...
+compiling tx_block_pool_info_get.c...
+compiling tx_block_pool_initialize.c...
+compiling tx_block_pool_performance_info_get.c...
+compiling tx_block_pool_performance_system_info_get.c...
+compiling tx_block_pool_prioritize.c...
+compiling tx_block_release.c...
+compiling tx_byte_allocate.c...
+compiling tx_byte_pool_cleanup.c...
+compiling tx_byte_pool_create.c...
+compiling tx_byte_pool_delete.c...
+compiling tx_byte_pool_info_get.c...
+compiling tx_byte_pool_initialize.c...
+compiling tx_byte_pool_performance_info_get.c...
+compiling tx_byte_pool_performance_system_info_get.c...
+compiling tx_byte_pool_prioritize.c...
+compiling tx_byte_pool_search.c...
+compiling tx_byte_release.c...
+compiling tx_event_flags_cleanup.c...
+compiling tx_event_flags_create.c...
+compiling tx_event_flags_delete.c...
+compiling tx_event_flags_get.c...
+compiling tx_event_flags_info_get.c...
+compiling tx_event_flags_initialize.c...
+compiling tx_event_flags_performance_info_get.c...
+compiling tx_event_flags_performance_system_info_get.c...
+compiling tx_event_flags_set.c...
+compiling tx_event_flags_set_notify.c...
+compiling tx_initialize_high_level.c...
+compiling tx_initialize_kernel_enter.c...
+compiling tx_initialize_kernel_setup.c...
+compiling tx_mutex_cleanup.c...
+compiling tx_mutex_create.c...
+compiling tx_mutex_delete.c...
+compiling tx_mutex_get.c...
+compiling tx_mutex_info_get.c...
+compiling tx_mutex_initialize.c...
+compiling tx_mutex_performance_info_get.c...
+compiling tx_mutex_performance_system_info_get.c...
+compiling tx_mutex_prioritize.c...
+compiling tx_mutex_priority_change.c...
+compiling tx_mutex_put.c...
+compiling tx_queue_cleanup.c...
+compiling tx_queue_create.c...
+compiling tx_queue_delete.c...
+compiling tx_queue_flush.c...
+compiling tx_queue_front_send.c...
+compiling tx_queue_info_get.c...
+compiling tx_queue_initialize.c...
+compiling tx_queue_performance_info_get.c...
+compiling tx_queue_performance_system_info_get.c...
+compiling tx_queue_prioritize.c...
+compiling tx_queue_receive.c...
+compiling tx_queue_send.c...
+compiling tx_queue_send_notify.c...
+compiling tx_semaphore_ceiling_put.c...
+compiling tx_semaphore_cleanup.c...
+compiling tx_semaphore_create.c...
+compiling tx_semaphore_delete.c...
+compiling tx_semaphore_get.c...
+compiling tx_semaphore_info_get.c...
+compiling tx_semaphore_initialize.c...
+compiling tx_semaphore_performance_info_get.c...
+compiling tx_semaphore_performance_system_info_get.c...
+compiling tx_semaphore_prioritize.c...
+compiling tx_semaphore_put.c...
+compiling tx_semaphore_put_notify.c...
+compiling tx_thread_create.c...
+compiling tx_thread_delete.c...
+compiling tx_thread_entry_exit_notify.c...
+compiling tx_thread_identify.c...
+compiling tx_thread_info_get.c...
+compiling tx_thread_initialize.c...
+compiling tx_thread_performance_info_get.c...
+compiling tx_thread_performance_system_info_get.c...
+compiling tx_thread_preemption_change.c...
+compiling tx_thread_priority_change.c...
+compiling tx_thread_relinquish.c...
+compiling tx_thread_reset.c...
+compiling tx_thread_resume.c...
+compiling tx_thread_shell_entry.c...
+compiling tx_thread_sleep.c...
+compiling tx_thread_stack_analyze.c...
+compiling tx_thread_stack_error_handler.c...
+compiling tx_thread_stack_error_notify.c...
+compiling tx_thread_suspend.c...
+compiling tx_thread_system_preempt_check.c...
+compiling tx_thread_system_resume.c...
+compiling tx_thread_system_suspend.c...
+compiling tx_thread_terminate.c...
+compiling tx_thread_time_slice.c...
+compiling tx_thread_time_slice_change.c...
+compiling tx_thread_timeout.c...
+compiling tx_thread_wait_abort.c...
+compiling tx_time_get.c...
+compiling tx_time_set.c...
+compiling tx_timer_activate.c...
+compiling tx_timer_change.c...
+compiling tx_timer_create.c...
+compiling tx_timer_deactivate.c...
+compiling tx_timer_delete.c...
+compiling tx_timer_expiration_process.c...
+compiling tx_timer_info_get.c...
+compiling tx_timer_initialize.c...
+compiling tx_timer_performance_info_get.c...
+compiling tx_timer_performance_system_info_get.c...
+compiling tx_timer_system_activate.c...
+compiling tx_timer_system_deactivate.c...
+compiling tx_timer_thread_entry.c...
+compiling tx_trace_disable.c...
+compiling tx_trace_enable.c...
+compiling tx_trace_initialize.c...
+compiling tx_trace_interrupt_control.c...
+compiling tx_trace_isr_enter_insert.c...
+compiling tx_trace_isr_exit_insert.c...
+compiling tx_trace_object_register.c...
+compiling tx_trace_object_unregister.c...
+compiling tx_trace_user_event_insert.c...
+compiling txe_block_allocate.c...
+compiling txe_block_pool_create.c...
+compiling txe_block_pool_delete.c...
+compiling txe_block_pool_info_get.c...
+compiling txe_block_pool_prioritize.c...
+compiling txe_block_release.c...
+compiling txe_byte_allocate.c...
+compiling txe_byte_pool_create.c...
+compiling txe_byte_pool_delete.c...
+compiling txe_byte_pool_info_get.c...
+compiling txe_byte_pool_prioritize.c...
+compiling txe_byte_release.c...
+compiling txe_event_flags_create.c...
+compiling txe_event_flags_delete.c...
+compiling txe_event_flags_get.c...
+compiling txe_event_flags_info_get.c...
+compiling txe_event_flags_set.c...
+compiling txe_event_flags_set_notify.c...
+compiling txe_mutex_create.c...
+compiling txe_mutex_delete.c...
+compiling txe_mutex_get.c...
+compiling txe_mutex_info_get.c...
+compiling txe_mutex_prioritize.c...
+compiling txe_mutex_put.c...
+compiling txe_queue_create.c...
+compiling txe_queue_delete.c...
+compiling txe_queue_flush.c...
+compiling txe_queue_front_send.c...
+compiling txe_queue_info_get.c...
+compiling txe_queue_prioritize.c...
+compiling txe_queue_receive.c...
+compiling txe_queue_send.c...
+compiling txe_queue_send_notify.c...
+compiling txe_semaphore_ceiling_put.c...
+compiling txe_semaphore_create.c...
+compiling txe_semaphore_delete.c...
+compiling txe_semaphore_get.c...
+compiling txe_semaphore_info_get.c...
+compiling txe_semaphore_prioritize.c...
+compiling txe_semaphore_put.c...
+compiling txe_semaphore_put_notify.c...
+compiling txe_thread_create.c...
+compiling txe_thread_delete.c...
+compiling txe_thread_entry_exit_notify.c...
+compiling txe_thread_info_get.c...
+compiling txe_thread_preemption_change.c...
+compiling txe_thread_priority_change.c...
+compiling txe_thread_relinquish.c...
+compiling txe_thread_reset.c...
+compiling txe_thread_resume.c...
+compiling txe_thread_suspend.c...
+compiling txe_thread_terminate.c...
+compiling txe_thread_time_slice_change.c...
+compiling txe_thread_wait_abort.c...
+compiling txe_timer_activate.c...
+compiling txe_timer_change.c...
+compiling txe_timer_create.c...
+compiling txe_timer_deactivate.c...
+compiling txe_timer_delete.c...
+assembling tx_timer_interrupt.s...
+assembling tx_thread_context_restore.s...
+assembling tx_thread_context_save.s...
+assembling tx_thread_interrupt_control.s...
+assembling tx_thread_schedule.s...
+assembling tx_thread_stack_build.s...
+assembling tx_thread_system_return.s...
+compiling tx_trace_buffer_full_notify.c...
+compiling tx_trace_event_filter.c...
+compiling tx_trace_event_unfilter.c...
+creating Library...
+"ThreadX_Library.lib" - 0 Error(s), 0 Warning(s).
diff --git a/ports/cortex_m4/keil/example_build/ThreadX_Library.uvopt b/ports/cortex_m4/keil/example_build/ThreadX_Library.uvopt
new file mode 100644
index 00000000..8205883f
--- /dev/null
+++ b/ports/cortex_m4/keil/example_build/ThreadX_Library.uvopt
@@ -0,0 +1,2664 @@
+
+
+
+  1.0
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+  
### uVision Project, (C) Keil Software

+
+  
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+  
+
+
diff --git a/ports/cortex_m4/keil/example_build/ThreadX_Library.uvproj b/ports/cortex_m4/keil/example_build/ThreadX_Library.uvproj
new file mode 100644
index 00000000..5c577681
--- /dev/null
+++ b/ports/cortex_m4/keil/example_build/ThreadX_Library.uvproj
@@ -0,0 +1,1481 @@
+
+
+
+  1.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
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+              1
+              ..\..\..\..\common\src\tx_timer_thread_entry.c
+            
+            
+              tx_trace_buffer_full_notify.c
+              1
+              ..\..\..\..\common\src\tx_trace_buffer_full_notify.c
+            
+            
+              tx_trace_disable.c
+              1
+              ..\..\..\..\common\src\tx_trace_disable.c
+            
+            
+              tx_trace_enable.c
+              1
+              ..\..\..\..\common\src\tx_trace_enable.c
+            
+            
+              tx_trace_event_filter.c
+              1
+              ..\..\..\..\common\src\tx_trace_event_filter.c
+            
+            
+              tx_trace_event_unfilter.c
+              1
+              ..\..\..\..\common\src\tx_trace_event_unfilter.c
+            
+            
+              tx_trace_initialize.c
+              1
+              ..\..\..\..\common\src\tx_trace_initialize.c
+            
+            
+              tx_trace_interrupt_control.c
+              1
+              ..\..\..\..\common\src\tx_trace_interrupt_control.c
+            
+            
+              tx_trace_isr_enter_insert.c
+              1
+              ..\..\..\..\common\src\tx_trace_isr_enter_insert.c
+            
+            
+              tx_trace_isr_exit_insert.c
+              1
+              ..\..\..\..\common\src\tx_trace_isr_exit_insert.c
+            
+            
+              tx_trace_object_register.c
+              1
+              ..\..\..\..\common\src\tx_trace_object_register.c
+            
+            
+              tx_trace_object_unregister.c
+              1
+              ..\..\..\..\common\src\tx_trace_object_unregister.c
+            
+            
+              tx_trace_user_event_insert.c
+              1
+              ..\..\..\..\common\src\tx_trace_user_event_insert.c
+            
+            
+              txe_block_allocate.c
+              1
+              ..\..\..\..\common\src\txe_block_allocate.c
+            
+            
+              txe_block_pool_create.c
+              1
+              ..\..\..\..\common\src\txe_block_pool_create.c
+            
+            
+              txe_block_pool_delete.c
+              1
+              ..\..\..\..\common\src\txe_block_pool_delete.c
+            
+            
+              txe_block_pool_info_get.c
+              1
+              ..\..\..\..\common\src\txe_block_pool_info_get.c
+            
+            
+              txe_block_pool_prioritize.c
+              1
+              ..\..\..\..\common\src\txe_block_pool_prioritize.c
+            
+            
+              txe_block_release.c
+              1
+              ..\..\..\..\common\src\txe_block_release.c
+            
+            
+              txe_byte_allocate.c
+              1
+              ..\..\..\..\common\src\txe_byte_allocate.c
+            
+            
+              txe_byte_pool_create.c
+              1
+              ..\..\..\..\common\src\txe_byte_pool_create.c
+            
+            
+              txe_byte_pool_delete.c
+              1
+              ..\..\..\..\common\src\txe_byte_pool_delete.c
+            
+            
+              txe_byte_pool_info_get.c
+              1
+              ..\..\..\..\common\src\txe_byte_pool_info_get.c
+            
+            
+              txe_byte_pool_prioritize.c
+              1
+              ..\..\..\..\common\src\txe_byte_pool_prioritize.c
+            
+            
+              txe_byte_release.c
+              1
+              ..\..\..\..\common\src\txe_byte_release.c
+            
+            
+              txe_event_flags_create.c
+              1
+              ..\..\..\..\common\src\txe_event_flags_create.c
+            
+            
+              txe_event_flags_delete.c
+              1
+              ..\..\..\..\common\src\txe_event_flags_delete.c
+            
+            
+              txe_event_flags_get.c
+              1
+              ..\..\..\..\common\src\txe_event_flags_get.c
+            
+            
+              txe_event_flags_info_get.c
+              1
+              ..\..\..\..\common\src\txe_event_flags_info_get.c
+            
+            
+              txe_event_flags_set.c
+              1
+              ..\..\..\..\common\src\txe_event_flags_set.c
+            
+            
+              txe_event_flags_set_notify.c
+              1
+              ..\..\..\..\common\src\txe_event_flags_set_notify.c
+            
+            
+              txe_mutex_create.c
+              1
+              ..\..\..\..\common\src\txe_mutex_create.c
+            
+            
+              txe_mutex_delete.c
+              1
+              ..\..\..\..\common\src\txe_mutex_delete.c
+            
+            
+              txe_mutex_get.c
+              1
+              ..\..\..\..\common\src\txe_mutex_get.c
+            
+            
+              txe_mutex_info_get.c
+              1
+              ..\..\..\..\common\src\txe_mutex_info_get.c
+            
+            
+              txe_mutex_prioritize.c
+              1
+              ..\..\..\..\common\src\txe_mutex_prioritize.c
+            
+            
+              txe_mutex_put.c
+              1
+              ..\..\..\..\common\src\txe_mutex_put.c
+            
+            
+              txe_queue_create.c
+              1
+              ..\..\..\..\common\src\txe_queue_create.c
+            
+            
+              txe_queue_delete.c
+              1
+              ..\..\..\..\common\src\txe_queue_delete.c
+            
+            
+              txe_queue_flush.c
+              1
+              ..\..\..\..\common\src\txe_queue_flush.c
+            
+            
+              txe_queue_front_send.c
+              1
+              ..\..\..\..\common\src\txe_queue_front_send.c
+            
+            
+              txe_queue_info_get.c
+              1
+              ..\..\..\..\common\src\txe_queue_info_get.c
+            
+            
+              txe_queue_prioritize.c
+              1
+              ..\..\..\..\common\src\txe_queue_prioritize.c
+            
+            
+              txe_queue_receive.c
+              1
+              ..\..\..\..\common\src\txe_queue_receive.c
+            
+            
+              txe_queue_send.c
+              1
+              ..\..\..\..\common\src\txe_queue_send.c
+            
+            
+              txe_queue_send_notify.c
+              1
+              ..\..\..\..\common\src\txe_queue_send_notify.c
+            
+            
+              txe_semaphore_ceiling_put.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_ceiling_put.c
+            
+            
+              txe_semaphore_create.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_create.c
+            
+            
+              txe_semaphore_delete.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_delete.c
+            
+            
+              txe_semaphore_get.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_get.c
+            
+            
+              txe_semaphore_info_get.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_info_get.c
+            
+            
+              txe_semaphore_prioritize.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_prioritize.c
+            
+            
+              txe_semaphore_put.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_put.c
+            
+            
+              txe_semaphore_put_notify.c
+              1
+              ..\..\..\..\common\src\txe_semaphore_put_notify.c
+            
+            
+              txe_thread_create.c
+              1
+              ..\..\..\..\common\src\txe_thread_create.c
+            
+            
+              txe_thread_delete.c
+              1
+              ..\..\..\..\common\src\txe_thread_delete.c
+            
+            
+              txe_thread_entry_exit_notify.c
+              1
+              ..\..\..\..\common\src\txe_thread_entry_exit_notify.c
+            
+            
+              txe_thread_info_get.c
+              1
+              ..\..\..\..\common\src\txe_thread_info_get.c
+            
+            
+              txe_thread_preemption_change.c
+              1
+              ..\..\..\..\common\src\txe_thread_preemption_change.c
+            
+            
+              txe_thread_priority_change.c
+              1
+              ..\..\..\..\common\src\txe_thread_priority_change.c
+            
+            
+              txe_thread_relinquish.c
+              1
+              ..\..\..\..\common\src\txe_thread_relinquish.c
+            
+            
+              txe_thread_reset.c
+              1
+              ..\..\..\..\common\src\txe_thread_reset.c
+            
+            
+              txe_thread_resume.c
+              1
+              ..\..\..\..\common\src\txe_thread_resume.c
+            
+            
+              txe_thread_suspend.c
+              1
+              ..\..\..\..\common\src\txe_thread_suspend.c
+            
+            
+              txe_thread_terminate.c
+              1
+              ..\..\..\..\common\src\txe_thread_terminate.c
+            
+            
+              txe_thread_time_slice_change.c
+              1
+              ..\..\..\..\common\src\txe_thread_time_slice_change.c
+            
+            
+              txe_thread_wait_abort.c
+              1
+              ..\..\..\..\common\src\txe_thread_wait_abort.c
+            
+            
+              txe_timer_activate.c
+              1
+              ..\..\..\..\common\src\txe_timer_activate.c
+            
+            
+              txe_timer_change.c
+              1
+              ..\..\..\..\common\src\txe_timer_change.c
+            
+            
+              txe_timer_create.c
+              1
+              ..\..\..\..\common\src\txe_timer_create.c
+            
+            
+              txe_timer_deactivate.c
+              1
+              ..\..\..\..\common\src\txe_timer_deactivate.c
+            
+            
+              txe_timer_delete.c
+              1
+              ..\..\..\..\common\src\txe_timer_delete.c
+            
+            
+              txe_timer_info_get.c
+              1
+              ..\..\..\..\common\src\txe_timer_info_get.c
+            
+          
+        
+      
+    
+  
+
+  
+    
+      
+        <Project Info>
+        
+        
+        
+        
+        
+        0
+        1
+      
+    
+  
+
+
diff --git a/ports/cortex_m4/keil/example_build/demo_threadx.c b/ports/cortex_m4/keil/example_build/demo_threadx.c
new file mode 100644
index 00000000..9b94bcd4
--- /dev/null
+++ b/ports/cortex_m4/keil/example_build/demo_threadx.c
@@ -0,0 +1,262 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of six
+   threads of different priorities, using a message queue, semaphore, and an event flags group.  */
+
+#include "tx_api.h"
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_QUEUE_SIZE         10
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+
+
+/* Define the thread stacks.  */
+
+UCHAR                   thread_0_stack[DEMO_STACK_SIZE];
+UCHAR                   thread_1_stack[DEMO_STACK_SIZE];
+UCHAR                   thread_2_stack[DEMO_STACK_SIZE];
+UCHAR                   thread_3_stack[DEMO_STACK_SIZE];
+UCHAR                   thread_4_stack[DEMO_STACK_SIZE];
+UCHAR                   thread_5_stack[DEMO_STACK_SIZE];
+
+
+/* Define the queue area.  */
+
+UCHAR					queue_0_area[DEMO_QUEUE_SIZE*sizeof(ULONG)];
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+
+
+volatile unsigned int bootloop;
+
+/* Define main entry point.  */
+
+
+
+int main()
+{
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            thread_0_stack, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            thread_1_stack, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            thread_2_stack, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            thread_3_stack, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            thread_4_stack, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            thread_5_stack, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, queue_0_area, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
diff --git a/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s
new file mode 100644
index 00000000..de11bafb
--- /dev/null
+++ b/ports/cortex_m4/keil/example_build/tx_initialize_low_level.s
@@ -0,0 +1,271 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Initialize                                                          */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_initialize.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IMPORT  _tx_thread_system_stack_ptr
+    IMPORT  _tx_initialize_unused_memory
+    IMPORT  _tx_thread_context_save
+    IMPORT  _tx_thread_context_restore
+    IMPORT  _tx_timer_interrupt
+    IMPORT  __main
+    IMPORT  |Image$$RO$$Limit|
+    IMPORT  |Image$$RW$$Base|
+    IMPORT  |Image$$ZI$$Base|
+    IMPORT  |Image$$ZI$$Limit|
+    IMPORT  __tx_PendSVHandler
+;
+;
+SYSTEM_CLOCK        EQU     6000000
+SYSTICK_CYCLES      EQU     ((SYSTEM_CLOCK / 100) -1)
+;
+;
+;/* Setup the stack and heap areas.  */
+;
+STACK_SIZE          EQU     0x00000400
+HEAP_SIZE           EQU     0x00000000
+
+    AREA    STACK, NOINIT, READWRITE, ALIGN=3
+StackMem
+    SPACE   STACK_SIZE
+__initial_sp
+
+
+    AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+HeapMem
+    SPACE   HEAP_SIZE
+__heap_limit
+
+
+    AREA    RESET, CODE, READONLY
+;
+    EXPORT  __tx_vectors
+__tx_vectors
+    DCD     __initial_sp                            ; Reset and system stack ptr
+    DCD     Reset_Handler                           ; Reset goes to startup function
+    DCD     __tx_NMIHandler                         ; NMI
+    DCD     __tx_BadHandler                         ; HardFault
+    DCD     0                                       ; MemManage
+    DCD     0                                       ; BusFault
+    DCD     0                                       ; UsageFault
+    DCD     0                                       ; 7
+    DCD     0                                       ; 8
+    DCD     0                                       ; 9
+    DCD     0                                       ; 10
+    DCD     __tx_SVCallHandler                      ; SVCall
+    DCD     __tx_DBGHandler                         ; Monitor
+    DCD     0                                       ; 13
+    DCD     __tx_PendSVHandler                      ; PendSV
+    DCD     __tx_SysTickHandler                     ; SysTick
+    DCD     __tx_IntHandler                         ; Int 0
+    DCD     __tx_IntHandler                         ; Int 1
+    DCD     __tx_IntHandler                         ; Int 2
+    DCD     __tx_IntHandler                         ; Int 3
+        
+;
+;
+    AREA ||.text||, CODE, READONLY
+    EXPORT  Reset_Handler
+Reset_Handler
+    CPSID   i
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    LDR     r0, =0xE000ED88                         ; Pickup address of CPACR
+	LDR     r1, [r0]                                ; Pickup CPACR
+	MOV32   r2, 0x00F00000                          ; Build enable value
+	ORR     r1, r1, r2                              ; Or in enable value
+	STR     r1, [r0]                                ; Setup CPACR
+    ENDIF
+    LDR     r0, =__main
+    BX      r0
+
+
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_initialize_low_level                          Cortex-M4/RVDS    */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for any low-level processor            */
+;/*    initialization, including setting up interrupt vectors, setting     */
+;/*    up a periodic timer interrupt source, saving the system stack       */
+;/*    pointer for use in ISR processing later, and finding the first      */
+;/*    available RAM memory address for tx_application_define.             */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_initialize_low_level(VOID)
+;{
+    EXPORT  _tx_initialize_low_level
+_tx_initialize_low_level
+;
+;    /* Disable interrupts during ThreadX initialization.  */
+;
+    CPSID   i
+;
+;    /* Set base of available memory to end of non-initialised RAM area.  */
+;     
+    LDR     r0, =_tx_initialize_unused_memory       ; Build address of unused memory pointer
+    LDR     r1, =|Image$$ZI$$Limit|                 ; Build first free address
+    ADD     r1, r1, #4                              ; 
+    STR     r1, [r0]                                ; Setup first unused memory pointer
+;
+;    /* Setup Vector Table Offset Register.  */
+;    
+    MOV     r0, #0xE000E000                         ; Build address of NVIC registers
+    LDR     r1, =__tx_vectors                       ; Pickup address of vector table
+    STR     r1, [r0, #0xD08]                        ; Set vector table address   
+;
+;    /* Enable the cycle count register.  */
+;
+;    LDR     r0, =0xE0001000                         ; Build address of DWT register
+;    LDR     r1, [r0]                                ; Pickup the current value
+;    ORR     r1, r1, #1                              ; Set the CYCCNTENA bit
+;    STR     r1, [r0]                                ; Enable the cycle count register 
+;
+;    /* Set system stack pointer from vector value.  */
+;
+    LDR     r0, =_tx_thread_system_stack_ptr        ; Build address of system stack pointer
+    LDR     r1, =__tx_vectors                       ; Pickup address of vector table
+    LDR     r1, [r1]                                ; Pickup reset stack pointer
+    STR     r1, [r0]                                ; Save system stack pointer
+;
+;    /* Configure SysTick.  */
+;
+    MOV     r0, #0xE000E000                         ; Build address of NVIC registers
+    LDR     r1, =SYSTICK_CYCLES
+    STR     r1, [r0, #0x14]                         ; Setup SysTick Reload Value
+    MOV     r1, #0x7                                ; Build SysTick Control Enable Value
+    STR     r1, [r0, #0x10]                         ; Setup SysTick Control
+;
+;    /* Configure handler priorities.  */
+;
+    LDR     r1, =0x00000000                         ; Rsrv, UsgF, BusF, MemM
+    STR     r1, [r0, #0xD18]                        ; Setup System Handlers 4-7 Priority Registers
+
+    LDR     r1, =0xFF000000                         ; SVCl, Rsrv, Rsrv, Rsrv
+    STR     r1, [r0, #0xD1C]                        ; Setup System Handlers 8-11 Priority Registers
+                                                    ; Note: SVC must be lowest priority, which is 0xFF
+
+    LDR     r1, =0x40FF0000                         ; SysT, PnSV, Rsrv, DbgM
+    STR     r1, [r0, #0xD20]                        ; Setup System Handlers 12-15 Priority Registers
+                                                    ; Note: PnSV must be lowest priority, which is 0xFF
+;
+;    /* Return to caller.  */
+;    
+    BX      lr 
+;}
+;
+;       
+;/* Define initial heap/stack routine for the ARM RVCT startup code.
+;   This routine will set the initial stack and heap locations */
+;
+    EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+    LDR     r0, =HeapMem
+    LDR     r1, =(StackMem + STACK_SIZE)
+    LDR     r2, =(HeapMem + HEAP_SIZE)
+    LDR     r3, =StackMem
+    BX      lr
+;
+;
+;/* Define shells for each of the unused vectors.  */
+;
+    EXPORT  __tx_BadHandler
+__tx_BadHandler 
+    B       __tx_BadHandler
+
+    EXPORT  __tx_SVCallHandler
+__tx_SVCallHandler
+    B       __tx_SVCallHandler 
+
+    EXPORT  __tx_IntHandler
+__tx_IntHandler
+; VOID InterruptHandler (VOID)
+; {
+    PUSH    {r0, lr}
+        
+;    /* Do interrupt handler work here */
+;    /* .... */
+
+    POP     {r0, lr}
+    BX      LR
+; }
+
+        EXPORT  __tx_SysTickHandler
+__tx_SysTickHandler
+; VOID TimerInterruptHandler (VOID)
+; {
+;
+    PUSH    {r0, lr}
+    BL      _tx_timer_interrupt
+    POP     {r0, lr}
+    BX      LR
+; }
+
+    EXPORT  __tx_NMIHandler 
+__tx_NMIHandler
+    B       __tx_NMIHandler
+
+    EXPORT  __tx_DBGHandler
+__tx_DBGHandler
+    B       __tx_DBGHandler
+
+    ALIGN
+    LTORG
+    END
diff --git a/ports/cortex_m4/keil/inc/tx_port.h b/ports/cortex_m4/keil/inc/tx_port.h
new file mode 100644
index 00000000..7474585b
--- /dev/null
+++ b/ports/cortex_m4/keil/inc/tx_port.h
@@ -0,0 +1,471 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */
+/*                                                                        */
+/*    tx_port.h                                         Cortex-M4/Keil    */
+/*                                                           6.0.1        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file contains data type definitions that make the ThreadX      */
+/*    real-time kernel function identically on a variety of different     */
+/*    processor architectures.  For example, the size or number of bits   */
+/*    in an "int" data type vary between microprocessor architectures and */
+/*    even C compilers for the same microprocessor.  ThreadX does not     */
+/*    directly use native C data types.  Instead, ThreadX creates its     */
+/*    own special types that can be mapped to actual data types by this   */
+/*    file to guarantee consistency in the interface and functionality.   */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include 
+#include 
+
+
+/* Define ThreadX basic types for this port.  */
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */
+#endif
+
+
+/* Define various constants for the ThreadX Cortex-M3 port.  */
+
+#define TX_INT_DISABLE                          1           /* Disable interrupts               */
+#define TX_INT_ENABLE                           0           /* Enable interrupts                */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_MISRA_ENABLE
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0xE0001004)  
+#endif
+#else
+ULONG   _tx_misra_time_stamp_get(VOID);
+#define TX_TRACE_TIME_SOURCE                    _tx_misra_time_stamp_get()
+#endif
+
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          (0)
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#ifdef TX_MISRA_ENABLE
+#define TX_DISABLE_INLINE
+#else
+#define TX_INLINE_INITIALIZATION
+#endif
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifndef TX_MISRA_ENABLE
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#define TX_THREAD_EXTENSION_2                   
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+
+
+#ifndef TX_MISRA_ENABLE
+
+register unsigned int _ipsr __asm("ipsr");
+
+#endif
+
+
+#ifdef __TARGET_FPU_VFP
+
+#ifdef TX_MISRA_ENABLE
+
+ULONG  _tx_misra_control_get(void);
+void   _tx_misra_control_set(ULONG value);
+ULONG  _tx_misra_fpccr_get(void);
+void   _tx_misra_vfp_touch(void);
+
+#else
+
+#ifdef TX_SOURCE_CODE
+
+register ULONG  _control __asm("control");
+
+#endif
+#endif
+
+/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA
+   in order to ensure no lazy stacking will occur. */
+
+#ifndef TX_MISRA_ENABLE
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)                   {                                                                                             \
+                                                                    ULONG  _tx_vfp_state;                                                                         \
+                                                                        _tx_vfp_state =  _control;                                                                \
+                                                                        _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                          \
+                                                                        _control =       _tx_vfp_state;                                                           \
+                                                                    }
+#else
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)                   {                                                                                             \
+                                                                    ULONG  _tx_vfp_state;                                                                         \
+                                                                        _tx_vfp_state =  _tx_misra_control_get();                                                 \
+                                                                        _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                          \
+                                                                        _tx_misra_control_set(_tx_vfp_state);                                                     \
+                                                                    }
+                                                                    
+#endif
+
+/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR.
+   If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating
+   this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush 
+   the lazy FPU save, then restore the CONTROL.FPCA state. */
+
+#ifndef TX_MISRA_ENABLE
+
+void _tx_vfp_access(void);
+
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  {                                                                                             \
+                                                                    ULONG  _tx_system_state;                                                                      \
+                                                                        _tx_system_state =  TX_THREAD_GET_SYSTEM_STATE();                                         \
+                                                                        if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr))        \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_vfp_state;                                                                     \
+                                                                            _tx_vfp_state =  _control;                                                            \
+                                                                            _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                      \
+                                                                            _control =       _tx_vfp_state;                                                       \
+                                                                        }                                                                                         \
+                                                                        else                                                                                      \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_fpccr;                                                                         \
+                                                                            _tx_fpccr =  *((ULONG *) 0xE000EF34);                                                 \
+                                                                            _tx_fpccr =  _tx_fpccr & ((ULONG) 0x01);                                              \
+                                                                            if (_tx_fpccr == ((ULONG) 0x01))                                                      \
+                                                                            {                                                                                     \
+                                                                            ULONG _tx_vfp_state;                                                                  \
+                                                                                _tx_vfp_state =  _control;                                                        \
+                                                                                _tx_vfp_state =  _tx_vfp_state & ((ULONG) 0x4);                                   \
+                                                                                _tx_vfp_access();                                                                 \
+                                                                                if (_tx_vfp_state == ((ULONG) 0))                                                 \
+                                                                                {                                                                                 \
+                                                                                    _tx_vfp_state =  _control;                                                    \
+                                                                                    _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                              \
+                                                                                    _control =       _tx_vfp_state;                                               \
+                                                                                }                                                                                 \
+                                                                            }                                                                                     \
+                                                                        }                                                                                         \
+                                                                    }
+#else
+
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  {                                                                                             \
+                                                                    ULONG  _tx_system_state;                                                                      \
+                                                                        _tx_system_state =  TX_THREAD_GET_SYSTEM_STATE();                                         \
+                                                                        if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr))        \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_vfp_state;                                                                     \
+                                                                            _tx_vfp_state =  _tx_misra_control_get();                                             \
+                                                                            _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                      \
+                                                                            _tx_misra_control_set(_tx_vfp_state);                                                 \
+                                                                        }                                                                                         \
+                                                                        else                                                                                      \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_fpccr;                                                                         \
+                                                                            _tx_fpccr =  _tx_misra_fpccr_get();                                                   \
+                                                                            _tx_fpccr =  _tx_fpccr & ((ULONG) 0x01);                                              \
+                                                                            if (_tx_fpccr == ((ULONG) 0x01))                                                      \
+                                                                            {                                                                                     \
+                                                                            ULONG _tx_vfp_state;                                                                  \
+                                                                                _tx_vfp_state = _tx_misra_control_get();                                          \
+                                                                                _tx_vfp_state =  _tx_vfp_state & ((ULONG) 0x4);                                   \
+                                                                                _tx_misra_vfp_touch();                                                            \
+                                                                                if (_tx_vfp_state == ((ULONG) 0))                                                 \
+                                                                                {                                                                                 \
+                                                                                    _tx_vfp_state =  _tx_misra_control_get();                                     \
+                                                                                    _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                              \
+                                                                                    _tx_misra_control_set(_tx_vfp_state);                                         \
+                                                                                }                                                                                 \
+                                                                            }                                                                                     \
+                                                                        }                                                                                         \
+                                                                    }
+#endif
+
+#else
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  
+
+#endif
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Define the get system state macro.   */
+   
+#ifndef TX_THREAD_GET_SYSTEM_STATE
+#ifndef TX_MISRA_ENABLE
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | _ipsr)
+#else
+ULONG   _tx_misra_ipsr_get(VOID);
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | _tx_misra_ipsr_get())
+#endif
+#endif
+
+
+/* Define the check for whether or not to call the _tx_thread_system_return function.  A non-zero value
+   indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h
+   for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always
+   zero after initialization for Cortex-M ports. */
+
+#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
+#define TX_THREAD_SYSTEM_RETURN_CHECK(c)    (c) = ((ULONG) _tx_thread_preempt_disable); 
+#endif
+
+
+/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to 
+   prevent early scheduling on Cortex-M parts.  */
+   
+#define TX_PORT_SPECIFIC_POST_INITIALIZATION    _tx_thread_preempt_disable++;
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef TX_DISABLE_INLINE
+   
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       (b) =  (UINT) __clz(__rbit((m)));
+
+#endif
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifdef TX_DISABLE_INLINE
+
+UINT                                            _tx_thread_interrupt_disable(VOID);
+VOID                                            _tx_thread_interrupt_restore(UINT previous_posture);
+
+#define TX_INTERRUPT_SAVE_AREA                  register UINT interrupt_save;
+
+#define TX_DISABLE                              interrupt_save = _tx_thread_interrupt_disable();
+
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+
+#else
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int  was_masked;
+#define TX_DISABLE                              was_masked = __disable_irq();
+#define TX_RESTORE                              if (was_masked == 0) __enable_irq();
+
+#define _tx_thread_system_return                _tx_thread_system_return_inline
+
+
+static void _tx_thread_system_return_inline(void)
+{
+unsigned int          was_masked;
+
+
+    /* Set PendSV to invoke ThreadX scheduler.  */
+    *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    if (_ipsr == 0)
+    {
+        was_masked = __disable_irq();
+        __enable_irq();
+        if (was_masked != 0)
+            __disable_irq();
+    }
+}
+#endif
+
+
+/* Define FPU extension for the Cortex-M4.  Each is assumed to be called in the context of the executing
+   thread. These are no longer needed, but are preserved for backward compatibility only.  */
+
+void    tx_thread_fpu_enable(void);
+void    tx_thread_fpu_disable(void);
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Cortex-M4/Keil Version 6.0 *";
+#else
+#ifdef TX_MISRA_ENABLE
+extern  CHAR                    _tx_version_id[100];
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+#endif
+
+
+#endif
+
+
+
+
diff --git a/ports/cortex_m4/keil/readme_threadx.txt b/ports/cortex_m4/keil/readme_threadx.txt
new file mode 100644
index 00000000..188eb21d
--- /dev/null
+++ b/ports/cortex_m4/keil/readme_threadx.txt
@@ -0,0 +1,208 @@
+                     Microsoft's Azure RTOS ThreadX for Cortex-M4 
+
+                               Thumb & 32-bit Mode
+
+                    Using the Keil Microcontroller Development Kit
+
+1.  Building the ThreadX run-time Library
+
+Building the ThreadX library is easy, simply load the project file 
+ThreadX_Library.Uv2, which is located inside the "example_build" directory. 
+
+Once the ThreadX library files are displayed in the project window,
+select the "Build Target" operation and observe the compilation and assembly
+of the ThreadX library. This project build produces the ThreadX library 
+file ThreadX_Library.lib.
+
+
+2.  Demonstration System
+
+The ThreadX demonstration is designed to execute under the Keil debugger or
+Cortex-M4 hardware. This demonstration is slightly smaller than typical ThreadX 
+demonstrations, and thus requires less than 7KB of Flash and less than 4KB of RAM.
+
+Building the demonstration is easy; simply open the ThreadX demonstration 
+project file ThreadX_Demo.Uv2, which is located inside the "example_build" 
+directory. 
+
+Once open, select the "Build Target" operation and observe the compilation of 
+sample_threadx.c (which is the demonstration application) and linking with 
+ThreadX_Library.lib. The resulting file sample_threadx.axf is a binary file that 
+can be downloaded and executed on Cortex-M4 hardware. 
+
+
+3.  System Initialization
+
+The entry point in ThreadX for the Cortex-M4 using Keil tools is at label 
+__main. This is defined within the Keil compiler's startup code. In 
+addition, this is where all static and global pre-set C variable 
+initialization processing takes place.
+
+The ThreadX tx_initialize_low_level.s file is responsible for setting up 
+various system data structures, the vector area, and a periodic timer interrupt 
+source. 
+
+In addition, _tx_initialize_low_level determines the first available 
+address for use by the application, which is supplied as the sole input 
+parameter to your application definition function, tx_application_define.
+
+
+4.  Register Usage and Stack Frames
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have the same stack frame in the Cortex-M4 version of
+ThreadX. The top of the suspended thread's stack is pointed to by 
+tx_thread_stack_ptr in the associated thread control block TX_THREAD.
+
+Non-FPU Stack Frame:
+
+  Stack Offset     Stack Contents 
+
+     0x00               r4
+     0x04               r5
+     0x08               r6
+     0x0C               r7
+     0x10               r8
+     0x14               r9
+     0x18               r10
+     0x1C               r11
+     0x20               r0          (Hardware stack starts here!!)
+     0x24               r1
+     0x28               r2
+     0x2C               r3
+     0x30               r12
+     0x34               lr
+     0x38               pc
+     0x3C               xPSR
+
+FPU Stack Frame (only interrupted thread with FPU enabled):
+
+  Stack Offset     Stack Contents 
+
+     0x00               s0
+     0x04               s1
+     0x08               s2
+     0x0C               s3
+     0x10               s4
+     0x14               s5
+     0x18               s6
+     0x1C               s7
+     0x20               s8
+     0x24               s9
+     0x28               s10
+     0x2C               s11
+     0x30               s12
+     0x34               s13
+     0x38               s14
+     0x3C               s15
+     0x40               s16
+     0x44               s17
+     0x48               s18
+     0x4C               s19
+     0x50               s20
+     0x54               s21
+     0x58               s22
+     0x5C               s23
+     0x60               s24
+     0x64               s25
+     0x68               s26
+     0x6C               s27
+     0x70               s28
+     0x74               s29
+     0x78               s30
+     0x7C               s31
+     0x80               fpscr
+     0x84               r4          
+     0x88               r5          
+     0x8C               r6          
+     0x90               r7          
+     0x94               r8          
+     0x98               r9          
+     0x9C               r10 (sl)    
+     0xA0               r11         
+     0xA4               r0          (Hardware stack starts here!!)
+     0xA8               r1          
+     0xAC               r2          
+     0xB0               r3          
+     0xB4               r12         
+     0xB8               lr          
+     0xBC               pc          
+     0xC0               xPSR        
+
+
+5.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+breakpoints inside of ThreadX itself. Of course, this costs some 
+performance. To make it run faster, you can change the ThreadX_Library.Uv2 
+project to debugging and enable all compiler optimizations. 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+6.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-M4
+targets. There are a certain set of requirements that are defined in the 
+following sub-sections:
+
+
+6.1  Vector Area
+
+The Cortex-M4 vectors start at the label __tx_vectors. The application may modify
+the vector area according to its needs.
+
+
+6.2 Managed Interrupts
+
+ISRs for Cortex-M can be written completely in C (or assembly language) without any
+calls to _tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed
+access to the ThreadX API that is available to ISRs.
+
+ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
+
+void    your_C_isr(void)
+{
+
+    /* ISR processing goes here, including any needed function calls.  */
+}
+
+ISRs written in assembly language will take the form:
+
+    EXPORT  your_assembly_isr
+your_assembly_isr
+
+    PUSH    {r0, lr}
+
+    ; ISR processing goes here, including any needed function calls.
+
+    POP     {r0, lr}
+    BX      lr
+
+
+7. FPU Support
+
+ThreadX for Cortex-M4 supports automatic ("lazy") VFP support, which means that applications threads 
+can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread 
+context - no additional setup by the application.
+
+
+
+8.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX 6.0.1 version for Cortex-M4 using Keil tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_m4/keil/src/tx_thread_context_restore.s b/ports/cortex_m4/keil/src/tx_thread_context_restore.s
new file mode 100644
index 00000000..7c54ab4e
--- /dev/null
+++ b/ports/cortex_m4/keil/src/tx_thread_context_restore.s
@@ -0,0 +1,99 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT  _tx_execution_isr_exit
+    ENDIF
+;
+;
+    AREA    ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_context_restore                        Cortex-M4/AC5    */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function restores the interrupt context if it is processing a  */
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */
+;/*    if no thread was running, the function returns to the scheduler.    */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_schedule                   Thread scheduling routine     */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ISRs                                  Interrupt Service Routines    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_restore(VOID)
+;{
+    EXPORT  _tx_thread_context_restore
+_tx_thread_context_restore
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR exit function to indicate an ISR is complete.  */
+;
+    PUSH    {r0,lr}                                 ; Save ISR lr
+    BL      _tx_execution_isr_exit                  ; Call the ISR exit function
+    POP     {r0,lr}                                 ; Restore ISR lr
+    ENDIF
+;
+    POP     {lr}
+    BX      lr
+;}
+    ALIGN
+    LTORG
+    END
diff --git a/ports/cortex_m4/keil/src/tx_thread_context_save.s b/ports/cortex_m4/keil/src/tx_thread_context_save.s
new file mode 100644
index 00000000..268b05a9
--- /dev/null
+++ b/ports/cortex_m4/keil/src/tx_thread_context_save.s
@@ -0,0 +1,99 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT  _tx_execution_isr_enter
+    ENDIF
+;
+;
+    AREA    ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_context_save                           Cortex-M4/AC5    */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function saves the context of an executing thread in the       */
+;/*    beginning of interrupt processing.  The function also ensures that  */
+;/*    the system stack is used upon return to the calling ISR.            */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ISRs                                                                */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_save(VOID)
+;{
+    EXPORT  _tx_thread_context_save
+_tx_thread_context_save
+   IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {r0, lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter                 ; Call the ISR enter function
+    POP     {r0, lr}                                ; Recover ISR lr
+    ENDIF
+;
+;    /* Return to interrupt processing.  */
+;     
+    BX      lr                                      ; Return to interrupt processing caller
+;}
+    ALIGN
+    LTORG
+    END
diff --git a/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s b/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s
new file mode 100644
index 00000000..a5889c6e
--- /dev/null
+++ b/ports/cortex_m4/keil/src/tx_thread_interrupt_control.s
@@ -0,0 +1,85 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_control                      Cortex-M4/AC5    */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for changing the interrupt lockout     */
+;/*    posture of the system.                                              */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    new_posture                           New interrupt lockout posture */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    old_posture                           Old interrupt lockout posture */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_control(UINT new_posture)
+;{
+    EXPORT  _tx_thread_interrupt_control
+_tx_thread_interrupt_control
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    MRS     r1, PRIMASK
+    MSR     PRIMASK, r0
+    MOV     r0, r1
+    BX      lr
+;
+;}
+    END
+    
diff --git a/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s b/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s
new file mode 100644
index 00000000..3cf2a68c
--- /dev/null
+++ b/ports/cortex_m4/keil/src/tx_thread_interrupt_disable.s
@@ -0,0 +1,83 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_disable                      Cortex-M4/AC5    */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for disabling interrupts and returning */
+;/*    the previous interrupt lockout posture.                             */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    old_posture                           Old interrupt lockout posture */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_disable(UINT new_posture)
+;{
+    EXPORT  _tx_thread_interrupt_disable
+_tx_thread_interrupt_disable
+;
+;    /* Return current interrupt lockout posture.  */
+;
+    MRS     r0, PRIMASK
+    CPSID   i
+    BX      lr
+;
+;}
+    END
diff --git a/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s b/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s
new file mode 100644
index 00000000..20447958
--- /dev/null
+++ b/ports/cortex_m4/keil/src/tx_thread_interrupt_restore.s
@@ -0,0 +1,82 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_restore                      Cortex-M4/AC5    */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for restoring the previous             */
+;/*    interrupt lockout posture.                                          */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    previous_posture                      Previous interrupt posture    */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_interrupt_restore(UINT new_posture)
+;{
+    EXPORT  _tx_thread_interrupt_restore
+_tx_thread_interrupt_restore
+;
+;    /* Restore previous interrupt lockout posture.  */
+;
+    MSR     PRIMASK, r0
+    BX      lr
+;
+;}
+    END
diff --git a/ports/cortex_m4/keil/src/tx_thread_schedule.s b/ports/cortex_m4/keil/src/tx_thread_schedule.s
new file mode 100644
index 00000000..fd29b203
--- /dev/null
+++ b/ports/cortex_m4/keil/src/tx_thread_schedule.s
@@ -0,0 +1,298 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;   
+    IMPORT  _tx_thread_current_ptr
+    IMPORT  _tx_thread_execute_ptr
+    IMPORT  _tx_timer_time_slice
+    IMPORT  _tx_thread_system_stack_ptr
+    IMPORT  _tx_thread_preempt_disable
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT  _tx_execution_thread_enter
+    IMPORT  _tx_execution_thread_exit        
+    ENDIF
+;
+;
+    AREA    ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_schedule                               Cortex-M4/AC5    */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function waits for a thread control block pointer to appear in */
+;/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
+;/*    in the variable, the corresponding thread is resumed.               */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter          ThreadX entry function         */
+;/*    _tx_thread_system_return             Return to system from thread   */
+;/*    _tx_thread_context_restore           Restore thread's context       */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_schedule(VOID)
+;{
+        EXPORT  _tx_thread_schedule
+_tx_thread_schedule
+;
+;    /* This function should only ever be called on Cortex-M
+;       from the first schedule request. Subsequent scheduling occurs
+;       from the PendSV handling routines below. */
+;
+;    /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets.  */
+;     
+    MOV     r0, #0                                  ; Build value for TX_FALSE
+    LDR     r2, =_tx_thread_preempt_disable         ; Build address of preempt disable flag
+    STR     r0, [r2, #0]                            ; Clear preempt disable flag
+;
+;    /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked.  */
+;
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    MRS     r0, CONTROL                             ; Pickup current CONTROL register
+    BIC     r0, r0, #4                              ; Clear the FPCA bit 
+    MSR     CONTROL, r0                             ; Setup new CONTROL register
+    ENDIF
+;
+;    /* Enable the interrupts */
+;
+    CPSIE   i
+;       
+;    /* Enter the scheduler for the first time.  */
+;
+    MOV     r0, #0x10000000                         ; Load PENDSVSET bit
+    MOV     r1, #0xE000E000                         ; Load NVIC base
+    STR     r0, [r1, #0xD04]                        ; Set PENDSVBIT in ICSR
+    DSB                                             ; Complete all memory accesses
+    ISB                                             ; Flush pipeline
+;
+;    /* Wait here for the PendSV to take place.  */
+;     
+__tx_wait_here
+    B       __tx_wait_here                          ; Wait for the PendSV to happen
+;}
+;
+;    /* Generic context switching PendSV handler.  */
+;     
+        EXPORT  __tx_PendSVHandler
+        EXPORT  PendSV_Handler
+__tx_PendSVHandler  
+PendSV_Handler
+;
+;    /* Get current thread value and new thread pointer.  */
+;       
+__tx_ts_handler 
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread exit function to indicate the thread is no longer executing.  */
+;
+    CPSID   i                                       ; Disable interrupts
+    PUSH    {r0, lr}                                ; Save LR (and r0 just for alignment)
+    BL      _tx_execution_thread_exit               ; Call the thread exit function
+    POP     {r0, lr}                                ; Recover LR
+    CPSIE   i                                       ; Enable interrupts
+    ENDIF
+    MOV32   r0, _tx_thread_current_ptr              ; Build current thread pointer address
+    MOV32   r2, _tx_thread_execute_ptr              ; Build execute thread pointer address
+    MOV     r3, #0                                  ; Build NULL value
+    LDR     r1, [r0]                                ; Pickup current thread pointer
+;
+;    /* Determine if there is a current thread to finish preserving.  */
+;       
+    CBZ     r1, __tx_ts_new                         ; If NULL, skip preservation
+;
+;    /* Recover PSP and preserve current thread context.  */
+;
+    STR     r3, [r0]                                ; Set _tx_thread_current_ptr to NULL
+    MRS     r12, PSP                                ; Pickup PSP pointer (thread's stack pointer)
+    STMDB   r12!, {r4-r11}                          ; Save its remaining registers
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    TST     LR, #0x10                               ; Determine if the VFP extended frame is present
+    BNE     _skip_vfp_save
+    VSTMDB  r12!,{s16-s31}                          ; Yes, save additional VFP registers
+_skip_vfp_save
+    ENDIF
+    MOV32   r4, _tx_timer_time_slice                ; Build address of time-slice variable
+    STMDB   r12!, {LR}                              ; Save LR on the stack
+;
+;    /* Determine if time-slice is active. If it isn't, skip time handling processing.  */
+;
+    LDR     r5, [r4]                                ; Pickup current time-slice
+    STR     r12, [r1, #8]                           ; Save the thread stack pointer
+    CBZ     r5, __tx_ts_new                         ; If not active, skip processing
+;
+;    /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable.  */
+;
+    STR     r5, [r1, #24]                           ; Save current time-slice
+;
+;    /* Clear the global time-slice.  */
+;
+    STR     r3, [r4]                                ; Clear time-slice
+;       
+;    /* Executing thread is now completely preserved!!!  */
+;
+__tx_ts_new 
+;
+;    /* Now we are looking for a new thread to execute!  */
+;
+    CPSID   i                                       ; Disable interrupts
+    LDR     r1, [r2]                                ; Is there another thread ready to execute?
+    CBZ     r1, __tx_ts_wait                        ; No, skip to the wait processing
+;
+;    /* Yes, another thread is ready for else, make the current thread the new thread.  */
+;
+    STR     r1, [r0]                                ; Setup the current thread pointer to the new thread
+    CPSIE   i                                       ; Enable interrupts
+;
+;    /* Increment the thread run count.  */
+;
+__tx_ts_restore 
+    LDR     r7, [r1, #4]                            ; Pickup the current thread run count
+    MOV32   r4, _tx_timer_time_slice                ; Build address of time-slice variable
+    LDR     r5, [r1, #24]                           ; Pickup thread's current time-slice
+    ADD     r7, r7, #1                              ; Increment the thread run count
+    STR     r7, [r1, #4]                            ; Store the new run count
+;
+;    /* Setup global time-slice with thread's current time-slice.  */
+;
+    STR     r5, [r4]                                ; Setup global time-slice
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread entry function to indicate the thread is executing.  */
+;
+    PUSH    {r0, r1}                                ; Save r0/r1
+    BL      _tx_execution_thread_enter              ; Call the thread execution enter function
+    POP     {r0, r1}                                ; Recover r3
+    ENDIF
+;
+;    /* Restore the thread context and PSP.  */
+;
+    LDR     r12, [r1, #8]                           ; Pickup thread's stack pointer
+    LDMIA   r12!, {LR}                              ; Pickup LR
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    TST     LR, #0x10                               ; Determine if the VFP extended frame is present
+    BNE     _skip_vfp_restore                       ; If not, skip VFP restore 
+    VLDMIA  r12!, {s16-s31}                         ; Yes, restore additional VFP registers
+_skip_vfp_restore
+    ENDIF
+    LDMIA   r12!, {r4-r11}                          ; Recover thread's registers
+    MSR     PSP, r12                                ; Setup the thread's stack pointer
+;
+;    /* Return to thread.  */
+;       
+        BX      lr                                  ; Return to thread!
+;
+;    /* The following is the idle wait processing... in this case, no threads are ready for execution and the
+;       system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts 
+;       are disabled to allow use of WFI for waiting for a thread to arrive.  */
+;
+__tx_ts_wait    
+    CPSID   i                                       ; Disable interrupts
+    LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
+    STR     r1, [r0]                                ; Store it in the current pointer
+    CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+    IF :DEF:TX_ENABLE_WFI
+    DSB                                             ; Ensure no outstanding memory transactions
+    WFI                                             ; Wait for interrupt
+    ISB                                             ; Ensure pipeline is flushed
+    ENDIF
+    CPSIE   i                                       ; Enable interrupts
+    B       __tx_ts_wait                            ; Loop to continue waiting
+;
+;    /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are 
+;       already in the handler!  */
+;
+__tx_ts_ready   
+    MOV     r7, #0x08000000                         ; Build clear PendSV value
+    MOV     r8, #0xE000E000                         ; Build base NVIC address
+    STR     r7, [r8, #0xD04]                        ; Clear any PendSV 
+;
+;    /* Re-enable interrupts and restore new thread.  */
+;       
+    CPSIE   i                                       ; Enable interrupts
+    B       __tx_ts_restore                         ; Restore the thread
+
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    EXPORT  tx_thread_fpu_enable
+tx_thread_fpu_enable
+;
+;    /* Automatic VPF logic is supported, this function is present only for 
+;       backward compatibility purposes and therefore simply returns.  */
+;
+    BX      LR                                      ; Return to caller
+
+    EXPORT  tx_thread_fpu_disable
+tx_thread_fpu_disable
+;
+;    /* Automatic VPF logic is supported, this function is present only for 
+;       backward compatibility purposes and therefore simply returns.  */
+;
+    BX      LR                                      ; Return to caller
+
+    EXPORT  _tx_vfp_access
+_tx_vfp_access
+    VMOV.F32 s0, s0                                 ; Simply access the VFP
+    BX       lr                                     ; Return to caller
+
+
+    ENDIF
+
+    ALIGN
+    LTORG
+    END
+    
diff --git a/ports/cortex_m4/keil/src/tx_thread_stack_build.s b/ports/cortex_m4/keil/src/tx_thread_stack_build.s
new file mode 100644
index 00000000..aa2f9d4d
--- /dev/null
+++ b/ports/cortex_m4/keil/src/tx_thread_stack_build.s
@@ -0,0 +1,143 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_stack_build                            Cortex-M4/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function builds a stack frame on the supplied thread's stack.  */
+;/*    The stack frame results in a fake interrupt return to the supplied  */
+;/*    function pointer.                                                   */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    thread_ptr                            Pointer to thread control blk */
+;/*    function_ptr                          Pointer to return function    */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_thread_create                     Create thread service         */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+;{
+    EXPORT  _tx_thread_stack_build
+_tx_thread_stack_build
+;
+;       
+;    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+;       on the Cortex-M4 should look like the following after it is built:
+;       
+;       Stack Top:      
+;                       LR          Interrupted LR (LR at time of PENDSV)
+;                       r4          Initial value for r4
+;                       r5          Initial value for r5
+;                       r6          Initial value for r6
+;                       r7          Initial value for r7
+;                       r8          Initial value for r8
+;                       r9          Initial value for r9
+;                       r10         Initial value for r10
+;                       r11         Initial value for r11
+;                       r0          Initial value for r0    (Hardware stack starts here!!)
+;                       r1          Initial value for r1
+;                       r2          Initial value for r2
+;                       r3          Initial value for r3
+;                       r12         Initial value for r12
+;                       lr          Initial value for lr
+;                       pc          Initial value for pc
+;                       xPSR        Initial value for xPSR
+;
+;    Stack Bottom: (higher memory address)  */
+;
+    LDR     r2, [r0, #16]                           ; Pickup end of stack area
+    BIC     r2, r2, #0x7                            ; Align frame for 8-byte alignment
+    SUB     r2, r2, #68                             ; Subtract frame size
+    LDR     r3, =0xFFFFFFFD                         ; Build initial LR value
+    STR     r3, [r2, #0]                            ; Save on the stack
+;
+;    /* Actually build the stack frame.  */
+;
+    MOV     r3, #0                                  ; Build initial register value
+    STR     r3, [r2, #4]                            ; Store initial r4
+    STR     r3, [r2, #8]                            ; Store initial r5
+    STR     r3, [r2, #12]                           ; Store initial r6
+    STR     r3, [r2, #16]                           ; Store initial r7
+    STR     r3, [r2, #20]                           ; Store initial r8
+    STR     r3, [r2, #24]                           ; Store initial r9
+    STR     r3, [r2, #28]                           ; Store initial r10
+    STR     r3, [r2, #32]                           ; Store initial r11
+;
+;    /* Hardware stack follows.  /
+;
+    STR     r3, [r2, #36]                           ; Store initial r0
+    STR     r3, [r2, #40]                           ; Store initial r1
+    STR     r3, [r2, #44]                           ; Store initial r2
+    STR     r3, [r2, #48]                           ; Store initial r3
+    STR     r3, [r2, #52]                           ; Store initial r12
+    MOV     r3, #0xFFFFFFFF                         ; Poison EXC_RETURN value
+    STR     r3, [r2, #56]                           ; Store initial lr
+    STR     r1, [r2, #60]                           ; Store initial pc
+    MOV     r3, #0x01000000                         ; Only T-bit need be set
+    STR     r3, [r2, #64]                           ; Store initial xPSR
+;
+;    /* Setup stack pointer.  */
+;    thread_ptr -> tx_thread_stack_ptr =  r2;
+;
+    STR     r2, [r0, #8]                            ; Save stack pointer in thread's
+                                                    ;   control block
+    BX      lr                                      ; Return to caller
+;}
+    END
+
diff --git a/ports/cortex_m4/keil/src/tx_thread_system_return.s b/ports/cortex_m4/keil/src/tx_thread_system_return.s
new file mode 100644
index 00000000..1e9c99a8
--- /dev/null
+++ b/ports/cortex_m4/keil/src/tx_thread_system_return.s
@@ -0,0 +1,96 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+;
+    AREA    ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_system_return                          Cortex-M4/AC5    */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is target processor specific.  It is used to transfer */
+;/*    control from a thread back to the ThreadX system.  Only a           */
+;/*    minimal context is saved since the compiler assumes temp registers  */
+;/*    are going to get slicked by a function call anyway.                 */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_schedule                   Thread scheduling loop        */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ThreadX components                                                  */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_system_return(VOID)
+;{
+    EXPORT  _tx_thread_system_return
+_tx_thread_system_return
+;
+;    /* Return to real scheduler via PendSV. Note that this routine is often 
+;       replaced with in-line assembly in tx_port.h to improved performance.  */
+;     
+    MOV     r0, #0x10000000                         ; Load PENDSVSET bit
+    MOV     r1, #0xE000E000                         ; Load NVIC base
+    STR     r0, [r1, #0xD04]                        ; Set PENDSVBIT in ICSR
+    MRS     r0, IPSR                                ; Pickup IPSR
+    CMP     r0, #0                                  ; Is it a thread returning?
+    BNE     _isr_context                            ; If ISR, skip interrupt enable
+    MRS     r1, PRIMASK                             ; Thread context returning, pickup PRIMASK
+    CPSIE   i                                       ; Enable interrupts
+    MSR     PRIMASK, r1                             ; Restore original interrupt posture
+_isr_context
+    BX      lr                                      ; Return to caller 
+;}
+    END  
+    
diff --git a/ports/cortex_m4/keil/src/tx_timer_interrupt.s b/ports/cortex_m4/keil/src/tx_timer_interrupt.s
new file mode 100644
index 00000000..3a53a2ee
--- /dev/null
+++ b/ports/cortex_m4/keil/src/tx_timer_interrupt.s
@@ -0,0 +1,271 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Timer                                                               */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_timer.h"
+;#include "tx_thread.h"
+;
+;
+;Define Assembly language external references...
+;
+    IMPORT      _tx_timer_time_slice
+    IMPORT      _tx_timer_system_clock
+    IMPORT      _tx_timer_current_ptr
+    IMPORT      _tx_timer_list_start
+    IMPORT      _tx_timer_list_end
+    IMPORT      _tx_timer_expired_time_slice
+    IMPORT      _tx_timer_expired
+    IMPORT      _tx_thread_time_slice
+    IMPORT      _tx_timer_expiration_process
+    IMPORT      _tx_thread_preempt_disable
+    IMPORT      _tx_thread_current_ptr
+    IMPORT      _tx_thread_execute_ptr
+;
+;
+    AREA ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_timer_interrupt                               Cortex-M4/AC5    */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function processes the hardware timer interrupt.  This         */
+;/*    processing includes incrementing the system clock and checking for  */
+;/*    time slice and/or timer expiration.  If either is found, the        */
+;/*    interrupt context save/restore functions are called along with the  */
+;/*    expiration functions.                                               */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_timer_expiration_process          Timer expiration processing   */
+;/*    _tx_thread_time_slice                 Time slice interrupted thread */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    interrupt vector                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_timer_interrupt(VOID)
+;{
+    EXPORT  _tx_timer_interrupt
+_tx_timer_interrupt
+;
+;    /* Upon entry to this routine, it is assumed that context save has already
+;       been called, and therefore the compiler scratch registers are available
+;       for use.  */
+;
+;    /* Increment the system clock.  */
+;    _tx_timer_system_clock++;
+;
+    MOV32   r1, _tx_timer_system_clock              ; Pickup address of system clock
+    LDR     r0, [r1, #0]                            ; Pickup system clock
+    ADD     r0, r0, #1                              ; Increment system clock
+    STR     r0, [r1, #0]                            ; Store new system clock
+;
+;    /* Test for time-slice expiration.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    MOV32   r3, _tx_timer_time_slice                ; Pickup address of time-slice 
+    LDR     r2, [r3, #0]                            ; Pickup time-slice
+    CBZ     r2,  __tx_timer_no_time_slice           ; Is it non-active?
+                                                    ; Yes, skip time-slice processing
+;
+;       /* Decrement the time_slice.  */
+;       _tx_timer_time_slice--;
+;
+    SUB     r2, r2, #1                              ; Decrement the time-slice
+    STR     r2, [r3, #0]                            ; Store new time-slice value
+;
+;       /* Check for expiration.  */
+;       if (__tx_timer_time_slice == 0)
+;
+    CBNZ    r2, __tx_timer_no_time_slice            ; Has it expired?
+;
+;       /* Set the time-slice expired flag.  */
+;       _tx_timer_expired_time_slice =  TX_TRUE;
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup address of expired flag
+    MOV     r0, #1                                  ; Build expired value
+    STR     r0, [r3, #0]                            ; Set time-slice expiration flag
+;
+;    }
+;
+__tx_timer_no_time_slice
+;
+;    /* Test for timer expiration.  */
+;    if (*_tx_timer_current_ptr)
+;    {
+;
+    MOV32   r1, _tx_timer_current_ptr               ; Pickup current timer pointer address
+    LDR     r0, [r1, #0]                            ; Pickup current timer
+    LDR     r2, [r0, #0]                            ; Pickup timer list entry
+    CBZ     r2, __tx_timer_no_timer                 ; Is there anything in the list?
+                                                    ; No, just increment the timer
+;
+;        /* Set expiration flag.  */
+;        _tx_timer_expired =  TX_TRUE;
+;
+    MOV32   r3, _tx_timer_expired                   ; Pickup expiration flag address
+    MOV     r2, #1                                  ; Build expired value
+    STR     r2, [r3, #0]                            ; Set expired flag
+    B       __tx_timer_done                         ; Finished timer processing
+;
+;    }
+;    else
+;    {
+__tx_timer_no_timer
+;
+;        /* No timer expired, increment the timer pointer.  */
+;        _tx_timer_current_ptr++;
+;
+    ADD     r0, r0, #4                              ; Move to next timer
+;
+;        /* Check for wrap-around.  */
+;        if (_tx_timer_current_ptr == _tx_timer_list_end)
+;
+    MOV32   r3, _tx_timer_list_end                  ; Pickup addr of timer list end
+    LDR     r2, [r3, #0]                            ; Pickup list end
+    CMP     r0, r2                                  ; Are we at list end?
+    BNE     __tx_timer_skip_wrap                    ; No, skip wrap-around logic
+;
+;            /* Wrap to beginning of list.  */
+;            _tx_timer_current_ptr =  _tx_timer_list_start;
+;
+    MOV32   r3, _tx_timer_list_start                ; Pickup addr of timer list start
+    LDR     r0, [r3, #0]                            ; Set current pointer to list start
+;
+__tx_timer_skip_wrap
+;
+    STR     r0, [r1, #0]                            ; Store new current timer pointer
+;    }
+;
+__tx_timer_done
+;
+;
+;    /* See if anything has expired.  */
+;    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+;    {
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup addr of expired flag
+    LDR     r2, [r3, #0]                            ; Pickup time-slice expired flag
+    CBNZ    r2, __tx_something_expired              ; Did a time-slice expire?
+                                                    ; If non-zero, time-slice expired
+    MOV32   r1, _tx_timer_expired                   ; Pickup addr of other expired flag
+    LDR     r0, [r1, #0]                            ; Pickup timer expired flag
+    CBZ     r0, __tx_timer_nothing_expired          ; Did a timer expire?
+                                                    ; No, nothing expired
+;
+__tx_something_expired
+;
+;
+    STMDB   sp!, {r0, lr}                           ; Save the lr register on the stack
+                                                    ;   and save r0 just to keep 8-byte alignment
+;
+;    /* Did a timer expire?  */
+;    if (_tx_timer_expired)
+;    {
+;
+    MOV32   r1, _tx_timer_expired                   ; Pickup addr of expired flag
+    LDR     r0, [r1, #0]                            ; Pickup timer expired flag
+    CBZ     r0, __tx_timer_dont_activate            ; Check for timer expiration
+                                                    ; If not set, skip timer activation
+;
+;        /* Process timer expiration.  */
+;        _tx_timer_expiration_process();
+;
+    BL      _tx_timer_expiration_process            ; Call the timer expiration handling routine
+;
+;    }
+__tx_timer_dont_activate
+;
+;    /* Did time slice expire?  */
+;    if (_tx_timer_expired_time_slice)
+;    {
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup addr of time-slice expired 
+    LDR     r2, [r3, #0]                            ; Pickup the actual flag
+    CBZ     r2, __tx_timer_not_ts_expiration        ; See if the flag is set
+                                                    ; No, skip time-slice processing
+;
+;        /* Time slice interrupted thread.  */
+;        _tx_thread_time_slice(); 
+
+    BL      _tx_thread_time_slice                   ; Call time-slice processing
+    MOV32   r0, _tx_thread_preempt_disable          ; Build address of preempt disable flag
+    LDR     r1, [r0]                                ; Is the preempt disable flag set?
+    CBNZ    r1, __tx_timer_skip_time_slice          ; Yes, skip the PendSV logic
+    MOV32   r0, _tx_thread_current_ptr              ; Build current thread pointer address
+    LDR     r1, [r0]                                ; Pickup the current thread pointer
+    MOV32   r2, _tx_thread_execute_ptr              ; Build execute thread pointer address
+    LDR     r3, [r2]                                ; Pickup the execute thread pointer
+    MOV32   r0, 0xE000ED04                          ; Build address of control register
+    MOV32   r2, 0x10000000                          ; Build value for PendSV bit
+    CMP     r1, r3                                  ; Are they the same?
+    BEQ     __tx_timer_skip_time_slice              ; If the same, there was no time-slice performed
+    STR     r2, [r0]                                ; Not the same, issue the PendSV for preemption
+__tx_timer_skip_time_slice
+;
+;    }
+;
+__tx_timer_not_ts_expiration
+;
+    LDMIA   sp!, {r0, lr}                           ; Recover lr register (r0 is just there for
+;
+;    }
+;
+__tx_timer_nothing_expired
+
+    DSB                                             ; Complete all memory access
+    BX      lr                                      ; Return to caller
+;
+;}
+    ALIGN
+    LTORG
+    END
+
diff --git a/ports/cortex_m7/ac5/example_build/build_threadx.bat b/ports/cortex_m7/ac5/example_build/build_threadx.bat
new file mode 100644
index 00000000..89656d39
--- /dev/null
+++ b/ports/cortex_m7/ac5/example_build/build_threadx.bat
@@ -0,0 +1,230 @@
+del tx.a
+armasm -g --cpu=cortex-m7 --apcs=interwork tx_initialize_low_level.s
+armasm -g --cpu=cortex-m7 --apcs=interwork ../src/tx_thread_stack_build.s
+armasm -g --cpu=cortex-m7 --apcs=interwork ../src/tx_thread_schedule.s
+armasm -g --cpu=cortex-m7 --apcs=interwork ../src/tx_thread_system_return.s
+armasm -g --cpu=cortex-m7 --apcs=interwork ../src/tx_thread_context_save.s
+armasm -g --cpu=cortex-m7 --apcs=interwork ../src/tx_thread_context_restore.s
+armasm -g --cpu=cortex-m7 --apcs=interwork ../src/tx_thread_interrupt_control.s
+armasm -g --cpu=cortex-m7 --apcs=interwork ../src/tx_thread_interrupt_disable.s
+armasm -g --cpu=cortex-m7 --apcs=interwork ../src/tx_thread_interrupt_restore.s
+armasm -g --cpu=cortex-m7 --apcs=interwork ../src/tx_timer_interrupt.s
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c
+armcc -g --cpu=cortex-m7 -Otime -O2 -Odiv -c --data_reorder -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c
+armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
+armar -r tx.a tx_initialize_low_level.o tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o
+armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
+armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
+armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
+armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
+armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
+armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
+armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
+armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
+armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
+armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o 
+armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
+armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
+armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
+armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
+armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
+armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
+armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
+armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
+armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
+armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
+armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o 
+armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
+armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
+armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o 
+armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o 
+armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o 
+armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
+armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
+armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
+armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
+armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o 
+armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
+armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o
diff --git a/ports/cortex_m7/ac5/example_build/build_threadx_sample.bat b/ports/cortex_m7/ac5/example_build/build_threadx_sample.bat
new file mode 100644
index 00000000..e964baa0
--- /dev/null
+++ b/ports/cortex_m7/ac5/example_build/build_threadx_sample.bat
@@ -0,0 +1,4 @@
+armasm -g --cpu=cortex-m7 --apcs=interwork tx_initialize_low_level.s
+armcc -c -g --cpu=cortex-m7 -O2 -I../../../../common/inc -I../inc sample_threadx.c
+armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --rw-base=0x20000000 --first __tx_vectors --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a
+
diff --git a/ports/cortex_m7/ac5/example_build/sample_threadx.c b/ports/cortex_m7/ac5/example_build/sample_threadx.c
new file mode 100644
index 00000000..418ec634
--- /dev/null
+++ b/ports/cortex_m7/ac5/example_build/sample_threadx.c
@@ -0,0 +1,369 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include "tx_api.h"
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_BYTE_POOL_SIZE     9120
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+/* Define main entry point.  */
+
+int main()
+{
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s
new file mode 100644
index 00000000..439b0d8b
--- /dev/null
+++ b/ports/cortex_m7/ac5/example_build/tx_initialize_low_level.s
@@ -0,0 +1,272 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Initialize                                                          */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_initialize.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IMPORT  _tx_thread_system_stack_ptr
+    IMPORT  _tx_initialize_unused_memory
+    IMPORT  _tx_thread_context_save
+    IMPORT  _tx_thread_context_restore
+    IMPORT  _tx_timer_interrupt
+    IMPORT  __main
+    IMPORT  |Image$$RO$$Limit|
+    IMPORT  |Image$$RW$$Base|
+    IMPORT  |Image$$ZI$$Base|
+    IMPORT  |Image$$ZI$$Limit|
+    IMPORT  __tx_PendSVHandler
+;
+;
+SYSTEM_CLOCK        EQU     6000000
+SYSTICK_CYCLES      EQU     ((SYSTEM_CLOCK / 100) -1)
+;
+;
+;/* Setup the stack and heap areas.  */
+;
+STACK_SIZE          EQU     0x00000400
+HEAP_SIZE           EQU     0x00000000
+
+    AREA    STACK, NOINIT, READWRITE, ALIGN=3
+StackMem
+    SPACE   STACK_SIZE
+__initial_sp
+
+
+    AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+HeapMem
+    SPACE   HEAP_SIZE
+__heap_limit
+
+
+    AREA    RESET, CODE, READONLY
+;
+    EXPORT  __tx_vectors
+__tx_vectors
+    DCD     __initial_sp                            ; Reset and system stack ptr
+    DCD     Reset_Handler                           ; Reset goes to startup function
+    DCD     __tx_NMIHandler                         ; NMI
+    DCD     __tx_BadHandler                         ; HardFault
+    DCD     0                                       ; MemManage
+    DCD     0                                       ; BusFault
+    DCD     0                                       ; UsageFault
+    DCD     0                                       ; 7
+    DCD     0                                       ; 8
+    DCD     0                                       ; 9
+    DCD     0                                       ; 10
+    DCD     __tx_SVCallHandler                      ; SVCall
+    DCD     __tx_DBGHandler                         ; Monitor
+    DCD     0                                       ; 13
+    DCD     __tx_PendSVHandler                      ; PendSV
+    DCD     __tx_SysTickHandler                     ; SysTick
+    DCD     __tx_IntHandler                         ; Int 0
+    DCD     __tx_IntHandler                         ; Int 1
+    DCD     __tx_IntHandler                         ; Int 2
+    DCD     __tx_IntHandler                         ; Int 3
+        
+;
+;
+    AREA ||.text||, CODE, READONLY
+    EXPORT  Reset_Handler
+Reset_Handler
+    CPSID   i
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    LDR     r0, =0xE000ED88                         ; Pickup address of CPACR
+	LDR     r1, [r0]                                ; Pickup CPACR
+	MOV32   r2, 0x00F00000                          ; Build enable value
+	ORR     r1, r1, r2                              ; Or in enable value
+	STR     r1, [r0]                                ; Setup CPACR
+    ENDIF
+    LDR     r0, =__main
+    BX      r0
+
+
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_initialize_low_level                          Cortex-M7/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for any low-level processor            */
+;/*    initialization, including setting up interrupt vectors, setting     */
+;/*    up a periodic timer interrupt source, saving the system stack       */
+;/*    pointer for use in ISR processing later, and finding the first      */
+;/*    available RAM memory address for tx_application_define.             */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_initialize_low_level(VOID)
+;{
+    EXPORT  _tx_initialize_low_level
+_tx_initialize_low_level
+;
+;    /* Disable interrupts during ThreadX initialization.  */
+;
+    CPSID   i
+;
+;    /* Set base of available memory to end of non-initialised RAM area.  */
+;     
+    LDR     r0, =_tx_initialize_unused_memory       ; Build address of unused memory pointer
+    LDR     r1, =|Image$$ZI$$Limit|                 ; Build first free address
+    ADD     r1, r1, #4                              ; 
+    STR     r1, [r0]                                ; Setup first unused memory pointer
+;
+;    /* Setup Vector Table Offset Register.  */
+;    
+    MOV     r0, #0xE000E000                         ; Build address of NVIC registers
+    LDR     r1, =__tx_vectors                       ; Pickup address of vector table
+    STR     r1, [r0, #0xD08]                        ; Set vector table address   
+;
+;    /* Enable the cycle count register.  */
+;
+;    LDR     r0, =0xE0001000                         ; Build address of DWT register
+;    LDR     r1, [r0]                                ; Pickup the current value
+;    ORR     r1, r1, #1                              ; Set the CYCCNTENA bit
+;    STR     r1, [r0]                                ; Enable the cycle count register 
+;
+;    /* Set system stack pointer from vector value.  */
+;
+    LDR     r0, =_tx_thread_system_stack_ptr        ; Build address of system stack pointer
+    LDR     r1, =__tx_vectors                       ; Pickup address of vector table
+    LDR     r1, [r1]                                ; Pickup reset stack pointer
+    STR     r1, [r0]                                ; Save system stack pointer
+;
+;    /* Configure SysTick.  */
+;
+    MOV     r0, #0xE000E000                         ; Build address of NVIC registers
+    LDR     r1, =SYSTICK_CYCLES
+    STR     r1, [r0, #0x14]                         ; Setup SysTick Reload Value
+    MOV     r1, #0x7                                ; Build SysTick Control Enable Value
+    STR     r1, [r0, #0x10]                         ; Setup SysTick Control
+;
+;    /* Configure handler priorities.  */
+;
+    LDR     r1, =0x00000000                         ; Rsrv, UsgF, BusF, MemM
+    STR     r1, [r0, #0xD18]                        ; Setup System Handlers 4-7 Priority Registers
+
+    LDR     r1, =0xFF000000                         ; SVCl, Rsrv, Rsrv, Rsrv
+    STR     r1, [r0, #0xD1C]                        ; Setup System Handlers 8-11 Priority Registers
+                                                    ; Note: SVC must be lowest priority, which is 0xFF
+
+    LDR     r1, =0x40FF0000                         ; SysT, PnSV, Rsrv, DbgM
+    STR     r1, [r0, #0xD20]                        ; Setup System Handlers 12-15 Priority Registers
+                                                    ; Note: PnSV must be lowest priority, which is 0xFF
+;
+;    /* Return to caller.  */
+;    
+    BX      lr 
+;}
+;
+;       
+;/* Define initial heap/stack routine for the ARM RVCT startup code.
+;   This routine will set the initial stack and heap locations */
+;
+    EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+    LDR     r0, =HeapMem
+    LDR     r1, =(StackMem + STACK_SIZE)
+    LDR     r2, =(HeapMem + HEAP_SIZE)
+    LDR     r3, =StackMem
+    BX      lr
+;
+;
+;/* Define shells for each of the unused vectors.  */
+;
+    EXPORT  __tx_BadHandler
+__tx_BadHandler 
+    B       __tx_BadHandler
+
+    EXPORT  __tx_SVCallHandler
+__tx_SVCallHandler
+    B       __tx_SVCallHandler 
+
+    EXPORT  __tx_IntHandler
+__tx_IntHandler
+; VOID InterruptHandler (VOID)
+; {
+    PUSH    {r0, lr}
+        
+;    /* Do interrupt handler work here */
+;    /* .... */
+
+    POP     {r0, lr}
+    BX      LR
+; }
+
+        EXPORT  __tx_SysTickHandler
+__tx_SysTickHandler
+; VOID TimerInterruptHandler (VOID)
+; {
+;
+    PUSH    {r0, lr}
+    BL      _tx_timer_interrupt
+    POP     {r0, lr}
+    BX      LR
+; }
+
+    EXPORT  __tx_NMIHandler 
+__tx_NMIHandler
+    B       __tx_NMIHandler
+
+    EXPORT  __tx_DBGHandler
+__tx_DBGHandler
+    B       __tx_DBGHandler
+
+    ALIGN
+    LTORG
+    END
+
diff --git a/ports/cortex_m7/ac5/inc/tx_port.h b/ports/cortex_m7/ac5/inc/tx_port.h
new file mode 100644
index 00000000..57480ebb
--- /dev/null
+++ b/ports/cortex_m7/ac5/inc/tx_port.h
@@ -0,0 +1,471 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */
+/*                                                                        */
+/*    tx_port.h                                         Cortex-M7/AC5     */
+/*                                                           6.0.1        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file contains data type definitions that make the ThreadX      */
+/*    real-time kernel function identically on a variety of different     */
+/*    processor architectures.  For example, the size or number of bits   */
+/*    in an "int" data type vary between microprocessor architectures and */
+/*    even C compilers for the same microprocessor.  ThreadX does not     */
+/*    directly use native C data types.  Instead, ThreadX creates its     */
+/*    own special types that can be mapped to actual data types by this   */
+/*    file to guarantee consistency in the interface and functionality.   */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include 
+#include 
+
+
+/* Define ThreadX basic types for this port.  */
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */
+#endif
+
+
+/* Define various constants for the ThreadX Cortex-M3 port.  */
+
+#define TX_INT_DISABLE                          1           /* Disable interrupts               */
+#define TX_INT_ENABLE                           0           /* Enable interrupts                */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_MISRA_ENABLE
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0xE0001004)  
+#endif
+#else
+ULONG   _tx_misra_time_stamp_get(VOID);
+#define TX_TRACE_TIME_SOURCE                    _tx_misra_time_stamp_get()
+#endif
+
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          (0)
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#ifdef TX_MISRA_ENABLE
+#define TX_DISABLE_INLINE
+#else
+#define TX_INLINE_INITIALIZATION
+#endif
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifndef TX_MISRA_ENABLE
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#define TX_THREAD_EXTENSION_2                   
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+
+
+#ifndef TX_MISRA_ENABLE
+
+register unsigned int _ipsr __asm("ipsr");
+
+#endif
+
+
+#ifdef __TARGET_FPU_VFP
+
+#ifdef TX_MISRA_ENABLE
+
+ULONG  _tx_misra_control_get(void);
+void   _tx_misra_control_set(ULONG value);
+ULONG  _tx_misra_fpccr_get(void);
+void   _tx_misra_vfp_touch(void);
+
+#else
+
+#ifdef TX_SOURCE_CODE
+
+register ULONG  _control __asm("control");
+
+#endif
+#endif
+
+/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA
+   in order to ensure no lazy stacking will occur. */
+
+#ifndef TX_MISRA_ENABLE
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)                   {                                                                                             \
+                                                                    ULONG  _tx_vfp_state;                                                                         \
+                                                                        _tx_vfp_state =  _control;                                                                \
+                                                                        _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                          \
+                                                                        _control =       _tx_vfp_state;                                                           \
+                                                                    }
+#else
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)                   {                                                                                             \
+                                                                    ULONG  _tx_vfp_state;                                                                         \
+                                                                        _tx_vfp_state =  _tx_misra_control_get();                                                 \
+                                                                        _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                          \
+                                                                        _tx_misra_control_set(_tx_vfp_state);                                                     \
+                                                                    }
+                                                                    
+#endif
+
+/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR.
+   If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating
+   this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush 
+   the lazy FPU save, then restore the CONTROL.FPCA state. */
+
+#ifndef TX_MISRA_ENABLE
+
+void _tx_vfp_access(void);
+
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  {                                                                                             \
+                                                                    ULONG  _tx_system_state;                                                                      \
+                                                                        _tx_system_state =  TX_THREAD_GET_SYSTEM_STATE();                                         \
+                                                                        if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr))        \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_vfp_state;                                                                     \
+                                                                            _tx_vfp_state =  _control;                                                            \
+                                                                            _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                      \
+                                                                            _control =       _tx_vfp_state;                                                       \
+                                                                        }                                                                                         \
+                                                                        else                                                                                      \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_fpccr;                                                                         \
+                                                                            _tx_fpccr =  *((ULONG *) 0xE000EF34);                                                 \
+                                                                            _tx_fpccr =  _tx_fpccr & ((ULONG) 0x01);                                              \
+                                                                            if (_tx_fpccr == ((ULONG) 0x01))                                                      \
+                                                                            {                                                                                     \
+                                                                            ULONG _tx_vfp_state;                                                                  \
+                                                                                _tx_vfp_state =  _control;                                                        \
+                                                                                _tx_vfp_state =  _tx_vfp_state & ((ULONG) 0x4);                                   \
+                                                                                _tx_vfp_access();                                                                 \
+                                                                                if (_tx_vfp_state == ((ULONG) 0))                                                 \
+                                                                                {                                                                                 \
+                                                                                    _tx_vfp_state =  _control;                                                    \
+                                                                                    _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                              \
+                                                                                    _control =       _tx_vfp_state;                                               \
+                                                                                }                                                                                 \
+                                                                            }                                                                                     \
+                                                                        }                                                                                         \
+                                                                    }
+#else
+
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  {                                                                                             \
+                                                                    ULONG  _tx_system_state;                                                                      \
+                                                                        _tx_system_state =  TX_THREAD_GET_SYSTEM_STATE();                                         \
+                                                                        if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr))        \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_vfp_state;                                                                     \
+                                                                            _tx_vfp_state =  _tx_misra_control_get();                                             \
+                                                                            _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                      \
+                                                                            _tx_misra_control_set(_tx_vfp_state);                                                 \
+                                                                        }                                                                                         \
+                                                                        else                                                                                      \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_fpccr;                                                                         \
+                                                                            _tx_fpccr =  _tx_misra_fpccr_get();                                                   \
+                                                                            _tx_fpccr =  _tx_fpccr & ((ULONG) 0x01);                                              \
+                                                                            if (_tx_fpccr == ((ULONG) 0x01))                                                      \
+                                                                            {                                                                                     \
+                                                                            ULONG _tx_vfp_state;                                                                  \
+                                                                                _tx_vfp_state = _tx_misra_control_get();                                          \
+                                                                                _tx_vfp_state =  _tx_vfp_state & ((ULONG) 0x4);                                   \
+                                                                                _tx_misra_vfp_touch();                                                            \
+                                                                                if (_tx_vfp_state == ((ULONG) 0))                                                 \
+                                                                                {                                                                                 \
+                                                                                    _tx_vfp_state =  _tx_misra_control_get();                                     \
+                                                                                    _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                              \
+                                                                                    _tx_misra_control_set(_tx_vfp_state);                                         \
+                                                                                }                                                                                 \
+                                                                            }                                                                                     \
+                                                                        }                                                                                         \
+                                                                    }
+#endif
+
+#else
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  
+
+#endif
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Define the get system state macro.   */
+   
+#ifndef TX_THREAD_GET_SYSTEM_STATE
+#ifndef TX_MISRA_ENABLE
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | _ipsr)
+#else
+ULONG   _tx_misra_ipsr_get(VOID);
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | _tx_misra_ipsr_get())
+#endif
+#endif
+
+
+/* Define the check for whether or not to call the _tx_thread_system_return function.  A non-zero value
+   indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h
+   for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always
+   zero after initialization for Cortex-M ports. */
+
+#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
+#define TX_THREAD_SYSTEM_RETURN_CHECK(c)    (c) = ((ULONG) _tx_thread_preempt_disable); 
+#endif
+
+
+/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to 
+   prevent early scheduling on Cortex-M parts.  */
+   
+#define TX_PORT_SPECIFIC_POST_INITIALIZATION    _tx_thread_preempt_disable++;
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef TX_DISABLE_INLINE
+   
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       (b) =  (UINT) __clz(__rbit((m)));
+
+#endif
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifdef TX_DISABLE_INLINE
+
+UINT                                            _tx_thread_interrupt_disable(VOID);
+VOID                                            _tx_thread_interrupt_restore(UINT previous_posture);
+
+#define TX_INTERRUPT_SAVE_AREA                  register UINT interrupt_save;
+
+#define TX_DISABLE                              interrupt_save = _tx_thread_interrupt_disable();
+
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+
+#else
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int  was_masked;
+#define TX_DISABLE                              was_masked = __disable_irq();
+#define TX_RESTORE                              if (was_masked == 0) __enable_irq();
+
+#define _tx_thread_system_return                _tx_thread_system_return_inline
+
+
+static void _tx_thread_system_return_inline(void)
+{
+unsigned int          was_masked;
+
+
+    /* Set PendSV to invoke ThreadX scheduler.  */
+    *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    if (_ipsr == 0)
+    {
+        was_masked = __disable_irq();
+        __enable_irq();
+        if (was_masked != 0)
+            __disable_irq();
+    }
+}
+#endif
+
+
+/* Define FPU extension for the Cortex-M7.  Each is assumed to be called in the context of the executing
+   thread. These are no longer needed, but are preserved for backward compatibility only.  */
+
+void    tx_thread_fpu_enable(void);
+void    tx_thread_fpu_disable(void);
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Cortex-M7/AC5 Version 6.0 *";
+#else
+#ifdef TX_MISRA_ENABLE
+extern  CHAR                    _tx_version_id[100];
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+#endif
+
+
+#endif
+
+
+
+
diff --git a/ports/cortex_m7/ac5/readme_threadx.txt b/ports/cortex_m7/ac5/readme_threadx.txt
new file mode 100644
index 00000000..4cf8c2da
--- /dev/null
+++ b/ports/cortex_m7/ac5/readme_threadx.txt
@@ -0,0 +1,207 @@
+                     Microsoft's Azure RTOS ThreadX for Cortex-M7 
+
+                               Thumb & 32-bit Mode
+
+                            Using ARM Compiler 5 (AC5)
+ 
+1.  Building the ThreadX run-time Library
+
+First make sure you are in the "example_build" directory. Also, make sure that 
+you have setup your path and other environment variables necessary for the AC5 
+compiler. At this point you may run the build_threadx.bat batch file. This will 
+build the ThreadX run-time environment in the "example_build" directory. 
+
+You should observe assembly and compilation of a series of ThreadX source 
+files. At the end of the batch file, they are all combined into the 
+run-time library file: tx.a. This file must be linked with your 
+application in order to use ThreadX.
+
+
+2.  Demonstration System
+
+The ThreadX demonstration is designed to execute under the ARM DS Cortex-M7
+simulator.
+
+Building the demonstration is easy; simply execute the build_threadx_sample.bat 
+batch file while inside the "example_build" directory. 
+
+You should observe the compilation of sample_threadx.c (which is the demonstration 
+application) and linking with tx.a. The resulting file sample_threadx.axf 
+is a binary file that can be downloaded and executed on the ARM DS Cortex-M7 
+simulator.
+
+
+3.  System Initialization
+
+The entry point in ThreadX for the Cortex-M7 using AC5 tools is at label 
+__main. This is defined within the AC5 compiler's startup code. In 
+addition, this is where all static and global pre-set C variable 
+initialization processing takes place.
+
+The ThreadX tx_initialize_low_level.s file is responsible for setting up 
+various system data structures, the vector area, and a periodic timer interrupt 
+source. 
+
+In addition, _tx_initialize_low_level determines the first available 
+address for use by the application, which is supplied as the sole input 
+parameter to your application definition function, tx_application_define.
+
+
+4.  Register Usage and Stack Frames
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have the same stack frame in the Cortex-M7 version of
+ThreadX. The top of the suspended thread's stack is pointed to by 
+tx_thread_stack_ptr in the associated thread control block TX_THREAD.
+
+Non-FPU Stack Frame:
+
+  Stack Offset     Stack Contents 
+
+     0x00               r4
+     0x04               r5
+     0x08               r6
+     0x0C               r7
+     0x10               r8
+     0x14               r9
+     0x18               r10
+     0x1C               r11
+     0x20               r0          (Hardware stack starts here!!)
+     0x24               r1
+     0x28               r2
+     0x2C               r3
+     0x30               r12
+     0x34               lr
+     0x38               pc
+     0x3C               xPSR
+
+FPU Stack Frame (only interrupted thread with FPU enabled):
+
+  Stack Offset     Stack Contents 
+
+     0x00               s0
+     0x04               s1
+     0x08               s2
+     0x0C               s3
+     0x10               s4
+     0x14               s5
+     0x18               s6
+     0x1C               s7
+     0x20               s8
+     0x24               s9
+     0x28               s10
+     0x2C               s11
+     0x30               s12
+     0x34               s13
+     0x38               s14
+     0x3C               s15
+     0x40               s16
+     0x44               s17
+     0x48               s18
+     0x4C               s19
+     0x50               s20
+     0x54               s21
+     0x58               s22
+     0x5C               s23
+     0x60               s24
+     0x64               s25
+     0x68               s26
+     0x6C               s27
+     0x70               s28
+     0x74               s29
+     0x78               s30
+     0x7C               s31
+     0x80               fpscr
+     0x84               r4          
+     0x88               r5          
+     0x8C               r6          
+     0x90               r7          
+     0x94               r8          
+     0x98               r9          
+     0x9C               r10 (sl)    
+     0xA0               r11         
+     0xA4               r0          (Hardware stack starts here!!)
+     0xA8               r1          
+     0xAC               r2          
+     0xB0               r3          
+     0xB4               r12         
+     0xB8               lr          
+     0xBC               pc          
+     0xC0               xPSR        
+
+
+5.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+breakpoints inside of ThreadX itself. Of course, this costs some 
+performance. To make it run faster, you can change the ThreadX_Library.Uv2 
+project to debugging and enable all compiler optimizations. 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+6.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-M7
+targets. There are a certain set of requirements that are defined in the 
+following sub-sections:
+
+
+6.1  Vector Area
+
+The Cortex-M7 vectors start at the label __tx_vectors. The application may modify
+the vector area according to its needs.
+
+
+6.2 Managed Interrupts
+
+ISRs for Cortex-M can be written completely in C (or assembly language) without any
+calls to _tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed
+access to the ThreadX API that is available to ISRs.
+
+ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
+
+void    your_C_isr(void)
+{
+
+    /* ISR processing goes here, including any needed function calls.  */
+}
+
+ISRs written in assembly language will take the form:
+
+    EXPORT  your_assembly_isr
+your_assembly_isr
+
+    PUSH    {r0, lr}
+
+    ; ISR processing goes here, including any needed function calls.
+
+    POP     {r0, lr}
+    BX      lr
+
+
+7. FPU Support
+
+ThreadX for Cortex-M7 supports automatic ("lazy") VFP support, which means that applications threads 
+can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread 
+context - no additional setup by the application.
+
+
+8.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX 6.0.1 version for Cortex-M7 using AC5 tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_m7/ac5/src/tx_thread_context_restore.s b/ports/cortex_m7/ac5/src/tx_thread_context_restore.s
new file mode 100644
index 00000000..b58508d3
--- /dev/null
+++ b/ports/cortex_m7/ac5/src/tx_thread_context_restore.s
@@ -0,0 +1,99 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT  _tx_execution_isr_exit
+    ENDIF
+;
+;
+    AREA    ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_context_restore                        Cortex-M7/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function restores the interrupt context if it is processing a  */
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */
+;/*    if no thread was running, the function returns to the scheduler.    */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_schedule                   Thread scheduling routine     */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ISRs                                  Interrupt Service Routines    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_restore(VOID)
+;{
+    EXPORT  _tx_thread_context_restore
+_tx_thread_context_restore
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR exit function to indicate an ISR is complete.  */
+;
+    PUSH    {r0,lr}                                 ; Save ISR lr
+    BL      _tx_execution_isr_exit                  ; Call the ISR exit function
+    POP     {r0,lr}                                 ; Restore ISR lr
+    ENDIF
+;
+    POP     {lr}
+    BX      lr
+;}
+    ALIGN
+    LTORG
+    END
diff --git a/ports/cortex_m7/ac5/src/tx_thread_context_save.s b/ports/cortex_m7/ac5/src/tx_thread_context_save.s
new file mode 100644
index 00000000..5e789200
--- /dev/null
+++ b/ports/cortex_m7/ac5/src/tx_thread_context_save.s
@@ -0,0 +1,99 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT  _tx_execution_isr_enter
+    ENDIF
+;
+;
+    AREA    ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_context_save                           Cortex-M7/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function saves the context of an executing thread in the       */
+;/*    beginning of interrupt processing.  The function also ensures that  */
+;/*    the system stack is used upon return to the calling ISR.            */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ISRs                                                                */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_save(VOID)
+;{
+    EXPORT  _tx_thread_context_save
+_tx_thread_context_save
+   IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {r0, lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter                 ; Call the ISR enter function
+    POP     {r0, lr}                                ; Recover ISR lr
+    ENDIF
+;
+;    /* Return to interrupt processing.  */
+;     
+    BX      lr                                      ; Return to interrupt processing caller
+;}
+    ALIGN
+    LTORG
+    END
diff --git a/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s
new file mode 100644
index 00000000..17e4a59a
--- /dev/null
+++ b/ports/cortex_m7/ac5/src/tx_thread_interrupt_control.s
@@ -0,0 +1,85 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_control                      Cortex-M7/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for changing the interrupt lockout     */
+;/*    posture of the system.                                              */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    new_posture                           New interrupt lockout posture */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    old_posture                           Old interrupt lockout posture */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_control(UINT new_posture)
+;{
+    EXPORT  _tx_thread_interrupt_control
+_tx_thread_interrupt_control
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    MRS     r1, PRIMASK
+    MSR     PRIMASK, r0
+    MOV     r0, r1
+    BX      lr
+;
+;}
+    END
+    
diff --git a/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s
new file mode 100644
index 00000000..894f969a
--- /dev/null
+++ b/ports/cortex_m7/ac5/src/tx_thread_interrupt_disable.s
@@ -0,0 +1,83 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_disable                      Cortex-M7/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for disabling interrupts and returning */
+;/*    the previous interrupt lockout posture.                             */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    old_posture                           Old interrupt lockout posture */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_disable(UINT new_posture)
+;{
+    EXPORT  _tx_thread_interrupt_disable
+_tx_thread_interrupt_disable
+;
+;    /* Return current interrupt lockout posture.  */
+;
+    MRS     r0, PRIMASK
+    CPSID   i
+    BX      lr
+;
+;}
+    END
diff --git a/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s
new file mode 100644
index 00000000..364f5414
--- /dev/null
+++ b/ports/cortex_m7/ac5/src/tx_thread_interrupt_restore.s
@@ -0,0 +1,82 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_restore                      Cortex-M7/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for restoring the previous             */
+;/*    interrupt lockout posture.                                          */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    previous_posture                      Previous interrupt posture    */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_interrupt_restore(UINT new_posture)
+;{
+    EXPORT  _tx_thread_interrupt_restore
+_tx_thread_interrupt_restore
+;
+;    /* Restore previous interrupt lockout posture.  */
+;
+    MSR     PRIMASK, r0
+    BX      lr
+;
+;}
+    END
diff --git a/ports/cortex_m7/ac5/src/tx_thread_schedule.s b/ports/cortex_m7/ac5/src/tx_thread_schedule.s
new file mode 100644
index 00000000..34bc8cd0
--- /dev/null
+++ b/ports/cortex_m7/ac5/src/tx_thread_schedule.s
@@ -0,0 +1,298 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;   
+    IMPORT  _tx_thread_current_ptr
+    IMPORT  _tx_thread_execute_ptr
+    IMPORT  _tx_timer_time_slice
+    IMPORT  _tx_thread_system_stack_ptr
+    IMPORT  _tx_thread_preempt_disable
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT  _tx_execution_thread_enter
+    IMPORT  _tx_execution_thread_exit        
+    ENDIF
+;
+;
+    AREA    ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_schedule                               Cortex-M7/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function waits for a thread control block pointer to appear in */
+;/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
+;/*    in the variable, the corresponding thread is resumed.               */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter          ThreadX entry function         */
+;/*    _tx_thread_system_return             Return to system from thread   */
+;/*    _tx_thread_context_restore           Restore thread's context       */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_schedule(VOID)
+;{
+    EXPORT  _tx_thread_schedule
+_tx_thread_schedule
+;
+;    /* This function should only ever be called on Cortex-M
+;       from the first schedule request. Subsequent scheduling occurs
+;       from the PendSV handling routines below. */
+;
+;    /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets.  */
+;     
+    MOV     r0, #0                                  ; Build value for TX_FALSE
+    LDR     r2, =_tx_thread_preempt_disable         ; Build address of preempt disable flag
+    STR     r0, [r2, #0]                            ; Clear preempt disable flag
+;
+;    /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked.  */
+;
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    MRS     r0, CONTROL                             ; Pickup current CONTROL register
+    BIC     r0, r0, #4                              ; Clear the FPCA bit 
+    MSR     CONTROL, r0                             ; Setup new CONTROL register
+    ENDIF
+;
+;    /* Enable the interrupts */
+;
+    CPSIE   i
+;       
+;    /* Enter the scheduler for the first time.  */
+;
+    MOV     r0, #0x10000000                         ; Load PENDSVSET bit
+    MOV     r1, #0xE000E000                         ; Load NVIC base
+    STR     r0, [r1, #0xD04]                        ; Set PENDSVBIT in ICSR
+    DSB                                             ; Complete all memory accesses
+    ISB                                             ; Flush pipeline
+;
+;    /* Wait here for the PendSV to take place.  */
+;     
+__tx_wait_here
+    B       __tx_wait_here                          ; Wait for the PendSV to happen
+;}
+;
+;    /* Generic context switching PendSV handler.  */
+;     
+    EXPORT  __tx_PendSVHandler
+    EXPORT  PendSV_Handler
+__tx_PendSVHandler  
+PendSV_Handler
+;
+;    /* Get current thread value and new thread pointer.  */
+;       
+__tx_ts_handler 
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread exit function to indicate the thread is no longer executing.  */
+;
+    CPSID   i                                       ; Disable interrupts
+    PUSH    {r0, lr}                                ; Save LR (and r0 just for alignment)
+    BL      _tx_execution_thread_exit               ; Call the thread exit function
+    POP     {r0, lr}                                ; Recover LR
+    CPSIE   i                                       ; Enable interrupts
+    ENDIF
+    MOV32   r0, _tx_thread_current_ptr              ; Build current thread pointer address
+    MOV32   r2, _tx_thread_execute_ptr              ; Build execute thread pointer address
+    MOV     r3, #0                                  ; Build NULL value
+    LDR     r1, [r0]                                ; Pickup current thread pointer
+;
+;    /* Determine if there is a current thread to finish preserving.  */
+;       
+    CBZ     r1, __tx_ts_new                         ; If NULL, skip preservation
+;
+;    /* Recover PSP and preserve current thread context.  */
+;
+    STR     r3, [r0]                                ; Set _tx_thread_current_ptr to NULL
+    MRS     r12, PSP                                ; Pickup PSP pointer (thread's stack pointer)
+    STMDB   r12!, {r4-r11}                          ; Save its remaining registers
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    TST     LR, #0x10                               ; Determine if the VFP extended frame is present
+    BNE     _skip_vfp_save
+    VSTMDB  r12!,{s16-s31}                          ; Yes, save additional VFP registers
+_skip_vfp_save
+    ENDIF
+    MOV32   r4, _tx_timer_time_slice                ; Build address of time-slice variable
+    STMDB   r12!, {LR}                              ; Save LR on the stack
+;
+;    /* Determine if time-slice is active. If it isn't, skip time handling processing.  */
+;
+    LDR     r5, [r4]                                ; Pickup current time-slice
+    STR     r12, [r1, #8]                           ; Save the thread stack pointer
+    CBZ     r5, __tx_ts_new                         ; If not active, skip processing
+;
+;    /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable.  */
+;
+    STR     r5, [r1, #24]                           ; Save current time-slice
+;
+;    /* Clear the global time-slice.  */
+;
+    STR     r3, [r4]                                ; Clear time-slice
+;       
+;    /* Executing thread is now completely preserved!!!  */
+;
+__tx_ts_new 
+;
+;    /* Now we are looking for a new thread to execute!  */
+;
+    CPSID   i                                       ; Disable interrupts
+    LDR     r1, [r2]                                ; Is there another thread ready to execute?
+    CBZ     r1, __tx_ts_wait                        ; No, skip to the wait processing
+;
+;    /* Yes, another thread is ready for else, make the current thread the new thread.  */
+;
+    STR     r1, [r0]                                ; Setup the current thread pointer to the new thread
+    CPSIE   i                                       ; Enable interrupts
+;
+;    /* Increment the thread run count.  */
+;
+__tx_ts_restore 
+    LDR     r7, [r1, #4]                            ; Pickup the current thread run count
+    MOV32   r4, _tx_timer_time_slice                ; Build address of time-slice variable
+    LDR     r5, [r1, #24]                           ; Pickup thread's current time-slice
+    ADD     r7, r7, #1                              ; Increment the thread run count
+    STR     r7, [r1, #4]                            ; Store the new run count
+;
+;    /* Setup global time-slice with thread's current time-slice.  */
+;
+    STR     r5, [r4]                                ; Setup global time-slice
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread entry function to indicate the thread is executing.  */
+;
+    PUSH    {r0, r1}                                ; Save r0/r1
+    BL      _tx_execution_thread_enter              ; Call the thread execution enter function
+    POP     {r0, r1}                                ; Recover r3
+    ENDIF
+;
+;    /* Restore the thread context and PSP.  */
+;
+    LDR     r12, [r1, #8]                           ; Pickup thread's stack pointer
+    LDMIA   r12!, {LR}                              ; Pickup LR
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    TST     LR, #0x10                               ; Determine if the VFP extended frame is present
+    BNE     _skip_vfp_restore                       ; If not, skip VFP restore 
+    VLDMIA  r12!, {s16-s31}                         ; Yes, restore additional VFP registers
+_skip_vfp_restore
+    ENDIF
+    LDMIA   r12!, {r4-r11}                          ; Recover thread's registers
+    MSR     PSP, r12                                ; Setup the thread's stack pointer
+;
+;    /* Return to thread.  */
+;       
+        BX      lr                                  ; Return to thread!
+;
+;    /* The following is the idle wait processing... in this case, no threads are ready for execution and the
+;       system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts 
+;       are disabled to allow use of WFI for waiting for a thread to arrive.  */
+;
+__tx_ts_wait    
+    CPSID   i                                       ; Disable interrupts
+    LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
+    STR     r1, [r0]                                ; Store it in the current pointer
+    CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+    IF :DEF:TX_ENABLE_WFI
+    DSB                                             ; Ensure no outstanding memory transactions
+    WFI                                             ; Wait for interrupt
+    ISB                                             ; Ensure pipeline is flushed
+    ENDIF
+    CPSIE   i                                       ; Enable interrupts
+    B       __tx_ts_wait                            ; Loop to continue waiting
+;
+;    /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are 
+;       already in the handler!  */
+;
+__tx_ts_ready   
+    MOV     r7, #0x08000000                         ; Build clear PendSV value
+    MOV     r8, #0xE000E000                         ; Build base NVIC address
+    STR     r7, [r8, #0xD04]                        ; Clear any PendSV 
+;
+;    /* Re-enable interrupts and restore new thread.  */
+;       
+    CPSIE   i                                       ; Enable interrupts
+    B       __tx_ts_restore                         ; Restore the thread
+
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    EXPORT  tx_thread_fpu_enable
+tx_thread_fpu_enable
+;
+;    /* Automatic VPF logic is supported, this function is present only for 
+;       backward compatibility purposes and therefore simply returns.  */
+;
+    BX      LR                                      ; Return to caller
+
+    EXPORT  tx_thread_fpu_disable
+tx_thread_fpu_disable
+;
+;    /* Automatic VPF logic is supported, this function is present only for 
+;       backward compatibility purposes and therefore simply returns.  */
+;
+    BX      LR                                      ; Return to caller
+
+    EXPORT  _tx_vfp_access
+_tx_vfp_access
+    VMOV.F32 s0, s0                                 ; Simply access the VFP
+    BX       lr                                     ; Return to caller
+
+
+    ENDIF
+
+    ALIGN
+    LTORG
+    END
+    
diff --git a/ports/cortex_m7/ac5/src/tx_thread_stack_build.s b/ports/cortex_m7/ac5/src/tx_thread_stack_build.s
new file mode 100644
index 00000000..d02c3df3
--- /dev/null
+++ b/ports/cortex_m7/ac5/src/tx_thread_stack_build.s
@@ -0,0 +1,143 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    AREA ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_stack_build                            Cortex-M7/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function builds a stack frame on the supplied thread's stack.  */
+;/*    The stack frame results in a fake interrupt return to the supplied  */
+;/*    function pointer.                                                   */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    thread_ptr                            Pointer to thread control blk */
+;/*    function_ptr                          Pointer to return function    */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_thread_create                     Create thread service         */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+;{
+    EXPORT  _tx_thread_stack_build
+_tx_thread_stack_build
+;
+;       
+;    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+;       on the Cortex-M7 should look like the following after it is built:
+;       
+;       Stack Top:      
+;                       LR          Interrupted LR (LR at time of PENDSV)
+;                       r4          Initial value for r4
+;                       r5          Initial value for r5
+;                       r6          Initial value for r6
+;                       r7          Initial value for r7
+;                       r8          Initial value for r8
+;                       r9          Initial value for r9
+;                       r10         Initial value for r10
+;                       r11         Initial value for r11
+;                       r0          Initial value for r0    (Hardware stack starts here!!)
+;                       r1          Initial value for r1
+;                       r2          Initial value for r2
+;                       r3          Initial value for r3
+;                       r12         Initial value for r12
+;                       lr          Initial value for lr
+;                       pc          Initial value for pc
+;                       xPSR        Initial value for xPSR
+;
+;    Stack Bottom: (higher memory address)  */
+;
+    LDR     r2, [r0, #16]                           ; Pickup end of stack area
+    BIC     r2, r2, #0x7                            ; Align frame for 8-byte alignment
+    SUB     r2, r2, #68                             ; Subtract frame size
+    LDR     r3, =0xFFFFFFFD                         ; Build initial LR value
+    STR     r3, [r2, #0]                            ; Save on the stack
+;
+;    /* Actually build the stack frame.  */
+;
+    MOV     r3, #0                                  ; Build initial register value
+    STR     r3, [r2, #4]                            ; Store initial r4
+    STR     r3, [r2, #8]                            ; Store initial r5
+    STR     r3, [r2, #12]                           ; Store initial r6
+    STR     r3, [r2, #16]                           ; Store initial r7
+    STR     r3, [r2, #20]                           ; Store initial r8
+    STR     r3, [r2, #24]                           ; Store initial r9
+    STR     r3, [r2, #28]                           ; Store initial r10
+    STR     r3, [r2, #32]                           ; Store initial r11
+;
+;    /* Hardware stack follows.  /
+;
+    STR     r3, [r2, #36]                           ; Store initial r0
+    STR     r3, [r2, #40]                           ; Store initial r1
+    STR     r3, [r2, #44]                           ; Store initial r2
+    STR     r3, [r2, #48]                           ; Store initial r3
+    STR     r3, [r2, #52]                           ; Store initial r12
+    MOV     r3, #0xFFFFFFFF                         ; Poison EXC_RETURN value
+    STR     r3, [r2, #56]                           ; Store initial lr
+    STR     r1, [r2, #60]                           ; Store initial pc
+    MOV     r3, #0x01000000                         ; Only T-bit need be set
+    STR     r3, [r2, #64]                           ; Store initial xPSR
+;
+;    /* Setup stack pointer.  */
+;    thread_ptr -> tx_thread_stack_ptr =  r2;
+;
+    STR     r2, [r0, #8]                            ; Save stack pointer in thread's
+                                                    ;   control block
+    BX      lr                                      ; Return to caller
+;}
+    END
+
diff --git a/ports/cortex_m7/ac5/src/tx_thread_system_return.s b/ports/cortex_m7/ac5/src/tx_thread_system_return.s
new file mode 100644
index 00000000..82daa084
--- /dev/null
+++ b/ports/cortex_m7/ac5/src/tx_thread_system_return.s
@@ -0,0 +1,96 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+;
+    AREA    ||.text||, CODE, READONLY
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_system_return                          Cortex-M7/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is target processor specific.  It is used to transfer */
+;/*    control from a thread back to the ThreadX system.  Only a           */
+;/*    minimal context is saved since the compiler assumes temp registers  */
+;/*    are going to get slicked by a function call anyway.                 */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_schedule                   Thread scheduling loop        */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ThreadX components                                                  */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_system_return(VOID)
+;{
+    EXPORT  _tx_thread_system_return
+_tx_thread_system_return
+;
+;    /* Return to real scheduler via PendSV. Note that this routine is often 
+;       replaced with in-line assembly in tx_port.h to improved performance.  */
+;     
+    MOV     r0, #0x10000000                         ; Load PENDSVSET bit
+    MOV     r1, #0xE000E000                         ; Load NVIC base
+    STR     r0, [r1, #0xD04]                        ; Set PENDSVBIT in ICSR
+    MRS     r0, IPSR                                ; Pickup IPSR
+    CMP     r0, #0                                  ; Is it a thread returning?
+    BNE     _isr_context                            ; If ISR, skip interrupt enable
+    MRS     r1, PRIMASK                             ; Thread context returning, pickup PRIMASK
+    CPSIE   i                                       ; Enable interrupts
+    MSR     PRIMASK, r1                             ; Restore original interrupt posture
+_isr_context
+    BX      lr                                      ; Return to caller 
+;}
+    END  
+    
diff --git a/ports/cortex_m7/ac5/src/tx_timer_interrupt.s b/ports/cortex_m7/ac5/src/tx_timer_interrupt.s
new file mode 100644
index 00000000..661e01e6
--- /dev/null
+++ b/ports/cortex_m7/ac5/src/tx_timer_interrupt.s
@@ -0,0 +1,271 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Timer                                                               */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_timer.h"
+;#include "tx_thread.h"
+;
+;
+;Define Assembly language external references...
+;
+    IMPORT      _tx_timer_time_slice
+    IMPORT      _tx_timer_system_clock
+    IMPORT      _tx_timer_current_ptr
+    IMPORT      _tx_timer_list_start
+    IMPORT      _tx_timer_list_end
+    IMPORT      _tx_timer_expired_time_slice
+    IMPORT      _tx_timer_expired
+    IMPORT      _tx_thread_time_slice
+    IMPORT      _tx_timer_expiration_process
+    IMPORT      _tx_thread_preempt_disable
+    IMPORT      _tx_thread_current_ptr
+    IMPORT      _tx_thread_execute_ptr
+;
+;
+    AREA ||.text||, CODE, READONLY
+    PRESERVE8
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_timer_interrupt                               Cortex-M7/AC5     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function processes the hardware timer interrupt.  This         */
+;/*    processing includes incrementing the system clock and checking for  */
+;/*    time slice and/or timer expiration.  If either is found, the        */
+;/*    interrupt context save/restore functions are called along with the  */
+;/*    expiration functions.                                               */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_timer_expiration_process          Timer expiration processing   */
+;/*    _tx_thread_time_slice                 Time slice interrupted thread */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    interrupt vector                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_timer_interrupt(VOID)
+;{
+    EXPORT  _tx_timer_interrupt
+_tx_timer_interrupt
+;
+;    /* Upon entry to this routine, it is assumed that context save has already
+;       been called, and therefore the compiler scratch registers are available
+;       for use.  */
+;
+;    /* Increment the system clock.  */
+;    _tx_timer_system_clock++;
+;
+    MOV32   r1, _tx_timer_system_clock              ; Pickup address of system clock
+    LDR     r0, [r1, #0]                            ; Pickup system clock
+    ADD     r0, r0, #1                              ; Increment system clock
+    STR     r0, [r1, #0]                            ; Store new system clock
+;
+;    /* Test for time-slice expiration.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    MOV32   r3, _tx_timer_time_slice                ; Pickup address of time-slice 
+    LDR     r2, [r3, #0]                            ; Pickup time-slice
+    CBZ     r2,  __tx_timer_no_time_slice           ; Is it non-active?
+                                                    ; Yes, skip time-slice processing
+;
+;       /* Decrement the time_slice.  */
+;       _tx_timer_time_slice--;
+;
+    SUB     r2, r2, #1                              ; Decrement the time-slice
+    STR     r2, [r3, #0]                            ; Store new time-slice value
+;
+;       /* Check for expiration.  */
+;       if (__tx_timer_time_slice == 0)
+;
+    CBNZ    r2, __tx_timer_no_time_slice            ; Has it expired?
+;
+;       /* Set the time-slice expired flag.  */
+;       _tx_timer_expired_time_slice =  TX_TRUE;
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup address of expired flag
+    MOV     r0, #1                                  ; Build expired value
+    STR     r0, [r3, #0]                            ; Set time-slice expiration flag
+;
+;    }
+;
+__tx_timer_no_time_slice
+;
+;    /* Test for timer expiration.  */
+;    if (*_tx_timer_current_ptr)
+;    {
+;
+    MOV32   r1, _tx_timer_current_ptr               ; Pickup current timer pointer address
+    LDR     r0, [r1, #0]                            ; Pickup current timer
+    LDR     r2, [r0, #0]                            ; Pickup timer list entry
+    CBZ     r2, __tx_timer_no_timer                 ; Is there anything in the list?
+                                                    ; No, just increment the timer
+;
+;        /* Set expiration flag.  */
+;        _tx_timer_expired =  TX_TRUE;
+;
+    MOV32   r3, _tx_timer_expired                   ; Pickup expiration flag address
+    MOV     r2, #1                                  ; Build expired value
+    STR     r2, [r3, #0]                            ; Set expired flag
+    B       __tx_timer_done                         ; Finished timer processing
+;
+;    }
+;    else
+;    {
+__tx_timer_no_timer
+;
+;        /* No timer expired, increment the timer pointer.  */
+;        _tx_timer_current_ptr++;
+;
+    ADD     r0, r0, #4                              ; Move to next timer
+;
+;        /* Check for wrap-around.  */
+;        if (_tx_timer_current_ptr == _tx_timer_list_end)
+;
+    MOV32   r3, _tx_timer_list_end                  ; Pickup addr of timer list end
+    LDR     r2, [r3, #0]                            ; Pickup list end
+    CMP     r0, r2                                  ; Are we at list end?
+    BNE     __tx_timer_skip_wrap                    ; No, skip wrap-around logic
+;
+;            /* Wrap to beginning of list.  */
+;            _tx_timer_current_ptr =  _tx_timer_list_start;
+;
+    MOV32   r3, _tx_timer_list_start                ; Pickup addr of timer list start
+    LDR     r0, [r3, #0]                            ; Set current pointer to list start
+;
+__tx_timer_skip_wrap
+;
+    STR     r0, [r1, #0]                            ; Store new current timer pointer
+;    }
+;
+__tx_timer_done
+;
+;
+;    /* See if anything has expired.  */
+;    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+;    {
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup addr of expired flag
+    LDR     r2, [r3, #0]                            ; Pickup time-slice expired flag
+    CBNZ    r2, __tx_something_expired              ; Did a time-slice expire?
+                                                    ; If non-zero, time-slice expired
+    MOV32   r1, _tx_timer_expired                   ; Pickup addr of other expired flag
+    LDR     r0, [r1, #0]                            ; Pickup timer expired flag
+    CBZ     r0, __tx_timer_nothing_expired          ; Did a timer expire?
+                                                    ; No, nothing expired
+;
+__tx_something_expired
+;
+;
+    STMDB   sp!, {r0, lr}                           ; Save the lr register on the stack
+                                                    ;   and save r0 just to keep 8-byte alignment
+;
+;    /* Did a timer expire?  */
+;    if (_tx_timer_expired)
+;    {
+;
+    MOV32   r1, _tx_timer_expired                   ; Pickup addr of expired flag
+    LDR     r0, [r1, #0]                            ; Pickup timer expired flag
+    CBZ     r0, __tx_timer_dont_activate            ; Check for timer expiration
+                                                    ; If not set, skip timer activation
+;
+;        /* Process timer expiration.  */
+;        _tx_timer_expiration_process();
+;
+    BL      _tx_timer_expiration_process            ; Call the timer expiration handling routine
+;
+;    }
+__tx_timer_dont_activate
+;
+;    /* Did time slice expire?  */
+;    if (_tx_timer_expired_time_slice)
+;    {
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup addr of time-slice expired 
+    LDR     r2, [r3, #0]                            ; Pickup the actual flag
+    CBZ     r2, __tx_timer_not_ts_expiration        ; See if the flag is set
+                                                    ; No, skip time-slice processing
+;
+;        /* Time slice interrupted thread.  */
+;        _tx_thread_time_slice(); 
+
+    BL      _tx_thread_time_slice                   ; Call time-slice processing
+    MOV32   r0, _tx_thread_preempt_disable          ; Build address of preempt disable flag
+    LDR     r1, [r0]                                ; Is the preempt disable flag set?
+    CBNZ    r1, __tx_timer_skip_time_slice          ; Yes, skip the PendSV logic
+    MOV32   r0, _tx_thread_current_ptr              ; Build current thread pointer address
+    LDR     r1, [r0]                                ; Pickup the current thread pointer
+    MOV32   r2, _tx_thread_execute_ptr              ; Build execute thread pointer address
+    LDR     r3, [r2]                                ; Pickup the execute thread pointer
+    MOV32   r0, 0xE000ED04                          ; Build address of control register
+    MOV32   r2, 0x10000000                          ; Build value for PendSV bit
+    CMP     r1, r3                                  ; Are they the same?
+    BEQ     __tx_timer_skip_time_slice              ; If the same, there was no time-slice performed
+    STR     r2, [r0]                                ; Not the same, issue the PendSV for preemption
+__tx_timer_skip_time_slice
+;
+;    }
+;
+__tx_timer_not_ts_expiration
+;
+    LDMIA   sp!, {r0, lr}                           ; Recover lr register (r0 is just there for
+;
+;    }
+;
+__tx_timer_nothing_expired
+
+    DSB                                             ; Complete all memory access
+    BX      lr                                      ; Return to caller
+;
+;}
+    ALIGN
+    LTORG
+    END
+
diff --git a/ports/cortex_m7/gnu/CMakeLists.txt b/ports/cortex_m7/gnu/CMakeLists.txt
index a361adf0..6a8d5852 100644
--- a/ports/cortex_m7/gnu/CMakeLists.txt
+++ b/ports/cortex_m7/gnu/CMakeLists.txt
@@ -8,7 +8,6 @@ target_sources(${PROJECT_NAME} PRIVATE
 	${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
 	${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
 	${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
-
     # {{END_TARGET_SOURCES}}
 )
 
diff --git a/ports/cortex_m7/gnu/example_build/build_threadx.bat b/ports/cortex_m7/gnu/example_build/build_threadx.bat
new file mode 100644
index 00000000..f0c995e7
--- /dev/null
+++ b/ports/cortex_m7/gnu/example_build/build_threadx.bat
@@ -0,0 +1,229 @@
+del tx.a
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb tx_initialize_low_level.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb ../src/tx_thread_stack_build.S
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+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c
+arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
+arm-none-eabi-ar -r tx.a tx_thread_interrupt_control.o tx_initialize_low_level.o
+arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
+arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
+arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
+arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
+arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
+arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
+arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
+arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
+arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
+arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o 
+arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
+arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
+arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
+arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
+arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
+arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
+arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
+arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
+arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
+arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
+arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o 
+arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
+arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
+arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o 
+arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o 
+arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o 
+arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
+arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
+arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
+arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
+arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o 
+arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
+arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o
diff --git a/ports/cortex_m7/gnu/example_build/build_threadx_sample.bat b/ports/cortex_m7/gnu/example_build/build_threadx_sample.bat
new file mode 100644
index 00000000..0e58e963
--- /dev/null
+++ b/ports/cortex_m7/gnu/example_build/build_threadx_sample.bat
@@ -0,0 +1,7 @@
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb tx_simulator_startup.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb cortexm7_crt0.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb tx_initialize_low_level.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-m7 -mthumb -I../../../../common/inc -I../inc sample_threadx.c
+arm-none-eabi-ld -A cortex-m7 -ereset_handler -T sample_threadx.ld tx_simulator_startup.o cortexm7_crt0.o tx_initialize_low_level.o sample_threadx.o tx.a  libc.a -o sample_threadx.out -M > sample_threadx.map
+
+
diff --git a/ports/cortex_m7/gnu/example_build/cortexm7_crt0.s b/ports/cortex_m7/gnu/example_build/cortexm7_crt0.s
new file mode 100644
index 00000000..d4cb1636
--- /dev/null
+++ b/ports/cortex_m7/gnu/example_build/cortexm7_crt0.s
@@ -0,0 +1,127 @@
+ .global _start
+  .extern main
+
+
+  .section .init, "ax"
+  .code 16
+  .align 2
+  .thumb_func
+
+
+_start:
+  CPSID   i
+  ldr r1, =__stack_end__
+  mov sp, r1
+
+
+  /* Copy initialised sections into RAM if required. */
+  ldr r0, =__data_load_start__
+  ldr r1, =__data_start__
+  ldr r2, =__data_end__
+  bl crt0_memory_copy
+  ldr r0, =__text_load_start__
+  ldr r1, =__text_start__
+  ldr r2, =__text_end__
+  bl crt0_memory_copy
+  ldr r0, =__fast_load_start__
+  ldr r1, =__fast_start__
+  ldr r2, =__fast_end__
+  bl crt0_memory_copy
+  ldr r0, =__ctors_load_start__
+  ldr r1, =__ctors_start__
+  ldr r2, =__ctors_end__
+  bl crt0_memory_copy
+  ldr r0, =__dtors_load_start__
+  ldr r1, =__dtors_start__
+  ldr r2, =__dtors_end__
+  bl crt0_memory_copy
+  ldr r0, =__rodata_load_start__
+  ldr r1, =__rodata_start__
+  ldr r2, =__rodata_end__
+  bl crt0_memory_copy
+
+
+  /* Zero bss. */
+  ldr r0, =__bss_start__
+  ldr r1, =__bss_end__
+  mov r2, #0
+  bl crt0_memory_set
+
+
+  /* Setup heap - not recommended for Threadx but here for compatibility reasons */
+  ldr r0, = __heap_start__
+  ldr r1, = __heap_end__
+  sub r1, r1, r0
+  mov r2, #0
+  str r2, [r0]
+  add r0, r0, #4
+  str r1, [r0]
+
+
+  /* constructors in case of using C++ */
+  ldr r0, =__ctors_start__
+  ldr r1, =__ctors_end__
+crt0_ctor_loop:
+  cmp r0, r1
+  beq crt0_ctor_end
+  ldr r2, [r0]
+  add r0, #4
+  push {r0-r1}  
+  blx r2
+  pop {r0-r1}
+  b crt0_ctor_loop
+crt0_ctor_end:
+
+
+  /* Setup call frame for main() */
+  mov r0, #0
+  mov lr, r0
+  mov r12, sp
+
+
+start:
+  /* Jump to main() */
+  mov r0, #0
+  mov r1, #0
+  ldr r2, =main
+  blx r2
+  /*  when main returns, loop forever. */
+crt0_exit_loop:
+  b crt0_exit_loop
+  
+
+
+  /* Startup helper functions. */
+
+
+crt0_memory_copy:
+  cmp r0, r1
+  beq memory_copy_done
+  sub r2, r2, r1
+  beq memory_copy_done
+memory_copy_loop:
+  ldrb r3, [r0]
+  add r0, r0, #1
+  strb r3, [r1]
+  add r1, r1, #1
+  sub r2, r2, #1
+  bne memory_copy_loop
+memory_copy_done:
+  bx lr
+
+
+crt0_memory_set:
+  cmp r0, r1
+  beq memory_set_done
+  strb r2, [r0]
+  add r0, r0, #1
+  b crt0_memory_set
+memory_set_done:
+  bx lr
+
+
+  /* Setup attibutes of stack and heap sections so they don't take up room in the elf file */
+  .section .stack, "wa", %nobits
+  .section .stack_process, "wa", %nobits
+  .section .heap, "wa", %nobits
+  
\ No newline at end of file
diff --git a/ports/cortex_m7/gnu/example_build/libc.a b/ports/cortex_m7/gnu/example_build/libc.a
new file mode 100644
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diff --git a/ports/cortex_m7/gnu/example_build/sample_threadx.c b/ports/cortex_m7/gnu/example_build/sample_threadx.c
new file mode 100644
index 00000000..597f373c
--- /dev/null
+++ b/ports/cortex_m7/gnu/example_build/sample_threadx.c
@@ -0,0 +1,370 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include "tx_api.h"
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_BYTE_POOL_SIZE     9120
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+UCHAR                   memory_area[DEMO_BYTE_POOL_SIZE];
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+/* Define main entry point.  */
+
+int main()
+{
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/cortex_m7/gnu/example_build/sample_threadx.ld b/ports/cortex_m7/gnu/example_build/sample_threadx.ld
new file mode 100644
index 00000000..28f203fd
--- /dev/null
+++ b/ports/cortex_m7/gnu/example_build/sample_threadx.ld
@@ -0,0 +1,206 @@
+MEMORY
+{
+  UNPLACED_SECTIONS (wx) : ORIGIN = 0x100000000, LENGTH = 0
+  CM3_System_Control_Space (wx) : ORIGIN = 0xe000e000, LENGTH = 0x00001000
+  AHB_Peripherals (wx) : ORIGIN = 0x50000000, LENGTH = 0x00200000
+  APB1_Peripherals (wx) : ORIGIN = 0x40080000, LENGTH = 0x00080000
+  APB0_Peripherals (wx) : ORIGIN = 0x40000000, LENGTH = 0x00080000
+  GPIO (wx) : ORIGIN = 0x2009c000, LENGTH = 0x00004000
+  AHBSRAM1 (wx) : ORIGIN = 0x20080000, LENGTH = 0x00004000
+  AHBSRAM0 (wx) : ORIGIN = 0x2007c000, LENGTH = 0x00004000
+  RAM (wx) : ORIGIN = 0x10000000, LENGTH = 0x00008000
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
+}
+
+
+SECTIONS
+{
+  __CM3_System_Control_Space_segment_start__ = 0xe000e000;
+  __CM3_System_Control_Space_segment_end__ = 0xe000f000;
+  __AHB_Peripherals_segment_start__ = 0x50000000;
+  __AHB_Peripherals_segment_end__ = 0x50200000;
+  __APB1_Peripherals_segment_start__ = 0x40080000;
+  __APB1_Peripherals_segment_end__ = 0x40100000;
+  __APB0_Peripherals_segment_start__ = 0x40000000;
+  __APB0_Peripherals_segment_end__ = 0x40080000;
+  __GPIO_segment_start__ = 0x2009c000;
+  __GPIO_segment_end__ = 0x200a0000;
+  __AHBSRAM1_segment_start__ = 0x20080000;
+  __AHBSRAM1_segment_end__ = 0x20084000;
+  __AHBSRAM0_segment_start__ = 0x2007c000;
+  __AHBSRAM0_segment_end__ = 0x20080000;
+  __RAM_segment_start__ = 0x10000000;
+  __RAM_segment_end__ = 0x10008000;
+  __FLASH_segment_start__ = 0x00000000;
+  __FLASH_segment_end__ = 0x00080000;
+
+  __STACKSIZE__ = 1024;
+  __STACKSIZE_PROCESS__ = 0;
+  __STACKSIZE_IRQ__ = 0;
+  __STACKSIZE_FIQ__ = 0;
+  __STACKSIZE_SVC__ = 0;
+  __STACKSIZE_ABT__ = 0;
+  __STACKSIZE_UND__ = 0;
+  __HEAPSIZE__ = 128;
+
+  __vectors_load_start__ = __FLASH_segment_start__;
+  .vectors __FLASH_segment_start__ : AT(__FLASH_segment_start__)
+  {
+    __vectors_start__ = .;
+    *(.vectors .vectors.*)
+  }
+  __vectors_end__ = __vectors_start__ + SIZEOF(.vectors);
+
+  . = ASSERT(__vectors_end__ >= __FLASH_segment_start__ && __vectors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .vectors is too large to fit in FLASH memory segment");
+
+  __init_load_start__ = ALIGN(__vectors_end__ , 4);
+  .init ALIGN(__vectors_end__ , 4) : AT(ALIGN(__vectors_end__ , 4))
+  {
+    __init_start__ = .;
+    *(.init .init.*)
+  }
+  __init_end__ = __init_start__ + SIZEOF(.init);
+
+  . = ASSERT(__init_end__ >= __FLASH_segment_start__ && __init_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .init is too large to fit in FLASH memory segment");
+
+  __text_load_start__ = ALIGN(__init_end__ , 4);
+  .text ALIGN(__init_end__ , 4) : AT(ALIGN(__init_end__ , 4))
+  {
+    __text_start__ = .;
+    *(.text .text.* .glue_7t .glue_7 .gnu.linkonce.t.* .gcc_except_table)
+  }
+  __text_end__ = __text_start__ + SIZEOF(.text);
+
+  . = ASSERT(__text_end__ >= __FLASH_segment_start__ && __text_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .text is too large to fit in FLASH memory segment");
+
+  __dtors_load_start__ = ALIGN(__text_end__ , 4);
+  .dtors ALIGN(__text_end__ , 4) : AT(ALIGN(__text_end__ , 4))
+  {
+    __dtors_start__ = .;
+    KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors))
+  }
+  __dtors_end__ = __dtors_start__ + SIZEOF(.dtors);
+
+  . = ASSERT(__dtors_end__ >= __FLASH_segment_start__ && __dtors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .dtors is too large to fit in FLASH memory segment");
+
+  __ctors_load_start__ = ALIGN(__dtors_end__ , 4);
+  .ctors ALIGN(__dtors_end__ , 4) : AT(ALIGN(__dtors_end__ , 4))
+  {
+    __ctors_start__ = .;
+    KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors))
+  }
+  __ctors_end__ = __ctors_start__ + SIZEOF(.ctors);
+
+  . = ASSERT(__ctors_end__ >= __FLASH_segment_start__ && __ctors_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .ctors is too large to fit in FLASH memory segment");
+
+  __rodata_load_start__ = ALIGN(__ctors_end__ , 4);
+  .rodata ALIGN(__ctors_end__ , 4) : AT(ALIGN(__ctors_end__ , 4))
+  {
+    __rodata_start__ = .;
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+  }
+  __rodata_end__ = __rodata_start__ + SIZEOF(.rodata);
+
+  . = ASSERT(__rodata_end__ >= __FLASH_segment_start__ && __rodata_end__ <= (__FLASH_segment_start__ + 0x00080000) , "error: .rodata is too large to fit in FLASH memory segment");
+
+  __fast_load_start__ = ALIGN(__rodata_end__ , 4);
+  .fast ALIGN(__RAM_segment_start__ , 4) : AT(ALIGN(__rodata_end__ , 4))
+  {
+    __fast_start__ = .;
+    *(.fast .fast.*)
+  }
+  __fast_end__ = __fast_start__ + SIZEOF(.fast);
+
+  __fast_load_end__ = __fast_load_start__ + SIZEOF(.fast);
+
+  . = ASSERT((__fast_load_start__ + SIZEOF(.fast)) >= __FLASH_segment_start__ && (__fast_load_start__ + SIZEOF(.fast)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .fast is too large to fit in FLASH memory segment");
+
+  .fast_run ALIGN(__RAM_segment_start__ , 4) (NOLOAD) :
+  {
+    __fast_run_start__ = .;
+    . = MAX(__fast_run_start__ + SIZEOF(.fast), .);
+  }
+  __fast_run_end__ = __fast_run_start__ + SIZEOF(.fast_run);
+
+  . = ASSERT(__fast_run_end__ >= __RAM_segment_start__ && __fast_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .fast_run is too large to fit in RAM memory segment");
+
+  __data_load_start__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4);
+  .data ALIGN(__fast_run_end__ , 4) : AT(ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4))
+  {
+    __data_start__ = .;
+    *(.data .data.* .gnu.linkonce.d.*)
+  }
+  __data_end__ = __data_start__ + SIZEOF(.data);
+
+  __data_load_end__ = __data_load_start__ + SIZEOF(.data);
+
+  __FLASH_segment_used_end__ = ALIGN(__fast_load_start__ + SIZEOF(.fast) , 4) + SIZEOF(.data);
+
+  . = ASSERT((__data_load_start__ + SIZEOF(.data)) >= __FLASH_segment_start__ && (__data_load_start__ + SIZEOF(.data)) <= (__FLASH_segment_start__ + 0x00080000) , "error: .data is too large to fit in FLASH memory segment");
+
+  .data_run ALIGN(__fast_run_end__ , 4) (NOLOAD) :
+  {
+    __data_run_start__ = .;
+    . = MAX(__data_run_start__ + SIZEOF(.data), .);
+  }
+  __data_run_end__ = __data_run_start__ + SIZEOF(.data_run);
+
+  . = ASSERT(__data_run_end__ >= __RAM_segment_start__ && __data_run_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .data_run is too large to fit in RAM memory segment");
+
+  __bss_load_start__ = ALIGN(__data_run_end__ , 4);
+  .bss ALIGN(__data_run_end__ , 4) (NOLOAD) : AT(ALIGN(__data_run_end__ , 4))
+  {
+    __bss_start__ = .;
+    *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON)
+  }
+  __bss_end__ = __bss_start__ + SIZEOF(.bss);
+
+  . = ASSERT(__bss_end__ >= __RAM_segment_start__ && __bss_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .bss is too large to fit in RAM memory segment");
+
+  __non_init_load_start__ = ALIGN(__bss_end__ , 4);
+  .non_init ALIGN(__bss_end__ , 4) (NOLOAD) : AT(ALIGN(__bss_end__ , 4))
+  {
+    __non_init_start__ = .;
+    *(.non_init .non_init.*)
+  }
+  __non_init_end__ = __non_init_start__ + SIZEOF(.non_init);
+
+  . = ASSERT(__non_init_end__ >= __RAM_segment_start__ && __non_init_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .non_init is too large to fit in RAM memory segment");
+
+  __heap_load_start__ = ALIGN(__non_init_end__ , 4);
+  .heap ALIGN(__non_init_end__ , 4) (NOLOAD) : AT(ALIGN(__non_init_end__ , 4))
+  {
+    __heap_start__ = .;
+    *(.heap)
+    . = ALIGN(MAX(__heap_start__ + __HEAPSIZE__ , .), 4);
+  }
+  __heap_end__ = __heap_start__ + SIZEOF(.heap);
+
+  . = ASSERT(__heap_end__ >= __RAM_segment_start__ && __heap_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .heap is too large to fit in RAM memory segment");
+
+  __stack_load_start__ = ALIGN(__heap_end__ , 4);
+  .stack ALIGN(__heap_end__ , 4) (NOLOAD) : AT(ALIGN(__heap_end__ , 4))
+  {
+    __stack_start__ = .;
+    *(.stack)
+    . = ALIGN(MAX(__stack_start__ + __STACKSIZE__ , .), 4);
+  }
+  __stack_end__ = __stack_start__ + SIZEOF(.stack);
+
+  . = ASSERT(__stack_end__ >= __RAM_segment_start__ && __stack_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack is too large to fit in RAM memory segment");
+
+  __stack_process_load_start__ = ALIGN(__stack_end__ , 4);
+  .stack_process ALIGN(__stack_end__ , 4) (NOLOAD) : AT(ALIGN(__stack_end__ , 4))
+  {
+    __stack_process_start__ = .;
+    *(.stack_process)
+    . = ALIGN(MAX(__stack_process_start__ + __STACKSIZE_PROCESS__ , .), 4);
+  }
+  __stack_process_end__ = __stack_process_start__ + SIZEOF(.stack_process);
+
+  __RAM_segment_used_end__ = ALIGN(__stack_end__ , 4) + SIZEOF(.stack_process);
+
+  . = ASSERT(__stack_process_end__ >= __RAM_segment_start__ && __stack_process_end__ <= (__RAM_segment_start__ + 0x00008000) , "error: .stack_process is too large to fit in RAM memory segment");
+
+}
+
diff --git a/ports/cortex_m7/gnu/src/tx_initialize_low_level_sample.S b/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S
old mode 100755
new mode 100644
similarity index 95%
rename from ports/cortex_m7/gnu/src/tx_initialize_low_level_sample.S
rename to ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S
index 1957867c..7b0e2100
--- a/ports/cortex_m7/gnu/src/tx_initialize_low_level_sample.S
+++ b/ports/cortex_m7/gnu/example_build/tx_initialize_low_level.S
@@ -59,7 +59,7 @@ SYSTICK_CYCLES    =   ((SYSTEM_CLOCK / 100) -1)
 @/*  FUNCTION                                               RELEASE        */
 @/*                                                                        */
 @/*    _tx_initialize_low_level                          Cortex-M7/GNU     */
-@/*                                                           6.0          */
+@/*                                                           6.0.1        */
 @/*  AUTHOR                                                                */
 @/*                                                                        */
 @/*    William E. Lamie, Microsoft Corporation                             */
@@ -93,6 +93,9 @@ SYSTICK_CYCLES    =   ((SYSTEM_CLOCK / 100) -1)
 @/*    DATE              NAME                      DESCRIPTION             */
 @/*                                                                        */
 @/*  05-19-2020     William E. Lamie         Initial Version 6.0           */
+@/*  06-30-2020     William E. Lamie         Modified Comment(s), fixed    */
+@/*                                            GNU assembly comment,       */
+@/*                                            resulting in version 6.0.1  */                        
 @/*                                                                        */
 @/**************************************************************************/
 @VOID   _tx_initialize_low_level(VOID)
@@ -191,14 +194,14 @@ __tx_IntHandler:
 @ {
     PUSH    {r0, lr}
 #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
-    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
 #endif       
 
 @    /* Do interrupt handler work here */
 @    /* BL .... */
 
 #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
-    BL      _tx_execution_isr_exit              ; Call the ISR exit function
+    BL      _tx_execution_isr_exit              @ Call the ISR exit function
 #endif
     POP     {r0, lr}
     BX      LR
@@ -216,11 +219,11 @@ SysTick_Handler:
 @
     PUSH    {r0, lr}
 #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
-    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
 #endif
     BL      _tx_timer_interrupt
 #ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
-    BL      _tx_execution_isr_exit              ; Call the ISR exit function
+    BL      _tx_execution_isr_exit              @ Call the ISR exit function
 #endif
     POP     {r0, lr}
     BX      LR
diff --git a/ports/cortex_m7/gnu/src/tx_vector_table_sample.S b/ports/cortex_m7/gnu/example_build/tx_simulator_startup.s
similarity index 100%
rename from ports/cortex_m7/gnu/src/tx_vector_table_sample.S
rename to ports/cortex_m7/gnu/example_build/tx_simulator_startup.s
diff --git a/ports/cortex_m7/gnu/readme_threadx.txt b/ports/cortex_m7/gnu/readme_threadx.txt
new file mode 100644
index 00000000..287d3481
--- /dev/null
+++ b/ports/cortex_m7/gnu/readme_threadx.txt
@@ -0,0 +1,151 @@
+                     Microsoft's Azure RTOS ThreadX for Cortex-M7 
+
+                              Using the GNU Tools
+
+1.  Building the ThreadX run-time Library
+
+First make sure you are in the "example_build" directory. Also, make sure that 
+you have setup your path and other environment variables necessary for the ARM 
+gnu (GNU) compiler. At this point you may run the build_threadx.bat batch file. 
+This will build the ThreadX run-time environment in the "example_build" 
+directory. 
+
+You should observe assembly and compilation of a series of ThreadX source 
+files. At the end of the batch file, they are all combined into the 
+run-time library file: tx.a. This file must be linked with your 
+application in order to use ThreadX.
+
+
+2.  Demonstration System for Cortex-M7
+
+The ThreadX demonstration is designed to execute on Cortex-M7 evaluation boards
+or on a dedicated simulator.
+
+Building the demonstration is easy, simply execute the build_threadx_sample.bat 
+batch file while inside the "example_build" directory. 
+
+You should observe the compilation of sample_threadx.c (which is the demonstration 
+application) and linking with tx.a. The resulting file sample_threadx.out is a binary 
+file that can be downloaded and executed on the a simulator, or downloaded to a board.
+
+
+3.  System Initialization
+
+The entry point in ThreadX for the Cortex-M7 using gnu tools uses the standard GNU 
+Cortex-M7 reset sequence. From the reset vector the C runtime will be initialized.
+
+The ThreadX tx_initialize_low_level.S file is responsible for setting up 
+various system data structures, the vector area, and a periodic timer interrupt 
+source. 
+
+In addition, _tx_initialize_low_level determines the first available 
+address for use by the application, which is supplied as the sole input 
+parameter to your application definition function, tx_application_define.
+
+
+4.  Register Usage and Stack Frames
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have the same stack frame in the Cortex-M7 version of
+ThreadX. The top of the suspended thread's stack is pointed to by 
+tx_thread_stack_ptr in the associated thread control block TX_THREAD.
+
+
+  Stack Offset     Stack Contents 
+
+     0x00               r4
+     0x04               r5
+     0x08               r6
+     0x0C               r7
+     0x10               r8
+     0x14               r9
+     0x18               r10
+     0x1C               r11
+     0x20               r0          (Hardware stack starts here!!)
+     0x24               r1
+     0x28               r2
+     0x2C               r3
+     0x30               r12
+     0x34               lr
+     0x38               pc
+     0x3C               xPSR
+
+
+5.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler optimizations. 
+This makes it easy to debug because you can trace or set breakpoints inside of 
+ThreadX itself. Of course, this costs some performance. To make it run faster, 
+you can change the build_threadx.bat file to remove the -g option and enable 
+all compiler optimizations. 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+6.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-M7
+targets. There are a certain set of requirements that are defined in the 
+following sub-sections:
+
+
+6.1  Vector Area
+
+The Cortex-M7 vectors start at the label __tx_vectors or similar. The application may modify
+the vector area according to its needs. There is code in tx_initialize_low_level() that will 
+configure the vector base register. 
+
+
+6.2 Managed Interrupts
+
+A ThreadX managed interrupt is defined below. By following these conventions, the 
+application ISR is then allowed access to various ThreadX services from the ISR.
+Here is the standard template for managed ISRs in ThreadX:
+
+
+        .global  __tx_IntHandler
+        .thumb_func
+__tx_IntHandler:
+; VOID InterruptHandler (VOID)
+; {
+        PUSH    {r0, lr}
+
+;    /* Do interrupt handler work here */
+;    /* BL  */
+
+        POP     {r0, lr}
+        BX      lr
+; }
+
+
+Note: the Cortex-M7 requires exception handlers to be thumb labels, this implies bit 0 set.
+To accomplish this, the declaration of the label has to be preceded by the assembler directive
+.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to 
+be inserted in the correct location in the interrupt vector table. This table is typically 
+located in either your runtime startup file or in the tx_initialize_low_level.S file.
+
+
+7. FPU Support
+
+ThreadX for Cortex-M7 supports automatic ("lazy") VFP support, which means that applications threads 
+can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread 
+context - no additional setup by the application.
+
+
+8.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+05/19/2020  Initial ThreadX 6.0 version for Cortex-M7 using GNU tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_m7/gnu/src/tx_thread_stack_build.S b/ports/cortex_m7/gnu/src/tx_thread_stack_build.S
index 19417731..8c4a6b7d 100755
--- a/ports/cortex_m7/gnu/src/tx_thread_stack_build.S
+++ b/ports/cortex_m7/gnu/src/tx_thread_stack_build.S
@@ -38,7 +38,7 @@
 @/*  FUNCTION                                               RELEASE        */
 @/*                                                                        */
 @/*    _tx_thread_stack_build                            Cortex-M7/GNU     */
-@/*                                                           6.0          */
+@/*                                                           6.0.1        */
 @/*  AUTHOR                                                                */
 @/*                                                                        */
 @/*    William E. Lamie, Microsoft Corporation                             */
@@ -71,6 +71,11 @@
 @/*    DATE              NAME                      DESCRIPTION             */
 @/*                                                                        */
 @/*  05-19-2020     William E. Lamie         Initial Version 6.0           */
+@/*  06-30-2020     William E. Lamie         Modified Comment(s), setting  */
+@/*                                             R10 to top of stack is not */
+@/*                                             needed. Removed references */
+@/*                                             to stack frame, resulting  */
+@/*                                             in version 6.0.1           */
 @/*                                                                        */
 @/**************************************************************************/
 @VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
@@ -91,7 +96,7 @@ _tx_thread_stack_build:
 @                       r7          Initial value for r7
 @                       r8          Initial value for r8
 @                       r9          Initial value for r9
-@                       r10 (sl)    Initial value for r10 (sl)
+@                       r10         Initial value for r10
 @                       r11         Initial value for r11
 @                       r0          Initial value for r0    (Hardware stack starts here!!)
 @                       r1          Initial value for r1
@@ -119,9 +124,7 @@ _tx_thread_stack_build:
     STR     r3, [r2, #16]                           @ Store initial r7
     STR     r3, [r2, #20]                           @ Store initial r8
     STR     r3, [r2, #24]                           @ Store initial r9
-    LDR     r3, [r0, #12]                           @ Pickup stack starting address
-    STR     r3, [r2, #28]                           @ Store initial r10 (sl)
-    MOV     r3, #0                                  @ Build initial register value
+    STR     r3, [r2, #28]                           @ Store initial r10
     STR     r3, [r2, #32]                           @ Store initial r11
 @
 @    /* Hardware stack follows.  */
diff --git a/ports/cortex_m7/iar/example_build/azure_rtos.eww b/ports/cortex_m7/iar/example_build/azure_rtos.eww
new file mode 100644
index 00000000..17e0d329
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/azure_rtos.eww
@@ -0,0 +1,13 @@
+
+
+
+  
+    $WS_DIR$\sample_threadx.ewp
+  
+  
+    $WS_DIR$\tx.ewp
+  
+  
+
+
+
diff --git a/ports/cortex_m7/iar/example_build/cstartup_M.s b/ports/cortex_m7/iar/example_build/cstartup_M.s
new file mode 100644
index 00000000..75d9369b
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/cstartup_M.s
@@ -0,0 +1,73 @@
+        EXTERN  __iar_program_start
+        PUBLIC  __vector_table
+
+        SECTION .text:CODE:REORDER(1)
+        
+        ;; Keep vector table even if it's not referenced
+        REQUIRE __vector_table
+        
+        THUMB
+        
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+        SECTION .intvec:CODE:NOROOT(2)
+        
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     __Reset_Vector
+
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemManage_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     DebugMon_Handler
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+
+        PUBWEAK NMI_Handler
+        PUBWEAK HardFault_Handler
+        PUBWEAK MemManage_Handler
+        PUBWEAK BusFault_Handler
+        PUBWEAK UsageFault_Handler
+        PUBWEAK SVC_Handler
+        PUBWEAK DebugMon_Handler
+        PUBWEAK PendSV_Handler
+        PUBWEAK SysTick_Handler
+
+        SECTION .text:CODE:REORDER:NOROOT(1)
+        THUMB
+__Reset_Vector:
+        CPSID   i                                       ; Disable interrupts
+        B        __iar_program_start
+
+
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+SVC_Handler
+DebugMon_Handler
+PendSV_Handler
+SysTick_Handler
+Default_Handler
+__default_handler
+        CALL_GRAPH_ROOT __default_handler, "interrupt"
+        NOCALL __default_handler
+        B __default_handler
+
+        END
diff --git a/ports/cortex_m7/iar/example_build/sample_threadx.c b/ports/cortex_m7/iar/example_build/sample_threadx.c
new file mode 100644
index 00000000..9a626828
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/sample_threadx.c
@@ -0,0 +1,381 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete
+   description of this demonstration.  */
+
+/* Optimize by disabling basic ThreadX error checking.  */
+#define TX_DISABLE_ERROR_CHECKING
+
+#include "tx_api.h"
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_BYTE_POOL_SIZE     9120
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define memory pool.  */
+
+UCHAR  memory_pool[DEMO_BYTE_POOL_SIZE];
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+/* Define main entry point.  */
+
+int main()
+{
+    
+    /* Please refer to Chapter 6 of the ThreadX User Guide for a complete
+       description of this demonstration.  */
+
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_pool, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/cortex_m7/iar/example_build/sample_threadx.dep b/ports/cortex_m7/iar/example_build/sample_threadx.dep
new file mode 100644
index 00000000..3e6a20f0
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/sample_threadx.dep
@@ -0,0 +1,113 @@
+
+
+    4
+    774047933
+    
+        Debug
+        
+            $PROJ_DIR$\Debug\Obj\sample_threadx.o
+            $TOOLKIT_DIR$\lib\rt7M_tl.a
+            $TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h
+            $PROJ_DIR$\sample_threadx.icf
+            $TOOLKIT_DIR$\inc\c\DLib_Defaults.h
+            $PROJ_DIR$\Debug\Obj\cstartup_M.o
+            $TOOLKIT_DIR$\inc\c\ycheck.h
+            $TOOLKIT_DIR$\inc\c\DLib_Product.h
+            $TOOLKIT_DIR$\inc\c\ysizet.h
+            $TOOLKIT_DIR$\inc\c\string.h
+            $PROJ_DIR$\Debug\Obj\tx_initialize_low_level.o
+            $TOOLKIT_DIR$\lib\shb_l.a
+            $PROJ_DIR$\Debug\Exe\sample_threadx.out
+            $PROJ_DIR$\Debug\Obj\sample_threadx.pbd
+            $TOOLKIT_DIR$\inc\c\yvals.h
+            $TOOLKIT_DIR$\inc\c\intrinsics.h
+            $TOOLKIT_DIR$\inc\c\DLib_Product_string.h
+            $PROJ_DIR$\Debug\Exe\tx.a
+            $TOOLKIT_DIR$\lib\m7M_tls.a
+            $TOOLKIT_DIR$\lib\dl7M_tln.a
+            $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h
+            $PROJ_DIR$\tx_initialize_low_level.s
+            $PROJ_DIR$\cstartup_M.s
+            $PROJ_DIR$\Debug\Obj\sample_threadx.xcl
+            $TOOLKIT_DIR$\inc\c\stdlib.h
+            $PROJ_DIR$\sample_threadx.c
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new file mode 100644
index 00000000..6f975a27
--- /dev/null
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diff --git a/ports/cortex_m7/iar/example_build/sample_threadx.ewp b/ports/cortex_m7/iar/example_build/sample_threadx.ewp
new file mode 100644
index 00000000..8c183b8f
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/sample_threadx.ewp
@@ -0,0 +1,2127 @@
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diff --git a/ports/cortex_m7/iar/example_build/sample_threadx.ewt b/ports/cortex_m7/iar/example_build/sample_threadx.ewt
new file mode 100644
index 00000000..24445b46
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/sample_threadx.ewt
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+                        
+                    
+                
+            
+        
+        
+            RuntimeChecking
+            0
+            
+                2
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+    
+    
+        $PROJ_DIR$\cstartup_M.s
+    
+    
+        $PROJ_DIR$\sample_threadx.c
+    
+    
+        $PROJ_DIR$\Debug\Exe\tx.a
+    
+    
+        $PROJ_DIR$\tx_initialize_low_level.s
+    
+
diff --git a/ports/cortex_m7/iar/example_build/sample_threadx.icf b/ports/cortex_m7/iar/example_build/sample_threadx.icf
new file mode 100644
index 00000000..246d387e
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/sample_threadx.icf
@@ -0,0 +1,42 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x0007FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x2001FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x200;
+define symbol __ICFEDIT_size_heap__     = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol FlashConfig_start__= 0x00000400;
+define symbol FlashConfig_end__  = 0x0000040f;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__ to (FlashConfig_start__ - 1)] | [from (FlashConfig_end__+1)  to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+define region FlashConfig_region = mem:[from FlashConfig_start__ to FlashConfig_end__];
+
+initialize by copy { readwrite };
+initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+
+place in FlashConfig_region
+                      {section FlashConfig};
+
+place in RAM_region { last section FREE_MEM};
+
diff --git a/ports/cortex_m7/iar/example_build/settings/azure_rtos.wsdt b/ports/cortex_m7/iar/example_build/settings/azure_rtos.wsdt
new file mode 100644
index 00000000..85a9832f
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/azure_rtos.wsdt
@@ -0,0 +1,535 @@
+
+
+    
+        
+            sample_threadx/Debug
+            tx/Debug
+        
+        sample_threadx
+        1
+    
+    
+        
+            
+                21
+                2518
+                2
+                
+                0
+                -1
+            
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+                
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+                
+                    286
+                    30
+                    30
+                    30
+                
+                
+                    <ws>
+                
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+                020000000A00259600000100000010860000090000000C81000002000000048600000100000000810000010000000E81000001000000118600000900000046810000020000000D81000001000000E880000001000000
+            
+            
+                0A000D8400000F84000008840000FFFFFFFF54840000328100001C810000098400000E84000030840000
+                0400048400004C000000068400004E0000000B8100001B0000000D8100001D000000
+            
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+                0A0000000A0000006E0000006E000000
+                000000004E050000000A000061050000
+                4096
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+                34051
+                000000001700000022010000C8000000
+                000000000000000022010000B1000000
+                32768
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+                0000000062040000000A000065050000
+                000000004B040000000A00004E050000
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+                000000001700000022010000C8000000
+                0400000063040000FC09000034050000
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diff --git a/ports/cortex_m7/iar/example_build/settings/sample_threadx.Debug.cspy.bat b/ports/cortex_m7/iar/example_build/settings/sample_threadx.Debug.cspy.bat
new file mode 100644
index 00000000..f5c060f6
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/sample_threadx.Debug.cspy.bat
@@ -0,0 +1,40 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+@echo off 
+
+if not "%~1" == "" goto debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m7\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m7\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m7\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m7\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+
+@echo off 
+:end
\ No newline at end of file
diff --git a/ports/cortex_m7/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports/cortex_m7/iar/example_build/settings/sample_threadx.Debug.cspy.ps1
new file mode 100644
index 00000000..9fc15b26
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/sample_threadx.Debug.cspy.ps1
@@ -0,0 +1,31 @@
+param([String]$debugfile = "");
+
+# This powershell file has been generated by the IAR Embedded Workbench
+# C - SPY Debugger, as an aid to preparing a command line for running
+# the cspybat command line utility using the appropriate settings.
+#
+# Note that this file is generated every time a new debug session
+# is initialized, so you may want to move or rename the file before
+# making changes.
+#
+# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
+# by the name of the debug file (usually an ELF / DWARF or UBROF file).
+#
+# Read about available command line parameters in the C - SPY Debugging
+# Guide. Hints about additional command line parameters that may be
+# useful in specific cases :
+#   --download_only   Downloads a code image without starting a debug
+#                     session afterwards.
+#   --silent          Omits the sign - on message.
+#   --timeout         Limits the maximum allowed execution time.
+#
+
+
+if ($debugfile -eq "")
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m7\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m7\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+}
+else
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m7\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m7\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+}
diff --git a/ports/cortex_m7/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports/cortex_m7/iar/example_build/settings/sample_threadx.Debug.driver.xcl
new file mode 100644
index 00000000..c0ab94e4
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/sample_threadx.Debug.driver.xcl
@@ -0,0 +1,13 @@
+"--endian=little" 
+
+"--cpu=Cortex-M7" 
+
+"--fpu=VFPv5_SP" 
+
+"--semihosting" 
+
+"--multicore_nr_of_cores=1" 
+
+
+
+
diff --git a/ports/cortex_m7/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports/cortex_m7/iar/example_build/settings/sample_threadx.Debug.general.xcl
new file mode 100644
index 00000000..db2ac682
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/sample_threadx.Debug.general.xcl
@@ -0,0 +1,11 @@
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" 
+
+"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_m7\iar\example_build\Debug\Exe\sample_threadx.out" 
+
+--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" 
+
+
+
+
diff --git a/ports/cortex_m7/iar/example_build/settings/sample_threadx.crun b/ports/cortex_m7/iar/example_build/settings/sample_threadx.crun
new file mode 100644
index 00000000..d71ea555
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/sample_threadx.crun
@@ -0,0 +1,13 @@
+
+
+    1
+    
+        
+            *
+            *
+            *
+            0
+            1
+        
+    
+
diff --git a/ports/cortex_m7/iar/example_build/settings/sample_threadx.dbgdt b/ports/cortex_m7/iar/example_build/settings/sample_threadx.dbgdt
new file mode 100644
index 00000000..40bc8d5f
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/sample_threadx.dbgdt
@@ -0,0 +1,1356 @@
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+            
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+                00200000010000002100FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000064000000FFFEFF000000000000000000000000000100000001000000018001E100000000000065000000FFFEFF000000000000000000000000000100000001000000018003E100000000000067000000FFFEFF0000000000000000000000000001000000010000000180008100000000000048000000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF000000000000000000000000000100000001000000018007E10000000000006A000000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF000000000000000000000000000100000001000000018023E10000000004006C000000FFFEFF000000000000000000000000000100000001000000018022E10000000004006B000000FFFEFF000000000000000000000000000100000001000000018025E10000000000006E000000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF00000000000000000000000000010000000100000001802BE100000000040071000000FFFEFF00000000000000000000000000010000000100000001802CE100000000040072000000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF000000000000000000000000000100000001000000FFFF01000D005061737465436F6D626F426F784281000000000000FFFFFFFFFFFEFF0000000000000000000100000000000000010000007800000002002050FFFFFFFFFFFEFF0096000000000000000000018021810000000004005B000000FFFEFF000000000000000000000000000100000001000000018024E10000000000006D000000FFFEFF000000000000000000000000000100000001000000018028E10000000004006F000000FFFEFF000000000000000000000000000100000001000000018029E100000000000070000000FFFEFF000000000000000000000000000100000001000000018002810000000000004A000000FFFEFF000000000000000000000000000100000001000000018029810000000000005F000000FFFEFF000000000000000000000000000100000001000000018027810000000000005D000000FFFEFF000000000000000000000000000100000001000000018028810000000000005E000000FFFEFF00000000000000000000000000010000000100000001801D8100000000040057000000FFFEFF00000000000000000000000000010000000100000001801E8100000000040058000000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF00000000000000000000000000010000000100000001800B810000000004004E000000FFFEFF00000000000000000000000000010000000100000001800C810000000000004F000000FFFEFF00000000000000000000000000010000000100000001805F8600000000000063000000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF00000000000000000000000000010000000100000001801F8100000000000059000000FFFEFF000000000000000000000000000100000001000000018020810000000000005A000000FFFEFF0000000000000000000000000001000000010000000180468100000000020061000000FFFEFF00000000000000000000000000010000000100000000000000FFFEFF044D00610069006E00FF7F0000
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+    
+
diff --git a/ports/cortex_m7/iar/example_build/settings/sample_threadx.dnx b/ports/cortex_m7/iar/example_build/settings/sample_threadx.dnx
new file mode 100644
index 00000000..7ae81233
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/sample_threadx.dnx
@@ -0,0 +1,99 @@
+
+
+    
+        0
+        1
+        90
+        1
+        1
+        1
+        main
+        0
+        50
+    
+    
+        0
+        1
+    
+    
+        4108083456
+    
+    
+        0
+    
+    
+        _ 0
+        _ 0
+    
+    
+        0
+    
+    
+        0
+        0
+        0
+    
+    
+        0
+        1
+        0
+        0
+    
+    
+        0
+    
+    
+        1
+    
+    
+        _ 0
+        _ ""
+    
+    
+        _ 0
+        _ ""
+        _ 0
+    
+    
+        0
+        0
+        1
+        0
+        1
+        0
+    
+    
+        0
+        0
+        1
+        0
+        1
+    
+    
+        0
+    
+    
+        0
+    
+    
+        1
+        _ 0 9999 0 9999 1 0 0 100 0 1 "SysTick 1 0x3C"
+        1
+    
+    
+        1
+        0
+        1
+        0
+        1
+    
+    
+        0
+        0
+    
+    
+        10000000
+        0
+        1
+    
+
diff --git a/ports/cortex_m7/iar/example_build/settings/tx.Debug.cspy.bat b/ports/cortex_m7/iar/example_build/settings/tx.Debug.cspy.bat
new file mode 100644
index 00000000..d76cfad9
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/tx.Debug.cspy.bat
@@ -0,0 +1,40 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+@echo off 
+
+if not "%~1" == "" goto debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+
+@echo off 
+:end
\ No newline at end of file
diff --git a/ports/cortex_m7/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports/cortex_m7/iar/example_build/settings/tx.Debug.cspy.ps1
new file mode 100644
index 00000000..1c1ba13b
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/tx.Debug.cspy.ps1
@@ -0,0 +1,31 @@
+param([String]$debugfile = "");
+
+# This powershell file has been generated by the IAR Embedded Workbench
+# C - SPY Debugger, as an aid to preparing a command line for running
+# the cspybat command line utility using the appropriate settings.
+#
+# Note that this file is generated every time a new debug session
+# is initialized, so you may want to move or rename the file before
+# making changes.
+#
+# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
+# by the name of the debug file (usually an ELF / DWARF or UBROF file).
+#
+# Read about available command line parameters in the C - SPY Debugging
+# Guide. Hints about additional command line parameters that may be
+# useful in specific cases :
+#   --download_only   Downloads a code image without starting a debug
+#                     session afterwards.
+#   --silent          Omits the sign - on message.
+#   --timeout         Limits the maximum allowed execution time.
+#
+
+
+if ($debugfile -eq "")
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+}
+else
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+}
diff --git a/ports/cortex_m7/iar/example_build/settings/tx.Debug.driver.xcl b/ports/cortex_m7/iar/example_build/settings/tx.Debug.driver.xcl
new file mode 100644
index 00000000..b5f366cc
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/tx.Debug.driver.xcl
@@ -0,0 +1,13 @@
+"--endian=little" 
+
+"--cpu=Cortex-M7" 
+
+"--fpu=None" 
+
+"--semihosting" 
+
+"--multicore_nr_of_cores=1" 
+
+
+
+
diff --git a/ports/cortex_m7/iar/example_build/settings/tx.Debug.general.xcl b/ports/cortex_m7/iar/example_build/settings/tx.Debug.general.xcl
new file mode 100644
index 00000000..ef6d6dd5
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/tx.Debug.general.xcl
@@ -0,0 +1,11 @@
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armproc.dll" 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armsim2.dll" 
+
+"C:\release\threadx\Debug\Exe\tx.out" 
+
+--plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armbat.dll" 
+
+
+
+
diff --git a/ports/cortex_m7/iar/example_build/settings/tx.crun b/ports/cortex_m7/iar/example_build/settings/tx.crun
new file mode 100644
index 00000000..d71ea555
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/tx.crun
@@ -0,0 +1,13 @@
+
+
+    1
+    
+        
+            *
+            *
+            *
+            0
+            1
+        
+    
+
diff --git a/ports/cortex_m7/iar/example_build/settings/tx.dbgdt b/ports/cortex_m7/iar/example_build/settings/tx.dbgdt
new file mode 100644
index 00000000..73e71f6e
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/tx.dbgdt
@@ -0,0 +1,4 @@
+
+
+    
+
diff --git a/ports/cortex_m7/iar/example_build/settings/tx.dnx b/ports/cortex_m7/iar/example_build/settings/tx.dnx
new file mode 100644
index 00000000..1872e83f
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/settings/tx.dnx
@@ -0,0 +1,58 @@
+
+
+    
+        0
+        0
+        1
+        0
+        1
+        0
+    
+    
+        0
+        0
+        1
+        0
+        1
+    
+    
+        0
+        1
+        90
+        1
+        1
+        1
+        main
+        0
+        50
+    
+    
+        0
+    
+    
+        0
+    
+    
+        1
+    
+    
+        1
+        0
+        1
+        0
+        1
+    
+    
+        0
+        1
+    
+    
+        0
+        0
+    
+    
+        10000000
+        0
+        1
+    
+
diff --git a/ports/cortex_m7/iar/example_build/tx.dep b/ports/cortex_m7/iar/example_build/tx.dep
new file mode 100644
index 00000000..30b4e270
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/tx.dep
@@ -0,0 +1,8055 @@
+
+
+    4
+    851124999
+    
+        Debug
+        
+            $PROJ_DIR$\tx_block_release.c
+            $PROJ_DIR$\tx_block_pool_cleanup.c
+            $PROJ_DIR$\tx_block_pool_info_get.c
+            $PROJ_DIR$\tx_block_pool.h
+            $PROJ_DIR$\tx_block_allocate.c
+            $PROJ_DIR$\tx_block_pool_create.c
+            $PROJ_DIR$\tx_block_pool_initialize.c
+            $PROJ_DIR$\tx_block_pool_performance_info_get.c
+            $PROJ_DIR$\tx_api.h
+            $PROJ_DIR$\tx_block_pool_delete.c
+            $PROJ_DIR$\tx_block_pool_performance_system_info_get.c
+            $PROJ_DIR$\tx_block_pool_prioritize.c
+            $PROJ_DIR$\Debug\Obj\tx_queue_front_send.o
+            $PROJ_DIR$\Debug\Obj\tx_byte_pool_delete.pbi
+            $PROJ_DIR$\Debug\Obj\tx_thread_priority_change.pbi
+            $PROJ_DIR$\Debug\Obj\tx_thread_timeout.o
+            $PROJ_DIR$\Debug\Obj\txe_mutex_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_byte_pool_create.pbi
+            $PROJ_DIR$\Debug\Obj\tx_block_release.pbi
+            $PROJ_DIR$\Debug\Obj\tx_thread_priority_change.o
+            $PROJ_DIR$\Debug\Obj\tx_mutex_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_timer_expiration_process.o
+            $PROJ_DIR$\Debug\Obj\txe_timer_delete.pbi
+            $PROJ_DIR$\Debug\Obj\tx_timer_interrupt.o
+            $PROJ_DIR$\Debug\Obj\tx_block_pool_prioritize.pbi
+            $PROJ_DIR$\Debug\Obj\tx_timer_system_activate.pbi
+            $PROJ_DIR$\Debug\Obj\tx_semaphore_put.pbi
+            $PROJ_DIR$\Debug\Obj\txe_queue_send_notify.pbi
+            $PROJ_DIR$\Debug\Obj\txe_thread_suspend.pbi
+            $PROJ_DIR$\Debug\Obj\tx_timer_create.pbi
+            $PROJ_DIR$\Debug\Obj\tx_timer_system_deactivate.pbi
+            $PROJ_DIR$\Debug\Obj\txe_thread_delete.pbi
+            $PROJ_DIR$\Debug\Obj\tx_timer_activate.o
+            $PROJ_DIR$\Debug\Obj\txe_queue_send.pbi
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\txe_queue_info_get.o
+            $PROJ_DIR$\Debug\Obj\tx_thread_resume.o
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_delete.o
+            $PROJ_DIR$\Debug\Obj\tx_thread_sleep.o
+            $PROJ_DIR$\Debug\Obj\tx_block_pool_performance_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_semaphore_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_mutex_initialize.o
+            $PROJ_DIR$\Debug\Obj\tx_trace_initialize.o
+            $PROJ_DIR$\Debug\Obj\tx_thread_stack_analyze.pbi
+            $PROJ_DIR$\Debug\Obj\tx_byte_pool_initialize.o
+            $PROJ_DIR$\Debug\Obj\txe_mutex_info_get.o
+            $PROJ_DIR$\Debug\Obj\txe_semaphore_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_timer_deactivate.o
+            $PROJ_DIR$\Debug\Obj\tx_initialize_high_level.pbi
+            $PROJ_DIR$\Debug\Obj\tx_timer_initialize.o
+            $PROJ_DIR$\Debug\Obj\txe_block_release.pbi
+            $PROJ_DIR$\Debug\Obj\tx_trace_event_unfilter.pbi
+            $PROJ_DIR$\Debug\Obj\tx_block_pool_cleanup.pbi
+            $PROJ_DIR$\Debug\Obj\txe_semaphore_create.pbi
+            $PROJ_DIR$\Debug\Obj\tx_mutex_info_get.o
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_delete.pbi
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_set.pbi
+            $PROJ_DIR$\Debug\Obj\tx_thread_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_byte_release.o
+            $PROJ_DIR$\Debug\Obj\tx_mutex_prioritize.pbi
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_performance_system_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_iar.pbi
+            $PROJ_DIR$\Debug\Obj\tx_byte_pool_search.pbi
+            $PROJ_DIR$\Debug\Obj\tx_thread_context_restore.o
+            $PROJ_DIR$\Debug\Obj\txe_mutex_delete.o
+            $PROJ_DIR$\Debug\Obj\tx_semaphore_info_get.o
+            $PROJ_DIR$\Debug\Obj\tx_thread_timeout.pbi
+            $PROJ_DIR$\Debug\Obj\txe_byte_pool_delete.o
+            $PROJ_DIR$\Debug\Obj\tx_initialize_high_level.o
+            $PROJ_DIR$\Debug\Obj\tx_byte_allocate.pbi
+            $PROJ_DIR$\Debug\Obj\tx_mutex_performance_info_get.o
+            $PROJ_DIR$\Debug\Obj\tx_timer_system_deactivate.o
+            $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_create.o
+            $PROJ_DIR$\Debug\Obj\tx_iar.o
+            $PROJ_DIR$\Debug\Obj\tx_trace_buffer_full_notify.o
+            $PROJ_DIR$\Debug\Obj\tx_byte_pool_performance_system_info_get.o
+            $PROJ_DIR$\Debug\Obj\tx_mutex_prioritize.o
+            $PROJ_DIR$\Debug\Obj\txe_byte_pool_prioritize.o
+            $PROJ_DIR$\Debug\Obj\tx_trace_user_event_insert.pbi
+            $PROJ_DIR$\Debug\Obj\txe_thread_suspend.o
+            $PROJ_DIR$\Debug\Obj\tx_semaphore_prioritize.pbi
+            $PROJ_DIR$\Debug\Obj\tx_trace_disable.pbi
+            $PROJ_DIR$\Debug\Obj\txe_queue_receive.pbi
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_info_get.o
+            $PROJ_DIR$\Debug\Obj\tx_trace_isr_exit_insert.pbi
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_cleanup.o
+            $PROJ_DIR$\Debug\Obj\tx_trace_buffer_full_notify.pbi
+            $PROJ_DIR$\Debug\Obj\tx_thread_relinquish.o
+            $PROJ_DIR$\Debug\Obj\txe_timer_info_get.o
+            $PROJ_DIR$\Debug\Obj\tx_thread_shell_entry.pbi
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_cleanup.pbi
+            $PROJ_DIR$\Debug\Obj\txe_block_pool_prioritize.o
+            $PROJ_DIR$\Debug\Obj\txe_block_allocate.pbi
+            $PROJ_DIR$\Debug\Obj\tx_thread_interrupt_control.o
+            $PROJ_DIR$\Debug\Obj\tx_semaphore_ceiling_put.pbi
+            $PROJ_DIR$\Debug\Obj\tx_block_pool_create.pbi
+            $PROJ_DIR$\Debug\Obj\tx_trace_interrupt_control.pbi
+            $PROJ_DIR$\Debug\Obj\txe_mutex_put.pbi
+            $PROJ_DIR$\Debug\Obj\tx_semaphore_performance_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_queue_front_send.pbi
+            $PROJ_DIR$\Debug\Obj\txe_byte_allocate.pbi
+            $PROJ_DIR$\Debug\Obj\tx_semaphore_get.pbi
+            $PROJ_DIR$\Debug\Obj\txe_semaphore_delete.pbi
+            $PROJ_DIR$\Debug\Obj\tx_time_set.pbi
+            $PROJ_DIR$\Debug\Obj\txe_block_pool_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_mutex_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_thread_system_return.o
+            $PROJ_DIR$\Debug\Obj\tx_queue_performance_system_info_get.o
+            $PROJ_DIR$\Debug\Obj\tx_byte_pool_initialize.pbi
+            $PROJ_DIR$\Debug\Obj\txe_byte_release.o
+            $PROJ_DIR$\Debug\Obj\tx_byte_pool_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_thread_system_preempt_check.o
+            $PROJ_DIR$\Debug\Obj\tx_thread_system_suspend.pbi
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_delete.pbi
+            $PROJ_DIR$\Debug\Obj\tx_queue_initialize.pbi
+            $PROJ_DIR$\Debug\Obj\tx_timer_initialize.pbi
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_timer_deactivate.pbi
+            $PROJ_DIR$\Debug\Obj\txe_thread_relinquish.pbi
+            $PROJ_DIR$\Debug\Exe\tx.a
+            $PROJ_DIR$\Debug\Obj\txe_byte_pool_info_get.o
+            $PROJ_DIR$\Debug\Obj\tx_semaphore_performance_system_info_get.o
+            $PROJ_DIR$\Debug\Obj\tx_mutex_cleanup.pbi
+            $PROJ_DIR$\Debug\Obj\txe_queue_flush.o
+            $PROJ_DIR$\Debug\Obj\txe_thread_entry_exit_notify.pbi
+            $PROJ_DIR$\Debug\Obj\tx_trace_isr_enter_insert.o
+            $PROJ_DIR$\Debug\Obj\tx_queue_create.o
+            $PROJ_DIR$\Debug\Obj\txe_semaphore_create.o
+            $PROJ_DIR$\Debug\Obj\tx.pbd
+            $PROJ_DIR$\Debug\Obj\tx_thread_initialize.o
+            $PROJ_DIR$\Debug\Obj\txe_timer_create.pbi
+            $PROJ_DIR$\Debug\Obj\tx_queue_initialize.o
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new file mode 100644
index 00000000..5bb89d18
--- /dev/null
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new file mode 100644
index 00000000..1bb260e3
--- /dev/null
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+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_buffer_full_notify.c
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+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_disable.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_enable.c
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+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_filter.c
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+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_unfilter.c
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+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_initialize.c
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+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_interrupt_control.c
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+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_enter_insert.c
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+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_exit_insert.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_register.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_unregister.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_user_event_insert.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_allocate.c
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+        
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_reset.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_resume.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_suspend.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_terminate.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_time_slice_change.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c
+        
+    
+
diff --git a/ports/cortex_m7/iar/example_build/tx.ewt b/ports/cortex_m7/iar/example_build/tx.ewt
new file mode 100644
index 00000000..b13c96f7
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/tx.ewt
@@ -0,0 +1,3403 @@
+
+
+    3
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+        Debug
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+            ARM
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+        1
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+            C-STAT
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+                263
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+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_relinquish.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_reset.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_resume.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_schedule.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_shell_entry.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_sleep.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_analyze.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_stack_build.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_error_handler.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_error_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_suspend.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_preempt_check.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_resume.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_system_return.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_suspend.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_terminate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_time_slice.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_time_slice_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_timeout.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_wait_abort.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_time_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_time_set.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_activate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_deactivate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_expiration_process.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_initialize.c
+        
+        
+            $PROJ_DIR$\..\src\tx_timer_interrupt.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_performance_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_performance_system_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_system_activate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_system_deactivate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_thread_entry.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_buffer_full_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_disable.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_enable.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_filter.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_unfilter.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_initialize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_interrupt_control.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_enter_insert.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_exit_insert.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_register.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_unregister.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_user_event_insert.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_allocate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_release.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_allocate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_release.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_flush.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_front_send.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_receive.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_ceiling_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_entry_exit_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_preemption_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_priority_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_relinquish.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_reset.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_resume.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_suspend.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_terminate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_time_slice_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c
+        
+    
+
diff --git a/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s b/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s
new file mode 100644
index 00000000..bcf8d4b1
--- /dev/null
+++ b/ports/cortex_m7/iar/example_build/tx_initialize_low_level.s
@@ -0,0 +1,177 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Initialize                                                          */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_initialize.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+        EXTERN  _tx_thread_system_stack_ptr
+        EXTERN  _tx_initialize_unused_memory
+        EXTERN  _tx_timer_interrupt
+        EXTERN  __vector_table
+        EXTERN  _tx_execution_isr_enter
+        EXTERN  _tx_execution_isr_exit
+;
+;
+SYSTEM_CLOCK      EQU   25000000
+SYSTICK_CYCLES    EQU   ((SYSTEM_CLOCK / 100) -1)
+        
+    RSEG    FREE_MEM:DATA
+    PUBLIC  __tx_free_memory_start
+__tx_free_memory_start
+    DS32    4        
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_initialize_low_level                          Cortex-M7/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for any low-level processor            */
+;/*    initialization, including setting up interrupt vectors, setting     */
+;/*    up a periodic timer interrupt source, saving the system stack       */
+;/*    pointer for use in ISR processing later, and finding the first      */
+;/*    available RAM memory address for tx_application_define.             */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_initialize_low_level(VOID)
+;{
+    PUBLIC  _tx_initialize_low_level
+_tx_initialize_low_level:
+;       
+;    /* Ensure that interrupts are disabled.  */
+;
+    CPSID   i                                       ; Disable interrupts
+;
+;
+;    /* Set base of available memory to end of non-initialised RAM area.  */
+;     
+    LDR     r0, =__tx_free_memory_start             ; Get end of non-initialized RAM area
+    LDR     r2, =_tx_initialize_unused_memory       ; Build address of unused memory pointer
+    STR     r0, [r2, #0]                            ; Save first free memory address
+;
+;    /* Enable the cycle count register.  */
+;
+    LDR     r0, =0xE0001000                         ; Build address of DWT register
+    LDR     r1, [r0]                                ; Pickup the current value
+    ORR     r1, r1, #1                              ; Set the CYCCNTENA bit
+    STR     r1, [r0]                                ; Enable the cycle count register 
+;
+;    /* Setup Vector Table Offset Register.  */
+;    
+    MOV     r0, #0xE000E000                         ; Build address of NVIC registers
+    LDR     r1, =__vector_table                     ; Pickup address of vector table
+    STR     r1, [r0, #0xD08]                        ; Set vector table address   
+;
+;    /* Set system stack pointer from vector value.  */
+;
+    LDR     r0, =_tx_thread_system_stack_ptr        ; Build address of system stack pointer
+    LDR     r1, =__vector_table                     ; Pickup address of vector table
+    LDR     r1, [r1]                                ; Pickup reset stack pointer
+    STR     r1, [r0]                                ; Save system stack pointer
+;
+;    /* Configure SysTick.  */
+;
+    MOV     r0, #0xE000E000                         ; Build address of NVIC registers
+    LDR     r1, =SYSTICK_CYCLES
+    STR     r1, [r0, #0x14]                         ; Setup SysTick Reload Value
+    MOV     r1, #0x7                                ; Build SysTick Control Enable Value
+    STR     r1, [r0, #0x10]                         ; Setup SysTick Control
+;
+;    /* Configure handler priorities.  */
+;
+    LDR     r1, =0x00000000                         ; Rsrv, UsgF, BusF, MemM
+    STR     r1, [r0, #0xD18]                        ; Setup System Handlers 4-7 Priority Registers
+
+    LDR     r1, =0xFF000000                         ; SVCl, Rsrv, Rsrv, Rsrv
+    STR     r1, [r0, #0xD1C]                        ; Setup System Handlers 8-11 Priority Registers
+                                                    ; Note: SVC must be lowest priority, which is 0xFF
+
+    LDR     r1, =0x40FF0000                         ; SysT, PnSV, Rsrv, DbgM
+    STR     r1, [r0, #0xD20]                        ; Setup System Handlers 12-15 Priority Registers
+                                                    ; Note: PnSV must be lowest priority, which is 0xFF
+;
+;    /* Return to caller.  */
+;    
+    BX      lr 
+;}
+;
+;
+    PUBLIC  SysTick_Handler
+    PUBLIC  __tx_SysTickHandler
+__tx_SysTickHandler:
+SysTick_Handler:
+;
+; VOID SysTick_Handler (VOID)
+; {
+;
+    PUSH    {r0, lr}
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+#endif
+    BL      _tx_timer_interrupt
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    BL      _tx_execution_isr_exit              ; Call the ISR exit function
+#endif
+    POP     {r0, lr}
+    BX      LR
+; }
+    END
+
diff --git a/ports/cortex_m7/iar/inc/tx_port.h b/ports/cortex_m7/iar/inc/tx_port.h
new file mode 100644
index 00000000..9995e99a
--- /dev/null
+++ b/ports/cortex_m7/iar/inc/tx_port.h
@@ -0,0 +1,499 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/
+/*                                                                        */
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */
+/*                                                                        */
+/*    tx_port.h                                         Cortex-M7/IAR     */
+/*                                                           6.0.1        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This file contains data type definitions that make the ThreadX      */
+/*    real-time kernel function identically on a variety of different     */
+/*    processor architectures.  For example, the size or number of bits   */
+/*    in an "int" data type vary between microprocessor architectures and */
+/*    even C compilers for the same microprocessor.  ThreadX does not     */
+/*    directly use native C data types.  Instead, ThreadX creates its     */
+/*    own special types that can be mapped to actual data types by this   */
+/*    file to guarantee consistency in the interface and functionality.   */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include 
+#include 
+#include 
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#include 
+#endif
+
+
+/* Define ThreadX basic types for this port.  */
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */
+#endif
+
+
+/* Define various constants for the ThreadX Cortex-M3 port.  */
+
+#define TX_INT_DISABLE                          1           /* Disable interrupts               */
+#define TX_INT_ENABLE                           0           /* Enable interrupts                */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_MISRA_ENABLE
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0xE0001004)  
+#endif
+#else
+ULONG   _tx_misra_time_stamp_get(VOID);
+#define TX_TRACE_TIME_SOURCE                    _tx_misra_time_stamp_get()
+#endif
+
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          (0)
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#ifdef TX_MISRA_ENABLE
+#define TX_DISABLE_INLINE
+#else
+#define TX_INLINE_INITIALIZATION
+#endif
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifndef TX_MISRA_ENABLE
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_EXTENSION_2           VOID    *tx_thread_iar_tls_pointer;          
+#else
+#define TX_THREAD_EXTENSION_2          
+#endif
+#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+#define TX_THREAD_EXTENSION_3          
+#else
+#define TX_THREAD_EXTENSION_3           unsigned long long  tx_thread_execution_time_total; \
+                                        unsigned long long  tx_thread_execution_time_last_start; 
+#endif
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#if (__VER__ < 8000000)
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  __iar_dlib_perthread_allocate();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                    thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL;            
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               __iar_dlib_perthread_access(0);
+#else
+void    *_tx_iar_create_per_thread_tls_area(void);
+void    _tx_iar_destroy_per_thread_tls_area(void *tls_ptr);
+void    __iar_Initlocks(void);
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  _tx_iar_create_per_thread_tls_area();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                        thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL; } while(0);
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               do {__iar_Initlocks();} while(0); 
+#endif
+#else
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#endif
+
+
+#ifdef __ARMVFP__
+
+#ifdef TX_MISRA_ENABLE
+
+ULONG  _tx_misra_control_get(void);
+void   _tx_misra_control_set(ULONG value);
+ULONG  _tx_misra_fpccr_get(void);
+void   _tx_misra_vfp_touch(void);
+
+#endif
+
+/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA
+   in order to ensure no lazy stacking will occur. */
+
+#ifndef TX_MISRA_ENABLE
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)                   {                                                                                             \
+                                                                    ULONG  _tx_vfp_state;                                                                         \
+                                                                        _tx_vfp_state =  __get_CONTROL();                                                         \
+                                                                        _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                          \
+                                                                        __set_CONTROL(_tx_vfp_state);                                                             \
+                                                                    }
+#else
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)                   {                                                                                             \
+                                                                    ULONG  _tx_vfp_state;                                                                         \
+                                                                        _tx_vfp_state =  _tx_misra_control_get();                                                 \
+                                                                        _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                          \
+                                                                        _tx_misra_control_set(_tx_vfp_state);                                                     \
+                                                                    }
+                                                                    
+#endif
+
+/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR.
+   If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating
+   this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush 
+   the lazy FPU save, then restore the CONTROL.FPCA state. */
+
+#ifndef TX_MISRA_ENABLE
+
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  {                                                                                             \
+                                                                    ULONG  _tx_system_state;                                                                      \
+                                                                        _tx_system_state =  TX_THREAD_GET_SYSTEM_STATE();                                         \
+                                                                        if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr))        \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_vfp_state;                                                                     \
+                                                                            _tx_vfp_state =  __get_CONTROL();                                                     \
+                                                                            _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                      \
+                                                                            __set_CONTROL(_tx_vfp_state);                                                         \
+                                                                        }                                                                                         \
+                                                                        else                                                                                      \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_fpccr;                                                                         \
+                                                                            _tx_fpccr =  *((ULONG *) 0xE000EF34);                                                 \
+                                                                            _tx_fpccr =  _tx_fpccr & ((ULONG) 0x01);                                              \
+                                                                            if (_tx_fpccr == ((ULONG) 0x01))                                                      \
+                                                                            {                                                                                     \
+                                                                            ULONG _tx_vfp_state;                                                                  \
+                                                                                _tx_vfp_state = __get_CONTROL();                                                  \
+                                                                                _tx_vfp_state =  _tx_vfp_state & ((ULONG) 0x4);                                   \
+                                                                                __asm volatile ("vmov.f32 s0, s0");                                               \
+                                                                                if (_tx_vfp_state == ((ULONG) 0))                                                 \
+                                                                                {                                                                                 \
+                                                                                    _tx_vfp_state =  __get_CONTROL();                                             \
+                                                                                    _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                              \
+                                                                                    __set_CONTROL(_tx_vfp_state);                                                 \
+                                                                                }                                                                                 \
+                                                                            }                                                                                     \
+                                                                        }                                                                                         \
+                                                                    }
+#else
+
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  {                                                                                             \
+                                                                    ULONG  _tx_system_state;                                                                      \
+                                                                        _tx_system_state =  TX_THREAD_GET_SYSTEM_STATE();                                         \
+                                                                        if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr))        \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_vfp_state;                                                                     \
+                                                                            _tx_vfp_state =  _tx_misra_control_get();                                             \
+                                                                            _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                                      \
+                                                                            _tx_misra_control_set(_tx_vfp_state);                                                 \
+                                                                        }                                                                                         \
+                                                                        else                                                                                      \
+                                                                        {                                                                                         \
+                                                                        ULONG  _tx_fpccr;                                                                         \
+                                                                            _tx_fpccr =  _tx_misra_fpccr_get();                                                   \
+                                                                            _tx_fpccr =  _tx_fpccr & ((ULONG) 0x01);                                              \
+                                                                            if (_tx_fpccr == ((ULONG) 0x01))                                                      \
+                                                                            {                                                                                     \
+                                                                            ULONG _tx_vfp_state;                                                                  \
+                                                                                _tx_vfp_state = _tx_misra_control_get();                                          \
+                                                                                _tx_vfp_state =  _tx_vfp_state & ((ULONG) 0x4);                                   \
+                                                                                _tx_misra_vfp_touch();                                                            \
+                                                                                if (_tx_vfp_state == ((ULONG) 0))                                                 \
+                                                                                {                                                                                 \
+                                                                                    _tx_vfp_state =  _tx_misra_control_get();                                     \
+                                                                                    _tx_vfp_state =  _tx_vfp_state & ~((ULONG) 0x4);                              \
+                                                                                    _tx_misra_control_set(_tx_vfp_state);                                         \
+                                                                                }                                                                                 \
+                                                                            }                                                                                     \
+                                                                        }                                                                                         \
+                                                                    }
+#endif
+
+#else
+
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                  
+
+#endif
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Define the get system state macro.   */
+   
+#ifndef TX_THREAD_GET_SYSTEM_STATE
+#ifndef TX_MISRA_ENABLE
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | __get_IPSR())
+#else
+ULONG   _tx_misra_ipsr_get(VOID);
+#define TX_THREAD_GET_SYSTEM_STATE()        (_tx_thread_system_state | _tx_misra_ipsr_get())
+#endif
+#endif
+
+
+/* Define the check for whether or not to call the _tx_thread_system_return function.  A non-zero value
+   indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h
+   for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always
+   zero after initialization for Cortex-M ports. */
+
+#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
+#define TX_THREAD_SYSTEM_RETURN_CHECK(c)    (c) = ((ULONG) _tx_thread_preempt_disable); 
+#endif
+
+
+/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to 
+   prevent early scheduling on Cortex-M parts.  */
+   
+#define TX_PORT_SPECIFIC_POST_INITIALIZATION    _tx_thread_preempt_disable++;
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef TX_DISABLE_INLINE
+
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       (b) = (UINT)__CLZ(__RBIT((m)));
+
+#endif
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+/* The embedded assembler blocks are design so as to be inlinable by the
+   armlink linker inlining. This requires them to consist of either a
+   single 32-bit instruction, or either one or two 16-bit instructions
+   followed by a "BX lr". Note that to reduce the critical region size, the
+   16-bit "CPSID i" instruction is preceeded by a 16-bit NOP */
+
+#ifdef TX_DISABLE_INLINE
+
+UINT                                            _tx_thread_interrupt_disable(VOID);
+VOID                                            _tx_thread_interrupt_restore(UINT previous_posture);
+
+#define TX_INTERRUPT_SAVE_AREA                  register UINT interrupt_save;
+
+#define TX_DISABLE                              interrupt_save = _tx_thread_interrupt_disable();
+
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+
+#else
+
+#define TX_INTERRUPT_SAVE_AREA                  __istate_t interrupt_save;
+#define TX_DISABLE                              {interrupt_save = __get_interrupt_state();__disable_interrupt();};
+#define TX_RESTORE                              {__set_interrupt_state(interrupt_save);};
+
+#define _tx_thread_system_return                _tx_thread_system_return_inline
+
+static void _tx_thread_system_return_inline(void)
+{
+__istate_t interrupt_save;
+
+    /* Set PendSV to invoke ThreadX scheduler.  */
+    *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
+    if (__get_IPSR() == 0)
+    {
+        interrupt_save = __get_interrupt_state();
+        __enable_interrupt();
+        __set_interrupt_state(interrupt_save);
+    }
+}
+
+#endif
+
+
+/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing
+   thread. These are no longer needed, but are preserved for backward compatibility only.  */
+
+void    tx_thread_fpu_enable(void);
+void    tx_thread_fpu_disable(void);
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Cortex-M7/IAR Version 6.0 *";
+#else
+#ifdef TX_MISRA_ENABLE
+extern  CHAR                    _tx_version_id[100];
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+#endif
+
+
+#endif
+
+
+
diff --git a/ports/cortex_m7/iar/readme_threadx.txt b/ports/cortex_m7/iar/readme_threadx.txt
new file mode 100644
index 00000000..42c8d901
--- /dev/null
+++ b/ports/cortex_m7/iar/readme_threadx.txt
@@ -0,0 +1,216 @@
+                       Microsoft's Azure RTOS ThreadX for Cortex-M7 
+
+                                   Using the IAR Tools
+
+
+1.  Building the ThreadX run-time Library
+
+Building the ThreadX library is easy. First, open the Azure RTOS workspace
+azure_rtos.eww. Next, make the TX project the "active project" in the 
+IAR Embedded Workbench and select the "Make" button. You should observe 
+assembly and compilation of a series of ThreadX source files. This 
+results in the ThreadX run-time library file tx.a, which is needed by 
+the application.
+
+
+2.  Demonstration System
+
+The ThreadX demonstration is designed to execute under the IAR debugger under 
+simulation.
+
+Building the demonstration is easy; simply open the threadx.www workspace file,
+make the sample_threadx.ewp project the "active project" in the IAR Embedded 
+Workbench, and select the "Make" button.
+
+You should observe the compilation of sample_threadx.c (which is the demonstration 
+application) and linking with tx.a. The resulting file sample_threadx.out is a 
+binary ELF file that can be downloaded and executed on the IAR Windows-based 
+Cortex-M7 simulator.
+
+
+3.  System Initialization
+
+The entry point in ThreadX for the Cortex-M7 using IAR tools is at label 
+__iar_program_start. This is defined within the IAR compiler's startup code. 
+In addition, this is where all static and global preset C variable 
+initialization processing takes place.
+
+The ThreadX tx_initialize_low_level.s file is responsible for setting up 
+various system data structures, and a periodic timer interrupt source. 
+By default, the vector area is defined at the top of cstartup_M.s, which is
+a slightly modified from the base IAR file. 
+
+The _tx_initialize_low_level function inside of tx_initialize_low_level.s
+also determines the first available address for use by the application, which 
+is supplied as the sole input parameter to your application definition function, 
+tx_application_define. To accomplish this, a section is created in 
+tx_initialize_low_level.s called FREE_MEM, which must be located after all 
+other RAM sections in memory.
+
+
+4.  Register Usage and Stack Frames
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have the same stack frame in the Cortex-M7 version of
+ThreadX. The top of the suspended thread's stack is pointed to by 
+tx_thread_stack_ptr in the associated thread control block TX_THREAD.
+
+Non-FPU Stack Frame:
+
+  Stack Offset     Stack Contents 
+
+     0x00               LR          Interrupted LR (LR at time of PENDSV)
+     0x04               r4          
+     0x08               r5          
+     0x0C               r6          
+     0x10               r7          
+     0x14               r8          
+     0x18               r9          
+     0x1C               r10 (sl)    
+     0x20               r11         
+     0x24               r0          (Hardware stack starts here!!)
+     0x28               r1          
+     0x2C               r2          
+     0x30               r3          
+     0x34               r12         
+     0x38               lr          
+     0x3C               pc          
+     0x40               xPSR        
+
+FPU Stack Frame (only interrupted thread with FPU enabled):
+
+  Stack Offset     Stack Contents 
+
+     0x00               LR          Interrupted LR (LR at time of PENDSV)
+     0x04               s0
+     0x08               s1
+     0x0C               s2
+     0x10               s3
+     0x14               s4
+     0x18               s5
+     0x1C               s6
+     0x20               s7
+     0x24               s8
+     0x28               s9
+     0x2C               s10
+     0x30               s11
+     0x34               s12
+     0x38               s13
+     0x3C               s14
+     0x40               s15
+     0x44               s16
+     0x48               s17
+     0x4C               s18
+     0x50               s19
+     0x54               s20
+     0x58               s21
+     0x5C               s22
+     0x60               s23
+     0x64               s24
+     0x68               s25
+     0x6C               s26
+     0x70               s27
+     0x74               s28
+     0x78               s29
+     0x7C               s30
+     0x80               s31
+     0x84               fpscr
+     0x88               r4          
+     0x8C               r5          
+     0x90               r6          
+     0x94               r7          
+     0x98               r8          
+     0x9C               r9          
+     0xA0               r10 (sl)    
+     0xA4               r11         
+     0xA8               r0          (Hardware stack starts here!!)
+     0xAC               r1          
+     0xB0               r2          
+     0xB4               r3          
+     0xB8               r12         
+     0xBC               lr          
+     0xC0               pc          
+     0xC4               xPSR        
+
+
+5.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+breakpoints inside of ThreadX itself. Of course, this costs some 
+performance. To make it run faster, you can change the ThreadX library
+project to enable various compiler optimizations. 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+6.  Interrupt Handling
+
+The Cortex-M7 vectors start at the label __vector_table and is defined in cstartup_M.s. 
+The application may modify the vector area according to its needs.
+
+
+6.1 Managed Interrupts
+
+ISRs for Cortex-M using the IAR tools can be written completely in C (or assembly
+language) without any calls to _tx_thread_context_save or _tx_thread_context_restore.
+These ISRs are allowed access to the ThreadX API that is available to ISRs.
+
+ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):
+
+void    your_C_isr(void)
+{
+
+    /* ISR processing goes here, including any needed function calls.  */
+}
+
+ISRs written in assembly language will take the form:
+
+        PUBLIC  your_assembly_isr
+your_assembly_isr:
+
+    PUSH    {r0, lr}
+
+    ; ISR processing goes here, including any needed function calls.
+
+    POP     {r0, lr}
+    BX      lr
+
+
+7.  IAR Thread-safe Library Support
+
+Thread-safe support for the IAR tools is easily enabled by building the ThreadX library
+and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file
+should have the following line added (if not already in place):
+
+initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
+
+The project options "General Options -> Library Configuration" should also have the 
+"Enable thread support in library" box selected.
+
+
+8. VFP Support
+
+ThreadX for Cortex-M7 supports automatic ("lazy") VFP support, which means that applications threads 
+can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread 
+context - no additional setup by the application.
+
+
+
+9.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX version 6.0.1 for Cortex-M7 using IAR's ARM tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_m7/iar/src/tx_iar.c b/ports/cortex_m7/iar/src/tx_iar.c
new file mode 100644
index 00000000..dd719370
--- /dev/null
+++ b/ports/cortex_m7/iar/src/tx_iar.c
@@ -0,0 +1,804 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   IAR Multithreaded Library Support                                   */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Define IAR library for tools prior to version 8.  */
+
+#if (__VER__ < 8000000)
+
+
+/* IAR version 7 and below.  */
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_initialize.h"
+#include "tx_thread.h"
+#include "tx_mutex.h"
+
+
+/* This implementation requires that the following macros are defined in the 
+   tx_port.h file and  is included with the following code segments:
+   
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#include 
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_EXTENSION_2           VOID    *tx_thread_iar_tls_pointer;          
+#else
+#define TX_THREAD_EXTENSION_2          
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  __iar_dlib_perthread_allocate();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                    thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL;            
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               __iar_dlib_perthread_access(0);
+#else
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#endif
+
+    This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the 
+    application.  
+
+    Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected.
+*/
+
+#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
+
+#include 
+
+
+#if _MULTI_THREAD
+
+TX_MUTEX    __tx_iar_system_lock_mutexes[_MAX_LOCK];
+UINT        __tx_iar_system_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_system_lock_no_mutexes;
+UINT        __tx_iar_system_lock_internal_errors;
+UINT        __tx_iar_system_lock_isr_caller;
+
+
+/* Define the TLS access function for the IAR library.  */
+
+void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp)
+{
+
+char _DLIB_TLS_MEMORY   *p = 0;
+    
+    /* Is there a current thread?  */
+    if (_tx_thread_current_ptr)
+      p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer;
+    else
+      p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD");
+    p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp);
+    return (void _DLIB_TLS_MEMORY *) p;
+}
+
+
+/* Define mutexes for IAR library.  */
+
+void __iar_system_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_LOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_system_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_system_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_system_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_system_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_system_Mtxlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+}
+
+void __iar_system_Mtxunlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+}
+
+
+#if _DLIB_FILE_DESCRIPTOR
+
+TX_MUTEX    __tx_iar_file_lock_mutexes[_MAX_FLOCK];
+UINT        __tx_iar_file_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_file_lock_no_mutexes;
+UINT        __tx_iar_file_lock_internal_errors;
+UINT        __tx_iar_file_lock_isr_caller;
+
+
+void __iar_file_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_FLOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_file_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_file_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_file_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_file_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_file_Mtxlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+
+void __iar_file_Mtxunlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+#endif  /* _DLIB_FILE_DESCRIPTOR */
+
+#endif  /* _MULTI_THREAD  */
+
+#endif  /* TX_ENABLE_IAR_LIBRARY_SUPPORT  */
+
+#else   /* IAR version 8 and above.  */
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_initialize.h"
+#include "tx_thread.h"
+#include "tx_mutex.h"
+
+/* This implementation requires that the following macros are defined in the 
+   tx_port.h file and  is included with the following code segments:
+   
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#include 
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_EXTENSION_2           VOID    *tx_thread_iar_tls_pointer;          
+#else
+#define TX_THREAD_EXTENSION_2          
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+void    *_tx_iar_create_per_thread_tls_area(void);
+void    _tx_iar_destroy_per_thread_tls_area(void *tls_ptr);
+void    __iar_Initlocks(void);
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  __iar_dlib_perthread_allocate();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                        thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL; } while(0);
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               do {__iar_Initlocks();} while(0);
+#else
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#endif
+
+    This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the 
+    application.  
+
+    Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected.
+*/
+
+#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
+
+#include 
+
+
+void * __aeabi_read_tp();
+
+void* _tx_iar_create_per_thread_tls_area();
+void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr);
+
+#pragma section="__iar_tls$$DATA"
+
+/* Define the TLS access function for the IAR library.  */
+void * __aeabi_read_tp(void)
+{
+  void *p = 0;
+  TX_THREAD *thread_ptr = _tx_thread_current_ptr;
+  if (thread_ptr)
+  {
+    p = thread_ptr->tx_thread_iar_tls_pointer;      
+  }
+  else
+  {
+    p = __section_begin("__iar_tls$$DATA");
+  }
+  return p;
+}
+
+/* Define the TLS creation and destruction to use malloc/free.  */
+
+void* _tx_iar_create_per_thread_tls_area()
+{
+  UINT tls_size = __iar_tls_size();  
+  
+  /* Get memory for TLS.  */  
+  void *p = malloc(tls_size);
+
+  /* Initialize TLS-area and run constructors for objects in TLS */
+  __iar_tls_init(p);
+  return p;
+}
+
+void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr)
+{
+  /* Destroy objects living in TLS */
+  __call_thread_dtors();
+  free(tls_ptr);  
+}
+
+#ifndef _MAX_LOCK
+#define _MAX_LOCK 4
+#endif
+
+static TX_MUTEX    __tx_iar_system_lock_mutexes[_MAX_LOCK];
+static UINT        __tx_iar_system_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_system_lock_no_mutexes;
+UINT        __tx_iar_system_lock_internal_errors;
+UINT        __tx_iar_system_lock_isr_caller;
+
+
+/* Define mutexes for IAR library.  */
+
+void __iar_system_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_LOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_system_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_system_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_system_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_system_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_system_Mtxlock(__iar_Rmtx *m)
+{
+  if (*m)
+  {  
+    UINT    status;
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+  }
+}
+
+void __iar_system_Mtxunlock(__iar_Rmtx *m)
+{
+  if (*m)
+  {
+    UINT    status;
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+  }
+}
+
+
+#if _DLIB_FILE_DESCRIPTOR
+
+#include                         /* Added to get access to FOPEN_MAX */
+#ifndef _MAX_FLOCK
+#define _MAX_FLOCK FOPEN_MAX              /* Define _MAX_FLOCK as the maximum number of open files */
+#endif
+
+
+TX_MUTEX    __tx_iar_file_lock_mutexes[_MAX_FLOCK];
+UINT        __tx_iar_file_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_file_lock_no_mutexes;
+UINT        __tx_iar_file_lock_internal_errors;
+UINT        __tx_iar_file_lock_isr_caller;
+
+
+void __iar_file_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_FLOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_file_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_file_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_file_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_file_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_file_Mtxlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+
+void __iar_file_Mtxunlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+#endif  /* _DLIB_FILE_DESCRIPTOR */
+
+#endif  /* TX_ENABLE_IAR_LIBRARY_SUPPORT  */
+
+#endif /* IAR version 8 and above.  */
diff --git a/ports/cortex_m7/iar/src/tx_misra.s b/ports/cortex_m7/iar/src/tx_misra.s
new file mode 100644
index 00000000..60ab3549
--- /dev/null
+++ b/ports/cortex_m7/iar/src/tx_misra.s
@@ -0,0 +1,1074 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   ThreadX MISRA Compliance                                            */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        #define SHT_PROGBITS 0x1
+
+        EXTERN __aeabi_memset
+        EXTERN _tx_thread_current_ptr
+        EXTERN _tx_thread_interrupt_disable
+        EXTERN _tx_thread_interrupt_restore
+        EXTERN _tx_thread_stack_analyze
+        EXTERN _tx_thread_stack_error_handler
+        EXTERN _tx_thread_system_state
+#ifdef TX_ENABLE_EVENT_TRACE
+        EXTERN _tx_trace_buffer_current_ptr
+        EXTERN _tx_trace_buffer_end_ptr
+        EXTERN _tx_trace_buffer_start_ptr
+        EXTERN _tx_trace_event_enable_bits
+        EXTERN _tx_trace_full_notify_function
+        EXTERN _tx_trace_header_ptr
+#endif
+
+        PUBLIC _tx_misra_always_true
+        PUBLIC _tx_misra_block_pool_to_uchar_pointer_convert
+        PUBLIC _tx_misra_byte_pool_to_uchar_pointer_convert
+        PUBLIC _tx_misra_char_to_uchar_pointer_convert
+        PUBLIC _tx_misra_const_char_to_char_pointer_convert
+#ifdef TX_ENABLE_EVENT_TRACE
+        PUBLIC _tx_misra_entry_to_uchar_pointer_convert
+#endif
+        PUBLIC _tx_misra_indirect_void_to_uchar_pointer_convert
+        PUBLIC _tx_misra_memset
+        PUBLIC _tx_misra_message_copy
+#ifdef TX_ENABLE_EVENT_TRACE
+        PUBLIC _tx_misra_object_to_uchar_pointer_convert
+#endif
+        PUBLIC _tx_misra_pointer_to_ulong_convert
+        PUBLIC _tx_misra_status_get
+        PUBLIC _tx_misra_thread_stack_check
+#ifdef TX_ENABLE_EVENT_TRACE
+        PUBLIC _tx_misra_time_stamp_get
+#endif
+        PUBLIC _tx_misra_timer_indirect_to_void_pointer_convert
+        PUBLIC _tx_misra_timer_pointer_add
+        PUBLIC _tx_misra_timer_pointer_dif
+#ifdef TX_ENABLE_EVENT_TRACE
+        PUBLIC _tx_misra_trace_event_insert
+#endif
+        PUBLIC _tx_misra_uchar_pointer_add
+        PUBLIC _tx_misra_uchar_pointer_dif
+        PUBLIC _tx_misra_uchar_pointer_sub
+        PUBLIC _tx_misra_uchar_to_align_type_pointer_convert
+        PUBLIC _tx_misra_uchar_to_block_pool_pointer_convert
+#ifdef TX_ENABLE_EVENT_TRACE
+        PUBLIC _tx_misra_uchar_to_entry_pointer_convert
+        PUBLIC _tx_misra_uchar_to_header_pointer_convert
+#endif
+        PUBLIC _tx_misra_uchar_to_indirect_byte_pool_pointer_convert
+        PUBLIC _tx_misra_uchar_to_indirect_uchar_pointer_convert
+#ifdef TX_ENABLE_EVENT_TRACE
+        PUBLIC _tx_misra_uchar_to_object_pointer_convert
+#endif
+        PUBLIC _tx_misra_uchar_to_void_pointer_convert
+        PUBLIC _tx_misra_ulong_pointer_add
+        PUBLIC _tx_misra_ulong_pointer_dif
+        PUBLIC _tx_misra_ulong_pointer_sub
+        PUBLIC _tx_misra_ulong_to_pointer_convert
+        PUBLIC _tx_misra_ulong_to_thread_pointer_convert
+        PUBLIC _tx_misra_user_timer_pointer_get
+        PUBLIC _tx_misra_void_to_block_pool_pointer_convert
+        PUBLIC _tx_misra_void_to_byte_pool_pointer_convert
+        PUBLIC _tx_misra_void_to_event_flags_pointer_convert
+        PUBLIC _tx_misra_void_to_indirect_uchar_pointer_convert
+        PUBLIC _tx_misra_void_to_mutex_pointer_convert
+        PUBLIC _tx_misra_void_to_queue_pointer_convert
+        PUBLIC _tx_misra_void_to_semaphore_pointer_convert
+        PUBLIC _tx_misra_void_to_thread_pointer_convert
+        PUBLIC _tx_misra_void_to_uchar_pointer_convert
+        PUBLIC _tx_misra_void_to_ulong_pointer_convert
+        PUBLIC _tx_misra_ipsr_get
+        PUBLIC _tx_misra_control_get
+        PUBLIC _tx_misra_control_set
+#ifdef __ARMVFP__
+        PUBLIC _tx_misra_fpccr_get
+        PUBLIC _tx_misra_vfp_touch
+#endif
+        PUBLIC _tx_version_id
+
+
+        SECTION `.data`:DATA:REORDER:NOROOT(2)
+        DATA
+//   51 CHAR  _tx_version_id[100] =  "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0       MISRA C Compliant *";
+_tx_version_id:
+        DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H
+        DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H
+        DC8 39H, 36H, 2DH, 32H, 30H, 31H, 38H, 20H
+        DC8 45H, 78H, 70H, 72H, 65H, 73H, 73H, 20H
+        DC8 4CH, 6FH, 67H, 69H, 63H, 20H, 49H, 6EH
+        DC8 63H, 2EH, 20H, 2AH, 20H, 54H, 68H, 72H
+        DC8 65H, 61H, 64H, 58H, 20H, 35H, 2EH, 38H
+        DC8 20H, 4DH, 49H, 53H, 52H, 41H, 20H, 43H
+        DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H
+        DC8 6EH, 74H, 20H, 2AH, 0
+        DC8 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  VOID  _tx_misra_memset(VOID *ptr, UINT value, UINT size);            */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_memset:
+        PUSH     {R4,LR}
+        MOVS     R4,R0
+        MOVS     R0,R2
+        MOVS     R2,R1
+        MOVS     R1,R0
+        MOVS     R0,R4
+        BL       __aeabi_memset
+        POP      {R4,PC}          ;; return
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  UCHAR  *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount);       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_pointer_add:
+        ADD      R0,R0,R1
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  UCHAR  *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount);       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_pointer_sub:
+        RSBS     R1,R1,#+0
+        ADD      R0,R0,R1
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  ULONG  _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2);        */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_pointer_dif:
+        SUBS     R0,R0,R1
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  ULONG  _tx_misra_pointer_to_ulong_convert(VOID *ptr);                */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_pointer_to_ulong_convert:
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  ULONG  *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount);       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_ulong_pointer_add:
+        ADD      R0,R0,R1, LSL #+2
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  ULONG  *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount);       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_ulong_pointer_sub:
+        MVNS     R2,#+3
+        MULS     R1,R2,R1
+        ADD      R0,R0,R1
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  ULONG  _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2);        */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_ulong_pointer_dif:
+        SUBS     R0,R0,R1
+        ASRS     R0,R0,#+2
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  VOID  *_tx_misra_ulong_to_pointer_convert(ULONG input);              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_ulong_to_pointer_convert:
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  VOID  _tx_misra_message_copy(ULONG **source, ULONG **destination,    */
+/**                                                           UINT size); */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_message_copy:
+        PUSH     {R4,R5}
+        LDR      R3,[R0, #+0]
+        LDR      R4,[R1, #+0]
+        LDR      R5,[R3, #+0]
+        STR      R5,[R4, #+0]
+        ADDS     R4,R4,#+4
+        ADDS     R3,R3,#+4
+        CMP      R2,#+2
+        BCC.N    ??_tx_misra_message_copy_0
+        SUBS     R2,R2,#+1
+        B.N      ??_tx_misra_message_copy_1
+??_tx_misra_message_copy_2:
+        LDR      R5,[R3, #+0]
+        STR      R5,[R4, #+0]
+        ADDS     R4,R4,#+4
+        ADDS     R3,R3,#+4
+        SUBS     R2,R2,#+1
+??_tx_misra_message_copy_1:
+        CMP      R2,#+0
+        BNE.N    ??_tx_misra_message_copy_2
+??_tx_misra_message_copy_0:
+        STR      R3,[R0, #+0]
+        STR      R4,[R1, #+0]
+        POP      {R4,R5}
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  ULONG  _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1,         */
+/**                                           TX_TIMER_INTERNAL **ptr2);  */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_timer_pointer_dif:
+        SUBS     R0,R0,R1
+        ASRS     R0,R0,#+2
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL    */
+/**                                                  **ptr1, ULONG size); */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_timer_pointer_add:
+        ADD      R0,R0,R1, LSL #+2
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  VOID  _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL             */
+/**                              *internal_timer, TX_TIMER **user_timer); */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_user_timer_pointer_get:
+        ADDS     R2,R0,#+8
+        SUBS     R2,R2,R0
+        RSBS     R2,R2,#+0
+        ADD      R0,R0,R2
+        STR      R0,[R1, #+0]
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  VOID  _tx_misra_thread_stack_check(TX_THREAD *thread_ptr,            */
+/**                                              VOID **highest_stack);   */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_thread_stack_check:
+        PUSH     {R3-R5,LR}
+        MOVS     R4,R0
+        MOVS     R5,R1
+        BL       _tx_thread_interrupt_disable
+        CMP      R4,#+0
+        BEQ.N    ??_tx_misra_thread_stack_check_0
+        LDR      R1,[R4, #+0]
+        LDR.N    R2,??DataTable2  ;; 0x54485244
+        CMP      R1,R2
+        BNE.N    ??_tx_misra_thread_stack_check_0
+        LDR      R1,[R4, #+8]
+        LDR      R2,[R5, #+0]
+        CMP      R1,R2
+        BCS.N    ??_tx_misra_thread_stack_check_1
+        LDR      R1,[R4, #+8]
+        STR      R1,[R5, #+0]
+??_tx_misra_thread_stack_check_1:
+        LDR      R1,[R4, #+12]
+        LDR      R1,[R1, #+0]
+        CMP      R1,#-269488145
+        BNE.N    ??_tx_misra_thread_stack_check_2
+        LDR      R1,[R4, #+16]
+        LDR      R1,[R1, #+1]
+        CMP      R1,#-269488145
+        BNE.N    ??_tx_misra_thread_stack_check_2
+        LDR      R1,[R5, #+0]
+        LDR      R2,[R4, #+12]
+        CMP      R1,R2
+        BCS.N    ??_tx_misra_thread_stack_check_3
+??_tx_misra_thread_stack_check_2:
+        BL       _tx_thread_interrupt_restore
+        MOVS     R0,R4
+        BL       _tx_thread_stack_error_handler
+        BL       _tx_thread_interrupt_disable
+??_tx_misra_thread_stack_check_3:
+        LDR      R1,[R5, #+0]
+        LDR      R1,[R1, #-4]
+        CMP      R1,#-269488145
+        BEQ.N    ??_tx_misra_thread_stack_check_0
+        BL       _tx_thread_interrupt_restore
+        MOVS     R0,R4
+        BL       _tx_thread_stack_analyze
+        BL       _tx_thread_interrupt_disable
+??_tx_misra_thread_stack_check_0:
+        BL       _tx_thread_interrupt_restore
+        POP      {R0,R4,R5,PC}    ;; return
+
+#ifdef TX_ENABLE_EVENT_TRACE
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  VOID  _tx_misra_trace_event_insert(ULONG event_id,                   */
+/**           VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */
+/**           ULONG info_field_4, ULONG filter, ULONG time_stamp);        */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_trace_event_insert:
+        PUSH     {R3-R7,LR}
+        LDR.N    R4,??DataTable2_1
+        LDR      R4,[R4, #+0]
+        CMP      R4,#+0
+        BEQ.N    ??_tx_misra_trace_event_insert_0
+        LDR.N    R5,??DataTable2_2
+        LDR      R5,[R5, #+0]
+        LDR      R6,[SP, #+28]
+        TST      R5,R6
+        BEQ.N    ??_tx_misra_trace_event_insert_0
+        LDR.N    R5,??DataTable2_3
+        LDR      R5,[R5, #+0]
+        LDR.N    R6,??DataTable2_4
+        LDR      R6,[R6, #+0]
+        CMP      R5,#+0
+        BNE.N    ??_tx_misra_trace_event_insert_1
+        LDR      R5,[R6, #+44]
+        LDR      R7,[R6, #+60]
+        LSLS     R7,R7,#+16
+        ORRS     R7,R7,#0x80000000
+        ORRS     R5,R7,R5
+        B.N      ??_tx_misra_trace_event_insert_2
+??_tx_misra_trace_event_insert_1:
+        CMP      R5,#-252645136
+        BCS.N    ??_tx_misra_trace_event_insert_3
+        MOVS     R5,R6
+        MOVS     R6,#-1
+        B.N      ??_tx_misra_trace_event_insert_2
+??_tx_misra_trace_event_insert_3:
+        MOVS     R6,#-252645136
+        MOVS     R5,#+0
+??_tx_misra_trace_event_insert_2:
+        STR      R6,[R4, #+0]
+        STR      R5,[R4, #+4]
+        STR      R0,[R4, #+8]
+        LDR      R0,[SP, #+32]
+        STR      R0,[R4, #+12]
+        STR      R1,[R4, #+16]
+        STR      R2,[R4, #+20]
+        STR      R3,[R4, #+24]
+        LDR      R0,[SP, #+24]
+        STR      R0,[R4, #+28]
+        ADDS     R4,R4,#+32
+        LDR.N    R0,??DataTable2_5
+        LDR      R0,[R0, #+0]
+        CMP      R4,R0
+        BCC.N    ??_tx_misra_trace_event_insert_4
+        LDR.N    R0,??DataTable2_6
+        LDR      R4,[R0, #+0]
+        LDR.N    R0,??DataTable2_1
+        STR      R4,[R0, #+0]
+        LDR.N    R0,??DataTable2_7
+        LDR      R0,[R0, #+0]
+        STR      R4,[R0, #+32]
+        LDR.N    R0,??DataTable2_8
+        LDR      R0,[R0, #+0]
+        CMP      R0,#+0
+        BEQ.N    ??_tx_misra_trace_event_insert_0
+        LDR.N    R0,??DataTable2_7
+        LDR      R0,[R0, #+0]
+        LDR.N    R1,??DataTable2_8
+        LDR      R1,[R1, #+0]
+        BLX      R1
+        B.N      ??_tx_misra_trace_event_insert_0
+??_tx_misra_trace_event_insert_4:
+        LDR.N    R0,??DataTable2_1
+        STR      R4,[R0, #+0]
+        LDR.N    R0,??DataTable2_7
+        LDR      R0,[R0, #+0]
+        STR      R4,[R0, #+32]
+??_tx_misra_trace_event_insert_0:
+        POP      {R0,R4-R7,PC}    ;; return
+
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_1:
+        DC32     _tx_trace_buffer_current_ptr
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_2:
+        DC32     _tx_trace_event_enable_bits
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_5:
+        DC32     _tx_trace_buffer_end_ptr
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_6:
+        DC32     _tx_trace_buffer_start_ptr
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_7:
+        DC32     _tx_trace_header_ptr
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_8:
+        DC32     _tx_trace_full_notify_function
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  ULONG  _tx_misra_time_stamp_get(VOID);                               */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_time_stamp_get:
+        MOVS     R0,#+0
+        BX       LR               ;; return
+
+#endif
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2:
+        DC32     0x54485244
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_3:
+        DC32     _tx_thread_system_state
+
+        SECTION `.text`:CODE:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+??DataTable2_4:
+        DC32     _tx_thread_current_ptr
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  UINT  _tx_misra_always_true(void);                                   */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_always_true:
+        MOVS     R0,#+1
+        BX       LR               ;; return
+
+
+/******************************************************************************************/
+/******************************************************************************************/
+/**                                                                                       */
+/**  UCHAR  **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr);        */
+/**                                                                                       */
+/******************************************************************************************/
+/******************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_indirect_void_to_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/***************************************************************************************/
+/***************************************************************************************/
+/**                                                                                    */
+/**  UCHAR  **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer);       */
+/**                                                                                    */
+/***************************************************************************************/
+/***************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_indirect_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/***********************************************************************************/
+/***********************************************************************************/
+/**                                                                                */
+/**  UCHAR  *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool);   */
+/**                                                                                */
+/***********************************************************************************/
+/***********************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_block_pool_to_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/******************************************************************************************/
+/******************************************************************************************/
+/**                                                                                       */
+/**  TX_BLOCK_POOL  *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer);         */
+/**                                                                                       */
+/******************************************************************************************/
+/******************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_block_pool_pointer_convert:
+        BX       LR               ;; return
+
+
+/*****************************************************************************/
+/*****************************************************************************/
+/**                                                                          */
+/**  UCHAR  *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer);         */
+/**                                                                          */
+/*****************************************************************************/
+/*****************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/************************************************************************************/
+/************************************************************************************/
+/**                                                                                 */
+/**  TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer);  */
+/**                                                                                 */
+/************************************************************************************/
+/************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_block_pool_pointer_convert:
+        BX       LR               ;; return
+
+
+/**************************************************************************************/
+/**************************************************************************************/
+/**                                                                                   */
+/**  UCHAR  **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer);        */
+/**                                                                                   */
+/**************************************************************************************/
+/**************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_indirect_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/*****************************************************************************************/
+/*****************************************************************************************/
+/**                                                                                      */
+/**  TX_BYTE_POOL  *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer);          */
+/**                                                                                      */
+/*****************************************************************************************/
+/*****************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_byte_pool_pointer_convert:
+        BX       LR               ;; return
+
+
+/***************************************************************************************/
+/***************************************************************************************/
+/**                                                                                    */
+/**  UCHAR  *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool);         */
+/**                                                                                    */
+/***************************************************************************************/
+/***************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_byte_pool_to_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/*****************************************************************************************/
+/*****************************************************************************************/
+/**                                                                                      */
+/**  ALIGN_TYPE  *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer);         */
+/**                                                                                      */
+/*****************************************************************************************/
+/*****************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_align_type_pointer_convert:
+        BX       LR               ;; return
+
+
+/****************************************************************************************************/
+/****************************************************************************************************/
+/**                                                                                                 */
+/**  TX_BYTE_POOL  **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer);         */
+/**                                                                                                 */
+/****************************************************************************************************/
+/****************************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_indirect_byte_pool_pointer_convert:
+        BX       LR               ;; return
+
+
+/**************************************************************************************************/
+/**************************************************************************************************/
+/**                                                                                               */
+/**  TX_EVENT_FLAGS_GROUP  *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer);         */
+/**                                                                                               */
+/**************************************************************************************************/
+/**************************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_event_flags_pointer_convert:
+        BX       LR               ;; return
+
+
+/*****************************************************************************/
+/*****************************************************************************/
+/**                                                                          */
+/**  ULONG  *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer);         */
+/**                                                                          */
+/*****************************************************************************/
+/*****************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_ulong_pointer_convert:
+        BX       LR               ;; return
+
+
+/********************************************************************************/
+/********************************************************************************/
+/**                                                                             */
+/**  TX_MUTEX  *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer);         */
+/**                                                                             */
+/********************************************************************************/
+/********************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_mutex_pointer_convert:
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  UINT  _tx_misra_status_get(UINT status);                             */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_status_get:
+        MOVS     R0,#+0
+        BX       LR               ;; return
+
+
+/********************************************************************************/
+/********************************************************************************/
+/**                                                                             */
+/**  TX_QUEUE  *_tx_misra_void_to_queue_pointer_convert(VOID *pointer);         */
+/**                                                                             */
+/********************************************************************************/
+/********************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_queue_pointer_convert:
+        BX       LR               ;; return
+
+
+/****************************************************************************************/
+/****************************************************************************************/
+/**                                                                                     */
+/**  TX_SEMAPHORE  *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer);         */
+/**                                                                                     */
+/****************************************************************************************/
+/****************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_semaphore_pointer_convert:
+        BX       LR               ;; return
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/**  VOID  *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer);      */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_void_pointer_convert:
+        BX       LR               ;; return
+
+
+/*********************************************************************************/
+/*********************************************************************************/
+/**                                                                              */
+/**  TX_THREAD  *_tx_misra_ulong_to_thread_pointer_convert(ULONG value);         */
+/**                                                                              */
+/*********************************************************************************/
+/*********************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_ulong_to_thread_pointer_convert:
+        BX       LR               ;; return
+
+
+/***************************************************************************************************/
+/***************************************************************************************************/
+/**                                                                                                */
+/**  VOID  *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer);         */
+/**                                                                                                */
+/***************************************************************************************************/
+/***************************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_timer_indirect_to_void_pointer_convert:
+        BX       LR               ;; return
+
+
+/***************************************************************************************/
+/***************************************************************************************/
+/**                                                                                    */
+/**  CHAR  *_tx_misra_const_char_to_char_pointer_convert(const char *pointer);         */
+/**                                                                                    */
+/***************************************************************************************/
+/***************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_const_char_to_char_pointer_convert:
+        BX       LR               ;; return
+
+
+/**********************************************************************************/
+/**********************************************************************************/
+/**                                                                               */
+/**  TX_THREAD  *_tx_misra_void_to_thread_pointer_convert(void *pointer);         */
+/**                                                                               */
+/**********************************************************************************/
+/**********************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_void_to_thread_pointer_convert:
+        BX       LR               ;; return
+
+
+#ifdef TX_ENABLE_EVENT_TRACE
+
+/************************************************************************************************/
+/************************************************************************************************/
+/**                                                                                             */
+/**  UCHAR  *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer);         */
+/**                                                                                             */
+/************************************************************************************************/
+/************************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_object_to_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/************************************************************************************************/
+/************************************************************************************************/
+/**                                                                                             */
+/**  TX_TRACE_OBJECT_ENTRY  *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer);         */
+/**                                                                                             */
+/************************************************************************************************/
+/************************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_object_pointer_convert:
+        BX       LR               ;; return
+
+
+/******************************************************************************************/
+/******************************************************************************************/
+/**                                                                                       */
+/**  TX_TRACE_HEADER  *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer);         */
+/**                                                                                       */
+/******************************************************************************************/
+/******************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_header_pointer_convert:
+        BX       LR               ;; return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  TX_TRACE_BUFFER_ENTRY  *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer);         */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_uchar_to_entry_pointer_convert:
+        BX       LR               ;; return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  UCHAR  *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer);         */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_entry_to_uchar_pointer_convert:
+        BX       LR               ;; return
+#endif
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  UCHAR  *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer);                           */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_char_to_uchar_pointer_convert:
+        BX       LR               ;; return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  ULONG  _tx_misra_ipsr_get(void);                                                          */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_ipsr_get:
+        MRS      R0, IPSR
+        BX       LR               ;; return
+
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  ULONG  _tx_misra_control_get(void);                                                       */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_control_get:
+        MRS      R0, CONTROL
+        BX       LR               ;; return
+
+        
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  void   _tx_misra_control_set(ULONG value);                                                */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_control_set:
+        MSR      CONTROL, R0
+        BX       LR               ;; return
+
+        
+#ifdef __ARMVFP__
+
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  ULONG  _tx_misra_fpccr_get(void);                                                         */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+_tx_misra_fpccr_get:
+        LDR      r0, =0xE000EF34  ; Build FPCCR address
+        LDR      r0, [r0]         ; Load FPCCR value
+        BX       LR               ;; return
+        
+        
+/***********************************************************************************************/
+/***********************************************************************************************/
+/**                                                                                            */
+/**  void   _tx_misra_vfp_touch(void);                                                         */
+/**                                                                                            */
+/***********************************************************************************************/
+/***********************************************************************************************/
+
+        SECTION `.text`:CODE:NOROOT(1)
+        THUMB
+_tx_misra_vfp_touch:
+        vmov.f32 s0, s0
+        BX       LR               ;; return
+        
+#endif
+        
+        
+        SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2)
+        SECTION_TYPE SHT_PROGBITS, 0
+        DATA
+        DC32 0
+
+        END
diff --git a/ports/cortex_m7/iar/src/tx_thread_context_restore.s b/ports/cortex_m7/iar/src/tx_thread_context_restore.s
new file mode 100644
index 00000000..f671f2d4
--- /dev/null
+++ b/ports/cortex_m7/iar/src/tx_thread_context_restore.s
@@ -0,0 +1,105 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+        EXTERN  _tx_thread_system_state
+        EXTERN  _tx_thread_current_ptr
+        EXTERN  _tx_thread_system_stack_ptr
+        EXTERN  _tx_thread_execute_ptr
+        EXTERN  _tx_timer_time_slice
+        EXTERN  _tx_thread_schedule
+        EXTERN  _tx_thread_preempt_disable
+        EXTERN  _tx_execution_isr_exit
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_context_restore                        Cortex-M7/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function restores the interrupt context if it is processing a  */
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */
+;/*    if no thread was running, the function returns to the scheduler.    */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_schedule                   Thread scheduling routine     */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ISRs                                  Interrupt Service Routines    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_restore(VOID)
+;{
+    PUBLIC  _tx_thread_context_restore
+_tx_thread_context_restore:
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR exit function to indicate an ISR is complete.  */
+;
+    PUSH    {r0,lr}                                 ; Save ISR lr
+    BL      _tx_execution_isr_exit                  ; Call the ISR exit function
+    POP     {r0,lr}                                 ; Restore ISR lr
+#endif
+;
+    POP     {lr}
+    BX      lr
+;
+;}
+        END
+
diff --git a/ports/cortex_m7/iar/src/tx_thread_context_save.s b/ports/cortex_m7/iar/src/tx_thread_context_save.s
new file mode 100644
index 00000000..1febcc18
--- /dev/null
+++ b/ports/cortex_m7/iar/src/tx_thread_context_save.s
@@ -0,0 +1,97 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+        EXTERN  _tx_thread_system_state
+        EXTERN  _tx_thread_current_ptr
+        EXTERN  _tx_execution_isr_enter
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_context_save                           Cortex-M7/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function saves the context of an executing thread in the       */
+;/*    beginning of interrupt processing.  The function also ensures that  */
+;/*    the system stack is used upon return to the calling ISR.            */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ISRs                                                                */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_save(VOID)
+;{
+    PUBLIC  _tx_thread_context_save
+_tx_thread_context_save:
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is starting.  */
+;   
+    PUSH    {r0, lr}                                ; Save return address
+    BL      _tx_execution_isr_enter                 ; Call the ISR enter function
+    POP     {r0, lr}                                ; Recover return address
+#endif
+;
+; /* Context is already saved - just return!  */
+;
+    BX      lr
+;}
+    END
diff --git a/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s
new file mode 100644
index 00000000..2e95e0f7
--- /dev/null
+++ b/ports/cortex_m7/iar/src/tx_thread_interrupt_control.s
@@ -0,0 +1,86 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_control                      Cortex-M7/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for changing the interrupt lockout     */
+;/*    posture of the system.                                              */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    new_posture                           New interrupt lockout posture */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    old_posture                           Old interrupt lockout posture */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_control(UINT new_posture)
+;{
+    PUBLIC  _tx_thread_interrupt_control
+_tx_thread_interrupt_control:
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    MRS     r1, PRIMASK
+    MSR     PRIMASK, r0
+    MOV     r0, r1
+    BX      lr
+;
+;}
+        END
+        
diff --git a/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s
new file mode 100644
index 00000000..e435b0b8
--- /dev/null
+++ b/ports/cortex_m7/iar/src/tx_thread_interrupt_disable.s
@@ -0,0 +1,84 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_restore                      Cortex-M7/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for disabling interrupts and returning */
+;/*    the previous interrupt lockout posture.                             */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    old_posture                           Old interrupt lockout posture */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_disable(UINT new_posture)
+;{
+    PUBLIC  _tx_thread_interrupt_disable
+_tx_thread_interrupt_disable:
+;
+;    /* Return current interrupt lockout posture.  */
+;
+    MRS     r0, PRIMASK
+    CPSID   i
+    BX      lr
+;
+;}
+    END
diff --git a/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s
new file mode 100644
index 00000000..cfdb140d
--- /dev/null
+++ b/ports/cortex_m7/iar/src/tx_thread_interrupt_restore.s
@@ -0,0 +1,83 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_interrupt_restore                      Cortex-M7/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is responsible for restoring the previous             */
+;/*    interrupt lockout posture.                                          */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    previous_posture                      Previous interrupt posture    */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    Application Code                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_interrupt_restore(UINT new_posture)
+;{
+    PUBLIC  _tx_thread_interrupt_restore
+_tx_thread_interrupt_restore:
+;
+;    /* Restore previous interrupt lockout posture.  */
+;
+    MSR     PRIMASK, r0
+    BX      lr
+;
+;}
+    END
diff --git a/ports/cortex_m7/iar/src/tx_thread_schedule.s b/ports/cortex_m7/iar/src/tx_thread_schedule.s
new file mode 100644
index 00000000..4e97613c
--- /dev/null
+++ b/ports/cortex_m7/iar/src/tx_thread_schedule.s
@@ -0,0 +1,291 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;   
+        EXTERN  _tx_thread_current_ptr
+        EXTERN  _tx_thread_execute_ptr
+        EXTERN  _tx_timer_time_slice
+        EXTERN  _tx_thread_system_stack_ptr
+        EXTERN  _tx_execution_thread_enter
+        EXTERN  _tx_execution_thread_exit
+        EXTERN  _tx_thread_preempt_disable
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_schedule                               Cortex-M7/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function waits for a thread control block pointer to appear in */
+;/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
+;/*    in the variable, the corresponding thread is resumed.               */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_initialize_kernel_enter          ThreadX entry function         */
+;/*    _tx_thread_system_return             Return to system from thread   */
+;/*    _tx_thread_context_restore           Restore thread's context       */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_schedule(VOID)
+;{
+    PUBLIC  _tx_thread_schedule
+_tx_thread_schedule:
+;
+;    /* This function should only ever be called on Cortex-M
+;       from the first schedule request. Subsequent scheduling occurs
+;       from the PendSV handling routines below. */
+;
+;    /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets.  */
+;     
+    MOV     r0, #0                                  ; Build value for TX_FALSE
+    LDR     r2, =_tx_thread_preempt_disable         ; Build address of preempt disable flag
+    STR     r0, [r2, #0]                            ; Clear preempt disable flag
+;
+;    /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked.  */
+;
+#ifdef __ARMVFP__
+    MRS     r0, CONTROL                             ; Pickup current CONTROL register
+    BIC     r0, r0, #4                              ; Clear the FPCA bit 
+    MSR     CONTROL, r0                             ; Setup new CONTROL register
+#endif
+;
+;    /* Enable interrupts */
+;
+    CPSIE   i
+;            
+;    /* Enter the scheduler for the first time.  */
+;
+    MOV     r0, #0x10000000                         ; Load PENDSVSET bit
+    MOV     r1, #0xE000E000                         ; Load NVIC base
+    STR     r0, [r1, #0xD04]                        ; Set PENDSVBIT in ICSR
+    DSB                                             ; Complete all memory accesses
+    ISB                                             ; Flush pipeline
+;
+;    /* Wait here for the PendSV to take place.  */
+;     
+__tx_wait_here:
+    B       __tx_wait_here                          ; Wait for the PendSV to happen
+;}
+;
+;    /* Generic context PendSV handler.  */
+;     
+    PUBLIC  PendSV_Handler
+    PUBLIC  __tx_PendSVHandler
+PendSV_Handler:
+__tx_PendSVHandler:
+;
+;    /* Get current thread value and new thread pointer.  */
+;       
+__tx_ts_handler: 
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread exit function to indicate the thread is no longer executing.  */
+;
+    CPSID   i                                       ; Disable interrupts
+    PUSH    {r0, lr}                                ; Save LR (and r0 just for alignment)
+    BL      _tx_execution_thread_exit               ; Call the thread exit function
+    POP     {r0, lr}                                ; Recover LR
+    CPSIE   i                                       ; Enable interrupts
+#endif
+    MOV32   r0, _tx_thread_current_ptr              ; Build current thread pointer address
+    MOV32   r2, _tx_thread_execute_ptr              ; Build execute thread pointer address
+    MOV     r3, #0                                  ; Build NULL value
+    LDR     r1, [r0]                                ; Pickup current thread pointer
+;
+;    /* Determine if there is a current thread to finish preserving.  */
+;       
+    CBZ     r1, __tx_ts_new                         ; If NULL, skip preservation
+;
+;    /* Recover PSP and preserve current thread context.  */
+;
+    STR     r3, [r0]                                ; Set _tx_thread_current_ptr to NULL
+    MRS     r12, PSP                                ; Pickup PSP pointer (thread's stack pointer)
+    STMDB   r12!, {r4-r11}                          ; Save its remaining registers
+#ifdef __ARMVFP__
+    TST     LR, #0x10                               ; Determine if the VFP extended frame is present
+    BNE     _skip_vfp_save
+    VSTMDB  r12!,{s16-s31}                          ; Yes, save additional VFP registers
+_skip_vfp_save:
+#endif
+    MOV32   r4, _tx_timer_time_slice                ; Build address of time-slice variable
+    STMDB   r12!, {LR}                              ; Save LR on the stack
+;
+;    /* Determine if time-slice is active. If it isn't, skip time handling processing.  */
+;
+    LDR     r5, [r4]                                ; Pickup current time-slice
+    STR     r12, [r1, #8]                           ; Save the thread stack pointer
+    CBZ     r5, __tx_ts_new                         ; If not active, skip processing
+;
+;    /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable.  */
+;
+    STR     r5, [r1, #24]                           ; Save current time-slice
+;
+;    /* Clear the global time-slice.  */
+;
+    STR     r3, [r4]                                ; Clear time-slice
+;
+;       
+;    /* Executing thread is now completely preserved!!!  */
+;
+__tx_ts_new:
+;
+;    /* Now we are looking for a new thread to execute!  */
+;
+    CPSID   i                                       ; Disable interrupts
+    LDR     r1, [r2]                                ; Is there another thread ready to execute?
+    CBZ     r1, __tx_ts_wait                        ; No, skip to the wait processing
+;
+;    /* Yes, another thread is ready for else, make the current thread the new thread.  */
+;
+    STR     r1, [r0]                                ; Setup the current thread pointer to the new thread
+    CPSIE   i                                       ; Enable interrupts
+;
+;    /* Increment the thread run count.  */
+;
+__tx_ts_restore:
+    LDR     r7, [r1, #4]                            ; Pickup the current thread run count
+    MOV32   r4, _tx_timer_time_slice                ; Build address of time-slice variable
+    LDR     r5, [r1, #24]                           ; Pickup thread's current time-slice
+    ADD     r7, r7, #1                              ; Increment the thread run count
+    STR     r7, [r1, #4]                            ; Store the new run count
+;
+;    /* Setup global time-slice with thread's current time-slice.  */
+;
+    STR     r5, [r4]                                ; Setup global time-slice
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread entry function to indicate the thread is executing.  */
+;
+    PUSH    {r0, r1}                                ; Save r0/r1
+    BL      _tx_execution_thread_enter              ; Call the thread execution enter function
+    POP     {r0, r1}                                ; Recover r3
+#endif
+;
+;    /* Restore the thread context and PSP.  */
+;
+    LDR     r12, [r1, #8]                           ; Pickup thread's stack pointer
+    LDMIA   r12!, {LR}                              ; Pickup LR
+#ifdef __ARMVFP__
+    TST     LR, #0x10                               ; Determine if the VFP extended frame is present
+    BNE     _skip_vfp_restore                       ; If not, skip VFP restore 
+    VLDMIA  r12!, {s16-s31}                         ; Yes, restore additional VFP registers
+_skip_vfp_restore:
+#endif
+    LDMIA   r12!, {r4-r11}                          ; Recover thread's registers
+    MSR     PSP, r12                                ; Setup the thread's stack pointer
+;
+;    /* Return to thread.  */
+;       
+    BX      lr                                      ; Return to thread!
+;
+;    /* The following is the idle wait processing... in this case, no threads are ready for execution and the
+;       system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts 
+;       are disabled to allow use of WFI for waiting for a thread to arrive.  */
+;
+__tx_ts_wait:
+    CPSID   i                                       ; Disable interrupts
+    LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
+    STR     r1, [r0]                                ; Store it in the current pointer
+    CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+#ifdef TX_ENABLE_WFI
+    DSB                                             ; Ensure no outstanding memory transactions
+    WFI                                             ; Wait for interrupt
+    ISB                                             ; Ensure pipeline is flushed
+#endif
+    CPSIE   i                                       ; Enable interrupts
+    B       __tx_ts_wait                            ; Loop to continue waiting
+;
+;    /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are 
+;       already in the handler!  */
+;
+__tx_ts_ready:
+    MOV     r7, #0x08000000                         ; Build clear PendSV value
+    MOV     r8, #0xE000E000                         ; Build base NVIC address
+    STR     r7, [r8, #0xD04]                        ; Clear any PendSV 
+;
+;    /* Re-enable interrupts and restore new thread.  */
+;       
+    CPSIE   i                                       ; Enable interrupts
+    B       __tx_ts_restore                         ; Restore the thread
+;}
+;
+#ifdef __ARMVFP__
+
+    PUBLIC  tx_thread_fpu_enable
+tx_thread_fpu_enable:
+;
+;    /* Automatic VPF logic is supported, this function is present only for 
+;       backward compatibility purposes and therefore simply returns.  */
+;
+    BX      LR                                      ; Return to caller
+
+    PUBLIC  tx_thread_fpu_disable
+tx_thread_fpu_disable:
+;
+;    /* Automatic VPF logic is supported, this function is present only for 
+;       backward compatibility purposes and therefore simply returns.  */
+;
+    BX      LR                                      ; Return to caller
+
+#endif
+
+    END
+        
diff --git a/ports/cortex_m7/iar/src/tx_thread_stack_build.s b/ports/cortex_m7/iar/src/tx_thread_stack_build.s
new file mode 100644
index 00000000..36518e5e
--- /dev/null
+++ b/ports/cortex_m7/iar/src/tx_thread_stack_build.s
@@ -0,0 +1,144 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_stack_build                            Cortex-M7/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function builds a stack frame on the supplied thread's stack.  */
+;/*    The stack frame results in a fake interrupt return to the supplied  */
+;/*    function pointer.                                                   */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    thread_ptr                            Pointer to thread control blk */
+;/*    function_ptr                          Pointer to return function    */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    _tx_thread_create                     Create thread service         */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+;{
+    PUBLIC  _tx_thread_stack_build
+_tx_thread_stack_build:
+;
+;       
+;    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+;       on the Cortex-M7 should look like the following after it is built:
+;       
+;       Stack Top:      
+;                       LR          Interrupted LR (LR at time of PENDSV)
+;                       r4          Initial value for r4
+;                       r5          Initial value for r5
+;                       r6          Initial value for r6
+;                       r7          Initial value for r7
+;                       r8          Initial value for r8
+;                       r9          Initial value for r9
+;                       r10         Initial value for r10
+;                       r11         Initial value for r11
+;                       r0          Initial value for r0    (Hardware stack starts here!!)
+;                       r1          Initial value for r1
+;                       r2          Initial value for r2
+;                       r3          Initial value for r3
+;                       r12         Initial value for r12
+;                       lr          Initial value for lr
+;                       pc          Initial value for pc
+;                       xPSR        Initial value for xPSR
+;
+;    Stack Bottom: (higher memory address)  */
+;
+    LDR     r2, [r0, #16]                           ; Pickup end of stack area
+    BIC     r2, r2, #0x7                            ; Align frame for 8-byte alignment
+    SUB     r2, r2, #68                             ; Subtract frame size
+    LDR     r3, =0xFFFFFFFD                         ; Build initial LR value
+    STR     r3, [r2, #0]                            ; Save on the stack
+;
+;    /* Actually build the stack frame.  */
+;
+    MOV     r3, #0                                  ; Build initial register value
+    STR     r3, [r2, #4]                            ; Store initial r4
+    STR     r3, [r2, #8]                            ; Store initial r5
+    STR     r3, [r2, #12]                           ; Store initial r6
+    STR     r3, [r2, #16]                           ; Store initial r7
+    STR     r3, [r2, #20]                           ; Store initial r8
+    STR     r3, [r2, #24]                           ; Store initial r9
+    STR     r3, [r2, #28]                           ; Store initial r10
+    STR     r3, [r2, #32]                           ; Store initial r11
+;
+;    /* Hardware stack follows.  /
+;
+    STR     r3, [r2, #36]                           ; Store initial r0
+    STR     r3, [r2, #40]                           ; Store initial r1
+    STR     r3, [r2, #44]                           ; Store initial r2
+    STR     r3, [r2, #48]                           ; Store initial r3
+    STR     r3, [r2, #52]                           ; Store initial r12
+    MOV     r3, #0xFFFFFFFF                         ; Poison EXC_RETURN value
+    STR     r3, [r2, #56]                           ; Store initial lr
+    STR     r1, [r2, #60]                           ; Store initial pc
+    MOV     r3, #0x01000000                         ; Only T-bit need be set
+    STR     r3, [r2, #64]                           ; Store initial xPSR
+;
+;    /* Setup stack pointer.  */
+;    thread_ptr -> tx_thread_stack_ptr =  r2;
+;
+    STR     r2, [r0, #8]                            ; Save stack pointer in thread's
+                                                    ;   control block
+    BX      lr                                      ; Return to caller
+;}
+    END
+
diff --git a/ports/cortex_m7/iar/src/tx_thread_system_return.s b/ports/cortex_m7/iar/src/tx_thread_system_return.s
new file mode 100644
index 00000000..126a9c78
--- /dev/null
+++ b/ports/cortex_m7/iar/src/tx_thread_system_return.s
@@ -0,0 +1,97 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_thread_system_return                          Cortex-M7/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function is target processor specific.  It is used to transfer */
+;/*    control from a thread back to the ThreadX system.  Only a           */
+;/*    minimal context is saved since the compiler assumes temp registers  */
+;/*    are going to get slicked by a function call anyway.                 */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_thread_schedule                   Thread scheduling loop        */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    ThreadX components                                                  */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_system_return(VOID)
+;{
+    PUBLIC  _tx_thread_system_return
+_tx_thread_system_return??rA:
+_tx_thread_system_return:
+;
+;    /* Return to real scheduler via PendSV. Note that this routine is often 
+;       replaced with in-line assembly in tx_port.h to improved performance.  */
+;     
+    MOV     r0, #0x10000000                         ; Load PENDSVSET bit
+    MOV     r1, #0xE000E000                         ; Load NVIC base
+    STR     r0, [r1, #0xD04]                        ; Set PENDSVBIT in ICSR
+    MRS     r0, IPSR                                ; Pickup IPSR
+    CMP     r0, #0                                  ; Is it a thread returning?
+    BNE     _isr_context                            ; If ISR, skip interrupt enable
+    MRS     r1, PRIMASK                             ; Thread context returning, pickup PRIMASK
+    CPSIE   i                                       ; Enable interrupts
+    MSR     PRIMASK, r1                             ; Restore original interrupt posture
+_isr_context:
+    BX      lr                                      ; Return to caller 
+;}
+    END  
diff --git a/ports/cortex_m7/iar/src/tx_timer_interrupt.s b/ports/cortex_m7/iar/src/tx_timer_interrupt.s
new file mode 100644
index 00000000..c900f267
--- /dev/null
+++ b/ports/cortex_m7/iar/src/tx_timer_interrupt.s
@@ -0,0 +1,268 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */
+;/** ThreadX Component                                                     */
+;/**                                                                       */
+;/**   Timer                                                               */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_timer.h"
+;#include "tx_thread.h"
+;
+;
+;Define Assembly language external references...
+;
+    EXTERN      _tx_timer_time_slice
+    EXTERN      _tx_timer_system_clock
+    EXTERN      _tx_timer_current_ptr
+    EXTERN      _tx_timer_list_start
+    EXTERN      _tx_timer_list_end
+    EXTERN      _tx_timer_expired_time_slice
+    EXTERN      _tx_timer_expired
+    EXTERN      _tx_thread_time_slice
+    EXTERN      _tx_timer_expiration_process
+    EXTERN      _tx_thread_current_ptr
+    EXTERN      _tx_thread_execute_ptr
+    EXTERN      _tx_thread_preempt_disable
+;
+;
+        SECTION `.text`:CODE:NOROOT(2)
+        THUMB
+;/**************************************************************************/
+;/*                                                                        */
+;/*  FUNCTION                                               RELEASE        */
+;/*                                                                        */
+;/*    _tx_timer_interrupt                               Cortex-M7/IAR     */
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */
+;/*    This function processes the hardware timer interrupt.  This         */
+;/*    processing includes incrementing the system clock and checking for  */
+;/*    time slice and/or timer expiration.  If either is found, the        */
+;/*    the expiration functions are called.                                */
+;/*                                                                        */
+;/*  INPUT                                                                 */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  OUTPUT                                                                */
+;/*                                                                        */
+;/*    None                                                                */
+;/*                                                                        */
+;/*  CALLS                                                                 */
+;/*                                                                        */
+;/*    _tx_timer_expiration_process          Timer expiration processing   */
+;/*    _tx_thread_time_slice                 Time slice interrupted thread */
+;/*                                                                        */
+;/*  CALLED BY                                                             */
+;/*                                                                        */
+;/*    interrupt vector                                                    */
+;/*                                                                        */
+;/*  RELEASE HISTORY                                                       */
+;/*                                                                        */
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_timer_interrupt(VOID)
+;{
+    PUBLIC  _tx_timer_interrupt
+_tx_timer_interrupt:
+;
+;    /* Upon entry to this routine, it is assumed that the compiler scratch registers are available
+;       for use.  */
+;
+;    /* Increment the system clock.  */
+;    _tx_timer_system_clock++;
+;
+    MOV32   r1, _tx_timer_system_clock              ; Pickup address of system clock
+    LDR     r0, [r1, #0]                            ; Pickup system clock
+    ADD     r0, r0, #1                              ; Increment system clock
+    STR     r0, [r1, #0]                            ; Store new system clock
+;
+;    /* Test for time-slice expiration.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    MOV32   r3, _tx_timer_time_slice                ; Pickup address of time-slice 
+    LDR     r2, [r3, #0]                            ; Pickup time-slice
+    CBZ     r2,  __tx_timer_no_time_slice           ; Is it non-active?
+                                                    ; Yes, skip time-slice processing
+;
+;       /* Decrement the time_slice.  */
+;       _tx_timer_time_slice--;
+;
+    SUB     r2, r2, #1                              ; Decrement the time-slice
+    STR     r2, [r3, #0]                            ; Store new time-slice value
+;
+;       /* Check for expiration.  */
+;       if (__tx_timer_time_slice == 0)
+;
+    CBNZ    r2, __tx_timer_no_time_slice            ; Has it expired?
+;
+;       /* Set the time-slice expired flag.  */
+;       _tx_timer_expired_time_slice =  TX_TRUE;
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup address of expired flag
+    MOV     r0, #1                                  ; Build expired value
+    STR     r0, [r3, #0]                            ; Set time-slice expiration flag
+;
+;    }
+;
+__tx_timer_no_time_slice:
+;
+;    /* Test for timer expiration.  */
+;    if (*_tx_timer_current_ptr)
+;    {
+;
+    MOV32   r1, _tx_timer_current_ptr               ; Pickup current timer pointer address
+    LDR     r0, [r1, #0]                            ; Pickup current timer
+    LDR     r2, [r0, #0]                            ; Pickup timer list entry
+    CBZ     r2, __tx_timer_no_timer                 ; Is there anything in the list?
+                                                    ; No, just increment the timer
+;
+;        /* Set expiration flag.  */
+;        _tx_timer_expired =  TX_TRUE;
+;
+    MOV32   r3, _tx_timer_expired                   ; Pickup expiration flag address
+    MOV     r2, #1                                  ; Build expired value
+    STR     r2, [r3, #0]                            ; Set expired flag
+    B       __tx_timer_done                         ; Finished timer processing
+;
+;    }
+;    else
+;    {
+__tx_timer_no_timer:
+;
+;        /* No timer expired, increment the timer pointer.  */
+;        _tx_timer_current_ptr++;
+;
+    ADD     r0, r0, #4                              ; Move to next timer
+;
+;        /* Check for wrap-around.  */
+;        if (_tx_timer_current_ptr == _tx_timer_list_end)
+;
+    MOV32   r3, _tx_timer_list_end                  ; Pickup addr of timer list end
+    LDR     r2, [r3, #0]                            ; Pickup list end
+    CMP     r0, r2                                  ; Are we at list end?
+    BNE     __tx_timer_skip_wrap                    ; No, skip wrap-around logic
+;
+;            /* Wrap to beginning of list.  */
+;            _tx_timer_current_ptr =  _tx_timer_list_start;
+;
+    MOV32   r3, _tx_timer_list_start                ; Pickup addr of timer list start
+    LDR     r0, [r3, #0]                            ; Set current pointer to list start
+;
+__tx_timer_skip_wrap:
+;
+    STR     r0, [r1, #0]                            ; Store new current timer pointer
+;    }
+;
+__tx_timer_done:
+;
+;
+;    /* See if anything has expired.  */
+;    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+;    {
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup addr of expired flag
+    LDR     r2, [r3, #0]                            ; Pickup time-slice expired flag
+    CBNZ    r2, __tx_something_expired              ; Did a time-slice expire?
+                                                    ; If non-zero, time-slice expired
+    MOV32   r1, _tx_timer_expired                   ; Pickup addr of other expired flag
+    LDR     r0, [r1, #0]                            ; Pickup timer expired flag
+    CBZ     r0, __tx_timer_nothing_expired          ; Did a timer expire?
+                                                    ; No, nothing expired
+;
+__tx_something_expired:
+;
+;
+    STMDB   sp!, {r0, lr}                           ; Save the lr register on the stack
+                                                    ;   and save r0 just to keep 8-byte alignment
+;
+;    /* Did a timer expire?  */
+;    if (_tx_timer_expired)
+;    {
+;
+    MOV32   r1, _tx_timer_expired                   ; Pickup addr of expired flag
+    LDR     r0, [r1, #0]                            ; Pickup timer expired flag
+    CBZ     r0, __tx_timer_dont_activate            ; Check for timer expiration
+                                                    ; If not set, skip timer activation
+;
+;        /* Process timer expiration.  */
+;        _tx_timer_expiration_process();
+;
+    BL      _tx_timer_expiration_process            ; Call the timer expiration handling routine
+;
+;    }
+__tx_timer_dont_activate:
+;
+;    /* Did time slice expire?  */
+;    if (_tx_timer_expired_time_slice)
+;    {
+;
+    MOV32   r3, _tx_timer_expired_time_slice        ; Pickup addr of time-slice expired 
+    LDR     r2, [r3, #0]                            ; Pickup the actual flag
+    CBZ     r2, __tx_timer_not_ts_expiration        ; See if the flag is set
+                                                    ; No, skip time-slice processing
+;
+;        /* Time slice interrupted thread.  */
+;        _tx_thread_time_slice(); 
+
+    BL      _tx_thread_time_slice                   ; Call time-slice processing
+    MOV32   r0, _tx_thread_preempt_disable          ; Build address of preempt disable flag
+    LDR     r1, [r0]                                ; Is the preempt disable flag set?
+    CBNZ    r1, __tx_timer_skip_time_slice          ; Yes, skip the PendSV logic
+    MOV32   r0, _tx_thread_current_ptr              ; Build current thread pointer address
+    LDR     r1, [r0]                                ; Pickup the current thread pointer
+    MOV32   r2, _tx_thread_execute_ptr              ; Build execute thread pointer address
+    LDR     r3, [r2]                                ; Pickup the execute thread pointer
+    MOV32   r0, 0xE000ED04                          ; Build address of control register
+    MOV32   r2, 0x10000000                          ; Build value for PendSV bit
+    CMP     r1, r3                                  ; Are they the same?
+    BEQ     __tx_timer_skip_time_slice              ; If the same, there was no time-slice performed
+    STR     r2, [r0]                                ; Not the same, issue the PendSV for preemption
+__tx_timer_skip_time_slice:
+;
+;    }
+;
+__tx_timer_not_ts_expiration:
+;
+    LDMIA   sp!, {r0, lr}                           ; Recover lr register (r0 is just there for
+                                                    ;   the 8-byte stack alignment
+;
+;    }
+;
+__tx_timer_nothing_expired:
+
+    DSB                                             ; Complete all memory access
+    BX      lr                                      ; Return to caller
+;
+;}
+    END
+
diff --git a/ports/cortex_r4/ac5/example_build/build_threadx.bat b/ports/cortex_r4/ac5/example_build/build_threadx.bat
new file mode 100644
index 00000000..74f59d4d
--- /dev/null
+++ b/ports/cortex_r4/ac5/example_build/build_threadx.bat
@@ -0,0 +1,238 @@
+del tx.a
+armasm -g --cpu=cortex-r4 --apcs=interwork tx_initialize_low_level.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_stack_build.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_schedule.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_system_return.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_context_save.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_context_restore.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_interrupt_control.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_timer_interrupt.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_fiq_context_restore.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_fiq_context_save.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_fiq_nesting_end.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_fiq_nesting_start.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_interrupt_disable.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_interrupt_restore.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_irq_nesting_end.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_irq_nesting_start.s
+armasm -g --cpu=cortex-r4 --apcs=interwork ../src/tx_thread_vectored_context_save.s
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c
+armcc -g --cpu=cortex-r4 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c
+armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
+armar -r tx.a tx_initialize_low_level.o tx_thread_fiq_context_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_end.o tx_thread_fiq_nesting_start.o tx_thread_interrupt_disable.o 
+armar -r tx.a tx_thread_interrupt_restore.o tx_thread_irq_nesting_end.o tx_thread_irq_nesting_start.o
+armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
+armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
+armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
+armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
+armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
+armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
+armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
+armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
+armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
+armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o 
+armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
+armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
+armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
+armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
+armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
+armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
+armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
+armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
+armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
+armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
+armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o 
+armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
+armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
+armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o 
+armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o 
+armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o 
+armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
+armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
+armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
+armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
+armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o 
+armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
+armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o
diff --git a/ports/cortex_r4/ac5/example_build/build_threadx_sample.bat b/ports/cortex_r4/ac5/example_build/build_threadx_sample.bat
new file mode 100644
index 00000000..20c1b323
--- /dev/null
+++ b/ports/cortex_r4/ac5/example_build/build_threadx_sample.bat
@@ -0,0 +1,4 @@
+armasm -g --cpu=cortex-r4 --apcs=interwork tx_initialize_low_level.s
+armcc -c -g --cpu=cortex-r4 -I../../../../common/inc -I../inc sample_threadx.c
+armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --rw-base=0x20000000 --first tx_initialize_low_level.o(Init) --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a
+
diff --git a/ports/cortex_r4/ac5/example_build/sample_threadx.c b/ports/cortex_r4/ac5/example_build/sample_threadx.c
new file mode 100644
index 00000000..418ec634
--- /dev/null
+++ b/ports/cortex_r4/ac5/example_build/sample_threadx.c
@@ -0,0 +1,369 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include "tx_api.h"
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_BYTE_POOL_SIZE     9120
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+/* Define main entry point.  */
+
+int main()
+{
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/cortex_r4/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_r4/ac5/example_build/tx_initialize_low_level.s
new file mode 100644
index 00000000..330e7865
--- /dev/null
+++ b/ports/cortex_r4/ac5/example_build/tx_initialize_low_level.s
@@ -0,0 +1,394 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Initialize                                                          */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_initialize.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+DISABLE_INTS    EQU     0xC0                    ; Disable IRQ & FIQ interrupts
+FIQ_MODE        EQU     0xD1                    ; FIQ mode
+IRQ_MODE        EQU     0xD2                    ; IRQ mode
+SVC_MODE        EQU     0xD3                    ; SVC mode
+SYS_MODE        EQU     0xDF                    ; SYS mode
+    ELSE
+DISABLE_INTS    EQU     0x80                    ; Disable IRQ interrupts
+FIQ_MODE        EQU     0x91                    ; FIQ mode
+IRQ_MODE        EQU     0x92                    ; IRQ mode
+SVC_MODE        EQU     0x93                    ; SVC mode
+SYS_MODE        EQU     0x9F                    ; SYS mode
+    ENDIF
+HEAP_SIZE       EQU     4096                    ; Heap size
+FIQ_STACK_SIZE  EQU     512                     ; FIQ stack size
+SYS_STACK_SIZE  EQU     1024                    ; SYS stack size (used for nested interrupts)
+IRQ_STACK_SIZE  EQU     1024                    ; IRQ stack size
+;
+;
+    IMPORT      _tx_thread_system_stack_ptr
+    IMPORT      _tx_initialize_unused_memory
+    IMPORT      _tx_thread_context_save
+    IMPORT      _tx_thread_context_restore
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+    IMPORT      _tx_thread_fiq_context_save
+    IMPORT      _tx_thread_fiq_context_restore
+    ENDIF
+    IF  :DEF:TX_ENABLE_IRQ_NESTING
+    IMPORT      _tx_thread_irq_nesting_start
+    IMPORT      _tx_thread_irq_nesting_end
+    ENDIF
+    IF  :DEF:TX_ENABLE_FIQ_NESTING
+    IMPORT      _tx_thread_fiq_nesting_start
+    IMPORT      _tx_thread_fiq_nesting_end
+    ENDIF
+    IMPORT      _tx_timer_interrupt
+    IMPORT      __main
+    IMPORT      _tx_version_id
+    IMPORT      _tx_build_options
+    IMPORT      |Image$$ZI$$Limit|
+;
+;
+        AREA  Init, CODE, READONLY
+;
+;/* Define the default Cortex-R4 vector area.  This should be located or copied to 0.  */
+;
+    EXPORT  __vectors
+__vectors
+    LDR     pc,=__main                          ; Reset goes to startup function
+    LDR     pc,=__tx_undefined                  ; Undefined handler
+    LDR     pc,=__tx_swi_interrupt              ; Software interrupt handler
+    LDR     pc,=__tx_prefetch_handler           ; Prefetch exception handler
+    LDR     pc,=__tx_abort_handler              ; Abort exception handler
+    LDR     pc,=__tx_reserved_handler           ; Reserved exception handler
+    LDR     pc,=__tx_irq_handler                ; IRQ interrupt handler
+    LDR     pc,=__tx_fiq_handler                ; FIQ interrupt handler
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_low_level                           Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for any low-level processor            */ 
+;/*    initialization, including setting up interrupt vectors, setting     */ 
+;/*    up a periodic timer interrupt source, saving the system stack       */ 
+;/*    pointer for use in ISR processing later, and finding the first      */ 
+;/*    available RAM memory address for tx_application_define.             */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_initialize_low_level(VOID)
+;{
+    EXPORT  _tx_initialize_low_level
+_tx_initialize_low_level
+;
+;
+;    /****** NOTE ****** We must be in SVC MODE at this point.  Some monitors
+;       enter this routine in USER mode and require a software interrupt to
+;       change into SVC mode.  */
+;
+    LDR     r1, =|Image$$ZI$$Limit|             ; Get end of non-initialized RAM area
+    LDR     r2, =HEAP_SIZE                      ; Pickup the heap size
+    ADD     r1, r2, r1                          ; Setup heap limit
+    ADD     r1, r1, #4                          ; Setup stack limit
+;
+    IF :DEF:TX_ENABLE_IRQ_NESTING
+;    /* Setup the system mode stack for nested interrupt support  */
+    LDR     r2, =SYS_STACK_SIZE                 ; Pickup stack size
+    MOV     r3, #SYS_MODE                       ; Build SYS mode CPSR
+    MSR     CPSR_c, r3                          ; Enter SYS mode
+    ADD     r1, r1, r2                          ; Calculate start of SYS stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    MOV     sp, r1                              ; Setup SYS stack pointer
+    ENDIF
+;
+    LDR     r2, =FIQ_STACK_SIZE                 ; Pickup stack size
+    MOV     r0, #FIQ_MODE                       ; Build FIQ mode CPSR
+    MSR     CPSR_c, r0                          ; Enter FIQ mode
+    ADD     r1, r1, r2                          ; Calculate start of FIQ stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    MOV     sp, r1                              ; Setup FIQ stack pointer
+    MOV     sl, #0                              ; Clear sl
+    MOV     fp, #0                              ; Clear fp
+    LDR     r2, =IRQ_STACK_SIZE                 ; Pickup IRQ (system stack size)
+    MOV     r0, #IRQ_MODE                       ; Build IRQ mode CPSR
+    MSR     CPSR_c, r0                          ; Enter IRQ mode
+    ADD     r1, r1, r2                          ; Calculate start of IRQ stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    MOV     sp, r1                              ; Setup IRQ stack pointer
+    MOV     r0, #SVC_MODE                       ; Build SVC mode CPSR
+    MSR     CPSR_c, r0                          ; Enter SVC mode
+    LDR     r3, =_tx_thread_system_stack_ptr    ; Pickup stack pointer
+    STR     r1, [r3, #0]                        ; Save the system stack
+;
+;    /* Save the system stack pointer.  */
+;    _tx_thread_system_stack_ptr = (VOID_PTR) (sp);
+;
+    LDR     r1, =_tx_thread_system_stack_ptr    ; Pickup address of system stack ptr
+    LDR     r0, [r1, #0]                        ; Pickup system stack 
+    ADD     r0, r0, #4                          ; Increment to next free word
+;
+;    /* Save the first available memory address.  */
+;    _tx_initialize_unused_memory =  (VOID_PTR) |Image$$ZI$$Limit| + HEAP + [SYS_STACK] + FIQ_STACK + IRQ_STACK;
+;
+    LDR     r2, =_tx_initialize_unused_memory   ; Pickup unused memory ptr address
+    STR     r0, [r2, #0]                        ; Save first free memory address
+;
+;    /* Setup Timer for periodic interrupts.  */
+;
+;    /* Done, return to caller.  */
+;
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;}
+;
+;
+;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code.  This
+;   routine will set the initial stack to use the ThreadX IRQ & FIQ & 
+;   (optionally SYS) stack areas.  */
+;
+    EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+    LDR     r0, =|Image$$ZI$$Limit|             ; Get end of non-initialized RAM area
+    LDR     r2, =HEAP_SIZE                      ; Pickup the heap size
+    ADD     r2, r2, r0                          ; Setup heap limit
+    ADD     r3, r2, #4                          ; Setup stack limit
+    MOV     r1, r3                              ; Setup start of stack
+    IF :DEF:TX_ENABLE_IRQ_NESTING
+    LDR     r12, =SYS_STACK_SIZE                ; Pickup IRQ system stack
+    ADD     r1, r1, r12                         ; Setup the return system stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    ENDIF
+    LDR     r12, =FIQ_STACK_SIZE                ; Pickup FIQ stack size
+    ADD     r1, r1, r12                         ; Setup the return system stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    LDR     r12, =IRQ_STACK_SIZE                ; Pickup IRQ system stack
+    ADD     r1, r1, r12                         ; Setup the return system stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+;
+;/* Define shells for each of the interrupt vectors.  */
+;
+    EXPORT  __tx_undefined
+__tx_undefined
+    B       __tx_undefined                      ; Undefined handler
+;
+    EXPORT  __tx_swi_interrupt
+__tx_swi_interrupt
+    B       __tx_swi_interrupt                  ; Software interrupt handler
+;
+    EXPORT  __tx_prefetch_handler
+__tx_prefetch_handler
+    B       __tx_prefetch_handler               ; Prefetch exception handler
+;
+    EXPORT  __tx_abort_handler
+__tx_abort_handler
+    B       __tx_abort_handler                  ; Abort exception handler
+;
+    EXPORT  __tx_reserved_handler
+__tx_reserved_handler
+    B       __tx_reserved_handler               ; Reserved exception handler
+;
+;
+    EXPORT  __tx_irq_handler
+    EXPORT  __tx_irq_processing_return      
+__tx_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return
+;
+;    /* At this point execution is still in the IRQ mode.  The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  In 
+;       addition, IRQ interrupts may be re-enabled - with certain restrictions -
+;       if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
+;       small code sequences where lr is saved before enabling interrupts and 
+;       restored after interrupts are again disabled.  */
+;
+;
+    BL      _tx_timer_interrupt                 ; Timer interrupt handler
+_tx_not_timer_interrupt
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start 
+;       from IRQ mode with interrupts disabled.  This routine switches to the
+;       system mode and returns with IRQ interrupts enabled.  
+;       
+;       NOTE:  It is very important to ensure all IRQ interrupts are cleared 
+;       prior to enabling nested IRQ interrupts.  */
+    IF :DEF:TX_ENABLE_IRQ_NESTING
+    BL      _tx_thread_irq_nesting_start
+    ENDIF
+;
+;
+;    /* Application IRQ handlers can be called here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_context_restore.  
+;       This routine returns in processing in IRQ mode with interrupts disabled.  */
+    IF :DEF:TX_ENABLE_IRQ_NESTING
+    BL      _tx_thread_irq_nesting_end
+    ENDIF
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+;
+;
+;    /* This is an example of a vectored IRQ handler.  */
+;
+    EXPORT  __tx_example_vectored_irq_handler
+__tx_example_vectored_irq_handler
+;
+;
+;    /* Save initial context and call context save to prepare for 
+;       vectored ISR execution.  */
+;
+;    STMDB   sp!, {r0-r3}                        ; Save some scratch registers
+;    MRS     r0, SPSR                            ; Pickup saved SPSR
+;    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+;    STMDB   sp!, {r0, r10, r12, lr}             ; Store other scratch registers
+;    BL      _tx_thread_vectored_context_save    ; Vectored context save
+;
+;    /* At this point execution is still in the IRQ mode.  The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  In 
+;       addition, IRQ interrupts may be re-enabled - with certain restrictions -
+;       if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
+;       small code sequences where lr is saved before enabling interrupts and 
+;       restored after interrupts are again disabled.  */
+;
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start 
+;       from IRQ mode with interrupts disabled.  This routine switches to the
+;       system mode and returns with IRQ interrupts enabled.  
+;       
+;       NOTE:  It is very important to ensure all IRQ interrupts are cleared 
+;       prior to enabling nested IRQ interrupts.  */
+;    IF :DEF:TX_ENABLE_IRQ_NESTING
+;    BL      _tx_thread_irq_nesting_start
+;    ENDIF
+;
+;    /* Application IRQ handlers can be called here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_context_restore.  
+;       This routine returns in processing in IRQ mode with interrupts disabled.  */
+;    IF :DEF:TX_ENABLE_IRQ_NESTING
+;    BL      _tx_thread_irq_nesting_end
+;    ENDIF
+;
+;    /* Jump to context restore to restore system context.  */
+;    B       _tx_thread_context_restore
+;
+;
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+    EXPORT  __tx_fiq_handler
+    EXPORT  __tx_fiq_processing_return
+__tx_fiq_handler
+;
+;    /* Jump to fiq context save to save system context.  */
+    B       _tx_thread_fiq_context_save
+__tx_fiq_processing_return
+;
+;    /* At this point execution is still in the FIQ mode.  The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  */
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start 
+;       from FIQ mode with interrupts disabled.  This routine switches to the
+;       system mode and returns with FIQ interrupts enabled. 
+;
+;       NOTE:  It is very important to ensure all FIQ interrupts are cleared 
+;       prior to enabling nested FIQ interrupts.  */
+    IF  :DEF:TX_ENABLE_FIQ_NESTING
+    BL      _tx_thread_fiq_nesting_start
+    ENDIF
+;
+;    /* Application FIQ handlers can be called here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_fiq_context_restore.  */
+    IF  :DEF:TX_ENABLE_FIQ_NESTING
+    BL      _tx_thread_fiq_nesting_end
+    ENDIF
+;
+;    /* Jump to fiq context restore to restore system context.  */
+    B       _tx_thread_fiq_context_restore
+;
+;
+    ELSE
+    EXPORT  __tx_fiq_handler
+__tx_fiq_handler
+    B       __tx_fiq_handler                    ; FIQ interrupt handler
+    ENDIF
+;
+;    /* Reference build options and version ID to ensure they come in.  */
+;
+    LDR     r2, =_tx_build_options              ; Pickup build options variable address
+    LDR     r0, [r2, #0]                        ; Pickup build options content
+    LDR     r2, =_tx_version_id                 ; Pickup version ID variable address
+    LDR     r0, [r2, #0]                        ; Pickup version ID content
+;
+;
+    END
+
diff --git a/ports/cortex_r4/ac5/inc/tx_port.h b/ports/cortex_r4/ac5/inc/tx_port.h
new file mode 100644
index 00000000..75238e40
--- /dev/null
+++ b/ports/cortex_r4/ac5/inc/tx_port.h
@@ -0,0 +1,335 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */ 
+/*                                                                        */ 
+/*    tx_port.h                                          Cortex-R4/AC5    */ 
+/*                                                           6.0.1        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This file contains data type definitions that make the ThreadX      */ 
+/*    real-time kernel function identically on a variety of different     */ 
+/*    processor architectures.  For example, the size or number of bits   */ 
+/*    in an "int" data type vary between microprocessor architectures and */ 
+/*    even C compilers for the same microprocessor.  ThreadX does not     */ 
+/*    directly use native C data types.  Instead, ThreadX creates its     */ 
+/*    own special types that can be mapped to actual data types by this   */ 
+/*    file to guarantee consistency in the interface and functionality.   */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include 
+#include 
+
+
+/* Define ThreadX basic types for this port.  */ 
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */ 
+#endif
+
+
+/* Define various constants for the ThreadX ARM port.  */ 
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_INT_DISABLE                          0xC0        /* Disable IRQ & FIQ interrupts     */
+#else
+#define TX_INT_DISABLE                          0x80        /* Disable IRQ interrupts           */
+#endif
+#define TX_INT_ENABLE                           0x00        /* Enable IRQ interrupts            */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ++_tx_trace_simulated_time
+#endif
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_FIQ_ENABLED                          1
+#else
+#define TX_FIQ_ENABLED                          0
+#endif
+
+#ifdef TX_ENABLE_IRQ_NESTING
+#define TX_IRQ_NESTING_ENABLED                  2
+#else
+#define TX_IRQ_NESTING_ENABLED                  0
+#endif
+
+#ifdef TX_ENABLE_FIQ_NESTING
+#define TX_FIQ_NESTING_ENABLED                  4
+#else
+#define TX_FIQ_NESTING_ENABLED                  0
+#endif
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#define TX_INLINE_INITIALIZATION
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#define TX_THREAD_EXTENSION_2                  ULONG       tx_thread_vfp_enable;
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef __thumb
+
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       m = m & ((ULONG) (-((LONG) m))); \
+                                                b = (ULONG) __clz((unsigned int) m); \
+                                                b = 31 - b; 
+#endif
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifndef __thumb
+
+#define TX_INTERRUPT_SAVE_AREA                  register unsigned int interrupt_save_disabled;
+
+#ifdef  TX_ENABLE_FIQ_SUPPORT
+
+/* IRQ and FIQ support.  */
+
+#define TX_DISABLE                              __memory_changed(), interrupt_save_disabled =  __disable_irq(); \
+                                                __disable_fiq();
+
+#define TX_RESTORE                              if (!interrupt_save_disabled) \
+                                                { \
+                                                    __enable_irq(); \
+                                                    __enable_fiq(); \
+                                                } 
+
+#else
+
+#define TX_DISABLE                              __memory_changed(), interrupt_save_disabled =  __disable_irq();
+
+#define TX_RESTORE                              if (!interrupt_save_disabled) \
+                                                { \
+                                                    __enable_irq(); \
+                                                } 
+#endif
+
+#else
+
+unsigned int   _tx_thread_interrupt_disable(void);
+unsigned int   _tx_thread_interrupt_restore(UINT old_posture);
+
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int interrupt_save;
+
+#define TX_DISABLE                              interrupt_save =  _tx_thread_interrupt_disable();
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+#endif
+
+
+/* Define VFP extension for the Cortex-R4.  Each is assumed to be called in the context of the executing
+   thread.  */
+
+void    tx_thread_vfp_enable(void);
+void    tx_thread_vfp_disable(void);
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX  Cortex-R4/AC5 Version 6.0 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+
+#endif
+
+
diff --git a/ports/cortex_r4/ac5/readme_threadx.txt b/ports/cortex_r4/ac5/readme_threadx.txt
new file mode 100644
index 00000000..93ef3dbc
--- /dev/null
+++ b/ports/cortex_r4/ac5/readme_threadx.txt
@@ -0,0 +1,549 @@
+                     Microsoft's Azure RTOS ThreadX for Cortex-R4 
+
+                               Thumb & 32-bit Mode
+
+                            Using ARM Compiler 5 (AC5)
+
+1.  Building the ThreadX run-time Library
+
+First make sure you are in the "example_build" directory. Also, make sure that 
+you have setup your path and other environment variables necessary for the ARM 
+AC5 development environment. At this point you may run the build_threadx.bat 
+batch file. This will build the ThreadX run-time environment in the 
+"example_build" directory. 
+
+You should observe assembly and compilation of a series of ThreadX source 
+files. At the end of the batch file, they are all combined into the 
+run-time library file: tx.a. This file must be linked with your 
+application in order to use ThreadX.
+
+1.1  Building with Project Files
+
+The ThreadX library can also be built via project files. Simply open 
+the tx.mcp file with project builder and select make. This will place 
+the tx.a library file into the Debug sub-directory.
+
+
+2.  Demonstration System
+
+The ThreadX demonstration is designed to execute under the ARM
+Windows-based simulator.
+
+Building the demonstration is easy; simply execute the build_threadx_demo.bat 
+batch file while inside the "example_build" directory. 
+
+You should observe the compilation of sample_threadx.c (which is the demonstration 
+application) and linking with tx.a. The resulting file sample_threadx.axf 
+is a binary file that can be downloaded and executed on the ARM simulator.
+
+2.0.1  Building with Project Files
+
+The ThreadX demonstration can also be built via project files. Simply open 
+the sample_threadx.mcp file with project builder and select make. This will place 
+the sample_threadx.axf output image into the Debug sub-directory.
+
+
+3.  System Initialization
+
+The entry point in ThreadX for the Cortex-R4 using AC5 tools is at label 
+__main. This is defined within the AC5 compiler's startup code. In 
+addition, this is where all static and global pre-set C variable 
+initialization processing takes place.
+
+The ThreadX tx_initialize_low_level.s file is responsible for setting up 
+various system data structures, the vector area, and a periodic timer interrupt 
+source. By default, the vector area is defined to be located in the Init area, 
+which is defined at the top of tx_initialize_low_level.s. This area is typically 
+located at 0. In situations where this is impossible, the vectors at the beginning 
+of the Init area should be copied to address 0.
+
+This is also where initialization of a periodic timer interrupt source
+should take place.
+
+In addition, _tx_initialize_low_level determines the first available 
+address for use by the application, which is supplied as the sole input 
+parameter to your application definition function, tx_application_define.
+
+
+4.  Assembler / Compiler Switches
+
+The following are compiler switches used in building the demonstration 
+system:
+
+Compiler Switch                 Meaning
+
+    -g                  Specifies debug information
+    -c                  Specifies object code generation
+    --cpu Cortex-R4     Specifies Cortex-R4 instruction set
+    --apcs /interwork   Specifies Thumb/32-bit compatibility
+
+Linker Switch                   Meaning
+
+    -d                  Specifies to retain debug information in output file
+    -o demo.axf         Specifies demo output file name
+    --elf               Specifies elf output file format
+    --ro                Specifies that Read-Only memory starts at address 0
+    --first tx_initialize_low_level.o(Init) 
+                        Specifies that the first area loaded is Init
+    --remove            Remove unused areas
+    --list              Specifies map file name 
+    --symbols           Specifies symbols for map file
+    --map               Creates a map file
+
+Application Defines
+
+    --PD "TX_ENABLE_FIQ_SUPPORT SETL {TRUE}"    This assembler define enables FIQ
+                                                interrupt handling support in the
+                                                ThreadX assembly files. If used,
+                                                it should be used on all assembly
+                                                files and the generic C source of
+                                                ThreadX should be compiled with 
+                                                TX_ENABLE_FIQ_SUPPORT defined as well.
+    --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}"    This assembler define enables IRQ
+                                                nested support. If IRQ nested 
+                                                interrupt support is needed, this
+                                                define should be applied to 
+                                                tx_initialize_low_level.s.
+    --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}"    This assembler define enables FIQ
+                                                nested support. If FIQ nested 
+                                                interrupt support is needed, this
+                                                define should be applied to 
+                                                tx_initialize_low_level.s. In addition,
+                                                IRQ nesting should also be enabled.
+    -DTX_ENABLE_FIQ_SUPPORT                     This compiler define enables FIQ
+                                                interrupt handling in the ThreadX
+                                                generic C source. This define 
+                                                should also be used in conjunction
+                                                with the corresponding assembler
+                                                define.                                               
+    -DTX_DISABLE_ERROR_CHECKING                 If defined before tx_api.h is included,
+                                                this define causes basic ThreadX error
+                                                checking to be disabled. Please see
+                                                Chapter 2 in the "ThreadX User Guide" 
+                                                for more details.
+
+    -DTX_MAX_PRIORITIES                         Defines the priority levels for ThreadX. 
+                                                Legal values range from 32 through 
+                                                1024 (inclusive) and MUST be evenly divisible 
+                                                by 32. Increasing the number of priority levels 
+                                                supported increases the RAM usage by 128 bytes 
+                                                for every group of 32 priorities. However, there 
+                                                is only a negligible effect on performance. By 
+                                                default, this value is set to 32 priority levels.
+
+    -DTX_MINIMUM_STACK                          Defines the minimum stack size (in bytes). It is 
+                                                used for error checking when threads are created. 
+                                                The default value is port-specific and is found 
+                                                in tx_port.h.
+
+    -DTX_TIMER_THREAD_STACK_SIZE                Defines the stack size (in bytes) of the internal 
+                                                ThreadX timer thread. This thread processes all 
+                                                thread sleep requests as well as all service call 
+                                                timeouts. In addition, all application timer callback 
+                                                routines are invoked from this context. The default 
+                                                value is port-specific and is found in tx_port.h.
+
+    -DTX_TIMER_THREAD_PRIORITY                  Defines the priority of the internal ThreadX timer 
+                                                thread. The default value is priority 0 - the highest 
+                                                priority in ThreadX. The default value is defined 
+                                                in tx_port.h.
+
+    -DTX_TIMER_PROCESS_IN_ISR                   Defined, this option eliminates the internal system 
+                                                timer thread for ThreadX. This results in improved 
+                                                performance on timer events and smaller RAM requirements 
+                                                because the timer stack and control block are no 
+                                                longer needed. However, using this option moves all 
+                                                the timer expiration processing to the timer ISR level. 
+                                                By default, this option is not defined.
+
+    -DTX_REACTIVATE_INLINE                      Defined, this option performs reactivation of ThreadX 
+                                                timers in-line instead of using a function call. This 
+                                                improves performance but slightly increases code size. 
+                                                By default, this option is not defined.
+
+    -DTX_DISABLE_STACK_FILLING                  Defined, placing the 0xEF value in each byte of each 
+                                                thread's stack is disabled. By default, this option is 
+                                                not defined.
+
+    -DTX_ENABLE_STACK_CHECKING                  Defined, this option enables ThreadX run-time stack checking, 
+                                                which includes analysis of how much stack has been used and 
+                                                examination of data pattern "fences" before and after the 
+                                                stack area. If a stack error is detected, the registered 
+                                                application stack error handler is called. This option does 
+                                                result in slightly increased overhead and code size. Please 
+                                                review the tx_thread_stack_error_notify API for more information. 
+                                                By default, this option is not defined.
+
+    -DTX_DISABLE_PREEMPTION_THRESHOLD           Defined, this option disables the preemption-threshold feature 
+                                                and slightly reduces code size and improves performance. Of course, 
+                                                the preemption-threshold capabilities are no longer available. 
+                                                By default, this option is not defined.
+
+    -DTX_DISABLE_REDUNDANT_CLEARING             Defined, this option removes the logic for initializing ThreadX 
+                                                global C data structures to zero. This should only be used if 
+                                                the compiler's initialization code sets all un-initialized 
+                                                C global data to zero. Using this option slightly reduces 
+                                                code size and improves performance during initialization. 
+                                                By default, this option is not defined.
+
+    -DTX_DISABLE_NOTIFY_CALLBACKS               Defined, this option disables the notify callbacks for various 
+                                                ThreadX objects. Using this option slightly reduces code size 
+                                                and improves performance.
+
+    -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO     Defined, this option enables the gathering of performance 
+                                                information on block pools. By default, this option is 
+                                                not defined.
+
+    -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO      Defined, this option enables the gathering of performance 
+                                                information on byte pools. By default, this option is 
+                                                not defined.
+
+    -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO    Defined, this option enables the gathering of performance 
+                                                information on event flags groups. By default, this option 
+                                                is not defined.
+
+    -DTX_MUTEX_ENABLE_PERFORMANCE_INFO          Defined, this option enables the gathering of performance 
+                                                information on mutexes. By default, this option is 
+                                                not defined.
+
+    -DTX_QUEUE_ENABLE_PERFORMANCE_INFO          Defined, this option enables the gathering of performance 
+                                                information on queues. By default, this option is 
+                                                not defined.
+
+    -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO      Defined, this option enables the gathering of performance 
+                                                information on semaphores. By default, this option is 
+                                                not defined.
+
+    -DTX_THREAD_ENABLE_PERFORMANCE_INFO         Defined, this option enables the gathering of performance 
+                                                information on threads. By default, this option is 
+                                                not defined.
+
+    -DTX_TIMER_ENABLE_PERFORMANCE_INFO          Defined, this option enables the gathering of performance 
+                                                information on timers. By default, this option is 
+                                                not defined.
+
+    -DTX_ENABLE_EVENT_TRACE                     Defined, this option enables the internal ThreadX trace
+                                                feature. The trace buffer is supplied at a later time
+                                                via an application call to tx_trace_enable.
+
+    -DTX_TRACE_TIME_SOURCE                      This defines the time-stamp source for event tracing. 
+                                                This define is only pertinent if the ThreadX library is 
+                                                built with TX_ENABLE_EVENT_TRACE defined.
+
+    -DTX_TRACE_TIME_MASK                        This defines the number of valid bits in the event trace 
+                                                time-stamp source defined previously. If the time-stamp 
+                                                source is 16-bits, this value should be 0xFFFF. Alternatively, 
+                                                if the time-stamp source is 32-bits, this value should be 
+                                                0xFFFFFFFF. This define is only pertinent if the ThreadX 
+                                                library is built with TX_ENABLE_EVENT_TRACE defined.
+
+
+
+5.  Register Usage and Stack Frames
+
+The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch 
+registers for each function. All other registers used by a C function must 
+be preserved by the function. ThreadX takes advantage of this in situations 
+where a context switch happens as a result of making a ThreadX service call 
+(which is itself a C function). In such cases, the saved context of a thread 
+is only the non-scratch registers.
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have one of these two types of stack frames. The top
+of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the 
+associated thread control block TX_THREAD.
+
+
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x00                   1                           0
+     0x04                   CPSR                        CPSR
+     0x08                   r0  (a1)                    r4  (v1)
+     0x0C                   r1  (a2)                    r5  (v2)
+     0x10                   r2  (a3)                    r6  (v3)
+     0x14                   r3  (a4)                    r7  (v4)
+     0x18                   r4  (v1)                    r8  (v5)
+     0x1C                   r5  (v2)                    r9  (v6)
+     0x20                   r6  (v3)                    r10 (v7)
+     0x24                   r7  (v4)                    r11 (fp)
+     0x28                   r8  (v5)                    r14 (lr)
+     0x2C                   r9  (v6)                        
+     0x30                   r10 (v7)                        
+     0x34                   r11 (fp)                        
+     0x38                   r12 (ip)                         
+     0x3C                   r14 (lr)
+     0x40                   PC 
+
+
+6.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+breakpoints inside of ThreadX itself. Of course, this costs some 
+performance. To make it run faster, you can change the build_threadx.bat file to 
+remove the -g option and enable all compiler optimizations. 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+7.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-R4
+targets. There are a certain set of requirements that are defined in the 
+following sub-sections:
+
+
+7.1  Vector Area
+
+The Cortex-R4 vectors start at address zero. The demonstration system startup
+Init area contains the vectors and is loaded at address zero. On actual 
+hardware platforms, this area might have to be copied to address 0. 
+
+
+7.2  IRQ ISRs
+
+ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested
+IRQ interrupts. The following sub-sections define the IRQ capabilities.
+
+
+7.2.1 Standard IRQ ISRs
+
+The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ 
+interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following 
+is the default IRQ handler defined in tx_initialize_low_level.s:
+
+    EXPORT  __tx_irq_handler
+    EXPORT  __tx_irq_processing_return      
+__tx_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save             ; Jump to the context save
+__tx_irq_processing_return
+;
+;    /* At this point execution is still in the IRQ mode. The CPSR, point of
+;       interrupt, and all C scratch registers are available for use. Note 
+;       that IRQ interrupts are still disabled upon return from the context
+;       save function.  */
+;
+;    /* Application ISR call(s) go here!  */
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.2.2 Vectored IRQ ISRs
+
+The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified
+by the particular implementation. The following is an example IRQ handler defined in 
+tx_initialize_low_level.s:
+
+    EXPORT  __tx_irq_example_handler
+__tx_irq_example_handler
+;
+;    /* Call context save to save system context.  */
+
+    STMDB   sp!, {r0-r3}                        ; Save some scratch registers
+    MRS     r0, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}             ; Store other scratch registers
+    BL      _tx_thread_vectored_context_save    ; Call the vectored IRQ context save
+;
+;    /* At this point execution is still in the IRQ mode. The CPSR, point of
+;       interrupt, and all C scratch registers are available for use. Note 
+;       that IRQ interrupts are still disabled upon return from the context
+;       save function.  */
+;
+;    /* Application ISR call goes here!  */
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.2.3  Nested IRQ Support
+
+By default, nested IRQ interrupt support is not enabled. To enable nested
+IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING
+defined. With this defined, two new IRQ interrupt management services are
+available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end.
+These function should be called between the IRQ context save and restore
+calls. 
+
+Execution between the calls to _tx_thread_irq_nesting_start and 
+_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved 
+by switching from IRQ mode to SYS mode and enabling IRQ interrupts.
+The SYS mode stack is used during the SYS mode operation, which was 
+setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required,
+calling the _tx_thread_irq_nesting_end service disables nesting by disabling
+IRQ interrupts and switching back to IRQ mode in preparation for the IRQ 
+context restore service.
+
+The following is an example of enabling IRQ nested interrupts in a standard 
+IRQ handler:
+
+    EXPORT  __tx_irq_handler
+    EXPORT  __tx_irq_processing_return      
+__tx_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return
+;
+;    /* Enable nested IRQ interrupts. NOTE:  Since this service returns
+;       with IRQ interrupts enabled, all IRQ interrupt sources must be 
+;       cleared prior to calling this service.  */
+    BL      _tx_thread_irq_nesting_start
+;    
+;    /* Application ISR call(s) go here!  */
+;
+;    /* Disable nested IRQ interrupts. The mode is switched back to
+;       IRQ mode and IRQ interrupts are disable upon return.  */
+    BL      _tx_thread_irq_nesting_end
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.3  FIQ Interrupts
+
+By default, Cortex-R4 FIQ interrupts are left alone by ThreadX. Of course, this 
+means that the application is fully responsible for enabling the FIQ interrupt 
+and saving/restoring any registers used in the FIQ ISR processing. To globally 
+enable FIQ interrupts, the application should enable FIQ interrupts at the 
+beginning of each thread or before any threads are created in tx_application_define. 
+In addition, the application must ensure that no ThreadX service calls are made 
+from default FIQ ISRs, which is located in tx_initialize_low_level.s.
+
+
+7.3.1  Managed FIQ Interrupts
+
+Full ThreadX management of FIQ interrupts is provided if the ThreadX sources
+are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built
+this way, the FIQ interrupt handlers are very similar to the IRQ interrupt
+handlers defined previously. The following is default FIQ handler 
+defined in tx_initialize_low_level.s:
+
+
+    EXPORT  __tx_fiq_handler
+    EXPORT  __tx_fiq_processing_return
+__tx_fiq_handler
+;
+;    /* Jump to fiq context save to save system context.  */
+    B       _tx_thread_fiq_context_save
+__tx_fiq_processing_return:
+;
+;    /* At this point execution is still in the FIQ mode. The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  */
+;
+;    /* Application FIQ handlers can be called here!  */
+;
+;    /* Jump to fiq context restore to restore system context.  */
+    B       _tx_thread_fiq_context_restore
+
+
+7.3.1.1 Nested FIQ Support
+
+By default, nested FIQ interrupt support is not enabled. To enable nested
+FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING
+defined. With this defined, two new FIQ interrupt management services are
+available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end.
+These function should be called between the FIQ context save and restore
+calls. 
+
+Execution between the calls to _tx_thread_fiq_nesting_start and 
+_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved 
+by switching from FIQ mode to SYS mode and enabling FIQ interrupts.
+The SYS mode stack is used during the SYS mode operation, which was 
+setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required,
+calling the _tx_thread_fiq_nesting_end service disables nesting by disabling
+FIQ interrupts and switching back to FIQ mode in preparation for the FIQ 
+context restore service.
+
+The following is an example of enabling FIQ nested interrupts in the 
+typical FIQ handler:
+
+
+    EXPORT  __tx_fiq_handler
+    EXPORT  __tx_fiq_processing_return
+__tx_fiq_handler
+;
+;    /* Jump to fiq context save to save system context.  */
+    B       _tx_thread_fiq_context_save
+__tx_fiq_processing_return
+;
+;    /* At this point execution is still in the FIQ mode. The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  */
+;
+;    /* Enable nested FIQ interrupts. NOTE:  Since this service returns
+;       with FIQ interrupts enabled, all FIQ interrupt sources must be 
+;       cleared prior to calling this service.  */
+    BL      _tx_thread_fiq_nesting_start
+;
+;    /* Application FIQ handlers can be called here!  */
+;
+;    /* Disable nested FIQ interrupts. The mode is switched back to
+;       FIQ mode and FIQ interrupts are disable upon return.  */
+    BL      _tx_thread_fiq_nesting_end
+;
+;    /* Jump to fiq context restore to restore system context.  */
+    B       _tx_thread_fiq_context_restore
+
+
+8.  ThreadX Timer Interrupt
+
+ThreadX requires a periodic interrupt source to manage all time-slicing, 
+thread sleeps, timeouts, and application timers. Without such a timer 
+interrupt source, these services are not functional. However, all other
+ThreadX services are operational without a periodic timer source.
+
+To add the timer interrupt processing, simply make a call to 
+_tx_timer_interrupt in the IRQ processing. An example of this can be
+found in the file tx_initialize_low_level.s in the Integrator sub-directories.
+
+
+9.  Thumb/Cortex-R4 Mixed Mode
+
+By default, ThreadX is setup for running in Cortex-R4 32-bit mode. This is 
+also true for the demonstration system. It is possible to build any 
+ThreadX file and/or the application in Thumb mode. If any Thumb code 
+is used the entire ThreadX source- both C and assembly - should be built 
+with the "-apcs /interwork" option.
+
+
+10. VFP Support
+
+By default, VFP support is disabled for each thread. If saving the context of the VFP registers
+is needed, the following API call must be made from the context of the application thread - before 
+the VFP usage:
+
+void    tx_thread_vfp_enable(void);
+
+After this API is called in the application, VFP registers will be saved/restored for this thread if it
+is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers
+to be saved/restored.
+
+To disable VFP register context saving, simply call the following API:
+
+void    tx_thread_vfp_disable(void);
+
+Note that if VFP registers are used in ISRs, the save/restore of VFP registers must be done by the ISR.
+In addition, the startup code is responsible for enabling VFP usage.
+
+
+11.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX 6.0.1 version for Cortex-R4 using AC5 tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_context_restore.s b/ports/cortex_r4/ac5/src/tx_thread_context_restore.s
new file mode 100644
index 00000000..b1f4023c
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_context_restore.s
@@ -0,0 +1,255 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+DISABLE_INTS    EQU     0xC0                    ; Disable IRQ & FIQ interrupts
+IRQ_MODE        EQU     0xD2                    ; IRQ mode
+SVC_MODE        EQU     0xD3                    ; SVC mode
+    ELSE
+DISABLE_INTS    EQU     0x80                    ; Disable IRQ interrupts
+IRQ_MODE        EQU     0x92                    ; IRQ mode
+SVC_MODE        EQU     0x93                    ; SVC mode
+    ENDIF
+;
+;
+    IMPORT      _tx_thread_system_state
+    IMPORT      _tx_thread_current_ptr
+    IMPORT      _tx_thread_execute_ptr
+    IMPORT      _tx_timer_time_slice
+    IMPORT      _tx_thread_schedule
+    IMPORT      _tx_thread_preempt_disable
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT      _tx_execution_isr_exit
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_context_restore                         Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function restores the interrupt context if it is processing a  */ 
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */ 
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+;/*    if no thread was running, the function returns to the scheduler.    */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                   Thread scheduling routine     */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                  Interrupt Service Routines    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_restore(VOID)
+;{
+    EXPORT  _tx_thread_context_restore
+_tx_thread_context_restore
+;
+;    /* Lockout interrupts.  */
+;
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Disable IRQ and FIQ interrupts
+    ELSE
+    CPSID   i                                   ; Disable IRQ interrupts
+    ENDIF
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR exit function to indicate an ISR is complete.  */
+;
+    BL      _tx_execution_isr_exit              ; Call the ISR exit function
+    ENDIF
+;
+;    /* Determine if interrupts are nested.  */
+;    if (--_tx_thread_system_state)
+;    {
+;
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3, #0]                        ; Pickup system state
+    SUB     r2, r2, #1                          ; Decrement the counter
+    STR     r2, [r3, #0]                        ; Store the counter 
+    CMP     r2, #0                              ; Was this the first interrupt?
+    BEQ     __tx_thread_not_nested_restore      ; If so, not a nested restore
+;
+;    /* Interrupts are nested.  */
+;
+;    /* Just recover the saved registers and return to the point of 
+;       interrupt.  */
+;
+    LDMIA   sp!, {r0, r10, r12, lr}             ; Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       ; Put SPSR back
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOVS    pc, lr                              ; Return to point of interrupt
+;
+;    }
+__tx_thread_not_nested_restore
+;
+;    /* Determine if a thread was interrupted and no preemption is required.  */
+;    else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) 
+;               || (_tx_thread_preempt_disable))
+;    {
+;
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        ; Pickup actual current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_idle_system_restore     ; Yes, idle system was interrupted
+;
+    LDR     r3, =_tx_thread_preempt_disable     ; Pickup preempt disable address
+    LDR     r2, [r3, #0]                        ; Pickup actual preempt disable flag
+    CMP     r2, #0                              ; Is it set?
+    BNE     __tx_thread_no_preempt_restore      ; Yes, don't preempt this thread
+    LDR     r3, =_tx_thread_execute_ptr         ; Pickup address of execute thread ptr
+    LDR     r2, [r3, #0]                        ; Pickup actual execute thread pointer
+    CMP     r0, r2                              ; Is the same thread highest priority?
+    BNE     __tx_thread_preempt_restore         ; No, preemption needs to happen
+;
+;
+__tx_thread_no_preempt_restore
+;
+;    /* Restore interrupted thread or ISR.  */
+;
+;    /* Pickup the saved stack pointer.  */
+;    tmp_ptr =  _tx_thread_current_ptr -> tx_thread_stack_ptr;
+;
+;   /* Recover the saved context and return to the point of interrupt.  */
+;
+    LDMIA   sp!, {r0, r10, r12, lr}             ; Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       ; Put SPSR back
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOVS    pc, lr                              ; Return to point of interrupt
+;
+;    }
+;    else
+;    {
+__tx_thread_preempt_restore
+;
+    LDMIA   sp!, {r3, r10, r12, lr}             ; Recover temporarily saved registers
+    MOV     r1, lr                              ; Save lr (point of interrupt)
+    MOV     r2, #SVC_MODE                       ; Build SVC mode CPSR
+    MSR     CPSR_c, r2                          ; Enter SVC mode
+    STR     r1, [sp, #-4]!                      ; Save point of interrupt
+    STMDB   sp!, {r4-r12, lr}                   ; Save upper half of registers
+    MOV     r4, r3                              ; Save SPSR in r4
+    MOV     r2, #IRQ_MODE                       ; Build IRQ mode CPSR
+    MSR     CPSR_c, r2                          ; Enter IRQ mode
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOV     r5, #SVC_MODE                       ; Build SVC mode CPSR
+    MSR     CPSR_c, r5                          ; Enter SVC mode
+    STMDB   sp!, {r0-r3}                        ; Save r0-r3 on thread's stack
+
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        ; Pickup current thread pointer
+
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    LDR     r2, [r0, #144]                      ; Pickup the VFP enabled flag
+    CMP     r2, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_irq_vfp_save               ; No, skip VFP IRQ save
+    VMRS    r2, FPSCR                           ; Pickup the FPSCR
+    STR     r2, [sp, #-4]!                      ; Save FPSCR
+    VSTMDB  sp!, {D0-D15}                       ; Save D0-D15
+_tx_skip_irq_vfp_save
+    ENDIF
+
+    MOV     r3, #1                              ; Build interrupt stack type
+    STMDB   sp!, {r3, r4}                       ; Save interrupt stack type and SPSR
+    STR     sp, [r0, #8]                        ; Save stack pointer in thread control
+                                                ;   block
+;
+;    /* Save the remaining time-slice and disable it.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    LDR     r3, =_tx_timer_time_slice           ; Pickup time-slice variable address
+    LDR     r2, [r3, #0]                        ; Pickup time-slice
+    CMP     r2, #0                              ; Is it active?
+    BEQ     __tx_thread_dont_save_ts            ; No, don't save it
+;
+;        _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+;        _tx_timer_time_slice =  0;
+;
+    STR     r2, [r0, #24]                       ; Save thread's time-slice
+    MOV     r2, #0                              ; Clear value
+    STR     r2, [r3, #0]                        ; Disable global time-slice flag
+;
+;    }
+__tx_thread_dont_save_ts
+;
+;
+;    /* Clear the current task pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;
+    MOV     r0, #0                              ; NULL value
+    STR     r0, [r1, #0]                        ; Clear current thread pointer
+;
+;    /* Return to the scheduler.  */
+;    _tx_thread_schedule();
+;
+    B       _tx_thread_schedule                 ; Return to scheduler
+;    }
+;
+__tx_thread_idle_system_restore
+;
+;    /* Just return back to the scheduler!  */
+;
+    MOV     r3, #SVC_MODE                       ; Build SVC mode with interrupts disabled
+    MSR     CPSR_c, r3                          ; Change to SVC mode
+    B       _tx_thread_schedule                 ; Return to scheduler
+;}
+;
+    END
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_context_save.s b/ports/cortex_r4/ac5/src/tx_thread_context_save.s
new file mode 100644
index 00000000..f6bde687
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_context_save.s
@@ -0,0 +1,199 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    IMPORT      _tx_thread_system_state
+    IMPORT      _tx_thread_current_ptr
+    IMPORT      __tx_irq_processing_return
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT      _tx_execution_isr_enter
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_context_save                            Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function saves the context of an executing thread in the       */ 
+;/*    beginning of interrupt processing.  The function also ensures that  */ 
+;/*    the system stack is used upon return to the calling ISR.            */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_save(VOID)
+;{
+    EXPORT  _tx_thread_context_save
+_tx_thread_context_save
+;
+;    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+;       out, we are in IRQ mode, and all registers are intact.  */
+;
+;    /* Check for a nested interrupt condition.  */
+;    if (_tx_thread_system_state++)
+;    {
+;
+    STMDB   sp!, {r0-r3}                        ; Save some working registers 
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Disable FIQ interrupts
+    ENDIF
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3, #0]                        ; Pickup system state
+    CMP     r2, #0                              ; Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         ; Yes, not a nested context save
+;
+;    /* Nested interrupt condition.  */
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+;
+;   /* Save the rest of the scratch registers on the stack and return to the
+;      calling ISR.  */
+;
+    MRS     r0, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}             ; Store other registers
+;
+;    /* Return to the ISR.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    B       __tx_irq_processing_return          ; Continue IRQ processing 
+;
+__tx_thread_not_nested_save
+;    }
+;
+;    /* Otherwise, not nested, check to see if a thread was running.  */
+;    else if (_tx_thread_current_ptr)
+;    {
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        ; Pickup current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_idle_system_save        ; If so, interrupt occurred in 
+                                                ;   scheduling loop - nothing needs saving!
+;
+;    /* Save minimal context of interrupted thread.  */
+;
+    MRS     r2, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r2, r10, r12, lr}             ; Store other registers
+;
+;    /* Save the current stack pointer in the thread's control block.  */
+;    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+;
+;    /* Switch to the system stack.  */
+;    sp =  _tx_thread_system_stack_ptr;
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    B       __tx_irq_processing_return          ; Continue IRQ processing 
+;
+;    }
+;    else
+;    {
+;
+__tx_thread_idle_system_save
+;
+;    /* Interrupt occurred in the scheduling loop.  */
+;
+;    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+;       processing.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    ADD     sp, sp, #16                         ; Recover saved registers
+    B       __tx_irq_processing_return          ; Continue IRQ processing  
+;
+;    }
+;}
+;
+    END
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s
new file mode 100644
index 00000000..79ddc37e
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_fiq_context_restore.s
@@ -0,0 +1,258 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+SVC_MODE        EQU     0xD3                    ; SVC mode
+FIQ_MODE        EQU     0xD1                    ; FIQ mode
+MODE_MASK       EQU     0x1F                    ; Mode mask 
+IRQ_MODE_BITS   EQU     0x12                    ; IRQ mode bits
+;
+;
+    IMPORT      _tx_thread_system_state
+    IMPORT      _tx_thread_current_ptr
+    IMPORT      _tx_thread_system_stack_ptr
+    IMPORT      _tx_thread_execute_ptr
+    IMPORT      _tx_timer_time_slice
+    IMPORT      _tx_thread_schedule
+    IMPORT      _tx_thread_preempt_disable
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT      _tx_execution_isr_exit
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_fiq_context_restore                     Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function restores the fiq interrupt context when processing a  */ 
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */ 
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+;/*    if no thread was running, the function returns to the scheduler.    */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                   Thread scheduling routine     */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    FIQ ISR                               Interrupt Service Routines    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_fiq_context_restore(VOID)
+;{
+    EXPORT  _tx_thread_fiq_context_restore
+_tx_thread_fiq_context_restore
+;
+;    /* Lockout interrupts.  */
+;
+    CPSID   if                                  ; Disable IRQ and FIQ interrupts
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR exit function to indicate an ISR is complete.  */
+;
+    BL      _tx_execution_isr_exit              ; Call the ISR exit function
+    ENDIF
+;
+;    /* Determine if interrupts are nested.  */
+;    if (--_tx_thread_system_state)
+;    {
+;
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3]                            ; Pickup system state
+    SUB     r2, r2, #1                          ; Decrement the counter
+    STR     r2, [r3]                            ; Store the counter 
+    CMP     r2, #0                              ; Was this the first interrupt?
+    BEQ     __tx_thread_fiq_not_nested_restore  ; If so, not a nested restore
+;
+;    /* Interrupts are nested.  */
+;
+;    /* Just recover the saved registers and return to the point of 
+;       interrupt.  */
+;
+    LDMIA   sp!, {r0, r10, r12, lr}             ; Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       ; Put SPSR back
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOVS    pc, lr                              ; Return to point of interrupt
+;
+;    }
+__tx_thread_fiq_not_nested_restore
+;
+;    /* Determine if a thread was interrupted and no preemption is required.  */
+;    else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) 
+;               || (_tx_thread_preempt_disable))
+;    {
+;
+    LDR     r1, [sp]                            ; Pickup the saved SPSR
+    MOV     r2, #MODE_MASK                      ; Build mask to isolate the interrupted mode
+    AND     r1, r1, r2                          ; Isolate mode bits
+    CMP     r1, #IRQ_MODE_BITS                  ; Was an interrupt taken in IRQ mode before we
+                                                ;   got to context save? */
+    BEQ     __tx_thread_fiq_no_preempt_restore  ; Yes, just go back to point of interrupt
+
+
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1]                            ; Pickup actual current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted
+
+    LDR     r3, =_tx_thread_preempt_disable     ; Pickup preempt disable address
+    LDR     r2, [r3]                            ; Pickup actual preempt disable flag
+    CMP     r2, #0                              ; Is it set?
+    BNE     __tx_thread_fiq_no_preempt_restore  ; Yes, don't preempt this thread
+    LDR     r3, =_tx_thread_execute_ptr         ; Pickup address of execute thread ptr
+    LDR     r2, [r3]                            ; Pickup actual execute thread pointer
+    CMP     r0, r2                              ; Is the same thread highest priority?
+    BNE     __tx_thread_fiq_preempt_restore     ; No, preemption needs to happen
+
+
+__tx_thread_fiq_no_preempt_restore
+;
+;    /* Restore interrupted thread or ISR.  */
+;
+;    /* Pickup the saved stack pointer.  */
+;    tmp_ptr =  _tx_thread_current_ptr -> tx_thread_stack_ptr; 
+;
+;    /* Recover the saved context and return to the point of interrupt.  */
+;
+    LDMIA   sp!, {r0, lr}                       ; Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       ; Put SPSR back
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOVS    pc, lr                              ; Return to point of interrupt
+;
+;    }
+;    else
+;    {
+__tx_thread_fiq_preempt_restore
+;
+    LDMIA   sp!, {r3, lr}                       ; Recover temporarily saved registers
+    MOV     r1, lr                              ; Save lr (point of interrupt)
+    MOV     r2, #SVC_MODE                       ; Build SVC mode CPSR
+    MSR     CPSR_c, r2                          ; Enter SVC mode
+    STR     r1, [sp, #-4]!                      ; Save point of interrupt
+    STMDB   sp!, {r4-r12, lr}                   ; Save upper half of registers
+    MOV     r4, r3                              ; Save SPSR in r4
+    MOV     r2, #FIQ_MODE                       ; Build FIQ mode CPSR
+    MSR     CPSR_c, r2                          ; Re-enter FIQ mode
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOV     r5, #SVC_MODE                       ; Build SVC mode CPSR
+    MSR     CPSR_c, r5                          ; Enter SVC mode
+    STMDB   sp!, {r0-r3}                        ; Save r0-r3 on thread's stack
+
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1]                            ; Pickup current thread pointer
+
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    LDR     r2, [r0, #144]                      ; Pickup the VFP enabled flag
+    CMP     r2, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_fiq_vfp_save               ; No, skip VFP FIQ save
+    VMRS    r2, FPSCR                           ; Pickup the FPSCR
+    STR     r2, [sp, #-4]!                      ; Save FPSCR
+    VSTMDB  sp!, {D0-D15}                       ; Save D0-D15
+_tx_skip_fiq_vfp_save
+    ENDIF
+
+    MOV     r3, #1                              ; Build interrupt stack type
+    STMDB   sp!, {r3, r4}                       ; Save interrupt stack type and SPSR
+    STR     sp, [r0, #8]                        ; Save stack pointer in thread control
+                                                ;   block  
+;
+;    /* Save the remaining time-slice and disable it.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    LDR     r3, =_tx_timer_time_slice           ; Pickup time-slice variable address
+    LDR     r2, [r3]                            ; Pickup time-slice
+    CMP     r2, #0                              ; Is it active?
+    BEQ     __tx_thread_fiq_dont_save_ts        ; No, don't save it
+;
+;        _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+;        _tx_timer_time_slice =  0; 
+;
+    STR     r2, [r0, #24]                       ; Save thread's time-slice
+    MOV     r2, #0                              ; Clear value
+    STR     r2, [r3]                            ; Disable global time-slice flag
+;
+;    }
+__tx_thread_fiq_dont_save_ts
+;
+;
+;    /* Clear the current task pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;
+    MOV     r0, #0                              ; NULL value
+    STR     r0, [r1]                            ; Clear current thread pointer
+;
+;    /* Return to the scheduler.  */
+;    _tx_thread_schedule();
+;
+    B       _tx_thread_schedule                 ; Return to scheduler
+;    }
+;
+__tx_thread_fiq_idle_system_restore
+;
+;    /* Just return back to the scheduler!  */
+;
+    ADD     sp, sp, #24                         ; Recover FIQ stack space
+    MOV     r3, #SVC_MODE                       ; Build SVC mode CPSR
+    MSR     CPSR_c, r3                          ; Enter SVC mode
+    B       _tx_thread_schedule                 ; Return to scheduler
+;
+;}
+;
+    END
+
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_r4/ac5/src/tx_thread_fiq_context_save.s
new file mode 100644
index 00000000..75325f33
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_fiq_context_save.s
@@ -0,0 +1,203 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    IMPORT      _tx_thread_system_state
+    IMPORT      _tx_thread_current_ptr
+    IMPORT      __tx_fiq_processing_return
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT      _tx_execution_isr_enter
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_fiq_context_save                        Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function saves the context of an executing thread in the       */ 
+;/*    beginning of interrupt processing.  The function also ensures that  */ 
+;/*    the system stack is used upon return to the calling ISR.            */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+; VOID   _tx_thread_fiq_context_save(VOID)
+;{
+    EXPORT  _tx_thread_fiq_context_save
+_tx_thread_fiq_context_save
+;
+;    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+;       out, we are in IRQ mode, and all registers are intact.  */
+;
+;    /* Check for a nested interrupt condition.  */
+;    if (_tx_thread_system_state++)
+;    {
+;
+    STMDB   sp!, {r0-r3}                        ; Save some working registers 
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3]                            ; Pickup system state
+    CMP     r2, #0                              ; Is this the first interrupt?
+    BEQ     __tx_thread_fiq_not_nested_save     ; Yes, not a nested context save
+;
+;    /* Nested interrupt condition.  */
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3]                            ; Store it back in the variable
+;
+;    /* Save the rest of the scratch registers on the stack and return to the
+;       calling ISR.  */
+;
+    MRS     r0, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}             ; Store other registers
+;
+;    /* Return to the ISR.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    B       __tx_fiq_processing_return          ; Continue FIQ processing 
+;
+__tx_thread_fiq_not_nested_save
+;    }  
+;
+;    /* Otherwise, not nested, check to see if a thread was running.  */
+;    else if (_tx_thread_current_ptr)
+;    {   
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3]                            ; Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1]                            ; Pickup current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_fiq_idle_system_save    ; If so, interrupt occurred in 
+;                                               ;   scheduling loop - nothing needs saving! 
+;
+;    /* Save minimal context of interrupted thread.  */
+;
+    MRS     r2, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r2, lr}                       ; Store other registers, Note that we don't
+;                                               ;   need to save sl and ip since FIQ has 
+;                                               ;   copies of these registers.  Nested 
+;                                               ;   interrupt processing does need to save
+;                                               ;   these registers.
+;
+;    /* Save the current stack pointer in the thread's control block.  */
+;    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp; 
+;
+;    /* Switch to the system stack.  */
+;    sp =  _tx_thread_system_stack_ptr; 
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    B       __tx_fiq_processing_return          ; Continue FIQ processing 
+;
+;   }
+;   else
+;   {
+;
+__tx_thread_fiq_idle_system_save
+;
+;    /* Interrupt occurred in the scheduling loop.  */
+;
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+;
+;    /* Not much to do here, save the current SPSR and LR for possible
+;       use in IRQ interrupted in idle system conditions, and return to 
+;       FIQ interrupt processing.  */
+;
+    MRS     r0, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r0, lr}                       ; Store other registers that will get used
+;                                               ;   or stripped off the stack in context 
+;                                               ;   restore 
+    B       __tx_fiq_processing_return          ; Continue FIQ processing  
+;
+;    }
+;}  
+;
+    END
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_end.s
new file mode 100644
index 00000000..e4727145
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_end.s
@@ -0,0 +1,111 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+DISABLE_INTS    EQU     0xC0                    ; Disable IRQ & FIQ interrupts
+    ELSE
+DISABLE_INTS    EQU     0x80                    ; Disable IRQ interrupts
+    ENDIF
+MODE_MASK       EQU     0x1F                    ; Mode mask 
+FIQ_MODE_BITS   EQU     0x11                    ; FIQ mode bits
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_fiq_nesting_end                         Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is called by the application from FIQ mode after      */ 
+;/*    _tx_thread_fiq_nesting_start has been called and switches the FIQ   */ 
+;/*    processing from system mode back to FIQ mode prior to the ISR       */ 
+;/*    calling _tx_thread_fiq_context_restore.  Note that this function    */ 
+;/*    assumes the system stack pointer is in the same position after      */ 
+;/*    nesting start function was called.                                  */ 
+;/*                                                                        */ 
+;/*    This function assumes that the system mode stack pointer was setup  */ 
+;/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+;/*                                                                        */ 
+;/*    This function returns with FIQ interrupts disabled.                 */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_fiq_nesting_end(VOID)
+;{
+    EXPORT  _tx_thread_fiq_nesting_end
+_tx_thread_fiq_nesting_end
+    MOV     r3,lr                               ; Save ISR return address
+    MRS     r0, CPSR                            ; Pickup the CPSR
+    ORR     r0, r0, #DISABLE_INTS               ; Build disable interrupt value
+    MSR     CPSR_c, r0                          ; Disable interrupts
+    LDMIA   sp!, {r1, lr}                       ; Pickup saved lr (and r1 throw-away for 
+                                                ;   8-byte alignment logic)
+    BIC     r0, r0, #MODE_MASK                  ; Clear mode bits
+    ORR     r0, r0, #FIQ_MODE_BITS              ; Build IRQ mode CPSR
+    MSR     CPSR_c, r0                          ; Re-enter IRQ mode
+    IF  {INTER} = {TRUE}
+    BX      r3                                  ; Return to caller
+    ELSE
+    MOV     pc, r3                              ; Return to caller
+    ENDIF
+;}
+;
+    END
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_start.s
new file mode 100644
index 00000000..24f4689d
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_fiq_nesting_start.s
@@ -0,0 +1,104 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+FIQ_DISABLE     EQU     0x40                    ; FIQ disable bit
+MODE_MASK       EQU     0x1F                    ; Mode mask
+SYS_MODE_BITS   EQU     0x1F                    ; System mode bits
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_fiq_nesting_start                       Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is called by the application from FIQ mode after      */ 
+;/*    _tx_thread_fiq_context_save has been called and switches the FIQ    */ 
+;/*    processing to the system mode so nested FIQ interrupt processing    */ 
+;/*    is possible (system mode has its own "lr" register).  Note that     */ 
+;/*    this function assumes that the system mode stack pointer was setup  */ 
+;/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+;/*                                                                        */ 
+;/*    This function returns with FIQ interrupts enabled.                  */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_fiq_nesting_start(VOID)
+;{
+    EXPORT  _tx_thread_fiq_nesting_start
+_tx_thread_fiq_nesting_start
+    MOV     r3,lr                               ; Save ISR return address
+    MRS     r0, CPSR                            ; Pickup the CPSR
+    BIC     r0, r0, #MODE_MASK                  ; Clear the mode bits
+    ORR     r0, r0, #SYS_MODE_BITS              ; Build system mode CPSR
+    MSR     CPSR_c, r0                          ; Enter system mode
+    STMDB   sp!, {r1, lr}                       ; Push the system mode lr on the system mode stack
+                                                ;   and push r1 just to keep 8-byte alignment
+    BIC     r0, r0, #FIQ_DISABLE                ; Build enable FIQ CPSR
+    MSR     CPSR_c, r0                          ; Enter system mode
+    IF  {INTER} = {TRUE}
+    BX      r3                                  ; Return to caller
+    ELSE
+    MOV     pc, r3                              ; Return to caller
+    ENDIF
+;}
+;
+    END
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_r4/ac5/src/tx_thread_interrupt_control.s
new file mode 100644
index 00000000..984102e0
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_interrupt_control.s
@@ -0,0 +1,102 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+INT_MASK        EQU         0xC0                ; Interrupt bit mask
+    ELSE
+INT_MASK        EQU         0x80                ; Interrupt bit mask
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_interrupt_control                       Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for changing the interrupt lockout     */ 
+;/*    posture of the system.                                              */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    new_posture                           New interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    old_posture                           Old interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    Application Code                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_control(UINT new_posture)
+;{
+    EXPORT  _tx_thread_interrupt_control
+_tx_thread_interrupt_control
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    MRS     r3, CPSR                            ; Pickup current CPSR
+    BIC     r1, r3, #INT_MASK                   ; Clear interrupt lockout bits
+    ORR     r1, r1, r0                          ; Or-in new interrupt lockout bits
+;
+;    /* Apply the new interrupt posture.  */
+;
+    MSR     CPSR_c, r1                          ; Setup new CPSR
+    AND     r0, r3, #INT_MASK                   ; Return previous interrupt mask
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+;}
+;
+    END
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_r4/ac5/src/tx_thread_interrupt_disable.s
new file mode 100644
index 00000000..da0cae5c
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_interrupt_disable.s
@@ -0,0 +1,95 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_interrupt_disable                       Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for disabling interrupts               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    old_posture                           Old interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    Application Code                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_disable(void)
+;{
+    EXPORT _tx_thread_interrupt_disable
+_tx_thread_interrupt_disable
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    MRS     r0, CPSR                            ; Pickup current CPSR
+;
+;    /* Mask interrupts.  */
+;
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Disable IRQ and FIQ
+    ELSE
+    CPSID   i                                   ; Disable IRQ 
+    ENDIF
+
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;}
+;
+    END
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_r4/ac5/src/tx_thread_interrupt_restore.s
new file mode 100644
index 00000000..021d8f95
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_interrupt_restore.s
@@ -0,0 +1,87 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_interrupt_restore                       Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for restoring interrupts to the state  */
+;/*    returned by a previous _tx_thread_interrupt_disable call.           */
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    old_posture                           Old interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    Application Code                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_restore(UINT old_posture)
+;{
+    EXPORT  _tx_thread_interrupt_restore
+_tx_thread_interrupt_restore
+;
+;    /* Apply the new interrupt posture.  */
+;
+    MSR     CPSR_c, r0                          ; Setup new CPSR
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;}
+;
+    END
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_end.s
new file mode 100644
index 00000000..6ad5dcf4
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_end.s
@@ -0,0 +1,110 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+DISABLE_INTS    EQU     0xC0                    ; Disable IRQ & FIQ interrupts
+    ELSE
+DISABLE_INTS    EQU     0x80                    ; Disable IRQ interrupts
+    ENDIF
+MODE_MASK       EQU     0x1F                    ; Mode mask 
+IRQ_MODE_BITS   EQU     0x12                    ; IRQ mode bits
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_irq_nesting_end                         Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is called by the application from IRQ mode after      */ 
+;/*    _tx_thread_irq_nesting_start has been called and switches the IRQ   */ 
+;/*    processing from system mode back to IRQ mode prior to the ISR       */ 
+;/*    calling _tx_thread_context_restore.  Note that this function        */ 
+;/*    assumes the system stack pointer is in the same position after      */ 
+;/*    nesting start function was called.                                  */ 
+;/*                                                                        */ 
+;/*    This function assumes that the system mode stack pointer was setup  */ 
+;/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+;/*                                                                        */ 
+;/*    This function returns with IRQ interrupts disabled.                 */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_irq_nesting_end(VOID)
+;{
+    EXPORT  _tx_thread_irq_nesting_end
+_tx_thread_irq_nesting_end
+    MOV     r3,lr                               ; Save ISR return address
+    MRS     r0, CPSR                            ; Pickup the CPSR
+    ORR     r0, r0, #DISABLE_INTS               ; Build disable interrupt value
+    MSR     CPSR_c, r0                          ; Disable interrupts
+    LDMIA   sp!, {r1, lr}                       ; Pickup saved lr (and r1 throw-away for 
+                                                ;   8-byte alignment logic)
+    BIC     r0, r0, #MODE_MASK                  ; Clear mode bits
+    ORR     r0, r0, #IRQ_MODE_BITS              ; Build IRQ mode CPSR
+    MSR     CPSR_c, r0                          ; Re-enter IRQ mode
+    IF  {INTER} = {TRUE}
+    BX      r3                                  ; Return to caller
+    ELSE
+    MOV     pc, r3                              ; Return to caller
+    ENDIF
+;}
+    END
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_start.s
new file mode 100644
index 00000000..5fcd5382
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_irq_nesting_start.s
@@ -0,0 +1,104 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+IRQ_DISABLE     EQU     0x80                    ; IRQ disable bit
+MODE_MASK       EQU     0x1F                    ; Mode mask
+SYS_MODE_BITS   EQU     0x1F                    ; System mode bits
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_irq_nesting_start                       Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is called by the application from IRQ mode after      */ 
+;/*    _tx_thread_context_save has been called and switches the IRQ        */ 
+;/*    processing to the system mode so nested IRQ interrupt processing    */ 
+;/*    is possible (system mode has its own "lr" register).  Note that     */ 
+;/*    this function assumes that the system mode stack pointer was setup  */ 
+;/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+;/*                                                                        */ 
+;/*    This function returns with IRQ interrupts enabled.                  */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_irq_nesting_start(VOID)
+;{
+    EXPORT  _tx_thread_irq_nesting_start
+_tx_thread_irq_nesting_start
+    MOV     r3,lr                               ; Save ISR return address
+    MRS     r0, CPSR                            ; Pickup the CPSR
+    BIC     r0, r0, #MODE_MASK                  ; Clear the mode bits
+    ORR     r0, r0, #SYS_MODE_BITS              ; Build system mode CPSR
+    MSR     CPSR_c, r0                          ; Enter system mode
+    STMDB   sp!, {r1, lr}                       ; Push the system mode lr on the system mode stack
+                                                ;   and push r1 just to keep 8-byte alignment
+    BIC     r0, r0, #IRQ_DISABLE                ; Build enable IRQ CPSR
+    MSR     CPSR_c, r0                          ; Enter system mode
+    IF  {INTER} = {TRUE}
+    BX      r3                                  ; Return to caller
+    ELSE
+    MOV     pc, r3                              ; Return to caller
+    ENDIF
+;}
+;
+    END
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_schedule.s b/ports/cortex_r4/ac5/src/tx_thread_schedule.s
new file mode 100644
index 00000000..a9f7f55a
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_schedule.s
@@ -0,0 +1,234 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IMPORT     _tx_thread_execute_ptr
+    IMPORT     _tx_thread_current_ptr
+    IMPORT     _tx_timer_time_slice
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT     _tx_execution_thread_enter
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                                Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function waits for a thread control block pointer to appear in */ 
+;/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */ 
+;/*    in the variable, the corresponding thread is resumed.               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_kernel_enter          ThreadX entry function         */ 
+;/*    _tx_thread_system_return             Return to system from thread   */ 
+;/*    _tx_thread_context_restore           Restore thread's context       */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_schedule(VOID)
+;{
+    EXPORT  _tx_thread_schedule
+_tx_thread_schedule
+;
+;    /* Enable interrupts.  */
+;
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSIE   if                                  ; Enable IRQ and FIQ interrupts
+    ELSE
+    CPSIE   i                                   ; Enable IRQ interrupts
+    ENDIF
+;
+;    /* Wait for a thread to execute.  */
+;    do
+;    {
+    LDR     r1, =_tx_thread_execute_ptr         ; Address of thread execute ptr
+;
+__tx_thread_schedule_loop
+;
+    LDR     r0, [r1, #0]                        ; Pickup next thread to execute
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_schedule_loop           ; If so, keep looking for a thread
+;
+;    }
+;    while(_tx_thread_execute_ptr == TX_NULL);
+;    
+;    /* Yes! We have a thread to execute.  Lockout interrupts and
+;       transfer control to it.  */
+;
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Enable IRQ and FIQ interrupts
+    ELSE
+    CPSID   i                                   ; Enable IRQ interrupts
+    ENDIF
+;
+;    /* Setup the current thread pointer.  */
+;    _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+;
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread 
+    STR     r0, [r1, #0]                        ; Setup current thread pointer
+;
+;    /* Increment the run count for this thread.  */
+;    _tx_thread_current_ptr -> tx_thread_run_count++;
+;
+    LDR     r2, [r0, #4]                        ; Pickup run counter
+    LDR     r3, [r0, #24]                       ; Pickup time-slice for this thread
+    ADD     r2, r2, #1                          ; Increment thread run-counter
+    STR     r2, [r0, #4]                        ; Store the new run counter
+;
+;    /* Setup time-slice, if present.  */
+;    _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+;
+    LDR     r2, =_tx_timer_time_slice           ; Pickup address of time slice 
+                                                ;   variable
+    LDR     sp, [r0, #8]                        ; Switch stack pointers
+    STR     r3, [r2, #0]                        ; Setup time-slice
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread entry function to indicate the thread is executing.  */
+;
+    MOV     r5, r0                              ; Save r0
+    BL      _tx_execution_thread_enter          ; Call the thread execution enter function
+    MOV     r0, r5                              ; Restore r0
+    ENDIF
+;
+;    /* Switch to the thread's stack.  */
+;    sp =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;
+;
+;    /* Determine if an interrupt frame or a synchronous task suspension frame
+;       is present.  */
+;
+    LDMIA   sp!, {r4, r5}                       ; Pickup the stack type and saved CPSR
+    CMP     r4, #0                              ; Check for synchronous context switch
+    BEQ     _tx_solicited_return
+    MSR     SPSR_cxsf, r5                       ; Setup SPSR for return
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    LDR     r1, [r0, #144]                      ; Pickup the VFP enabled flag
+    CMP     r1, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_interrupt_vfp_restore      ; No, skip VFP interrupt restore
+    VLDMIA  sp!, {D0-D15}                       ; Recover D0-D15
+    LDR     r4, [sp], #4                        ; Pickup FPSCR
+    VMSR    FPSCR, r4                           ; Restore FPSCR
+_tx_skip_interrupt_vfp_restore
+    ENDIF
+    LDMIA   sp!, {r0-r12, lr, pc}^              ; Return to point of thread interrupt
+
+_tx_solicited_return
+
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    LDR     r1, [r0, #144]                      ; Pickup the VFP enabled flag
+    CMP     r1, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_solicited_vfp_restore      ; No, skip VFP solicited restore
+    VLDMIA  sp!, {D8-D15}                       ; Recover D8-D15
+    LDR     r4, [sp], #4                        ; Pickup FPSCR
+    VMSR    FPSCR, r4                           ; Restore FPSCR
+_tx_skip_solicited_vfp_restore
+    ENDIF
+    MSR     CPSR_cxsf, r5                       ; Recover CPSR
+    LDMIA   sp!, {r4-r11, lr}                   ; Return to thread synchronously
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+;}
+;
+
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    EXPORT  tx_thread_vfp_enable
+tx_thread_vfp_enable
+    MRS     r2, CPSR                            ; Pickup the CPSR
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Disable IRQ and FIQ interrupts
+    ELSE
+    CPSID   i                                   ; Disable IRQ interrupts
+    ENDIF
+    LDR     r0, =_tx_thread_current_ptr         ; Build current thread pointer address
+    LDR     r1, [r0]                            ; Pickup current thread pointer
+    CMP     r1, #0                              ; Check for NULL thread pointer
+    BEQ     __tx_no_thread_to_enable            ; If NULL, skip VFP enable
+    MOV     r0, #1                              ; Build enable value
+    STR     r0, [r1, #144]                      ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
+__tx_no_thread_to_enable
+    MSR     CPSR_cxsf, r2                       ; Recover CPSR
+    BX      LR                                  ; Return to caller
+
+    EXPORT  tx_thread_vfp_disable
+tx_thread_vfp_disable
+    MRS     r2, CPSR                            ; Pickup the CPSR
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Disable IRQ and FIQ interrupts
+    ELSE
+    CPSID   i                                   ; Disable IRQ interrupts
+    ENDIF
+    LDR     r0, =_tx_thread_current_ptr         ; Build current thread pointer address
+    LDR     r1, [r0]                            ; Pickup current thread pointer
+    CMP     r1, #0                              ; Check for NULL thread pointer
+    BEQ     __tx_no_thread_to_disable           ; If NULL, skip VFP disable
+    MOV     r0, #0                              ; Build disable value
+    STR     r0, [r1, #144]                      ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
+__tx_no_thread_to_disable
+    MSR     CPSR_cxsf, r2                       ;   Recover CPSR
+    BX      LR                                  ; Return to caller
+    ENDIF
+
+    END
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_stack_build.s b/ports/cortex_r4/ac5/src/tx_thread_stack_build.s
new file mode 100644
index 00000000..053db0e1
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_stack_build.s
@@ -0,0 +1,164 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+SVC_MODE        EQU     0x13                    ; SVC mode
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+CPSR_MASK       EQU     0xDF                    ; Mask initial CPSR, IRQ & FIQ ints enabled
+    ELSE
+CPSR_MASK       EQU     0x9F                    ; Mask initial CPSR, IRQ ints enabled
+    ENDIF
+
+THUMB_BIT       EQU     0x20                    ; Thumb-bit
+
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_stack_build                             Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function builds a stack frame on the supplied thread's stack.  */
+;/*    The stack frame results in a fake interrupt return to the supplied  */
+;/*    function pointer.                                                   */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    thread_ptr                            Pointer to thread control blk */
+;/*    function_ptr                          Pointer to return function    */
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_thread_create                     Create thread service         */
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+;{
+    EXPORT  _tx_thread_stack_build
+_tx_thread_stack_build
+;
+;       
+;    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+;       on the Cortex-R4 should look like the following after it is built:
+;       
+;       Stack Top:      1           Interrupt stack frame type
+;                       CPSR        Initial value for CPSR
+;                       a1 (r0)     Initial value for a1
+;                       a2 (r1)     Initial value for a2
+;                       a3 (r2)     Initial value for a3
+;                       a4 (r3)     Initial value for a4
+;                       v1 (r4)     Initial value for v1
+;                       v2 (r5)     Initial value for v2
+;                       v3 (r6)     Initial value for v3
+;                       v4 (r7)     Initial value for v4
+;                       v5 (r8)     Initial value for v5
+;                       sb (r9)     Initial value for sb
+;                       sl (r10)    Initial value for sl
+;                       fp (r11)    Initial value for fp
+;                       ip (r12)    Initial value for ip
+;                       lr (r14)    Initial value for lr
+;                       pc (r15)    Initial value for pc
+;                       0           For stack backtracing
+;
+;    Stack Bottom: (higher memory address)  */
+;
+    LDR     r2, [r0, #16]                       ; Pickup end of stack area
+    BIC     r2, r2, #7                          ; Ensure 8-byte alignment
+    SUB     r2, r2, #76                         ; Allocate space for the stack frame
+;
+;    /* Actually build the stack frame.  */
+;
+    MOV     r3, #1                              ; Build interrupt stack type
+    STR     r3, [r2, #0]                        ; Store stack type
+    MOV     r3, #0                              ; Build initial register value
+    STR     r3, [r2, #8]                        ; Store initial r0
+    STR     r3, [r2, #12]                       ; Store initial r1
+    STR     r3, [r2, #16]                       ; Store initial r2
+    STR     r3, [r2, #20]                       ; Store initial r3
+    STR     r3, [r2, #24]                       ; Store initial r4
+    STR     r3, [r2, #28]                       ; Store initial r5
+    STR     r3, [r2, #32]                       ; Store initial r6
+    STR     r3, [r2, #36]                       ; Store initial r7
+    STR     r3, [r2, #40]                       ; Store initial r8
+    STR     r3, [r2, #44]                       ; Store initial r9
+    LDR     r3, [r0, #12]                       ; Pickup stack starting address
+    STR     r3, [r2, #48]                       ; Store initial r10 (sl)
+    MOV     r3, #0                              ; Build initial register value
+    STR     r3, [r2, #52]                       ; Store initial r11
+    STR     r3, [r2, #56]                       ; Store initial r12
+    STR     r3, [r2, #60]                       ; Store initial lr
+    STR     r1, [r2, #64]                       ; Store initial pc
+    STR     r3, [r2, #68]                       ; 0 for back-trace
+
+    MRS     r3, CPSR                            ; Pickup CPSR
+    BIC     r3, r3, #CPSR_MASK                  ; Mask mode bits of CPSR
+    ORR     r3, r3, #SVC_MODE                   ; Build CPSR, SVC mode, interrupts enabled
+    BIC     r3, r3, #THUMB_BIT                  ; Clear Thumb-bit by default
+    AND     r1, r1, #1                          ; Determine if the entry function is in Thumb mode
+    CMP     r1, #1                              ; Is the Thumb-bit set?
+    ORREQ   r3, r3, #THUMB_BIT                  ; Yes, set the Thumb-bit
+    STR     r3, [r2, #4]                        ; Store initial CPSR
+;
+;    /* Setup stack pointer.  */
+;    thread_ptr -> tx_thread_stack_ptr =  r2;
+;
+    STR     r2, [r0, #8]                        ; Save stack pointer in thread's
+                                                ;   control block
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;}
+    END
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_system_return.s b/ports/cortex_r4/ac5/src/tx_thread_system_return.s
new file mode 100644
index 00000000..4c5b0d28
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_system_return.s
@@ -0,0 +1,158 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IMPORT      _tx_thread_current_ptr
+    IMPORT      _tx_timer_time_slice
+    IMPORT      _tx_thread_schedule
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT      _tx_execution_thread_exit        
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_system_return                           Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is target processor specific.  It is used to transfer */ 
+;/*    control from a thread back to the ThreadX system.  Only a           */ 
+;/*    minimal context is saved since the compiler assumes temp registers  */ 
+;/*    are going to get slicked by a function call anyway.                 */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                   Thread scheduling loop        */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ThreadX components                                                  */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_system_return(VOID)
+;{
+    EXPORT  _tx_thread_system_return
+_tx_thread_system_return
+;
+;    /* Save minimal context on the stack.  */
+;
+    STMDB   sp!, {r4-r11, lr}                   ; Save minimal context
+    LDR     r5, =_tx_thread_current_ptr         ; Pickup address of current ptr
+    LDR     r6, [r5, #0]                        ; Pickup current thread pointer
+
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    LDR     r0, [r6, #144]                      ; Pickup the VFP enabled flag
+    CMP     r0, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_solicited_vfp_save         ; No, skip VFP solicited save
+    VMRS    r4, FPSCR                           ; Pickup the FPSCR
+    STR     r4, [sp, #-4]!                      ; Save FPSCR
+    VSTMDB  sp!, {D8-D15}                       ; Save D8-D15
+_tx_skip_solicited_vfp_save
+    ENDIF
+
+    MOV     r0, #0                              ; Build a solicited stack type
+    MRS     r1, CPSR                            ; Pickup the CPSR
+    STMDB   sp!, {r0-r1}                        ; Save type and CPSR
+;   
+;   /* Lockout interrupts.  */
+;
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Disable IRQ and FIQ interrupts
+    ELSE
+    CPSID   i                                   ; Disable IRQ interrupts
+    ENDIF
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread exit function to indicate the thread is no longer executing.  */
+;
+    BL      _tx_execution_thread_exit           ; Call the thread exit function
+    ENDIF
+    LDR     r2, =_tx_timer_time_slice           ; Pickup address of time slice
+    LDR     r1, [r2, #0]                        ; Pickup current time slice
+;
+;    /* Save current stack and switch to system stack.  */
+;    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+;    sp = _tx_thread_system_stack_ptr;
+;
+    STR     sp, [r6, #8]                        ; Save thread stack pointer
+;
+;    /* Determine if the time-slice is active.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    MOV     r4, #0                              ; Build clear value
+    CMP     r1, #0                              ; Is a time-slice active?
+    BEQ     __tx_thread_dont_save_ts            ; No, don't save the time-slice
+;
+;       /* Save the current remaining time-slice.  */
+;       _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+;       _tx_timer_time_slice =  0;
+;
+    STR     r4, [r2, #0]                        ; Clear time-slice
+    STR     r1, [r6, #24]                       ; Store current time-slice
+;
+;    }
+__tx_thread_dont_save_ts
+;
+;    /* Clear the current thread pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;
+    STR     r4, [r5, #0]                        ; Clear current thread pointer
+
+    B       _tx_thread_schedule                 ; Jump to scheduler!
+;
+;}
+    END
+
diff --git a/ports/cortex_r4/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_r4/ac5/src/tx_thread_vectored_context_save.s
new file mode 100644
index 00000000..be161ce7
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_thread_vectored_context_save.s
@@ -0,0 +1,200 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    IMPORT      _tx_thread_system_state
+    IMPORT      _tx_thread_current_ptr
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT      _tx_execution_isr_enter
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_vectored_context_save                   Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function saves the context of an executing thread in the       */ 
+;/*    beginning of interrupt processing.  The function also ensures that  */ 
+;/*    the system stack is used upon return to the calling ISR.            */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID  _tx_thread_vectored_context_save(VOID)
+;{
+    EXPORT  _tx_thread_vectored_context_save
+_tx_thread_vectored_context_save
+;
+;    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+;       out, we are in IRQ mode, and all registers are intact.  */
+;
+;    /* Check for a nested interrupt condition.  */
+;    if (_tx_thread_system_state++)
+;    {
+;
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Disable IRQ and FIQ interrupts
+    ENDIF
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3, #0]                        ; Pickup system state
+    CMP     r2, #0                              ; Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         ; Yes, not a nested context save
+;
+;    /* Nested interrupt condition.  */
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+;
+;    /* Note: Minimal context of interrupted thread is already saved.  */
+;
+;    /* Return to the ISR.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+    
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+__tx_thread_not_nested_save
+;    }
+;
+;    /* Otherwise, not nested, check to see if a thread was running.  */
+;    else if (_tx_thread_current_ptr)
+;    {
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        ; Pickup current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_idle_system_save        ; If so, interrupt occurred in 
+                                                ;   scheduling loop - nothing needs saving!
+;
+;    /* Note: Minimal context of interrupted thread is already saved.  */
+;
+;    /* Save the current stack pointer in the thread's control block.  */
+;    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+;
+;    /* Switch to the system stack.  */
+;    sp =  _tx_thread_system_stack_ptr;
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+;    }
+;    else
+;    {
+;
+__tx_thread_idle_system_save
+;
+;    /* Interrupt occurred in the scheduling loop.  */
+;
+;    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+;       processing.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    ADD     sp, sp, #32                         ; Recover saved registers
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+;    }
+;}
+;
+    END
+
diff --git a/ports/cortex_r4/ac5/src/tx_timer_interrupt.s b/ports/cortex_r4/ac5/src/tx_timer_interrupt.s
new file mode 100644
index 00000000..f6482e30
--- /dev/null
+++ b/ports/cortex_r4/ac5/src/tx_timer_interrupt.s
@@ -0,0 +1,258 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Timer                                                               */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_timer.h"
+;#include "tx_thread.h"
+;
+;
+;Define Assembly language external references...
+;
+    IMPORT      _tx_timer_time_slice
+    IMPORT      _tx_timer_system_clock
+    IMPORT      _tx_timer_current_ptr
+    IMPORT      _tx_timer_list_start
+    IMPORT      _tx_timer_list_end
+    IMPORT      _tx_timer_expired_time_slice
+    IMPORT      _tx_timer_expired
+    IMPORT      _tx_thread_time_slice
+    IMPORT      _tx_timer_expiration_process
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_timer_interrupt                                Cortex-R4/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function processes the hardware timer interrupt.  This         */ 
+;/*    processing includes incrementing the system clock and checking for  */ 
+;/*    time slice and/or timer expiration.  If either is found, the        */ 
+;/*    interrupt context save/restore functions are called along with the  */ 
+;/*    expiration functions.                                               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_timer_expiration_process          Timer expiration processing   */ 
+;/*    _tx_thread_time_slice                 Time slice interrupted thread */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    interrupt vector                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_timer_interrupt(VOID)
+;{
+    EXPORT  _tx_timer_interrupt
+_tx_timer_interrupt
+;
+;    /* Upon entry to this routine, it is assumed that context save has already
+;       been called, and therefore the compiler scratch registers are available
+;       for use.  */
+;
+;    /* Increment the system clock.  */
+;    _tx_timer_system_clock++;
+;
+    LDR     r1, =_tx_timer_system_clock         ; Pickup address of system clock
+    LDR     r0, [r1, #0]                        ; Pickup system clock
+    ADD     r0, r0, #1                          ; Increment system clock
+    STR     r0, [r1, #0]                        ; Store new system clock
+;
+;    /* Test for time-slice expiration.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    LDR     r3, =_tx_timer_time_slice           ; Pickup address of time-slice 
+    LDR     r2, [r3, #0]                        ; Pickup time-slice
+    CMP     r2, #0                              ; Is it non-active?
+    BEQ     __tx_timer_no_time_slice            ; Yes, skip time-slice processing
+;
+;       /* Decrement the time_slice.  */
+;       _tx_timer_time_slice--;
+;
+    SUB     r2, r2, #1                          ; Decrement the time-slice
+    STR     r2, [r3, #0]                        ; Store new time-slice value
+;
+;       /* Check for expiration.  */
+;       if (__tx_timer_time_slice == 0)
+;
+    CMP     r2, #0                              ; Has it expired?
+    BNE     __tx_timer_no_time_slice            ; No, skip expiration processing
+;
+;       /* Set the time-slice expired flag.  */
+;       _tx_timer_expired_time_slice =  TX_TRUE;
+;
+    LDR     r3, =_tx_timer_expired_time_slice   ; Pickup address of expired flag
+    MOV     r0, #1                              ; Build expired value
+    STR     r0, [r3, #0]                        ; Set time-slice expiration flag
+;
+;    }
+;
+__tx_timer_no_time_slice
+;
+;    /* Test for timer expiration.  */
+;    if (*_tx_timer_current_ptr)
+;    {
+;
+    LDR     r1, =_tx_timer_current_ptr          ; Pickup current timer pointer addr
+    LDR     r0, [r1, #0]                        ; Pickup current timer
+    LDR     r2, [r0, #0]                        ; Pickup timer list entry
+    CMP     r2, #0                              ; Is there anything in the list?
+    BEQ     __tx_timer_no_timer                 ; No, just increment the timer
+;
+;        /* Set expiration flag.  */
+;        _tx_timer_expired =  TX_TRUE;
+;
+    LDR     r3, =_tx_timer_expired              ; Pickup expiration flag address
+    MOV     r2, #1                              ; Build expired value
+    STR     r2, [r3, #0]                        ; Set expired flag
+    B       __tx_timer_done                     ; Finished timer processing
+;
+;    }
+;    else
+;    {
+__tx_timer_no_timer
+;
+;        /* No timer expired, increment the timer pointer.  */
+;        _tx_timer_current_ptr++;
+;
+    ADD     r0, r0, #4                          ; Move to next timer
+;
+;        /* Check for wrap-around.  */
+;        if (_tx_timer_current_ptr == _tx_timer_list_end)
+;
+    LDR     r3, =_tx_timer_list_end             ; Pickup addr of timer list end
+    LDR     r2, [r3, #0]                        ; Pickup list end
+    CMP     r0, r2                              ; Are we at list end?
+    BNE     __tx_timer_skip_wrap                ; No, skip wrap-around logic
+;
+;            /* Wrap to beginning of list.  */
+;            _tx_timer_current_ptr =  _tx_timer_list_start;
+;
+    LDR     r3, =_tx_timer_list_start           ; Pickup addr of timer list start
+    LDR     r0, [r3, #0]                        ; Set current pointer to list start
+;
+__tx_timer_skip_wrap
+;
+    STR     r0, [r1, #0]                        ; Store new current timer pointer
+;    }
+;
+__tx_timer_done
+;
+;
+;    /* See if anything has expired.  */
+;    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+;    {
+;
+    LDR     r3, =_tx_timer_expired_time_slice   ; Pickup addr of expired flag
+    LDR     r2, [r3, #0]                        ; Pickup time-slice expired flag
+    CMP     r2, #0                              ; Did a time-slice expire?
+    BNE     __tx_something_expired              ; If non-zero, time-slice expired
+    LDR     r1, =_tx_timer_expired              ; Pickup addr of other expired flag
+    LDR     r0, [r1, #0]                        ; Pickup timer expired flag
+    CMP     r0, #0                              ; Did a timer expire?
+    BEQ     __tx_timer_nothing_expired          ; No, nothing expired
+;
+__tx_something_expired
+;
+;
+    STMDB   sp!, {r0, lr}                       ; Save the lr register on the stack
+                                                ;   and save r0 just to keep 8-byte alignment
+;
+;    /* Did a timer expire?  */
+;    if (_tx_timer_expired)
+;    {
+;
+    LDR     r1, =_tx_timer_expired              ; Pickup addr of expired flag
+    LDR     r0, [r1, #0]                        ; Pickup timer expired flag
+    CMP     r0, #0                              ; Check for timer expiration
+    BEQ     __tx_timer_dont_activate            ; If not set, skip timer activation
+;
+;        /* Process timer expiration.  */
+;        _tx_timer_expiration_process();
+;
+    BL      _tx_timer_expiration_process        ; Call the timer expiration handling routine
+;
+;    }
+__tx_timer_dont_activate
+;
+;    /* Did time slice expire?  */
+;    if (_tx_timer_expired_time_slice)
+;    {
+;
+    LDR     r3, =_tx_timer_expired_time_slice   ; Pickup addr of time-slice expired 
+    LDR     r2, [r3, #0]                        ; Pickup the actual flag
+    CMP     r2, #0                              ; See if the flag is set
+    BEQ     __tx_timer_not_ts_expiration        ; No, skip time-slice processing
+;
+;        /* Time slice interrupted thread.  */
+;        _tx_thread_time_slice(); 
+
+    BL      _tx_thread_time_slice               ; Call time-slice processing
+;
+;    }
+;
+__tx_timer_not_ts_expiration
+;
+    LDMIA   sp!, {r0, lr}                       ; Recover lr register (r0 is just there for
+                                                ;   the 8-byte stack alignment
+;
+;    }
+;
+__tx_timer_nothing_expired
+;
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+;}
+    END
+
diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/.cproject b/ports/cortex_r4/ac6/example_build/sample_threadx/.cproject
new file mode 100644
index 00000000..ba7c73aa
--- /dev/null
+++ b/ports/cortex_r4/ac6/example_build/sample_threadx/.cproject
@@ -0,0 +1,134 @@
+
+
+	
+		
+			
+				
+					
+						
+						
+						
+					
+				
+				
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+					
+						
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+		
+	
+	
+	
+	
+		
+			
+		
+		
+			
+		
+	
+	
+
diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/.project b/ports/cortex_r4/ac6/example_build/sample_threadx/.project
new file mode 100644
index 00000000..a1b15572
--- /dev/null
+++ b/ports/cortex_r4/ac6/example_build/sample_threadx/.project
@@ -0,0 +1,26 @@
+
+
+	sample_threadx
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		org.eclipse.cdt.core.cnature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+
diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_r4/ac6/example_build/sample_threadx/.settings/language.settings.xml
new file mode 100644
index 00000000..9fa316ab
--- /dev/null
+++ b/ports/cortex_r4/ac6/example_build/sample_threadx/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+
+
+	
+		
+			
+			
+			
+			
+				
+				
+			
+		
+	
+	
+		
+			
+			
+			
+			
+				
+				
+			
+		
+	
+
diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/cortex-r4_tx.launch b/ports/cortex_r4/ac6/example_build/sample_threadx/cortex-r4_tx.launch
new file mode 100644
index 00000000..37577868
--- /dev/null
+++ b/ports/cortex_r4/ac6/example_build/sample_threadx/cortex-r4_tx.launch
@@ -0,0 +1,288 @@
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diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/gic.c b/ports/cortex_r4/ac6/example_build/sample_threadx/gic.c
new file mode 100644
index 00000000..32f21bbe
--- /dev/null
+++ b/ports/cortex_r4/ac6/example_build/sample_threadx/gic.c
@@ -0,0 +1,239 @@
+/** GIC start **/
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+#include "gic.h"
+
+#define VE_R4_GIC_DISTRIBUTOR_BASE         (0xAE001000UL)         /*!< (PL390 GIC Distributor ) Base Address */
+#define VE_R4_GIC_INTERFACE_BASE           (0xAE000000UL)         /*!< (PL390 GIC CPU Interface) Base Address */
+
+#define GICDistributor      ((GICDistributor_Type      *)     VE_R4_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
+#define GICInterface        ((GICInterface_Type        *)     VE_R4_GIC_INTERFACE_BASE )   /*!< GIC Interface configuration struct */
+
+/* Globals for use of post-scatterloading code that must access GIC */
+const uint32_t GICDistributor_BASE = VE_R4_GIC_DISTRIBUTOR_BASE;
+const uint32_t GICInterface_BASE = VE_R4_GIC_INTERFACE_BASE;
+
+#if 0
+
+void GIC_SetICDICFR (const uint32_t *ICDICFRn)
+{
+    uint32_t i, num_irq;
+
+    //Get the maximum number of interrupts that the GIC supports
+    num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
+
+    for (i = 0; i < (num_irq/16); i++)
+    {
+        GICDistributor->ICDISPR[i] = *ICDICFRn++;
+    }
+}
+
+uint32_t GIC_DistributorImplementer(void)
+{
+    return (uint32_t)(GICDistributor->ICDIIDR);
+}
+
+uint32_t GIC_GetTarget(IRQn_Type IRQn)
+{
+    char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
+    field += IRQn % 4;
+    return ((uint32_t)*field & 0xf);
+}
+
+IRQn_Type GIC_AcknowledgePending(void)
+{
+    return (IRQn_Type)(GICInterface->ICCIAR);
+}
+
+uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
+{
+    return (uint32_t)GICInterface->ICCBPR;
+}
+
+uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
+{
+    uint32_t pending, active;
+
+    active = ((GICDistributor->ICDABR[IRQn / 32])  >> (IRQn % 32)) & 0x1;
+    pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
+
+    return ((active<<1) | pending);
+}
+
+void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
+{
+    GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
+}
+
+void GIC_EndInterrupt(IRQn_Type IRQn)
+{
+    GICInterface->ICCEOIR = IRQn;
+}
+
+void GIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+    GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+void GIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+    GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
+}
+#endif
+
+void GIC_EnableDistributor(void)
+{
+    GICDistributor->ICDDCR |= 1; //enable distributor
+}
+
+void GIC_DisableDistributor(void)
+{
+    GICDistributor->ICDDCR &=~1; //disable distributor
+}
+
+void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
+{
+    char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
+    field += IRQn % 4;
+    *field = (char)cpu_target & 0xf;
+}
+
+void GIC_EnableInterface(void)
+{
+    GICInterface->ICCICR |= 1; //enable interface
+}
+
+void GIC_DisableInterface(void)
+{
+    GICInterface->ICCICR &=~1; //disable distributor
+}
+
+void GIC_EnableIRQ(IRQn_Type IRQn)
+{
+    GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+void GIC_DisableIRQ(IRQn_Type IRQn)
+{
+    GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
+}
+
+uint32_t GIC_DistributorInfo(void)
+{
+    return (uint32_t)(GICDistributor->ICDICTR);
+}
+
+
+void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
+{   // Word-size read/writes must be used to access this register
+    volatile uint32_t * field = &(GICDistributor->ICDICFR[IRQn / 16]);
+    unsigned bit_shift = (IRQn % 16)<<1;
+    unsigned int save_word;
+
+    save_word = *field;
+    save_word &= (~(3 << bit_shift));
+
+    *field = (save_word | (((edge_level<<1) | model) << bit_shift));
+}
+
+void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+    char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
+    field += IRQn % 4;
+    *field = (char)priority;
+}
+
+uint32_t GIC_GetPriority(IRQn_Type IRQn)
+{
+    char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
+    field += IRQn % 4;
+    return (uint32_t)*field;
+}
+
+void GIC_InterfacePriorityMask(uint32_t priority)
+{
+    GICInterface->ICCPMR = priority & 0xff; //set priority mask
+}
+
+void GIC_SetBinaryPoint(uint32_t binary_point)
+{
+    GICInterface->ICCBPR = binary_point & 0x07; //set binary point
+}
+
+void GIC_DistInit(void)
+{
+    IRQn_Type i;
+    uint32_t num_irq = 0;
+    uint32_t priority_field;
+
+    //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
+    //configuring all of the interrupts as Secure.
+
+    //Disable interrupt forwarding
+    GIC_DisableDistributor();
+    //Get the maximum number of interrupts that the GIC supports
+    num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
+
+    /* Priority level is implementation defined.
+     To determine the number of priority bits implemented write 0xFF to an ICDIPR
+     priority field and read back the value stored.*/
+    GIC_SetPriority((IRQn_Type)0, 0xff);
+    priority_field = GIC_GetPriority((IRQn_Type)0);
+
+    for (i = (IRQn_Type)32; i < num_irq; i++)
+    {
+        //Disable the SPI interrupt
+        GIC_DisableIRQ(i);
+        //Set level-sensitive and 1-N model
+        GIC_SetLevelModel(i, 0, 1);
+        //Set priority
+        GIC_SetPriority(i, priority_field/2);
+        //Set target list to CPU0
+        GIC_SetTarget(i, 1);
+    }
+    //Enable distributor
+    GIC_EnableDistributor();
+}
+
+void GIC_CPUInterfaceInit(void)
+{
+    IRQn_Type i;
+    uint32_t priority_field;
+
+    //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
+    //configuring all of the interrupts as Secure.
+
+    //Disable interrupt forwarding
+    GIC_DisableInterface();
+
+    /* Priority level is implementation defined.
+     To determine the number of priority bits implemented write 0xFF to an ICDIPR
+     priority field and read back the value stored.*/
+    GIC_SetPriority((IRQn_Type)0, 0xff);
+    priority_field = GIC_GetPriority((IRQn_Type)0);
+
+    //SGI and PPI
+    for (i = (IRQn_Type)0; i < 32; i++)
+    {
+        //Set level-sensitive and 1-N model for PPI
+    	if(i > 15)
+            GIC_SetLevelModel(i, 0, 1);
+        //Disable SGI and PPI interrupts
+        GIC_DisableIRQ(i);
+        //Set priority
+        GIC_SetPriority(i, priority_field/2);
+    }
+    //Enable interface
+    GIC_EnableInterface();
+    //Set binary point to 0
+    GIC_SetBinaryPoint(0);
+    //Set priority mask
+    GIC_InterfacePriorityMask(0xff);
+}
+
+void GIC_Enable(void)
+{
+    GIC_DistInit();
+    GIC_CPUInterfaceInit(); //per CPU
+}
+/** GIC end **/
diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/gic.h b/ports/cortex_r4/ac6/example_build/sample_threadx/gic.h
new file mode 100644
index 00000000..7891f74f
--- /dev/null
+++ b/ports/cortex_r4/ac6/example_build/sample_threadx/gic.h
@@ -0,0 +1,360 @@
+/**************************************************************************//**
+ * @file     gic.h
+ * @brief    Generic Interrupt Controller (GIC) functions
+ * @version
+ * @date     29 August 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+#ifndef GIC_H_
+#define GIC_H_
+
+#include "stdint.h"
+
+typedef enum IRQn
+{
+/******  SGI Interrupts Numbers                 ****************************************/
+  SGI0_IRQn            =  0,
+  SGI1_IRQn            =  1,
+  SGI2_IRQn            =  2,
+  SGI3_IRQn            =  3,
+  SGI4_IRQn            =  4,
+  SGI5_IRQn            =  5,
+  SGI6_IRQn            =  6,
+  SGI7_IRQn            =  7,
+  SGI8_IRQn            =  8,
+  SGI9_IRQn            =  9,
+  SGI10_IRQn           = 10,
+  SGI11_IRQn           = 11,
+  SGI12_IRQn           = 12,
+  SGI13_IRQn           = 13,
+  SGI14_IRQn           = 14,
+  SGI15_IRQn           = 15,
+
+/******  Cortex-R4 Processor Exceptions Numbers ****************************************/
+  PrivTimer_IRQn       = 34,        /*!< Private Timer Interrupt                       */
+
+/******  Platform Exceptions Numbers ***************************************************/
+  Watchdog_IRQn        = 32,        /*!< SP805 Interrupt        */
+  Timer0_IRQn          = 34,        /*!< SP804 Interrupt        */
+  Timer1_IRQn          = 35,        /*!< SP804 Interrupt        */
+  RTClock_IRQn         = 36,        /*!< PL031 Interrupt        */
+  UART0_IRQn           = 37,        /*!< PL011 Interrupt        */
+  UART1_IRQn           = 38,        /*!< PL011 Interrupt        */
+  UART2_IRQn           = 39,        /*!< PL011 Interrupt        */
+  UART3_IRQn           = 40,        /*!< PL011 Interrupt        */
+  MCI0_IRQn            = 41,        /*!< PL180 Interrupt (1st)  */
+  MCI1_IRQn            = 42,        /*!< PL180 Interrupt (2nd)  */
+  AACI_IRQn            = 43,        /*!< PL041 Interrupt        */
+  Keyboard_IRQn        = 44,        /*!< PL050 Interrupt        */
+  Mouse_IRQn           = 45,        /*!< PL050 Interrupt        */
+  CLCD_IRQn            = 46,        /*!< PL111 Interrupt        */
+  Ethernet_IRQn        = 47,        /*!< SMSC_91C111 Interrupt  */
+  VFS2_IRQn            = 73,        /*!< VFS2 Interrupt         */
+} IRQn_Type;
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/** \brief  Structure type to access the Generic Interrupt Controller Distributor (GICD)
+ */
+typedef struct
+{
+  __IO uint32_t ICDDCR;
+  __I  uint32_t ICDICTR;
+  __I  uint32_t ICDIIDR;
+       uint32_t RESERVED0[29];
+  __IO uint32_t ICDISR[32];
+  __IO uint32_t ICDISER[32];
+  __IO uint32_t ICDICER[32];
+  __IO uint32_t ICDISPR[32];
+  __IO uint32_t ICDICPR[32];
+  __I  uint32_t ICDABR[32];
+       uint32_t RESERVED1[32];
+  __IO uint32_t ICDIPR[256];
+  __IO uint32_t ICDIPTR[256];
+  __IO uint32_t ICDICFR[64];
+       uint32_t RESERVED2[128];
+  __IO uint32_t ICDSGIR;
+}  GICDistributor_Type;
+
+/** \brief  Structure type to access the Controller Interface (GICC)
+ */
+typedef struct
+{
+  __IO uint32_t ICCICR;          // +0x000 - RW - CPU Interface Control Register
+  __IO uint32_t ICCPMR;          // +0x004 - RW - Interrupt Priority Mask Register
+  __IO uint32_t ICCBPR;          // +0x008 - RW - Binary Point Register
+  __I  uint32_t ICCIAR;          // +0x00C - RO - Interrupt Acknowledge Register
+  __IO uint32_t ICCEOIR;         // +0x010 - WO - End of Interrupt Register
+  __I  uint32_t ICCRPR;          // +0x014 - RO - Running Priority Register
+  __I  uint32_t ICCHPIR;         // +0x018 - RO - Highest Pending Interrupt Register
+  __IO uint32_t ICCABPR;         // +0x01C - RW - Aliased Binary Point Register
+
+       uint32_t RESERVED[55];
+
+  __I  uint32_t ICCIIDR;         // +0x0FC - RO - CPU Interface Identification Register
+}  GICInterface_Type;
+
+/*@} end of GICD */
+
+/* ##########################   GIC functions  #################################### */
+/**  \brief      Functions that manage interrupts via the GIC.
+  @{
+ */
+
+/** \brief  Enable DistributorGICInterface->ICCICR |= 1; //enable interface
+
+   Enables the forwarding of pending interrupts to the CPU interfaces.
+
+ */
+void GIC_EnableDistributor(void);
+
+/** \brief  Disable Distributor
+
+   Disables the forwarding of pending interrupts to the CPU interfaces.
+
+ */
+void GIC_DisableDistributor(void);
+
+/** \brief  Provides information about the configuration of the GIC.
+   Provides information about the configuration of the GIC.
+   - whether the GIC implements the Security Extensions
+   - the maximum number of interrupt IDs that the GIC supports
+   - the number of CPU interfaces implemented
+   - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
+
+   \return Distributor Information.
+ */
+uint32_t GIC_DistributorInfo(void);
+
+/** \brief  Distributor Implementer Identification Register.
+
+   Distributor Implementer Identification Register
+
+   \return Implementer Information.
+ */
+uint32_t GIC_DistributorImplementer(void);
+
+/** \brief  Set list of processors that the interrupt is sent to if it is asserted.
+
+    The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
+    This field stores the list of processors that the interrupt is sent to if it is asserted.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]    target  CPU target
+ */
+void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target);
+
+/** \brief  Get list of processors that the interrupt is sent to if it is asserted.
+
+    The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
+    This field stores the list of processors that the interrupt is sent to if it is asserted.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]    target  CPU target
+*/
+uint32_t GIC_GetTarget(IRQn_Type IRQn);
+
+/** \brief  Enable Interface
+
+   Enables the signalling of interrupts to the target processors.
+
+ */
+void GIC_EnableInterface(void);
+
+/** \brief  Disable Interface
+
+   Disables the signalling of interrupts to the target processors.
+
+ */
+void GIC_DisableInterface(void);
+
+/** \brief  Acknowledge Interrupt
+
+    The function acknowledges the highest priority pending interrupt and returns its IRQ number.
+
+    \return             Interrupt number
+ */
+IRQn_Type GIC_AcknowledgePending(void);
+
+/** \brief  End Interrupt
+
+    The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
+
+    \param [in]   IRQn  Interrupt number.
+ */
+void GIC_EndInterrupt(IRQn_Type IRQn);
+
+
+/** \brief  Enable Interrupt
+
+    Set-enable bit for each interrupt supported by the GIC.
+
+    \param [in]      IRQn  External interrupt number.
+ */
+void GIC_EnableIRQ(IRQn_Type IRQn);
+
+/** \brief  Disable Interrupt
+
+    Clear-enable bit for each interrupt supported by the GIC.
+
+    \param [in]      IRQn  Number of the external interrupt to disable
+ */
+void GIC_DisableIRQ(IRQn_Type IRQn);
+
+/** \brief  Set Pending Interrupt
+
+    Set-pending bit for each interrupt supported by the GIC.
+
+    \param [in]      IRQn  Interrupt number.
+ */
+void GIC_SetPendingIRQ(IRQn_Type IRQn);
+
+/** \brief  Clear Pending Interrupt
+
+    Clear-pending bit for each interrupt supported by the GIC
+
+    \param [in]      IRQn  Number of the interrupt for clear pending
+ */
+void GIC_ClearPendingIRQ(IRQn_Type IRQn);
+
+/** \brief  Int_config field for each interrupt supported by the GIC.
+
+    This field identifies whether the corresponding interrupt is:
+    (1) edge-triggered or (0) level-sensitive
+    (1) 1-N model or (0) N-N model
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in] edge_level (1) edge-triggered or (0) level-sensitive
+    \param [in] model      (1) 1-N model or (0) N-N model
+ */
+void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model);
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt.
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority.
+ */
+uint32_t GIC_GetPriority(IRQn_Type IRQn);
+
+/** \brief  CPU Interface Priority Mask Register
+
+    The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
+    value indicated by this field, the interface signals the interrupt to the processor.
+
+    \param [in]   Mask.
+ */
+void GIC_InterfacePriorityMask(uint32_t priority);
+
+/** \brief  Set the binary point.
+
+     Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
+
+    \param [in]   Mask.
+ */
+void GIC_SetBinaryPoint(uint32_t binary_point);
+
+/** \brief  Get the binary point.
+
+     Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
+
+    \return  Binary point.
+ */
+uint32_t GIC_GetBinaryPoint(uint32_t binary_point);
+
+/** \brief  Get Interrupt state.
+
+     Get the interrupt state, whether pending and/or active
+
+    \return  0 - inactive, 1 - pending, 2 - active, 3 - pending and active
+ */
+uint32_t GIC_GetIRQStatus(IRQn_Type IRQn);
+
+/** \brief  Send Software Generated interrupt
+
+    Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
+GIC_InterfacePriorityMask
+    \param [in]   IRQn         The Interrupt ID of the SGI.
+    \param [in]   target_list  CPUTargetList
+    \param [in]   filter_list  TargetListFilter
+ */
+void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list);
+
+/** \brief  API call to initialise the interrupt distributor
+
+   API call to initialise the interrupt distributor
+
+ */
+void GIC_DistInit(void);
+
+/** \brief  API call to initialise the CPU interface
+
+   API call to initialise the CPU interface
+
+ */
+void GIC_CPUInterfaceInit(void);
+
+/** \brief  API call to set the Interrupt Configuration Registers
+
+   API call to initialise the Interrupt Configuration Registers
+
+ */
+void GIC_SetICDICFR (const uint32_t *ICDICFRn);
+
+/** \brief  API call to  Enable the GIC
+
+   API call to  Enable the GIC
+
+ */
+void GIC_Enable(void);
+
+#endif /* GIC_H_ */
diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c
new file mode 100644
index 00000000..a32037a6
--- /dev/null
+++ b/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.c
@@ -0,0 +1,373 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include "tx_api.h"
+#include "timer.h"
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_BYTE_POOL_SIZE     9120
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+/* Define main entry point.  */
+
+int main()
+{
+
+    /* Setup the timer. */
+    timer_init();
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+UINT    status;
+CHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    status = tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.scat
new file mode 100644
index 00000000..926647b2
--- /dev/null
+++ b/ports/cortex_r4/ac6/example_build/sample_threadx/sample_threadx.scat
@@ -0,0 +1,39 @@
+;**************************************************
+; Copyright (c) 2017 ARM Ltd.  All rights reserved.
+;**************************************************
+
+; Scatter-file for RTX Example on Versatile Express R4
+
+; This scatter-file places application code, data and peripherals at suitable addresses in the memory map.
+
+; This platform has 2GB SDRAM starting at 0x0.
+
+
+SDRAM 0x0 0x40000000
+{
+    CODE +0 0x200000
+    {
+        startup.o (Vectors, +FIRST)       ; Vector table and other (assembler) startup code
+        * (InRoot$$Sections)      ; All (library) code that must be in a root region
+        * (+RO-CODE)              ; Application RO code (.text)
+        * (+RO-DATA)              ; Application RO data (.constdata)
+    }
+    
+	IRQ_STACK +0 ALIGN 8 EMPTY 1024 {}
+	
+    FIQ_STACK +0 ALIGN 8 EMPTY 512 {}
+	
+    SVC_STACK +0 ALIGN 8 EMPTY 2048 {}
+    
+    SYS_STACK +0 ALIGN 8 EMPTY 2048 {}
+    
+    ABORT_STACK +0 ALIGN 8 EMPTY 2048 {}
+
+    ; Application RW & ZI data (.data & .bss)
+    DATA +0 0x100000
+    {
+        * (+RW,+ZI) 
+    }
+
+    PERIPHERALS 0xA0000000 EMPTY 0x20000000 { }; Peripherals
+}
diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/startup.S b/ports/cortex_r4/ac6/example_build/sample_threadx/startup.S
new file mode 100644
index 00000000..98d3b2b1
--- /dev/null
+++ b/ports/cortex_r4/ac6/example_build/sample_threadx/startup.S
@@ -0,0 +1,249 @@
+//----------------------------------------------------------------
+// Cortex-R4(F) Embedded example - Startup Code
+//
+// Copyright (c) 2006-2018 Arm Limited (or its affiliates). All rights reserved.
+// Use, modification and redistribution of this file is subject to your possession of a
+// valid End User License Agreement for the Arm Product of which these examples are part of 
+// and your compliance with all applicable terms and conditions of such licence agreement.
+//----------------------------------------------------------------
+
+
+#define FIQ_MODE        0x11
+#define IRQ_MODE        0x12
+#define SVC_MODE        0x13
+#define ABT_MODE        0x17
+#define SYS_MODE        0x1F
+
+//----------------------------------------------------------------
+
+    .eabi_attribute Tag_ABI_align8_preserved,1
+
+    .section  VECTORS,"ax"
+    .align 3
+    .cfi_sections .debug_frame  // put stack frame info into .debug_frame instead of .eh_frame
+
+//----------------------------------------------------------------
+// Exception Vector Table
+//----------------------------------------------------------------
+// Note: LDR PC instructions are used here, though branch (B) instructions
+// could also be used, unless the exception handlers are >32MB away.
+
+    .global Vectors
+
+Vectors:
+    LDR PC, Reset_Addr
+    LDR pc,=__tx_undefined                  // Undefined handler
+    LDR pc,=__tx_swi_interrupt              // Software interrupt handler
+    LDR pc,=__tx_prefetch_handler           // Prefetch exception handler
+    LDR pc,=__tx_abort_handler              // Abort exception handler
+    LDR pc,=__tx_reserved_handler           // Reserved exception handler
+    LDR pc,=__tx_irq_handler                // IRQ interrupt handler
+    LDR pc,=__tx_fiq_handler                // FIQ interrupt handler
+
+
+    .balign 4
+Reset_Addr:     .word Reset_Handler
+Undefined_Addr: .word __tx_undefined
+SVC_Addr:       .word __tx_swi_interrupt
+Prefetch_Addr:  .word __tx_prefetch_handler
+Abort_Addr:     .word __tx_abort_handler
+IRQ_Addr:       .word __tx_irq_handler
+FIQ_Addr:       .word __tx_fiq_handler
+
+
+//----------------------------------------------------------------
+// Reset Handler
+//----------------------------------------------------------------
+
+    .global Reset_Handler
+    .type Reset_Handler, "function"
+Reset_Handler:
+
+//----------------------------------------------------------------
+// Disable MPU and caches
+//----------------------------------------------------------------
+
+// Disable MPU and cache in case it was left enabled from an earlier run
+// This does not need to be done from a cold reset
+
+        MRC     p15, 0, r0, c1, c0, 0       // Read System Control Register
+        BIC     r0, r0, #(0x1 << 12)        // Clear I bit 12 to disable I Cache
+        BIC     r0, r0, #(0x1 <<  2)        // Clear C bit  2 to disable D Cache
+        BIC     r0, r0, #0x1                // Clear M bit  0 to disable MPU
+        DSB                                 // Ensure all previous loads/stores have completed
+        MCR     p15, 0, r0, c1, c0, 0       // Write System Control Register
+        ISB                                 // Ensure subsequent insts execute wrt new MPU settings
+
+//----------------------------------------------------------------
+// Disable Branch prediction
+//----------------------------------------------------------------
+
+// In the Cortex-R4, the Z-bit of the SCTLR does not control the program flow prediction.
+// Some control bits in the ACTLR control the program flow and prefetch features instead.
+// These are enabled by default, but are shown here for completeness.
+
+        MRC     p15, 0, r0, c1, c0, 1       // Read ACTLR
+        ORR     r0, r0, #(0x1 << 17)        // Enable RSDIS bit 17 to disable the return stack
+        ORR     r0, r0, #(0x1 << 16)        // Clear BP bit 15 and set BP bit 16:
+        BIC     r0, r0, #(0x1 << 15)        // Branch always not taken and history table updates disabled
+        MCR     p15, 0, r0, c1, c0, 1       // Write ACTLR
+        ISB
+
+//----------------------------------------------------------------
+// Cache invalidation
+//----------------------------------------------------------------
+
+        DSB                 // Complete all outstanding explicit memory operations
+
+        MOV     r0, #0
+
+        MCR     p15, 0, r0, c7, c5, 0       // Invalidate entire instruction cache
+        MCR     p15, 0, r0, c15, c5, 0      // Invalidate entire data cache
+
+
+//----------------------------------------------------------------
+// Initialize Supervisor Mode Stack using Linker symbol from scatter file.
+// Stacks must be 8 byte aligned.
+//----------------------------------------------------------------
+
+    /****** NOTE ****** We must be in SVC MODE at this point.  Some monitors
+       enter this routine in USER mode and require a software interrupt to
+       change into SVC mode.  */
+
+#ifdef TX_ENABLE_IRQ_NESTING
+    /* Setup the system mode stack for nested interrupt support  */
+    MOV     r3, #SYS_MODE                       // Build SYS mode CPSR
+    MSR     CPSR_c, r3                          // Enter SYS mode
+    LDR     sp, =Image$$SYS_STACK$$ZI$$Limit    // Setup SYS stack pointer
+#endif
+
+	CPS     #ABT_MODE                           // Build Abort mode CPSR
+    LDR     sp, =Image$$ABORT_STACK$$ZI$$Limit  // Setup abort stack pointer
+
+    CPS		#FIQ_MODE                       	// Build FIQ mode CPSR
+    LDR     sp, =Image$$FIQ_STACK$$ZI$$Limit    // Setup FIQ stack pointer
+    MOV     sl, #0                              // Clear sl
+    MOV     fp, #0                              // Clear fp
+
+    CPS 	#IRQ_MODE                       	// Build IRQ mode CPSR
+    LDR     sp, =Image$$IRQ_STACK$$ZI$$Limit    // Setup IRQ stack pointer
+
+    CPS    	#SVC_MODE                       	// Build SVC mode CPSR
+    LDR     sp, =Image$$SVC_STACK$$ZI$$Limit    // Setup SVC stack pointer
+
+
+//----------------------------------------------------------------
+// TCM Configuration
+//----------------------------------------------------------------
+
+// Cortex-R4 optionally provides two Tightly-Coupled Memory (TCM) blocks (ATCM and BTCM) for fast access to code or data.
+// ATCM typically holds interrupt or exception code that must be accessed at high speed,
+//    without any potential delay resulting from a cache miss.
+// BTCM typically holds a block of data for intensive processing, such as audio or video data.
+// In the Cortex-R4 processor, both ATCM and BTCM support both instruction and data accesses.
+
+// The following illustrates basic TCM configuration, as the basis for exploration by the user
+
+#ifdef TCM
+    .global  Image$$ATCM$$Base
+    .global  Image$$BTCM0$$Base
+    .global  Image$$BTCM1$$Base
+
+        MRC     p15, 0, r0, c0, c0, 2       // Read TCM Type Register
+        // r0 now contains ATCM & BTCM availability
+
+        MRC     p15, 0, r0, c9, c1, 1       // Read ATCM Region Register
+        // r0 now contains ATCM size in bits [6:2]
+
+        MRC     p15, 0, r0, c9, c1, 0       // Read BTCM Region Register
+        // r0 now contains BTCM size in bits [6:2]
+
+// The Cortex-R4F Core Tile has
+// 64K ATCM  from 0xE0FD0000 to 0xE0FDFFFF
+// 64K BTCM0 from 0xE0FE0000 to 0xE0FEFFFF
+// 64K BTCM1 from 0xE0FF0000 to 0xE0FFFFFF
+
+        LDR     r0, =Image$$ATCM$$Base      // Set ATCM base address
+        ORR     r0, r0, #1                  // Enable it
+        MCR     p15, 0, r0, c9, c1, 1       // Write ATCM Region Register
+
+        LDR     r0, =Image$$BTCM0$$Base     // Set BTCM base address
+        ORR     r0, r0, #1                  // Enable it
+        MCR     p15, 0, r0, c9, c1, 0       // Write BTCM Region Register
+
+#endif
+
+#ifdef __ARM_FP
+//----------------------------------------------------------------
+// Enable access to VFP by enabling access to Coprocessors 10 and 11.
+// Enables Full Access i.e. in both privileged and non privileged modes
+//----------------------------------------------------------------
+
+        MRC     p15, 0, r0, c1, c0, 2      // Read Coprocessor Access Control Register (CPACR)
+        ORR     r0, r0, #(0xF << 20)       // Enable access to CP 10 & 11
+        MCR     p15, 0, r0, c1, c0, 2      // Write Coprocessor Access Control Register (CPACR)
+        ISB
+
+//----------------------------------------------------------------
+// Switch on the VFP hardware
+//----------------------------------------------------------------
+
+        MOV     r0, #0x40000000
+        VMSR    FPEXC, r0                   // Write FPEXC register, EN bit set
+#endif
+
+//----------------------------------------------------------------
+// Enable Branch prediction
+//----------------------------------------------------------------
+
+// In the Cortex-R4, the Z-bit of the SCTLR does not control the program flow prediction. 
+// Some control bits in the ACTLR control the program flow and prefetch features instead.
+// These are enabled by default, but are shown here for completeness.
+
+        MRC     p15, 0, r0, c1, c0, 1       // Read ACTLR
+        BIC     r0, r0, #(0x1 << 17)        // Clear RSDIS bit 17 to enable return stack
+        BIC     r0, r0, #(0x1 << 16)        // Clear BP bit 15 and BP bit 16:
+        BIC     r0, r0, #(0x1 << 15)        // Normal operation, BP is taken from the global history table.
+        MCR     p15, 0, r0, c1, c0, 1       // Write ACTLR
+        ISB
+
+
+        /* Enable the GIC.  */
+        BL      GIC_Enable
+
+    .global     __main
+        B       __main
+
+    .size Reset_Handler, . - Reset_Handler
+
+//----------------------------------------------------------------
+// Global Enable for Instruction and Data Caching
+//----------------------------------------------------------------
+
+    .global enable_caches
+
+    .type enable_caches, "function"
+    .cfi_startproc
+enable_caches:
+
+        MRC     p15, 0, r0, c1, c0, 0       // Read System Control Register
+        ORR     r0, r0, #(0x1 << 12)        // enable I Cache
+        ORR     r0, r0, #(0x1 << 2)         // enable D Cache
+        MCR     p15, 0, r0, c1, c0, 0       // Write System Control Register
+        ISB
+
+        BX    lr
+    .cfi_endproc
+
+    .size enable_caches, . - enable_caches
+
+/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code.  This
+    routine will set the initial stack to use the ThreadX IRQ & FIQ &
+    (optionally SYS) stack areas.  */
+
+    .global __user_initial_stackheap
+    .type   __user_initial_stackheap, %function
+__user_initial_stackheap:
+
+    LDR     r1, =Image$$SVC_STACK$$ZI$$Limit
+    BX      lr                                  // Return to caller
diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/timer.c b/ports/cortex_r4/ac6/example_build/sample_threadx/timer.c
new file mode 100644
index 00000000..e964d0f6
--- /dev/null
+++ b/ports/cortex_r4/ac6/example_build/sample_threadx/timer.c
@@ -0,0 +1,28 @@
+#include "gic.h"
+
+/* Systick registers */
+#define PRIVTIM_IRQ     34
+#define PRIVATE_TIMER_BASE (0xB0110000)
+#define PRIVTIM_RELOAD  (*((volatile uint32_t *)(PRIVATE_TIMER_BASE + 0x0)))
+#define PRIVTIM_CURRENT (*((volatile uint32_t *)(PRIVATE_TIMER_BASE + 0x4)))
+#define PRIVTIM_CTRL    (*((volatile uint32_t *)(PRIVATE_TIMER_BASE + 0x8)))
+#define PRIVTIM_STATUS  (*((volatile uint32_t *)(PRIVATE_TIMER_BASE + 0xc)))
+
+#define OS_CLOCK       12000000
+#define OS_TICK        1000
+#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+#define U32 uint32_t
+#define GICD_ICDICER0   (*((volatile U32 *)(GICDistributor_BASE + 0x180))) /* - RW - Interrupt Clear-Enable Registers */
+#define GICD_ICDISER0   (*((volatile U32 *)(GICDistributor_BASE + 0x100))) /* - RW - Interrupt Set-Enable Registers */
+#define GICD_ICDIPR0    (*((volatile U32 *)(GICDistributor_BASE + 0x400))) /* - RW - Interrupt Priority Registers */
+#define GICD_ICDSGIR    (*((volatile U32 *)(GICDistributor_BASE + 0xf00))) /* - RW - Interrupt Software Interrupt Register */
+#define GICD_ICDICERx(irq)   *(volatile U32 *)(&GICD_ICDICER0 + irq/32)
+#define GICD_ICDISERx(irq)   *(volatile U32 *)(&GICD_ICDISER0 + irq/32)
+
+void timer_init()
+{
+    GIC_EnableIRQ(34);
+    PRIVTIM_RELOAD  = 0x200;
+    PRIVTIM_CTRL    |= 0xC0; /* Enable timer, periodic mode */
+}
diff --git a/ports/cortex_r4/ac6/example_build/sample_threadx/timer.h b/ports/cortex_r4/ac6/example_build/sample_threadx/timer.h
new file mode 100644
index 00000000..efab1fe1
--- /dev/null
+++ b/ports/cortex_r4/ac6/example_build/sample_threadx/timer.h
@@ -0,0 +1,4 @@
+#ifndef TIMER_H
+#define TIMER_H
+void timer_init();
+#endif
diff --git a/ports/cortex_r4/ac6/example_build/tx/.cproject b/ports/cortex_r4/ac6/example_build/tx/.cproject
new file mode 100644
index 00000000..fed5c2d2
--- /dev/null
+++ b/ports/cortex_r4/ac6/example_build/tx/.cproject
@@ -0,0 +1,135 @@
+
+
+	
+		
+			
+				
+					
+						
+						
+						
+					
+				
+				
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+					
+						
+					
+				
+			
+			
+		
+		
+			
+				
+				
+					
+					
+					
+				
+			
+			
+				
+					
+						
+							
+					
+					
+						
+					
+				
+			
+			
+		
+	
+	
+		
+	
+	
+		
+	
+	
+	
+		
+			
+		
+		
+			
+		
+	
+	
+	
+
diff --git a/ports/cortex_r4/ac6/example_build/tx/.project b/ports/cortex_r4/ac6/example_build/tx/.project
new file mode 100644
index 00000000..161d4e8f
--- /dev/null
+++ b/ports/cortex_r4/ac6/example_build/tx/.project
@@ -0,0 +1,48 @@
+
+
+	tx
+	
+	
+	
+	
+		
+			org.eclipse.cdt.managedbuilder.core.genmakebuilder
+			clean,full,incremental,
+			
+			
+		
+		
+			org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+			full,incremental,
+			
+			
+		
+	
+	
+		org.eclipse.cdt.core.cnature
+		org.eclipse.cdt.managedbuilder.core.managedBuildNature
+		org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+	
+	
+		
+			inc_common
+			2
+			$%7BPARENT-5-PROJECT_LOC%7D/common/inc
+		
+		
+			inc_port
+			2
+			$%7BPARENT-2-PROJECT_LOC%7D/inc
+		
+		
+			src_common
+			2
+			$%7BPARENT-5-PROJECT_LOC%7D/common/src
+		
+		
+			src_port
+			2
+			$%7BPARENT-2-PROJECT_LOC%7D/src
+		
+	
+
diff --git a/ports/cortex_r4/ac6/example_build/tx/.settings/language.settings.xml b/ports/cortex_r4/ac6/example_build/tx/.settings/language.settings.xml
new file mode 100644
index 00000000..b515c43e
--- /dev/null
+++ b/ports/cortex_r4/ac6/example_build/tx/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+
+
+	
+		
+			
+			
+			
+			
+				
+				
+			
+		
+	
+	
+		
+			
+			
+			
+			
+				
+				
+			
+		
+	
+
diff --git a/ports/cortex_r4/ac6/inc/tx_port.h b/ports/cortex_r4/ac6/inc/tx_port.h
new file mode 100644
index 00000000..5a38b4bf
--- /dev/null
+++ b/ports/cortex_r4/ac6/inc/tx_port.h
@@ -0,0 +1,341 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */ 
+/*                                                                        */ 
+/*    tx_port.h                                         Cortex-R4/AC6     */ 
+/*                                                           6.0.1        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This file contains data type definitions that make the ThreadX      */ 
+/*    real-time kernel function identically on a variety of different     */ 
+/*    processor architectures.  For example, the size or number of bits   */ 
+/*    in an "int" data type vary between microprocessor architectures and */ 
+/*    even C compilers for the same microprocessor.  ThreadX does not     */ 
+/*    directly use native C data types.  Instead, ThreadX creates its     */ 
+/*    own special types that can be mapped to actual data types by this   */ 
+/*    file to guarantee consistency in the interface and functionality.   */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+/* Define compiler intrinsics.  */
+
+#include "arm_compat.h"
+
+/* Define compiler library include files.  */
+
+#include 
+#include 
+
+
+/* Define ThreadX basic types for this port.  */ 
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */ 
+#endif
+
+
+/* Define various constants for the ThreadX ARM port.  */ 
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_INT_DISABLE                          0xC0        /* Disable IRQ & FIQ interrupts     */
+#else
+#define TX_INT_DISABLE                          0x80        /* Disable IRQ interrupts           */
+#endif
+#define TX_INT_ENABLE                           0x00        /* Enable IRQ interrupts            */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ++_tx_trace_simulated_time
+#endif
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_FIQ_ENABLED                          1
+#else
+#define TX_FIQ_ENABLED                          0
+#endif
+
+#ifdef TX_ENABLE_IRQ_NESTING
+#define TX_IRQ_NESTING_ENABLED                  2
+#else
+#define TX_IRQ_NESTING_ENABLED                  0
+#endif
+
+#ifdef TX_ENABLE_FIQ_NESTING
+#define TX_FIQ_NESTING_ENABLED                  4
+#else
+#define TX_FIQ_NESTING_ENABLED                  0
+#endif
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#define TX_INLINE_INITIALIZATION
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#define TX_THREAD_EXTENSION_2                  ULONG       tx_thread_vfp_enable;
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef __thumb
+
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       m = m & ((ULONG) (-((LONG) m))); \
+                                                b = (ULONG) __clz((unsigned int) m); \
+                                                b = 31 - b; 
+#endif
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifndef __thumb
+
+#define TX_INTERRUPT_SAVE_AREA                  register unsigned int interrupt_save_disabled;
+
+#ifdef  TX_ENABLE_FIQ_SUPPORT
+
+/* IRQ and FIQ support.  */
+
+#define TX_DISABLE                              __memory_changed(), interrupt_save_disabled =  __disable_irq(); \
+                                                __disable_fiq();
+
+#define TX_RESTORE                              if (!interrupt_save_disabled) \
+                                                { \
+                                                    __enable_irq(); \
+                                                    __enable_fiq(); \
+                                                } 
+
+#else
+
+#define TX_DISABLE                              __memory_changed(), interrupt_save_disabled =  __disable_irq();
+
+#define TX_RESTORE                              if (!interrupt_save_disabled) \
+                                                { \
+                                                    __enable_irq(); \
+                                                } 
+#endif
+
+#else
+
+unsigned int   _tx_thread_interrupt_disable(void);
+unsigned int   _tx_thread_interrupt_restore(UINT old_posture);
+
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int interrupt_save;
+
+#define TX_DISABLE                              interrupt_save =  _tx_thread_interrupt_disable();
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+#endif
+
+
+/* Define VFP extension for the Cortex-R4.  Each is assumed to be called in the context of the executing
+   thread.  */
+
+void    tx_thread_vfp_enable(void);
+void    tx_thread_vfp_disable(void);
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Cortex-R4/AC6 Version 6.0 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+
+#endif
+
+
+
+
+
diff --git a/ports/cortex_r4/ac6/readme_threadx.txt b/ports/cortex_r4/ac6/readme_threadx.txt
new file mode 100644
index 00000000..a5849018
--- /dev/null
+++ b/ports/cortex_r4/ac6/readme_threadx.txt
@@ -0,0 +1,392 @@
+                     Microsoft's Azure RTOS ThreadX for Cortex-R4 
+
+                               Thumb & 32-bit Mode
+
+                            Using ARM Compiler 6 & DS
+
+1. Import the ThreadX Projects
+
+In order to build the ThreadX library and the ThreadX demonstration, first move 
+the project folders into your DS workspace directory. The project folders are 
+named 'tx' and 'sample_threadx' and are located in the installation directory. 
+
+Now that the projects are in the workspace directory, import them into DS by
+doing the following for each project: 
+
+    1. Click 'File -> Import -> Existing Projects into Workspace'
+    2. Set the root directory the project i.e. the 'tx' or 'sample_threadx' directory
+    3. Click 'Finish'
+
+Note: the projects were made using DS-5, so DS will prompt you to migrate the projects.
+This is expected, so please do so.
+
+
+2.  Building the ThreadX run-time Library
+
+Building the ThreadX library is easy; simply right-click the Eclipse project 
+"tx" and then select the "Build Project" button. You should now observe the compilation 
+and assembly of the ThreadX library. This project build produces the ThreadX
+library file tx.a.
+
+
+3.  Demonstration System
+
+The ThreadX demonstration is designed to execute under the DS-5 debugger on the
+VE_Cortex-R4 Bare Metal simulator.
+
+Building the demonstration is easy; simply right-click the Eclipse project 
+"sample_threadx" and then select the "Build Project" button. You should now observe 
+the compilation and assembly of the ThreadX demonstration. This project build produces 
+the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder 
+in the Project Explorer window, right-click on the 'cortex-r4_tx.launch' file, click
+'Debug As', and then click 'cortex-r4_tx' from the submenu. This will cause the
+debugger to load the sample_threadx.axf ELF file and run to main. You are now ready 
+to execute the ThreadX demonstration.
+
+
+4.  System Initialization
+
+The entry point in ThreadX for the Cortex-R4 using ARM tools is at label 
+"Vectors". This is defined within startup.S in the sample_threadx project. In addition, 
+this is where all static and global pre-set C variable initialization processing 
+takes place.
+
+The ThreadX tx_initialize_low_level.s file is responsible for determining the 
+first available RAM address for use by the application, which is supplied as the 
+sole input parameter to your application definition function, tx_application_define.
+
+
+5.  Register Usage and Stack Frames
+
+The ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch 
+registers for each function. All other registers used by a C function must 
+be preserved by the function. ThreadX takes advantage of this in situations 
+where a context switch happens as a result of making a ThreadX service call 
+(which is itself a C function). In such cases, the saved context of a thread 
+is only the non-scratch registers.
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have one of these two types of stack frames. The top
+of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the 
+associated thread control block TX_THREAD.
+
+
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x00                   1                           0
+     0x04                   CPSR                        CPSR
+     0x08                   r0  (a1)                    r4  (v1)
+     0x0C                   r1  (a2)                    r5  (v2)
+     0x10                   r2  (a3)                    r6  (v3)
+     0x14                   r3  (a4)                    r7  (v4)
+     0x18                   r4  (v1)                    r8  (v5)
+     0x1C                   r5  (v2)                    r9  (v6)
+     0x20                   r6  (v3)                    r10 (v7)
+     0x24                   r7  (v4)                    r11 (fp)
+     0x28                   r8  (v5)                    r14 (lr)
+     0x2C                   r9  (v6)                        
+     0x30                   r10 (v7)                        
+     0x34                   r11 (fp)                        
+     0x38                   r12 (ip)                         
+     0x3C                   r14 (lr)
+     0x40                   PC 
+
+
+6.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+breakpoints inside of ThreadX itself. Of course, this costs some 
+performance. To make it run faster, you can change the build_threadx.bat file to 
+remove the -g option and enable all compiler optimizations. 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+7.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-R4
+targets. There are a certain set of requirements that are defined in the 
+following sub-sections:
+
+
+7.1  Vector Area
+
+The Cortex-R4 vectors start at address zero. The demonstration system startup.S
+file contains the vectors and is loaded at address zero. On actual hardware platforms, 
+this area might have to be copied to address 0. 
+
+
+7.2  IRQ ISRs
+
+ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested
+IRQ interrupts. The following sub-sections define the IRQ capabilities.
+
+
+7.2.1 Standard IRQ ISRs
+
+The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ 
+interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following 
+is the default IRQ handler defined in tx_initialize_low_level.s:
+
+    .global __tx_irq_handler
+    .type   __tx_irq_handler, %function
+__tx_irq_handler:
+
+    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+
+    ...
+
+    /* At this point execution is still in the IRQ mode.  The CPSR, point of
+       interrupt, and all C scratch registers are available for use.  In
+       addition, IRQ interrupts may be re-enabled - with certain restrictions -
+       if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
+       small code sequences where lr is saved before enabling interrupts and
+       restored after interrupts are again disabled.  */
+
+    /* Application IRQ handlers can be called here!  */
+
+    ...
+
+    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+7.2.2 Vectored IRQ ISRs
+
+The vectored ARM ISR mechanism has multiple interrupt vectors at addresses specified
+by the particular implementation. The following is an example ISR handler defined in 
+tx_initialize_low_level.s:
+
+    .global __tx_example_vectored_irq_handler
+    .type   __tx_example_vectored_irq_handler, %function
+__tx_example_vectored_irq_handler:
+
+
+    /* Save initial context and call context save to prepare for
+       vectored ISR execution. */
+
+    STMDB   sp!, {r0-r3}                        // Save some scratch registers
+    MRS     r0, SPSR                            // Pickup saved SPSR
+    SUB     lr, lr, #4                          // Adjust point of interrupt
+    STMDB   sp!, {r0, r10, r12, lr}             // Store other scratch registers
+    BL      _tx_thread_vectored_context_save    // Vectored context save
+
+    ...
+
+    /* At this point execution is still in the IRQ mode.  The CPSR, point of
+       interrupt, and all C scratch registers are available for use.  In
+       addition, IRQ interrupts may be re-enabled - with certain restrictions -
+       if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
+       small code sequences where lr is saved before enabling interrupts and
+       restored after interrupts are again disabled.  */
+
+    /* Application IRQ handlers can be called here!  */
+
+    ...
+
+    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.2.3  Nested IRQ Support
+
+By default, nested IRQ interrupt support is not enabled. To enable nested
+IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING
+defined. With this defined, two new IRQ interrupt management services are
+available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end.
+These function should be called between the IRQ context save and restore
+calls. 
+
+Execution between the calls to _tx_thread_irq_nesting_start and 
+_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved 
+by switching from IRQ mode to SYS mode and enabling IRQ interrupts.
+The SYS mode stack is used during the SYS mode operation, which was 
+setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required,
+calling the _tx_thread_irq_nesting_end service disables nesting by disabling
+IRQ interrupts and switching back to IRQ mode in preparation for the IRQ 
+context restore service.
+
+The following is an example of enabling IRQ nested interrupts in a standard 
+IRQ handler:
+
+    .global __tx_irq_handler
+    .type   __tx_irq_handler, %function
+    .global __tx_irq_processing_return
+    .type   __tx_irq_processing_return, %function
+__tx_irq_handler:
+
+    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return:
+
+    ...
+
+    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start
+       from IRQ mode with interrupts disabled.  This routine switches to the
+       system mode and returns with IRQ interrupts enabled. */
+
+    /* NOTE:  It is very important to ensure all IRQ interrupts are cleared
+       prior to enabling nested IRQ interrupts.  */
+    BL      _tx_thread_irq_nesting_start
+
+    /* Application IRQ handlers can be called here!  */
+
+    ...
+
+    /* If interrupt nesting was started earlier, the end of interrupt nesting
+       service must be called before returning to _tx_thread_context_restore.
+       This routine returns in processing in IRQ mode with interrupts disabled.  */
+    BL      _tx_thread_irq_nesting_end
+
+    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.3  FIQ Interrupts
+
+By default, Cortex-R4 FIQ interrupts are left alone by ThreadX. Of course, this 
+means that the application is fully responsible for enabling the FIQ interrupt 
+and saving/restoring any registers used in the FIQ ISR processing. To globally 
+enable FIQ interrupts, the application should enable FIQ interrupts at the 
+beginning of each thread or before any threads are created in tx_application_define. 
+In addition, the application must ensure that no ThreadX service calls are made 
+from default FIQ ISRs, which is located in tx_initialize_low_level.s.
+
+
+7.3.1  Managed FIQ Interrupts
+
+Full ThreadX management of FIQ interrupts is provided if the ThreadX sources
+are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built
+this way, the FIQ interrupt handlers are very similar to the IRQ interrupt
+handlers defined previously. The following is default FIQ handler 
+defined in tx_initialize_low_level.s:
+
+
+    .global __tx_fiq_handler
+    .type   __tx_fiq_handler, %function
+    .global __tx_fiq_processing_return
+    .type   __tx_fiq_processing_return, %function
+__tx_fiq_handler:
+
+    /* Jump to fiq context save to save system context.  */
+    B       _tx_thread_fiq_context_save
+__tx_fiq_processing_return:
+
+    /* At this point execution is still in the FIQ mode. The CPSR, point of
+       interrupt, and all C scratch registers are available for use.  */
+
+    /* Application FIQ handlers can be called here!  */
+
+    /* Jump to fiq context restore to restore system context.  */
+    B       _tx_thread_fiq_context_restore
+
+
+7.3.1.1 Nested FIQ Support
+
+By default, nested FIQ interrupt support is not enabled. To enable nested
+FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING
+defined. With this defined, two new FIQ interrupt management services are
+available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end.
+These function should be called between the FIQ context save and restore
+calls. 
+
+Execution between the calls to _tx_thread_fiq_nesting_start and 
+_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved 
+by switching from FIQ mode to SYS mode and enabling FIQ interrupts.
+The SYS mode stack is used during the SYS mode operation, which was 
+setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required,
+calling the _tx_thread_fiq_nesting_end service disables nesting by disabling
+FIQ interrupts and switching back to FIQ mode in preparation for the FIQ 
+context restore service.
+
+The following is an example of enabling FIQ nested interrupts in the 
+typical FIQ handler:
+
+
+    .global __tx_fiq_handler
+    .type   __tx_fiq_handler, %function
+    .global __tx_fiq_processing_return
+    .type   __tx_fiq_processing_return, %function
+__tx_fiq_handler:
+
+    /* Jump to fiq context save to save system context.  */
+    B       _tx_thread_fiq_context_save
+__tx_fiq_processing_return:
+
+    /* At this point execution is still in the FIQ mode. The CPSR, point of
+       interrupt, and all C scratch registers are available for use.  */
+
+    /* Enable nested FIQ interrupts. NOTE:  Since this service returns
+       with FIQ interrupts enabled, all FIQ interrupt sources must be 
+       cleared prior to calling this service.  */
+    BL      _tx_thread_fiq_nesting_start
+
+    /* Application FIQ handlers can be called here!  */
+
+    /* Disable nested FIQ interrupts. The mode is switched back to
+       FIQ mode and FIQ interrupts are disable upon return.  */
+    BL      _tx_thread_fiq_nesting_end
+
+    /* Jump to fiq context restore to restore system context.  */
+    B       _tx_thread_fiq_context_restore
+
+
+8.  ThreadX Timer Interrupt
+
+ThreadX requires a periodic interrupt source to manage all time-slicing, 
+thread sleeps, timeouts, and application timers. Without such a timer 
+interrupt source, these services are not functional. However, all other
+ThreadX services are operational without a periodic timer source.
+
+To add the timer interrupt processing, simply make a call to 
+_tx_timer_interrupt in the IRQ processing. An example of this can be
+found in the file tx_initialize_low_level.s in the Integrator sub-directories.
+
+
+9.  Thumb/Cortex-R4 Mixed Mode
+
+By default, ThreadX is setup for running in Cortex-R4 32-bit mode. This is 
+also true for the demonstration system. It is possible to build any 
+ThreadX file and/or the application in Thumb mode. To build ThreadX 
+assembly files in Thumb mode, define TX_THUMB_MODE. 
+
+
+10. VFP Support
+
+By default, VFP support is disabled for each thread. If saving the context of the VFP registers
+is needed, the following API call must be made from the context of the application thread - before 
+the VFP usage:
+
+void    tx_thread_vfp_enable(void);
+
+After this API is called in the application, VFP registers will be saved/restored for this thread if it
+is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers
+to be saved/restored.
+
+To disable VFP register context saving, simply call the following API:
+
+void    tx_thread_vfp_disable(void);
+
+Note that if VFP registers are used in ISRs, the save/restore of VFP registers must be done by the ISR.
+In addition, the startup code is responsible for enabling VFP usage.
+
+
+11.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX 6.0.1 version for Cortex-R4 using ARM tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_r4/ac6/src/tx_initialize_low_level.S b/ports/cortex_r4/ac6/src/tx_initialize_low_level.S
new file mode 100644
index 00000000..e1995158
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_initialize_low_level.S
@@ -0,0 +1,326 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Initialize                                                          */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/*
+#include "tx_api.h"
+#include "tx_initialize.h"
+#include "tx_thread.h"
+#include "tx_timer.h"
+*/
+
+
+#define GICI_BASE       0xAE000000
+#define ICCIAR_OFFSET   0x0000000C
+#define ICCEOIR_OFFSET  0x00000010
+
+
+    .global      _tx_thread_system_stack_ptr
+    .global      _tx_initialize_unused_memory
+    .global      _tx_thread_context_save
+    .global      _tx_thread_context_restore
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    .global      _tx_thread_fiq_context_save
+    .global      _tx_thread_fiq_context_restore
+#endif
+#ifdef TX_ENABLE_IRQ_NESTING
+    .global      _tx_thread_irq_nesting_start
+    .global      _tx_thread_irq_nesting_end
+#endif
+#ifdef TX_ENABLE_FIQ_NESTING
+    .global      _tx_thread_fiq_nesting_start
+    .global      _tx_thread_fiq_nesting_end
+#endif
+    .global      _tx_timer_interrupt
+    .global      __main
+    .global      _tx_version_id
+    .global      _tx_build_options
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_initialize_low_level                          Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for any low-level processor            */
+/*    initialization, including setting up interrupt vectors, setting     */
+/*    up a periodic timer interrupt source, saving the system stack       */
+/*    pointer for use in ISR processing later, and finding the first      */
+/*    available RAM memory address for tx_application_define.             */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_kernel_enter           ThreadX entry function        */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_initialize_low_level(VOID)
+{ */
+    .global _tx_initialize_low_level
+    .type   _tx_initialize_low_level, "function"
+_tx_initialize_low_level:
+
+     /* Save the system stack pointer.  */
+     /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */
+
+    LDR     r0, =Image$$SVC_STACK$$ZI$$Limit
+    LDR     r1, =_tx_thread_system_stack_ptr    // Pickup address of system stack ptr
+    STR     r0, [r1]                            // Pickup system stack
+
+     /* Save the first available memory address.  */
+     /* _tx_initialize_unused_memory =  (VOID_PTR) Image$$ZI$$Limit   + HEAP + [SYS_STACK] + FIQ_STACK + IRQ_STACK; */
+
+    LDR     r0, =Image$$DATA$$ZI$$Limit
+    LDR     r2, =_tx_initialize_unused_memory   // Pickup unused memory ptr address
+    STR     r0, [r2, #0]                        // Save first free memory address
+
+    /* Return to caller.  */
+    BX      lr                                  // Return to caller
+/* } */
+
+    /* Define shells for each of the interrupt vectors.  */
+
+    .global __tx_undefined
+    .type   __tx_undefined, "function"
+__tx_undefined:
+    B       __tx_undefined                      // Undefined handler
+
+    .global __tx_swi_interrupt
+    .type   __tx_swi_interrupt, "function"
+__tx_swi_interrupt:
+    B       __tx_swi_interrupt                  // Software interrupt handler
+
+    .global __tx_prefetch_handler
+    .type   __tx_prefetch_handler, "function"
+__tx_prefetch_handler:
+    B       __tx_prefetch_handler               // Prefetch exception handler
+
+    .global __tx_abort_handler
+    .type   __tx_abort_handler, "function"
+__tx_abort_handler:
+    B       __tx_abort_handler                  // Abort exception handler
+
+    .global __tx_reserved_handler
+    .type   __tx_reserved_handler, "function"
+__tx_reserved_handler:
+    B       __tx_reserved_handler               // Reserved exception handler
+
+
+    .global __tx_irq_handler
+    .type   __tx_irq_handler, "function"
+    .global __tx_irq_processing_return
+    .type   __tx_irq_processing_return, "function"
+__tx_irq_handler:
+
+    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return:
+
+    /* Acknowledge the interrupt.  */
+    LDR     r1, =GICI_BASE                      // Load the base of the GIC
+    LDR     r0, [r1, #ICCIAR_OFFSET]            // Read ICCIAR (GIC CPU Interface register)
+    DSB                                         // Ensure that interrupt acknowledge completes before re-enabling interrupts
+    PUSH    {r0, r1}                            // Save the IRQ ID and the GIC base address on the stack
+
+    /* Clear the timer interrupt.  */
+    LDR     r0, =0xB0110000                     // Load the base address of the timer
+    MOV     r1, #1                              // Setup value to write to the interrupt clear register - can be anything.
+    STR     r1, [r0, #0x0C]                     // Clear the interrupt. 0x0C is the offset to the interrupt clear register.
+
+    /* At this point execution is still in the IRQ mode.  The CPSR, point of
+       interrupt, and all C scratch registers are available for use.  In
+       addition, IRQ interrupts may be re-enabled - with certain restrictions -
+       if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
+       small code sequences where lr is saved before enabling interrupts and
+       restored after interrupts are again disabled.  */
+
+
+    BL      _tx_timer_interrupt                 // Timer interrupt handler
+_tx_not_timer_interrupt:
+
+    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start
+       from IRQ mode with interrupts disabled.  This routine switches to the
+       system mode and returns with IRQ interrupts enabled. */
+
+       /* NOTE:  It is very important to ensure all IRQ interrupts are cleared
+          prior to enabling nested IRQ interrupts.  */
+#ifdef TX_ENABLE_IRQ_NESTING
+    BL      _tx_thread_irq_nesting_start
+#endif
+
+
+    /* Application IRQ handlers can be called here!  */
+
+    /* If interrupt nesting was started earlier, the end of interrupt nesting
+       service must be called before returning to _tx_thread_context_restore.
+       This routine returns in processing in IRQ mode with interrupts disabled.  */
+#ifdef TX_ENABLE_IRQ_NESTING
+    BL      _tx_thread_irq_nesting_end
+#endif
+
+    POP     {r0, r1}                            // Restore the IRQ ID and GIC base address
+    STR     r0, [r1, #ICCEOIR_OFFSET]           // Write the IRQ ID to the End Of Interrupt register to clear the active bit
+
+    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+    /* This is an example of a vectored IRQ handler.  */
+
+    .global __tx_example_vectored_irq_handler
+    .type   __tx_example_vectored_irq_handler, "function"
+__tx_example_vectored_irq_handler:
+
+
+    /* Save initial context and call context save to prepare for
+       vectored ISR execution. */
+
+/*
+    STMDB   sp!, {r0-r3}                        // Save some scratch registers
+    MRS     r0, SPSR                            // Pickup saved SPSR
+    SUB     lr, lr, #4                          // Adjust point of interrupt
+    STMDB   sp!, {r0, r10, r12, lr}             // Store other scratch registers
+    BL      _tx_thread_vectored_context_save    // Vectored context save
+*/
+
+    /* At this point execution is still in the IRQ mode.  The CPSR, point of
+       interrupt, and all C scratch registers are available for use.  In
+       addition, IRQ interrupts may be re-enabled - with certain restrictions -
+       if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
+       small code sequences where lr is saved before enabling interrupts and
+       restored after interrupts are again disabled.  */
+
+
+    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start
+       from IRQ mode with interrupts disabled.  This routine switches to the
+       system mode and returns with IRQ interrupts enabled. */
+
+       /* NOTE:  It is very important to ensure all IRQ interrupts are cleared
+          prior to enabling nested IRQ interrupts.  */
+/*
+#ifdef TX_ENABLE_IRQ_NESTING
+    BL      _tx_thread_irq_nesting_start
+#endif
+*/
+
+    /* Application IRQ handlers can be called here!  */
+
+    /* If interrupt nesting was started earlier, the end of interrupt nesting
+       service must be called before returning to _tx_thread_context_restore.
+       This routine returns in processing in IRQ mode with interrupts disabled.  */
+/*
+#ifdef TX_ENABLE_IRQ_NESTING
+    BL      _tx_thread_irq_nesting_end
+#endif
+*/
+
+    /* Jump to context restore to restore system context.  */
+/*
+    B       _tx_thread_context_restore
+*/
+
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    .global __tx_fiq_handler
+    .type   __tx_fiq_handler, "function"
+__tx_fiq_handler:
+
+    /* Jump to fiq context save to save system context.  */
+    B       _tx_thread_fiq_context_save
+
+    .global __tx_fiq_processing_return
+    .type   __tx_fiq_processing_return, "function"
+__tx_fiq_processing_return:
+
+    /* At this point execution is still in the FIQ mode.  The CPSR, point of
+       interrupt, and all C scratch registers are available for use.  */
+
+    /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start
+       from FIQ mode with interrupts disabled.  This routine switches to the
+       system mode and returns with FIQ interrupts enabled. */
+
+       /* NOTE:  It is very important to ensure all FIQ interrupts are cleared
+          prior to enabling nested FIQ interrupts.  */
+#ifdef TX_ENABLE_FIQ_NESTING
+    BL      _tx_thread_fiq_nesting_start
+#endif
+
+    /* Application FIQ handlers can be called here!  */
+
+    /* If interrupt nesting was started earlier, the end of interrupt nesting
+       service must be called before returning to _tx_thread_fiq_context_restore.  */
+#ifdef TX_ENABLE_FIQ_NESTING
+    BL      _tx_thread_fiq_nesting_end
+#endif
+
+    /* Jump to fiq context restore to restore system context.  */
+    B       _tx_thread_fiq_context_restore
+
+
+#else
+    .global __tx_fiq_handler
+    .type   __tx_fiq_handler, "function"
+__tx_fiq_handler:
+    B       __tx_fiq_handler                    // FIQ interrupt handler
+#endif
+
+    /* Reference build options and version ID to ensure they come in.  */
+
+    LDR     r2, =_tx_build_options              // Pickup build options variable address
+    LDR     r0, [r2, #0]                        // Pickup build options content
+    LDR     r2, =_tx_version_id                 // Pickup version ID variable address
+    LDR     r0, [r2, #0]                        // Pickup version ID content
diff --git a/ports/cortex_r4/ac6/src/tx_thread_context_restore.S b/ports/cortex_r4/ac6/src/tx_thread_context_restore.S
new file mode 100644
index 00000000..eefbe092
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_context_restore.S
@@ -0,0 +1,252 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/*
+#include "tx_api.h"
+#include "tx_thread.h"
+#include "tx_timer.h"
+*/
+
+
+#define IRQ_MODE        0x12            // IRQ mode
+#define SVC_MODE        0x13            // SVC mode
+
+
+    .global      _tx_thread_system_state
+    .global      _tx_thread_current_ptr
+    .global      _tx_thread_execute_ptr
+    .global      _tx_timer_time_slice
+    .global      _tx_thread_schedule
+    .global      _tx_thread_preempt_disable
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    .global      _tx_execution_isr_exit
+#endif
+
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+   .text
+   .eabi_attribute Tag_ABI_align_preserved, 1
+       
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_context_restore                        Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function restores the interrupt context if it is processing a  */
+/*    nested interrupt.  If not, it returns to the interrupt thread if no */
+/*    preemption is necessary.  Otherwise, if preemption is necessary or  */
+/*    if no thread was running, the function returns to the scheduler.    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling routine     */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                  Interrupt Service Routines    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_thread_context_restore(VOID)
+{ */
+    .global _tx_thread_context_restore
+    .type   _tx_thread_context_restore, "function"
+_tx_thread_context_restore:
+
+     /* Lockout interrupts.  */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  // Disable IRQ and FIQ interrupts
+#else
+    CPSID   i                                   // Disable IRQ interrupts
+#endif
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+     /* Call the ISR exit function to indicate an ISR is complete.  */
+
+    BL      _tx_execution_isr_exit              // Call the ISR exit function
+#endif
+
+    /* Determine if interrupts are nested.  */
+    /* if (--_tx_thread_system_state)
+    { */
+
+    LDR     r3, =_tx_thread_system_state        // Pickup address of system state var
+    LDR     r2, [r3, #0]                        // Pickup system state
+    SUB     r2, r2, #1                          // Decrement the counter
+    STR     r2, [r3, #0]                        // Store the counter
+    CMP     r2, #0                              // Was this the first interrupt?
+    BEQ     __tx_thread_not_nested_restore      // If so, not a nested restore
+
+    /* Interrupts are nested.  */
+
+    /* Just recover the saved registers and return to the point of
+       interrupt.  */
+
+    LDMIA   sp!, {r0, r10, r12, lr}             // Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       // Put SPSR back
+    LDMIA   sp!, {r0-r3}                        // Recover r0-r3
+    SUBS    pc, lr, #0                          // Return to point of interrupt
+
+     /* } */
+__tx_thread_not_nested_restore:
+
+    /* Determine if a thread was interrupted and no preemption is required.  */
+    /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
+                (_tx_thread_preempt_disable))
+    { */
+
+    LDR     r1, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        // Pickup actual current thread pointer
+    CMP     r0, #0                              // Is it NULL?
+    BEQ     __tx_thread_idle_system_restore     // Yes, idle system was interrupted
+
+    LDR     r3, =_tx_thread_preempt_disable     // Pickup preempt disable address
+    LDR     r2, [r3, #0]                        // Pickup actual preempt disable flag
+    CMP     r2, #0                              // Is it set?
+    BNE     __tx_thread_no_preempt_restore      // Yes, don't preempt this thread
+    LDR     r3, =_tx_thread_execute_ptr         // Pickup address of execute thread ptr
+    LDR     r2, [r3, #0]                        // Pickup actual execute thread pointer
+    CMP     r0, r2                              // Is the same thread highest priority?
+    BNE     __tx_thread_preempt_restore         // No, preemption needs to happen
+
+
+__tx_thread_no_preempt_restore:
+
+    /* Restore interrupted thread or ISR.  */
+
+    /* Pickup the saved stack pointer.  */
+    /* tmp_ptr =  _tx_thread_current_ptr -> tx_thread_stack_ptr; */
+
+    /* Recover the saved context and return to the point of interrupt.  */
+
+    LDMIA   sp!, {r0, r10, r12, lr}             // Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       // Put SPSR back
+    LDMIA   sp!, {r0-r3}                        // Recover r0-r3
+    SUBS    pc, lr, #0                          // Return to point of interrupt
+
+    /* }
+    else
+    { */
+__tx_thread_preempt_restore:
+
+    LDMIA   sp!, {r3, r10, r12, lr}             // Recover temporarily saved registers
+    MOV     r1, lr                              // Save lr (point of interrupt)
+    
+    CPS     #SVC_MODE                           // Switch to SVC mode to save context on thread stack
+    STR     r1, [sp, #-4]!                      // Save point of interrupt
+    STMDB   sp!, {r4-r12, lr}                   // Save upper half of registers
+    MOV     r4, r3                              // Save SPSR in r4
+    
+    CPS     #IRQ_MODE                           // Switch back to IRQ mode
+    LDMIA   sp!, {r0-r3}                        // Recover r0-r3
+    
+    CPS     #SVC_MODE                           // Switch to SVC mode to save remaining context on thread stack
+    STMDB   sp!, {r0-r3}                        // Save r0-r3 on thread's stack
+
+    LDR     r1, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        // Pickup current thread pointer
+
+#ifdef __ARM_FP
+    LDR     r2, [r0, #144]                      // Pickup the VFP enabled flag
+    CMP     r2, #0                              // Is the VFP enabled?
+    BEQ     _tx_skip_irq_vfp_save               // No, skip VFP IRQ save
+    VMRS    r2, FPSCR                           // Pickup the FPSCR
+    STR     r2, [sp, #-4]!                      // Save FPSCR
+    VSTMDB  sp!, {D0-D15}                       // Save D0-D15
+_tx_skip_irq_vfp_save:
+#endif
+
+    MOV     r3, #1                              // Build interrupt stack type
+    STMDB   sp!, {r3, r4}                       // Save interrupt stack type and SPSR
+    STR     sp, [r0, #8]                        // Save stack pointer in thread control
+                                                //   block
+
+    /* Save the remaining time-slice and disable it.  */
+    /* if (_tx_timer_time_slice)
+    { */
+
+    LDR     r3, =_tx_timer_time_slice           // Pickup time-slice variable address
+    LDR     r2, [r3, #0]                        // Pickup time-slice
+    CMP     r2, #0                              // Is it active?
+    BEQ     __tx_thread_dont_save_ts            // No, don't save it
+
+        /* _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice; */
+        /* _tx_timer_time_slice =  0; */
+
+    STR     r2, [r0, #24]                       // Save thread's time-slice
+    MOV     r2, #0                              // Clear value
+    STR     r2, [r3, #0]                        // Disable global time-slice flag
+
+    /* } */
+__tx_thread_dont_save_ts:
+
+
+    /* Clear the current task pointer.  */
+    /* _tx_thread_current_ptr =  TX_NULL; */
+
+    MOV     r0, #0                              // NULL value
+    STR     r0, [r1, #0]                        // Clear current thread pointer
+
+    /* Return to the scheduler.  */
+    /* _tx_thread_schedule(); */
+
+    B       _tx_thread_schedule                 // Return to scheduler
+    /* } */
+
+__tx_thread_idle_system_restore:
+
+    /* Just return back to the scheduler!  */
+    CPS     #SVC_MODE                           // Switch to SVC mode
+    B       _tx_thread_schedule                 // Return to scheduler
+/* } */
diff --git a/ports/cortex_r4/ac6/src/tx_thread_context_save.S b/ports/cortex_r4/ac6/src/tx_thread_context_save.S
new file mode 100644
index 00000000..9f5e23db
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_context_save.S
@@ -0,0 +1,202 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_thread.h" */
+
+
+    .global      _tx_thread_system_state
+    .global      _tx_thread_current_ptr
+    .global      __tx_irq_processing_return
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    .global      _tx_execution_isr_enter
+#endif
+
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_context_save                           Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function saves the context of an executing thread in the       */
+/*    beginning of interrupt processing.  The function also ensures that  */
+/*    the system stack is used upon return to the calling ISR.            */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                                                */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_thread_context_save(VOID)
+{ */
+    .global _tx_thread_context_save
+    .type   _tx_thread_context_save, "function"
+_tx_thread_context_save:
+
+    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+       out, we are in IRQ mode, and all registers are intact.  */
+
+    /* Check for a nested interrupt condition.  */
+    /* if (_tx_thread_system_state++)
+    { */
+
+    STMDB   sp!, {r0-r3}                        // Save some working registers
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  // Disable FIQ interrupts
+#endif
+    LDR     r3, =_tx_thread_system_state        // Pickup address of system state var
+    LDR     r2, [r3, #0]                        // Pickup system state
+    CMP     r2, #0                              // Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         // Yes, not a nested context save
+
+    /* Nested interrupt condition.  */
+
+    ADD     r2, r2, #1                          // Increment the interrupt counter
+    STR     r2, [r3, #0]                        // Store it back in the variable
+
+    /* Save the rest of the scratch registers on the stack and return to the
+       calling ISR.  */
+
+    MRS     r0, SPSR                            // Pickup saved SPSR
+    SUB     lr, lr, #4                          // Adjust point of interrupt
+    STMDB   sp!, {r0, r10, r12, lr}             // Store other registers
+
+    /* Return to the ISR.  */
+
+    MOV     r10, #0                             // Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    PUSH    {lr}                                // Save ISR lr
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    POP     {lr}                                // Recover ISR lr
+#endif
+
+    B       __tx_irq_processing_return          // Continue IRQ processing
+
+__tx_thread_not_nested_save:
+    /* } */
+
+    /* Otherwise, not nested, check to see if a thread was running.  */
+    /* else if (_tx_thread_current_ptr)
+    { */
+
+    ADD     r2, r2, #1                          // Increment the interrupt counter
+    STR     r2, [r3, #0]                        // Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        // Pickup current thread pointer
+    CMP     r0, #0                              // Is it NULL?
+    BEQ     __tx_thread_idle_system_save        // If so, interrupt occurred in
+                                                //   scheduling loop - nothing needs saving!
+
+    /* Save minimal context of interrupted thread.  */
+
+    MRS     r2, SPSR                            // Pickup saved SPSR
+    SUB     lr, lr, #4                          // Adjust point of interrupt
+    STMDB   sp!, {r2, r10, r12, lr}             // Store other registers
+
+    /* Save the current stack pointer in the thread's control block.  */
+    /* _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp; */
+
+    /* Switch to the system stack.  */
+    /* sp =  _tx_thread_system_stack_ptr; */
+
+    MOV     r10, #0                             // Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    PUSH    {lr}                                // Save ISR lr
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    POP     {lr}                                // Recover ISR lr
+#endif
+
+    B       __tx_irq_processing_return          // Continue IRQ processing
+
+    /* }
+    else
+    { */
+
+__tx_thread_idle_system_save:
+
+    /* Interrupt occurred in the scheduling loop.  */
+
+    /* Not much to do here, just adjust the stack pointer, and return to IRQ
+       processing.  */
+
+    MOV     r10, #0                             // Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    PUSH    {lr}                                // Save ISR lr
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    POP     {lr}                                // Recover ISR lr
+#endif
+
+    ADD     sp, sp, #16                         // Recover saved registers
+    B       __tx_irq_processing_return          // Continue IRQ processing
+
+    /* } */
+/* } */
diff --git a/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S
new file mode 100644
index 00000000..8d26087f
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_fiq_context_restore.S
@@ -0,0 +1,260 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_thread.h" */
+/* #include "tx_timer.h" */
+
+
+#define FIQ_MODE        0x11            // FIQ mode
+#define SVC_MODE        0x13            // SVC mode
+#define MODE_MASK       0x1F            // Mode mask
+#define IRQ_MODE_BITS   0x12            // IRQ mode bits
+
+
+    .global      _tx_thread_system_state
+    .global      _tx_thread_current_ptr
+    .global      _tx_thread_system_stack_ptr
+    .global      _tx_thread_execute_ptr
+    .global      _tx_timer_time_slice
+    .global      _tx_thread_schedule
+    .global      _tx_thread_preempt_disable
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    .global      _tx_execution_isr_exit
+#endif
+
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_fiq_context_restore                    Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function restores the fiq interrupt context when processing a  */
+/*    nested interrupt.  If not, it returns to the interrupt thread if no */
+/*    preemption is necessary.  Otherwise, if preemption is necessary or  */
+/*    if no thread was running, the function returns to the scheduler.    */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling routine     */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    FIQ ISR                               Interrupt Service Routines    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_thread_fiq_context_restore(VOID) */
+/* { */
+    .global _tx_thread_fiq_context_restore
+    .type   _tx_thread_fiq_context_restore, "function"
+_tx_thread_fiq_context_restore:
+
+    /* Lockout interrupts.  */
+
+    CPSID   if                                  // Disable IRQ and FIQ interrupts
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR exit function to indicate an ISR is complete.  */
+
+    BL      _tx_execution_isr_exit              // Call the ISR exit function
+#endif
+
+    /* Determine if interrupts are nested.  */
+    /* if (--_tx_thread_system_state) */
+    /* { */
+
+    LDR     r3, =_tx_thread_system_state        // Pickup address of system state var
+    LDR     r2, [r3]                            // Pickup system state
+    SUB     r2, r2, #1                          // Decrement the counter
+    STR     r2, [r3]                            // Store the counter
+    CMP     r2, #0                              // Was this the first interrupt?
+    BEQ     __tx_thread_fiq_not_nested_restore  // If so, not a nested restore
+
+    /* Interrupts are nested.  */
+
+    /* Just recover the saved registers and return to the point of
+       interrupt.  */
+
+    LDMIA   sp!, {r0, r10, r12, lr}             // Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       // Put SPSR back
+    LDMIA   sp!, {r0-r3}                        // Recover r0-r3
+    SUBS    pc, lr, #0                          // Return to point of interrupt
+
+
+    /* } */
+__tx_thread_fiq_not_nested_restore:
+
+    /* Determine if a thread was interrupted and no preemption is required.  */
+    /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) */
+               /*    (_tx_thread_preempt_disable)) */
+    /* { */
+
+    LDR     r1, [sp]                            // Pickup the saved SPSR
+    MOV     r2, #MODE_MASK                      // Build mask to isolate the interrupted mode
+    AND     r1, r1, r2                          // Isolate mode bits
+    CMP     r1, #IRQ_MODE_BITS                  // Was an interrupt taken in IRQ mode before we
+                                                //   got to context save? */
+    BEQ     __tx_thread_fiq_no_preempt_restore  // Yes, just go back to point of interrupt
+
+
+    LDR     r1, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     r0, [r1]                            // Pickup actual current thread pointer
+    CMP     r0, #0                              // Is it NULL?
+    BEQ     __tx_thread_fiq_idle_system_restore // Yes, idle system was interrupted
+
+    LDR     r3, =_tx_thread_preempt_disable     // Pickup preempt disable address
+    LDR     r2, [r3]                            // Pickup actual preempt disable flag
+    CMP     r2, #0                              // Is it set?
+    BNE     __tx_thread_fiq_no_preempt_restore  // Yes, don't preempt this thread
+    LDR     r3, =_tx_thread_execute_ptr         // Pickup address of execute thread ptr
+    LDR     r2, [r3]                            // Pickup actual execute thread pointer
+    CMP     r0, r2                              // Is the same thread highest priority?
+    BNE     __tx_thread_fiq_preempt_restore     // No, preemption needs to happen
+
+
+__tx_thread_fiq_no_preempt_restore:
+
+    /* Restore interrupted thread or ISR.  */
+
+    /* Pickup the saved stack pointer.  */
+    /* tmp_ptr =  _tx_thread_current_ptr -> tx_thread_stack_ptr; */
+
+    /* Recover the saved context and return to the point of interrupt.  */
+
+    LDMIA   sp!, {r0, lr}                       // Recover SPSR and POI
+    MSR     SPSR_cxsf, r0                       // Put SPSR back
+    LDMIA   sp!, {r0-r3}                        // Recover r0-r3
+    SUBS    pc, lr, #0                          // Return to point of interrupt
+
+    /* } */
+    /* else */
+    /* { */
+__tx_thread_fiq_preempt_restore:
+
+    LDMIA   sp!, {r3, lr}                       // Recover temporarily saved registers
+    MOV     r1, lr                              // Save lr (point of interrupt)
+    
+    CPS     #SVC_MODE                           // Switch to SVC mode to save context on thread stack
+    STR     r1, [sp, #-4]!                      // Save point of interrupt
+    STMDB   sp!, {r4-r12, lr}                   // Save upper half of registers
+    MOV     r4, r3                              // Save SPSR in r4
+    
+    CPS     #FIQ_MODE                           // Switch back to FIQ mode
+    LDMIA   sp!, {r0-r3}                        // Recover r0-r3
+    
+    CPS     #SVC_MODE                           // Switch to SVC mode to save remaining context on thread stack
+    STMDB   sp!, {r0-r3}                        // Save r0-r3 on thread's stack
+
+    LDR     r1, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     r0, [r1]                            // Pickup current thread pointer
+
+#ifdef __ARM_FP
+    LDR     r2, [r0, #144]                      // Pickup the VFP enabled flag
+    CMP     r2, #0                              // Is the VFP enabled?
+    BEQ     _tx_skip_fiq_vfp_save               // No, skip VFP FIQ save
+    VMRS    r2, FPSCR                           // Pickup the FPSCR
+    STR     r2, [sp, #-4]!                      // Save FPSCR
+    VSTMDB  sp!, {D0-D15}                       // Save D0-D15
+_tx_skip_fiq_vfp_save:
+#endif
+
+    MOV     r3, #1                              // Build interrupt stack type
+    STMDB   sp!, {r3, r4}                       // Save interrupt stack type and SPSR
+    STR     sp, [r0, #8]                        // Save stack pointer in thread control
+                                                //   block
+
+    /* Save the remaining time-slice and disable it.  */
+    /* if (_tx_timer_time_slice) */
+    /* { */
+
+    LDR     r3, =_tx_timer_time_slice           // Pickup time-slice variable address
+    LDR     r2, [r3]                            // Pickup time-slice
+    CMP     r2, #0                              // Is it active?
+    BEQ     __tx_thread_fiq_dont_save_ts        // No, don't save it
+
+        /* _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice; */
+        /* _tx_timer_time_slice =  0; */
+
+    STR     r2, [r0, #24]                       // Save thread's time-slice
+    MOV     r2, #0                              // Clear value
+    STR     r2, [r3]                            // Disable global time-slice flag
+
+    /* } */
+__tx_thread_fiq_dont_save_ts:
+
+
+    /* Clear the current task pointer.  */
+    /* _tx_thread_current_ptr =  TX_NULL; */
+
+    MOV     r0, #0                              // NULL value
+    STR     r0, [r1]                            // Clear current thread pointer
+
+    /* Return to the scheduler.  */
+    /* _tx_thread_schedule(); */
+
+    B       _tx_thread_schedule                 // Return to scheduler
+    /* } */
+
+__tx_thread_fiq_idle_system_restore:
+
+    /* Just return back to the scheduler!  */
+
+    ADD     sp, sp, #24                         // Recover FIQ stack space
+    CPS     #SVC_MODE                           // Switch to SVC mode
+    B       _tx_thread_schedule                 // Return to scheduler
+
+/* } */
diff --git a/ports/cortex_r4/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_r4/ac6/src/tx_thread_fiq_context_save.S
new file mode 100644
index 00000000..3221a358
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_fiq_context_save.S
@@ -0,0 +1,209 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_thread.h" */
+
+    .global      _tx_thread_system_state
+    .global      _tx_thread_current_ptr
+    .global      __tx_fiq_processing_return
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    .global      _tx_execution_isr_enter
+#endif
+
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_fiq_context_save                       Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function saves the context of an executing thread in the       */
+/*    beginning of interrupt processing.  The function also ensures that  */
+/*    the system stack is used upon return to the calling ISR.            */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                                                */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+ /* VOID   _tx_thread_fiq_context_save(VOID) */
+/* { */
+
+    .global _tx_thread_fiq_context_save
+    .type   _tx_thread_fiq_context_save, "function"
+_tx_thread_fiq_context_save:
+
+    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked 
+       out, we are in IRQ mode, and all registers are intact.  */
+
+    /* Check for a nested interrupt condition.  */
+    /* if (_tx_thread_system_state++) */
+    /* { */
+
+    STMDB   sp!, {r0-r3}                        // Save some working registers
+    LDR     r3, =_tx_thread_system_state        // Pickup address of system state var
+    LDR     r2, [r3]                            // Pickup system state
+    CMP     r2, #0                              // Is this the first interrupt?
+    BEQ     __tx_thread_fiq_not_nested_save     // Yes, not a nested context save
+
+    /* Nested interrupt condition.  */
+
+    ADD     r2, r2, #1                          // Increment the interrupt counter
+    STR     r2, [r3]                            // Store it back in the variable
+
+    /* Save the rest of the scratch registers on the stack and return to the
+       calling ISR.  */
+
+    MRS     r0, SPSR                            // Pickup saved SPSR
+    SUB     lr, lr, #4                          // Adjust point of interrupt
+    STMDB   sp!, {r0, r10, r12, lr}             // Store other registers
+
+    /* Return to the ISR.  */
+
+    MOV     r10, #0                             // Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    PUSH    {lr}                                // Save ISR lr
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    POP     {lr}                                // Recover ISR lr
+#endif
+
+    B       __tx_fiq_processing_return          // Continue FIQ processing
+
+__tx_thread_fiq_not_nested_save:
+    /* } */
+
+    /* Otherwise, not nested, check to see if a thread was running.  */
+    /* else if (_tx_thread_current_ptr) */
+    /* { */
+
+    ADD     r2, r2, #1                          // Increment the interrupt counter
+    STR     r2, [r3]                            // Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     r0, [r1]                            // Pickup current thread pointer
+    CMP     r0, #0                              // Is it NULL?
+    BEQ     __tx_thread_fiq_idle_system_save    // If so, interrupt occurred in
+                                                //   scheduling loop - nothing needs saving!
+
+    /* Save minimal context of interrupted thread.  */
+
+    MRS     r2, SPSR                            // Pickup saved SPSR
+    SUB     lr, lr, #4                          // Adjust point of interrupt
+    STMDB   sp!, {r2, lr}                       // Store other registers, Note that we don't
+                                                //   need to save sl and ip since FIQ has
+                                                //   copies of these registers.  Nested
+                                                //   interrupt processing does need to save
+                                                //   these registers.
+
+    /* Save the current stack pointer in the thread's control block.  */
+    /* _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp; */
+
+    /* Switch to the system stack.  */
+    /* sp =  _tx_thread_system_stack_ptr; */
+
+    MOV     r10, #0                             // Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    PUSH    {lr}                                // Save ISR lr
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    POP     {lr}                                // Recover ISR lr
+#endif
+
+    B       __tx_fiq_processing_return          // Continue FIQ processing
+
+   /* } */
+   /* else */
+   /* { */
+
+__tx_thread_fiq_idle_system_save:
+
+    /* Interrupt occurred in the scheduling loop.  */
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    PUSH    {lr}                                // Save ISR lr
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    POP     {lr}                                // Recover ISR lr
+#endif
+
+    /* Not much to do here, save the current SPSR and LR for possible
+       use in IRQ interrupted in idle system conditions, and return to
+       FIQ interrupt processing.  */
+
+    MRS     r0, SPSR                            // Pickup saved SPSR
+    SUB     lr, lr, #4                          // Adjust point of interrupt
+    STMDB   sp!, {r0, lr}                       // Store other registers that will get used
+                                                //   or stripped off the stack in context
+                                                //   restore
+    B       __tx_fiq_processing_return          // Continue FIQ processing
+
+    /* } */
+/* } */
+
+#endif
diff --git a/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_end.S
new file mode 100644
index 00000000..8568b961
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_end.S
@@ -0,0 +1,108 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_thread.h" */
+
+#define FIQ_MODE        0x11            // FIQ Mode bits
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_fiq_nesting_end                        Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is called by the application from FIQ mode after      */
+/*    _tx_thread_fiq_nesting_start has been called and switches the FIQ   */
+/*    processing from system mode back to FIQ mode prior to the ISR       */
+/*    calling _tx_thread_fiq_context_restore.  Note that this function    */
+/*    assumes the system stack pointer is in the same position after      */
+/*    nesting start function was called.                                  */
+/*                                                                        */
+/*    This function assumes that the system mode stack pointer was setup  */
+/*    during low-level initialization (tx_initialize_low_level.s).        */
+/*                                                                        */
+/*    This function returns with FIQ interrupts disabled.                 */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                                                */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_thread_fiq_nesting_end(VOID) */
+/* { */
+    .global _tx_thread_fiq_nesting_end
+    .type   _tx_thread_fiq_nesting_end, "function"
+_tx_thread_fiq_nesting_end:
+    MOV     r3, lr                              // Save ISR return address
+    
+    #ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  // Disable IRQ and FIQ interrupts
+    #else
+    CPSID   i                                   // Disable IRQ interrupts
+    #endif
+    
+    LDMIA   sp!, {r1, lr}                       // Pickup saved lr (and r1 throw-away for
+                                                //   8-byte alignment logic)
+    CPS     #FIQ_MODE                           // Switch back to FIQ mode
+    BX      r3                                  // Return to caller
+/* } */
+
+
+
diff --git a/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_start.S
new file mode 100644
index 00000000..60bd335f
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_fiq_nesting_start.S
@@ -0,0 +1,96 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_thread.h" */
+
+#define SYS_MODE        0x12            // System mode
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_fiq_nesting_start                      Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is called by the application from FIQ mode after      */
+/*    _tx_thread_fiq_context_save has been called and switches the FIQ    */
+/*    processing to the system mode so nested FIQ interrupt processing    */
+/*    is possible (system mode has its own "lr" register).  Note that     */
+/*    this function assumes that the system mode stack pointer was setup  */
+/*    during low-level initialization (tx_initialize_low_level.s).        */
+/*                                                                        */
+/*    This function returns with FIQ interrupts enabled.                  */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                                                */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_thread_fiq_nesting_start(VOID) */
+/* { */
+    .global _tx_thread_fiq_nesting_start
+    .type   _tx_thread_fiq_nesting_start, "function"
+_tx_thread_fiq_nesting_start:
+    MOV     r3, lr                              // Save ISR return address
+    CPS     #SYS_MODE                           // Switch to system mode
+    STMDB   sp!, {r1, lr}                       // Push the system mode lr on the system mode stack
+                                                //   and push r1 just to keep 8-byte alignment
+    CPSIE   f                                   // Enable FIQ interrupts
+    BX      r3                                  // Return to caller
+/* } */
diff --git a/ports/cortex_r4/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_r4/ac6/src/tx_thread_interrupt_control.S
new file mode 100644
index 00000000..aa0215ac
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_interrupt_control.S
@@ -0,0 +1,102 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_thread.h" */
+
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define INT_MASK 0xC0               // Interrupt bit mask
+#else
+#define INT_MASK 0x80               // Interrupt bit mask
+#endif
+
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_control                      Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for changing the interrupt lockout     */
+/*    posture of the system.                                              */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    new_posture                           New interrupt lockout posture */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* UINT   _tx_thread_interrupt_control(UINT new_posture) */
+/* { */
+    .global _tx_thread_interrupt_control
+    .type   _tx_thread_interrupt_control, "function"
+_tx_thread_interrupt_control:
+
+    /* Pickup current interrupt lockout posture.  */
+
+    MRS     r3, CPSR                            // Pickup current CPSR
+    BIC     r1, r3, #INT_MASK                   // Clear interrupt lockout bits
+    ORR     r1, r1, r0                          // Or-in new interrupt lockout bits
+
+    /* Apply the new interrupt posture.  */
+
+    MSR     CPSR_c, r1                          // Setup new CPSR
+    AND     r0, r3, #INT_MASK                   // Return previous interrupt mask
+    BX      lr                                  // Return to caller
+
+/* } */
diff --git a/ports/cortex_r4/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_r4/ac6/src/tx_thread_interrupt_disable.S
new file mode 100644
index 00000000..079cbfdc
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_interrupt_disable.S
@@ -0,0 +1,96 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_thread.h" */
+
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_disable                      Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for disabling interrupts               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* UINT   _tx_thread_interrupt_disable(void) */
+/* { */
+    .global _tx_thread_interrupt_disable
+    .type   _tx_thread_interrupt_disable, "function"
+_tx_thread_interrupt_disable:
+
+    /* Pickup current interrupt lockout posture.  */
+
+    MRS     r0, CPSR                            // Pickup current CPSR
+
+    /* Mask interrupts.  */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  // Disable IRQ and FIQ
+#else
+    CPSID   i                                   // Disable IRQ
+#endif
+
+    BX      lr                                  // Return to caller
+
+/* } */
diff --git a/ports/cortex_r4/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_r4/ac6/src/tx_thread_interrupt_restore.S
new file mode 100644
index 00000000..7c374cad
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_interrupt_restore.S
@@ -0,0 +1,90 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_thread.h" */
+
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_interrupt_restore                      Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is responsible for restoring interrupts to the state  */
+/*    returned by a previous _tx_thread_interrupt_disable call.           */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    old_posture                           Old interrupt lockout posture */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    Application Code                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* UINT   _tx_thread_interrupt_restore(UINT old_posture) */
+/* { */
+    .global _tx_thread_interrupt_restore
+    .type   _tx_thread_interrupt_restore, "function"
+_tx_thread_interrupt_restore:
+
+    /* Apply the new interrupt posture.  */
+
+    MSR     CPSR_c, r0                          // Setup new CPSR
+    BX      lr                                  // Return to caller
+/* } */
+
+
+
diff --git a/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_end.S
new file mode 100644
index 00000000..7f81779a
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_end.S
@@ -0,0 +1,105 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_thread.h" */
+
+#define IRQ_MODE        0x12            // IRQ Mode bits
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_irq_nesting_end                        Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is called by the application from IRQ mode after      */
+/*    _tx_thread_irq_nesting_start has been called and switches the IRQ   */
+/*    processing from system mode back to IRQ mode prior to the ISR       */
+/*    calling _tx_thread_context_restore.  Note that this function        */
+/*    assumes the system stack pointer is in the same position after      */
+/*    nesting start function was called.                                  */
+/*                                                                        */
+/*    This function assumes that the system mode stack pointer was setup  */
+/*    during low-level initialization (tx_initialize_low_level.s).        */
+/*                                                                        */
+/*    This function returns with IRQ interrupts disabled.                 */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                                                */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_thread_irq_nesting_end(VOID) */
+/* { */
+    .global _tx_thread_irq_nesting_end
+    .type   _tx_thread_irq_nesting_end, "function"
+_tx_thread_irq_nesting_end:
+    MOV     r3, lr                              // Save ISR return address
+
+    #ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  // Disable IRQ and FIQ interrupts
+    #else
+    CPSID   i                                   // Disable IRQ interrupts
+    #endif
+    
+    LDMIA   sp!, {r1, lr}                       // Pickup saved lr (and r1 throw-away for
+                                                //   8-byte alignment logic)
+    CPS     #IRQ_MODE                           // Switch back to IRQ mode
+    BX      r3                                  // Return to caller
+/* } */
diff --git a/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_start.S
new file mode 100644
index 00000000..c8cd19a5
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_irq_nesting_start.S
@@ -0,0 +1,96 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_thread.h" */
+
+#define SYS_MODE        0x1F            // System mode bits
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_irq_nesting_start                      Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is called by the application from IRQ mode after      */
+/*    _tx_thread_context_save has been called and switches the IRQ        */
+/*    processing to the system mode so nested IRQ interrupt processing    */
+/*    is possible (system mode has its own "lr" register).  Note that     */
+/*    this function assumes that the system mode stack pointer was setup  */
+/*    during low-level initialization (tx_initialize_low_level.s).        */
+/*                                                                        */
+/*    This function returns with IRQ interrupts enabled.                  */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                                                */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_thread_irq_nesting_start(VOID) */
+/* { */
+    .global _tx_thread_irq_nesting_start
+    .type   _tx_thread_irq_nesting_start, "function"
+_tx_thread_irq_nesting_start:
+    MOV     r3, lr                              // Save ISR return address
+    CPS     #SYS_MODE                           // Switch to System Mode
+    STMDB   sp!, {r1, lr}                       // Push the system mode lr on the system mode stack
+                                                //   and push r1 just to keep 8-byte alignment
+    CPSIE   i                                   // Enable IRQ interrupts
+    BX      r3                                  // Return to caller
+/* } */
diff --git a/ports/cortex_r4/ac6/src/tx_thread_schedule.S b/ports/cortex_r4/ac6/src/tx_thread_schedule.S
new file mode 100644
index 00000000..75d29128
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_schedule.S
@@ -0,0 +1,230 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_thread.h" */
+/* #include "tx_timer.h" */
+
+
+    .global     _tx_thread_execute_ptr
+    .global     _tx_thread_current_ptr
+    .global     _tx_timer_time_slice
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    .global     _tx_execution_thread_enter
+#endif
+
+    .arm
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_schedule                               Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function waits for a thread control block pointer to appear in */
+/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
+/*    in the variable, the corresponding thread is resumed.               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_kernel_enter          ThreadX entry function         */
+/*    _tx_thread_system_return             Return to system from thread   */
+/*    _tx_thread_context_restore           Restore thread's context       */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_thread_schedule(VOID) */
+/* { */
+    .global _tx_thread_schedule
+    .type   _tx_thread_schedule, "function"
+_tx_thread_schedule:
+
+    /* Enable interrupts.  */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSIE   if                                  // Enable IRQ and FIQ interrupts
+#else
+    CPSIE   i                                   // Enable IRQ interrupts
+#endif
+
+    /* Wait for a thread to execute.  */
+    /* do */
+    /* { */
+    LDR     r1, =_tx_thread_execute_ptr         // Address of thread execute ptr
+
+__tx_thread_schedule_loop:
+
+    LDR     r0, [r1, #0]                        // Pickup next thread to execute
+    CMP     r0, #0                              // Is it NULL?
+    BEQ     __tx_thread_schedule_loop           // If so, keep looking for a thread
+
+    /* } */
+    /* while(_tx_thread_execute_ptr == TX_NULL); */
+
+    /* Yes! We have a thread to execute.  Lockout interrupts and
+       transfer control to it.  */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  // Disable IRQ and FIQ interrupts
+#else
+    CPSID   i                                   // Disable IRQ interrupts
+#endif
+
+    /* Setup the current thread pointer.  */
+    /* _tx_thread_current_ptr =  _tx_thread_execute_ptr; */
+
+    LDR     r1, =_tx_thread_current_ptr         // Pickup address of current thread
+    STR     r0, [r1, #0]                        // Setup current thread pointer
+
+    /* Increment the run count for this thread.  */
+    /* _tx_thread_current_ptr -> tx_thread_run_count++; */
+
+    LDR     r2, [r0, #4]                        // Pickup run counter
+    LDR     r3, [r0, #24]                       // Pickup time-slice for this thread
+    ADD     r2, r2, #1                          // Increment thread run-counter
+    STR     r2, [r0, #4]                        // Store the new run counter
+
+    /* Setup time-slice, if present.  */
+    /* _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice; */
+
+    LDR     r2, =_tx_timer_time_slice           // Pickup address of time slice
+                                                //   variable
+    LDR     sp, [r0, #8]                        // Switch stack pointers
+    STR     r3, [r2, #0]                        // Setup time-slice
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the thread entry function to indicate the thread is executing.  */
+
+    MOV     r5, r0                              // Save r0
+    BL      _tx_execution_thread_enter          // Call the thread execution enter function
+    MOV     r0, r5                              // Restore r0
+#endif
+
+    /* Switch to the thread's stack.  */
+    /* sp =  _tx_thread_execute_ptr -> tx_thread_stack_ptr; */
+
+    /* Determine if an interrupt frame or a synchronous task suspension frame
+       is present.  */
+
+    LDMIA   sp!, {r4, r5}                       // Pickup the stack type and saved CPSR
+    CMP     r4, #0                              // Check for synchronous context switch
+    BEQ     _tx_solicited_return
+    MSR     SPSR_cxsf, r5                       // Setup SPSR for return
+#ifdef __ARM_FP
+    LDR     r1, [r0, #144]                      // Pickup the VFP enabled flag
+    CMP     r1, #0                              // Is the VFP enabled?
+    BEQ     _tx_skip_interrupt_vfp_restore      // No, skip VFP interrupt restore
+    VLDMIA  sp!, {D0-D15}                       // Recover D0-D15
+    LDR     r4, [sp], #4                        // Pickup FPSCR
+    VMSR    FPSCR, r4                           // Restore FPSCR
+_tx_skip_interrupt_vfp_restore:
+#endif
+    LDMIA   sp!, {r0-r12, lr, pc}^              // Return to point of thread interrupt
+
+_tx_solicited_return:
+
+#ifdef __ARM_FP
+    LDR     r1, [r0, #144]                      // Pickup the VFP enabled flag
+    CMP     r1, #0                              // Is the VFP enabled?
+    BEQ     _tx_skip_solicited_vfp_restore      // No, skip VFP solicited restore
+    VLDMIA  sp!, {D8-D15}                       // Recover D8-D15
+    LDR     r4, [sp], #4                        // Pickup FPSCR
+    VMSR    FPSCR, r4                           // Restore FPSCR
+_tx_skip_solicited_vfp_restore:
+#endif
+    MSR     CPSR_cxsf, r5                       // Recover CPSR
+    LDMIA   sp!, {r4-r11, lr}                   // Return to thread synchronously
+    BX      lr                                  // Return to caller
+
+/* } */
+
+
+#ifdef __ARM_FP
+    .global tx_thread_vfp_enable
+    .type   tx_thread_vfp_enable, "function"
+tx_thread_vfp_enable:
+    MRS     r2, CPSR                            // Pickup the CPSR
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  // Disable IRQ and FIQ interrupts
+#else
+    CPSID   i                                   // Disable IRQ interrupts
+#endif
+    LDR     r0, =_tx_thread_current_ptr         // Build current thread pointer address
+    LDR     r1, [r0]                            // Pickup current thread pointer
+    CMP     r1, #0                              // Check for NULL thread pointer
+    BEQ     __tx_no_thread_to_enable            // If NULL, skip VFP enable
+    MOV     r0, #1                              // Build enable value
+    STR     r0, [r1, #144]                      // Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
+__tx_no_thread_to_enable:
+    MSR     CPSR_cxsf, r2                       // Recover CPSR
+    BX      LR                                  // Return to caller
+
+    .global tx_thread_vfp_disable
+    .type   tx_thread_vfp_disable, "function"
+tx_thread_vfp_disable:
+    MRS     r2, CPSR                            // Pickup the CPSR
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  // Disable IRQ and FIQ interrupts
+#else
+    CPSID   i                                   // Disable IRQ interrupts
+#endif
+    LDR     r0, =_tx_thread_current_ptr         // Build current thread pointer address
+    LDR     r1, [r0]                            // Pickup current thread pointer
+    CMP     r1, #0                              // Check for NULL thread pointer
+    BEQ     __tx_no_thread_to_disable           // If NULL, skip VFP disable
+    MOV     r0, #0                              // Build disable value
+    STR     r0, [r1, #144]                      // Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
+__tx_no_thread_to_disable:
+    MSR     CPSR_cxsf, r2                       // Recover CPSR
+    BX      LR                                  // Return to caller
+#endif
diff --git a/ports/cortex_r4/ac6/src/tx_thread_stack_build.S b/ports/cortex_r4/ac6/src/tx_thread_stack_build.S
new file mode 100644
index 00000000..57fbb637
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_stack_build.S
@@ -0,0 +1,164 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_thread.h" */
+
+
+#define SVC_MODE 0x13                       // SVC mode
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define CPSR_MASK 0xDF                      // Mask initial CPSR, IRQ & FIQ ints enabled
+#else
+#define CPSR_MASK 0x9F                      // Mask initial CPSR, IRQ ints enabled
+#endif
+
+#define THUMB_BIT 0x20                      // Thumb-bit
+
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_stack_build                            Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function builds a stack frame on the supplied thread's stack.  */
+/*    The stack frame results in a fake interrupt return to the supplied  */
+/*    function pointer.                                                   */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    thread_ptr                            Pointer to thread control blk */
+/*    function_ptr                          Pointer to return function    */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_thread_create                     Create thread service         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) */
+/* { */
+    .global _tx_thread_stack_build
+    .type   _tx_thread_stack_build, "function"
+_tx_thread_stack_build:
+
+
+    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+       on the Cortex-R4 should look like the following after it is built:
+
+       Stack Top:      1           Interrupt stack frame type
+                       CPSR        Initial value for CPSR
+                       a1 (r0)     Initial value for a1
+                       a2 (r1)     Initial value for a2
+                       a3 (r2)     Initial value for a3
+                       a4 (r3)     Initial value for a4
+                       v1 (r4)     Initial value for v1
+                       v2 (r5)     Initial value for v2
+                       v3 (r6)     Initial value for v3
+                       v4 (r7)     Initial value for v4
+                       v5 (r8)     Initial value for v5
+                       sb (r9)     Initial value for sb
+                       sl (r10)    Initial value for sl
+                       fp (r11)    Initial value for fp
+                       ip (r12)    Initial value for ip
+                       lr (r14)    Initial value for lr
+                       pc (r15)    Initial value for pc
+                       0           For stack backtracing */
+
+    /* Stack Bottom: (higher memory address)  */
+
+    LDR     r2, [r0, #16]                       // Pickup end of stack area
+    BIC     r2, r2, #7                          // Ensure 8-byte alignment
+    SUB     r2, r2, #76                         // Allocate space for the stack frame
+
+    /* Actually build the stack frame.  */
+
+    MOV     r3, #1                              // Build interrupt stack type
+    STR     r3, [r2, #0]                        // Store stack type
+    MOV     r3, #0                              // Build initial register value
+    STR     r3, [r2, #8]                        // Store initial r0
+    STR     r3, [r2, #12]                       // Store initial r1
+    STR     r3, [r2, #16]                       // Store initial r2
+    STR     r3, [r2, #20]                       // Store initial r3
+    STR     r3, [r2, #24]                       // Store initial r4
+    STR     r3, [r2, #28]                       // Store initial r5
+    STR     r3, [r2, #32]                       // Store initial r6
+    STR     r3, [r2, #36]                       // Store initial r7
+    STR     r3, [r2, #40]                       // Store initial r8
+    STR     r3, [r2, #44]                       // Store initial r9
+    LDR     r3, [r0, #12]                       // Pickup stack starting address
+    STR     r3, [r2, #48]                       // Store initial r10 (sl)
+    MOV     r3, #0                              // Build initial register value
+    STR     r3, [r2, #52]                       // Store initial r11
+    STR     r3, [r2, #56]                       // Store initial r12
+    STR     r3, [r2, #60]                       // Store initial lr
+    STR     r1, [r2, #64]                       // Store initial pc
+    STR     r3, [r2, #68]                       // 0 for back-trace
+
+    MRS     r3, CPSR                            // Pickup CPSR
+    BIC     r3, r3, #CPSR_MASK                  // Mask mode bits of CPSR
+    ORR     r3, r3, #SVC_MODE                   // Build CPSR, SVC mode, interrupts enabled
+    TST     r1, 1                               // Test if Thumb bit is set in entry function address
+    ITE NE
+    ORRNE   r3, r3, #THUMB_BIT                  // Yes, set the Thumb bit
+    BICEQ   r3, r3, #THUMB_BIT                  // No, clear the Thumb bit
+    STR     r3, [r2, #4]                        // Store initial CPSR
+
+    /* Setup stack pointer.  */
+    /* thread_ptr -> tx_thread_stack_ptr =  r2; */
+
+    STR     r2, [r0, #8]                        // Save stack pointer in thread's
+                                                //   control block
+    BX      lr                                  // Return to caller
+/* } */
diff --git a/ports/cortex_r4/ac6/src/tx_thread_system_return.S b/ports/cortex_r4/ac6/src/tx_thread_system_return.S
new file mode 100644
index 00000000..4c025765
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_system_return.S
@@ -0,0 +1,162 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_thread.h" */
+/* #include "tx_timer.h" */
+
+
+    .global      _tx_thread_current_ptr
+    .global      _tx_timer_time_slice
+    .global      _tx_thread_schedule
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    .global      _tx_execution_thread_exit
+#endif
+
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_system_return                          Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function is target processor specific.  It is used to transfer */
+/*    control from a thread back to the ThreadX system.  Only a           */
+/*    minimal context is saved since the compiler assumes temp registers  */
+/*    are going to get slicked by a function call anyway.                 */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_thread_schedule                   Thread scheduling loop        */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ThreadX components                                                  */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_thread_system_return(VOID) */
+/* { */
+    .global _tx_thread_system_return
+    .type   _tx_thread_system_return, "function"
+_tx_thread_system_return:
+
+    /* Save minimal context on the stack.  */
+
+    STMDB   sp!, {r4-r11, lr}                   // Save minimal context
+    LDR     r5, =_tx_thread_current_ptr         // Pickup address of current ptr
+    LDR     r6, [r5, #0]                        // Pickup current thread pointer
+
+#ifdef __ARM_FP
+    LDR     r0, [r6, #144]                      // Pickup the VFP enabled flag
+    CMP     r0, #0                              // Is the VFP enabled?
+    BEQ     _tx_skip_solicited_vfp_save         // No, skip VFP solicited save
+    VMRS    r4, FPSCR                           // Pickup the FPSCR
+    STR     r4, [sp, #-4]!                      // Save FPSCR
+    VSTMDB  sp!, {D8-D15}                       // Save D8-D15
+_tx_skip_solicited_vfp_save:
+#endif
+
+    MOV     r0, #0                              // Build a solicited stack type
+    MRS     r1, CPSR                            // Pickup the CPSR
+    STMDB   sp!, {r0-r1}                        // Save type and CPSR
+
+   /* Lockout interrupts.  */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  // Disable IRQ and FIQ interrupts
+#else
+    CPSID   i                                   // Disable IRQ interrupts
+#endif
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the thread exit function to indicate the thread is no longer executing.  */
+
+    BL      _tx_execution_thread_exit           // Call the thread exit function
+#endif
+    LDR     r2, =_tx_timer_time_slice           // Pickup address of time slice
+    LDR     r1, [r2, #0]                        // Pickup current time slice
+
+    /* Save current stack and switch to system stack.  */
+    /* _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp; */
+    /* sp = _tx_thread_system_stack_ptr; */
+
+    STR     sp, [r6, #8]                        // Save thread stack pointer
+
+    /* Determine if the time-slice is active.  */
+    /* if (_tx_timer_time_slice) */
+    /* { */
+
+    MOV     r4, #0                              // Build clear value
+    CMP     r1, #0                              // Is a time-slice active?
+    BEQ     __tx_thread_dont_save_ts            // No, don't save the time-slice
+
+       /* Save the current remaining time-slice.  */
+       /* _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice; */
+       /* _tx_timer_time_slice =  0; */
+
+    STR     r4, [r2, #0]                        // Clear time-slice
+    STR     r1, [r6, #24]                       // Store current time-slice
+
+    /* } */
+__tx_thread_dont_save_ts:
+
+    /* Clear the current thread pointer.  */
+    /* _tx_thread_current_ptr =  TX_NULL; */
+
+    STR     r4, [r5, #0]                        // Clear current thread pointer
+
+    B       _tx_thread_schedule                 // Jump to scheduler!
+
+/* } */
diff --git a/ports/cortex_r4/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_r4/ac6/src/tx_thread_vectored_context_save.S
new file mode 100644
index 00000000..0b7134bd
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_thread_vectored_context_save.S
@@ -0,0 +1,193 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_thread.h" */
+
+
+    .global      _tx_thread_system_state
+    .global      _tx_thread_current_ptr
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    .global      _tx_execution_isr_enter
+#endif
+
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_vectored_context_save                  Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function saves the context of an executing thread in the       */
+/*    beginning of interrupt processing.  The function also ensures that  */
+/*    the system stack is used upon return to the calling ISR.            */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    ISRs                                                                */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* VOID  _tx_thread_vectored_context_save(VOID) */
+/* { */
+    .global _tx_thread_vectored_context_save
+    .type   _tx_thread_vectored_context_save, "function"
+_tx_thread_vectored_context_save:
+
+    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+       out, we are in IRQ mode, and all registers are intact.  */
+
+    /* Check for a nested interrupt condition.  */
+    /* if (_tx_thread_system_state++) */
+    /* { */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  // Disable IRQ and FIQ interrupts
+#endif
+    LDR     r3, =_tx_thread_system_state        // Pickup address of system state var
+    LDR     r2, [r3, #0]                        // Pickup system state
+    CMP     r2, #0                              // Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         // Yes, not a nested context save
+
+    /* Nested interrupt condition.  */
+
+    ADD     r2, r2, #1                          // Increment the interrupt counter
+    STR     r2, [r3, #0]                        // Store it back in the variable
+
+    /* Note: Minimal context of interrupted thread is already saved.  */
+
+    /* Return to the ISR.  */
+
+    MOV     r10, #0                             // Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    PUSH    {lr}                                // Save ISR lr
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    POP     {lr}                                // Recover ISR lr
+#endif
+
+    BX      lr                                  // Return to caller
+
+
+__tx_thread_not_nested_save:
+    /* } */
+
+    /* Otherwise, not nested, check to see if a thread was running.  */
+    /* else if (_tx_thread_current_ptr) */
+    /* { */
+
+    ADD     r2, r2, #1                          // Increment the interrupt counter
+    STR     r2, [r3, #0]                        // Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         // Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        // Pickup current thread pointer
+    CMP     r0, #0                              // Is it NULL?
+    BEQ     __tx_thread_idle_system_save        // If so, interrupt occurred in
+                                                //   scheduling loop - nothing needs saving!
+
+    /* Note: Minimal context of interrupted thread is already saved.  */
+
+    /* Save the current stack pointer in the thread's control block.  */
+    /* _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp; */
+
+    /* Switch to the system stack.  */
+    /* sp =  _tx_thread_system_stack_ptr; */
+
+    MOV     r10, #0                             // Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    PUSH    {lr}                                // Save ISR lr
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    POP     {lr}                                // Recover ISR lr
+#endif
+
+    BX      lr                                  // Return to caller
+
+    /* } */
+    /* else */
+    /* { */
+
+__tx_thread_idle_system_save:
+
+    /* Interrupt occurred in the scheduling loop.  */
+
+    /* Not much to do here, just adjust the stack pointer, and return to IRQ
+       processing.  */
+
+    MOV     r10, #0                             // Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+
+    /* Call the ISR enter function to indicate an ISR is executing.  */
+
+    PUSH    {lr}                                // Save ISR lr
+    BL      _tx_execution_isr_enter             // Call the ISR enter function
+    POP     {lr}                                // Recover ISR lr
+#endif
+
+    ADD     sp, sp, #32                         // Recover saved registers
+
+    BX      lr                                  // Return to caller
+
+    /* } */
+/* } */
diff --git a/ports/cortex_r4/ac6/src/tx_timer_interrupt.S b/ports/cortex_r4/ac6/src/tx_timer_interrupt.S
new file mode 100644
index 00000000..1426b7f9
--- /dev/null
+++ b/ports/cortex_r4/ac6/src/tx_timer_interrupt.S
@@ -0,0 +1,257 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Timer                                                               */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+/* #define TX_SOURCE_CODE  */
+
+
+/* Include necessary system files.  */
+
+/* #include "tx_api.h" */
+/* #include "tx_timer.h" */
+/* #include "tx_thread.h" */
+
+
+/* Define Assembly language external references... */
+
+    .global      _tx_timer_time_slice
+    .global      _tx_timer_system_clock
+    .global      _tx_timer_current_ptr
+    .global      _tx_timer_list_start
+    .global      _tx_timer_list_end
+    .global      _tx_timer_expired_time_slice
+    .global      _tx_timer_expired
+    .global      _tx_thread_time_slice
+    .global      _tx_timer_expiration_process
+
+
+#ifdef TX_THUMB_MODE
+    .thumb
+#else
+    .arm
+#endif
+    .text
+    .eabi_attribute Tag_ABI_align_preserved, 1
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_timer_interrupt                               Cortex-R4/AC6     */
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function processes the hardware timer interrupt.  This         */
+/*    processing includes incrementing the system clock and checking for  */
+/*    time slice and/or timer expiration.  If either is found, the        */
+/*    interrupt context save/restore functions are called along with the  */
+/*    expiration functions.                                               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    _tx_timer_expiration_process          Timer expiration processing   */
+/*    _tx_thread_time_slice                 Time slice interrupted thread */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    interrupt vector                                                    */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+/* VOID   _tx_timer_interrupt(VOID) */
+/* { */
+    .global _tx_timer_interrupt
+    .type   _tx_timer_interrupt, "function"
+_tx_timer_interrupt:
+
+    /* Upon entry to this routine, it is assumed that context save has already
+       been called, and therefore the compiler scratch registers are available
+       for use.  */
+
+    /* Increment the system clock.  */
+    /* _tx_timer_system_clock++; */
+
+    LDR     r1, =_tx_timer_system_clock         // Pickup address of system clock
+    LDR     r0, [r1, #0]                        // Pickup system clock
+    ADD     r0, r0, #1                          // Increment system clock
+    STR     r0, [r1, #0]                        // Store new system clock
+
+    /* Test for time-slice expiration.  */
+    /* if (_tx_timer_time_slice) */
+    /* { */
+
+    LDR     r3, =_tx_timer_time_slice           // Pickup address of time-slice
+    LDR     r2, [r3, #0]                        // Pickup time-slice
+    CMP     r2, #0                              // Is it non-active?
+    BEQ     __tx_timer_no_time_slice            // Yes, skip time-slice processing
+
+       /* Decrement the time_slice.  */
+       /* _tx_timer_time_slice--; */
+
+    SUB     r2, r2, #1                          // Decrement the time-slice
+    STR     r2, [r3, #0]                        // Store new time-slice value
+
+       /* Check for expiration.  */
+       /* if (__tx_timer_time_slice == 0) */
+
+    CMP     r2, #0                              // Has it expired?
+    BNE     __tx_timer_no_time_slice            // No, skip expiration processing
+
+       /* Set the time-slice expired flag.  */
+       /* _tx_timer_expired_time_slice =  TX_TRUE; */
+
+    LDR     r3, =_tx_timer_expired_time_slice   // Pickup address of expired flag
+    MOV     r0, #1                              // Build expired value
+    STR     r0, [r3, #0]                        // Set time-slice expiration flag
+
+    /* } */
+
+__tx_timer_no_time_slice:
+
+    /* Test for timer expiration.  */
+    /* if (*_tx_timer_current_ptr) */
+    /* { */
+
+    LDR     r1, =_tx_timer_current_ptr          // Pickup current timer pointer addr
+    LDR     r0, [r1, #0]                        // Pickup current timer
+    LDR     r2, [r0, #0]                        // Pickup timer list entry
+    CMP     r2, #0                              // Is there anything in the list?
+    BEQ     __tx_timer_no_timer                 // No, just increment the timer
+
+        /* Set expiration flag.  */
+        /* _tx_timer_expired =  TX_TRUE; */
+
+    LDR     r3, =_tx_timer_expired              // Pickup expiration flag address
+    MOV     r2, #1                              // Build expired value
+    STR     r2, [r3, #0]                        // Set expired flag
+    B       __tx_timer_done                     // Finished timer processing
+
+    /* } */
+    /* else */
+    /* { */
+__tx_timer_no_timer:
+
+        /* No timer expired, increment the timer pointer.  */
+        /* _tx_timer_current_ptr++; */
+
+    ADD     r0, r0, #4                          // Move to next timer
+
+        /* Check for wrap-around.  */
+        /* if (_tx_timer_current_ptr == _tx_timer_list_end) */
+
+    LDR     r3, =_tx_timer_list_end             // Pickup addr of timer list end
+    LDR     r2, [r3, #0]                        // Pickup list end
+    CMP     r0, r2                              // Are we at list end?
+    BNE     __tx_timer_skip_wrap                // No, skip wrap-around logic
+
+            /* Wrap to beginning of list.  */
+            /* _tx_timer_current_ptr =  _tx_timer_list_start; */
+
+    LDR     r3, =_tx_timer_list_start           // Pickup addr of timer list start
+    LDR     r0, [r3, #0]                        // Set current pointer to list start
+
+__tx_timer_skip_wrap:
+
+    STR     r0, [r1, #0]                        // Store new current timer pointer
+    /* } */
+
+__tx_timer_done:
+
+
+    /* See if anything has expired.  */
+    /* if ((_tx_timer_expired_time_slice)    (_tx_timer_expired)) */
+    /* { */
+
+    LDR     r3, =_tx_timer_expired_time_slice   // Pickup addr of expired flag
+    LDR     r2, [r3, #0]                        // Pickup time-slice expired flag
+    CMP     r2, #0                              // Did a time-slice expire?
+    BNE     __tx_something_expired              // If non-zero, time-slice expired
+    LDR     r1, =_tx_timer_expired              // Pickup addr of other expired flag
+    LDR     r0, [r1, #0]                        // Pickup timer expired flag
+    CMP     r0, #0                              // Did a timer expire?
+    BEQ     __tx_timer_nothing_expired          // No, nothing expired
+
+__tx_something_expired:
+
+
+    STMDB   sp!, {r0, lr}                       // Save the lr register on the stack
+                                                //   and save r0 just to keep 8-byte alignment
+
+    /* Did a timer expire?  */
+    /* if (_tx_timer_expired) */
+    /* { */
+
+    LDR     r1, =_tx_timer_expired              // Pickup addr of expired flag
+    LDR     r0, [r1, #0]                        // Pickup timer expired flag
+    CMP     r0, #0                              // Check for timer expiration
+    BEQ     __tx_timer_dont_activate            // If not set, skip timer activation
+
+        /* Process timer expiration.  */
+        /* _tx_timer_expiration_process(); */
+
+    BL      _tx_timer_expiration_process        // Call the timer expiration handling routine
+
+    /* } */
+__tx_timer_dont_activate:
+
+    /* Did time slice expire?  */
+    /* if (_tx_timer_expired_time_slice) */
+    /* { */
+
+    LDR     r3, =_tx_timer_expired_time_slice   // Pickup addr of time-slice expired
+    LDR     r2, [r3, #0]                        // Pickup the actual flag
+    CMP     r2, #0                              // See if the flag is set
+    BEQ     __tx_timer_not_ts_expiration        // No, skip time-slice processing
+
+        /* Time slice interrupted thread.  */
+        /* _tx_thread_time_slice(); */
+
+    BL      _tx_thread_time_slice               // Call time-slice processing
+
+    /* } */
+
+__tx_timer_not_ts_expiration:
+
+    LDMIA   sp!, {r0, lr}                       // Recover lr register (r0 is just there for
+                                                //   the 8-byte stack alignment
+
+    /* } */
+
+__tx_timer_nothing_expired:
+    BX      lr                                  // Return to caller
+
+/* } */
diff --git a/ports/cortex_r4/gnu/example_build/build_threadx.bat b/ports/cortex_r4/gnu/example_build/build_threadx.bat
new file mode 100644
index 00000000..106c3447
--- /dev/null
+++ b/ports/cortex_r4/gnu/example_build/build_threadx.bat
@@ -0,0 +1,238 @@
+del tx.a
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 tx_initialize_low_level.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_stack_build.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_schedule.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_system_return.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_context_save.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_context_restore.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_interrupt_control.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_timer_interrupt.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_interrupt_disable.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_interrupt_restore.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_fiq_context_save.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_fiq_nesting_start.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_irq_nesting_start.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_irq_nesting_end.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_fiq_nesting_end.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_fiq_context_restore.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 ../src/tx_thread_vectored_context_save.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c
+arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
+arm-none-eabi-ar -r tx.a tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_start.o tx_thread_irq_nesting_start.o tx_thread_irq_nesting_end.o
+arm-none-eabi-ar -r tx.a tx_thread_fiq_nesting_end.o tx_thread_fiq_context_restore.o tx_thread_vectored_context_save.o tx_initialize_low_level.o
+arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
+arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
+arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
+arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
+arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
+arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
+arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
+arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
+arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
+arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o 
+arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
+arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
+arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
+arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
+arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
+arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
+arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
+arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
+arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
+arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
+arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o 
+arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
+arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
+arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o 
+arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o 
+arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o 
+arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
+arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
+arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
+arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
+arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o 
+arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
+arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o
diff --git a/ports/cortex_r4/gnu/example_build/build_threadx_sample.bat b/ports/cortex_r4/gnu/example_build/build_threadx_sample.bat
new file mode 100644
index 00000000..517b6d62
--- /dev/null
+++ b/ports/cortex_r4/gnu/example_build/build_threadx_sample.bat
@@ -0,0 +1,6 @@
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 reset.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 crt0.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 tx_initialize_low_level.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r4 -I../../../../common/inc -I../inc sample_threadx.c
+arm-none-eabi-ld -A cortex-r4 -T sample_threadx.ld reset.o crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libc.a libgcc.a -o sample_threadx.out -M > sample_threadx.map
+
diff --git a/ports/cortex_r4/gnu/example_build/crt0.S b/ports/cortex_r4/gnu/example_build/crt0.S
new file mode 100644
index 00000000..aa0f3239
--- /dev/null
+++ b/ports/cortex_r4/gnu/example_build/crt0.S
@@ -0,0 +1,90 @@
+
+/* .text is used instead of .section .text so it works with arm-aout too.  */
+    .text
+    .code 32
+    .align  0
+
+    .global _mainCRTStartup
+    .global _start
+    .global start
+start:
+_start:
+_mainCRTStartup:
+
+/* Start by setting up a stack */
+    /*  Set up the stack pointer to a fixed value */
+    ldr r3, .LC0
+    mov     sp, r3
+    /* Setup a default stack-limit in case the code has been
+       compiled with "-mapcs-stack-check".  Hard-wiring this value
+       is not ideal, since there is currently no support for
+       checking that the heap and stack have not collided, or that
+       this default 64k is enough for the program being executed.
+       However, it ensures that this simple crt0 world will not
+       immediately cause an overflow event:  */
+    sub sl, sp, #64 << 10   /* Still assumes 256bytes below sl */
+    mov     a2, #0          /* Second arg: fill value */
+    mov fp, a2          /* Null frame pointer */
+    mov r7, a2          /* Null frame pointer for Thumb */
+    
+    ldr a1, .LC1        /* First arg: start of memory block */
+    ldr a3, .LC2    
+    sub a3, a3, a1      /* Third arg: length of block */
+    
+
+    
+        bl      memset
+    mov r0, #0      /*  no arguments  */
+    mov r1, #0      /*  no argv either */
+#ifdef __USES_INITFINI__
+    /* Some arm/elf targets use the .init and .fini sections
+       to create constructors and destructors, and for these
+       targets we need to call the _init function and arrange
+       for _fini to be called at program exit.  */
+    mov r4, r0
+    mov r5, r1
+/*        ldr     r0, .Lfini */
+        bl      atexit
+/*        bl      init */
+    mov r0, r4
+    mov r1, r5
+#endif  
+        bl      main
+
+        bl      exit         /* Should not return.  */
+
+    
+    /* For Thumb, constants must be after the code since only 
+       positive offsets are supported for PC relative addresses.  */
+    
+    .align 0
+.LC0:
+.LC1:
+    .word   __bss_start__
+.LC2:
+    .word   __bss_end__
+/*
+#ifdef __USES_INITFINI__
+.Lfini:
+    .word   _fini
+#endif  */
+    /* Return ...  */
+#ifdef __APCS_26__
+    movs    pc, lr
+#else
+#ifdef __THUMB_INTERWORK
+    bx  lr
+#else
+    mov pc, lr
+#endif
+#endif
+
+
+/*  Workspace for Angel calls.  */
+    .data
+/*  Data returned by monitor SWI.  */
+.global __stack_base__
+HeapBase:   .word   0
+HeapLimit:  .word   0
+__stack_base__: .word   0
+StackLimit: .word   0
diff --git a/ports/cortex_r4/gnu/example_build/libc.a b/ports/cortex_r4/gnu/example_build/libc.a
new file mode 100644
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+#include 
+
+
+/* Define ThreadX basic types for this port.  */ 
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */ 
+#endif
+
+
+/* Define various constants for the ThreadX ARM port.  */ 
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_INT_DISABLE                          0xC0        /* Disable IRQ & FIQ interrupts     */
+#else
+#define TX_INT_DISABLE                          0x80        /* Disable IRQ interrupts           */
+#endif
+#define TX_INT_ENABLE                           0x00        /* Enable IRQ interrupts            */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ++_tx_trace_simulated_time
+#endif
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_FIQ_ENABLED                          1
+#else
+#define TX_FIQ_ENABLED                          0
+#endif
+
+#ifdef TX_ENABLE_IRQ_NESTING
+#define TX_IRQ_NESTING_ENABLED                  2
+#else
+#define TX_IRQ_NESTING_ENABLED                  0
+#endif
+
+#ifdef TX_ENABLE_FIQ_NESTING
+#define TX_FIQ_NESTING_ENABLED                  4
+#else
+#define TX_FIQ_NESTING_ENABLED                  0
+#endif
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#define TX_INLINE_INITIALIZATION
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#define TX_THREAD_EXTENSION_2          
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+   
+#if __TARGET_ARCH_ARM > 4
+
+#ifndef __thumb__
+
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       m = m & ((ULONG) (-((LONG) m))); \
+                                                asm volatile (" CLZ  %0,%1 ": "=r" (b) : "r" (m) ); \
+                                                b = 31 - b; 
+#endif
+#endif
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifdef __thumb__
+
+unsigned int   _tx_thread_interrupt_disable(void);
+unsigned int   _tx_thread_interrupt_restore(UINT old_posture);
+
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int interrupt_save;
+
+#define TX_DISABLE                              interrupt_save =  _tx_thread_interrupt_disable();
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+
+#else
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int interrupt_save, tx_temp;
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_DISABLE                              asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) );
+#else
+#define TX_DISABLE                              asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) );
+#endif
+
+#define TX_RESTORE                              asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) );
+
+#endif
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Cortex-R5/GNU Version 6.0 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+
+#endif
+
diff --git a/ports/cortex_r5/gnu/readme_threadx.txt b/ports/cortex_r5/gnu/readme_threadx.txt
new file mode 100644
index 00000000..8c26cebd
--- /dev/null
+++ b/ports/cortex_r5/gnu/readme_threadx.txt
@@ -0,0 +1,496 @@
+                     Microsoft's Azure RTOS ThreadX for Cortex-R5 
+
+                              Using the GNU Tools
+
+1.  Building the ThreadX run-time Library
+
+First make sure you are in the "example_build" directory. Also, make sure that 
+you have setup your path and other environment variables necessary for the GNU 
+development environment. 
+
+At this point you may run the build_threadx.bat batch file. This will build the 
+ThreadX run-time environment in the "example_build" directory. 
+
+You should observe assembly and compilation of a series of ThreadX source 
+files. At the end of the batch file, they are all combined into the 
+run-time library file: tx.a. This file must be linked with your 
+application in order to use ThreadX.
+
+
+2.  Demonstration System
+
+Building the demonstration is easy; simply execute the build_threadx_sample.bat 
+batch file while inside the "example_build" directory. 
+
+You should observe the compilation of sample_threadx.c (which is the demonstration 
+application) and linking with TX.A. The resulting file DEMO is a binary file 
+that can be downloaded and executed.
+
+
+3.  System Initialization
+
+The entry point in ThreadX for the Cortex-R5 using GNU tools is at label _start. 
+This is defined within the modified version of the GNU startup code - crt0.S.
+
+The ThreadX tx_initialize_low_level.S file is responsible for setting up various 
+system data structures, the interrupt vectors, and a periodic timer interrupt source. 
+By default, the vector area is defined to be located at the "__vectors" label, 
+which is defined in reset.S. This area is typically located at 0. In situations 
+where this is impossible, the vectors at the "__vectors" label should be copied 
+to address 0.
+
+This is also where initialization of a periodic timer interrupt source should take 
+place.
+
+In addition, _tx_initialize_low_level defines the first available address 
+for use by the application, which is supplied as the sole input parameter 
+to your application definition function, tx_application_define.
+
+
+4.  Assembler / Compiler Switches
+
+The following are compiler switches used in building the demonstration 
+system:
+
+Compiler/Assembler                  Meaning
+    Switches
+
+    -g                      Specifies debug information
+    -c                      Specifies object code generation
+    -mcpu=cortex-r5              Specifies target cpu
+
+Linker Switch                       Meaning
+
+    -o sample_threadx.out     Specifies output file
+    -M > sample_threadx.map   Specifies demo map file
+    -A cortex-r5            Specifies target architecture
+    -T sample_threadx.ld      Specifies the loader control file
+
+Application Defines ( -D option)
+
+    TX_ENABLE_FIQ_SUPPORT                       This assembler define enables FIQ
+                                                interrupt handling support in the
+                                                ThreadX assembly files. If used,
+                                                it should be used on all assembly
+                                                files and the generic C source of
+                                                ThreadX should be compiled with 
+                                                TX_ENABLE_FIQ_SUPPORT defined as well.
+
+    TX_ENABLE_IRQ_NESTING                       This assembler define enables IRQ
+                                                nested support. If IRQ nested 
+                                                interrupt support is needed, this
+                                                define should be applied to 
+                                                tx_initialize_low_level.S.
+
+    TX_ENABLE_FIQ_NESTING                       This assembler define enables FIQ
+                                                nested support. If FIQ nested 
+                                                interrupt support is needed, this
+                                                define should be applied to 
+                                                tx_initialize_low_level.S. In addition,
+                                                IRQ nesting should also be enabled.
+
+    TX_ENABLE_FIQ_SUPPORT                       This compiler define enables FIQ
+                                                interrupt handling in the ThreadX
+                                                generic C source. This define 
+                                                should also be used in conjunction
+                                                with the corresponding assembler
+                                                define.                                               
+
+    TX_DISABLE_ERROR_CHECKING                   If defined before tx_api.h is included,
+                                                this define causes basic ThreadX error
+                                                checking to be disabled. Please see
+                                                Chapter 2 in the "ThreadX User Guide" 
+                                                for more details.
+
+    TX_MAX_PRIORITIES                           Defines the priority levels for ThreadX. 
+                                                Legal values range from 32 through 
+                                                1024 (inclusive) and MUST be evenly divisible 
+                                                by 32. Increasing the number of priority levels 
+                                                supported increases the RAM usage by 128 bytes 
+                                                for every group of 32 priorities. However, there 
+                                                is only a negligible effect on performance. By 
+                                                default, this value is set to 32 priority levels.
+
+    TX_MINIMUM_STACK                            Defines the minimum stack size (in bytes). It is 
+                                                used for error checking when threads are created. 
+                                                The default value is port-specific and is found 
+                                                in tx_port.h.
+
+    TX_TIMER_THREAD_STACK_SIZE                  Defines the stack size (in bytes) of the internal 
+                                                ThreadX timer thread. This thread processes all 
+                                                thread sleep requests as well as all service call 
+                                                timeouts. In addition, all application timer callback 
+                                                routines are invoked from this context. The default 
+                                                value is port-specific and is found in tx_port.h.
+
+    TX_TIMER_THREAD_PRIORITY                    Defines the priority of the internal ThreadX timer 
+                                                thread. The default value is priority 0 - the highest 
+                                                priority in ThreadX. The default value is defined 
+                                                in tx_port.h.
+
+    TX_TIMER_PROCESS_IN_ISR                     Defined, this option eliminates the internal system 
+                                                timer thread for ThreadX. This results in improved 
+                                                performance on timer events and smaller RAM requirements 
+                                                because the timer stack and control block are no 
+                                                longer needed. However, using this option moves all 
+                                                the timer expiration processing to the timer ISR level. 
+                                                By default, this option is not defined.
+
+    TX_REACTIVATE_INLINE                        Defined, this option performs reactivation of ThreadX 
+                                                timers in-line instead of using a function call. This 
+                                                improves performance but slightly increases code size. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_STACK_FILLING                    Defined, placing the 0xEF value in each byte of each 
+                                                thread's stack is disabled. By default, this option is 
+                                                not defined.
+
+    TX_ENABLE_STACK_CHECKING                    Defined, this option enables ThreadX run-time stack checking, 
+                                                which includes analysis of how much stack has been used and 
+                                                examination of data pattern "fences" before and after the 
+                                                stack area. If a stack error is detected, the registered 
+                                                application stack error handler is called. This option does 
+                                                result in slightly increased overhead and code size. Please 
+                                                review the tx_thread_stack_error_notify API for more information. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_PREEMPTION_THRESHOLD             Defined, this option disables the preemption-threshold feature 
+                                                and slightly reduces code size and improves performance. Of course, 
+                                                the preemption-threshold capabilities are no longer available. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_REDUNDANT_CLEARING               Defined, this option removes the logic for initializing ThreadX 
+                                                global C data structures to zero. This should only be used if 
+                                                the compiler's initialization code sets all un-initialized 
+                                                C global data to zero. Using this option slightly reduces 
+                                                code size and improves performance during initialization. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_NOTIFY_CALLBACKS                 Defined, this option disables the notify callbacks for various 
+                                                ThreadX objects. Using this option slightly reduces code size 
+                                                and improves performance.
+
+    TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO       Defined, this option enables the gathering of performance 
+                                                information on block pools. By default, this option is 
+                                                not defined.
+
+    TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO        Defined, this option enables the gathering of performance 
+                                                information on byte pools. By default, this option is 
+                                                not defined.
+
+    TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO      Defined, this option enables the gathering of performance 
+                                                information on event flags groups. By default, this option 
+                                                is not defined.
+
+    TX_MUTEX_ENABLE_PERFORMANCE_INFO            Defined, this option enables the gathering of performance 
+                                                information on mutexes. By default, this option is 
+                                                not defined.
+
+    TX_QUEUE_ENABLE_PERFORMANCE_INFO            Defined, this option enables the gathering of performance 
+                                                information on queues. By default, this option is 
+                                                not defined.
+
+    TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO        Defined, this option enables the gathering of performance 
+                                                information on semaphores. By default, this option is 
+                                                not defined.
+
+    TX_THREAD_ENABLE_PERFORMANCE_INFO           Defined, this option enables the gathering of performance 
+                                                information on threads. By default, this option is 
+                                                not defined.
+
+    TX_TIMER_ENABLE_PERFORMANCE_INFO            Defined, this option enables the gathering of performance 
+                                                information on timers. By default, this option is 
+                                                not defined.
+
+    TX_ENABLE_EVENT_TRACE                       Defined, this option enables the internal ThreadX trace
+                                                feature. The trace buffer is supplied at a later time
+                                                via an application call to tx_trace_enable.
+
+    TX_TRACE_TIME_SOURCE                        This defines the time-stamp source for event tracing. 
+                                                This define is only pertinent if the ThreadX library is 
+                                                built with TX_ENABLE_EVENT_TRACE defined.
+
+    TX_TRACE_TIME_MASK                          This defines the number of valid bits in the event trace 
+                                                time-stamp source defined previously. If the time-stamp 
+                                                source is 16-bits, this value should be 0xFFFF. Alternatively, 
+                                                if the time-stamp source is 32-bits, this value should be 
+                                                0xFFFFFFFF. This define is only pertinent if the ThreadX 
+                                                library is built with TX_ENABLE_EVENT_TRACE defined.
+
+
+5.  Register Usage and Stack Frames
+
+The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch 
+registers for each function. All other registers used by a C function must 
+be preserved by the function. ThreadX takes advantage of this in situations 
+where a context switch happens as a result of making a ThreadX service call 
+(which is itself a C function). In such cases, the saved context of a thread 
+is only the non-scratch registers.
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have one of these two types of stack frames. The top
+of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the 
+associated thread control block TX_THREAD.
+
+
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x00                   1                           0
+     0x04                   CPSR                        CPSR
+     0x08                   r0  (a1)                    r4  (v1)
+     0x0C                   r1  (a2)                    r5  (v2)
+     0x10                   r2  (a3)                    r6  (v3)
+     0x14                   r3  (a4)                    r7  (v4)
+     0x18                   r4  (v1)                    r8  (v5)
+     0x1C                   r5  (v2)                    r9  (v6)
+     0x20                   r6  (v3)                    r10 (v7)
+     0x24                   r7  (v4)                    r11 (fp)
+     0x28                   r8  (v5)                    r14 (lr)
+     0x2C                   r9  (v6)                        
+     0x30                   r10 (v7)                        
+     0x34                   r11 (fp)                        
+     0x38                   r12 (ip)                         
+     0x3C                   r14 (lr)
+     0x40                   PC 
+
+
+6.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+7.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-R5
+targets. There are a certain set of requirements that are defined in the 
+following sub-sections:
+
+
+7.1  Vector Area
+
+The Cortex-R5 vectors start at address zero. The demonstration system startup
+reset.S file contains the vectors and is loaded at address zero. On actual 
+hardware platforms, this area might have to be copied to address 0. 
+
+
+7.2  IRQ ISRs
+
+ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports 
+nested IRQ interrupts. The following sub-sections define the IRQ capabilities.
+
+
+7.2.1 Standard IRQ ISRs
+
+The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ 
+interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following 
+is the default IRQ handler defined in tx_initialize_low_level.S:
+
+    .global __tx_irq_handler
+    .global __tx_irq_processing_return      
+__tx_irq_handler:
+@
+@    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save             @ Jump to the context save
+__tx_irq_processing_return:
+@
+@    /* At this point execution is still in the IRQ mode. The CPSR, point of
+@       interrupt, and all C scratch registers are available for use. Note 
+@       that IRQ interrupts are still disabled upon return from the context
+@       save function.  */
+@
+@    /* Application ISR call(s) go here!  */
+@
+@    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.2.2 Vectored IRQ ISRs
+
+The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified
+by the particular implementation. The following is an example IRQ handler defined in 
+tx_initialize_low_level.S:
+
+    .global __tx_irq_example_handler
+__tx_irq_example_handler:
+@
+@    /* Call context save to save system context.  */
+
+    STMDB   sp!, {r0-r3}                        @ Save some scratch registers
+    MRS     r0, SPSR                            @ Pickup saved SPSR
+    SUB     lr, lr, #4                          @ Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}             @ Store other scratch registers
+    BL      _tx_thread_vectored_context_save    @ Call the vectored IRQ context save
+@
+@    /* At this point execution is still in the IRQ mode. The CPSR, point of
+@       interrupt, and all C scratch registers are available for use. Note 
+@       that IRQ interrupts are still disabled upon return from the context
+@       save function.  */
+@
+@    /* Application ISR call goes here!  */
+@
+@    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.2.3  Nested IRQ Support
+
+By default, nested IRQ interrupt support is not enabled. To enable nested
+IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING
+defined. With this defined, two new IRQ interrupt management services are
+available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end.
+These function should be called between the IRQ context save and restore
+calls. 
+
+Execution between the calls to _tx_thread_irq_nesting_start and 
+_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved 
+by switching from IRQ mode to SYS mode and enabling IRQ interrupts.
+The SYS mode stack is used during the SYS mode operation, which was 
+setup in tx_initialize_low_level.S. When nested IRQ interrupts are no 
+longer required, calling the _tx_thread_irq_nesting_end service disables 
+nesting by disabling IRQ interrupts and switching back to IRQ mode in 
+preparation for the IRQ context restore service.
+
+The following is an example of enabling IRQ nested interrupts in a standard 
+IRQ handler:
+
+    .global __tx_irq_handler
+    .global __tx_irq_processing_return      
+__tx_irq_handler:
+@
+@    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return:
+@
+@    /* Enable nested IRQ interrupts. NOTE:  Since this service returns
+@       with IRQ interrupts enabled, all IRQ interrupt sources must be 
+@       cleared prior to calling this service.  */
+    BL      _tx_thread_irq_nesting_start
+@    
+@    /* Application ISR call(s) go here!  */
+@
+@    /* Disable nested IRQ interrupts. The mode is switched back to
+@       IRQ mode and IRQ interrupts are disable upon return.  */
+    BL      _tx_thread_irq_nesting_end
+@
+@    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.3  FIQ Interrupts
+
+By default, FIQ interrupts are left alone by ThreadX. Of course, this 
+means that the application is fully responsible for enabling the FIQ interrupt 
+and saving/restoring any registers used in the FIQ ISR processing. To globally 
+enable FIQ interrupts, the application should enable FIQ interrupts at the 
+beginning of each thread or before any threads are created in tx_application_define. 
+In addition, the application must ensure that no ThreadX service calls are made 
+from default FIQ ISRs, which is located in tx_initialize_low_level.S.
+
+
+7.3.1  Managed FIQ Interrupts
+
+Full ThreadX management of FIQ interrupts is provided if the ThreadX sources
+are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built
+this way, the FIQ interrupt handlers are very similar to the IRQ interrupt
+handlers defined previously. The following is default FIQ handler 
+defined in tx_initialize_low_level.S:
+
+
+    .global __tx_fiq_handler
+    .global __tx_fiq_processing_return
+__tx_fiq_handler:
+@
+@    /* Jump to fiq context save to save system context.  */
+    B       _tx_thread_fiq_context_save
+__tx_fiq_processing_return:
+@
+@    /* At this point execution is still in the FIQ mode. The CPSR, point of
+@       interrupt, and all C scratch registers are available for use.  */
+@
+@    /* Application FIQ handlers can be called here!  */
+@
+@    /* Jump to fiq context restore to restore system context.  */
+    B       _tx_thread_fiq_context_restore
+
+
+7.3.1.1 Nested FIQ Support
+
+By default, nested FIQ interrupt support is not enabled. To enable nested
+FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING
+defined. With this defined, two new FIQ interrupt management services are
+available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end.
+These function should be called between the FIQ context save and restore
+calls. 
+
+Execution between the calls to _tx_thread_fiq_nesting_start and 
+_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved 
+by switching from FIQ mode to SYS mode and enabling FIQ interrupts.
+The SYS mode stack is used during the SYS mode operation, which was 
+setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required,
+calling the _tx_thread_fiq_nesting_end service disables nesting by disabling
+FIQ interrupts and switching back to FIQ mode in preparation for the FIQ 
+context restore service.
+
+The following is an example of enabling FIQ nested interrupts in the 
+typical FIQ handler:
+
+
+    .global __tx_fiq_handler
+    .global __tx_fiq_processing_return
+__tx_fiq_handler:
+@
+@    /* Jump to fiq context save to save system context.  */
+    B       _tx_thread_fiq_context_save
+__tx_fiq_processing_return:
+@
+@    /* At this point execution is still in the FIQ mode. The CPSR, point of
+@       interrupt, and all C scratch registers are available for use.  */
+@
+@    /* Enable nested FIQ interrupts. NOTE:  Since this service returns
+@       with FIQ interrupts enabled, all FIQ interrupt sources must be 
+@       cleared prior to calling this service.  */
+    BL      _tx_thread_fiq_nesting_start
+@
+@    /* Application FIQ handlers can be called here!  */
+@
+@    /* Disable nested FIQ interrupts. The mode is switched back to
+@       FIQ mode and FIQ interrupts are disable upon return.  */
+    BL      _tx_thread_fiq_nesting_end
+@
+@    /* Jump to fiq context restore to restore system context.  */
+    B       _tx_thread_fiq_context_restore
+
+
+8.  ThreadX Timer Interrupt
+
+ThreadX requires a periodic interrupt source to manage all time-slicing, 
+thread sleeps, timeouts, and application timers. Without such a timer 
+interrupt source, these services are not functional but the remainder of 
+ThreadX will still run.
+
+To add the timer interrupt processing, simply make a call to 
+_tx_timer_interrupt in the IRQ processing. An example of this can be
+found in the file tx_initialize_low_level.S for the demonstration system.
+
+
+9.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX 6.0.1 version for Cortex-R5 using GNU tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_context_restore.S b/ports/cortex_r5/gnu/src/tx_thread_context_restore.S
new file mode 100644
index 00000000..cdca28e5
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_context_restore.S
@@ -0,0 +1,256 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@#include "tx_timer.h"
+@
+    .arm
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+SVC_MODE        =     0xD3               @ Disable IRQ/FIQ, SVC mode
+IRQ_MODE        =     0xD2               @ Disable IRQ/FIQ, IRQ mode
+#else
+SVC_MODE        =     0x93               @ Disable IRQ, SVC mode
+IRQ_MODE        =     0x92               @ Disable IRQ, IRQ mode
+#endif
+@
+    .global     _tx_thread_system_state
+    .global     _tx_thread_current_ptr
+    .global     _tx_thread_execute_ptr
+    .global     _tx_timer_time_slice
+    .global     _tx_thread_schedule
+    .global     _tx_thread_preempt_disable
+    .global     _tx_execution_isr_exit
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore
+@   since it will never be called 16-bit mode.  */
+@ 
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_context_restore                        Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function restores the interrupt context if it is processing a  */ 
+@/*    nested interrupt.  If not, it returns to the interrupt thread if no */ 
+@/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+@/*    if no thread was running, the function returns to the scheduler.    */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    _tx_thread_schedule                   Thread scheduling routine     */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                  Interrupt Service Routines    */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_context_restore(VOID)
+@{
+    .global _tx_thread_context_restore
+    .type   _tx_thread_context_restore,function
+_tx_thread_context_restore:
+@
+@    /* Lockout interrupts.  */
+@
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                              @ Disable IRQ and FIQ interrupts
+#else
+    CPSID   i                               @ Disable IRQ interrupts
+#endif
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR exit function to indicate an ISR is complete.  */
+@
+    BL      _tx_execution_isr_exit          @ Call the ISR exit function
+#endif
+@
+@    /* Determine if interrupts are nested.  */
+@    if (--_tx_thread_system_state)
+@    {
+@
+    LDR     r3, =_tx_thread_system_state    @ Pickup address of system state variable
+    LDR     r2, [r3]                        @ Pickup system state
+    SUB     r2, r2, #1                      @ Decrement the counter
+    STR     r2, [r3]                        @ Store the counter 
+    CMP     r2, #0                          @ Was this the first interrupt?
+    BEQ     __tx_thread_not_nested_restore  @ If so, not a nested restore
+@
+@    /* Interrupts are nested.  */
+@
+@    /* Just recover the saved registers and return to the point of 
+@       interrupt.  */
+@
+    LDMIA   sp!, {r0, r10, r12, lr}         @ Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                   @ Put SPSR back
+    LDMIA   sp!, {r0-r3}                    @ Recover r0-r3
+    MOVS    pc, lr                          @ Return to point of interrupt
+@
+@    }
+__tx_thread_not_nested_restore:
+@
+@    /* Determine if a thread was interrupted and no preemption is required.  */
+@    else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) 
+@               || (_tx_thread_preempt_disable))
+@    {
+@
+    LDR     r1, =_tx_thread_current_ptr     @ Pickup address of current thread ptr
+    LDR     r0, [r1]                        @ Pickup actual current thread pointer
+    CMP     r0, #0                          @ Is it NULL?
+    BEQ     __tx_thread_idle_system_restore @ Yes, idle system was interrupted
+@
+    LDR     r3, =_tx_thread_preempt_disable @ Pickup preempt disable address
+    LDR     r2, [r3]                        @ Pickup actual preempt disable flag
+    CMP     r2, #0                          @ Is it set?
+    BNE     __tx_thread_no_preempt_restore  @ Yes, don't preempt this thread
+    LDR     r3, =_tx_thread_execute_ptr     @ Pickup address of execute thread ptr
+    LDR     r2, [r3]                        @ Pickup actual execute thread pointer
+    CMP     r0, r2                          @ Is the same thread highest priority?
+    BNE     __tx_thread_preempt_restore     @ No, preemption needs to happen
+@
+@
+__tx_thread_no_preempt_restore:
+@
+@    /* Restore interrupted thread or ISR.  */
+@
+@    /* Pickup the saved stack pointer.  */
+@    tmp_ptr =  _tx_thread_current_ptr -> tx_thread_stack_ptr;
+@
+@   /* Recover the saved context and return to the point of interrupt.  */
+@
+    LDMIA   sp!, {r0, r10, r12, lr}         @ Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                   @ Put SPSR back
+    LDMIA   sp!, {r0-r3}                    @ Recover r0-r3
+    MOVS    pc, lr                          @ Return to point of interrupt
+@
+@    }
+@    else
+@    {
+__tx_thread_preempt_restore:
+@
+    LDMIA   sp!, {r3, r10, r12, lr}         @ Recover temporarily saved registers
+    MOV     r1, lr                          @ Save lr (point of interrupt)
+    MOV     r2, #SVC_MODE                   @ Build SVC mode CPSR
+    MSR     CPSR_c, r2                      @ Enter SVC mode
+    STR     r1, [sp, #-4]!                  @ Save point of interrupt
+    STMDB   sp!, {r4-r12, lr}               @ Save upper half of registers
+    MOV     r4, r3                          @ Save SPSR in r4
+    MOV     r2, #IRQ_MODE                   @ Build IRQ mode CPSR
+    MSR     CPSR_c, r2                      @ Enter IRQ mode
+    LDMIA   sp!, {r0-r3}                    @ Recover r0-r3
+    MOV     r5, #SVC_MODE                   @ Build SVC mode CPSR
+    MSR     CPSR_c, r5                      @ Enter SVC mode
+    STMDB   sp!, {r0-r3}                    @ Save r0-r3 on thread's stack
+@
+    LDR     r1, =_tx_thread_current_ptr     @ Pickup address of current thread ptr
+    LDR     r0, [r1]                        @ Pickup current thread pointer
+@
+#ifdef TX_ENABLE_VFP_SUPPORT
+    LDR     r2, [r0, #144]                  @ Pickup the VFP enabled flag
+    CMP     r2, #0                          @ Is the VFP enabled?
+    BEQ     _tx_skip_irq_vfp_save           @ No, skip VFP IRQ save
+    VMRS    r2, FPSCR                       @ Pickup the FPSCR
+    STR     r2, [sp, #-4]!                  @ Save FPSCR
+    VSTMDB  sp!, {D0-D15}                   @ Save D0-D15
+_tx_skip_irq_vfp_save:
+#endif
+@
+    MOV     r3, #1                          @ Build interrupt stack type
+    STMDB   sp!, {r3, r4}                   @ Save interrupt stack type and SPSR
+    STR     sp, [r0, #8]                    @ Save stack pointer in thread control
+                                            @   block
+@
+@    /* Save the remaining time-slice and disable it.  */
+@    if (_tx_timer_time_slice)
+@    {
+@
+    LDR     r3, =_tx_timer_time_slice       @ Pickup time-slice variable address
+    LDR     r2, [r3]                        @ Pickup time-slice
+    CMP     r2, #0                          @ Is it active?
+    BEQ     __tx_thread_dont_save_ts        @ No, don't save it
+@
+@        _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+@        _tx_timer_time_slice =  0;
+@
+    STR     r2, [r0, #24]                   @ Save thread's time-slice
+    MOV     r2, #0                          @ Clear value
+    STR     r2, [r3]                        @ Disable global time-slice flag
+@
+@    }
+__tx_thread_dont_save_ts:
+@
+@
+@    /* Clear the current task pointer.  */
+@    _tx_thread_current_ptr =  TX_NULL;
+@
+    MOV     r0, #0                          @ NULL value
+    STR     r0, [r1]                        @ Clear current thread pointer
+@
+@    /* Return to the scheduler.  */
+@    _tx_thread_schedule();
+@
+    B       _tx_thread_schedule             @ Return to scheduler
+@    }
+@
+__tx_thread_idle_system_restore:
+@
+@    /* Just return back to the scheduler!  */
+@
+    MOV     r0, #SVC_MODE                   @ Build SVC mode CPSR
+    MSR     CPSR_c, r0                      @ Enter SVC mode
+    B       _tx_thread_schedule             @ Return to scheduler
+@}
+
+
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_context_save.S b/ports/cortex_r5/gnu/src/tx_thread_context_save.S
new file mode 100644
index 00000000..ac7a98f4
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_context_save.S
@@ -0,0 +1,203 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@#include "tx_timer.h"
+@
+@
+    .global     _tx_thread_system_state
+    .global     _tx_thread_current_ptr
+    .global     _tx_irq_processing_return
+    .global     _tx_execution_isr_enter
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save
+@   since it will never be called 16-bit mode.  */
+@ 
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_context_save                           Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function saves the context of an executing thread in the       */ 
+@/*    beginning of interrupt processing.  The function also ensures that  */ 
+@/*    the system stack is used upon return to the calling ISR.            */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                                                */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_context_save(VOID)
+@{
+    .global _tx_thread_context_save
+    .type   _tx_thread_context_save,function
+_tx_thread_context_save:
+@
+@    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+@       out, we are in IRQ mode, and all registers are intact.  */
+@
+@    /* Check for a nested interrupt condition.  */
+@    if (_tx_thread_system_state++)
+@    {
+@
+    STMDB   sp!, {r0-r3}                    @ Save some working registers 
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                              @ Disable FIQ interrupts
+#endif
+    LDR     r3, =_tx_thread_system_state    @ Pickup address of system state variable
+    LDR     r2, [r3]                        @ Pickup system state
+    CMP     r2, #0                          @ Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save     @ Yes, not a nested context save
+@
+@    /* Nested interrupt condition.  */
+@
+    ADD     r2, r2, #1                      @ Increment the interrupt counter
+    STR     r2, [r3]                        @ Store it back in the variable
+@
+@   /* Save the rest of the scratch registers on the stack and return to the
+@      calling ISR.  */
+@
+    MRS     r0, SPSR                        @ Pickup saved SPSR
+    SUB     lr, lr, #4                      @ Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}         @ Store other registers
+@
+@    /* Return to the ISR.  */
+@
+    MOV     r10, #0                         @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                            @ Save ISR lr
+    BL      _tx_execution_isr_enter         @ Call the ISR enter function
+    POP     {lr}                            @ Recover ISR lr
+#endif
+
+    B       __tx_irq_processing_return      @ Continue IRQ processing 
+@
+__tx_thread_not_nested_save:
+@    }
+@
+@    /* Otherwise, not nested, check to see if a thread was running.  */
+@    else if (_tx_thread_current_ptr)
+@    {
+@
+    ADD     r2, r2, #1                      @ Increment the interrupt counter
+    STR     r2, [r3]                        @ Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr     @ Pickup address of current thread ptr
+    LDR     r0, [r1]                        @ Pickup current thread pointer
+    CMP     r0, #0                          @ Is it NULL?
+    BEQ     __tx_thread_idle_system_save    @ If so, interrupt occurred in 
+                                            @   scheduling loop - nothing needs saving!
+@
+@    /* Save minimal context of interrupted thread.  */
+@
+    MRS     r2, SPSR                        @ Pickup saved SPSR
+    SUB     lr, lr, #4                      @ Adjust point of interrupt 
+    STMDB   sp!, {r2, r10, r12, lr}         @ Store other registers
+@
+@    /* Save the current stack pointer in the thread's control block.  */
+@    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+@
+@    /* Switch to the system stack.  */
+@    sp =  _tx_thread_system_stack_ptr@
+@
+    MOV     r10, #0                         @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                            @ Save ISR lr
+    BL      _tx_execution_isr_enter         @ Call the ISR enter function
+    POP     {lr}                            @ Recover ISR lr
+#endif
+
+    B       __tx_irq_processing_return      @ Continue IRQ processing 
+@
+@    }
+@    else
+@    {
+@
+__tx_thread_idle_system_save:
+@
+@    /* Interrupt occurred in the scheduling loop.  */
+@
+@    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+@       processing.  */
+@
+    MOV     r10, #0                         @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                            @ Save ISR lr
+    BL      _tx_execution_isr_enter         @ Call the ISR enter function
+    POP     {lr}                            @ Recover ISR lr
+#endif
+
+    ADD     sp, sp, #16                     @ Recover saved registers
+    B       __tx_irq_processing_return      @ Continue IRQ processing  
+@
+@    }
+@}
+
+
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S
new file mode 100644
index 00000000..955a9e8c
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_restore.S
@@ -0,0 +1,247 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@#include "tx_timer.h"
+@
+@
+SVC_MODE        =       0xD3                    @ SVC mode
+FIQ_MODE        =       0xD1                    @ FIQ mode
+MODE_MASK       =       0x1F                    @ Mode mask 
+THUMB_MASK      =       0x20                    @ Thumb bit mask
+IRQ_MODE_BITS   =       0x12                    @ IRQ mode bits
+@
+@
+    .global     _tx_thread_system_state
+    .global     _tx_thread_current_ptr
+    .global     _tx_thread_system_stack_ptr
+    .global     _tx_thread_execute_ptr
+    .global     _tx_timer_time_slice
+    .global     _tx_thread_schedule
+    .global     _tx_thread_preempt_disable
+    .global     _tx_execution_isr_exit
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore
+@   since it will never be called 16-bit mode.  */
+@
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_fiq_context_restore                    Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function restores the fiq interrupt context when processing a  */ 
+@/*    nested interrupt.  If not, it returns to the interrupt thread if no */ 
+@/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+@/*    if no thread was running, the function returns to the scheduler.    */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    _tx_thread_schedule                   Thread scheduling routine     */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    FIQ ISR                               Interrupt Service Routines    */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_fiq_context_restore(VOID)
+@{
+    .global  _tx_thread_fiq_context_restore
+    .type    _tx_thread_fiq_context_restore,function
+_tx_thread_fiq_context_restore:
+@
+@    /* Lockout interrupts.  */
+@
+    CPSID   if                                  @ Disable IRQ and FIQ interrupts
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR exit function to indicate an ISR is complete.  */
+@
+    BL      _tx_execution_isr_exit              @ Call the ISR exit function
+#endif
+@
+@    /* Determine if interrupts are nested.  */
+@    if (--_tx_thread_system_state)
+@    {
+@
+    LDR     r3, =_tx_thread_system_state        @ Pickup address of system state variable
+    LDR     r2, [r3]                            @ Pickup system state
+    SUB     r2, r2, #1                          @ Decrement the counter
+    STR     r2, [r3]                            @ Store the counter 
+    CMP     r2, #0                              @ Was this the first interrupt?
+    BEQ     __tx_thread_fiq_not_nested_restore  @ If so, not a nested restore
+@
+@    /* Interrupts are nested.  */
+@
+@    /* Just recover the saved registers and return to the point of 
+@       interrupt.  */
+@
+    LDMIA   sp!, {r0, r10, r12, lr}             @ Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       @ Put SPSR back
+    LDMIA   sp!, {r0-r3}                        @ Recover r0-r3
+    MOVS    pc, lr                              @ Return to point of interrupt
+@
+@    }
+__tx_thread_fiq_not_nested_restore:
+@
+@    /* Determine if a thread was interrupted and no preemption is required.  */
+@    else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) 
+@               || (_tx_thread_preempt_disable))
+@    {
+@
+    LDR     r1, [sp]                            @ Pickup the saved SPSR
+    MOV     r2, #MODE_MASK                      @ Build mask to isolate the interrupted mode
+    AND     r1, r1, r2                          @ Isolate mode bits
+    CMP     r1, #IRQ_MODE_BITS                  @ Was an interrupt taken in IRQ mode before we
+                                                @   got to context save? */
+    BEQ     __tx_thread_fiq_no_preempt_restore  @ Yes, just go back to point of interrupt
+
+
+    LDR     r1, =_tx_thread_current_ptr         @ Pickup address of current thread ptr
+    LDR     r0, [r1]                            @ Pickup actual current thread pointer
+    CMP     r0, #0                              @ Is it NULL?
+    BEQ     __tx_thread_fiq_idle_system_restore @ Yes, idle system was interrupted
+
+    LDR     r3, =_tx_thread_preempt_disable     @ Pickup preempt disable address
+    LDR     r2, [r3]                            @ Pickup actual preempt disable flag
+    CMP     r2, #0                              @ Is it set?
+    BNE     __tx_thread_fiq_no_preempt_restore  @ Yes, don't preempt this thread
+    LDR     r3, =_tx_thread_execute_ptr         @ Pickup address of execute thread ptr
+    LDR     r2, [r3]                            @ Pickup actual execute thread pointer
+    CMP     r0, r2                              @ Is the same thread highest priority?
+    BNE     __tx_thread_fiq_preempt_restore     @ No, preemption needs to happen
+
+
+__tx_thread_fiq_no_preempt_restore:
+@
+@    /* Restore interrupted thread or ISR.  */
+@
+@    /* Pickup the saved stack pointer.  */
+@    tmp_ptr =  _tx_thread_current_ptr -> tx_thread_stack_ptr;
+@
+@    /* Recover the saved context and return to the point of interrupt.  */
+@
+    LDMIA   sp!, {r0, lr}                       @ Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       @ Put SPSR back
+    LDMIA   sp!, {r0-r3}                        @ Recover r0-r3
+    MOVS    pc, lr                              @ Return to point of interrupt
+@
+@    }
+@    else
+@    {
+__tx_thread_fiq_preempt_restore:
+@
+    LDMIA   sp!, {r3, lr}                       @ Recover temporarily saved registers
+    MOV     r1, lr                              @ Save lr (point of interrupt)
+    MOV     r2, #SVC_MODE                       @ Build SVC mode CPSR
+    MSR     CPSR_c, r2                          @ Enter SVC mode
+    STR     r1, [sp, #-4]!                      @ Save point of interrupt
+    STMDB   sp!, {r4-r12, lr}                   @ Save upper half of registers
+    MOV     r4, r3                              @ Save SPSR in r4
+    MOV     r2, #FIQ_MODE                       @ Build FIQ mode CPSR
+    MSR     CPSR_c, r2                          @ Reenter FIQ mode
+    LDMIA   sp!, {r0-r3}                        @ Recover r0-r3
+    MOV     r5, #SVC_MODE                       @ Build SVC mode CPSR
+    MSR     CPSR_c, r5                          @ Enter SVC mode
+    STMDB   sp!, {r0-r3}                        @ Save r0-r3 on thread's stack
+    MOV     r3, #1                              @ Build interrupt stack type
+    STMDB   sp!, {r3, r4}                       @ Save interrupt stack type and SPSR
+    LDR     r1, =_tx_thread_current_ptr         @ Pickup address of current thread ptr
+    LDR     r0, [r1]                            @ Pickup current thread pointer
+    STR     sp, [r0, #8]                        @ Save stack pointer in thread control
+                                                @   block  */
+@
+@    /* Save the remaining time-slice and disable it.  */
+@    if (_tx_timer_time_slice)
+@    {
+@
+    LDR     r3, =_tx_timer_time_slice           @ Pickup time-slice variable address
+    LDR     r2, [r3]                            @ Pickup time-slice
+    CMP     r2, #0                              @ Is it active?
+    BEQ     __tx_thread_fiq_dont_save_ts        @ No, don't save it
+@
+@        _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+@        _tx_timer_time_slice =  0; 
+@
+    STR     r2, [r0, #24]                       @ Save thread's time-slice
+    MOV     r2, #0                              @ Clear value
+    STR     r2, [r3]                            @ Disable global time-slice flag
+@
+@    }
+__tx_thread_fiq_dont_save_ts:
+@
+@
+@    /* Clear the current task pointer.  */
+@    _tx_thread_current_ptr =  TX_NULL;
+@
+    MOV     r0, #0                              @ NULL value
+    STR     r0, [r1]                            @ Clear current thread pointer
+@
+@    /* Return to the scheduler.  */
+@    _tx_thread_schedule();
+@
+    B       _tx_thread_schedule                 @ Return to scheduler
+@    }
+@
+__tx_thread_fiq_idle_system_restore:
+@
+@    /* Just return back to the scheduler!  */
+@
+    ADD     sp, sp, #24                         @ Recover FIQ stack space
+    MOV     r3, #SVC_MODE                       @ Build SVC mode CPSR
+    MSR     CPSR_c, r3                          @ Lockout interrupts
+    B       _tx_thread_schedule                 @ Return to scheduler
+@
+@}
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S
new file mode 100644
index 00000000..576ecc4c
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_context_save.S
@@ -0,0 +1,204 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+    .global     _tx_thread_system_state
+    .global     _tx_thread_current_ptr
+    .global     __tx_fiq_processing_return
+    .global     _tx_execution_isr_enter
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save
+@   since it will never be called 16-bit mode.  */
+@
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_fiq_context_save                      Cortex-R5/GNU      */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function saves the context of an executing thread in the       */ 
+@/*    beginning of interrupt processing.  The function also ensures that  */ 
+@/*    the system stack is used upon return to the calling ISR.            */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                                                */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@ VOID   _tx_thread_fiq_context_save(VOID)
+@{
+    .global  _tx_thread_fiq_context_save
+    .type    _tx_thread_fiq_context_save,function
+_tx_thread_fiq_context_save:
+@
+@    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+@       out, we are in IRQ mode, and all registers are intact.  */
+@
+@    /* Check for a nested interrupt condition.  */
+@    if (_tx_thread_system_state++)
+@    {
+@
+    STMDB   sp!, {r0-r3}                        @ Save some working registers 
+    LDR     r3, =_tx_thread_system_state        @ Pickup address of system state variable
+    LDR     r2, [r3]                            @ Pickup system state
+    CMP     r2, #0                              @ Is this the first interrupt?
+    BEQ     __tx_thread_fiq_not_nested_save     @ Yes, not a nested context save
+@
+@    /* Nested interrupt condition.  */
+@
+    ADD     r2, r2, #1                          @ Increment the interrupt counter
+    STR     r2, [r3]                            @ Store it back in the variable
+@
+@    /* Save the rest of the scratch registers on the stack and return to the
+@       calling ISR.  */
+@
+    MRS     r0, SPSR                            @ Pickup saved SPSR
+    SUB     lr, lr, #4                          @ Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}             @ Store other registers
+@
+@    /* Return to the ISR.  */
+@
+    MOV     r10, #0                             @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                                @ Save ISR lr
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
+    POP     {lr}                                @ Recover ISR lr
+#endif
+
+    B       __tx_fiq_processing_return          @ Continue FIQ processing 
+@
+__tx_thread_fiq_not_nested_save:
+@    }  
+@
+@    /* Otherwise, not nested, check to see if a thread was running.  */
+@    else if (_tx_thread_current_ptr)
+@    {   
+@
+    ADD     r2, r2, #1                          @ Increment the interrupt counter
+    STR     r2, [r3]                            @ Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         @ Pickup address of current thread ptr
+    LDR     r0, [r1]                            @ Pickup current thread pointer
+    CMP     r0, #0                              @ Is it NULL?
+    BEQ     __tx_thread_fiq_idle_system_save    @ If so, interrupt occurred in 
+@                                               @   scheduling loop - nothing needs saving! 
+@
+@    /* Save minimal context of interrupted thread.  */
+@
+    MRS     r2, SPSR                            @ Pickup saved SPSR
+    SUB     lr, lr, #4                          @ Adjust point of interrupt 
+    STMDB   sp!, {r2, lr}                       @ Store other registers, Note that we don't
+@                                               @   need to save sl and ip since FIQ has 
+@                                               @   copies of these registers.  Nested 
+@                                               @   interrupt processing does need to save
+@                                               @   these registers.
+@
+@    /* Save the current stack pointer in the thread's control block.  */
+@    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp; 
+@
+@    /* Switch to the system stack.  */
+@    sp =  _tx_thread_system_stack_ptr; 
+@
+    MOV     r10, #0                             @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                                @ Save ISR lr
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
+    POP     {lr}                                @ Recover ISR lr
+#endif
+
+    B       __tx_fiq_processing_return          @ Continue FIQ processing 
+@
+@   }
+@   else
+@   {
+@
+__tx_thread_fiq_idle_system_save:
+@
+@    /* Interrupt occurred in the scheduling loop.  */
+@
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                                @ Save ISR lr
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
+    POP     {lr}                                @ Recover ISR lr
+#endif
+@
+@    /* Not much to do here, save the current SPSR and LR for possible
+@       use in IRQ interrupted in idle system conditions, and return to 
+@       FIQ interrupt processing.  */
+@
+    MRS     r0, SPSR                            @ Pickup saved SPSR
+    SUB     lr, lr, #4                          @ Adjust point of interrupt 
+    STMDB   sp!, {r0, lr}                       @ Store other registers that will get used
+@                                               @   or stripped off the stack in context 
+@                                               @   restore 
+    B       __tx_fiq_processing_return          @ Continue FIQ processing  
+@
+@    }
+@}  
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S
new file mode 100644
index 00000000..d3e4972a
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_end.S
@@ -0,0 +1,116 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+#ifdef TX_ENABLE_FIQ_SUPPORT
+DISABLE_INTS    =       0xC0                    @ Disable IRQ/FIQ interrupts
+#else
+DISABLE_INTS    =       0x80                    @ Disable IRQ interrupts
+#endif
+MODE_MASK       =       0x1F                    @ Mode mask 
+FIQ_MODE_BITS   =       0x11                    @ FIQ mode bits
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end
+@   since it will never be called 16-bit mode.  */
+@
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_fiq_nesting_end                        Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is called by the application from FIQ mode after      */ 
+@/*    _tx_thread_fiq_nesting_start has been called and switches the FIQ   */ 
+@/*    processing from system mode back to FIQ mode prior to the ISR       */ 
+@/*    calling _tx_thread_fiq_context_restore.  Note that this function    */ 
+@/*    assumes the system stack pointer is in the same position after      */ 
+@/*    nesting start function was called.                                  */ 
+@/*                                                                        */ 
+@/*    This function assumes that the system mode stack pointer was setup  */ 
+@/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+@/*                                                                        */ 
+@/*    This function returns with FIQ interrupts disabled.                 */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                                                */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_fiq_nesting_end(VOID)
+@{
+    .global  _tx_thread_fiq_nesting_end
+    .type    _tx_thread_fiq_nesting_end,function
+_tx_thread_fiq_nesting_end:
+    MOV     r3,lr                               @ Save ISR return address
+    MRS     r0, CPSR                            @ Pickup the CPSR
+    ORR     r0, r0, #DISABLE_INTS               @ Build disable interrupt value
+    MSR     CPSR_c, r0                          @ Disable interrupts
+    LDMIA   sp!, {r1, lr}                       @ Pickup saved lr (and r1 throw-away for 
+                                                @   8-byte alignment logic)
+    BIC     r0, r0, #MODE_MASK                  @ Clear mode bits
+    ORR     r0, r0, #FIQ_MODE_BITS              @ Build IRQ mode CPSR
+    MSR     CPSR_c, r0                          @ Reenter IRQ mode
+
+#ifdef __THUMB_INTERWORK
+    BX      r3                                  @ Return to caller
+#else
+    MOV     pc, r3                              @ Return to caller
+#endif
+@}
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S
new file mode 100644
index 00000000..0b2ef7e0
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_fiq_nesting_start.S
@@ -0,0 +1,108 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+FIQ_DISABLE     =       0x40                    @ FIQ disable bit
+MODE_MASK       =       0x1F                    @ Mode mask
+SYS_MODE_BITS   =       0x1F                    @ System mode bits
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start
+@   since it will never be called 16-bit mode.  */
+@
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_fiq_nesting_start                      Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is called by the application from FIQ mode after      */ 
+@/*    _tx_thread_fiq_context_save has been called and switches the FIQ    */ 
+@/*    processing to the system mode so nested FIQ interrupt processing    */ 
+@/*    is possible (system mode has its own "lr" register).  Note that     */ 
+@/*    this function assumes that the system mode stack pointer was setup  */ 
+@/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+@/*                                                                        */ 
+@/*    This function returns with FIQ interrupts enabled.                  */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                                                */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_fiq_nesting_start(VOID)
+@{
+    .global  _tx_thread_fiq_nesting_start
+    .type    _tx_thread_fiq_nesting_start,function
+_tx_thread_fiq_nesting_start:
+    MOV     r3,lr                               @ Save ISR return address
+    MRS     r0, CPSR                            @ Pickup the CPSR
+    BIC     r0, r0, #MODE_MASK                  @ Clear the mode bits
+    ORR     r0, r0, #SYS_MODE_BITS              @ Build system mode CPSR
+    MSR     CPSR_c, r0                          @ Enter system mode
+    STMDB   sp!, {r1, lr}                       @ Push the system mode lr on the system mode stack
+                                                @   and push r1 just to keep 8-byte alignment
+    BIC     r0, r0, #FIQ_DISABLE                @ Build enable FIQ CPSR
+    MSR     CPSR_c, r0                          @ Enter system mode
+#ifdef __THUMB_INTERWORK
+    BX      r3                                  @ Return to caller
+#else
+    MOV     pc, r3                              @ Return to caller
+#endif
+@}
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S
new file mode 100644
index 00000000..ac10ca1e
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_interrupt_control.S
@@ -0,0 +1,115 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"  */
+@
+
+INT_MASK        =   0x03F
+
+@
+@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for
+@   applications calling this function from to 16-bit Thumb mode.  */
+@
+    .text
+    .align 2
+    .global $_tx_thread_interrupt_control
+$_tx_thread_interrupt_control:
+        .thumb
+     BX        pc                               @ Switch to 32-bit mode
+     NOP                                        @ 
+    .arm
+     STMFD     sp!, {lr}                        @ Save return address
+     BL        _tx_thread_interrupt_control     @ Call _tx_thread_interrupt_control function
+     LDMFD     sp!, {lr}                        @ Recover saved return address
+     BX        lr                               @ Return to 16-bit caller
+@
+@
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_interrupt_control                      Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is responsible for changing the interrupt lockout     */ 
+@/*    posture of the system.                                              */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    new_posture                           New interrupt lockout posture */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    old_posture                           Old interrupt lockout posture */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    Application Code                                                    */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@UINT   _tx_thread_interrupt_control(UINT new_posture)
+@{
+    .global _tx_thread_interrupt_control
+    .type   _tx_thread_interrupt_control,function
+_tx_thread_interrupt_control:
+@
+@    /* Pickup current interrupt lockout posture.  */
+@
+    MRS     r3, CPSR                    @ Pickup current CPSR
+    MOV     r2, #INT_MASK               @ Build interrupt mask
+    AND     r1, r3, r2                  @ Clear interrupt lockout bits
+    ORR     r1, r1, r0                  @ Or-in new interrupt lockout bits
+@
+@    /* Apply the new interrupt posture.  */
+@
+    MSR     CPSR_c, r1                  @ Setup new CPSR
+    BIC     r0, r3, r2                  @ Return previous interrupt mask
+#ifdef __THUMB_INTERWORK
+    BX      lr                          @ Return to caller
+#else
+    MOV     pc, lr                      @ Return to caller
+#endif
+@}
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S
new file mode 100644
index 00000000..dd2ba781
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_interrupt_disable.S
@@ -0,0 +1,113 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for
+@   applications calling this function from to 16-bit Thumb mode.  */
+@
+    .text
+    .align 2
+    .global $_tx_thread_interrupt_disable
+$_tx_thread_interrupt_disable:
+        .thumb
+     BX        pc                               @ Switch to 32-bit mode
+     NOP                                        @ 
+    .arm
+     STMFD     sp!, {lr}                        @ Save return address
+     BL        _tx_thread_interrupt_disable     @ Call _tx_thread_interrupt_disable function
+     LDMFD     sp!, {lr}                        @ Recover saved return address
+     BX        lr                               @ Return to 16-bit caller
+@
+@
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_interrupt_disable                      Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is responsible for disabling interrupts               */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    old_posture                           Old interrupt lockout posture */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    Application Code                                                    */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@UINT   _tx_thread_interrupt_disable(void)
+@{
+    .global _tx_thread_interrupt_disable
+    .type   _tx_thread_interrupt_disable,function
+_tx_thread_interrupt_disable:
+@
+@    /* Pickup current interrupt lockout posture.  */
+@
+    MRS     r0, CPSR                            @ Pickup current CPSR
+@
+@    /* Mask interrupts.  */
+@
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  @ Disable IRQ and FIQ
+#else
+    CPSID   i                                   @ Disable IRQ 
+#endif
+
+#ifdef __THUMB_INTERWORK
+    BX      lr                                  @ Return to caller
+#else
+    MOV     pc, lr                              @ Return to caller
+#endif
+@}
+
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S
new file mode 100644
index 00000000..885b43c8
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_interrupt_restore.S
@@ -0,0 +1,104 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for
+@   applications calling this function from to 16-bit Thumb mode.  */
+@
+    .text
+    .align 2
+    .global $_tx_thread_interrupt_restore
+$_tx_thread_interrupt_restore:
+        .thumb
+     BX        pc                               @ Switch to 32-bit mode
+     NOP                                        @ 
+    .arm
+     STMFD     sp!, {lr}                        @ Save return address
+     BL        _tx_thread_interrupt_restore     @ Call _tx_thread_interrupt_restore function
+     LDMFD     sp!, {lr}                        @ Recover saved return address
+     BX        lr                               @ Return to 16-bit caller
+@
+@
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_interrupt_restore                      Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is responsible for restoring interrupts to the state  */
+@/*    returned by a previous _tx_thread_interrupt_disable call.           */
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    old_posture                           Old interrupt lockout posture */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    Application Code                                                    */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@UINT   _tx_thread_interrupt_restore(UINT old_posture)
+@{
+    .global  _tx_thread_interrupt_restore
+    .type    _tx_thread_interrupt_restore,function
+_tx_thread_interrupt_restore:
+@
+@    /* Apply the new interrupt posture.  */
+@
+    MSR     CPSR_c, r0                          @ Setup new CPSR
+#ifdef __THUMB_INTERWORK
+    BX      lr                                  @ Return to caller
+#else
+    MOV     pc, lr                              @ Return to caller
+#endif
+@}
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S
new file mode 100644
index 00000000..8d1d1952
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_end.S
@@ -0,0 +1,115 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+#ifdef TX_ENABLE_FIQ_SUPPORT
+DISABLE_INTS    =       0xC0                    @ Disable IRQ/FIQ interrupts
+#else
+DISABLE_INTS    =       0x80                    @ Disable IRQ interrupts
+#endif
+MODE_MASK       =       0x1F                    @ Mode mask 
+IRQ_MODE_BITS   =       0x12                    @ IRQ mode bits
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end
+@   since it will never be called 16-bit mode.  */
+@
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_irq_nesting_end                        Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is called by the application from IRQ mode after      */ 
+@/*    _tx_thread_irq_nesting_start has been called and switches the IRQ   */ 
+@/*    processing from system mode back to IRQ mode prior to the ISR       */ 
+@/*    calling _tx_thread_context_restore.  Note that this function        */ 
+@/*    assumes the system stack pointer is in the same position after      */ 
+@/*    nesting start function was called.                                  */ 
+@/*                                                                        */ 
+@/*    This function assumes that the system mode stack pointer was setup  */ 
+@/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+@/*                                                                        */ 
+@/*    This function returns with IRQ interrupts disabled.                 */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                                                */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_irq_nesting_end(VOID)
+@{
+    .global  _tx_thread_irq_nesting_end
+    .type    _tx_thread_irq_nesting_end,function
+_tx_thread_irq_nesting_end:
+    MOV     r3,lr                               @ Save ISR return address
+    MRS     r0, CPSR                            @ Pickup the CPSR
+    ORR     r0, r0, #DISABLE_INTS               @ Build disable interrupt value
+    MSR     CPSR_c, r0                          @ Disable interrupts
+    LDMIA   sp!, {r1, lr}                       @ Pickup saved lr (and r1 throw-away for 
+                                                @   8-byte alignment logic)
+    BIC     r0, r0, #MODE_MASK                  @ Clear mode bits
+    ORR     r0, r0, #IRQ_MODE_BITS              @ Build IRQ mode CPSR
+    MSR     CPSR_c, r0                          @ Reenter IRQ mode
+#ifdef __THUMB_INTERWORK
+    BX      r3                                  @ Return to caller
+#else
+    MOV     pc, r3                              @ Return to caller
+#endif
+@}
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S
new file mode 100644
index 00000000..e2d38c62
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_irq_nesting_start.S
@@ -0,0 +1,108 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+IRQ_DISABLE     =       0x80                    @ IRQ disable bit
+MODE_MASK       =       0x1F                    @ Mode mask
+SYS_MODE_BITS   =       0x1F                    @ System mode bits
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start
+@   since it will never be called 16-bit mode.  */
+@
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_irq_nesting_start                      Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is called by the application from IRQ mode after      */ 
+@/*    _tx_thread_context_save has been called and switches the IRQ        */ 
+@/*    processing to the system mode so nested IRQ interrupt processing    */ 
+@/*    is possible (system mode has its own "lr" register).  Note that     */ 
+@/*    this function assumes that the system mode stack pointer was setup  */ 
+@/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+@/*                                                                        */ 
+@/*    This function returns with IRQ interrupts enabled.                  */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                                                */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_irq_nesting_start(VOID)
+@{
+    .global  _tx_thread_irq_nesting_start
+    .type    _tx_thread_irq_nesting_start,function
+_tx_thread_irq_nesting_start:
+    MOV     r3,lr                               @ Save ISR return address
+    MRS     r0, CPSR                            @ Pickup the CPSR
+    BIC     r0, r0, #MODE_MASK                  @ Clear the mode bits
+    ORR     r0, r0, #SYS_MODE_BITS              @ Build system mode CPSR
+    MSR     CPSR_c, r0                          @ Enter system mode
+    STMDB   sp!, {r1, lr}                       @ Push the system mode lr on the system mode stack
+                                                @   and push r1 just to keep 8-byte alignment
+    BIC     r0, r0, #IRQ_DISABLE                @ Build enable IRQ CPSR
+    MSR     CPSR_c, r0                          @ Enter system mode
+#ifdef __THUMB_INTERWORK
+    BX      r3                                  @ Return to caller
+#else
+    MOV     pc, r3                              @ Return to caller
+#endif
+@}
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_schedule.S b/ports/cortex_r5/gnu/src/tx_thread_schedule.S
new file mode 100644
index 00000000..e62fc22c
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_schedule.S
@@ -0,0 +1,250 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@#include "tx_timer.h"
+@
+@
+    .global     _tx_thread_execute_ptr
+    .global     _tx_thread_current_ptr
+    .global     _tx_timer_time_slice
+    .global     _tx_execution_thread_enter
+@
+@
+@/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for
+@   applications calling this function from to 16-bit Thumb mode.  */
+@
+    .text
+    .align  2
+    .global $_tx_thread_schedule
+    .type   $_tx_thread_schedule,function
+$_tx_thread_schedule:
+         .thumb
+     BX        pc                                   @ Switch to 32-bit mode
+     NOP                                            @ 
+    .arm
+     STMFD     sp!, {lr}                            @ Save return address
+     BL        _tx_thread_schedule                  @ Call _tx_thread_schedule function
+     LDMFD     sp!, {lr}                            @ Recover saved return address
+     BX        lr                                   @ Return to 16-bit caller
+@
+@
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_schedule                               Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function waits for a thread control block pointer to appear in */ 
+@/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */ 
+@/*    in the variable, the corresponding thread is resumed.               */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    _tx_initialize_kernel_enter          ThreadX entry function         */ 
+@/*    _tx_thread_system_return             Return to system from thread   */ 
+@/*    _tx_thread_context_restore           Restore thread's context       */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_schedule(VOID)
+@{
+    .global _tx_thread_schedule
+        .type  _tx_thread_schedule,function
+_tx_thread_schedule:
+@
+@    /* Enable interrupts.  */
+@
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSIE   if                                  @ Enable IRQ and FIQ interrupts
+#else
+    CPSIE   i                                   @ Enable IRQ interrupts
+#endif
+@
+@    /* Wait for a thread to execute.  */
+@    do
+@    {
+    LDR     r1, =_tx_thread_execute_ptr         @ Address of thread execute ptr
+@
+__tx_thread_schedule_loop:
+@
+    LDR     r0, [r1]                            @ Pickup next thread to execute
+    CMP     r0, #0                              @ Is it NULL?
+    BEQ     __tx_thread_schedule_loop           @ If so, keep looking for a thread
+@
+@    }
+@    while(_tx_thread_execute_ptr == TX_NULL);
+@    
+@    /* Yes! We have a thread to execute.  Lockout interrupts and
+@       transfer control to it.  */
+@
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  @ Disable IRQ and FIQ interrupts
+#else
+    CPSID   i                                   @ Disable IRQ interrupts
+#endif
+@
+@    /* Setup the current thread pointer.  */
+@    _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+@
+    LDR     r1, =_tx_thread_current_ptr         @ Pickup address of current thread 
+    STR     r0, [r1]                            @ Setup current thread pointer
+@
+@    /* Increment the run count for this thread.  */
+@    _tx_thread_current_ptr -> tx_thread_run_count++;
+@
+    LDR     r2, [r0, #4]                        @ Pickup run counter
+    LDR     r3, [r0, #24]                       @ Pickup time-slice for this thread
+    ADD     r2, r2, #1                          @ Increment thread run-counter
+    STR     r2, [r0, #4]                        @ Store the new run counter
+@
+@    /* Setup time-slice, if present.  */
+@    _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+@
+    LDR     r2, =_tx_timer_time_slice           @ Pickup address of time-slice 
+                                                @   variable
+    LDR     sp, [r0, #8]                        @ Switch stack pointers
+    STR     r3, [r2]                            @ Setup time-slice
+@
+@    /* Switch to the thread's stack.  */
+@    sp =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;
+@
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the thread entry function to indicate the thread is executing.  */
+@
+    BL      _tx_execution_thread_enter      @ Call the thread execution enter function
+#endif
+@
+@    /* Determine if an interrupt frame or a synchronous task suspension frame
+@   is present.  */
+@
+    LDMIA   sp!, {r4, r5}                       @ Pickup the stack type and saved CPSR
+    CMP     r4, #0                              @ Check for synchronous context switch
+    BEQ     _tx_solicited_return
+    MSR     SPSR_cxsf, r5                       @ Setup SPSR for return
+#ifdef TX_ENABLE_VFP_SUPPORT
+    LDR     r1, [r0, #144]                      @ Pickup the VFP enabled flag
+    CMP     r1, #0                              @ Is the VFP enabled?
+    BEQ     _tx_skip_interrupt_vfp_restore      @ No, skip VFP interrupt restore
+    VLDMIA  sp!, {D0-D15}                       @ Recover D0-D15
+    LDR     r4, [sp], #4                        @ Pickup FPSCR
+    VMSR    FPSCR, r4                           @ Restore FPSCR
+_tx_skip_interrupt_vfp_restore:
+#endif
+    LDMIA   sp!, {r0-r12, lr, pc}^              @ Return to point of thread interrupt
+@
+_tx_solicited_return:
+#ifdef TX_ENABLE_VFP_SUPPORT
+    LDR     r1, [r0, #144]                      @ Pickup the VFP enabled flag
+    CMP     r1, #0                              @ Is the VFP enabled?
+    BEQ     _tx_skip_solicited_vfp_restore      @ No, skip VFP solicited restore
+    VLDMIA  sp!, {D8-D15}                       @ Recover D8-D15
+    LDR     r4, [sp], #4                        @ Pickup FPSCR
+    VMSR    FPSCR, r4                           @ Restore FPSCR
+_tx_skip_solicited_vfp_restore:
+#endif
+    MOV     r0, r5                              @ Move CPSR to scratch register
+    LDMIA   sp!, {r4-r11, lr}                   @ Return to thread synchronously
+    MSR     CPSR_cxsf, r0                       @ Recover CPSR
+@
+#ifdef __THUMB_INTERWORK
+    BX      lr                                  @ Return to caller
+#else
+    MOV     pc, lr                              @ Return to caller
+#endif
+@
+@}
+@
+@
+#ifdef TX_ENABLE_VFP_SUPPORT
+    .global tx_thread_vfp_enable
+    .type  tx_thread_vfp_enable,function
+tx_thread_vfp_enable:
+    MRS     r2, CPSR                            @ Pickup the CPSR
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  @ Disable IRQ and FIQ interrupts
+#else
+    CPSID   i                                   @ Disable IRQ interrupts
+#endif
+    LDR     r0, =_tx_thread_current_ptr         @ Build current thread pointer address
+    LDR     r1, [r0]                            @ Pickup current thread pointer
+    CMP     r1, #0                              @ Check for NULL thread pointer
+    BEQ     __tx_no_thread_to_enable            @ If NULL, skip VFP enable
+    MOV     r0, #1                              @ Build enable value
+    STR     r0, [r1, #144]                      @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
+__tx_no_thread_to_enable:
+    MSR     CPSR_cxsf, r2                       @ Recover CPSR
+    BX      LR                                  @ Return to caller
+@
+    .global tx_thread_vfp_disable
+    .type  tx_thread_vfp_disable,function
+tx_thread_vfp_disable:
+    MRS     r2, CPSR                            @ Pickup the CPSR
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  @ Disable IRQ and FIQ interrupts
+#else
+    CPSID   i                                   @ Disable IRQ interrupts
+#endif
+    LDR     r0, =_tx_thread_current_ptr         @ Build current thread pointer address
+    LDR     r1, [r0]                            @ Pickup current thread pointer
+    CMP     r1, #0                              @ Check for NULL thread pointer
+    BEQ     __tx_no_thread_to_disable           @ If NULL, skip VFP disable
+    MOV     r0, #0                              @ Build disable value
+    STR     r0, [r1, #144]                      @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
+__tx_no_thread_to_disable:
+    MSR     CPSR_cxsf, r2                       @ Recover CPSR
+    BX      LR                                  @ Return to caller
+#endif
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_stack_build.S b/ports/cortex_r5/gnu/src/tx_thread_stack_build.S
new file mode 100644
index 00000000..bed62a6d
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_stack_build.S
@@ -0,0 +1,178 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+    .arm
+
+SVC_MODE        =       0x13                    @ SVC mode
+#ifdef TX_ENABLE_FIQ_SUPPORT
+CPSR_MASK       =       0xDF                    @ Mask initial CPSR, IRQ & FIQ interrupts enabled
+#else
+CPSR_MASK       =       0x9F                    @ Mask initial CPSR, IRQ interrupts enabled
+#endif
+@
+@
+@/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for
+@   applications calling this function from to 16-bit Thumb mode.  */
+@
+    .text
+    .align 2
+    .thumb
+    .global $_tx_thread_stack_build
+    .type    $_tx_thread_stack_build,function
+$_tx_thread_stack_build:
+     BX        pc                               @ Switch to 32-bit mode
+     NOP                                        @ 
+    .arm
+     STMFD     sp!, {lr}                        @ Save return address
+     BL        _tx_thread_stack_build           @ Call _tx_thread_stack_build function
+     LDMFD     sp!, {lr}                        @ Recover saved return address
+     BX        lr                               @ Return to 16-bit caller
+@
+@
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_stack_build                            Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function builds a stack frame on the supplied thread's stack.  */
+@/*    The stack frame results in a fake interrupt return to the supplied  */
+@/*    function pointer.                                                   */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    thread_ptr                            Pointer to thread control blk */
+@/*    function_ptr                          Pointer to return function    */
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    _tx_thread_create                     Create thread service         */
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+@{
+    .global  _tx_thread_stack_build
+    .type    _tx_thread_stack_build,function
+_tx_thread_stack_build:
+@
+@       
+@    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+@       on the ARM9 should look like the following after it is built:
+@       
+@       Stack Top:      1           Interrupt stack frame type
+@                       CPSR        Initial value for CPSR
+@                       a1 (r0)     Initial value for a1
+@                       a2 (r1)     Initial value for a2
+@                       a3 (r2)     Initial value for a3
+@                       a4 (r3)     Initial value for a4
+@                       v1 (r4)     Initial value for v1
+@                       v2 (r5)     Initial value for v2
+@                       v3 (r6)     Initial value for v3
+@                       v4 (r7)     Initial value for v4
+@                       v5 (r8)     Initial value for v5
+@                       sb (r9)     Initial value for sb
+@                       sl (r10)    Initial value for sl
+@                       fp (r11)    Initial value for fp
+@                       ip (r12)    Initial value for ip
+@                       lr (r14)    Initial value for lr
+@                       pc (r15)    Initial value for pc
+@                       0       For stack backtracing
+@
+@    Stack Bottom: (higher memory address)  */
+@
+    LDR     r2, [r0, #16]                   @ Pickup end of stack area
+    BIC     r2, r2, #7                      @ Ensure 8-byte alignment
+    SUB     r2, r2, #76                     @ Allocate space for the stack frame
+@
+@    /* Actually build the stack frame.  */
+@
+    MOV     r3, #1                          @ Build interrupt stack type
+    STR     r3, [r2, #0]                    @ Store stack type
+    MOV     r3, #0                          @ Build initial register value
+    STR     r3, [r2, #8]                    @ Store initial r0
+    STR     r3, [r2, #12]                   @ Store initial r1
+    STR     r3, [r2, #16]                   @ Store initial r2
+    STR     r3, [r2, #20]                   @ Store initial r3
+    STR     r3, [r2, #24]                   @ Store initial r4
+    STR     r3, [r2, #28]                   @ Store initial r5
+    STR     r3, [r2, #32]                   @ Store initial r6
+    STR     r3, [r2, #36]                   @ Store initial r7
+    STR     r3, [r2, #40]                   @ Store initial r8
+    STR     r3, [r2, #44]                   @ Store initial r9
+    LDR     r3, [r0, #12]                   @ Pickup stack starting address
+    STR     r3, [r2, #48]                   @ Store initial r10 (sl)
+    LDR     r3,=_tx_thread_schedule         @ Pickup address of _tx_thread_schedule for GDB backtrace
+    STR     r3, [r2, #60]                   @ Store initial r14 (lr)
+    MOV     r3, #0                          @ Build initial register value
+    STR     r3, [r2, #52]                   @ Store initial r11
+    STR     r3, [r2, #56]                   @ Store initial r12
+    STR     r1, [r2, #64]                   @ Store initial pc
+    STR     r3, [r2, #68]                   @ 0 for back-trace
+    MRS     r1, CPSR                        @ Pickup CPSR
+    BIC     r1, r1, #CPSR_MASK              @ Mask mode bits of CPSR
+    ORR     r3, r1, #SVC_MODE               @ Build CPSR, SVC mode, interrupts enabled
+    STR     r3, [r2, #4]                    @ Store initial CPSR
+@
+@    /* Setup stack pointer.  */
+@    thread_ptr -> tx_thread_stack_ptr =  r2;
+@
+    STR     r2, [r0, #8]                    @ Save stack pointer in thread's
+                                            @   control block
+#ifdef __THUMB_INTERWORK
+    BX      lr                              @ Return to caller
+#else
+    MOV     pc, lr                          @ Return to caller
+#endif
+@}
+
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_system_return.S b/ports/cortex_r5/gnu/src/tx_thread_system_return.S
new file mode 100644
index 00000000..c7c551a5
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_system_return.S
@@ -0,0 +1,177 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@#include "tx_timer.h"
+@
+    .arm
+@
+@
+    .global     _tx_thread_current_ptr
+    .global     _tx_timer_time_slice
+    .global     _tx_thread_schedule
+    .global     _tx_execution_thread_exit
+@
+@
+@
+@/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for
+@   applications calling this function from to 16-bit Thumb mode.  */
+@
+    .text
+    .align  2
+    .global $_tx_thread_system_return
+    .type   $_tx_thread_system_return,function
+$_tx_thread_system_return:
+    .thumb
+     BX        pc                               @ Switch to 32-bit mode
+     NOP                                        @ 
+    .arm
+     STMFD     sp!, {lr}                        @ Save return address
+     BL        _tx_thread_system_return         @ Call _tx_thread_system_return function
+     LDMFD     sp!, {lr}                        @ Recover saved return address
+     BX        lr                               @ Return to 16-bit caller
+@
+@
+    .text
+    .align  2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_system_return                          Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is target processor specific.  It is used to transfer */ 
+@/*    control from a thread back to the ThreadX system.  Only a           */ 
+@/*    minimal context is saved since the compiler assumes temp registers  */ 
+@/*    are going to get slicked by a function call anyway.                 */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    _tx_thread_schedule                   Thread scheduling loop        */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ThreadX components                                                  */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_system_return(VOID)
+@{
+    .global _tx_thread_system_return
+    .type   _tx_thread_system_return,function
+_tx_thread_system_return:
+@
+@   /* Lockout interrupts.  */
+@
+    MRS     r1, CPSR                            @ Pickup the CPSR
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  @ Disable IRQ and FIQ interrupts
+#else
+    CPSID   i                                   @ Disable IRQ interrupts
+#endif
+@    /* Save minimal context on the stack.  */
+@
+    STMDB   sp!, {r4-r11, lr}                   @ Save minimal context
+    LDR     r5, =_tx_thread_current_ptr         @ Pickup address of current ptr
+    LDR     r6, [r5, #0]                        @ Pickup current thread pointer
+@
+#ifdef TX_ENABLE_VFP_SUPPORT
+    LDR     r0, [r6, #144]                      @ Pickup the VFP enabled flag
+    CMP     r0, #0                              @ Is the VFP enabled?
+    BEQ     _tx_skip_solicited_vfp_save         @ No, skip VFP solicited save
+    VMRS    r4, FPSCR                           @ Pickup the FPSCR
+    STR     r4, [sp, #-4]!                      @ Save FPSCR
+    VSTMDB  sp!, {D8-D15}                       @ Save D8-D15
+_tx_skip_solicited_vfp_save:
+#endif
+@
+    MOV     r0, #0                              @ Build a solicited stack type
+    STMDB   sp!, {r0-r1}                        @ Save type and CPSR
+@   
+@
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the thread exit function to indicate the thread is no longer executing.  */
+@
+    BL      _tx_execution_thread_exit           @ Call the thread exit function
+#endif
+@
+    LDR     r2, =_tx_timer_time_slice           @ Pickup address of time slice
+    LDR     r1, [r2, #0]                        @ Pickup current time slice
+@
+@    /* Save current stack and switch to system stack.  */
+@    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+@    sp = _tx_thread_system_stack_ptr;
+@
+    STR     sp, [r6, #8]                        @ Save thread stack pointer
+@
+@    /* Determine if the time-slice is active.  */
+@    if (_tx_timer_time_slice)
+@    {
+@
+    MOV     r4, #0                              @ Build clear value
+    CMP     r1, #0                              @ Is a time-slice active?
+    BEQ     __tx_thread_dont_save_ts            @ No, don't save the time-slice
+@
+@       /* Save time-slice for the thread and clear the current time-slice.  */
+@       _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+@       _tx_timer_time_slice =  0;
+@
+    STR     r4, [r2, #0]                        @ Clear time-slice
+    STR     r1, [r6, #24]                       @ Save current time-slice
+@
+@    }
+__tx_thread_dont_save_ts:
+@
+@    /* Clear the current thread pointer.  */
+@    _tx_thread_current_ptr =  TX_NULL;
+@
+    STR     r4, [r5, #0]                        @ Clear current thread pointer
+    B       _tx_thread_schedule                 @ Jump to scheduler!
+@
+@}
+
diff --git a/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S
new file mode 100644
index 00000000..3d99f69f
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_thread_vectored_context_save.S
@@ -0,0 +1,190 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+    .global     _tx_thread_system_state
+    .global     _tx_thread_current_ptr
+    .global     _tx_execution_isr_enter
+@
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save
+@   since it will never be called 16-bit mode.  */
+@ 
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_vectored_context_save                  Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function saves the context of an executing thread in the       */ 
+@/*    beginning of interrupt processing.  The function also ensures that  */ 
+@/*    the system stack is used upon return to the calling ISR.            */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                                                */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID  _tx_thread_vectored_context_save(VOID)
+@{
+    .global  _tx_thread_vectored_context_save
+    .type    _tx_thread_vectored_context_save,function
+_tx_thread_vectored_context_save:
+@
+@    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+@       out, we are in IRQ mode, and all registers are intact.  */
+@
+@    /* Check for a nested interrupt condition.  */
+@    if (_tx_thread_system_state++)
+@    {
+@
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  @ Disable IRQ and FIQ interrupts
+#endif
+    LDR     r3, =_tx_thread_system_state        @ Pickup address of system state variable
+    LDR     r2, [r3, #0]                        @ Pickup system state
+    CMP     r2, #0                              @ Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         @ Yes, not a nested context save
+@
+@    /* Nested interrupt condition.  */
+@
+    ADD     r2, r2, #1                          @ Increment the interrupt counter
+    STR     r2, [r3, #0]                        @ Store it back in the variable
+@
+@    /* Note: Minimal context of interrupted thread is already saved.  */
+@
+@    /* Return to the ISR.  */
+@
+    MOV     r10, #0                             @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                                @ Save ISR lr
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
+    POP     {lr}                                @ Recover ISR lr
+#endif
+
+    MOV     pc, lr                              @ Return to caller
+@
+__tx_thread_not_nested_save:
+@    }
+@
+@    /* Otherwise, not nested, check to see if a thread was running.  */
+@    else if (_tx_thread_current_ptr)
+@    {
+@
+    ADD     r2, r2, #1                          @ Increment the interrupt counter
+    STR     r2, [r3, #0]                        @ Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         @ Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        @ Pickup current thread pointer
+    CMP     r0, #0                              @ Is it NULL?
+    BEQ     __tx_thread_idle_system_save        @ If so, interrupt occurred in 
+                                                @   scheduling loop - nothing needs saving!
+@
+@    /* Note: Minimal context of interrupted thread is already saved.  */
+@
+@    /* Save the current stack pointer in the thread's control block.  */
+@    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+@
+@    /* Switch to the system stack.  */
+@    sp =  _tx_thread_system_stack_ptr;
+@
+    MOV     r10, #0                             @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                                @ Save ISR lr
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
+    POP     {lr}                                @ Recover ISR lr
+#endif
+
+    MOV     pc, lr                              @ Return to caller
+@
+@    }
+@    else
+@    {
+@
+__tx_thread_idle_system_save:
+@
+@    /* Interrupt occurred in the scheduling loop.  */
+@
+@    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+@       processing.  */
+@
+    MOV     r10, #0                             @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                                @ Save ISR lr
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
+    POP     {lr}                                @ Recover ISR lr
+#endif
+
+    ADD     sp, sp, #32                         @ Recover saved registers
+    MOV     pc, lr                              @ Return to caller
+@
+@    }
+@}
+
diff --git a/ports/cortex_r5/gnu/src/tx_timer_interrupt.S b/ports/cortex_r5/gnu/src/tx_timer_interrupt.S
new file mode 100644
index 00000000..050258bd
--- /dev/null
+++ b/ports/cortex_r5/gnu/src/tx_timer_interrupt.S
@@ -0,0 +1,279 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Timer                                                               */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_timer.h"
+@#include "tx_thread.h"
+@
+@
+    .arm
+
+@
+@/* Define Assembly language external references...  */
+@
+    .global     _tx_timer_time_slice
+    .global     _tx_timer_system_clock
+    .global     _tx_timer_current_ptr
+    .global     _tx_timer_list_start
+    .global     _tx_timer_list_end
+    .global     _tx_timer_expired_time_slice
+    .global     _tx_timer_expired
+    .global     _tx_thread_time_slice
+@
+@
+@
+@/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for
+@   applications calling this function from to 16-bit Thumb mode.  */
+@
+    .text
+    .align 2
+    .thumb
+    .global $_tx_timer_interrupt
+    .type   $_tx_timer_interrupt,function
+$_tx_timer_interrupt:
+     BX        pc                               @ Switch to 32-bit mode
+     NOP                                        @ 
+    .arm
+     STMFD     sp!, {lr}                        @ Save return address
+     BL        _tx_timer_interrupt              @ Call _tx_timer_interrupt function
+     LDMFD     sp!, {lr}                        @ Recover saved return address
+     BX        lr                               @ Return to 16-bit caller
+@
+@
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_timer_interrupt                               Cortex-R5/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function processes the hardware timer interrupt.  This         */ 
+@/*    processing includes incrementing the system clock and checking for  */ 
+@/*    time slice and/or timer expiration.  If either is found, the        */ 
+@/*    interrupt context save/restore functions are called along with the  */ 
+@/*    expiration functions.                                               */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    _tx_thread_time_slice                 Time slice interrupted thread */ 
+@/*    _tx_timer_expiration_process          Timer expiration processing   */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    interrupt vector                                                    */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_timer_interrupt(VOID)
+@{
+    .global _tx_timer_interrupt
+    .type   _tx_timer_interrupt,function
+_tx_timer_interrupt:
+@
+@    /* Upon entry to this routine, it is assumed that context save has already
+@       been called, and therefore the compiler scratch registers are available
+@       for use.  */
+@
+@    /* Increment the system clock.  */
+@    _tx_timer_system_clock++;
+@
+    LDR     r1, =_tx_timer_system_clock         @ Pickup address of system clock
+    LDR     r0, [r1]                            @ Pickup system clock
+    ADD     r0, r0, #1                          @ Increment system clock
+    STR     r0, [r1]                            @ Store new system clock
+@
+@    /* Test for time-slice expiration.  */
+@    if (_tx_timer_time_slice)
+@    {
+@
+    LDR     r3, =_tx_timer_time_slice           @ Pickup address of time-slice 
+    LDR     r2, [r3]                            @ Pickup time-slice
+    CMP     r2, #0                              @ Is it non-active?
+    BEQ     __tx_timer_no_time_slice            @ Yes, skip time-slice processing
+@
+@       /* Decrement the time_slice.  */
+@       _tx_timer_time_slice--;
+@
+    SUB     r2, r2, #1                          @ Decrement the time-slice
+    STR     r2, [r3]                            @ Store new time-slice value
+@
+@       /* Check for expiration.  */
+@       if (__tx_timer_time_slice == 0)
+@
+    CMP     r2, #0                              @ Has it expired?
+    BNE     __tx_timer_no_time_slice            @ No, skip expiration processing
+@
+@       /* Set the time-slice expired flag.  */
+@       _tx_timer_expired_time_slice =  TX_TRUE;
+@
+    LDR     r3, =_tx_timer_expired_time_slice   @ Pickup address of expired flag
+    MOV     r0, #1                              @ Build expired value
+    STR     r0, [r3]                            @ Set time-slice expiration flag
+@
+@    }
+@
+__tx_timer_no_time_slice:
+@
+@    /* Test for timer expiration.  */
+@    if (*_tx_timer_current_ptr)
+@    {
+@
+    LDR     r1, =_tx_timer_current_ptr          @ Pickup current timer pointer address
+    LDR     r0, [r1]                            @ Pickup current timer
+    LDR     r2, [r0]                            @ Pickup timer list entry
+    CMP     r2, #0                              @ Is there anything in the list?
+    BEQ     __tx_timer_no_timer                 @ No, just increment the timer
+@
+@        /* Set expiration flag.  */
+@        _tx_timer_expired =  TX_TRUE;
+@
+    LDR     r3, =_tx_timer_expired              @ Pickup expiration flag address
+    MOV     r2, #1                              @ Build expired value
+    STR     r2, [r3]                            @ Set expired flag
+    B       __tx_timer_done                     @ Finished timer processing
+@
+@    }
+@    else
+@    {
+__tx_timer_no_timer:
+@
+@        /* No timer expired, increment the timer pointer.  */
+@        _tx_timer_current_ptr++;
+@
+    ADD     r0, r0, #4                          @ Move to next timer
+@
+@        /* Check for wraparound.  */
+@        if (_tx_timer_current_ptr == _tx_timer_list_end)
+@
+    LDR     r3, =_tx_timer_list_end             @ Pickup address of timer list end
+    LDR     r2, [r3]                            @ Pickup list end
+    CMP     r0, r2                              @ Are we at list end?
+    BNE     __tx_timer_skip_wrap                @ No, skip wraparound logic
+@
+@            /* Wrap to beginning of list.  */
+@            _tx_timer_current_ptr =  _tx_timer_list_start;
+@
+    LDR     r3, =_tx_timer_list_start           @ Pickup address of timer list start
+    LDR     r0, [r3]                            @ Set current pointer to list start
+@
+__tx_timer_skip_wrap:
+@
+    STR     r0, [r1]                            @ Store new current timer pointer
+@    }
+@
+__tx_timer_done:
+@
+@
+@    /* See if anything has expired.  */
+@    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+@    {
+@
+    LDR     r3, =_tx_timer_expired_time_slice   @ Pickup address of expired flag
+    LDR     r2, [r3]                            @ Pickup time-slice expired flag
+    CMP     r2, #0                              @ Did a time-slice expire?
+    BNE     __tx_something_expired              @ If non-zero, time-slice expired
+    LDR     r1, =_tx_timer_expired              @ Pickup address of other expired flag
+    LDR     r0, [r1]                            @ Pickup timer expired flag
+    CMP     r0, #0                              @ Did a timer expire?
+    BEQ     __tx_timer_nothing_expired          @ No, nothing expired
+@
+__tx_something_expired:
+@
+@
+    STMDB   sp!, {r0, lr}                       @ Save the lr register on the stack
+                                                @   and save r0 just to keep 8-byte alignment
+@
+@    /* Did a timer expire?  */
+@    if (_tx_timer_expired)
+@    {
+@
+    LDR     r1, =_tx_timer_expired              @ Pickup address of expired flag
+    LDR     r0, [r1]                            @ Pickup timer expired flag
+    CMP     r0, #0                              @ Check for timer expiration
+    BEQ     __tx_timer_dont_activate            @ If not set, skip timer activation
+@
+@        /* Process timer expiration.  */
+@        _tx_timer_expiration_process();
+@
+    BL      _tx_timer_expiration_process        @ Call the timer expiration handling routine
+@
+@    }
+__tx_timer_dont_activate:
+@
+@    /* Did time slice expire?  */
+@    if (_tx_timer_expired_time_slice)
+@    {
+@
+    LDR     r3, =_tx_timer_expired_time_slice   @ Pickup address of time-slice expired 
+    LDR     r2, [r3]                            @ Pickup the actual flag
+    CMP     r2, #0                              @ See if the flag is set
+    BEQ     __tx_timer_not_ts_expiration        @ No, skip time-slice processing
+@
+@        /* Time slice interrupted thread.  */
+@        _tx_thread_time_slice();
+@
+    BL      _tx_thread_time_slice               @ Call time-slice processing
+@
+@    }
+@
+__tx_timer_not_ts_expiration:
+@
+    LDMIA   sp!, {r0, lr}                       @ Recover lr register (r0 is just there for
+                                                @   the 8-byte stack alignment
+@
+@    }
+@
+__tx_timer_nothing_expired:
+@
+#ifdef __THUMB_INTERWORK
+    BX      lr                                  @ Return to caller
+#else
+    MOV     pc, lr                              @ Return to caller
+#endif
+@
+@}
+
diff --git a/ports/cortex_r5/iar/example_build/azure_rtos.eww b/ports/cortex_r5/iar/example_build/azure_rtos.eww
new file mode 100644
index 00000000..17e0d329
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/azure_rtos.eww
@@ -0,0 +1,13 @@
+
+
+
+  
+    $WS_DIR$\sample_threadx.ewp
+  
+  
+    $WS_DIR$\tx.ewp
+  
+  
+
+
+
diff --git a/ports/cortex_r5/iar/example_build/cstartup.s b/ports/cortex_r5/iar/example_build/cstartup.s
new file mode 100644
index 00000000..7a46bec0
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/cstartup.s
@@ -0,0 +1,163 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Part one of the system initialization code,
+;; contains low-level
+;; initialization.
+;;
+;; Copyright 2007 IAR Systems. All rights reserved.
+;;
+;; $Revision: 49919 $
+;;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION IRQ_STACK:DATA:NOROOT(3)
+        SECTION FIQ_STACK:DATA:NOROOT(3)
+        SECTION CSTACK:DATA:NOROOT(3)
+
+;
+; The module in this file are included in the libraries, and may be
+; replaced by any user-defined modules that define the PUBLIC symbol
+; __iar_program_start or a user defined start symbol.
+;
+; To override the cstartup defined in the library, simply add your
+; modified version to the workbench project.
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        PUBLIC  __vector
+        PUBLIC  __iar_program_start
+        EXTERN  Undefined_Handler
+        EXTERN  SWI_Handler
+        EXTERN  Prefetch_Handler
+        EXTERN  Abort_Handler
+        EXTERN  IRQ_Handler
+        EXTERN  FIQ_Handler
+
+        DATA
+
+__iar_init$$done:               ; The vector table is not needed
+                                ; until after copy initialization is done
+
+__vector:                       ; Make this a DATA label, so that stack usage
+                                ; analysis doesn't consider it an uncalled fun
+
+        ARM
+
+        ; All default exception handlers (except reset) are
+        ; defined as weak symbol definitions.
+        ; If a handler is defined by the application it will take precedence.
+        LDR     PC,Reset_Addr           ; Reset
+        LDR     PC,Undefined_Addr       ; Undefined instructions
+        LDR     PC,SWI_Addr             ; Software interrupt (SWI/SVC)
+        LDR     PC,Prefetch_Addr        ; Prefetch abort
+        LDR     PC,Abort_Addr           ; Data abort
+        DCD     0                       ; RESERVED
+        LDR     PC,IRQ_Addr             ; IRQ
+        LDR     PC,FIQ_Addr             ; FIQ
+
+        DATA
+
+Reset_Addr:     DCD   __iar_program_start
+Undefined_Addr: DCD   Undefined_Handler
+SWI_Addr:       DCD   SWI_Handler
+Prefetch_Addr:  DCD   Prefetch_Handler
+Abort_Addr:     DCD   Abort_Handler
+IRQ_Addr:       DCD   IRQ_Handler
+FIQ_Addr:       DCD   FIQ_Handler
+
+
+; --------------------------------------------------
+; ?cstartup -- low-level system initialization code.
+;
+; After a reset execution starts here, the mode is ARM, supervisor
+; with interrupts disabled.
+;
+
+
+
+        SECTION .text:CODE:NOROOT(2)
+
+        EXTERN  __cmain
+        REQUIRE __vector
+        EXTWEAK __iar_init_core
+        EXTWEAK __iar_init_vfp
+
+
+        ARM
+
+__iar_program_start:
+?cstartup:
+
+;
+; Add initialization needed before setup of stackpointers here.
+;
+
+;
+; Initialize the stack pointers.
+; The pattern below can be used for any of the exception stacks:
+; FIQ, IRQ, SVC, ABT, UND, SYS.
+; The USR mode uses the same stack as SYS.
+; The stack segments must be defined in the linker command file,
+; and be declared above.
+;
+
+
+; --------------------
+; Mode, correspords to bits 0-5 in CPSR
+
+#define MODE_MSK 0x1F            ; Bit mask for mode bits in CPSR
+
+#define USR_MODE 0x10            ; User mode
+#define FIQ_MODE 0x11            ; Fast Interrupt Request mode
+#define IRQ_MODE 0x12            ; Interrupt Request mode
+#define SVC_MODE 0x13            ; Supervisor mode
+#define ABT_MODE 0x17            ; Abort mode
+#define UND_MODE 0x1B            ; Undefined Instruction mode
+#define SYS_MODE 0x1F            ; System mode
+
+        MRS     r0, cpsr                ; Original PSR value
+
+        ;; Set up the interrupt stack pointer.
+
+        BIC     r0, r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0, r0, #IRQ_MODE       ; Set IRQ mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(IRQ_STACK)     ; End of IRQ_STACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+        ;; Set up the fast interrupt stack pointer.
+
+        BIC     r0, r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0, r0, #FIQ_MODE       ; Set FIR mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(FIQ_STACK)     ; End of FIQ_STACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+        ;; Set up the normal stack pointer.
+
+        BIC     r0 ,r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0 ,r0, #SYS_MODE       ; Set System mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(CSTACK)        ; End of CSTACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+        ;; Turn on core features assumed to be enabled.
+          FUNCALL __iar_program_start, __iar_init_core
+        BL      __iar_init_core
+
+        ;; Initialize VFP (if needed).
+          FUNCALL __iar_program_start, __iar_init_vfp
+        BL      __iar_init_vfp
+
+;;;
+;;; Add more initialization here
+;;;
+
+;;; Continue to __cmain for C-level initialization.
+
+          FUNCALL __iar_program_start, __cmain
+        B       __cmain
+
+        END
diff --git a/ports/cortex_r5/iar/example_build/sample_threadx.c b/ports/cortex_r5/iar/example_build/sample_threadx.c
new file mode 100644
index 00000000..983109cc
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/sample_threadx.c
@@ -0,0 +1,376 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include   "tx_api.h"
+
+#define     DEMO_STACK_SIZE         1024
+#define     DEMO_BYTE_POOL_SIZE     9120
+#define     DEMO_BLOCK_POOL_SIZE    100
+#define     DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+
+/* Define byte pool memory.  */
+
+UCHAR                   byte_pool_memory[DEMO_BYTE_POOL_SIZE];
+
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG           thread_0_counter;
+ULONG           thread_1_counter;
+ULONG           thread_1_messages_sent;
+ULONG           thread_2_counter;
+ULONG           thread_2_messages_received;
+ULONG           thread_3_counter;
+ULONG           thread_4_counter;
+ULONG           thread_5_counter;
+ULONG           thread_6_counter;
+ULONG           thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+/* Define main entry point.  */
+
+int main()
+{
+   
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/cortex_r5/iar/example_build/sample_threadx.dep b/ports/cortex_r5/iar/example_build/sample_threadx.dep
new file mode 100644
index 00000000..5dad90e2
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/sample_threadx.dep
@@ -0,0 +1,253 @@
+
+
+    4
+    811054824
+    
+        Debug
+        
+            $PROJ_DIR$\Debug\Obj\sample_threadx.__cstat.et
+            $PROJ_DIR$\Debug\Exe\sample_threadx.out
+            $PROJ_DIR$\rti.h
+            $PROJ_DIR$\Debug\Obj\demo.r79
+            $PROJ_DIR$\Debug\Obj\rti.pbi
+            $TOOLKIT_DIR$\inc\DLib_Threads.h
+            $PROJ_DIR$\sample_threadx.icf
+            $TOOLKIT_DIR$\inc\ysizet.h
+            $TOOLKIT_DIR$\inc\DLib_Defaults.h
+            $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h
+            $PROJ_DIR$\Debug\Obj\rti.__cstat.et
+            $TOOLKIT_DIR$\inc\DLib_Config_Normal.h
+            $PROJ_DIR$\Debug\List\cstartup.lst
+            $PROJ_DIR$\tx_initialize_low_level.s79
+            $TOOLKIT_DIR$\inc\c\intrinsics.h
+            $TOOLKIT_DIR$\inc\DLib_Product_string.h
+            $TOOLKIT_DIR$\inc\intrinsics.h
+            $PROJ_DIR$\Debug\List\sample_threadx.map
+            $PROJ_DIR$\Debug\Obj\sample_threadx.pbd
+            $TOOLKIT_DIR$\inc\c\DLib_Defaults.h
+            $TOOLKIT_DIR$\inc\c\stdlib.h
+            $PROJ_DIR$\Debug\List\tx_initialize_low_level.lst
+            $PROJ_DIR$\Debug\Obj\sample_threadx.o
+            $TOOLKIT_DIR$\inc\c\string.h
+            $TOOLKIT_DIR$\lib\dl7Sx_tbn.a
+            $TOOLKIT_DIR$\inc\stdlib.h
+            $TOOLKIT_DIR$\inc\xencoding_limits.h
+            $PROJ_DIR$\Debug\Obj\tx_execution_profile.pbi
+            $PROJ_DIR$\Debug\Obj\tx_initialize_low_level.o
+            $TOOLKIT_DIR$\lib\rt7Sx_tb.a
+            $TOOLKIT_DIR$\inc\c\yvals.h
+            $PROJ_DIR$\cstartup.s
+            $PROJ_DIR$\Debug\Obj\rti.o
+            $PROJ_DIR$\Debug\Obj\TX_ILL.r79
+            $PROJ_DIR$\Debug\Exe\tx.a
+            $PROJ_DIR$\sample_threadx.c
+            $PROJ_DIR$\tx_api.h
+            $PROJ_DIR$\tx_initialize_low_level.s
+            $PROJ_DIR$\tx_execution_profile.c
+            $PROJ_DIR$\tx_port.h
+            $TOOLKIT_DIR$\inc\c\ycheck.h
+            $TOOLKIT_DIR$\lib\sh7Sxs_b.a
+            $TOOLKIT_DIR$\inc\yvals.h
+            $PROJ_DIR$\tx_cstartup.s79
+            $TOOLKIT_DIR$\inc\c\iccarm_builtin.h
+            $PROJ_DIR$\Debug\Obj\tx_cstartup.r79
+            $TOOLKIT_DIR$\inc\c\DLib_Product.h
+            $TOOLKIT_DIR$\inc\c\ysizet.h
+            $TOOLKIT_DIR$\lib\m7Sx_tbv.a
+            $TOOLKIT_DIR$\inc\c\DLib_Product_string.h
+            $PROJ_DIR$\DEMO.C
+            $PROJ_DIR$\Debug\Obj\sample_threadx.xcl
+            $PROJ_DIR$\Debug\Obj\cstartup.o
+            $TOOLKIT_DIR$\inc\ycheck.h
+            $TOOLKIT_DIR$\inc\c\iar_intrinsics_common.h
+            $PROJ_DIR$\cstartup.s79
+            $TOOLKIT_DIR$\inc\DLib_Product.h
+            $TOOLKIT_DIR$\inc\string.h
+            $PROJ_DIR$\rti.c
+            $TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h
+            $PROJ_DIR$\TX_ILL.s79
+            $PROJ_DIR$\Debug\Obj\tx_execution_profile.o
+            $PROJ_DIR$\..\..\..\..\common\inc\tx_api.h
+            $PROJ_DIR$\..\inc\tx_port.h
+            $PROJ_DIR$\..\..\..\..\common\src\tx_queue_send.c
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_resume.c
+        
+        
+            [ROOT_NODE]
+            
+                
+                    ILINK
+                     1 17
+                
+            
+        
+        
+            $PROJ_DIR$\Debug\Exe\sample_threadx.out
+            
+                
+                    ILINK
+                     17
+                
+            
+            
+                
+                    ILINK
+                     6 52 22 34 28 41 29 48 24
+                
+            
+        
+        
+            $PROJ_DIR$\tx_initialize_low_level.s79
+            
+                
+                    AARM
+                     28 21
+                
+            
+        
+        
+            $PROJ_DIR$\cstartup.s
+            
+                
+                    AARM
+                     52 12
+                
+            
+        
+        
+            $PROJ_DIR$\sample_threadx.c
+            
+                
+                    ICCARM
+                     22
+                
+                
+                    __cstat
+                     0
+                
+                
+                    BICOMP
+                     51
+                
+            
+            
+                
+                    ICCARM
+                     62 63 20 40 30 19 9 46 47 59 23 49 14 44 54
+                
+            
+        
+        
+            $PROJ_DIR$\tx_initialize_low_level.s
+            
+                
+                    AARM
+                     28 21
+                
+            
+        
+        
+            $PROJ_DIR$\tx_execution_profile.c
+            
+                
+                    ICCARM
+                     61
+                
+                
+                    BICOMP
+                     27
+                
+            
+            
+                
+                    ICCARM
+                     36 39 25 53 42 8 11 56 26 5 7 57 15 16
+                
+                
+                    BICOMP
+                     36 39 25 53 42 8 56 26 5 7 57 15 16
+                
+            
+        
+        
+            $PROJ_DIR$\tx_cstartup.s79
+            
+                
+                    AARM
+                     45
+                
+            
+        
+        
+            $PROJ_DIR$\DEMO.C
+            
+                
+                    ICCARM
+                     3
+                
+            
+            
+                
+                    ICCARM
+                     36 39
+                
+            
+        
+        
+            $PROJ_DIR$\cstartup.s79
+            
+                
+                    AARM
+                     52
+                
+            
+        
+        
+            $PROJ_DIR$\rti.c
+            
+                
+                    ICCARM
+                     32
+                
+                
+                    __cstat
+                     10
+                
+                
+                    BICOMP
+                     4
+                
+            
+            
+                
+                    ICCARM
+                     2
+                
+                
+                    BICOMP
+                     2
+                
+            
+        
+        
+            $PROJ_DIR$\TX_ILL.s79
+            
+                
+                    AARM
+                     33
+                
+            
+        
+    
+    
+        Release
+        
+        
+            [MULTI_TOOL]
+            ILINK
+        
+        
+            [REBUILD_ALL]
+        
+    
+
diff --git a/ports/cortex_r5/iar/example_build/sample_threadx.ewd b/ports/cortex_r5/iar/example_build/sample_threadx.ewd
new file mode 100644
index 00000000..28a9ad4c
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/sample_threadx.ewd
@@ -0,0 +1,2974 @@
+
+
+    3
+    
+        Debug
+        
+            ARM
+        
+        1
+        
+            C-SPY
+            2
+            
+                32
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ARMSIM_ID
+            2
+            
+                1
+                1
+                1
+                
+                
+                
+                
+            
+        
+        
+            CADI_ID
+            2
+            
+                0
+                1
+                1
+                
+                
+                
+                
+                
+            
+        
+        
+            CMSISDAP_ID
+            2
+            
+                4
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            GDBSERVER_ID
+            2
+            
+                0
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            IJET_ID
+            2
+            
+                8
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            JLINK_ID
+            2
+            
+                16
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            LMIFTDI_ID
+            2
+            
+                2
+                1
+                1
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            NULINK_ID
+            2
+            
+                0
+                1
+                1
+                
+                
+                
+            
+        
+        
+            PEMICRO_ID
+            2
+            
+                3
+                1
+                1
+                
+                
+                
+                
+            
+        
+        
+            STLINK_ID
+            2
+            
+                7
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            THIRDPARTY_ID
+            2
+            
+                0
+                1
+                1
+                
+                
+                
+                
+            
+        
+        
+            TIFET_ID
+            2
+            
+                1
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            XDS100_ID
+            2
+            
+                8
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            
+                $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin
+                0
+            
+            
+                $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin
+                0
+            
+            
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new file mode 100644
index 00000000..a7c609f4
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/sample_threadx.ewp
@@ -0,0 +1,2140 @@
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diff --git a/ports/cortex_r5/iar/example_build/sample_threadx.ewt b/ports/cortex_r5/iar/example_build/sample_threadx.ewt
new file mode 100644
index 00000000..77fe620f
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/sample_threadx.ewt
@@ -0,0 +1,2791 @@
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+            
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+    
+        Common sources
+        
+            $PROJ_DIR$\cstartup.s
+        
+        
+            $PROJ_DIR$\sample_threadx.c
+        
+        
+            $PROJ_DIR$\Debug\Exe\tx.a
+        
+        
+            $PROJ_DIR$\tx_initialize_low_level.s
+        
+    
+
diff --git a/ports/cortex_r5/iar/example_build/sample_threadx.icf b/ports/cortex_r5/iar/example_build/sample_threadx.icf
new file mode 100644
index 00000000..13723763
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/sample_threadx.icf
@@ -0,0 +1,49 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__       = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x00000040;
+define symbol __ICFEDIT_region_ROM_end__     = 0x0013FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x08000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x0802FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x200;
+define symbol __ICFEDIT_size_svcstack__ = 0x100;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x100;
+define symbol __ICFEDIT_size_undstack__ = 0x100;
+define symbol __ICFEDIT_size_abtstack__ = 0x100;
+define symbol __ICFEDIT_size_heap__     = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define symbol __region_DRAM_start__   = 0x80000000;
+define symbol __region_DRAM_end__     = 0x807FFFFF;
+define region DRAM_region  = mem:[from __region_DRAM_start__   to __region_DRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+                        block UND_STACK, block ABT_STACK, block HEAP};
+place in DRAM_region  { section DRAM };
+
+place in RAM_region { last section FREE_MEM};
\ No newline at end of file
diff --git a/ports/cortex_r5/iar/example_build/settings/azure_rtos.wsdt b/ports/cortex_r5/iar/example_build/settings/azure_rtos.wsdt
new file mode 100644
index 00000000..0923efcb
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/azure_rtos.wsdt
@@ -0,0 +1,535 @@
+
+
+    
+        
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+            tx/Debug
+        
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+            
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+    
+
diff --git a/ports/cortex_r5/iar/example_build/settings/sample_threadx.Debug.cspy.bat b/ports/cortex_r5/iar/example_build/settings/sample_threadx.Debug.cspy.bat
new file mode 100644
index 00000000..ed996cec
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/sample_threadx.Debug.cspy.bat
@@ -0,0 +1,40 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+@echo off 
+
+if not "%~1" == "" goto debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r5\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r5\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r5\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r5\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+
+@echo off 
+:end
\ No newline at end of file
diff --git a/ports/cortex_r5/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports/cortex_r5/iar/example_build/settings/sample_threadx.Debug.cspy.ps1
new file mode 100644
index 00000000..198168ed
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/sample_threadx.Debug.cspy.ps1
@@ -0,0 +1,31 @@
+param([String]$debugfile = "");
+
+# This powershell file has been generated by the IAR Embedded Workbench
+# C - SPY Debugger, as an aid to preparing a command line for running
+# the cspybat command line utility using the appropriate settings.
+#
+# Note that this file is generated every time a new debug session
+# is initialized, so you may want to move or rename the file before
+# making changes.
+#
+# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
+# by the name of the debug file (usually an ELF / DWARF or UBROF file).
+#
+# Read about available command line parameters in the C - SPY Debugging
+# Guide. Hints about additional command line parameters that may be
+# useful in specific cases :
+#   --download_only   Downloads a code image without starting a debug
+#                     session afterwards.
+#   --silent          Omits the sign - on message.
+#   --timeout         Limits the maximum allowed execution time.
+#
+
+
+if ($debugfile -eq "")
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r5\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r5\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+}
+else
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r5\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r5\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+}
diff --git a/ports/cortex_r5/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports/cortex_r5/iar/example_build/settings/sample_threadx.Debug.driver.xcl
new file mode 100644
index 00000000..7f8b9b49
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/sample_threadx.Debug.driver.xcl
@@ -0,0 +1,15 @@
+"--endian=big" 
+
+"--cpu=Cortex-R5" 
+
+"--fpu=VFPv3" 
+
+"--semihosting" 
+
+"--BE8" 
+
+"--multicore_nr_of_cores=1" 
+
+
+
+
diff --git a/ports/cortex_r5/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports/cortex_r5/iar/example_build/settings/sample_threadx.Debug.general.xcl
new file mode 100644
index 00000000..23f67303
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/sample_threadx.Debug.general.xcl
@@ -0,0 +1,11 @@
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" 
+
+"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r5\iar\example_build\Debug\Exe\sample_threadx.out" 
+
+--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" 
+
+
+
+
diff --git a/ports/cortex_r5/iar/example_build/settings/sample_threadx.crun b/ports/cortex_r5/iar/example_build/settings/sample_threadx.crun
new file mode 100644
index 00000000..d71ea555
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/sample_threadx.crun
@@ -0,0 +1,13 @@
+
+
+    1
+    
+        
+            *
+            *
+            *
+            0
+            1
+        
+    
+
diff --git a/ports/cortex_r5/iar/example_build/settings/sample_threadx.dbgdt b/ports/cortex_r5/iar/example_build/settings/sample_threadx.dbgdt
new file mode 100644
index 00000000..43d2a650
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/sample_threadx.dbgdt
@@ -0,0 +1,1797 @@
+
+
+    
+        
+            
+                
+                    447
+                    27
+                    27
+                    2010398909
+                
+            
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+                    thread_4_counter
+                    thread_5_counter
+                    thread_6_counter
+                    thread_7_counter
+                    
+                
+                
+                    Expression
+                    Location
+                    Type
+                    Value
+                
+                
+                    161
+                    150
+                    100
+                    100
+                
+            
+        
+        
+            
+                
+                    
+                        TabID-32281-8114
+                        Workspace
+                        Workspace
+                        
+                            
+                                <ws>
+                                <ws>/sample_threadx
+                                <ws>/sample_threadx/Common sources
+                                <ws>/sample_threadx/Common sources/tx_cstartup.s79
+                                sample_threadx
+                                sample_threadx/Output
+                                sample_threadx/Output/sample_threadx.out
+                                sample_threadx/Output/sample_threadx.out/Output
+                            
+                        
+                    
+                
+                0
+            
+            
+                
+                    
+                        TabID-31758-8124
+                        Debug Log
+                        Debug-Log
+                        
+                    
+                    
+                        TabID-9738-8128
+                        Build
+                        Build
+                        
+                    
+                    
+                        TabID-20156-25745
+                        Breakpoints
+                        Breakpoints
+                    
+                
+                0
+            
+            
+                
+                    
+                        TabID-19697-5905
+                        Thread List
+                        TX-THREAD
+                        
+                            1
+                        
+                    
+                    
+                        TabID-19175-5914
+                        Message Queues
+                        TX-MESSAGEQUEUE
+                    
+                    
+                        TabID-29400-5927
+                        Semaphores
+                        TX-SEMAPHORE
+                    
+                    
+                        TabID-6858-5940
+                        Mutexes
+                        TX-MUTEX
+                    
+                    
+                        TabID-6335-5950
+                        Byte Pools
+                        TX-BYTEPOOL
+                    
+                    
+                        TabID-16561-5963
+                        Block Pools
+                        TX-BLOCKPOOL
+                    
+                    
+                        TabID-26786-5976
+                        Timers
+                        TX-TIMER
+                    
+                    
+                        TabID-26264-5986
+                        Event Flag Groups
+                        TX-EVENTFLAG
+                    
+                
+                0
+            
+            
+                
+                    
+                        TabID-4531-19825
+                        Watch 1
+                        WATCH_1
+                    
+                
+                0
+            
+        
+        
+            
+                
+                    TextEditor
+                    $WS_DIR$\sample_threadx.c
+                    0
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+                
+                0
+            
+            0
+            
+                
+                    1000000
+                    1000000
+                
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+            1
+        
+        
+            
+                
+                    
+                        
+                            iaridepm.enu1
+                        
+                    
+                
+                
+                    
+                        
+                            debuggergui.enu1
+                        
+                    
+                
+                
+                    
+                        
+                            threadxarmplugin.enu1
+                        
+                    
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+                00200000010000002100FFFF01001100434D4643546F6F6C426172427574746F6E00E100000000000064000000FFFEFF000000000000000000000000000100000001000000018001E100000000000065000000FFFEFF000000000000000000000000000100000001000000018003E100000000000067000000FFFEFF0000000000000000000000000001000000010000000180008100000000000048000000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF000000000000000000000000000100000001000000018007E10000000000006A000000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF000000000000000000000000000100000001000000018023E10000000004006C000000FFFEFF000000000000000000000000000100000001000000018022E10000000004006B000000FFFEFF000000000000000000000000000100000001000000018025E10000000000006E000000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF00000000000000000000000000010000000100000001802BE100000000040071000000FFFEFF00000000000000000000000000010000000100000001802CE100000000040072000000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF000000000000000000000000000100000001000000FFFF01000D005061737465436F6D626F426F784281000000000000FFFFFFFFFFFEFF0000000000000000000100000000000000010000007800000002002050FFFFFFFFFFFEFF0096000000000000000000018021810000000004005B000000FFFEFF000000000000000000000000000100000001000000018024E10000000000006D000000FFFEFF000000000000000000000000000100000001000000018028E10000000004006F000000FFFEFF000000000000000000000000000100000001000000018029E100000000000070000000FFFEFF000000000000000000000000000100000001000000018002810000000000004A000000FFFEFF000000000000000000000000000100000001000000018029810000000000005F000000FFFEFF000000000000000000000000000100000001000000018027810000000000005D000000FFFEFF000000000000000000000000000100000001000000018028810000000000005E000000FFFEFF00000000000000000000000000010000000100000001801D8100000000040057000000FFFEFF00000000000000000000000000010000000100000001801E8100000000040058000000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF00000000000000000000000000010000000100000001800B810000000004004E000000FFFEFF00000000000000000000000000010000000100000001800C810000000000004F000000FFFEFF00000000000000000000000000010000000100000001805F8600000000000063000000FFFEFF00000000000000000000000000010000000100000001800000000001000000FFFFFFFFFFFEFF00000000000000000000000000010000000100000001801F8100000000000059000000FFFEFF000000000000000000000000000100000001000000018020810000000000005A000000FFFEFF0000000000000000000000000001000000010000000180468100000000020061000000FFFEFF00000000000000000000000000010000000100000000000000FFFEFF044D00610069006E00FF7F0000
+            
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+
diff --git a/ports/cortex_r5/iar/example_build/settings/sample_threadx.dnx b/ports/cortex_r5/iar/example_build/settings/sample_threadx.dnx
new file mode 100644
index 00000000..4c51289b
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/sample_threadx.dnx
@@ -0,0 +1,130 @@
+
+
+    
+        0
+        1
+        90
+        1
+        1
+        1
+        main
+        0
+        50
+    
+    
+        0
+        1
+    
+    
+        256381086
+    
+    
+        0
+    
+    
+        HL512000
+        
+        0
+        2
+        _ 0
+        _ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+        _ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+        _ 0
+        _ 0
+    
+    
+        _ 0
+        _ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+        _ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+        _ 0
+        _ 0
+        0
+        1
+    
+    
+        _ 0
+        _ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+        _ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+        _ 0
+        _ 0
+    
+    
+        _ 0
+        _ 0
+    
+    
+        0
+    
+    
+        1
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+    
+    
+        0
+        0
+        0
+    
+    
+        0
+        1
+        0
+        0
+    
+    
+        0
+    
+    
+        1
+    
+    
+        _ 0
+        _ ""
+    
+    
+        _ 0
+        _ ""
+        _ 0
+    
+    
+        0
+        0
+        1
+        0
+        1
+        0
+    
+    
+        0
+        0
+        1
+        0
+        1
+    
+    
+        0
+    
+    
+        0
+    
+    
+        1
+        _ 0 9999 0 9999 1 0 0 100 0 1 "IRQ 1 0x18 CPSR.I"
+        1
+    
+    
+        1
+        0
+        1
+        0
+        1
+    
+    
+        0
+        0
+    
+    
+        10000000
+        0
+        1
+    
+
diff --git a/ports/cortex_r5/iar/example_build/settings/sample_threadx.reggroups b/ports/cortex_r5/iar/example_build/settings/sample_threadx.reggroups
new file mode 100644
index 00000000..5f282702
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/sample_threadx.reggroups
@@ -0,0 +1 @@
+
\ No newline at end of file
diff --git a/ports/cortex_r5/iar/example_build/settings/sample_threadx_Debug_xds100board.dat b/ports/cortex_r5/iar/example_build/settings/sample_threadx_Debug_xds100board.dat
new file mode 100644
index 00000000..192ce771
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/sample_threadx_Debug_xds100board.dat
@@ -0,0 +1,32 @@
+# config version=3.5
+$ sepk
+  pod_drvr=jioxds110.dll
+  pod_port=0
+  pod_serial=HL512000
+$ /
+$ product
+  title="Texas Instruments XDS110 USB"
+  alias=TI_XDS110_USB
+  name=XDS110
+$ /
+$ uscif
+  tdoedge=FALL
+  tclk_program=DEFAULT
+  tclk_frequency=2.5MHz
+$ /
+$ dot7
+  dts_usage=nothing
+$ /
+$ swd
+  swd_debug=disabled
+  swo_data=aux_uart
+$ /
+@ icepick family=icepick_c irbits=6 drbits=1 subpaths=2
+  & port17 address=17 default=no custom=no force=yes pseudo=no
+  & port16 address=16 default=no custom=no force=yes pseudo=no
+    @ dap family=cs_dap irbits=4 drbits=1 subpaths=1 identify=0
+      & portr4 type=debug address=0 default=no custom=no force=no pseudo=no
+        @ cortexr4 family=cortex_rxx irbits=0 drbits=0 address=0x80001000 identify=0x02000100 traceid=0x0
+      & /
+  & /
+# /
diff --git a/ports/cortex_r5/iar/example_build/settings/tx.Debug.cspy.bat b/ports/cortex_r5/iar/example_build/settings/tx.Debug.cspy.bat
new file mode 100644
index 00000000..ddbce99e
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/tx.Debug.cspy.bat
@@ -0,0 +1,40 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+@echo off 
+
+if not "%~1" == "" goto debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+
+@echo off 
+:end
\ No newline at end of file
diff --git a/ports/cortex_r5/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports/cortex_r5/iar/example_build/settings/tx.Debug.cspy.ps1
new file mode 100644
index 00000000..903a188b
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/tx.Debug.cspy.ps1
@@ -0,0 +1,31 @@
+param([String]$debugfile = "");
+
+# This powershell file has been generated by the IAR Embedded Workbench
+# C - SPY Debugger, as an aid to preparing a command line for running
+# the cspybat command line utility using the appropriate settings.
+#
+# Note that this file is generated every time a new debug session
+# is initialized, so you may want to move or rename the file before
+# making changes.
+#
+# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
+# by the name of the debug file (usually an ELF / DWARF or UBROF file).
+#
+# Read about available command line parameters in the C - SPY Debugging
+# Guide. Hints about additional command line parameters that may be
+# useful in specific cases :
+#   --download_only   Downloads a code image without starting a debug
+#                     session afterwards.
+#   --silent          Omits the sign - on message.
+#   --timeout         Limits the maximum allowed execution time.
+#
+
+
+if ($debugfile -eq "")
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+}
+else
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+}
diff --git a/ports/cortex_r5/iar/example_build/settings/tx.Debug.driver.xcl b/ports/cortex_r5/iar/example_build/settings/tx.Debug.driver.xcl
new file mode 100644
index 00000000..7f8b9b49
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/tx.Debug.driver.xcl
@@ -0,0 +1,15 @@
+"--endian=big" 
+
+"--cpu=Cortex-R5" 
+
+"--fpu=VFPv3" 
+
+"--semihosting" 
+
+"--BE8" 
+
+"--multicore_nr_of_cores=1" 
+
+
+
+
diff --git a/ports/cortex_r5/iar/example_build/settings/tx.Debug.general.xcl b/ports/cortex_r5/iar/example_build/settings/tx.Debug.general.xcl
new file mode 100644
index 00000000..d5205384
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/tx.Debug.general.xcl
@@ -0,0 +1,11 @@
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\bin\armproc.dll" 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\bin\armsim2.dll" 
+
+"C:\release\threadx\Debug\Exe\tx.out" 
+
+--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.1\arm\bin\armbat.dll" 
+
+
+
+
diff --git a/ports/cortex_r5/iar/example_build/settings/tx.crun b/ports/cortex_r5/iar/example_build/settings/tx.crun
new file mode 100644
index 00000000..d71ea555
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/tx.crun
@@ -0,0 +1,13 @@
+
+
+    1
+    
+        
+            *
+            *
+            *
+            0
+            1
+        
+    
+
diff --git a/ports/cortex_r5/iar/example_build/settings/tx.dbgdt b/ports/cortex_r5/iar/example_build/settings/tx.dbgdt
new file mode 100644
index 00000000..9e08d965
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/tx.dbgdt
@@ -0,0 +1,4 @@
+
+
+    
+
diff --git a/ports/cortex_r5/iar/example_build/settings/tx.dnx b/ports/cortex_r5/iar/example_build/settings/tx.dnx
new file mode 100644
index 00000000..25e4c4ba
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/settings/tx.dnx
@@ -0,0 +1,58 @@
+
+
+    
+        0
+        1
+        90
+        1
+        1
+        1
+        main
+        0
+        50
+    
+    
+        0
+        1
+    
+    
+        0
+        0
+        1
+        0
+        1
+        0
+    
+    
+        0
+        0
+        1
+        0
+        1
+    
+    
+        0
+    
+    
+        0
+    
+    
+        1
+    
+    
+        1
+        0
+        1
+        0
+        1
+    
+    
+        0
+        0
+    
+    
+        10000000
+        0
+        1
+    
+
diff --git a/ports/cortex_r5/iar/example_build/tx.dep b/ports/cortex_r5/iar/example_build/tx.dep
new file mode 100644
index 00000000..a10cf92c
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/tx.dep
@@ -0,0 +1,10476 @@
+
+
+    4
+    2479021136
+    
+        Debug
+        
+            $PROJ_DIR$\tx_api.h
+            $PROJ_DIR$\tx_block_pool.h
+            $PROJ_DIR$\tx_block_pool_info_get.c
+            $PROJ_DIR$\tx_block_pool_delete.c
+            $PROJ_DIR$\tx_block_pool_initialize.c
+            $PROJ_DIR$\tx_block_allocate.c
+            $PROJ_DIR$\tx_block_pool_performance_system_info_get.c
+            $PROJ_DIR$\tx_block_pool_prioritize.c
+            $PROJ_DIR$\tx_block_release.c
+            $PROJ_DIR$\tx_block_pool_performance_info_get.c
+            $PROJ_DIR$\tx_block_pool_cleanup.c
+            $PROJ_DIR$\tx_block_pool_create.c
+            $PROJ_DIR$\tx_byte_pool_info_get.c
+            $PROJ_DIR$\tx_event_flags_delete.c
+            $PROJ_DIR$\tx_event_flags_create.c
+            $PROJ_DIR$\tx_event_flags_performance_system_info_get.c
+            $PROJ_DIR$\tx_mutex_create.c
+            $PROJ_DIR$\tx_byte_pool_search.c
+            $PROJ_DIR$\tx_event_flags_set_notify.c
+            $PROJ_DIR$\tx_byte_pool_performance_info_get.c
+            $PROJ_DIR$\tx_byte_pool_create.c
+            $PROJ_DIR$\tx_byte_pool_performance_system_info_get.c
+            $PROJ_DIR$\tx_byte_pool_prioritize.c
+            $PROJ_DIR$\tx_byte_release.c
+            $PROJ_DIR$\tx_byte_pool_initialize.c
+            $PROJ_DIR$\tx_byte_pool.h
+            $PROJ_DIR$\tx_event_flags.h
+            $PROJ_DIR$\tx_event_flags_get.c
+            $PROJ_DIR$\tx_event_flags_info_get.c
+            $PROJ_DIR$\tx_event_flags_performance_info_get.c
+            $PROJ_DIR$\tx_byte_allocate.c
+            $PROJ_DIR$\tx_event_flags_set.c
+            $PROJ_DIR$\tx_iar.c
+            $PROJ_DIR$\tx_initialize.h
+            $PROJ_DIR$\tx_initialize_high_level.c
+            $PROJ_DIR$\tx_event_flags_cleanup.c
+            $PROJ_DIR$\tx_initialize_kernel_enter.c
+            $PROJ_DIR$\tx_byte_pool_cleanup.c
+            $PROJ_DIR$\tx_initialize_kernel_setup.c
+            $PROJ_DIR$\tx_mutex_cleanup.c
+            $PROJ_DIR$\tx_event_flags_initialize.c
+            $PROJ_DIR$\tx_mutex.h
+            $PROJ_DIR$\tx_byte_pool_delete.c
+            $PROJ_DIR$\tx_queue.h
+            $PROJ_DIR$\tx_queue_create.c
+            $PROJ_DIR$\tx_queue_performance_info_get.c
+            $PROJ_DIR$\tx_semaphore_ceiling_put.c
+            $PROJ_DIR$\tx_semaphore_delete.c
+            $PROJ_DIR$\tx_mutex_info_get.c
+            $PROJ_DIR$\tx_semaphore.h
+            $PROJ_DIR$\tx_semaphore_get.c
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+        
+    
+    
+        Release
+        
+        
+            [MULTI_TOOL]
+            IARCHIVE
+        
+        
+            [REBUILD_ALL]
+        
+    
+
diff --git a/ports/cortex_r5/iar/example_build/tx.ewd b/ports/cortex_r5/iar/example_build/tx.ewd
new file mode 100644
index 00000000..23d5eff1
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/tx.ewd
@@ -0,0 +1,2974 @@
+
+
+    3
+    
+        Debug
+        
+            ARM
+        
+        1
+        
+            C-SPY
+            2
+            
+                32
+                1
+                1
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+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_buffer_full_notify.c
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+        
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+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_unfilter.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_initialize.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_interrupt_control.c
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+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_enter_insert.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_exit_insert.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_register.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_unregister.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_user_event_insert.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_allocate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_create.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_delete.c
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+        
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+        
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c
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+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c
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+        
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+        
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+        
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+        
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+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c
+        
+    
+
diff --git a/ports/cortex_r5/iar/example_build/tx.ewt b/ports/cortex_r5/iar/example_build/tx.ewt
new file mode 100644
index 00000000..016f76bc
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/tx.ewt
@@ -0,0 +1,3415 @@
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+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_time_slice_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_timeout.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_vectored_context_save.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_wait_abort.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_time_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_time_set.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_activate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_deactivate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_expiration_process.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_initialize.c
+        
+        
+            $PROJ_DIR$\..\src\tx_timer_interrupt.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_performance_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_performance_system_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_system_activate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_system_deactivate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_thread_entry.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_buffer_full_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_disable.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_enable.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_filter.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_unfilter.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_initialize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_interrupt_control.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_enter_insert.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_exit_insert.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_register.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_unregister.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_user_event_insert.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_allocate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_release.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_allocate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_release.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_flush.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_front_send.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_receive.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_ceiling_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_entry_exit_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_preemption_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_priority_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_relinquish.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_reset.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_resume.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_suspend.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_terminate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_time_slice_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c
+        
+    
+
diff --git a/ports/cortex_r5/iar/example_build/tx_initialize_low_level.s b/ports/cortex_r5/iar/example_build/tx_initialize_low_level.s
new file mode 100644
index 00000000..6e5da9e4
--- /dev/null
+++ b/ports/cortex_r5/iar/example_build/tx_initialize_low_level.s
@@ -0,0 +1,277 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Initialize                                                          */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_initialize.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+SVC_MODE        DEFINE  0x13                    ; SVC mode
+;
+
+    EXTERN      _tx_thread_system_stack_ptr
+    EXTERN      _tx_initialize_unused_memory
+    EXTERN      _tx_thread_context_save
+;    EXTERN      _tx_thread_vectored_context_save
+    EXTERN      _tx_thread_context_restore
+
+#ifdef TX_ENABLE_IRQ_NESTING
+    EXTERN      _tx_thread_irq_nesting_start
+    EXTERN      _tx_thread_irq_nesting_end
+#endif
+
+    EXTERN      _tx_timer_interrupt
+    EXTERN      ?cstartup
+    EXTERN      _tx_build_options
+    EXTERN      _tx_version_id
+;
+;
+;
+;/* Define the FREE_MEM segment that will specify where free memory is 
+;   defined.  This must also be located in at the end of other RAM segments
+;   in the linker control file.  The value of this segment is what is passed
+;   to tx_application_define.  */
+;
+    RSEG    FREE_MEM:DATA
+    PUBLIC  __tx_free_memory_start
+__tx_free_memory_start
+    DS32    4
+;
+;
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_low_level                           Cortex-R5/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for any low-level processor            */ 
+;/*    initialization, including setting up interrupt vectors, setting     */ 
+;/*    up a periodic timer interrupt source, saving the system stack       */ 
+;/*    pointer for use in ISR processing later, and finding the first      */ 
+;/*    available RAM memory address for tx_application_define.             */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_initialize_low_level(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    ARM
+    PUBLIC  _tx_initialize_low_level
+_tx_initialize_low_level
+;
+;    /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode.  */
+;
+;    /* Remember the stack pointer, link register, and switch to SVC mode.  */
+;
+    MOV     r0, sp                              ; Remember the SP
+    MOV     r1, lr                              ; Remember the LR
+    CPS     #SVC_MODE                           ; Switch to SVC mode
+    MOV     sp, r0                              ; Inherit the stack pointer setup by cstartup
+    MOV     lr, r1                              ; Inherit the link register
+;
+;    /* Pickup the start of free memory.  */
+;
+    LDR     r0, =__tx_free_memory_start         ; Get end of non-initialized RAM area
+;
+;    /* Save the system stack pointer.  */
+;    _tx_thread_system_stack_ptr = (VOID_PTR) (sp);
+;
+;    /* Save the first available memory address.  */
+;    _tx_initialize_unused_memory =  (VOID_PTR) FREE_MEM;
+;
+    LDR     r2, =_tx_initialize_unused_memory   ; Pickup unused memory ptr address
+    STR     r0, [r2, #0]                        ; Save first free memory address
+;                      
+;    /* Setup Timer for periodic interrupts.  */
+;
+;    /* Done, return to caller.  */
+;
+    BX      lr                                  ; Return to caller
+;}
+;
+;/* Define shells for each of the interrupt vectors.  */
+;
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_undefined
+__tx_undefined
+    B       __tx_undefined                      ; Undefined handler
+;
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_swi_interrupt
+__tx_swi_interrupt
+    B       __tx_swi_interrupt                  ; Software interrupt handler
+;
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_prefetch_handler
+__tx_prefetch_handler
+    B       __tx_prefetch_handler               ; Prefetch exception handler
+;
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_abort_handler
+__tx_abort_handler
+    B       __tx_abort_handler                  ; Abort exception handler
+;
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_reserved_handler
+__tx_reserved_handler
+    B       __tx_reserved_handler               ; Reserved exception handler
+;
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_irq_handler
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_irq_processing_return
+    PUBLIC  IRQ_Handler
+__tx_irq_handler
+IRQ_Handler
+;
+;    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return
+;
+;    /* At this point execution is still in the IRQ mode.  The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  In 
+;       addition, IRQ interrupts may be re-enabled - with certain restrictions -
+;       if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
+;       small code sequences where lr is saved before enabling interrupts and 
+;       restored after interrupts are again disabled.  */
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start 
+;       from IRQ mode with interrupts disabled.  This routine switches to the
+;       system mode and returns with IRQ interrupts enabled.  
+;       
+;       NOTE:  It is very important to ensure all IRQ interrupts are cleared 
+;       prior to enabling nested IRQ interrupts.  */
+#ifdef TX_ENABLE_IRQ_NESTING
+    BL      _tx_thread_irq_nesting_start
+#endif
+;
+;    /* For debug purpose, execute the timer interrupt processing here.  In
+;       a real system, some kind of status indication would have to be checked
+;       before the timer interrupt handler could be called.  */
+;
+    BL      _tx_timer_interrupt                 ; Timer interrupt handler
+;
+;    /* Application IRQ handlers can be called here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_context_restore.  
+;       This routine returns in processing in IRQ mode with interrupts disabled.  */
+#ifdef TX_ENABLE_IRQ_NESTING
+    BL      _tx_thread_irq_nesting_end
+#endif
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+;
+;
+;    /* This is an example of a vectored IRQ handler.  */
+;
+;    RSEG    .text:CODE:NOROOT(2)
+;    PUBLIC  __tx_example_vectored_irq_handler
+;__tx_example_vectored_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+;    STMDB   sp!, {r0-r3}                    ; Save some scratch registers
+;    MRS     r0, SPSR                        ; Pickup saved SPSR
+;    SUB     lr, lr, #4                      ; Adjust point of interrupt 
+;    STMDB   sp!, {r0, r10, r12, lr}         ; Store other registers
+;    BL      _tx_thread_vectored_context_save
+;
+;    /* At this point execution is still in the IRQ mode.  The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  In 
+;       addition, IRQ interrupts may be re-enabled - with certain restrictions -
+;       if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
+;       small code sequences where lr is saved before enabling interrupts and 
+;       restored after interrupts are again disabled.  */
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start 
+;       from IRQ mode with interrupts disabled.  This routine switches to the
+;       system mode and returns with IRQ interrupts enabled.  
+;       
+;       NOTE:  It is very important to ensure all IRQ interrupts are cleared 
+;       prior to enabling nested IRQ interrupts.  */
+;#ifdef TX_ENABLE_IRQ_NESTING
+;    BL      _tx_thread_irq_nesting_start
+;#endif
+;
+;    /* Application IRQ handler is called here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_context_restore.  
+;       This routine returns in processing in IRQ mode with interrupts disabled.  */
+;#ifdef TX_ENABLE_IRQ_NESTING
+;    BL      _tx_thread_irq_nesting_end
+;#endif
+;
+;    /* Jump to context restore to restore system context.  */
+;    B       _tx_thread_context_restore
+;
+;
+;    /* FIQ Handler */
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_fiq_handler
+__tx_fiq_handler
+    B       __tx_fiq_handler                    ; FIQ interrupt handler
+;
+;
+BUILD_OPTIONS
+    DC32    _tx_build_options                   ; Reference to ensure it comes in
+VERSION_ID
+    DC32    _tx_version_id                      ; Reference to ensure it comes in
+    END
+
diff --git a/ports/cortex_r5/iar/inc/tx_port.h b/ports/cortex_r5/iar/inc/tx_port.h
new file mode 100644
index 00000000..5c597d04
--- /dev/null
+++ b/ports/cortex_r5/iar/inc/tx_port.h
@@ -0,0 +1,384 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */ 
+/*                                                                        */ 
+/*    tx_port.h                                         Cortex-R5/IAR     */ 
+/*                                                           6.0.1        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This file contains data type definitions that make the ThreadX      */ 
+/*    real-time kernel function identically on a variety of different     */ 
+/*    processor architectures.  For example, the size or number of bits   */ 
+/*    in an "int" data type vary between microprocessor architectures and */ 
+/*    even C compilers for the same microprocessor.  ThreadX does not     */ 
+/*    directly use native C data types.  Instead, ThreadX creates its     */ 
+/*    own special types that can be mapped to actual data types by this   */ 
+/*    file to guarantee consistency in the interface and functionality.   */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include 
+#include 
+#include 
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#include 
+#endif
+
+
+/* Define ThreadX basic types for this port.  */ 
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */ 
+#endif
+
+
+/* Define various constants for the ThreadX ARM port.  */ 
+
+#define TX_INT_DISABLE                          0x80        /* Disable IRQ interrupts           */
+#define TX_INT_ENABLE                           0x00        /* Enable IRQ interrupts            */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_MISRA_ENABLE
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ++_tx_trace_simulated_time
+#endif
+#else
+ULONG   _tx_misra_time_stamp_get(VOID);
+#define TX_TRACE_TIME_SOURCE                    _tx_misra_time_stamp_get()
+#endif
+
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#ifdef TX_ENABLE_IRQ_NESTING
+#define TX_IRQ_NESTING_ENABLED                  1
+#else
+#define TX_IRQ_NESTING_ENABLED                  0
+#endif
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          (TX_IRQ_NESTING_ENABLED)
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#ifdef TX_MISRA_ENABLE
+#define TX_DISABLE_INLINE
+#else
+#define TX_INLINE_INITIALIZATION
+#endif
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifndef TX_MISRA_ENABLE
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_EXTENSION_2                               ULONG       tx_thread_vfp_enable; \
+                                                            VOID        *tx_thread_iar_tls_pointer;          
+#else
+#define TX_THREAD_EXTENSION_2                               ULONG       tx_thread_vfp_enable;
+#endif
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#if (__VER__ < 8000000)
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  __iar_dlib_perthread_allocate();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                    thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL;            
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               __iar_dlib_perthread_access(0);
+#else
+void    *_tx_iar_create_per_thread_tls_area(void);
+void    _tx_iar_destroy_per_thread_tls_area(void *tls_ptr);
+void    __iar_Initlocks(void);
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  _tx_iar_create_per_thread_tls_area();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                        thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL; } while(0);
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               do {__iar_Initlocks();} while(0); 
+#endif
+#else
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#endif
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef TX_DISABLE_INLINE
+
+#if __CORE__ > __ARM4TM__
+
+#if __CPU_MODE__ == 2
+
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       m = m & ((ULONG) (-((LONG) m))); \
+                                                b = (UINT) __CLZ(m); \
+                                                b = 31 - b; 
+#endif
+#endif
+#endif
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+
+/* First, check and see what mode the file is being compiled in. The IAR compiler
+   defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode 
+   is present.  If ARM 32-bit mode is present, the fast CPSR manipulation macros
+   are available. Otherwise, if Thumb mode is present, we must use function calls.  */
+
+#ifdef TX_DISABLE_INLINE
+
+UINT  _tx_thread_interrupt_disable(void);
+void  _tx_thread_interrupt_restore(UINT old_posture);
+
+
+#define TX_INTERRUPT_SAVE_AREA      UINT  interrupt_save;
+
+#define TX_DISABLE                  interrupt_save =  _tx_thread_interrupt_disable();
+#define TX_RESTORE                  _tx_thread_interrupt_restore(interrupt_save);
+
+#else
+#if __CPU_MODE__ == 2
+
+#if (__VER__ < 8002000)
+__intrinsic unsigned long __get_CPSR();
+__intrinsic void          __set_CPSR( unsigned long );
+#endif
+
+
+#if (__VER__ < 8002000)
+#define TX_INTERRUPT_SAVE_AREA      unsigned long interrupt_save;
+#else
+#define TX_INTERRUPT_SAVE_AREA      unsigned int interrupt_save;
+#endif
+
+#define TX_DISABLE                  interrupt_save =  __get_CPSR(); \
+                                    __set_CPSR(interrupt_save | TX_INT_DISABLE);
+#define TX_RESTORE                  __set_CPSR(interrupt_save);
+
+#else
+
+UINT  _tx_thread_interrupt_disable(void);
+void  _tx_thread_interrupt_restore(UINT old_posture);
+
+
+#define TX_INTERRUPT_SAVE_AREA      UINT  interrupt_save;
+
+#define TX_DISABLE                  interrupt_save =  _tx_thread_interrupt_disable();
+#define TX_RESTORE                  _tx_thread_interrupt_restore(interrupt_save);
+
+#endif
+#endif
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define VFP extension for the Cortex-R5.  Each is assumed to be called in the context of the executing
+   thread.  */
+
+void    tx_thread_vfp_enable(void);
+void    tx_thread_vfp_disable(void);
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Cortex-R5/IAR Version 6.0 *";
+#else
+#ifdef TX_MISRA_ENABLE
+extern  CHAR                    _tx_version_id[100];
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+#endif
+
+
+#endif
+
+
+
+
+
+
+
diff --git a/ports/cortex_r5/iar/readme_threadx.txt b/ports/cortex_r5/iar/readme_threadx.txt
new file mode 100644
index 00000000..96f7a37f
--- /dev/null
+++ b/ports/cortex_r5/iar/readme_threadx.txt
@@ -0,0 +1,426 @@
+                       Microsoft's Azure RTOS ThreadX for Cortex-R5 
+
+                                 Thumb & 32-bit Mode
+
+                                 Using the IAR Tools
+
+1.  Building the ThreadX run-time Library
+
+Building the ThreadX library is easy. First, open the Azure RTOS workspace
+azure_rtos.eww. Next, make the TX project the "active project" in the 
+IAR Embedded Workbench and select the "Make" button. You should observe 
+assembly and compilation of a series of ThreadX source files. This 
+results in the ThreadX run-time library file tx.a, which is needed by 
+the application.
+
+
+2.  Demonstration System
+
+The ThreadX demonstration is designed to execute under the IAR
+Windows-based Cortex-R5 simulator.
+
+Building the demonstration is easy; simply make the sample_threadx.ewp project
+the "active project" in the IAR Embedded Workbench and select the 
+"Make" button.
+
+You should observe the compilation of sample_threadx.c (which is the demonstration 
+application) and linking with tx.a. The resulting file sample_threadx.out is a
+binary file that can be downloaded and executed on IAR's Cortex-R5 simulator.
+
+
+3.  System Initialization
+
+The entry point in ThreadX for the Cortex-R5 using IAR tools is at label 
+?cstartup. This is defined within the IAR compiler's startup code. In 
+addition, this is where all static and global preset C variable 
+initialization processing takes place.
+
+The ThreadX tx_initialize_low_level.s file is responsible for setting up 
+various system data structures, and a periodic timer interrupt source. 
+By default, the vector area is defined at the top of cstartup.s, which is
+a slightly modified from the base IAR file. 
+
+The _tx_initialize_low_level function inside of tx_initialize_low_level.s
+also determines the first available address for use by the application, which 
+is supplied as the sole input parameter to your application definition function, 
+tx_application_define. To accomplish this, a section is created in 
+tx_initialize_low_level.s called FREE_MEM, which must be located after all 
+other RAM sections in memory.
+
+
+4.  Register Usage and Stack Frames
+
+The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are 
+scratch registers for each function. All other registers used by a C function 
+must be preserved by the function. ThreadX takes advantage of this in 
+situations where a context switch happens as a result of making a ThreadX 
+service call (which is itself a C function). In such cases, the saved 
+context of a thread is only the non-scratch registers.
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have one of these two types of stack frames. The top
+of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the 
+associated thread control block TX_THREAD.
+
+
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x00                   1                           0
+     0x04                   CPSR                        CPSR
+     0x08                   r0  (a1)                    r4  (v1)
+     0x0C                   r1  (a2)                    r5  (v2)
+     0x10                   r2  (a3)                    r6  (v3)
+     0x14                   r3  (a4)                    r7  (v4)
+     0x18                   r4  (v1)                    r8  (v5)
+     0x1C                   r5  (v2)                    r9  (v6)
+     0x20                   r6  (v3)                    r10 (v7)
+     0x24                   r7  (v4)                    r11 (fp)
+     0x28                   r8  (v5)                    r14 (lr)
+     0x2C                   r9  (v6)                        
+     0x30                   r10 (v7)                        
+     0x34                   r11 (fp)                        
+     0x38                   r12 (ip)                         
+     0x3C                   r14 (lr)
+     0x40                   PC 
+
+
+5.  Conditional Compilation Switches
+
+The following are conditional compilation options for building the ThreadX library
+and application:
+
+    TX_ENABLE_IRQ_NESTING                       This assembler define enables IRQ
+                                                nested support. If IRQ nested 
+                                                interrupt support is needed, this
+                                                define should be applied to 
+                                                tx_initialize_low_level.s.
+
+    TX_DISABLE_ERROR_CHECKING                   If defined before tx_api.h is included,
+                                                this define causes basic ThreadX error
+                                                checking to be disabled. Please see
+                                                Chapter 2 in the "ThreadX User Guide" 
+                                                for more details.
+
+    TX_MAX_PRIORITIES                           Defines the priority levels for ThreadX. 
+                                                Legal values range from 32 through 
+                                                1024 (inclusive) and MUST be evenly divisible 
+                                                by 32. Increasing the number of priority levels 
+                                                supported increases the RAM usage by 128 bytes 
+                                                for every group of 32 priorities. However, there 
+                                                is only a negligible effect on performance. By 
+                                                default, this value is set to 32 priority levels.
+
+    TX_MINIMUM_STACK                            Defines the minimum stack size (in bytes). It is 
+                                                used for error checking when threads are created. 
+                                                The default value is port-specific and is found 
+                                                in tx_port.h.
+
+    TX_TIMER_THREAD_STACK_SIZE                  Defines the stack size (in bytes) of the internal 
+                                                ThreadX timer thread. This thread processes all 
+                                                thread sleep requests as well as all service call 
+                                                timeouts. In addition, all application timer callback 
+                                                routines are invoked from this context. The default 
+                                                value is port-specific and is found in tx_port.h.
+
+    TX_TIMER_THREAD_PRIORITY                    Defines the priority of the internal ThreadX timer 
+                                                thread. The default value is priority 0 - the highest 
+                                                priority in ThreadX. The default value is defined 
+                                                in tx_port.h.
+
+    TX_TIMER_PROCESS_IN_ISR                     Defined, this option eliminates the internal system 
+                                                timer thread for ThreadX. This results in improved 
+                                                performance on timer events and smaller RAM requirements 
+                                                because the timer stack and control block are no 
+                                                longer needed. However, using this option moves all 
+                                                the timer expiration processing to the timer ISR level. 
+                                                By default, this option is not defined.
+
+    TX_REACTIVATE_INLINE                        Defined, this option performs reactivation of ThreadX 
+                                                timers in-line instead of using a function call. This 
+                                                improves performance but slightly increases code size. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_STACK_FILLING                    Defined, placing the 0xEF value in each byte of each 
+                                                thread's stack is disabled. By default, this option is 
+                                                not defined.
+
+    TX_ENABLE_STACK_CHECKING                    Defined, this option enables ThreadX run-time stack checking, 
+                                                which includes analysis of how much stack has been used and 
+                                                examination of data pattern "fences" before and after the 
+                                                stack area. If a stack error is detected, the registered 
+                                                application stack error handler is called. This option does 
+                                                result in slightly increased overhead and code size. Please 
+                                                review the tx_thread_stack_error_notify API for more information. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_PREEMPTION_THRESHOLD             Defined, this option disables the preemption-threshold feature 
+                                                and slightly reduces code size and improves performance. Of course, 
+                                                the preemption-threshold capabilities are no longer available. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_REDUNDANT_CLEARING               Defined, this option removes the logic for initializing ThreadX 
+                                                global C data structures to zero. This should only be used if 
+                                                the compiler's initialization code sets all un-initialized 
+                                                C global data to zero. Using this option slightly reduces 
+                                                code size and improves performance during initialization. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_NOTIFY_CALLBACKS                 Defined, this option disables the notify callbacks for various 
+                                                ThreadX objects. Using this option slightly reduces code size 
+                                                and improves performance.
+
+    TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO       Defined, this option enables the gathering of performance 
+                                                information on block pools. By default, this option is 
+                                                not defined.
+
+    TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO        Defined, this option enables the gathering of performance 
+                                                information on byte pools. By default, this option is 
+                                                not defined.
+
+    TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO      Defined, this option enables the gathering of performance 
+                                                information on event flags groups. By default, this option 
+                                                is not defined.
+
+    TX_MUTEX_ENABLE_PERFORMANCE_INFO            Defined, this option enables the gathering of performance 
+                                                information on mutexes. By default, this option is 
+                                                not defined.
+
+    TX_QUEUE_ENABLE_PERFORMANCE_INFO            Defined, this option enables the gathering of performance 
+                                                information on queues. By default, this option is 
+                                                not defined.
+
+    TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO        Defined, this option enables the gathering of performance 
+                                                information on semaphores. By default, this option is 
+                                                not defined.
+
+    TX_THREAD_ENABLE_PERFORMANCE_INFO           Defined, this option enables the gathering of performance 
+                                                information on threads. By default, this option is 
+                                                not defined.
+
+    TX_TIMER_ENABLE_PERFORMANCE_INFO            Defined, this option enables the gathering of performance 
+                                                information on timers. By default, this option is 
+                                                not defined.
+
+    TX_ENABLE_EVENT_TRACE                       Defined, this option enables the internal ThreadX trace
+                                                feature. The trace buffer is supplied at a later time
+                                                via an application call to tx_trace_enable.
+
+    TX_TRACE_TIME_SOURCE                        This defines the time-stamp source for event tracing. 
+                                                This define is only pertinent if the ThreadX library is 
+                                                built with TX_ENABLE_EVENT_TRACE defined.
+
+    TX_TRACE_TIME_MASK                          This defines the number of valid bits in the event trace 
+                                                time-stamp source defined previously. If the time-stamp 
+                                                source is 16-bits, this value should be 0xFFFF. Alternatively, 
+                                                if the time-stamp source is 32-bits, this value should be 
+                                                0xFFFFFFFF. This define is only pertinent if the ThreadX 
+                                                library is built with TX_ENABLE_EVENT_TRACE defined.
+
+
+
+6.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+breakpoints inside of ThreadX itself. Of course, this costs some 
+performance. To make it run faster, you can change the ThreadX library
+project to enable various compiler optimizations. 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+7.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-R5
+targets. There are a certain set of requirements that are defined in the 
+following sub-sections:
+
+
+7.1  Vector Area
+
+The Cortex-R5 vectors start at address zero. The demonstration system startup
+cstartup.s file contains the vectors and is loaded at address zero. 
+On actual hardware platforms, this area might have to be copied to address 0. 
+
+
+7.2  IRQ ISRs
+
+ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested
+IRQ interrupts. The following sub-sections define the IRQ capabilities.
+
+
+7.2.1 Standard IRQ ISRs
+
+The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ 
+interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following 
+is the default IRQ handler defined in tx_initialize_low_level.s:
+
+    PUBLIC  __tx_irq_handler
+    PUBLIC  __tx_irq_processing_return      
+__tx_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return
+;
+;    /* At this point execution is still in the IRQ mode. The CPSR, point of
+;       interrupt, and all C scratch registers are available for use. Note 
+;       that IRQ interrupts are still disabled upon return from the context
+;       save function.  */
+;
+;    /* Application ISR dispatch call goes here!  */
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.2.2 Vectored IRQ ISRs
+
+The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified
+by the particular implementation. The following is an example IRQ handler defined in 
+tx_initialize_low_level.s:
+
+
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_example_vectored_irq_handler
+__tx_example_vectored_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+    STMDB   sp!, {r0-r3}                    ; Save some scratch registers
+    MRS     r0, SPSR                        ; Pickup saved SPSR
+    SUB     lr, lr, #4                      ; Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}         ; Store other registers
+    BL      _tx_thread_vectored_context_save
+;
+;    /* At this point execution is still in the IRQ mode. The CPSR, point of
+;       interrupt, and all C scratch registers are available for use. Note 
+;       that IRQ interrupts are still disabled upon return from the context
+;       save function.  */
+;
+;    /* Application ISR dispatch call goes here!  */
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.2.3  Nested IRQ Support
+
+By default, nested IRQ interrupt support is not enabled. To enable nested
+IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING
+defined. With this defined, two new IRQ interrupt management services are
+available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end.
+These function should be called between the IRQ context save and restore
+calls. 
+
+Execution between the calls to _tx_thread_irq_nesting_start and 
+_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved 
+by switching from IRQ mode to SYS mode and enabling IRQ interrupts.
+The SYS mode stack is used during the SYS mode operation, which was 
+setup in tx_initialize_low_level.s. When nested IRQ interrupts are no 
+longer required, calling the _tx_thread_irq_nesting_end service disables 
+nesting by disabling IRQ interrupts and switching back to IRQ mode in 
+preparation for the IRQ context restore service.
+
+The following is an example of enabling IRQ nested interrupts in a standard 
+IRQ handler:
+
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_irq_handler
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_irq_processing_return      
+__tx_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return
+;
+;    /* At this point execution is still in the IRQ mode. The CPSR, point of
+;       interrupt, and all C scratch registers are available for use. Note 
+;       that IRQ interrupts are still disabled upon return from the context
+;       save function.  */
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start 
+;       from IRQ mode with interrupts disabled. This routine switches to the
+;       system mode and returns with IRQ interrupts enabled. 
+;       
+;       NOTE:  It is very important to ensure all IRQ interrupts are cleared 
+;       prior to enabling nested IRQ interrupts. */
+;
+    BL      _tx_thread_irq_nesting_start
+
+;    /* Application ISR dispatch call goes here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_context_restore. 
+;       This routine returns in processing in IRQ mode with interrupts disabled.  */
+;
+    BL      _tx_thread_irq_nesting_end
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.3  FIQ Interrupts
+
+By default, Cortex-R5 FIQ interrupts are left alone by ThreadX. Of course, this 
+means that the application is fully responsible for enabling the FIQ interrupt 
+and saving/restoring any registers used in the FIQ ISR processing. To globally 
+enable FIQ interrupts, the application should enable FIQ interrupts at the 
+beginning of a thread or before any threads are created in tx_application_define. 
+In addition, the application must ensure that no ThreadX service calls are made 
+from default FIQ ISRs, which is located in tx_initialize_low_level.s.
+
+
+7.3.1  Managed FIQ Interrupts
+
+ThreadX management of FIQ interrupts is not provided because FIQ interrupts
+cannot be disabled. The hardware does not support nested FIQ interrupts.
+
+
+8.  ThreadX Timer Interrupt
+
+ThreadX requires a periodic interrupt source to manage all time-slicing, 
+thread sleeps, timeouts, and application timers. Without such a timer 
+interrupt source, these services are not functional. However, all other
+ThreadX services are operational without a periodic timer source.
+
+To add the timer interrupt processing, simply make a call to _tx_timer_interrupt 
+in the IRQ processing.
+
+
+9.  Thumb/Cortex-R5 Mixed Mode
+
+By default, ThreadX is setup for running in Cortex-R5 32-bit mode. This is 
+also true for the demonstration system. It is possible to build any 
+ThreadX file and/or the application in Thumb mode. The only exception
+to this is the file tx_thread_shell_entry.c. This file must always be 
+built in 32-bit mode.
+
+
+10.  IAR Thread-safe Library Support
+
+Thread-safe support for the IAR tools is easily enabled by building the ThreadX library
+and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file
+should have the following line added (if not already in place):
+
+initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
+
+
+11.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX version for Cortex-R5 using IAR's ARM tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_r5/iar/src/tx_iar.c b/ports/cortex_r5/iar/src/tx_iar.c
new file mode 100644
index 00000000..11fcefb3
--- /dev/null
+++ b/ports/cortex_r5/iar/src/tx_iar.c
@@ -0,0 +1,804 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   IAR Multithreaded Library Support                                   */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Define IAR library for tools prior to version 8.  */
+
+#if (__VER__ < 8000000)
+
+
+/* IAR version 7 and below.  */
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_initialize.h"
+#include "tx_thread.h"
+#include "tx_mutex.h"
+
+
+/* This implementation requires that the following macros are defined in the 
+   tx_port.h file and  is included with the following code segments:
+   
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#include 
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_EXTENSION_2           VOID    *tx_thread_iar_tls_pointer;          
+#else
+#define TX_THREAD_EXTENSION_2          
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  __iar_dlib_perthread_allocate();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                    thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL;            
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               __iar_dlib_perthread_access(0);
+#else
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#endif
+
+    This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the 
+    application.  
+
+    Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected.
+*/
+
+#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
+
+#include 
+
+
+#if _MULTI_THREAD
+
+TX_MUTEX    __tx_iar_system_lock_mutexes[_MAX_LOCK];
+UINT        __tx_iar_system_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_system_lock_no_mutexes;
+UINT        __tx_iar_system_lock_internal_errors;
+UINT        __tx_iar_system_lock_isr_caller;
+
+
+/* Define the TLS access function for the IAR library.  */
+
+void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp)
+{
+
+char _DLIB_TLS_MEMORY   *p = 0;
+    
+    /* Is there a current thread?  */
+    if (_tx_thread_current_ptr)
+      p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer;
+    else
+      p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD");
+    p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp);
+    return (void _DLIB_TLS_MEMORY *) p;
+}
+
+
+/* Define mutexes for IAR library.  */
+
+void __iar_system_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_LOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_system_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_system_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_system_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_system_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_system_Mtxlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+}
+
+void __iar_system_Mtxunlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+}
+
+
+#if _DLIB_FILE_DESCRIPTOR
+
+TX_MUTEX    __tx_iar_file_lock_mutexes[_MAX_FLOCK];
+UINT        __tx_iar_file_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_file_lock_no_mutexes;
+UINT        __tx_iar_file_lock_internal_errors;
+UINT        __tx_iar_file_lock_isr_caller;
+
+
+void __iar_file_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_FLOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_file_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_file_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_file_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_file_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_file_Mtxlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+
+void __iar_file_Mtxunlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+#endif  /* _DLIB_FILE_DESCRIPTOR */
+
+#endif  /* _MULTI_THREAD  */
+
+#endif  /* TX_ENABLE_IAR_LIBRARY_SUPPORT  */
+
+#else   /* IAR version 8 and above.  */
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_initialize.h"
+#include "tx_thread.h"
+#include "tx_mutex.h"
+
+/* This implementation requires that the following macros are defined in the 
+   tx_port.h file and  is included with the following code segments:
+   
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#include 
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_EXTENSION_2           VOID    *tx_thread_iar_tls_pointer;          
+#else
+#define TX_THREAD_EXTENSION_2          
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+void    *_tx_iar_create_per_thread_tls_area(void);
+void    _tx_iar_destroy_per_thread_tls_area(void *tls_ptr);
+void    __iar_Initlocks(void);
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  __iar_dlib_perthread_allocate();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                        thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL; } while(0);
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               do {__iar_Initlocks();} while(0);
+#else
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#endif
+
+    This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the 
+    application.  
+
+    Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected.
+*/
+
+#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
+
+#include 
+
+
+void * __aeabi_read_tp();
+
+void* _tx_iar_create_per_thread_tls_area();
+void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr);
+
+#pragma section="__iar_tls$$DATA"
+
+/* Define the TLS access function for the IAR library.  */
+void * __aeabi_read_tp(void)
+{
+  void *p = 0;
+  TX_THREAD *thread_ptr = _tx_thread_current_ptr;
+  if (thread_ptr)
+  {
+    p = thread_ptr->tx_thread_iar_tls_pointer;      
+  }
+  else
+  {
+    p = __section_begin("__iar_tls$$DATA");
+  }
+  return p;
+}
+
+/* Define the TLS creation and destruction to use malloc/free.  */
+
+void* _tx_iar_create_per_thread_tls_area()
+{
+  UINT tls_size = __iar_tls_size();  
+  
+  /* Get memory for TLS.  */  
+  void *p = malloc(tls_size);
+
+  /* Initialize TLS-area and run constructors for objects in TLS */
+  __iar_tls_init(p);
+  return p;
+}
+
+void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr)
+{
+  /* Destroy objects living in TLS */
+  __call_thread_dtors();
+  free(tls_ptr);  
+}
+
+#ifndef _MAX_LOCK
+#define _MAX_LOCK 4
+#endif
+
+static TX_MUTEX    __tx_iar_system_lock_mutexes[_MAX_LOCK];
+static UINT        __tx_iar_system_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_system_lock_no_mutexes;
+UINT        __tx_iar_system_lock_internal_errors;
+UINT        __tx_iar_system_lock_isr_caller;
+
+
+/* Define mutexes for IAR library.  */
+
+void __iar_system_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_LOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_system_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_system_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_system_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_system_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_system_Mtxlock(__iar_Rmtx *m)
+{
+  if (*m)
+  {  
+    UINT    status;
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+  }
+}
+
+void __iar_system_Mtxunlock(__iar_Rmtx *m)
+{
+  if (*m)
+  {
+    UINT    status;
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+  }
+}
+
+
+#if _DLIB_FILE_DESCRIPTOR
+
+#include                         /* Added to get access to FOPEN_MAX */
+#ifndef _MAX_FLOCK
+#define _MAX_FLOCK FOPEN_MAX              /* Define _MAX_FLOCK as the maximum number of open files */
+#endif
+
+
+TX_MUTEX    __tx_iar_file_lock_mutexes[_MAX_FLOCK];
+UINT        __tx_iar_file_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_file_lock_no_mutexes;
+UINT        __tx_iar_file_lock_internal_errors;
+UINT        __tx_iar_file_lock_isr_caller;
+
+
+void __iar_file_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_FLOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_file_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_file_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_file_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_file_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_file_Mtxlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+
+void __iar_file_Mtxunlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+#endif  /* _DLIB_FILE_DESCRIPTOR */
+
+#endif  /* TX_ENABLE_IAR_LIBRARY_SUPPORT  */
+
+#endif /* IAR version 8 and above.  */
diff --git a/ports/cortex_r5/iar/src/tx_thread_context_restore.s b/ports/cortex_r5/iar/src/tx_thread_context_restore.s
new file mode 100644
index 00000000..3d28fdb5
--- /dev/null
+++ b/ports/cortex_r5/iar/src/tx_thread_context_restore.s
@@ -0,0 +1,247 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+
+SVC_MODE        DEFINE  0x13                    ; SVC mode
+IRQ_MODE        DEFINE  0x12                    ; IRQ mode
+DISABLE_INTS    DEFINE  0x80                    ; Disable IRQ interrupts
+THUMB_MASK      DEFINE  0x20                    ; Thumb bit mask
+
+;
+    EXTERN      _tx_thread_system_state
+    EXTERN      _tx_thread_current_ptr
+    EXTERN      _tx_thread_execute_ptr
+    EXTERN      _tx_timer_time_slice
+    EXTERN      _tx_thread_schedule
+    EXTERN      _tx_thread_preempt_disable
+    EXTERN      _tx_execution_isr_exit
+;
+;
+
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_context_restore                         Cortex-R5/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function restores the interrupt context if it is processing a  */ 
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */ 
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+;/*    if no thread was running, the function returns to the scheduler.    */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                   Thread scheduling routine     */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                  Interrupt Service Routines    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_restore(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_context_restore
+    ARM
+_tx_thread_context_restore
+;
+;    /* Lockout interrupts.  */
+;
+    CPSID   i                                   ; Disable IRQ interrupts
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR exit function to indicate an ISR is complete.  */
+;
+    BL      _tx_execution_isr_exit              ; Call the ISR exit function
+#endif
+;
+;    /* Determine if interrupts are nested.  */
+;    if (--_tx_thread_system_state)
+;    {
+;
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3]                            ; Pickup system state
+    SUB     r2, r2, #1                          ; Decrement the counter
+    STR     r2, [r3]                            ; Store the counter 
+    CMP     r2, #0                              ; Was this the first interrupt?
+    BEQ     __tx_thread_not_nested_restore      ; If so, not a nested restore
+;
+;    /* Interrupts are nested.  */
+;
+;    /* Just recover the saved registers and return to the point of 
+;       interrupt.  */
+;
+    LDMIA   sp!, {r0, r10, r12, lr}             ; Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       ; Put SPSR back
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOVS    pc, lr                              ; Return to point of interrupt
+;
+;    }
+__tx_thread_not_nested_restore
+;
+;    /* Determine if a thread was interrupted and no preemption is required.  */
+;    else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) 
+;               || (_tx_thread_preempt_disable))
+;    {
+;
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1]                            ; Pickup actual current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_idle_system_restore     ; Yes, idle system was interrupted
+;
+    LDR     r3, =_tx_thread_preempt_disable     ; Pickup preempt disable address
+    LDR     r2, [r3]                            ; Pickup actual preempt disable flag
+    CMP     r2, #0                              ; Is it set?
+    BNE     __tx_thread_no_preempt_restore      ; Yes, don't preempt this thread
+    LDR     r3, =_tx_thread_execute_ptr         ; Pickup address of execute thread ptr
+    LDR     r2, [r3]                            ; Pickup actual execute thread pointer
+    CMP     r0, r2                              ; Is the same thread highest priority?
+    BNE     __tx_thread_preempt_restore         ; No, preemption needs to happen
+;
+;
+__tx_thread_no_preempt_restore
+;
+;    /* Restore interrupted thread or ISR.  */
+;
+;    /* Pickup the saved stack pointer.  */
+;    tmp_ptr =  _tx_thread_current_ptr -> tx_thread_stack_ptr;
+;
+;   /* Recover the saved context and return to the point of interrupt.  */
+;
+    LDMIA   sp!, {r0, r10, r12, lr}             ; Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       ; Put SPSR back
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOVS    pc, lr                              ; Return to point of interrupt
+;
+;    }
+;    else
+;    {
+__tx_thread_preempt_restore
+;
+    LDMIA   sp!, {r3, r10, r12, lr}             ; Recover temporarily saved registers
+    MOV     r1, lr                              ; Save lr (point of interrupt)
+    CPS     #SVC_MODE                           ; Enter SVC mode
+    STR     r1, [sp, #-4]!                      ; Save point of interrupt
+    STMDB   sp!, {r4-r12, lr}                   ; Save upper half of registers
+    MOV     r4, r3                              ; Save SPSR in r4
+    CPS     #IRQ_MODE                           ; Enter IRQ mode
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    CPS     #SVC_MODE                           ; Enter SVC mode
+    STMDB   sp!, {r0-r3}                        ; Save r0-r3 on thread's stack
+
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        ; Pickup current thread pointer
+    
+#ifdef __ARMVFP__
+    LDR     r2, [r0, #144]                      ; Pickup the VFP enabled flag
+    CMP     r2, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_irq_vfp_save               ; No, skip VFP IRQ save
+    VMRS    r2, FPSCR                           ; Pickup the FPSCR
+    STR     r2, [sp, #-4]!                      ; Save FPSCR
+    VSTMDB  sp!, {D0-D15}                       ; Save D0-D15
+_tx_skip_irq_vfp_save
+#endif
+    
+    MOV     r3, #1                              ; Build interrupt stack type
+    STMDB   sp!, {r3, r4}                       ; Save interrupt stack type and SPSR
+    STR     sp, [r0, #8]                        ; Save stack pointer in thread control
+                                                ;   block
+    BIC     r4, r4, #THUMB_MASK                 ; Clear the Thumb bit of CPSR
+    ORR     r3, r4, #DISABLE_INTS               ; Or-in interrupt lockout bit(s)
+    MSR     CPSR_cxsf, r3                       ; Lockout interrupts
+;
+;    /* Save the remaining time-slice and disable it.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    LDR     r3, =_tx_timer_time_slice           ; Pickup time-slice variable address
+    LDR     r2, [r3]                            ; Pickup time-slice
+    CMP     r2, #0                              ; Is it active?
+    BEQ     __tx_thread_dont_save_ts            ; No, don't save it
+;
+;        _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+;        _tx_timer_time_slice =  0;
+;
+    STR     r2, [r0, #24]                       ; Save thread's time-slice
+    MOV     r2, #0                              ; Clear value
+    STR     r2, [r3]                            ; Disable global time-slice flag
+;
+;    }
+__tx_thread_dont_save_ts
+;
+;
+;    /* Clear the current task pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;
+    MOV     r0, #0                              ; NULL value
+    STR     r0, [r1]                            ; Clear current thread pointer
+;
+;    /* Return to the scheduler.  */
+;    _tx_thread_schedule();
+;
+    B       _tx_thread_schedule                 ; Return to scheduler
+;    }
+;
+__tx_thread_idle_system_restore
+;
+;    /* Just return back to the scheduler!  */
+;
+    CPS     #SVC_MODE                           ; Enter SVC mode
+    
+    B       _tx_thread_schedule                 ; Return to scheduler
+;}
+;
+;
+    END
+
diff --git a/ports/cortex_r5/iar/src/tx_thread_context_save.s b/ports/cortex_r5/iar/src/tx_thread_context_save.s
new file mode 100644
index 00000000..97b1d3cf
--- /dev/null
+++ b/ports/cortex_r5/iar/src/tx_thread_context_save.s
@@ -0,0 +1,198 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    EXTERN      _tx_thread_system_state
+    EXTERN      _tx_thread_current_ptr
+    EXTERN      __tx_irq_processing_return
+    EXTERN      _tx_execution_isr_enter
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_context_save                            Cortex-R5/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function saves the context of an executing thread in the       */ 
+;/*    beginning of interrupt processing.  The function also ensures that  */ 
+;/*    the system stack is used upon return to the calling ISR.            */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_save(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_context_save
+    ARM
+_tx_thread_context_save
+;
+;    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+;       out, we are in IRQ mode, and all registers are intact.  */
+;
+;    /* Check for a nested interrupt condition.  */
+;    if (_tx_thread_system_state++)
+;    {
+;
+    STMDB   sp!, {r0-r3}                        ; Save some working registers 
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3, #0]                        ; Pickup system state
+    CMP     r2, #0                              ; Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         ; Yes, not a nested context save
+;
+;    /* Nested interrupt condition.  */
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+;
+;   /* Save the rest of the scratch registers on the stack and return to the
+;      calling ISR.  */
+;
+    MRS     r0, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}             ; Store other registers
+;
+;    /* Return to the ISR.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+#endif
+
+    B       __tx_irq_processing_return          ; Continue IRQ processing 
+;
+__tx_thread_not_nested_save
+;    }
+;
+;    /* Otherwise, not nested, check to see if a thread was running.  */
+;    else if (_tx_thread_current_ptr)
+;    {
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        ; Pickup current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_idle_system_save        ; If so, interrupt occured in 
+                                                ;   scheduling loop - nothing needs saving!
+;
+;    /* Save minimal context of interrupted thread.  */
+;
+    MRS     r2, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r2, r10, r12, lr}             ; Store other registers
+;
+;    /* Save the current stack pointer in the thread's control block.  */
+;    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+;
+;    /* Switch to the system stack.  */
+;    sp =  _tx_thread_system_stack_ptr;
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+#endif
+
+    B       __tx_irq_processing_return          ; Continue IRQ processing 
+;
+;    }
+;    else
+;    {
+;
+__tx_thread_idle_system_save
+;
+;    /* Interrupt occurred in the scheduling loop.  */
+;
+;    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+;       processing.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+#endif
+
+    ADD     sp, sp, #16                         ; Recover saved registers
+    B       __tx_irq_processing_return          ; Continue IRQ processing  
+;
+;    }
+;}
+;
+
+;
+;
+    END
+
diff --git a/ports/cortex_r5/iar/src/tx_thread_interrupt_control.s b/ports/cortex_r5/iar/src/tx_thread_interrupt_control.s
new file mode 100644
index 00000000..ad3a6bae
--- /dev/null
+++ b/ports/cortex_r5/iar/src/tx_thread_interrupt_control.s
@@ -0,0 +1,97 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+
+INT_MASK        DEFINE      0x80                ; Interrupt bit mask
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_interrupt_control                       Cortex-R5/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for changing the interrupt lockout     */ 
+;/*    posture of the system.                                              */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    new_posture                           New interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    old_posture                           Old interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    Application Code                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_control(UINT new_posture)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_interrupt_control
+    ARM
+_tx_thread_interrupt_control
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    MRS     r3, CPSR                            ; Pickup current CPSR
+    BIC     r1, r3, #INT_MASK                   ; Clear interrupt lockout bits
+    ORR     r1, r1, r0                          ; Or-in new interrupt lockout bits
+;
+;    /* Apply the new interrupt posture.  */
+;
+    MSR     CPSR_cxsf, r1                       ; Setup new CPSR
+    AND     r0, r3, #INT_MASK                   ; Return previous interrupt mask
+    
+    BX      lr                                  ; Return to caller
+;
+;}
+;
+;
+    END
diff --git a/ports/cortex_r5/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_r5/iar/src/tx_thread_interrupt_disable.s
new file mode 100644
index 00000000..b795d14f
--- /dev/null
+++ b/ports/cortex_r5/iar/src/tx_thread_interrupt_disable.s
@@ -0,0 +1,89 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+DISABLE_INTS    DEFINE      0x80                ; IRQ interrupts disabled
+;
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_interrupt_disable                       Cortex-R5/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for disabling interrupts               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    old_posture                           Old interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    Application Code                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_disable(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC _tx_thread_interrupt_disable
+    ARM
+_tx_thread_interrupt_disable??rA
+_tx_thread_interrupt_disable
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    MRS     r0, CPSR                            ; Pickup current CPSR
+    CPSID   i                                   ; Mask interrupts
+    BX      lr                                  ; Return to caller
+;}
+;
+;
+    END
diff --git a/ports/cortex_r5/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_r5/iar/src/tx_thread_interrupt_restore.s
new file mode 100644
index 00000000..9fc7b4e4
--- /dev/null
+++ b/ports/cortex_r5/iar/src/tx_thread_interrupt_restore.s
@@ -0,0 +1,84 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_interrupt_restore                       Cortex-R5/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for restoring interrupts to the state  */ 
+;/*    returned by a previous _tx_thread_interrupt_disable call.           */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    old_posture                           Old interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    Application Code                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;void   _tx_thread_interrupt_restore(UINT old_posture)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_interrupt_restore
+    ARM
+_tx_thread_interrupt_restore
+;
+;    /* Apply the new interrupt posture.  */
+;
+    MSR     CPSR_cxsf, r0                       ; Setup new CPSR
+
+    BX      lr                                  ; Return to caller
+;}
+;
+    END
diff --git a/ports/cortex_r5/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_r5/iar/src/tx_thread_irq_nesting_end.s
new file mode 100644
index 00000000..e9bb5eee
--- /dev/null
+++ b/ports/cortex_r5/iar/src/tx_thread_irq_nesting_end.s
@@ -0,0 +1,99 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+IRQ_MODE        DEFINE  0x12                    ; IRQ mode
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_irq_nesting_end                         Cortex-R5/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is called by the application from IRQ mode after      */ 
+;/*    _tx_thread_irq_nesting_start has been called and switches the IRQ   */ 
+;/*    processing from system mode back to IRQ mode prior to the ISR       */ 
+;/*    calling _tx_thread_context_restore.  Note that this function        */ 
+;/*    assumes the system stack pointer is in the same position after      */ 
+;/*    nesting start function was called.                                  */ 
+;/*                                                                        */ 
+;/*    This function assumes that the system mode stack pointer was setup  */ 
+;/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+;/*                                                                        */ 
+;/*    This function returns with IRQ interrupts disabled.                 */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_irq_nesting_end(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_irq_nesting_end
+    ARM
+_tx_thread_irq_nesting_end
+    MOV     r3, lr                              ; Save ISR return address
+    CPSID   i                                   ; Disable interrupts
+    POP     {lr}                                ; Pickup saved lr
+    CPS     #IRQ_MODE                           ; Switch to IRQ mode
+    MOV     pc, r3                              ; Return to ISR
+;}
+;
+;
+    END
+
diff --git a/ports/cortex_r5/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_r5/iar/src/tx_thread_irq_nesting_start.s
new file mode 100644
index 00000000..70e6116b
--- /dev/null
+++ b/ports/cortex_r5/iar/src/tx_thread_irq_nesting_start.s
@@ -0,0 +1,96 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+SYS_MODE        DEFINE  0x1F                    ; System mode
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_irq_nesting_start                       Cortex-R5/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is called by the application from IRQ mode after      */ 
+;/*    _tx_thread_context_save has been called and switches the IRQ        */ 
+;/*    processing to the system mode so nested IRQ interrupt processing    */ 
+;/*    is possible (system mode has its own "lr" register).  Note that     */ 
+;/*    this function assumes that the system mode stack pointer was setup  */ 
+;/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+;/*                                                                        */ 
+;/*    This function returns with IRQ interrupts enabled.                  */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_irq_nesting_start(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_irq_nesting_start
+    ARM
+_tx_thread_irq_nesting_start
+    MOV     r3, lr                              ; Save ISR return address
+    CPS     #SYS_MODE                           ; Enter SYS mode
+    PUSH    {lr}                                ; Save system mode lr on the system mode stack
+    CPSIE   i                                   ; Enable interrupts
+    MOV     pc, r3                              ; Return to ISR
+;}
+;
+;
+    END
+
diff --git a/ports/cortex_r5/iar/src/tx_thread_schedule.s b/ports/cortex_r5/iar/src/tx_thread_schedule.s
new file mode 100644
index 00000000..14403ee3
--- /dev/null
+++ b/ports/cortex_r5/iar/src/tx_thread_schedule.s
@@ -0,0 +1,220 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    EXTERN     _tx_thread_execute_ptr
+    EXTERN     _tx_thread_current_ptr
+    EXTERN     _tx_timer_time_slice
+    EXTERN     _tx_execution_thread_enter
+;
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                                Cortex-R5/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function waits for a thread control block pointer to appear in */ 
+;/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */ 
+;/*    in the variable, the corresponding thread is resumed.               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_kernel_enter          ThreadX entry function         */ 
+;/*    _tx_thread_system_return             Return to system from thread   */ 
+;/*    _tx_thread_context_restore           Restore thread's context       */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_schedule(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_schedule
+    ARM
+_tx_thread_schedule??rA
+_tx_thread_schedule
+;
+;    /* Enable interrupts.  */
+;
+    CPSIE   i                                   ; Enable IRQ interrupts
+
+;
+;    /* Wait for a thread to execute.  */
+;    do
+;    {
+    LDR     r1, =_tx_thread_execute_ptr         ; Address of thread execute ptr
+;
+__tx_thread_schedule_loop
+;
+    LDR     r0, [r1, #0]                        ; Pickup next thread to execute
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_schedule_loop           ; If so, keep looking for a thread
+;
+;    }
+;    while(_tx_thread_execute_ptr == TX_NULL);
+;    
+;    /* Yes! We have a thread to execute.  Lockout interrupts and
+;       transfer control to it.  */
+;
+    CPSID   i                                   ; Disable interrupts
+;
+;    /* Setup the current thread pointer.  */
+;    _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+;
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread 
+    STR     r0, [r1, #0]                        ; Setup current thread pointer
+;
+;    /* Increment the run count for this thread.  */
+;    _tx_thread_current_ptr -> tx_thread_run_count++;
+;
+    LDR     r2, [r0, #4]                        ; Pickup run counter
+    LDR     r3, [r0, #24]                       ; Pickup time-slice for this thread
+    ADD     r2, r2, #1                          ; Increment thread run-counter
+    STR     r2, [r0, #4]                        ; Store the new run counter
+;
+;    /* Setup time-slice, if present.  */
+;    _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+;
+    LDR     r2, =_tx_timer_time_slice           ; Pickup address of time slice 
+                                                ;   variable
+    LDR     sp, [r0, #8]                        ; Switch stack pointers
+    STR     r3, [r2, #0]                        ; Setup time-slice
+;
+;    /* Switch to the thread's stack.  */
+;    sp =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;
+;
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread entry function to indicate the thread is executing.  */
+;
+    MOV     r5, r0                              ; Save r0
+    BL      _tx_execution_thread_enter          ; Call the thread execution enter function
+    MOV     r0, r5                              ; Restore r0
+#endif
+;
+;    /* Determine if an interrupt frame or a synchronous task suspension frame
+;   is present.  */
+;
+    LDMIA   sp!, {r4, r5}                       ; Pickup the stack type and saved CPSR
+    CMP     r4, #0                              ; Check for synchronous context switch
+    BEQ     _tx_solicited_return
+    MSR     SPSR_cxsf, r5                       ; Setup SPSR for return
+#ifdef __ARMVFP__
+    LDR     r1, [r0, #144]                      ; Pickup the VFP enabled flag
+    CMP     r1, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_interrupt_vfp_restore      ; No, skip VFP interrupt restore
+    VLDMIA  sp!, {D0-D15}                       ; Recover D0-D15
+    LDR     r4, [sp], #4                        ; Pickup FPSCR
+    VMSR    FPSCR, r4                           ; Restore FPSCR
+_tx_skip_interrupt_vfp_restore:
+#endif
+    LDMIA   sp!, {r0-r12, lr, pc}^              ; Return to point of thread interrupt
+
+_tx_solicited_return:
+#ifdef __ARMVFP__
+    LDR     r1, [r0, #144]                      ; Pickup the VFP enabled flag
+    CMP     r1, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_solicited_vfp_restore      ; No, skip VFP solicited restore
+    VLDMIA  sp!, {D8-D15}                       ; Recover D8-D15
+    LDR     r4, [sp], #4                        ; Pickup FPSCR
+    VMSR    FPSCR, r4                           ; Restore FPSCR
+_tx_skip_solicited_vfp_restore:
+#endif
+    MOV     r0, r5                              ; Move CPSR to scratch register
+    LDMIA   sp!, {r4-r11, lr}                   ; Return to thread synchronously
+    MSR     CPSR_cxsf, r0                       ; Recover CPSR
+
+    BX      lr                                  ; Return to caller
+;
+;}
+;
+
+#ifdef __ARMVFP__
+    PUBLIC  tx_thread_vfp_enable
+    CODE32
+tx_thread_vfp_enable??rA    
+tx_thread_vfp_enable
+    MRS     r2, CPSR                            ; Pickup the CPSR
+    CPSID   i                                   ; Disable IRQ interrupts
+    LDR     r0, =_tx_thread_current_ptr         ; Build current thread pointer address
+    LDR     r1, [r0]                            ; Pickup current thread pointer
+    CMP     r1, #0                              ; Check for NULL thread pointer
+    BEQ     __tx_no_thread_to_enable            ; If NULL, skip VFP enable
+    MOV     r0, #1                              ; Build enable value
+    STR     r0, [r1, #144]                      ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
+__tx_no_thread_to_enable:
+    MSR     CPSR_cxsf, r2                       ; Recover CPSR
+    BX      LR                                  ; Return to caller
+
+    PUBLIC  tx_thread_vfp_disable
+    CODE32
+tx_thread_vfp_disable??rA    
+tx_thread_vfp_disable
+    MRS     r2, CPSR                            ; Pickup the CPSR
+    CPSID   i                                   ; Disable IRQ interrupts
+    LDR     r0, =_tx_thread_current_ptr         ; Build current thread pointer address
+    LDR     r1, [r0]                            ; Pickup current thread pointer
+    CMP     r1, #0                              ; Check for NULL thread pointer
+    BEQ     __tx_no_thread_to_disable           ; If NULL, skip VFP disable
+    MOV     r0, #0                              ; Build disable value
+    STR     r0, [r1, #144]                      ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
+__tx_no_thread_to_disable:
+    MSR     CPSR_cxsf, r2                       ; Recover CPSR
+    BX      LR                                  ; Return to caller
+#endif
+
+    END
+
diff --git a/ports/cortex_r5/iar/src/tx_thread_stack_build.s b/ports/cortex_r5/iar/src/tx_thread_stack_build.s
new file mode 100644
index 00000000..b09b4f98
--- /dev/null
+++ b/ports/cortex_r5/iar/src/tx_thread_stack_build.s
@@ -0,0 +1,151 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+SVC_MODE        DEFINE  0x13                    ; SVC mode
+CPSR_MASK       DEFINE  0x9F                    ; Mask initial CPSR, IRQ ints enabled
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_stack_build                             Cortex-R5/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function builds a stack frame on the supplied thread's stack.  */ 
+;/*    The stack frame results in a fake interrupt return to the supplied  */ 
+;/*    function pointer.                                                   */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    thread_ptr                            Pointer to thread control blk */ 
+;/*    function_ptr                          Pointer to return function    */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_thread_create                     Create thread service         */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_stack_build
+    
+    ARM
+_tx_thread_stack_build
+;
+;       
+;    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+;       on the Cortex-R5 should look like the following after it is built:
+;       
+;       Stack Top:      1           Interrupt stack frame type
+;                       CPSR        Initial value for CPSR
+;                       a1 (r0)     Initial value for a1
+;                       a2 (r1)     Initial value for a2
+;                       a3 (r2)     Initial value for a3
+;                       a4 (r3)     Initial value for a4
+;                       v1 (r4)     Initial value for v1
+;                       v2 (r5)     Initial value for v2
+;                       v3 (r6)     Initial value for v3
+;                       v4 (r7)     Initial value for v4
+;                       v5 (r8)     Initial value for v5
+;                       sb (r9)     Initial value for sb
+;                       sl (r10)    Initial value for sl
+;                       fp (r11)    Initial value for fp
+;                       ip (r12)    Initial value for ip
+;                       lr (r14)    Initial value for lr
+;                       pc (r15)    Initial value for pc
+;                       0           For stack backtracing
+;
+;    Stack Bottom: (higher memory address)  */
+;
+    LDR     r2, [r0, #16]                       ; Pickup end of stack area
+    BIC     r2, r2, #7                          ; Ensure 8-byte alignment
+    SUB     r2, r2, #76                         ; Allocate space for the stack frame
+;
+;    /* Actually build the stack frame.  */
+;
+    MOV     r3, #1                              ; Build interrupt stack type
+    STR     r3, [r2, #0]                        ; Store stack type
+    MOV     r3, #0                              ; Build initial register value
+    STR     r3, [r2, #8]                        ; Store initial r0
+    STR     r3, [r2, #12]                       ; Store initial r1
+    STR     r3, [r2, #16]                       ; Store initial r2
+    STR     r3, [r2, #20]                       ; Store initial r3
+    STR     r3, [r2, #24]                       ; Store initial r4
+    STR     r3, [r2, #28]                       ; Store initial r5
+    STR     r3, [r2, #32]                       ; Store initial r6
+    STR     r3, [r2, #36]                       ; Store initial r7
+    STR     r3, [r2, #40]                       ; Store initial r8
+    STR     r3, [r2, #44]                       ; Store initial r9
+    LDR     r3, [r0, #12]                       ; Pickup stack starting address
+    STR     r3, [r2, #48]                       ; Store initial r10 (sl)
+    MOV     r3, #0                              ; Build initial register value
+    STR     r3, [r2, #52]                       ; Store initial r11
+    STR     r3, [r2, #56]                       ; Store initial r12
+    STR     r3, [r2, #60]                       ; Store initial lr
+    STR     r1, [r2, #64]                       ; Store initial pc
+    STR     r3, [r2, #68]                       ; 0 for back-trace
+    MRS     r1, CPSR                            ; Pickup CPSR
+    BIC     r1, r1, #CPSR_MASK                  ; Mask mode bits of CPSR
+    ORR     r3, r1, #SVC_MODE                   ; Build CPSR, SVC mode, interrupts enabled
+    STR     r3, [r2, #4]                        ; Store initial CPSR
+;
+;    /* Setup stack pointer.  */
+;    thread_ptr -> tx_thread_stack_ptr =  r2;
+;
+    STR     r2, [r0, #8]                        ; Save stack pointer in thread's
+                                                ;   control block
+
+    BX      lr                                  ; Return to caller
+;}
+    END
+
diff --git a/ports/cortex_r5/iar/src/tx_thread_system_return.s b/ports/cortex_r5/iar/src/tx_thread_system_return.s
new file mode 100644
index 00000000..fbd5b756
--- /dev/null
+++ b/ports/cortex_r5/iar/src/tx_thread_system_return.s
@@ -0,0 +1,155 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+;
+    EXTERN      _tx_thread_current_ptr
+    EXTERN      _tx_timer_time_slice
+    EXTERN      _tx_thread_schedule
+    EXTERN      _tx_execution_thread_exit
+;
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_system_return                           Cortex-R5/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is target processor specific.  It is used to transfer */ 
+;/*    control from a thread back to the ThreadX system.  Only a           */ 
+;/*    minimal context is saved since the compiler assumes temp registers  */ 
+;/*    are going to get slicked by a function call anyway.                 */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                   Thread scheduling loop        */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ThreadX components                                                  */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_system_return(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_system_return
+    ARM
+_tx_thread_system_return??rA
+_tx_thread_system_return
+;
+;   /* Lockout interrupts.  */
+;
+    MRS     r1, CPSR                            ; Pickup the CPSR
+    CPSID   i                                   ; Disable interrupts
+;    /* Save minimal context on the stack.  */
+;
+    STMDB   sp!, {r4-r11, lr}                   ; Save minimal context
+    LDR     r5, =_tx_thread_current_ptr         ; Pickup address of current ptr
+    LDR     r6, [r5, #0]                        ; Pickup current thread pointer
+
+#ifdef __ARMVFP__
+    LDR     r0, [r6, #144]                      ; Pickup the VFP enabled flag
+    CMP     r0, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_solicited_vfp_save         ; No, skip VFP solicited save
+    VMRS    r4, FPSCR                           ; Pickup the FPSCR
+    STR     r4, [sp, #-4]!                      ; Save FPSCR
+    VSTMDB  sp!, {D8-D15}                       ; Save D8-D15
+_tx_skip_solicited_vfp_save:
+#endif
+
+    MOV     r0, #0                              ; Build a solicited stack type
+    STMDB   sp!, {r0-r1}                        ; Save type and CPSR
+;   
+;
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread exit function to indicate the thread is no longer executing.  */
+;
+    BL      _tx_execution_thread_exit           ; Call the thread exit function
+#endif
+
+    LDR     r2, =_tx_timer_time_slice           ; Pickup address of time slice
+    LDR     r1, [r2, #0]                        ; Pickup current time slice
+;
+;    /* Save current stack and switch to system stack.  */
+;    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+;    sp = _tx_thread_system_stack_ptr;
+;
+    STR     sp, [r6, #8]                        ; Save thread stack pointer
+;
+;    /* Determine if the time-slice is active.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    MOV     r4, #0                              ; Build clear value
+    CMP     r1, #0                              ; Is a time-slice active?
+    BEQ     __tx_thread_dont_save_ts            ; No, don't save the time-slice
+;
+;       /* Save time-slice for the thread and clear the current time-slice.  */
+;       _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+;       _tx_timer_time_slice =  0;
+;
+    STR     r4, [r2, #0]                        ; Clear time-slice
+    STR     r1, [r6, #24]                       ; Save current time-slice
+;
+;    }
+__tx_thread_dont_save_ts
+;
+;    /* Clear the current thread pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;
+    STR     r4, [r5, #0]                        ; Clear current thread pointer
+    B       _tx_thread_schedule                 ; Jump to scheduler!
+;
+;}
+    END
+
diff --git a/ports/cortex_r5/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_r5/iar/src/tx_thread_vectored_context_save.s
new file mode 100644
index 00000000..ebc54f54
--- /dev/null
+++ b/ports/cortex_r5/iar/src/tx_thread_vectored_context_save.s
@@ -0,0 +1,184 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    EXTERN      _tx_thread_system_state
+    EXTERN      _tx_thread_current_ptr
+    EXTERN      _tx_execution_isr_enter
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_vectored_context_save                  Cortex-R5/IAR     */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function saves the context of an executing thread in the       */ 
+;/*    beginning of interrupt processing.  The function also ensures that  */ 
+;/*    the system stack is used upon return to the calling ISR.            */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_vectored_context_save(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_vectored_context_save
+    ARM
+_tx_thread_vectored_context_save
+;
+;    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+;       out, we are in IRQ mode, the minimal context is already saved, and the
+;       lr register contains the return ISR address.  */
+;
+;    /* Check for a nested interrupt condition.  */
+;    if (_tx_thread_system_state++)
+;    {
+;
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3, #0]                        ; Pickup system state
+    CMP     r2, #0                              ; Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         ; Yes, not a nested context save
+;
+;    /* Nested interrupt condition.  */
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+;
+;    /* Note: Minimal context of interrupted thread is already saved.  */
+;
+;    /* Return to the ISR.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+#endif
+
+    BX      lr                                  ; Return to caller
+;
+__tx_thread_not_nested_save
+;    }
+;
+;    /* Otherwise, not nested, check to see if a thread was running.  */
+;    else if (_tx_thread_current_ptr)
+;    {
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        ; Pickup current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_idle_system_save        ; If so, interrupt occured in 
+                                                ;   scheduling loop - nothing needs saving!
+;
+;    /* Note: Minimal context of interrupted thread is already saved.  */
+;
+;    /* Save the current stack pointer in the thread's control block.  */
+;    _tx_thread_current_ptr -> tx_stack_ptr =  sp;
+;
+;    /* Switch to the system stack.  */
+;    sp =  _tx_thread_system_stack_ptr;
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+#endif
+
+    BX      lr                                  ; Return to caller
+;
+;    }
+;    else
+;    {
+;
+__tx_thread_idle_system_save
+;
+;    /* Interrupt occurred in the scheduling loop.  */
+;
+;    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+;       processing.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+#endif
+
+    ADD     sp, sp, #32                         ; Recover saved registers
+    MOV     pc, lr                              ; Return to caller
+;
+;    }
+;}
+    END
+
diff --git a/ports/cortex_r5/iar/src/tx_timer_interrupt.s b/ports/cortex_r5/iar/src/tx_timer_interrupt.s
new file mode 100644
index 00000000..007fc2aa
--- /dev/null
+++ b/ports/cortex_r5/iar/src/tx_timer_interrupt.s
@@ -0,0 +1,256 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Timer                                                               */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_timer.h"
+;#include "tx_thread.h"
+;
+;
+;Define Assembly language external references...
+;
+    EXTERN      _tx_timer_time_slice
+    EXTERN      _tx_timer_system_clock
+    EXTERN      _tx_timer_current_ptr
+    EXTERN      _tx_timer_list_start
+    EXTERN      _tx_timer_list_end
+    EXTERN      _tx_timer_expired_time_slice
+    EXTERN      _tx_timer_expired
+    EXTERN      _tx_thread_time_slice
+    EXTERN      _tx_timer_expiration_process
+;
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_timer_interrupt                               Cortex-R5/IAR     */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function processes the hardware timer interrupt.  This         */ 
+;/*    processing includes incrementing the system clock and checking for  */ 
+;/*    time slice and/or timer expiration.  If either is found, the        */ 
+;/*    interrupt context save/restore functions are called along with the  */ 
+;/*    expiration functions.                                               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_timer_expiration_process          Timer expiration processing   */ 
+;/*    _tx_thread_time_slice                 Time-slice interrupted thread */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    interrupt vector                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_timer_interrupt(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_timer_interrupt
+    ARM
+_tx_timer_interrupt
+;
+;    /* Upon entry to this routine, it is assumed that context save has already
+;       been called, and therefore the compiler scratch registers are available
+;       for use.  */
+;
+;    /* Increment the system clock.  */
+;    _tx_timer_system_clock++;
+;
+    LDR     r1, =_tx_timer_system_clock         ; Pickup address of system clock
+    LDR     r0, [r1, #0]                        ; Pickup system clock
+    ADD     r0, r0, #1                          ; Increment system clock
+    STR     r0, [r1, #0]                        ; Store new system clock
+;
+;    /* Test for time-slice expiration.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    LDR     r3, =_tx_timer_time_slice           ; Pickup address of time-slice 
+    LDR     r2, [r3, #0]                        ; Pickup time-slice
+    CMP     r2, #0                              ; Is it non-active?
+    BEQ     __tx_timer_no_time_slice            ; Yes, skip time-slice processing
+;
+;       /* Decrement the time_slice.  */
+;       _tx_timer_time_slice--;
+;
+    SUB     r2, r2, #1                          ; Decrement the time-slice
+    STR     r2, [r3, #0]                        ; Store new time-slice value
+;
+;       /* Check for expiration.  */
+;       if (__tx_timer_time_slice == 0)
+;
+    CMP     r2, #0                              ; Has it expired?
+    BNE     __tx_timer_no_time_slice            ; No, skip expiration processing
+;
+;       /* Set the time-slice expired flag.  */
+;       _tx_timer_expired_time_slice =  TX_TRUE;
+;
+    LDR     r3, =_tx_timer_expired_time_slice   ; Pickup address of expired flag
+    MOV     r0, #1                              ; Build expired value
+    STR     r0, [r3, #0]                        ; Set time-slice expiration flag
+;
+;    }
+;
+__tx_timer_no_time_slice
+;
+;    /* Test for timer expiration.  */
+;    if (*_tx_timer_current_ptr)
+;    {
+;
+    LDR     r1, =_tx_timer_current_ptr          ; Pickup current timer pointer addr
+    LDR     r0, [r1, #0]                        ; Pickup current timer
+    LDR     r2, [r0, #0]                        ; Pickup timer list entry
+    CMP     r2, #0                              ; Is there anything in the list?
+    BEQ     __tx_timer_no_timer                 ; No, just increment the timer
+;
+;        /* Set expiration flag.  */
+;        _tx_timer_expired =  TX_TRUE;
+;
+    LDR     r3, =_tx_timer_expired              ; Pickup expiration flag address
+    MOV     r2, #1                              ; Build expired value
+    STR     r2, [r3, #0]                        ; Set expired flag
+    B       __tx_timer_done                     ; Finished timer processing
+;
+;    }
+;    else
+;    {
+__tx_timer_no_timer
+;
+;        /* No timer expired, increment the timer pointer.  */
+;        _tx_timer_current_ptr++;
+;
+    ADD     r0, r0, #4                          ; Move to next timer
+;
+;        /* Check for wrap-around.  */
+;        if (_tx_timer_current_ptr == _tx_timer_list_end)
+;
+    LDR     r3, =_tx_timer_list_end             ; Pickup addr of timer list end
+    LDR     r2, [r3, #0]                        ; Pickup list end
+    CMP     r0, r2                              ; Are we at list end?
+    BNE     __tx_timer_skip_wrap                ; No, skip wrap-around logic
+;
+;            /* Wrap to beginning of list.  */
+;            _tx_timer_current_ptr =  _tx_timer_list_start;
+;
+    LDR     r3, =_tx_timer_list_start           ; Pickup addr of timer list start
+    LDR     r0, [r3, #0]                        ; Set current pointer to list start
+;
+__tx_timer_skip_wrap
+;
+    STR     r0, [r1, #0]                        ; Store new current timer pointer
+;    }
+;
+__tx_timer_done
+;
+;
+;    /* See if anything has expired.  */
+;    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+;    {
+;
+    LDR     r3, =_tx_timer_expired_time_slice   ; Pickup addr of expired flag
+    LDR     r2, [r3, #0]                        ; Pickup time-slice expired flag
+    CMP     r2, #0                              ; Did a time-slice expire?
+    BNE     __tx_something_expired              ; If non-zero, time-slice expired
+    LDR     r1, =_tx_timer_expired              ; Pickup addr of other expired flag
+    LDR     r0, [r1, #0]                        ; Pickup timer expired flag
+    CMP     r0, #0                              ; Did a timer expire?
+    BEQ     __tx_timer_nothing_expired          ; No, nothing expired
+;
+__tx_something_expired
+;
+;
+    STMDB   sp!, {r0, lr}                       ; Save the lr register on the stack
+                                                ;   and save r0 just to keep 8-byte alignment
+;
+;    /* Did a timer expire?  */
+;    if (_tx_timer_expired)
+;    {
+;
+    LDR     r1, =_tx_timer_expired              ; Pickup addr of expired flag
+    LDR     r0, [r1, #0]                        ; Pickup timer expired flag
+    CMP     r0, #0                              ; Check for timer expiration
+    BEQ     __tx_timer_dont_activate            ; If not set, skip timer activation
+;
+;        /* Process timer expiration.  */
+;        _tx_timer_expiration_process();
+;
+    BL      _tx_timer_expiration_process        ; Call the timer expiration handling routine
+;
+;    }
+__tx_timer_dont_activate
+;
+;    /* Did time slice expire?  */
+;    if (_tx_timer_expired_time_slice)
+;    {
+;
+    LDR     r3, =_tx_timer_expired_time_slice   ; Pickup addr of time-slice expired 
+    LDR     r2, [r3, #0]                        ; Pickup the actual flag
+    CMP     r2, #0                              ; See if the flag is set
+    BEQ     __tx_timer_not_ts_expiration        ; No, skip time-slice processing
+;
+;        /* Time slice interrupted thread.  */
+;        _tx_thread_time_slice(); 
+
+    BL      _tx_thread_time_slice               ; Call time-slice processing
+;
+;    }
+;
+__tx_timer_not_ts_expiration
+;
+;
+    LDMIA   sp!, {r0, lr}                       ; Recover lr register (r0 is just there for
+                                                ;   the 8-byte stack alignment
+;
+;    }
+;
+__tx_timer_nothing_expired
+;
+    BX      lr                                  ; Return to caller
+;
+;}
+    END
+
diff --git a/ports/linux/gnu/example_build/file_list.mk b/ports/linux/gnu/example_build/file_list.mk
new file mode 100644
index 00000000..73497590
--- /dev/null
+++ b/ports/linux/gnu/example_build/file_list.mk
@@ -0,0 +1,201 @@
+LINUX_SRCS = \
+tx_initialize_low_level.c \
+tx_thread_context_restore.c \
+tx_thread_context_save.c \
+tx_thread_interrupt_control.c \
+tx_thread_schedule.c \
+tx_thread_stack_build.c \
+tx_thread_system_return.c \
+tx_timer_interrupt.c \
+
+LINUX_OBJS = $(LINUX_SRCS:%.c=.tmp/%.o)
+
+
+GENERIC_SRCS = \
+tx_block_allocate.c \
+tx_block_pool_cleanup.c \
+tx_block_pool_create.c \
+tx_block_pool_delete.c \
+tx_block_pool_info_get.c \
+tx_block_pool_initialize.c \
+tx_block_pool_performance_info_get.c \
+tx_block_pool_performance_system_info_get.c \
+tx_block_pool_prioritize.c \
+tx_block_release.c \
+tx_byte_allocate.c \
+tx_byte_pool_cleanup.c \
+tx_byte_pool_create.c \
+tx_byte_pool_delete.c \
+tx_byte_pool_info_get.c \
+tx_byte_pool_initialize.c \
+tx_byte_pool_performance_info_get.c \
+tx_byte_pool_performance_system_info_get.c \
+tx_byte_pool_prioritize.c \
+tx_byte_pool_search.c \
+tx_byte_release.c \
+txe_block_allocate.c \
+txe_block_pool_create.c \
+txe_block_pool_delete.c \
+txe_block_pool_info_get.c \
+txe_block_pool_prioritize.c \
+txe_block_release.c \
+txe_byte_allocate.c \
+txe_byte_pool_create.c \
+txe_byte_pool_delete.c \
+txe_byte_pool_info_get.c \
+txe_byte_pool_prioritize.c \
+txe_byte_release.c \
+txe_event_flags_create.c \
+txe_event_flags_delete.c \
+txe_event_flags_get.c \
+txe_event_flags_info_get.c \
+txe_event_flags_set.c \
+txe_event_flags_set_notify.c \
+txe_mutex_create.c \
+txe_mutex_delete.c \
+txe_mutex_get.c \
+txe_mutex_info_get.c \
+txe_mutex_prioritize.c \
+txe_mutex_put.c \
+txe_queue_create.c \
+txe_queue_delete.c \
+txe_queue_flush.c \
+txe_queue_front_send.c \
+txe_queue_info_get.c \
+txe_queue_prioritize.c \
+txe_queue_receive.c \
+txe_queue_send.c \
+txe_queue_send_notify.c \
+txe_semaphore_ceiling_put.c \
+txe_semaphore_create.c \
+txe_semaphore_delete.c \
+txe_semaphore_get.c \
+txe_semaphore_info_get.c \
+txe_semaphore_prioritize.c \
+txe_semaphore_put.c \
+txe_semaphore_put_notify.c \
+txe_thread_create.c \
+txe_thread_delete.c \
+txe_thread_entry_exit_notify.c \
+txe_thread_info_get.c \
+txe_thread_preemption_change.c \
+txe_thread_priority_change.c \
+txe_thread_relinquish.c \
+txe_thread_reset.c \
+txe_thread_resume.c \
+txe_thread_suspend.c \
+txe_thread_terminate.c \
+txe_thread_time_slice_change.c \
+txe_thread_wait_abort.c \
+txe_timer_activate.c \
+txe_timer_change.c \
+txe_timer_create.c \
+txe_timer_deactivate.c \
+txe_timer_delete.c \
+txe_timer_info_get.c \
+tx_event_flags_cleanup.c \
+tx_event_flags_create.c \
+tx_event_flags_delete.c \
+tx_event_flags_get.c \
+tx_event_flags_info_get.c \
+tx_event_flags_initialize.c \
+tx_event_flags_performance_info_get.c \
+tx_event_flags_performance_system_info_get.c \
+tx_event_flags_set.c \
+tx_event_flags_set_notify.c \
+tx_initialize_high_level.c \
+tx_initialize_kernel_enter.c \
+tx_initialize_kernel_setup.c \
+tx_misra.c \
+tx_mutex_cleanup.c \
+tx_mutex_create.c \
+tx_mutex_delete.c \
+tx_mutex_get.c \
+tx_mutex_info_get.c \
+tx_mutex_initialize.c \
+tx_mutex_performance_info_get.c \
+tx_mutex_performance_system_info_get.c \
+tx_mutex_prioritize.c \
+tx_mutex_priority_change.c \
+tx_mutex_put.c \
+tx_queue_cleanup.c \
+tx_queue_create.c \
+tx_queue_delete.c \
+tx_queue_flush.c \
+tx_queue_front_send.c \
+tx_queue_info_get.c \
+tx_queue_initialize.c \
+tx_queue_performance_info_get.c \
+tx_queue_performance_system_info_get.c \
+tx_queue_prioritize.c \
+tx_queue_receive.c \
+tx_queue_send.c \
+tx_queue_send_notify.c \
+tx_semaphore_ceiling_put.c \
+tx_semaphore_cleanup.c \
+tx_semaphore_create.c \
+tx_semaphore_delete.c \
+tx_semaphore_get.c \
+tx_semaphore_info_get.c \
+tx_semaphore_initialize.c \
+tx_semaphore_performance_info_get.c \
+tx_semaphore_performance_system_info_get.c \
+tx_semaphore_prioritize.c \
+tx_semaphore_put.c \
+tx_semaphore_put_notify.c \
+tx_thread_create.c \
+tx_thread_delete.c \
+tx_thread_entry_exit_notify.c \
+tx_thread_identify.c \
+tx_thread_info_get.c \
+tx_thread_initialize.c \
+tx_thread_performance_info_get.c \
+tx_thread_performance_system_info_get.c \
+tx_thread_preemption_change.c \
+tx_thread_priority_change.c \
+tx_thread_relinquish.c \
+tx_thread_reset.c \
+tx_thread_resume.c \
+tx_thread_shell_entry.c \
+tx_thread_sleep.c \
+tx_thread_stack_analyze.c \
+tx_thread_stack_error_handler.c \
+tx_thread_stack_error_notify.c \
+tx_thread_suspend.c \
+tx_thread_system_preempt_check.c \
+tx_thread_system_resume.c \
+tx_thread_system_suspend.c \
+tx_thread_terminate.c \
+tx_thread_timeout.c \
+tx_thread_time_slice.c \
+tx_thread_time_slice_change.c \
+tx_thread_wait_abort.c \
+tx_time_get.c \
+tx_timer_activate.c \
+tx_timer_change.c \
+tx_timer_create.c \
+tx_timer_deactivate.c \
+tx_timer_delete.c \
+tx_timer_expiration_process.c \
+tx_timer_info_get.c \
+tx_timer_initialize.c \
+tx_timer_performance_info_get.c \
+tx_timer_performance_system_info_get.c \
+tx_timer_system_activate.c \
+tx_timer_system_deactivate.c \
+tx_timer_thread_entry.c \
+tx_time_set.c \
+tx_trace_buffer_full_notify.c \
+tx_trace_disable.c \
+tx_trace_enable.c \
+tx_trace_event_filter.c \
+tx_trace_event_unfilter.c \
+tx_trace_initialize.c \
+tx_trace_interrupt_control.c \
+tx_trace_isr_enter_insert.c \
+tx_trace_isr_exit_insert.c \
+tx_trace_object_register.c \
+tx_trace_object_unregister.c \
+tx_trace_user_event_insert.c \
+
+GENERIC_OBJS = $(GENERIC_SRCS:%.c=.tmp/generic/%.o)
diff --git a/ports/linux/gnu/example_build/sample_threadx.c b/ports/linux/gnu/example_build/sample_threadx.c
new file mode 100644
index 00000000..080be3c4
--- /dev/null
+++ b/ports/linux/gnu/example_build/sample_threadx.c
@@ -0,0 +1,380 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include   "tx_api.h"
+#include   
+
+#define     DEMO_STACK_SIZE         1024
+#define     DEMO_BYTE_POOL_SIZE     9120
+#define     DEMO_BLOCK_POOL_SIZE    100
+#define     DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG           thread_0_counter;
+ULONG           thread_1_counter;
+ULONG           thread_1_messages_sent;
+ULONG           thread_2_counter;
+ULONG           thread_2_messages_received;
+ULONG           thread_3_counter;
+ULONG           thread_4_counter;
+ULONG           thread_5_counter;
+ULONG           thread_6_counter;
+ULONG           thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+/* Define main entry point.  */
+
+int main()
+{
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Print results.  */
+        printf("**** ThreadX Linux Demonstration **** (c) 1996-2020 Microsoft Corporation\n\n");
+        printf("           thread 0 events sent:          %lu\n", thread_0_counter);
+        printf("           thread 1 messages sent:        %lu\n", thread_1_counter);
+        printf("           thread 2 messages received:    %lu\n", thread_2_counter);
+        printf("           thread 3 obtained semaphore:   %lu\n", thread_3_counter);
+        printf("           thread 4 obtained semaphore:   %lu\n", thread_4_counter);
+        printf("           thread 5 events received:      %lu\n", thread_5_counter);
+        printf("           thread 6 mutex obtained:       %lu\n", thread_6_counter);
+        printf("           thread 7 mutex obtained:       %lu\n\n", thread_7_counter);
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/linux/gnu/inc/tx_port.h b/ports/linux/gnu/inc/tx_port.h
new file mode 100644
index 00000000..9422e100
--- /dev/null
+++ b/ports/linux/gnu/inc/tx_port.h
@@ -0,0 +1,575 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */ 
+/*                                                                        */ 
+/*    tx_port.h                                           Linux/GNU       */ 
+/*                                                           6.0.1        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This file contains data type definitions that make the ThreadX      */ 
+/*    real-time kernel function identically on a variety of different     */ 
+/*    processor architectures.  For example, the size or number of bits   */ 
+/*    in an "int" data type vary between microprocessor architectures and */ 
+/*    even C compilers for the same microprocessor.  ThreadX does not     */ 
+/*    directly use native C data types.  Instead, ThreadX creates its     */ 
+/*    own special types that can be mapped to actual data types by this   */ 
+/*    file to guarantee consistency in the interface and functionality.   */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+#define TX_MAX_PRIORITIES                       32
+/* #define TX_MISRA_ENABLE  */
+
+
+/* #define TX_INLINE_INITIALIZATION */
+
+/* #define TX_NOT_INTERRUPTABLE  */
+/* #define TX_TIMER_PROCESS_IN_ISR */
+/* #define TX_REACTIVATE_INLINE */
+/* #define TX_DISABLE_STACK_FILLING */
+/* #define TX_ENABLE_STACK_CHECKING */
+/* #define TX_DISABLE_PREEMPTION_THRESHOLD */
+/* #define TX_DISABLE_REDUNDANT_CLEARING */
+/* #define TX_DISABLE_NOTIFY_CALLBACKS */
+/* #define TX_INLINE_THREAD_RESUME_SUSPEND */
+/* #define TX_ENABLE_EVENT_TRACE */
+
+
+/* For MISRA, define enable performance info. Also, for MISRA TX_DISABLE_NOTIFY_CALLBACKS should not be defined.  */
+
+
+/* #define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO
+#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO
+#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO
+#define TX_MUTEX_ENABLE_PERFORMANCE_INFO
+#define TX_QUEUE_ENABLE_PERFORMANCE_INFO
+#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO
+#define TX_THREAD_ENABLE_PERFORMANCE_INFO
+#define TX_TIMER_ENABLE_PERFORMANCE_INFO */
+
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include 
+#include 
+#include 
+#ifndef __USE_POSIX199309
+#define __USE_POSIX199309
+#include 
+#include 
+#include 
+#undef __USE_POSIX199309
+#else /* __USE_POSIX199309 */
+#include 
+#include 
+#include 
+#endif /* __USE_POSIX199309 */
+
+
+/* Define ThreadX basic types for this port.  */
+
+typedef void                                    VOID;
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+#if __x86_64__
+typedef int                                     LONG;
+typedef unsigned int                            ULONG;
+#else /* __x86_64__ */
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+#endif /* __x86_64__ */
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+typedef uint64_t                                ULONG64;
+
+
+/* Override the alignment type to use 64-bit alignment and storage for pointers.  */
+
+#if __x86_64__
+#define ALIGN_TYPE_DEFINED
+typedef unsigned long long                      ALIGN_TYPE;
+
+/* Override the free block marker for byte pools to be a 64-bit constant.   */
+
+#define TX_BYTE_BLOCK_FREE                      ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEE)
+#endif
+
+/* Define automated coverage test extensions...  These are required for the
+   ThreadX regression test.  */
+
+typedef unsigned int    TEST_FLAG;
+extern TEST_FLAG        threadx_byte_allocate_loop_test;
+extern TEST_FLAG        threadx_byte_release_loop_test;
+extern TEST_FLAG        threadx_mutex_suspension_put_test;
+extern TEST_FLAG        threadx_mutex_suspension_priority_test;
+#ifndef TX_TIMER_PROCESS_IN_ISR
+extern TEST_FLAG        threadx_delete_timer_thread;
+#endif
+
+extern void             abort_and_resume_byte_allocating_thread(void);
+extern void             abort_all_threads_suspended_on_mutex(void);
+extern void             suspend_lowest_priority(void);
+#ifndef TX_TIMER_PROCESS_IN_ISR
+extern void             delete_timer_thread(void);
+#endif
+extern TEST_FLAG        test_stack_analyze_flag;
+extern TEST_FLAG        test_initialize_flag;
+extern TEST_FLAG        test_forced_mutex_timeout;
+
+
+#ifdef TX_REGRESSION_TEST
+
+/* Define extension macros for automated coverage tests.  */
+
+
+#define TX_BYTE_ALLOCATE_EXTENSION              if (threadx_byte_allocate_loop_test == ((TEST_FLAG) 1))         \
+                                                {                                                               \
+                                                    pool_ptr -> tx_byte_pool_owner =  TX_NULL;                  \
+                                                    threadx_byte_allocate_loop_test = ((TEST_FLAG) 0);          \
+                                                }
+
+#define TX_BYTE_RELEASE_EXTENSION               if (threadx_byte_release_loop_test == ((TEST_FLAG) 1))          \
+                                                {                                                               \
+                                                    threadx_byte_release_loop_test = ((TEST_FLAG) 0);           \
+                                                    abort_and_resume_byte_allocating_thread();                  \
+                                                }
+
+#define TX_MUTEX_PUT_EXTENSION_1                if (threadx_mutex_suspension_put_test == ((TEST_FLAG) 1))       \
+                                                {                                                               \
+                                                    threadx_mutex_suspension_put_test = ((TEST_FLAG) 0);        \
+                                                    abort_all_threads_suspended_on_mutex();                     \
+                                                }
+
+
+#define TX_MUTEX_PUT_EXTENSION_2                if (test_forced_mutex_timeout == ((TEST_FLAG) 1))               \
+                                                {                                                               \
+                                                    test_forced_mutex_timeout = ((TEST_FLAG) 0);                \
+                                                    _tx_thread_wait_abort(mutex_ptr -> tx_mutex_suspension_list); \
+                                                }
+
+
+#define TX_MUTEX_PRIORITY_CHANGE_EXTENSION      if (threadx_mutex_suspension_priority_test == ((TEST_FLAG) 1))  \
+                                                {                                                               \
+                                                    threadx_mutex_suspension_priority_test = ((TEST_FLAG) 0);   \
+                                                    suspend_lowest_priority();                                  \
+                                                }
+
+#ifndef TX_TIMER_PROCESS_IN_ISR
+
+#define TX_TIMER_INITIALIZE_EXTENSION(a)        if (threadx_delete_timer_thread == ((TEST_FLAG) 1))             \
+                                                {                                                               \
+                                                    threadx_delete_timer_thread = ((TEST_FLAG) 0);              \
+                                                    delete_timer_thread();                                      \
+                                                    (a) =  ((UINT) 1);                                          \
+                                                }
+
+#endif
+
+#define TX_THREAD_STACK_ANALYZE_EXTENSION       if (test_stack_analyze_flag == ((TEST_FLAG) 1))                 \
+                                                {                                                               \
+                                                    thread_ptr -> tx_thread_id =  ((TEST_FLAG) 0);              \
+                                                    test_stack_analyze_flag =     ((TEST_FLAG) 0);              \
+                                                }                                                               \
+                                                else if (test_stack_analyze_flag == ((TEST_FLAG) 2))            \
+                                                {                                                               \
+                                                    stack_ptr =  thread_ptr -> tx_thread_stack_start;           \
+                                                    test_stack_analyze_flag =     ((TEST_FLAG) 0);              \
+                                                }                                                               \
+                                                else if (test_stack_analyze_flag == ((TEST_FLAG) 3))            \
+                                                {                                                               \
+                                                    *stack_ptr =  TX_STACK_FILL;                                \
+                                                    test_stack_analyze_flag =     ((TEST_FLAG) 0);              \
+                                                }                                                               \
+                                                else                                                            \
+                                                {                                                               \
+                                                    test_stack_analyze_flag =     ((TEST_FLAG) 0);              \
+                                                }
+
+#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION    if (test_initialize_flag == ((TEST_FLAG) 1))                    \
+                                                {                                                               \
+                                                    test_initialize_flag =  ((TEST_FLAG) 0);                    \
+                                                    return;                                                     \
+                                                }
+
+#endif
+
+
+
+/* Add Linux debug insert prototype.  */
+
+void    _tx_linux_debug_entry_insert(char *action, char *file, unsigned long line);
+
+#ifndef TX_LINUX_DEBUG_ENABLE
+
+/* If Linux debug is not enabled, turn logging into white-space.  */
+
+#define _tx_linux_debug_entry_insert(a, b, c)
+
+#endif
+
+
+
+/* Define the TX_MEMSET macro to remove library reference.  */
+
+#ifndef TX_MISRA_ENABLE
+#define TX_MEMSET(a,b,c)                        {                                       \
+                                                UCHAR *ptr;                             \
+                                                UCHAR value;                            \
+                                                UINT  i, size;                          \
+                                                    ptr =    (UCHAR *) ((VOID *) a);    \
+                                                    value =  (UCHAR) b;                 \
+                                                    size =   (UINT) c;                  \
+                                                    for (i = 0; i < size; i++)          \
+                                                    {                                   \
+                                                        *ptr++ =  value;                \
+                                                    }                                   \
+                                                }
+#endif
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              400         /* Default timer thread stack size - Not used in Linux port!  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */
+#endif
+
+
+/* Define various constants for the ThreadX  port.  */
+
+#define TX_INT_DISABLE                          1           /* Disable interrupts               */
+#define TX_INT_ENABLE                           0           /* Enable interrupts                */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_MISRA_ENABLE
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ((ULONG) (_tx_linux_time_stamp.tv_nsec));
+#endif
+#else
+ULONG   _tx_misra_time_stamp_get(VOID);
+#define TX_TRACE_TIME_SOURCE                    _tx_misra_time_stamp_get()
+#endif
+
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port-specific trace extension to pickup the Windows timer.  */
+
+#define TX_TRACE_PORT_EXTENSION                 clock_gettime(CLOCK_REALTIME, &_tx_linux_time_stamp);
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          0
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#ifdef TX_MISRA_ENABLE
+#define TX_DISABLE_INLINE
+#else
+#define TX_INLINE_INITIALIZATION
+#endif
+
+
+/* Define the Linux-specific initialization code that is expanded in the generic source.  */
+
+void    _tx_initialize_start_interrupts(void);
+
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION                       _tx_initialize_start_interrupts();
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifndef TX_MISRA_ENABLE
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0                                               pthread_t   tx_thread_linux_thread_id; \
+                                                                            sem_t       tx_thread_linux_thread_run_semaphore; \
+                                                                            UINT        tx_thread_linux_suspension_type; \
+                                                                            UINT        tx_thread_linux_int_disabled_flag;
+
+#define TX_THREAD_EXTENSION_1                                               VOID       *tx_thread_extension_ptr;
+#define TX_THREAD_EXTENSION_2
+#define TX_THREAD_EXTENSION_3
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+struct TX_THREAD_STRUCT;
+
+/* Define post completion processing for tx_thread_delete, so that the Linux thread resources are properly removed.  */
+
+void _tx_thread_delete_port_completion(struct TX_THREAD_STRUCT *thread_ptr, UINT tx_saved_posture);
+#define TX_THREAD_DELETE_PORT_COMPLETION(thread_ptr) _tx_thread_delete_port_completion(thread_ptr, tx_saved_posture);
+
+/* Define post completion processing for tx_thread_reset, so that the Linux thread resources are properly removed.  */
+
+void _tx_thread_reset_port_completion(struct TX_THREAD_STRUCT *thread_ptr, UINT tx_saved_posture);
+#define TX_THREAD_RESET_PORT_COMPLETION(thread_ptr) _tx_thread_reset_port_completion(thread_ptr, tx_saved_posture);
+
+#if __x86_64__
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout
+   can figure out what thread timeout to process.  */
+
+#define TX_TIMER_INTERNAL_EXTENSION             VOID    *tx_timer_internal_extension_ptr;
+
+
+/* Define the thread timeout setup logic in _tx_thread_create.  */
+
+#define TX_THREAD_CREATE_TIMEOUT_SETUP(t)    (t) -> tx_thread_timer.tx_timer_internal_timeout_function =    &(_tx_thread_timeout);            \
+                                             (t) -> tx_thread_timer.tx_timer_internal_timeout_param =       0;                                \
+                                             (t) -> tx_thread_timer.tx_timer_internal_extension_ptr =       (VOID *) (t);
+
+
+/* Define the thread timeout pointer setup in _tx_thread_timeout.  */
+
+#define TX_THREAD_TIMEOUT_POINTER_SETUP(t)   (t) =  (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_extension_ptr;
+#endif /* __x86_64__ */
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on
+   access of critical kernel information.  The restore interrupt macro must
+   restore the interrupt posture of the running thread prior to the value
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+UINT   _tx_thread_interrupt_disable(void);
+VOID   _tx_thread_interrupt_restore(UINT previous_posture);
+
+#define TX_INTERRUPT_SAVE_AREA      UINT    tx_saved_posture;
+
+#ifndef TX_LINUX_DEBUG_ENABLE
+#define TX_DISABLE                          tx_saved_posture =   _tx_thread_interrupt_disable();
+#define TX_RESTORE                          _tx_thread_interrupt_restore(tx_saved_posture);
+#else
+#define TX_DISABLE                          _tx_linux_debug_entry_insert("DISABLE", __FILE__, __LINE__); \
+                                            tx_saved_posture =   _tx_thread_interrupt_disable();
+
+#define TX_RESTORE                          _tx_linux_debug_entry_insert("RESTORE", __FILE__, __LINE__); \
+                                            _tx_thread_interrupt_restore(tx_saved_posture);
+#endif /* TX_LINUX_DEBUG_ENABLE */
+#define tx_linux_mutex_lock(p)              pthread_mutex_lock(&p)
+#define tx_linux_mutex_unlock(p)            pthread_mutex_unlock(&p)
+#define tx_linux_mutex_recursive_unlock(p)  {\
+                                                int _recursive_count = tx_linux_mutex_recursive_count;\
+                                                while(_recursive_count)\
+                                                {\
+                                                    pthread_mutex_unlock(&p);\
+                                                    _recursive_count--;\
+                                                }\
+                                            }
+#define tx_linux_mutex_recursive_count      _tx_linux_mutex.__data.__count
+#define tx_linux_sem_post(p)                tx_linux_mutex_lock(_tx_linux_mutex);\
+                                            sem_post(p);\
+                                            tx_linux_mutex_unlock(_tx_linux_mutex)
+#define tx_linux_sem_post_nolock(p)         sem_post(p)
+#define tx_linux_sem_wait(p)                sem_wait(p)
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE               TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE        TX_DISABLE
+#define TX_MUTEX_DISABLE                    TX_DISABLE
+#define TX_QUEUE_DISABLE                    TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] =
+                                    "Copyright (c) Microsoft Corporation * ThreadX Linux/gcc Version 6.0 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+
+/* Define externals for the Linux port of ThreadX.  */
+
+extern pthread_mutex_t                          _tx_linux_mutex;
+extern sem_t                                    _tx_linux_semaphore;
+extern sem_t                                    _tx_linux_semaphore_no_idle;
+extern ULONG                                    _tx_linux_global_int_disabled_flag;
+extern struct timespec                          _tx_linux_time_stamp;
+extern __thread int                             _tx_linux_threadx_thread;
+
+/* Define functions for linux thread. */
+void    _tx_linux_thread_suspend(pthread_t thread_id);
+void    _tx_linux_thread_resume(pthread_t thread_id);
+void    _tx_linux_thread_init();
+
+#ifndef TX_LINUX_MEMORY_SIZE
+#define TX_LINUX_MEMORY_SIZE                    64000
+#endif
+
+#define TX_TIMER_TICKS_PER_SECOND               100UL
+
+/* Define priorities of pthreads. */
+
+#define TX_LINUX_PRIORITY_SCHEDULE              (3)
+#define TX_LINUX_PRIORITY_ISR                   (2)
+#define TX_LINUX_PRIORITY_USER_THREAD           (1)
+
+#endif
+
diff --git a/ports/linux/gnu/readme_threadx.txt b/ports/linux/gnu/readme_threadx.txt
new file mode 100644
index 00000000..5fdd6c3f
--- /dev/null
+++ b/ports/linux/gnu/readme_threadx.txt
@@ -0,0 +1,155 @@
+                         Microsoft's Azure RTOS ThreadX for Linux 
+
+                              Using the GNU GCC Tools
+
+1.  Building the ThreadX run-time Library
+
+First make sure you are in the "example_build" directory. Also, make sure that
+you have setup your path and other environment variables necessary for the GNU
+development environment. The following command retrieves and installs GCC
+multilib on a Ubuntu system:
+ 
+sudo apt-get install gcc-multilib
+
+At this point you may run the GNU make command to build the ThreadX core 
+library. This will build the ThreadX run-time environment in the 
+"example_build" directory. 
+
+   make tx.a
+
+you should now observe the compilation of the ThreadX library source. At the 
+end of the make, they are all combined into the run-time library file: tx.a.
+This file must be linked with your application in order to use ThreadX.
+ 
+
+2.  Demonstration System
+
+Building the demonstration is easy; simply execute the GNU make command while 
+inside the "example_build" directory. 
+
+   make sample_threadx
+
+You should observe the compilation of sample_threadx.c (which is the demonstration 
+application) and linking with tx.a. The resulting file DEMO is a binary file 
+that can be executed.
+
+
+3.  System Initialization
+
+The system entry point is at main(), which is defined in the application. 
+Once the application calls tx_kernel_enter, ThreadX starts running and 
+performs various initialization duties prior to starting the scheduler. The 
+Linux-specific initialization is done in the function _tx_initialize_low_level,
+which is located in the file tx_initialize_low_level.c. This function is 
+responsible for setting up various system data structures and simulated 
+interrupts - including the periodic timer interrupt source for ThreadX.
+
+In addition, _tx_initialize_low_level determines the first available 
+address for use by the application. In Linux, this is basically done
+by using malloc to get a big block of memory from Linux.
+
+
+4.  Linux Implementation
+
+ThreadX for Linux is implemented using POSIX pthreads. Each application
+thread in ThreadX actually runs as a Linux pthread. The determination of
+which application thread to run is made by the ThreadX scheduler, which 
+itself is a Linux pthread. The ThreadX scheduler is the highest priority 
+thread in the system.
+
+Interrupts in ThreadX/Linux are also simulated by pthreads. A good example
+is the ThreadX system timer interrupt, which can be found in 
+tx_initialize_low_level.c.
+
+ThreadX for linux utilizes the API pthread_setschedparam() which requires
+the ThreadX application running with privilege. The following command is used
+to run a ThreadX application:
+
+./sample_threadx
+
+5.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+breakpoints inside of ThreadX itself. Of course, this costs some 
+performance. To make it run faster, you can change the makefile to 
+enable all compiler optimizations. In addition, you can eliminate the 
+ThreadX basic API error checking by compiling your application code with the 
+symbol TX_DISABLE_ERROR_CHECKING defined.
+
+
+6.  Interrupt Handling
+
+ThreadX provides simulated interrupt handling with Linux pthreads. Simulated
+interrupt threads may be created by the application or may be added to the
+simulated timer interrupt defined in tx_initialize_low_level.c. The following 
+format for creating simulated interrupts should be used:
+
+6.1  Data structures
+
+Here is an example of how to define the Linux data structures and prototypes
+necessary to create a simulated interrupt thread:
+
+pthread_t    _sample_linux_interrupt_thread;
+void        *_sample_linux_interrupt_entry(void *p);
+
+6.2  Creating a Simulated Interrupt Thread
+
+Here is an example of how to create a simulated interrupt thread in Linux.
+This may be done inside of tx_initialize_low_level.c or from your application code
+
+
+struct sched_param sp;
+
+       /* Create the ISR thread */
+       pthread_create(&_sample_linux_interrupt_thread, NULL, _sample_linux_interrupt_entry, &_sample_linux_interrupt_thread);
+
+       /* Set up the ISR priority */
+       sp.sched_priority = TX_LINUX_PRIORITY_ISR;
+       pthread_setschedparam(_sample_linux_interrupt_thread, SCHED_FIFO, &sp);
+
+
+
+6.3  Simulated Interrupt Thread Template
+
+The following is a template for the simulated interrupt thread. This interrupt will occur on
+a periodic basis. 
+
+void    *_sample_linux_interrupt_entry(void *p)
+{
+struct timespec ts;
+
+    while(1)
+    {
+
+        ts.tv_sec = 0;
+        ts.tv_nsec = 10000;
+        while(nanosleep(&ts, &ts));
+
+        /* Call ThreadX context save for interrupt preparation.  */
+        _tx_thread_context_save();
+
+        /* Call the real ISR routine */
+        _sample_linux_interrupt_isr();
+
+        /* Call ThreadX context restore for interrupt completion.  */
+        _tx_thread_context_restore();
+    } 
+}
+
+
+
+7.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX 6.0.1 version for Linux using GNU GCC tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/linux/gnu/src/tx_initialize_low_level.c b/ports/linux/gnu/src/tx_initialize_low_level.c
new file mode 100644
index 00000000..f8cd604b
--- /dev/null
+++ b/ports/linux/gnu/src/tx_initialize_low_level.c
@@ -0,0 +1,443 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Initialize                                                          */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+/* Define various Linux objects used by the ThreadX port.  */
+
+pthread_mutex_t     _tx_linux_mutex;
+sem_t               _tx_linux_semaphore;
+sem_t               _tx_linux_semaphore_no_idle;
+ULONG               _tx_linux_global_int_disabled_flag;
+struct timespec     _tx_linux_time_stamp;
+__thread int        _tx_linux_threadx_thread = 0;
+ 
+/* Define signals for linux thread. */
+#define SUSPEND_SIG SIGUSR1
+#define RESUME_SIG  SIGUSR2
+
+static sigset_t     _tx_linux_thread_wait_mask;
+static __thread int _tx_linux_thread_suspended; 
+static sem_t        _tx_linux_thread_timer_wait;
+static sem_t        _tx_linux_thread_other_wait;
+
+/* Define simulated timer interrupt.  This is done inside a thread, which is
+   how other interrupts may be defined as well.  See code below for an 
+   example.  */
+
+pthread_t           _tx_linux_timer_id;
+sem_t               _tx_linux_timer_semaphore;
+sem_t               _tx_linux_isr_semaphore;
+void               *_tx_linux_timer_interrupt(void *p);
+
+
+#ifdef TX_LINUX_DEBUG_ENABLE
+
+extern ULONG        _tx_thread_system_state;
+extern UINT         _tx_thread_preempt_disable;
+extern TX_THREAD    *_tx_thread_current_ptr;
+extern TX_THREAD    *_tx_thread_execute_ptr;
+
+
+/* Define debug log in order to debug Linux issues with this port.  */
+
+typedef struct TX_LINUX_DEBUG_ENTRY_STRUCT
+{
+    char                *tx_linux_debug_entry_action;
+    struct timespec     tx_linux_debug_entry_timestamp;
+    char                *tx_linux_debug_entry_file;
+    unsigned long       tx_linux_debug_entry_line;
+    pthread_mutex_t     tx_linux_debug_entry_mutex;
+    unsigned long       tx_linux_debug_entry_int_disabled_flag;
+    ULONG               tx_linux_debug_entry_system_state;
+    UINT                tx_linux_debug_entry_preempt_disable;
+    TX_THREAD           *tx_linux_debug_entry_current_thread;
+    TX_THREAD           *tx_linux_debug_entry_execute_thread;
+} TX_LINUX_DEBUG_ENTRY;
+
+
+/* Define the maximum size of the Linux debug array.  */
+
+#ifndef TX_LINUX_DEBUG_EVENT_SIZE
+#define TX_LINUX_DEBUG_EVENT_SIZE       400
+#endif
+
+
+/* Define the circular array of Linux debug entries.  */
+
+TX_LINUX_DEBUG_ENTRY    _tx_linux_debug_entry_array[TX_LINUX_DEBUG_EVENT_SIZE];
+
+
+/* Define the Linux debug index.  */
+
+unsigned long           _tx_linux_debug_entry_index =  0;
+
+
+/* Now define the debug entry function.  */
+void    _tx_linux_debug_entry_insert(char *action, char *file, unsigned long line)
+{
+
+pthread_mutex_t        temp_copy;
+
+    /* Save the current critical section value.  */
+    temp_copy =  _tx_linux_mutex;
+
+    /* Lock mutex.  */
+    tx_linux_mutex_lock(_tx_linux_mutex);
+
+    /* Get the time stamp.  */
+    clock_gettime(CLOCK_REALTIME, &_tx_linux_time_stamp);
+
+    /* Setup the debub entry.  */
+    _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_action =             action;
+    _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_timestamp =          _tx_linux_time_stamp;
+    _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_file =               file;
+    _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_line =               line;
+    _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_mutex =              temp_copy;
+    _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_int_disabled_flag =  _tx_linux_global_int_disabled_flag;
+    _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_system_state =       _tx_thread_system_state;
+    _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_preempt_disable =    _tx_thread_preempt_disable;
+    _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_current_thread =     _tx_thread_current_ptr;
+    _tx_linux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_execute_thread =     _tx_thread_execute_ptr;
+
+    /* Now move to the next entry.  */
+    _tx_linux_debug_entry_index++;
+    
+    /* Determine if we need to wrap the list.  */
+    if (_tx_linux_debug_entry_index >= TX_LINUX_DEBUG_EVENT_SIZE)
+    {
+    
+        /* Yes, wrap the list!  */
+        _tx_linux_debug_entry_index =  0;
+    }
+
+    /* Unlock mutex.  */
+    tx_linux_mutex_unlock(_tx_linux_mutex);
+}
+
+#endif
+
+
+/* Define the ThreadX timer interrupt handler.  */
+
+void    _tx_timer_interrupt(void);
+
+
+/* Define other external function references.  */
+
+VOID    _tx_initialize_low_level(VOID);
+VOID    _tx_thread_context_save(VOID);
+VOID    _tx_thread_context_restore(VOID);
+
+
+/* Define other external variable references.  */
+
+extern VOID     *_tx_initialize_unused_memory;
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_initialize_low_level                            Linux/GNU       */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function is responsible for any low-level processor            */ 
+/*    initialization, including setting up interrupt vectors, setting     */ 
+/*    up a periodic timer interrupt source, saving the system stack       */ 
+/*    pointer for use in ISR processing later, and finding the first      */ 
+/*    available RAM memory address for tx_application_define.             */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    sched_setaffinity                                                   */ 
+/*    getpid                                                              */ 
+/*    _tx_linux_thread_init                                               */ 
+/*    pthread_setschedparam                                               */ 
+/*    pthread_mutexattr_init                                              */ 
+/*    pthread_mutex_init                                                  */ 
+/*    _tx_linux_thread_suspend                                            */ 
+/*    sem_init                                                            */ 
+/*    pthread_create                                                      */ 
+/*    printf                                                              */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    _tx_initialize_kernel_enter           ThreadX entry function        */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_initialize_low_level(VOID)
+{
+struct sched_param sp;
+pthread_mutexattr_t attr;
+
+#ifdef TX_LINUX_MULTI_CORE
+cpu_set_t mask;
+
+    sched_getaffinity(getpid(), sizeof(mask), &mask);
+    if (CPU_COUNT(&mask) > 1)
+    {
+
+        srand((ULONG)pthread_self());
+
+        /* Limit this ThreadX simulation on Linux to a single core.  */
+        CPU_ZERO(&mask);
+        CPU_SET(rand() % get_nprocs(), &mask);
+        if (sched_setaffinity(getpid(), sizeof(mask), &mask) != 0)
+        {
+        
+            /* Error restricting the process to one core.  */
+            printf("ThreadX Linux error restricting the process to one core!\n");
+            while(1)
+            {
+            }
+        }
+    }
+#endif
+
+    /* Pickup the first available memory address.  */
+
+    /* Save the first available memory address.  */
+    _tx_initialize_unused_memory =  malloc(TX_LINUX_MEMORY_SIZE);
+
+    /* Init Linux thread. */
+    _tx_linux_thread_init();
+
+    /* Set priority and schedual of main thread. */
+    sp.sched_priority = TX_LINUX_PRIORITY_SCHEDULE;
+    pthread_setschedparam(pthread_self(), SCHED_FIFO, &sp);
+
+    /* Create the system critical section.  This is used by the 
+       scheduler thread (which is the main thread) to block all
+       other stuff out.  */
+    pthread_mutexattr_init(&attr);
+    pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE);
+    pthread_mutex_init(&_tx_linux_mutex, &attr);
+    sem_init(&_tx_linux_semaphore, 0, 0);
+#ifdef TX_LINUX_NO_IDLE_ENABLE
+    sem_init(&_tx_linux_semaphore_no_idle, 0, 0);
+#endif /* TX_LINUX_NO_IDLE_ENABLE */
+
+    /* Initialize the global interrupt disabled flag.  */
+    _tx_linux_global_int_disabled_flag =  TX_FALSE;
+    
+    /* Create semaphore for timer thread. */
+    sem_init(&_tx_linux_timer_semaphore, 0, 0);
+    
+    /* Create semaphore for ISR thread. */
+    sem_init(&_tx_linux_isr_semaphore, 0, 0);
+
+    /* Setup periodic timer interrupt.  */
+    if(pthread_create(&_tx_linux_timer_id, NULL, _tx_linux_timer_interrupt, NULL))
+    {
+
+        /* Error creating the timer interrupt.  */
+        printf("ThreadX Linux error creating timer interrupt thread!\n");
+        while(1)
+        {
+        }
+    }
+
+    /* Otherwise, we have a good thread create.  Now set the priority to
+       a level lower than the system thread but higher than the application
+       threads.  */
+    sp.sched_priority = TX_LINUX_PRIORITY_ISR;
+    pthread_setschedparam(_tx_linux_timer_id, SCHED_FIFO, &sp);
+
+    /* Done, return to caller.  */
+}
+
+
+/* This routine is called after initialization is complete in order to start
+   all interrupt threads.  Interrupt threads in addition to the timer may 
+   be added to this routine as well.  */
+
+void    _tx_initialize_start_interrupts(void)
+{
+
+    /* Kick the timer thread off to generate the ThreadX periodic interrupt
+       source.  */
+    tx_linux_sem_post(&_tx_linux_timer_semaphore);
+}
+
+
+/* Define the ThreadX system timer interrupt.  Other interrupts may be simulated
+   in a similar way.  */
+
+void    *_tx_linux_timer_interrupt(void *p)
+{
+struct timespec ts;
+long timer_periodic_nsec;
+int err;
+
+    /* Calculate periodic timer. */
+    timer_periodic_nsec = 1000000000 / TX_TIMER_TICKS_PER_SECOND;
+    nice(10);
+
+    /* Wait startup semaphore. */
+    tx_linux_sem_wait(&_tx_linux_timer_semaphore);
+
+    while(1)
+    {
+
+        clock_gettime(CLOCK_REALTIME, &ts);
+        ts.tv_nsec += timer_periodic_nsec;
+        if (ts.tv_nsec > 1000000000)
+        {
+            ts.tv_nsec -= 1000000000;
+            ts.tv_sec++;
+        }
+        do
+        {
+            if (sem_timedwait(&_tx_linux_timer_semaphore, &ts) == 0)
+            {
+                break;
+            }
+            err = errno;
+        } while (err != ETIMEDOUT);
+
+        /* Call ThreadX context save for interrupt preparation.  */
+        _tx_thread_context_save();
+
+        /* Call trace ISR enter event insert.  */
+        _tx_trace_isr_enter_insert(0);
+
+        /* Call the ThreadX system timer interrupt processing.  */
+        _tx_timer_interrupt();
+
+        /* Call trace ISR exit event insert.  */
+        _tx_trace_isr_exit_insert(0);
+
+        /* Call ThreadX context restore for interrupt completion.  */
+        _tx_thread_context_restore();
+
+#ifdef TX_LINUX_NO_IDLE_ENABLE
+        tx_linux_mutex_lock(_tx_linux_mutex);
+
+        /* Make sure semaphore is 0. */
+        while(!sem_trywait(&_tx_linux_semaphore_no_idle));
+
+        /* Wakeup the system thread by setting the system semaphore.  */
+        tx_linux_sem_post(&_tx_linux_semaphore_no_idle);
+
+        tx_linux_mutex_unlock(_tx_linux_mutex);
+#endif /* TX_LINUX_NO_IDLE_ENABLE */
+    } 
+}
+
+/* Define functions for linux thread. */
+void    _tx_linux_thread_resume_handler(int sig)
+{
+}
+
+void    _tx_linux_thread_suspend_handler(int sig)
+{
+    if(pthread_equal(pthread_self(), _tx_linux_timer_id))
+        tx_linux_sem_post_nolock(&_tx_linux_thread_timer_wait);
+    else
+        tx_linux_sem_post_nolock(&_tx_linux_thread_other_wait);
+
+    if(_tx_linux_thread_suspended) 
+        return;
+
+    _tx_linux_thread_suspended = 1;
+    sigsuspend(&_tx_linux_thread_wait_mask); 
+    _tx_linux_thread_suspended = 0;
+}
+
+void    _tx_linux_thread_suspend(pthread_t thread_id)
+{
+
+    /* Send signal. */
+    tx_linux_mutex_lock(_tx_linux_mutex);
+    pthread_kill(thread_id, SUSPEND_SIG);
+    tx_linux_mutex_unlock(_tx_linux_mutex);
+
+    /* Wait until signal is received. */
+    if(pthread_equal(thread_id, _tx_linux_timer_id))
+        tx_linux_sem_wait(&_tx_linux_thread_timer_wait);
+    else
+        tx_linux_sem_wait(&_tx_linux_thread_other_wait);
+}
+
+void    _tx_linux_thread_resume(pthread_t thread_id)
+{
+
+    /* Send signal. */
+    tx_linux_mutex_lock(_tx_linux_mutex);
+    pthread_kill(thread_id, RESUME_SIG);
+    tx_linux_mutex_unlock(_tx_linux_mutex);
+}
+
+void    _tx_linux_thread_init()
+{
+struct sigaction sa;
+
+    /* Create semaphore for linux thread. */
+    sem_init(&_tx_linux_thread_timer_wait, 0, 0);
+    sem_init(&_tx_linux_thread_other_wait, 0, 0);
+
+    sigfillset(&_tx_linux_thread_wait_mask);
+    sigdelset(&_tx_linux_thread_wait_mask, RESUME_SIG);
+
+    sigfillset(&sa.sa_mask);
+    sa.sa_flags = 0;
+    sa.sa_handler = _tx_linux_thread_resume_handler;
+    sigaction(RESUME_SIG, &sa, NULL);
+
+    sa.sa_handler = _tx_linux_thread_suspend_handler;
+    sigaction(SUSPEND_SIG, &sa, NULL);
+}
+
+
diff --git a/ports/linux/gnu/src/tx_thread_context_restore.c b/ports/linux/gnu/src/tx_thread_context_restore.c
new file mode 100644
index 00000000..ab24759e
--- /dev/null
+++ b/ports/linux/gnu/src/tx_thread_context_restore.c
@@ -0,0 +1,163 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include "tx_timer.h"
+
+extern sem_t _tx_linux_isr_semaphore;
+UINT _tx_linux_timer_waiting = 0;
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_thread_context_restore                          Linux/GNU       */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function restores the interrupt context if it is processing a  */ 
+/*    nested interrupt.  If not, it returns to the interrupt thread if no */ 
+/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+/*    if no thread was running, the function returns to the scheduler.    */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    _tx_linux_debug_entry_insert                                        */ 
+/*    tx_linux_mutex_lock                                                 */ 
+/*    sem_trywait                                                         */
+/*    tx_linux_sem_post                                                   */ 
+/*    tx_linux_sem_wait                                                   */ 
+/*    _tx_linux_thread_resume                                             */ 
+/*    tx_linux_mutex_recursive_unlock                                     */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    ISRs                                  Interrupt Service Routines    */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_thread_context_restore(VOID)
+{
+
+    /* Debug entry.  */
+    _tx_linux_debug_entry_insert("CONTEXT_RESTORE", __FILE__, __LINE__);
+
+    /* Lock mutex to ensure other threads are not playing with
+       the core ThreadX data structures.  */
+    tx_linux_mutex_lock(_tx_linux_mutex);
+
+    /* Decrement the nested interrupt count.  */
+    _tx_thread_system_state--;
+
+    /* Determine if this is the first nested interrupt and if a ThreadX
+       application thread was running at the time.  */
+    if ((!_tx_thread_system_state) && (_tx_thread_current_ptr))
+    {
+
+        /* Yes, this is the first and last interrupt processed.  */
+
+        /* Check to see if preemption is required.  */
+        if ((_tx_thread_preempt_disable == 0) && (_tx_thread_current_ptr != _tx_thread_execute_ptr))
+        {
+
+            /* Preempt the running application thread.  We don't need to suspend the 
+               application thread since that is done in the context save processing.  */
+
+            /* Indicate that this thread was suspended asynchronously.  */
+            _tx_thread_current_ptr -> tx_thread_linux_suspension_type =  1;
+
+            /* Save the remaining time-slice and disable it.  */
+            if (_tx_timer_time_slice)
+            {
+
+                _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+                _tx_timer_time_slice =  0;
+            }
+
+            /* Clear the current thread pointer.  */
+            _tx_thread_current_ptr =  TX_NULL;
+
+            /* Make sure semaphore is 0. */
+            while(!sem_trywait(&_tx_linux_semaphore));
+
+            /* Indicate it is in timer ISR. */
+            _tx_linux_timer_waiting = 1;
+
+            /* Wakeup the system thread by setting the system semaphore.  */
+            tx_linux_sem_post(&_tx_linux_semaphore);
+
+            if(_tx_thread_execute_ptr)
+            {
+                if(_tx_thread_execute_ptr -> tx_thread_linux_suspension_type == 0)
+                {
+
+                    /* Unlock linux mutex. */
+                    tx_linux_mutex_recursive_unlock(_tx_linux_mutex);
+
+                    /* Wait until TX_THREAD start running. */
+                    tx_linux_sem_wait(&_tx_linux_isr_semaphore);
+
+                    tx_linux_mutex_lock(_tx_linux_mutex);
+
+                    /* Make sure semaphore is 0. */
+                    while(!sem_trywait(&_tx_linux_isr_semaphore));
+                }
+            }
+
+            /* Indicate it is not in timer ISR. */
+            _tx_linux_timer_waiting = 0;
+        }
+        else
+        {
+
+            /* Since preemption is not required, resume the interrupted thread.  */
+            _tx_linux_thread_resume(_tx_thread_current_ptr -> tx_thread_linux_thread_id);
+        }
+    }
+
+    /* Unlock linux mutex. */
+    tx_linux_mutex_recursive_unlock(_tx_linux_mutex);
+}
+
diff --git a/ports/linux/gnu/src/tx_thread_context_save.c b/ports/linux/gnu/src/tx_thread_context_save.c
new file mode 100644
index 00000000..d2b54b23
--- /dev/null
+++ b/ports/linux/gnu/src/tx_thread_context_save.c
@@ -0,0 +1,107 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include "tx_timer.h"
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_thread_context_save                             Linux/GNU       */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function saves the context of an executing thread in the       */ 
+/*    beginning of interrupt processing.  The function also ensures that  */ 
+/*    the system stack is used upon return to the calling ISR.            */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    _tx_linux_debug_entry_insert                                        */ 
+/*    tx_linux_mutex_lock                                                 */ 
+/*    _tx_linux_thread_suspend                                            */ 
+/*    tx_linux_mutex_unlock                                               */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    ISRs                                                                */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_thread_context_save(VOID)
+{
+
+    /* Debug entry.  */
+    _tx_linux_debug_entry_insert("CONTEXT_SAVE", __FILE__, __LINE__);
+
+    /* Lock mutex to ensure other threads are not playing with
+       the core ThreadX data structures.  */
+    tx_linux_mutex_lock(_tx_linux_mutex);
+
+    /* If an application thread is running, suspend it to simulate preemption. */
+    if ((_tx_thread_current_ptr) && (_tx_thread_system_state == 0))
+    {
+
+        /* Debug entry.  */
+        _tx_linux_debug_entry_insert("CONTEXT_SAVE-suspend_thread", __FILE__, __LINE__);
+
+        /* Yes, this is the first interrupt and an application thread is running...
+           suspend it!  */
+        _tx_linux_thread_suspend(_tx_thread_current_ptr -> tx_thread_linux_thread_id);
+
+        /* Indicate that this thread was suspended asynchronously.  */
+        _tx_thread_current_ptr -> tx_thread_linux_suspension_type =  1;
+    }
+
+    /* Increment the nested interrupt condition.  */
+    _tx_thread_system_state++;
+
+    /* Unlock linux mutex. */
+    tx_linux_mutex_unlock(_tx_linux_mutex);
+}
+
diff --git a/ports/linux/gnu/src/tx_thread_interrupt_control.c b/ports/linux/gnu/src/tx_thread_interrupt_control.c
new file mode 100644
index 00000000..ea75e19f
--- /dev/null
+++ b/ports/linux/gnu/src/tx_thread_interrupt_control.c
@@ -0,0 +1,183 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+
+/* Define small routines used for the TX_DISABLE/TX_RESTORE macros.  */
+
+UINT   _tx_thread_interrupt_disable(void)
+{
+
+UINT    previous_value;
+
+
+    previous_value =  _tx_thread_interrupt_control(TX_INT_DISABLE);
+    return(previous_value);
+}
+
+
+VOID   _tx_thread_interrupt_restore(UINT previous_posture)
+{
+
+    previous_posture =  _tx_thread_interrupt_control(previous_posture);
+}
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_thread_interrupt_control                        Linux/GNU       */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function is responsible for changing the interrupt lockout     */ 
+/*    posture of the system.                                              */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    new_posture                           New interrupt lockout posture */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    old_posture                           Old interrupt lockout posture */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    tx_linux_mutex_lock                                                 */ 
+/*    pthread_self                                                        */ 
+/*    pthread_getschedparam                                               */ 
+/*    tx_linux_mutex_recursive_unlock                                     */ 
+/*    pthread_exit                                                        */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    Application Code                                                    */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+UINT   _tx_thread_interrupt_control(UINT new_posture)
+{
+
+UINT        old_posture;
+TX_THREAD   *thread_ptr; 
+pthread_t   thread_id;
+int         exit_code = 0;
+
+
+    /* Lock Linux mutex. */
+    tx_linux_mutex_lock(_tx_linux_mutex);
+
+    /* Pickup the id of the current thread.  */
+    thread_id = pthread_self();
+
+    /* Pickup the current thread pointer.  */
+    thread_ptr =      _tx_thread_current_ptr;
+
+    /* Determine if this is a thread and it does not 
+       match the current thread pointer.  */
+    if ((_tx_linux_threadx_thread) && 
+        ((!thread_ptr) || (!pthread_equal(thread_ptr -> tx_thread_linux_thread_id, thread_id)))) 
+    { 
+
+        /* This indicates the Linux thread was actually terminated by ThreadX is only 
+           being allowed to run in order to cleanup its resources.  */
+        /* Unlock linux mutex. */
+        tx_linux_mutex_recursive_unlock(_tx_linux_mutex);
+        pthread_exit((void *)&exit_code);
+    } 
+
+    /* Determine the current interrupt lockout condition.  */
+    if (tx_linux_mutex_recursive_count == 1)
+    {
+
+        /* Interrupts are enabled.  */
+        old_posture =  TX_INT_ENABLE;
+    }
+    else
+    {
+
+        /* Interrupts are disabled.  */
+        old_posture =  TX_INT_DISABLE;
+    }
+
+    /* First, determine if this call is from a non-thread.  */
+    if (_tx_thread_system_state)
+    {
+
+        /* Determine how to apply the new posture.  */
+        if (new_posture == TX_INT_ENABLE)
+        {
+
+            /* Clear the disabled flag.  */
+            _tx_linux_global_int_disabled_flag =  TX_FALSE;
+
+            /* Determine if the critical section is locked.  */
+            tx_linux_mutex_recursive_unlock(_tx_linux_mutex);
+        }
+        else if (new_posture == TX_INT_DISABLE)
+        {
+
+            /* Set the disabled flag.  */
+            _tx_linux_global_int_disabled_flag =  TX_TRUE;
+        }
+    }
+    else if (thread_ptr) 
+    {
+
+        /* Determine how to apply the new posture.  */
+        if (new_posture == TX_INT_ENABLE)
+        {
+
+            /* Clear the disabled flag.  */
+            _tx_thread_current_ptr -> tx_thread_linux_int_disabled_flag =  TX_FALSE;
+
+            /* Determine if the critical section is locked.  */
+            tx_linux_mutex_recursive_unlock(_tx_linux_mutex);
+        }
+        else if (new_posture == TX_INT_DISABLE)
+        {
+
+            /* Set the disabled flag.  */
+            _tx_thread_current_ptr -> tx_thread_linux_int_disabled_flag =  TX_TRUE;
+        }
+    }
+
+    /* Return the previous interrupt disable posture.  */
+    return(old_posture);
+}
+
diff --git a/ports/linux/gnu/src/tx_thread_schedule.c b/ports/linux/gnu/src/tx_thread_schedule.c
new file mode 100644
index 00000000..7843a3ec
--- /dev/null
+++ b/ports/linux/gnu/src/tx_thread_schedule.c
@@ -0,0 +1,264 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include "tx_timer.h"
+#include 
+#include 
+
+extern sem_t _tx_linux_timer_semaphore;
+extern sem_t _tx_linux_isr_semaphore;
+extern UINT _tx_linux_timer_waiting;
+extern pthread_t _tx_linux_timer_id;
+/**************************************************************************/
+/*                                                                        */
+/*  FUNCTION                                               RELEASE        */
+/*                                                                        */
+/*    _tx_thread_schedule                                 Linux/GNU       */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */
+/*    This function waits for a thread control block pointer to appear in */
+/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */
+/*    in the variable, the corresponding thread is resumed.               */
+/*                                                                        */
+/*  INPUT                                                                 */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  OUTPUT                                                                */
+/*                                                                        */
+/*    None                                                                */
+/*                                                                        */
+/*  CALLS                                                                 */
+/*                                                                        */
+/*    tx_linux_mutex_lock                                                 */
+/*    tx_linux_mutex_unlock                                               */
+/*    _tx_linux_debug_entry_insert                                        */
+/*    _tx_linux_thread_resume                                             */
+/*    tx_linux_sem_post                                                   */
+/*    sem_trywait                                                         */
+/*    tx_linux_sem_wait                                                   */
+/*                                                                        */
+/*  CALLED BY                                                             */
+/*                                                                        */
+/*    _tx_initialize_kernel_enter          ThreadX entry function         */
+/*                                                                        */
+/*  RELEASE HISTORY                                                       */
+/*                                                                        */
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_thread_schedule(VOID)
+{
+struct timespec ts;
+
+    /* Set timer. */
+    ts.tv_sec = 0;
+    ts.tv_nsec = 200000;
+
+    /* Loop forever.  */
+    while(1)
+    {
+
+        /* Wait for a thread to execute and all ISRs to complete.  */
+        while(1)
+        {
+
+            /* Lock Linux mutex.  */
+            tx_linux_mutex_lock(_tx_linux_mutex);
+
+            /* Determine if there is a thread ready to execute AND all ISRs
+               are complete.  */
+            if ((_tx_thread_execute_ptr != TX_NULL) && (_tx_thread_system_state == 0))
+            {
+
+                /* Get out of this loop and schedule the thread!  */
+                break;
+            }
+            else
+            {
+
+                /* Unlock linux mutex. */
+                tx_linux_mutex_unlock(_tx_linux_mutex);
+
+                /* Don't waste all the processor time here in the master thread...  */
+#ifdef TX_LINUX_NO_IDLE_ENABLE
+                while(!sem_trywait(&_tx_linux_timer_semaphore));
+                tx_linux_sem_post(&_tx_linux_timer_semaphore);
+                /*nanosleep(&ts, &ts);*/
+
+                clock_gettime(CLOCK_REALTIME, &ts);
+                ts.tv_nsec += 200000;
+                if (ts.tv_nsec > 1000000000)
+                {
+                    ts.tv_nsec -= 1000000000;
+                    ts.tv_sec++;
+                }
+                sem_timedwait(&_tx_linux_semaphore_no_idle, &ts);
+#else                
+                nanosleep(&ts, &ts);
+#endif /* TX_LINUX_NO_IDLE_ENABLE */                
+            }
+        }
+
+        /* Yes! We have a thread to execute. Note that the critical section is already
+           active from the scheduling loop above.  */
+
+        /* Setup the current thread pointer.  */
+        _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+
+        /* Increment the run count for this thread.  */
+        _tx_thread_current_ptr -> tx_thread_run_count++;
+
+        /* Setup time-slice, if present.  */
+        _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+
+        /* Determine how the thread was suspended.  */
+        if (_tx_thread_current_ptr -> tx_thread_linux_suspension_type)
+        {
+
+            /* Debug entry.  */
+            _tx_linux_debug_entry_insert("SCHEDULE-resume_thread", __FILE__, __LINE__);
+
+            /* Pseudo interrupt suspension.  The thread is not waiting on
+               its run semaphore.  */
+            _tx_linux_thread_resume(_tx_thread_current_ptr -> tx_thread_linux_thread_id);
+        }
+        else
+        {
+
+            /* Debug entry.  */
+            _tx_linux_debug_entry_insert("SCHEDULE-release_sem", __FILE__, __LINE__);
+
+            /* Make sure semaphore is 0. */
+            while(!sem_trywait(&_tx_thread_current_ptr -> tx_thread_linux_thread_run_semaphore));
+
+            /* Let the thread run again by releasing its run semaphore.  */
+            tx_linux_sem_post(&_tx_thread_current_ptr -> tx_thread_linux_thread_run_semaphore);
+
+            /* Block timer ISR. */
+            if(_tx_linux_timer_waiting)
+            {
+
+                /* It is woken up by timer ISR. */
+                /* Let ThreadX thread wake up first. */
+                tx_linux_sem_wait(&_tx_linux_semaphore);
+
+                /* Wake up timer ISR. */
+                tx_linux_sem_post_nolock(&_tx_linux_isr_semaphore);
+            }
+            else
+            {
+
+                /* It is woken up by TX_THREAD. */
+                /* Suspend timer thread and let ThreadX thread wake up first. */
+                _tx_linux_thread_suspend(_tx_linux_timer_id);
+                tx_linux_sem_wait(&_tx_linux_semaphore);
+                _tx_linux_thread_resume(_tx_linux_timer_id);
+
+            }
+        }
+
+        /* Unlock linux mutex. */
+        tx_linux_mutex_unlock(_tx_linux_mutex);
+
+        /* Debug entry.  */
+        _tx_linux_debug_entry_insert("SCHEDULE-self_suspend_sem", __FILE__, __LINE__);
+
+        /* Now suspend the main thread so the application thread can run.  */
+        tx_linux_sem_wait(&_tx_linux_semaphore);
+
+        /* Debug entry.  */
+        _tx_linux_debug_entry_insert("SCHEDULE-wake_up", __FILE__, __LINE__);
+
+    }
+}
+
+void _tx_thread_delete_port_completion(TX_THREAD *thread_ptr, UINT tx_saved_posture)
+{
+INT             linux_status;
+sem_t           *threadrunsemaphore;
+pthread_t       thread_id;
+struct          timespec ts;
+
+    thread_id = thread_ptr -> tx_thread_linux_thread_id;
+    threadrunsemaphore = &(thread_ptr -> tx_thread_linux_thread_run_semaphore);
+    ts.tv_sec = 0;
+    ts.tv_nsec = 1000000;
+    TX_RESTORE
+    do
+    {
+        linux_status = pthread_cancel(thread_id);
+        if(linux_status != EAGAIN)
+        {
+            break;
+        }
+        _tx_linux_thread_resume(thread_id);
+        tx_linux_sem_post(threadrunsemaphore);
+        nanosleep(&ts, &ts);
+    } while (1);
+    pthread_join(thread_id, NULL);
+    sem_destroy(threadrunsemaphore);
+    TX_DISABLE
+}
+
+void _tx_thread_reset_port_completion(TX_THREAD *thread_ptr, UINT tx_saved_posture)
+{
+INT             linux_status;
+sem_t           *threadrunsemaphore;
+pthread_t       thread_id;
+struct          timespec ts;
+
+    thread_id = thread_ptr -> tx_thread_linux_thread_id;
+    threadrunsemaphore = &(thread_ptr -> tx_thread_linux_thread_run_semaphore);
+    ts.tv_sec = 0;
+    ts.tv_nsec = 1000000;
+    TX_RESTORE
+    do
+    {
+        linux_status = pthread_cancel(thread_id);
+        if(linux_status != EAGAIN)
+        {
+            break;
+        }
+        _tx_linux_thread_resume(thread_id);
+        tx_linux_sem_post(threadrunsemaphore);
+        nanosleep(&ts, &ts);
+    } while (1);
+    pthread_join(thread_id, NULL);
+    sem_destroy(threadrunsemaphore);
+    TX_DISABLE
+}
diff --git a/ports/linux/gnu/src/tx_thread_stack_build.c b/ports/linux/gnu/src/tx_thread_stack_build.c
new file mode 100644
index 00000000..b18ae2fb
--- /dev/null
+++ b/ports/linux/gnu/src/tx_thread_stack_build.c
@@ -0,0 +1,153 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include 
+#include 
+
+
+/* Prototype for new thread entry function.  */
+
+void *_tx_linux_thread_entry(void *ptr);
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_thread_stack_build                              Linux/GNU       */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function builds a stack frame on the supplied thread's stack.  */
+/*    The stack frame results in a fake interrupt return to the supplied  */
+/*    function pointer.                                                   */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    thread_ptr                            Pointer to thread control blk */
+/*    function_ptr                          Pointer to return function    */
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    pthread_create                                                      */ 
+/*    pthread_setschedparam                                               */ 
+/*    _tx_linux_thread_suspend                                            */ 
+/*    sem_init                                                            */ 
+/*    printf                                                              */ 
+/*    _tx_linux_thread_resume                                             */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    _tx_thread_create                     Create thread service         */
+/*    _tx_thread_reset                      Reset thread service          */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+{
+struct sched_param sp;
+
+    /* Create the run semaphore for the thread.  This will allow the scheduler
+       control over when the thread actually runs.  */
+    if(sem_init(&thread_ptr -> tx_thread_linux_thread_run_semaphore, 0, 0))
+    {
+
+        /* Display an error message.  */
+        printf("ThreadX Linux error creating thread running semaphore!\n");
+        while(1)
+        {
+        }
+    }
+
+    /* Create a Linux thread for the application thread.  */
+    if(pthread_create(&thread_ptr -> tx_thread_linux_thread_id, NULL, _tx_linux_thread_entry, thread_ptr))
+    {
+
+        /* Display an error message.  */
+        printf("ThreadX Linux error creating thread!\n");
+        while(1)
+        {
+        }
+    }
+
+    /* Otherwise, we have a good thread create.  */
+    sp.sched_priority = TX_LINUX_PRIORITY_USER_THREAD;
+    pthread_setschedparam(thread_ptr -> tx_thread_linux_thread_id, SCHED_FIFO, &sp);
+
+    /* Setup the thread suspension type to solicited thread suspension.  
+       Pseudo interrupt handlers will suspend with this field set to 1.  */
+    thread_ptr -> tx_thread_linux_suspension_type =  0;
+
+    /* Clear the disabled count that will keep track of the 
+       tx_interrupt_control nesting.  */
+    thread_ptr -> tx_thread_linux_int_disabled_flag =  0;
+
+    /* Setup a fake thread stack pointer.   */
+    thread_ptr -> tx_thread_stack_ptr =  (VOID *) (((CHAR *) thread_ptr -> tx_thread_stack_end) - 8);
+
+    /* Clear the first word of the stack.  */
+    *(((ULONG *) thread_ptr -> tx_thread_stack_ptr) - 1) =  0;
+}
+
+
+void *_tx_linux_thread_entry(void *ptr)
+{
+
+TX_THREAD  *thread_ptr;
+
+    /* Pickup the current thread pointer.  */
+    thread_ptr =  (TX_THREAD *) ptr;
+    _tx_linux_threadx_thread = 1;
+    nice(20);
+
+    /* Now suspend the thread initially.  If the thread has already
+       been scheduled, this will return immediately.  */
+    tx_linux_sem_wait(&thread_ptr -> tx_thread_linux_thread_run_semaphore);
+    tx_linux_sem_post_nolock(&_tx_linux_semaphore);
+
+    /* Call ThreadX thread entry point.  */
+    _tx_thread_shell_entry();
+
+    return EXIT_SUCCESS;
+}
+
diff --git a/ports/linux/gnu/src/tx_thread_system_return.c b/ports/linux/gnu/src/tx_thread_system_return.c
new file mode 100644
index 00000000..9ee68d0d
--- /dev/null
+++ b/ports/linux/gnu/src/tx_thread_system_return.c
@@ -0,0 +1,207 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define    TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include "tx_timer.h"
+#include 
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_thread_system_return                            Linux/GNU       */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function is target processor specific.  It is used to transfer */ 
+/*    control from a thread back to the system.  Only a minimal context   */ 
+/*    is saved since the compiler assumes temp registers are going to get */ 
+/*    slicked by a function call anyway.                                  */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    _tx_linux_debug_entry_insert                                        */ 
+/*    tx_linux_mutex_lock                                                 */ 
+/*    pthread_self                                                        */ 
+/*    pthread_getschedparam                                               */ 
+/*    pthread_equal                                                       */ 
+/*    tx_linux_mutex_recursive_unlock                                     */ 
+/*    tx_linux_mutex_unlock                                               */ 
+/*    pthread_exit                                                        */ 
+/*    tx_linux_sem_post                                                   */ 
+/*    sem_trywait                                                         */
+/*    tx_linux_sem_wait                                                   */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    ThreadX components                                                  */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_thread_system_return(VOID)
+{
+
+TX_THREAD   *temp_thread_ptr;
+sem_t       *temp_run_semaphore;
+UINT        temp_thread_state;
+pthread_t   thread_id;
+int         exit_code = 0;
+
+
+    /* Debug entry.  */
+    _tx_linux_debug_entry_insert("SYSTEM_RETURN", __FILE__, __LINE__);
+
+    /* Lock Linux mutex.  */
+    tx_linux_mutex_lock(_tx_linux_mutex);
+
+    /* First, determine if the thread was terminated.  */
+
+    /* Pickup the id of the current thread.  */
+    thread_id = pthread_self();
+
+    /* Pickup the current thread pointer.  */
+    temp_thread_ptr =  _tx_thread_current_ptr;
+
+    /* Determine if this is a thread (0) and it does not 
+       match the current thread pointer.  */
+    if ((_tx_linux_threadx_thread) && 
+        ((!temp_thread_ptr) || (!pthread_equal(temp_thread_ptr -> tx_thread_linux_thread_id, thread_id)))) 
+    { 
+
+        /* This indicates the Linux thread was actually terminated by ThreadX is only 
+           being allowed to run in order to cleanup its resources.  */
+        /* Unlock linux mutex. */
+        tx_linux_mutex_recursive_unlock(_tx_linux_mutex);
+        pthread_exit((void *)&exit_code);
+    }
+
+    /* Determine if the time-slice is active.  */
+    if (_tx_timer_time_slice)
+    {
+
+        /* Preserve current remaining time-slice for the thread and clear the current time-slice.  */
+        temp_thread_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+        _tx_timer_time_slice =  0;
+    }
+
+    /* Save the run semaphore into a temporary variable as well.  */
+    temp_run_semaphore =  &temp_thread_ptr -> tx_thread_linux_thread_run_semaphore;
+
+    /* Pickup the current thread state.  */
+    temp_thread_state =  temp_thread_ptr -> tx_thread_state;
+
+    /* Setup the suspension type for this thread.  */
+    temp_thread_ptr -> tx_thread_linux_suspension_type  =  0;
+
+    /* Set the current thread pointer to NULL.  */
+    _tx_thread_current_ptr =  TX_NULL;
+
+    /* Unlock Linux mutex.  */
+    tx_linux_mutex_recursive_unlock(_tx_linux_mutex);
+
+    /* Debug entry.  */
+    _tx_linux_debug_entry_insert("SYSTEM_RETURN-release_sem", __FILE__, __LINE__);
+
+    /* Make sure semaphore is 0. */
+    while(!sem_trywait(&_tx_linux_semaphore));
+
+    /* Release the semaphore that the main scheduling thread is waiting
+       on.  Note that the main scheduling algorithm will take care of
+       setting the current thread pointer to NULL.  */
+    tx_linux_sem_post(&_tx_linux_semaphore);
+
+    /* Determine if the thread was self-terminating.  */
+    if (temp_thread_state ==  TX_TERMINATED)
+    {
+
+        /* Exit the thread instead of waiting on the semaphore!  */
+        pthread_exit((void *)&exit_code);
+    }
+
+    /* Wait on the run semaphore for this thread.  This won't get set again
+       until the thread is scheduled.  */
+    tx_linux_sem_wait(temp_run_semaphore);
+    tx_linux_sem_post_nolock(&_tx_linux_semaphore);
+
+    /* Lock Linux mutex.  */
+    tx_linux_mutex_lock(_tx_linux_mutex);
+
+    /* Debug entry.  */
+    _tx_linux_debug_entry_insert("SYSTEM_RETURN-wake_up", __FILE__, __LINE__);
+
+    /* Determine if the thread was terminated.  */
+
+    /* Pickup the current thread pointer.  */
+    temp_thread_ptr =  _tx_thread_current_ptr;
+
+    /* Determine if this is a thread and it does not 
+       match the current thread pointer.  */
+    if ((_tx_linux_threadx_thread) && 
+        ((!temp_thread_ptr) || (!pthread_equal(temp_thread_ptr -> tx_thread_linux_thread_id, thread_id)))) 
+    { 
+
+        /* Unlock Linux mutex.  */
+        tx_linux_mutex_recursive_unlock(_tx_linux_mutex);
+
+        /* This indicates the Linux thread was actually terminated by ThreadX and is only 
+           being allowed to run in order to cleanup its resources.  */
+        pthread_exit((void *)&exit_code);
+    } 
+
+    /* Now determine if the application thread last had interrupts disabled.  */
+
+    /* Determine if this thread had interrupts disabled.  */
+    if (!_tx_thread_current_ptr -> tx_thread_linux_int_disabled_flag)
+    {
+
+        /* Unlock Linux mutex.  */
+        tx_linux_mutex_recursive_unlock(_tx_linux_mutex);
+    }
+
+    /* Debug entry.  */
+    _tx_linux_debug_entry_insert("SYSTEM_RETURN-finish", __FILE__, __LINE__);
+}
+
diff --git a/ports/linux/gnu/src/tx_timer_interrupt.c b/ports/linux/gnu/src/tx_timer_interrupt.c
new file mode 100644
index 00000000..55207c14
--- /dev/null
+++ b/ports/linux/gnu/src/tx_timer_interrupt.c
@@ -0,0 +1,153 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Timer                                                               */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_timer.h"
+#include "tx_thread.h"
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_timer_interrupt                                 Linux/GNU       */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function processes the hardware timer interrupt.  This         */ 
+/*    processing includes incrementing the system clock and checking for  */ 
+/*    time slice and/or timer expiration.  If either is found, the        */ 
+/*    interrupt context save/restore functions are called along with the  */ 
+/*    expiration functions.                                               */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    _tx_linux_debug_entry_insert                                        */ 
+/*    tx_linux_mutex_lock                                                 */ 
+/*    tx_linux_mutex_unlock                                               */ 
+/*    _tx_timer_expiration_process                                        */ 
+/*    _tx_thread_time_slice                                               */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    interrupt vector                                                    */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_timer_interrupt(VOID)
+{
+
+    /* Debug entry.  */
+    _tx_linux_debug_entry_insert("TIMER INTERRUPT", __FILE__, __LINE__);
+
+    /* Lock mutex to ensure other threads are not playing with
+       the core ThreadX data structures.  */
+    tx_linux_mutex_lock(_tx_linux_mutex);
+
+    /* Increment the system clock.  */
+    _tx_timer_system_clock++;
+
+    /* Test for time-slice expiration.  */
+    if (_tx_timer_time_slice)
+    {
+
+        /* Decrement the time_slice.  */
+        _tx_timer_time_slice--;
+
+        /* Check for expiration.  */
+        if (_tx_timer_time_slice == 0)
+        {
+
+           /* Set the time-slice expired flag.  */
+           _tx_timer_expired_time_slice =  TX_TRUE;
+        }
+    }
+
+    /* Test for timer expiration.  */
+    if (*_tx_timer_current_ptr)
+    {
+
+        /* Set expiration flag.  */
+        _tx_timer_expired =  TX_TRUE;
+    }
+    else
+    {
+
+        /* No timer expired, increment the timer pointer.  */
+        _tx_timer_current_ptr++;
+
+        /* Check for wrap-around.  */
+        if (_tx_timer_current_ptr == _tx_timer_list_end)
+        {
+
+            /* Wrap to beginning of list.  */
+            _tx_timer_current_ptr =  _tx_timer_list_start;
+        }
+    }
+
+    /* See if anything has expired.  */
+    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+    {
+
+        /* Did a timer expire?  */
+        if (_tx_timer_expired)
+        {
+
+            /* Process timer expiration.  */
+            _tx_timer_expiration_process();
+        }
+
+        /* Did time slice expire?  */
+        if (_tx_timer_expired_time_slice)
+        {
+
+            /* Time slice interrupted thread.  */
+            _tx_thread_time_slice();
+        }
+    }
+
+    /* Unlock linux mutex. */
+    tx_linux_mutex_unlock(_tx_linux_mutex);
+}
+
diff --git a/ports/win32/vs_2019/example_build/azure_rtos.sln b/ports/win32/vs_2019/example_build/azure_rtos.sln
new file mode 100644
index 00000000..fb6be8b5
--- /dev/null
+++ b/ports/win32/vs_2019/example_build/azure_rtos.sln
@@ -0,0 +1,46 @@
+
+Microsoft Visual Studio Solution File, Format Version 12.00
+# Visual Studio Version 16
+VisualStudioVersion = 16.0.30204.135
+MinimumVisualStudioVersion = 10.0.40219.1
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "sample_threadx", "sample_threadx\sample_threadx.vcxproj", "{7342DEEF-AB3F-00D5-9EDB-2829CD277B76}"
+EndProject
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "tx", "tx\tx.vcxproj", "{51907112-62DA-98D6-7897-5A2FD48B99C3}"
+EndProject
+Global
+	GlobalSection(SolutionConfigurationPlatforms) = preSolution
+		Debug|Win32 = Debug|Win32
+		Debug|x64 = Debug|x64
+		Release|Win32 = Release|Win32
+		Release|x64 = Release|x64
+		Template|Win32 = Template|Win32
+		Template|x64 = Template|x64
+	EndGlobalSection
+	GlobalSection(ProjectConfigurationPlatforms) = postSolution
+		{7342DEEF-AB3F-00D5-9EDB-2829CD277B76}.Debug|Win32.ActiveCfg = Debug|Win32
+		{7342DEEF-AB3F-00D5-9EDB-2829CD277B76}.Debug|Win32.Build.0 = Debug|Win32
+		{7342DEEF-AB3F-00D5-9EDB-2829CD277B76}.Debug|x64.ActiveCfg = Debug|Win32
+		{7342DEEF-AB3F-00D5-9EDB-2829CD277B76}.Release|Win32.ActiveCfg = Release|Win32
+		{7342DEEF-AB3F-00D5-9EDB-2829CD277B76}.Release|Win32.Build.0 = Release|Win32
+		{7342DEEF-AB3F-00D5-9EDB-2829CD277B76}.Release|x64.ActiveCfg = Release|Win32
+		{7342DEEF-AB3F-00D5-9EDB-2829CD277B76}.Template|Win32.ActiveCfg = Release|Win32
+		{7342DEEF-AB3F-00D5-9EDB-2829CD277B76}.Template|Win32.Build.0 = Release|Win32
+		{7342DEEF-AB3F-00D5-9EDB-2829CD277B76}.Template|x64.ActiveCfg = Release|Win32
+		{7342DEEF-AB3F-00D5-9EDB-2829CD277B76}.Template|x64.Build.0 = Release|Win32
+		{51907112-62DA-98D6-7897-5A2FD48B99C3}.Debug|Win32.ActiveCfg = Debug|Win32
+		{51907112-62DA-98D6-7897-5A2FD48B99C3}.Debug|Win32.Build.0 = Debug|Win32
+		{51907112-62DA-98D6-7897-5A2FD48B99C3}.Debug|x64.ActiveCfg = Debug|Win32
+		{51907112-62DA-98D6-7897-5A2FD48B99C3}.Release|Win32.ActiveCfg = Release|Win32
+		{51907112-62DA-98D6-7897-5A2FD48B99C3}.Release|Win32.Build.0 = Release|Win32
+		{51907112-62DA-98D6-7897-5A2FD48B99C3}.Release|x64.ActiveCfg = Release|Win32
+		{51907112-62DA-98D6-7897-5A2FD48B99C3}.Template|Win32.ActiveCfg = Template|Win32
+		{51907112-62DA-98D6-7897-5A2FD48B99C3}.Template|Win32.Build.0 = Template|Win32
+		{51907112-62DA-98D6-7897-5A2FD48B99C3}.Template|x64.ActiveCfg = Template|Win32
+	EndGlobalSection
+	GlobalSection(SolutionProperties) = preSolution
+		HideSolutionNode = FALSE
+	EndGlobalSection
+	GlobalSection(ExtensibilityGlobals) = postSolution
+		SolutionGuid = {FAE0BBF6-14F8-4320-AAB9-65E1361EB38A}
+	EndGlobalSection
+EndGlobal
diff --git a/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.c b/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.c
new file mode 100644
index 00000000..46d2aff4
--- /dev/null
+++ b/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.c
@@ -0,0 +1,381 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include   "tx_api.h"
+#include   
+
+#define     DEMO_STACK_SIZE         1024
+#define     DEMO_BYTE_POOL_SIZE     9120
+#define     DEMO_BLOCK_POOL_SIZE    100
+#define     DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG           thread_0_counter;
+ULONG           thread_1_counter;
+ULONG           thread_1_messages_sent;
+ULONG           thread_2_counter;
+ULONG           thread_2_messages_received;
+ULONG           thread_3_counter;
+ULONG           thread_4_counter;
+ULONG           thread_5_counter;
+ULONG           thread_6_counter;
+ULONG           thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+/* Define main entry point.  */
+
+int main()
+{
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Print results.  */
+        printf("**** ThreadX Win32 Demonstration **** (c) 1996-2020 Microsoft Corporation\n\n");
+        printf("           thread 0 events sent:          %lu\n", thread_0_counter);
+        printf("           thread 1 messages sent:        %lu\n", thread_1_counter);
+        printf("           thread 2 messages received:    %lu\n", thread_2_counter);
+        printf("           thread 3 obtained semaphore:   %lu\n", thread_3_counter);
+        printf("           thread 4 obtained semaphore:   %lu\n", thread_4_counter);
+        printf("           thread 5 events received:      %lu\n", thread_5_counter);
+        printf("           thread 6 mutex obtained:       %lu\n", thread_6_counter);
+        printf("           thread 7 mutex obtained:       %lu\n\n", thread_7_counter);
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.vcxproj b/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.vcxproj
new file mode 100644
index 00000000..dbb6c98b
--- /dev/null
+++ b/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.vcxproj
@@ -0,0 +1,139 @@
+
+
+  
+    
+      Debug
+      Win32
+    
+    
+      Release
+      Win32
+    
+  
+  
+    
+    
+    {7342DEEF-AB3F-00D5-9EDB-2829CD277B76}
+    10.0
+  
+  
+  
+    Application
+    false
+    MultiByte
+    v142
+  
+  
+    Application
+    false
+    MultiByte
+    v142
+  
+  
+  
+  
+  
+    
+    
+  
+  
+    
+    
+  
+  
+  
+    .\Debug\
+    .\Debug\
+    false
+  
+  
+    .\Release\
+    .\Release\
+    false
+  
+  
+    
+      MultiThreadedDebug
+      Default
+      true
+      Disabled
+      true
+      Level3
+      WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions)
+      .\Debug\
+      .\Debug\sample_threadx.pch
+      .\Debug\
+      .\Debug\
+      EnableFastChecks
+      ..\..\inc;..\..\..\..\..\common\inc
+      false
+      false
+    
+    
+      .\Debug\sample_threadx.tlb
+    
+    
+      0x0409
+      _DEBUG;%(PreprocessorDefinitions)
+    
+    
+      true
+      .\Debug\sample_threadx.bsc
+    
+    
+      true
+      true
+      Console
+      .\Debug\sample_threadx.exe
+      odbc32.lib;odbccp32.lib;%(AdditionalDependencies)
+    
+  
+  
+    
+      MultiThreaded
+      OnlyExplicitInline
+      true
+      true
+      MaxSpeed
+      true
+      Level3
+      WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions)
+      .\Release\
+      .\Release\sample_threadx.pch
+      .\Release\
+      .\Release\
+      ../../../generic
+      false
+    
+    
+      .\Release\sample_threadx.tlb
+    
+    
+      0x0409
+      NDEBUG;%(PreprocessorDefinitions)
+    
+    
+      true
+      .\Release\sample_threadx.bsc
+    
+    
+      true
+      Console
+      .\Release\sample_threadx.exe
+      odbc32.lib;odbccp32.lib;%(AdditionalDependencies)
+    
+  
+  
+    
+    
+  
+  
+    
+  
+  
+    
+  
+  
+  
+  
+
\ No newline at end of file
diff --git a/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.vcxproj.filters b/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.vcxproj.filters
new file mode 100644
index 00000000..457cd446
--- /dev/null
+++ b/ports/win32/vs_2019/example_build/sample_threadx/sample_threadx.vcxproj.filters
@@ -0,0 +1,29 @@
+
+
+  
+    
+      {6006269e-f4d4-4e46-be11-4a87e3703f4b}
+      h;hpp;hxx;hm;inl
+    
+    
+      {92d04b48-db8b-4511-a4fd-305688bda3d5}
+      cpp;c;cxx;rc;def;r;odl;idl;hpj;bat
+    
+  
+  
+    
+      inc
+    
+    
+      inc
+    
+  
+  
+    
+      src
+    
+  
+  
+    
+  
+
\ No newline at end of file
diff --git a/ports/win32/vs_2019/example_build/tx/tx.vcxproj b/ports/win32/vs_2019/example_build/tx/tx.vcxproj
new file mode 100644
index 00000000..827ae65e
--- /dev/null
+++ b/ports/win32/vs_2019/example_build/tx/tx.vcxproj
@@ -0,0 +1,339 @@
+
+
+  
+    
+      Debug
+      Win32
+    
+    
+      Release
+      Win32
+    
+    
+      Template
+      Win32
+    
+  
+  
+    
+    
+    
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+    
+    
+    
+    
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+  
+  
+    
+    
+    {51907112-62DA-98D6-7897-5A2FD48B99C3}
+    10.0
+  
+  
+  
+    Application
+    v142
+  
+  
+    StaticLibrary
+    false
+    MultiByte
+    v142
+  
+  
+    StaticLibrary
+    false
+    MultiByte
+    v142
+  
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+    .\Release\
+    .\Release\
+  
+  
+    .\Debug\
+    .\Debug\
+  
+  
+    
+      MultiThreaded
+      OnlyExplicitInline
+      true
+      true
+      MaxSpeed
+      true
+      Level3
+      WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions)
+      .\Release\
+      .\Release\tx.pch
+      .\Release\
+      .\Release\
+      ..\;..\..\..\generic
+      None
+      false
+    
+    
+      0x0409
+      NDEBUG;%(PreprocessorDefinitions)
+    
+    
+      true
+      .\Release\tx.bsc
+    
+    
+      true
+      .\Release\tx.lib
+    
+  
+  
+    
+      MultiThreadedDebug
+      Default
+      true
+      Disabled
+      true
+      Level3
+      ProgramDatabase
+      WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions)
+      .\Debug\
+      .\Debug\tx.pch
+      .\Debug\
+      .\Debug\
+      EnableFastChecks
+      ..\..\inc;..\..\..\..\..\common\inc
+      false
+      true
+    
+    
+      0x0409
+      _DEBUG;%(PreprocessorDefinitions)
+    
+    
+      true
+      .\Debug\tx.bsc
+    
+    
+      true
+      .\Debug\tx.lib
+    
+  
+  
+  
+  
+
\ No newline at end of file
diff --git a/ports/win32/vs_2019/example_build/tx/tx.vcxproj.filters b/ports/win32/vs_2019/example_build/tx/tx.vcxproj.filters
new file mode 100644
index 00000000..303c5d5f
--- /dev/null
+++ b/ports/win32/vs_2019/example_build/tx/tx.vcxproj.filters
@@ -0,0 +1,633 @@
+
+
+  
+    
+      {096c4605-3053-4040-8f19-1e6fedb9568e}
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+    
+      src
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\ No newline at end of file
diff --git a/ports/win32/vs_2019/inc/tx_port.h b/ports/win32/vs_2019/inc/tx_port.h
new file mode 100644
index 00000000..c5f666f8
--- /dev/null
+++ b/ports/win32/vs_2019/inc/tx_port.h
@@ -0,0 +1,453 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */ 
+/*                                                                        */ 
+/*    tx_port.h                                          Win32/Visual     */ 
+/*                                                           6.0.1        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This file contains data type definitions that make the ThreadX      */ 
+/*    real-time kernel function identically on a variety of different     */ 
+/*    processor architectures.  For example, the size or number of bits   */ 
+/*    in an "int" data type vary between microprocessor architectures and */ 
+/*    even C compilers for the same microprocessor.  ThreadX does not     */ 
+/*    directly use native C data types.  Instead, ThreadX creates its     */ 
+/*    own special types that can be mapped to actual data types by this   */ 
+/*    file to guarantee consistency in the interface and functionality.   */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include 
+#include 
+
+
+/* Define performance metric symbols.  */
+
+#ifndef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO
+#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO
+#endif
+
+#ifndef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO
+#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO
+#endif
+
+#ifndef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO
+#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO
+#endif
+
+#ifndef TX_MUTEX_ENABLE_PERFORMANCE_INFO
+#define TX_MUTEX_ENABLE_PERFORMANCE_INFO
+#endif
+
+#ifndef TX_QUEUE_ENABLE_PERFORMANCE_INFO
+#define TX_QUEUE_ENABLE_PERFORMANCE_INFO
+#endif
+
+#ifndef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO
+#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO
+#endif
+
+#ifndef TX_THREAD_ENABLE_PERFORMANCE_INFO
+#define TX_THREAD_ENABLE_PERFORMANCE_INFO
+#endif
+
+#ifndef TX_TIMER_ENABLE_PERFORMANCE_INFO
+#define TX_TIMER_ENABLE_PERFORMANCE_INFO
+#endif
+
+
+/* Enable trace info.  */
+
+#ifndef TX_ENABLE_EVENT_TRACE
+#define TX_ENABLE_EVENT_TRACE
+#endif
+
+
+/* Define ThreadX basic types for this port.  */ 
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Add Win32 debug insert prototype.  */
+ 
+void    _tx_win32_debug_entry_insert(char *action, char *file, unsigned long line);
+
+#ifndef TX_WIN32_DEBUG_ENABLE
+
+/* If Win32 debug is not enabled, turn logging into white-space.  */
+
+#define _tx_win32_debug_entry_insert(a, b, c)
+
+#endif
+
+
+
+/* Define the TX_MEMSET macro to remove library reference.  */
+
+#define TX_MEMSET(a,b,c)                        {                                       \
+                                                UCHAR *ptr;                             \
+                                                UCHAR value;                            \
+                                                UINT  i, size;                          \
+                                                    ptr =    (UCHAR *) ((VOID *) a);    \
+                                                    value =  (UCHAR) b;                 \
+                                                    size =   (UINT) c;                  \
+                                                    for (i = 0; i < size; i++)          \
+                                                    {                                   \
+                                                        *ptr++ =  value;                \
+                                                    }                                   \
+                                                }
+                                               
+
+/* Include windows include file.  */
+
+#include 
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              400         /* Default timer thread stack size - Not used in Win32 port!  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */ 
+#endif
+
+
+/* Define various constants for the ThreadX  port.  */ 
+
+#define TX_INT_DISABLE                          1           /* Disable interrupts               */
+#define TX_INT_ENABLE                           0           /* Enable interrupts                */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ((ULONG) (_tx_win32_time_stamp.LowPart));
+#endif
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port-specific trace extension to pickup the Windows timer.  */
+
+#define TX_TRACE_PORT_EXTENSION                 QueryPerformanceCounter((LARGE_INTEGER *)&_tx_win32_time_stamp); 
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          0
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#define TX_INLINE_INITIALIZATION
+
+
+/* Define the Win32-specific initialization code that is expanded in the generic source.  */
+
+void    _tx_initialize_start_interrupts(void);
+
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION                       _tx_initialize_start_interrupts();
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0                                               HANDLE tx_thread_win32_thread_handle; \
+                                                                            DWORD  tx_thread_win32_thread_id; \
+                                                                            HANDLE tx_thread_win32_thread_run_semaphore; \
+                                                                            UINT   tx_thread_win32_suspension_type; \
+                                                                            UINT   tx_thread_win32_int_disabled_flag;
+#define TX_THREAD_EXTENSION_1                  
+#define TX_THREAD_EXTENSION_2          
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)                              
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+struct TX_THREAD_STRUCT;
+
+/* Define the Win32 critical section data structure.  */
+
+typedef struct TX_WIN32_CRITICAL_SECTION_STRUCT
+{
+    HANDLE                                      tx_win32_critical_section_mutex_handle;
+    DWORD                                       tx_win32_critical_section_owner;
+    ULONG                                       tx_win32_critical_section_nested_count;
+} TX_WIN32_CRITICAL_SECTION;
+
+
+/* Define Win32-specific critical section APIs.  */
+
+void  _tx_win32_critical_section_obtain(TX_WIN32_CRITICAL_SECTION *critical_section);
+void  _tx_win32_critical_section_release(TX_WIN32_CRITICAL_SECTION *critical_section);
+void  _tx_win32_critical_section_release_all(TX_WIN32_CRITICAL_SECTION *critical_section);
+
+
+/* Define post completion processing for tx_thread_delete, so that the Win32 thread resources are properly removed.  */
+
+#define TX_THREAD_DELETE_PORT_COMPLETION(thread_ptr)                            \
+{                                                                               \
+BOOL            win32_status;                                                   \
+DWORD           exitcode;                                                       \
+HANDLE          threadrunsemaphore;                                             \
+HANDLE          threadhandle;                                                   \
+    threadhandle =       thread_ptr -> tx_thread_win32_thread_handle;           \
+    threadrunsemaphore = thread_ptr -> tx_thread_win32_thread_run_semaphore;    \
+    _tx_thread_interrupt_restore(tx_saved_posture);                             \
+    do                                                                          \
+    {                                                                           \
+        win32_status =  GetExitCodeThread(threadhandle, &exitcode);             \
+        if ((win32_status) && (exitcode != STILL_ACTIVE))                       \
+        {                                                                       \
+            break;                                                              \
+        }                                                                       \
+        ResumeThread(threadhandle);                                             \
+        ReleaseSemaphore(threadrunsemaphore, 1, NULL);                          \
+        Sleep(1);                                                               \
+    } while (1);                                                                \
+    CloseHandle(threadhandle);                                                  \
+    tx_saved_posture =   _tx_thread_interrupt_disable();                        \
+}
+
+
+/* Define post completion processing for tx_thread_reset, so that the Win32 thread resources are properly removed.  */
+
+#define TX_THREAD_RESET_PORT_COMPLETION(thread_ptr)                             \
+{                                                                               \
+BOOL            win32_status;                                                   \
+DWORD           exitcode;                                                       \
+HANDLE          threadrunsemaphore;                                             \
+HANDLE          threadhandle;                                                   \
+    threadhandle =       thread_ptr -> tx_thread_win32_thread_handle;           \
+    threadrunsemaphore = thread_ptr -> tx_thread_win32_thread_run_semaphore;    \
+    _tx_thread_interrupt_restore(tx_saved_posture);                             \
+    do                                                                          \
+    {                                                                           \
+        win32_status =  GetExitCodeThread(threadhandle, &exitcode);             \
+        if ((win32_status) && (exitcode != STILL_ACTIVE))                       \
+        {                                                                       \
+            break;                                                              \
+        }                                                                       \
+        ResumeThread(threadhandle);                                             \
+        ReleaseSemaphore(threadrunsemaphore, 1, NULL);                          \
+        Sleep(1);                                                               \
+    } while (1);                                                                \
+    CloseHandle(threadhandle);                                                  \
+    tx_saved_posture =   _tx_thread_interrupt_disable();                        \
+}
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+UINT   _tx_thread_interrupt_disable(void);
+VOID   _tx_thread_interrupt_restore(UINT previous_posture);
+
+#define TX_INTERRUPT_SAVE_AREA UINT             tx_saved_posture;
+
+#define TX_DISABLE                              tx_saved_posture =   _tx_thread_interrupt_disable();
+
+#define TX_RESTORE                              _tx_thread_interrupt_restore(tx_saved_posture);
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Win32/Visual Studio Version 6.0 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+
+/* Define externals for the Win32 port of ThreadX.  */
+
+extern TX_WIN32_CRITICAL_SECTION                _tx_win32_critical_section;
+extern HANDLE                                   _tx_win32_scheduler_semaphore;
+extern DWORD                                    _tx_win32_scheduler_id;
+extern ULONG                                    _tx_win32_global_int_disabled_flag;
+extern LARGE_INTEGER                            _tx_win32_time_stamp;
+extern ULONG                                    _tx_win32_system_error;
+extern HANDLE                                   _tx_win32_timer_handle;
+extern DWORD                                    _tx_win32_timer_id;
+extern LARGE_INTEGER                            _tx_win32_time_stamp;
+
+
+#ifndef TX_WIN32_MEMORY_SIZE
+#define TX_WIN32_MEMORY_SIZE                    64000
+#endif
+
+#ifndef TX_TIMER_PERIODIC
+#define TX_TIMER_PERIODIC                       18
+#endif
+
+#endif
+
+
+
+
diff --git a/ports/win32/vs_2019/readme_threadx.txt b/ports/win32/vs_2019/readme_threadx.txt
new file mode 100644
index 00000000..348d1a37
--- /dev/null
+++ b/ports/win32/vs_2019/readme_threadx.txt
@@ -0,0 +1,155 @@
+                         Microsoft's Azure RTOS ThreadX for Win32 
+
+                              Using the Visual Studio Tools
+
+
+1. Open the ThreadX Project Workspace
+
+In order to build the ThreadX library and the ThreadX demonstration first load 
+the Azure RTOS Workspace azure_rtos.sln, which is located inside the "example_build"
+directory. 
+
+
+2. Building the ThreadX run-time Library
+
+Building the ThreadX library is easy; simply make the "tx" project active and 
+then select the build button. You should now observe the compilation of the 
+ThreadX library source. This project build produces the ThreadX library file 
+tx.lib.
+
+
+3.  Building the Demonstration System
+
+You are now ready to run the ThreadX Win32 demonstration. Simply make the 
+"sample_thread" project active and then select the build button. When the build
+is finished, select the run button from Visual Studio and observe various
+demonstration statistics being printed to the console window. You may also set
+breakpoints, single step, perform data watches, etc.
+
+
+4.  System Initialization
+
+The system entry point is at main(), which is defined in the application. 
+Once the application calls tx_kernel_enter, ThreadX starts running and 
+performs various initialization duties prior to starting the scheduler. The 
+Win32-specific initialization is done in the function _tx_initialize_low_level,
+which is located in the file tx_initialize_low_level.c. This function is 
+responsible for setting up various system data structures and simulated 
+interrupts - including the periodic timer interrupt source for ThreadX.
+
+In addition, _tx_initialize_low_level determines the first available 
+address for use by the application. In Win32, this is basically done
+by using malloc to get a big block of memory from Windows.
+
+
+5.  Win32 Implementation
+
+ThreadX for Win32 is implemented using Win32 threads. Each application
+thread in ThreadX actually runs as a Win32 thread. The determination of
+which application thread to run is made by the ThreadX scheduler, which 
+itself is a Win32 thread. The ThreadX scheduler is the highest priority 
+thread in the system.
+
+Interrupts in ThreadX/Win32 are also simulated by threads. A good example
+is the ThreadX system timer interrupt, which can be found in 
+tx_initialize_low_level.c.
+
+5.1  ThreadX Limitations
+
+ThreadX for Win32 behaves in the same manner as ThreadX in an embedded 
+environment EXCEPT in the case of thread termination. Unfortunately, the 
+Win32 API does not have a good mechanism to terminate threads and instead
+must rely on the thread itself terminating. Hence, threads in the ThreadX
+Win32 implementation must have some ThreadX call periodically in their 
+processing if they can be terminated by another ThreadX thread.
+
+
+6.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+breakpoints inside of ThreadX itself. Of course, this costs some 
+performance. To make it run faster, you can change the tx project file to 
+enable all compiler optimizations. In addition, you can eliminate the 
+ThreadX basic API error checking by compiling your application code with the 
+symbol TX_DISABLE_ERROR_CHECKING defined.
+
+
+7.  Interrupt Handling
+
+ThreadX provides simulated interrupt handling with Win32 threads. Simulated
+interrupt threads may be created by the application or may be added to the
+simulated timer interrupt defined in tx_initialize_low_level.c. The following 
+format for creating simulated interrupts should be used:
+
+7.1  Data structures
+
+Here is an example of how to define the Win32 data structures and prototypes
+necessary to create a simulated interrupt thread:
+
+HANDLE       _sample_win32_interrupt_handle;
+DWORD        _sample_win32_interrupt_id;
+DWORD WINAPI _sample_win32_interrupt(LPVOID);
+
+
+7.2  Creating a Simulated Interrupt Thread
+
+Here is an example of how to create a simulated interrupt thread in Win32.
+This may be done inside of tx_initialize_low_level.c or from your application code
+
+        _sample_win32_interrupt_handle =
+            CreateThread(NULL, 0, _sample_win32_interrupt, (LPVOID) &_sample_win32_interrupt_handle,
+                    CREATE_SUSPENDED, &_sample_win32_interrupt_id);
+
+        SetThreadPriority(_sample_win32_interrupt_handle, THREAD_PRIORITY_BELOW_NORMAL);
+
+
+7.3  Activating the Simulated Interrupt Thread
+
+Simulated interrupt threads should not be activated until initialization is complete, i.e. until
+ThreadX is ready to schedule threads. The following activation code may be added to the routine
+in tx_initialize_low_level.c called _tx_initialize_start_interrupts or into the application code directly:
+
+        ResumeThread(_sample_win32_interrupt_handle);
+
+
+7.4  Simulated Interrupt Thread Template
+
+The following is a template for the simulated interrupt thread. This interrupt will occur on
+a periodic basis. 
+
+DWORD WINAPI _sample_win32_interrupt(LPVOID *ptr)
+{
+
+
+    while(1)
+    {
+
+        /* Sleep for the desired time.  */
+        Sleep(18);
+
+        /* Call ThreadX context save for interrupt preparation.  */
+        _tx_thread_context_save();
+
+        /* Call application ISR here!  */
+
+        /* Call ThreadX context restore for interrupt completion.  */
+        _tx_thread_context_restore();
+    } 
+}
+
+
+8.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX version for Win32 using Microsoft Visual C/C++.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/win32/vs_2019/src/tx_initialize_low_level.c b/ports/win32/vs_2019/src/tx_initialize_low_level.c
new file mode 100644
index 00000000..f11df9dc
--- /dev/null
+++ b/ports/win32/vs_2019/src/tx_initialize_low_level.c
@@ -0,0 +1,307 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Initialize                                                          */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include 
+#include 
+#include 
+
+
+/* Define various Win32 objects used by the ThreadX port.  */
+
+TX_WIN32_CRITICAL_SECTION       _tx_win32_critical_section;
+HANDLE                          _tx_win32_scheduler_semaphore;
+DWORD                           _tx_win32_scheduler_id;
+ULONG                           _tx_win32_global_int_disabled_flag;
+LARGE_INTEGER                   _tx_win32_time_stamp;
+ULONG                           _tx_win32_system_error;
+extern TX_THREAD                *_tx_thread_current_ptr;
+
+
+/* Define simulated timer interrupt.  This is done inside a thread, which is
+   how other interrupts may be defined as well.  See code below for an 
+   example.  */
+
+HANDLE                          _tx_win32_timer_handle;
+DWORD                           _tx_win32_timer_id;
+DWORD WINAPI                    _tx_win32_timer_interrupt(LPVOID p);
+
+
+#ifdef TX_WIN32_DEBUG_ENABLE
+
+extern ULONG                    _tx_thread_system_state;
+extern UINT                     _tx_thread_preempt_disable;
+extern TX_THREAD                *_tx_thread_current_ptr;
+extern TX_THREAD                *_tx_thread_execute_ptr;
+
+
+/* Define the maximum size of the Win32 debug array.  */
+
+#ifndef TX_WIN32_DEBUG_EVENT_SIZE
+#define TX_WIN32_DEBUG_EVENT_SIZE           400
+#endif
+
+
+/* Define debug log in order to debug Win32 issues with this port.  */
+
+typedef struct TX_WIN32_DEBUG_ENTRY_STRUCT
+{
+    char                                    *tx_win32_debug_entry_action;
+    LARGE_INTEGER                           tx_win32_debug_entry_timestamp;
+    char                                    *tx_win32_debug_entry_file;
+    unsigned long                           tx_win32_debug_entry_line;
+    TX_WIN32_CRITICAL_SECTION               tx_win32_debug_entry_critical_section;
+    unsigned long                           tx_win32_debug_entry_int_disabled_flag;
+    ULONG                                   tx_win32_debug_entry_system_state;
+    UINT                                    tx_win32_debug_entry_preempt_disable;
+    TX_THREAD                               *tx_win32_debug_entry_current_thread;
+    DWORD                                   tx_win32_debug_entry_current_thread_id;
+    TX_THREAD                               *tx_win32_debug_entry_execute_thread;
+    DWORD                                   tx_win32_debug_entry_execute_thread_id;
+    DWORD                                   tx_win32_debug_entry_running_id;
+} TX_WIN32_DEBUG_ENTRY;
+
+
+/* Define the circular array of Win32 debug entries.  */
+
+TX_WIN32_DEBUG_ENTRY    _tx_win32_debug_entry_array[TX_WIN32_DEBUG_EVENT_SIZE];
+
+
+/* Define the Win32 debug index.  */
+
+unsigned long           _tx_win32_debug_entry_index =  0;
+
+
+/* Now define the debug entry function.  */
+void    _tx_win32_debug_entry_insert(char *action, char *file, unsigned long line)
+{
+
+
+    /* Get the time stamp.  */
+    QueryPerformanceCounter((LARGE_INTEGER *)&_tx_win32_time_stamp);
+
+    /* Setup the debug entry.  */
+    _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_action =             action;
+    _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_timestamp =          _tx_win32_time_stamp;
+    _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_file =               file;
+    _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_line =               line;
+    _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_critical_section =   _tx_win32_critical_section;
+    _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_int_disabled_flag =  _tx_win32_global_int_disabled_flag;
+    _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_system_state =       _tx_thread_system_state;
+    _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_preempt_disable =    _tx_thread_preempt_disable;
+    _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_current_thread =     _tx_thread_current_ptr;
+    if (_tx_thread_current_ptr)
+        _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_current_thread_id =  _tx_thread_current_ptr -> tx_thread_win32_thread_id;
+    else 
+    _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_current_thread_id =  0;
+    _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_execute_thread =     _tx_thread_execute_ptr;
+    if (_tx_thread_execute_ptr)
+        _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_execute_thread_id =  _tx_thread_execute_ptr -> tx_thread_win32_thread_id;
+    else 
+    _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_execute_thread_id =  0;
+    _tx_win32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_running_id =         GetCurrentThreadId();
+
+    /* Now move to the next entry.  */
+    _tx_win32_debug_entry_index++;
+    
+    /* Determine if we need to wrap the list.  */
+    if (_tx_win32_debug_entry_index >= TX_WIN32_DEBUG_EVENT_SIZE)
+    {
+    
+        /* Yes, wrap the list!  */
+        _tx_win32_debug_entry_index =  0;
+    }
+}
+
+#endif
+
+
+/* Define the ThreadX timer interrupt handler.  */
+
+void            _tx_timer_interrupt(void);
+
+
+/* Define other external function references.  */
+
+VOID            _tx_initialize_low_level(VOID);
+VOID            _tx_thread_context_save(VOID);
+VOID            _tx_thread_context_restore(VOID);
+
+
+/* Define other external variable references.  */
+
+extern VOID     *_tx_initialize_unused_memory;
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_initialize_low_level                          Win32/Visual      */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function is responsible for any low-level processor            */ 
+/*    initialization, including setting up interrupt vectors, setting     */ 
+/*    up a periodic timer interrupt source, saving the system stack       */ 
+/*    pointer for use in ISR processing later, and finding the first      */ 
+/*    available RAM memory address for tx_application_define.             */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    CreateMutex                           Win32 create mutex            */ 
+/*    CreateThread                          Win32 create thread           */ 
+/*    CreateSemaphore                       Win32 create semaphore        */ 
+/*    GetCurrentThreadId                    Win32 get current thread ID   */ 
+/*    SetProcessAffinityMask                Win32 process affinity set    */ 
+/*    SetThreadPriority                     Win32 set thread priority     */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    _tx_initialize_kernel_enter           ThreadX entry function        */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_initialize_low_level(VOID)
+{
+
+/* Deprecate TX_WIN32_MULTI_CORE build option and default to restricting
+   execution to one core.  */
+
+#ifndef TX_WIN32_BYPASS_AFFINITY_SETUP
+
+    /* Limit this ThreadX simulation on Win32 to a single core.  */
+    if (SetProcessAffinityMask( GetCurrentProcess(), 1 ) == 0)
+    {
+    
+        /* Error restricting the process to one core.  */
+        printf("ThreadX Win32 error restricting the process to one core!\n");
+        while(1)
+        {
+        }
+    }
+#endif
+
+    /* Pickup the first available memory address.  */
+
+    /* Save the first available memory address.  */
+    _tx_initialize_unused_memory =  malloc(TX_WIN32_MEMORY_SIZE);
+
+    /* Pickup the unique Id of the current thread, which will also be the Id of the scheduler.  */
+    _tx_win32_scheduler_id =        GetCurrentThreadId();
+
+    /* Create the system critical section mutex. This is used by the system to block all other access,
+       analogous to an interrupt lockout on an embedded target.  */
+    _tx_win32_critical_section.tx_win32_critical_section_mutex_handle =  CreateMutex(NULL, FALSE, NULL);
+    _tx_win32_critical_section.tx_win32_critical_section_nested_count =  0;
+    _tx_win32_critical_section.tx_win32_critical_section_owner =         0;
+       
+    /* Create the semaphore that regulates when the scheduler executes.  */
+    _tx_win32_scheduler_semaphore =  CreateSemaphore(NULL, 0, 1, NULL);
+
+    /* Initialize the global interrupt disabled flag.  */
+    _tx_win32_global_int_disabled_flag =  TX_FALSE;
+    
+    /* Setup periodic timer interrupt.  */
+    _tx_win32_timer_handle =
+        CreateThread(NULL, 0, _tx_win32_timer_interrupt, (LPVOID) &_tx_win32_timer_handle,CREATE_SUSPENDED, &_tx_win32_timer_id);
+
+    /* Check for a good thread create.  */
+    if (!_tx_win32_timer_handle)
+    {
+
+        /* Error creating the timer interrupt.  */
+        printf("ThreadX Win32 error creating timer interrupt thread!\n");
+        while(1)
+        {
+        }
+    }
+
+    /* Otherwise, we have a good thread create.  Now set the priority to
+       a level lower than the system thread but higher than the application
+       threads.  */
+    SetThreadPriority(_tx_win32_timer_handle, THREAD_PRIORITY_BELOW_NORMAL);
+
+    /* Done, return to caller.  */
+}
+
+
+/* This routine is called after initialization is complete in order to start
+   all interrupt threads.  Interrupt threads in addition to the timer may 
+   be added to this routine as well.  */
+
+void    _tx_initialize_start_interrupts(void)
+{
+
+    /* Kick the timer thread off to generate the ThreadX periodic interrupt
+       source.  */
+    ResumeThread(_tx_win32_timer_handle);
+}
+
+
+/* Define the ThreadX system timer interrupt.  Other interrupts may be simulated
+   in a similar way.  */
+
+
+DWORD WINAPI _tx_win32_timer_interrupt(LPVOID p)
+{
+
+    while(1)
+    {
+
+        /* Sleep for the desired time.  */
+        Sleep(TX_TIMER_PERIODIC);
+
+        /* Call ThreadX context save for interrupt preparation.  */
+        _tx_thread_context_save();
+
+
+        /* Call the ThreadX system timer interrupt processing.  */
+        _tx_timer_interrupt();
+
+        /* Call ThreadX context restore for interrupt completion.  */
+        _tx_thread_context_restore();
+    } 
+}
diff --git a/ports/win32/vs_2019/src/tx_thread_context_restore.c b/ports/win32/vs_2019/src/tx_thread_context_restore.c
new file mode 100644
index 00000000..8ff1ef23
--- /dev/null
+++ b/ports/win32/vs_2019/src/tx_thread_context_restore.c
@@ -0,0 +1,132 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include "tx_timer.h"
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_thread_context_restore                        Win32/Visual      */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function restores the interrupt context if it is processing a  */ 
+/*    nested interrupt.  If not, it returns to the interrupt thread if no */ 
+/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+/*    if no thread was running, the function returns to the scheduler.    */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    ReleaseSemaphore                      Win32 release semaphore       */ 
+/*    ResumeThread                          Win32 resume thread           */ 
+/*    _tx_win32_critical_section_obtain     Obtain critical section       */ 
+/*    _tx_win32_critical_section_release    Release critical section      */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    ISRs                                  Interrupt Service Routines    */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_thread_context_restore(VOID)
+{
+
+    /* Enter critical section to ensure other threads are not playing with
+       the core ThreadX data structures.  */
+    _tx_win32_critical_section_obtain(&_tx_win32_critical_section);
+
+    /* Debug entry.  */
+    _tx_win32_debug_entry_insert("CONTEXT_RESTORE", __FILE__, __LINE__);
+
+    /* Decrement the nested interrupt count.  */
+    _tx_thread_system_state--;
+
+    /* Determine if this is the first nested interrupt and if a ThreadX
+       application thread was running at the time.  */
+    if ((!_tx_thread_system_state) && (_tx_thread_current_ptr))
+    {
+
+        /* Yes, this is the first and last interrupt processed.  */
+
+        /* Check to see if preemption is required.  */
+        if ((_tx_thread_preempt_disable == 0) && (_tx_thread_current_ptr != _tx_thread_execute_ptr))
+        {
+
+            /* Preempt the running application thread.  We don't need to suspend the 
+               application thread since that is done in the context save processing.  */
+
+            /* Indicate that this thread was suspended asynchronously.  */
+            _tx_thread_current_ptr -> tx_thread_win32_suspension_type =  1;
+
+            /* Save the remaining time-slice and disable it.  */
+            if (_tx_timer_time_slice)
+            {
+
+                _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+                _tx_timer_time_slice =  0;
+            }
+
+            /* Clear the current thread pointer.  */
+            _tx_thread_current_ptr =  TX_NULL;
+
+            /* Wakeup the system thread by setting the system semaphore.  */
+            ReleaseSemaphore(_tx_win32_scheduler_semaphore, 1, NULL);
+        }
+        else
+        {
+
+            /* Since preemption is not required, resume the interrupted thread.  */
+            ResumeThread(_tx_thread_current_ptr -> tx_thread_win32_thread_handle);
+        }
+    }
+
+    /* Leave Win32 critical section.  */
+    _tx_win32_critical_section_release_all(&_tx_win32_critical_section);
+}
+
diff --git a/ports/win32/vs_2019/src/tx_thread_context_save.c b/ports/win32/vs_2019/src/tx_thread_context_save.c
new file mode 100644
index 00000000..676c2832
--- /dev/null
+++ b/ports/win32/vs_2019/src/tx_thread_context_save.c
@@ -0,0 +1,113 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include "tx_timer.h"
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_thread_context_save                           Win32/Visual      */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function saves the context of an executing thread in the       */ 
+/*    beginning of interrupt processing.  The function also ensures that  */ 
+/*    the system stack is used upon return to the calling ISR.            */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    SuspendThread                         Win32 thread suspend          */ 
+/*    _tx_win32_critical_section_obtain     Obtain critical section       */ 
+/*    _tx_win32_critical_section_release    Release critical section      */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    ISRs                                                                */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_thread_context_save(VOID)
+{
+
+TX_THREAD   *thread_ptr;
+
+
+    /* Enter critical section to ensure other threads are not playing with
+       the core ThreadX data structures.  */
+    _tx_win32_critical_section_obtain(&_tx_win32_critical_section);
+
+    /* Debug entry.  */
+    _tx_win32_debug_entry_insert("CONTEXT_SAVE", __FILE__, __LINE__);
+
+    /* Pickup the current thread pointer.  */
+    thread_ptr =  _tx_thread_current_ptr;
+
+    /* If an application thread is running, suspend it to simulate preemption. */
+    if ((thread_ptr) && (_tx_thread_system_state == 0))
+    {
+
+        /* Yes, this is the first interrupt and an application thread is running...
+           suspend it!  */
+
+        /* Suspend the thread to simulate preemption.  Note that the thread is suspended BEFORE the protection get
+           flag is checked to ensure there is not a race condition between this thread and the update of that flag.  */
+        SuspendThread(thread_ptr -> tx_thread_win32_thread_handle);
+
+        /* Debug entry.  */
+        _tx_win32_debug_entry_insert("CONTEXT_SAVE-suspend_thread", __FILE__, __LINE__);
+
+    }
+
+    /* Increment the nested interrupt condition.  */
+    _tx_thread_system_state++;
+
+    /* Exit Win32 critical section.  */
+    _tx_win32_critical_section_release(&_tx_win32_critical_section);
+}
+
diff --git a/ports/win32/vs_2019/src/tx_thread_interrupt_control.c b/ports/win32/vs_2019/src/tx_thread_interrupt_control.c
new file mode 100644
index 00000000..671758a1
--- /dev/null
+++ b/ports/win32/vs_2019/src/tx_thread_interrupt_control.c
@@ -0,0 +1,213 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+
+#include 
+
+/* Define small routines used for the TX_DISABLE/TX_RESTORE macros.  */
+
+UINT   _tx_thread_interrupt_disable(void)
+{
+
+UINT    previous_value;
+
+
+    previous_value =  _tx_thread_interrupt_control(TX_INT_DISABLE);
+    return(previous_value);
+}
+
+
+VOID   _tx_thread_interrupt_restore(UINT previous_posture)
+{
+
+    previous_posture =  _tx_thread_interrupt_control(previous_posture);
+}
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_thread_interrupt_control                      Win32/Visual      */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function is responsible for changing the interrupt lockout     */ 
+/*    posture of the system.                                              */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    new_posture                           New interrupt lockout posture */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    old_posture                           Old interrupt lockout posture */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    ExitThread                            Win32 thread exit             */ 
+/*    GetCurrentThread                      Win32 get current thread      */ 
+/*    GetCurrentThreadId                    Win32 get current thread ID   */ 
+/*    GetThreadPriority                     Win32 get thread priority     */ 
+/*    _tx_win32_critical_section_obtain     Obtain critical section       */ 
+/*    _tx_win32_critical_section_release    Release critical section      */ 
+/*    _tx_win32_critical_section_release_all                              */ 
+/*                                          Release critical section      */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    Application Code                                                    */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+UINT   _tx_thread_interrupt_control(UINT new_posture)
+{
+
+UINT        old_posture;
+HANDLE      threadhandle;
+int         threadpriority; 
+DWORD       threadid;
+TX_THREAD   *thread_ptr; 
+
+
+    /* Enter Win32 critical section.  */
+    _tx_win32_critical_section_obtain(&_tx_win32_critical_section);
+
+#ifdef TX_WIN32_DEBUG_ENABLE
+
+    /* Determine if this is a disable or enable request.  */
+    if (new_posture == TX_INT_ENABLE)
+    {
+        /* Enable.  */
+        _tx_win32_debug_entry_insert("RESTORE", __FILE__, __LINE__);
+    }
+    else
+    {   
+        /* Disable.  */
+        _tx_win32_debug_entry_insert("DISABLE", __FILE__, __LINE__);
+    }
+#endif
+
+    /* Determine if the thread was terminated.  */
+
+    /* Pickup the handle of the current thread.  */
+    threadhandle =    GetCurrentThread();
+
+    /* Pickup the current thread pointer.  */
+    thread_ptr =      _tx_thread_current_ptr;
+
+    /* Pickup the priority of the current thread.  */
+    threadpriority =  GetThreadPriority(threadhandle); 
+
+    /* Pickup the ID of the current thread.  */
+    threadid =        GetCurrentThreadId();
+
+    /* Determine if this is a thread (THREAD_PRIORITY_LOWEST) and it does not 
+       match the current thread pointer.  */
+    if ((threadpriority == THREAD_PRIORITY_LOWEST) && 
+        ((!thread_ptr) || (thread_ptr -> tx_thread_win32_thread_id != threadid))) 
+    { 
+
+        /* This indicates the Win32 thread was actually terminated by ThreadX is only 
+           being allowed to run in order to cleanup its resources.  */
+        _tx_win32_critical_section_release_all(&_tx_win32_critical_section);
+
+        /* Exit this thread.  */
+        ExitThread(0); 
+    } 
+
+    /* Determine the current interrupt lockout condition.  */
+    if (_tx_win32_critical_section.tx_win32_critical_section_nested_count == 1)
+    {
+
+        /* First pass through, interrupts are enabled.  */
+        old_posture =  TX_INT_ENABLE;
+    }
+    else
+    {
+
+        /* Interrupts are disabled.  */
+        old_posture =  TX_INT_DISABLE;
+    }
+
+    /* First, determine if this call is from a non-thread.  */
+    if (_tx_thread_system_state)
+    {
+
+        /* Determine how to apply the new posture.  */
+        if (new_posture == TX_INT_ENABLE)
+        {
+
+            /* Clear the disabled flag.  */
+            _tx_win32_global_int_disabled_flag =  TX_FALSE;
+
+            /* Determine if the critical section is locked.  */
+            _tx_win32_critical_section_release_all(&_tx_win32_critical_section);
+        }
+        else if (new_posture == TX_INT_DISABLE)
+        {
+
+            /* Set the disabled flag.  */
+            _tx_win32_global_int_disabled_flag =  TX_TRUE;
+        }
+    }
+    else if (thread_ptr) 
+    {
+
+        /* Determine how to apply the new posture.  */
+        if (new_posture == TX_INT_ENABLE)
+        {
+
+            /* Clear the disabled flag.  */
+            _tx_thread_current_ptr -> tx_thread_win32_int_disabled_flag =  TX_FALSE;
+
+            /* Determine if the critical section is locked.  */
+            _tx_win32_critical_section_release_all(&_tx_win32_critical_section);
+        }
+        else if (new_posture == TX_INT_DISABLE)
+        {
+
+            /* Set the disabled flag.  */
+            _tx_thread_current_ptr -> tx_thread_win32_int_disabled_flag =  TX_TRUE;
+        }
+    }
+
+    /* Return the previous interrupt disable posture.  */
+    return(old_posture);
+}
+
diff --git a/ports/win32/vs_2019/src/tx_thread_schedule.c b/ports/win32/vs_2019/src/tx_thread_schedule.c
new file mode 100644
index 00000000..5b8a756d
--- /dev/null
+++ b/ports/win32/vs_2019/src/tx_thread_schedule.c
@@ -0,0 +1,291 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include "tx_timer.h"
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_thread_schedule                               Win32/Visual      */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function waits for a thread control block pointer to appear in */ 
+/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */ 
+/*    in the variable, the corresponding thread is resumed.               */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    ReleaseSemaphore                      Win32 release semaphore       */ 
+/*    ResumeThread                          Win32 resume thread           */ 
+/*    Sleep                                 Win32 thread sleep            */ 
+/*    WaitForSingleObject                   Win32 wait on a semaphore     */ 
+/*    _tx_win32_critical_section_obtain     Obtain critical section       */ 
+/*    _tx_win32_critical_section_release    Release critical section      */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    _tx_initialize_kernel_enter          ThreadX entry function         */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_thread_schedule(VOID)
+{
+
+
+    /* Loop forever.  */
+    while(1)
+    {
+
+        /* Wait for a thread to execute and all ISRs to complete.  */
+        while(1)
+        {
+
+
+            /* Enter Win32 critical section.  */
+            _tx_win32_critical_section_obtain(&_tx_win32_critical_section);
+
+            /* Debug entry.  */
+            _tx_win32_debug_entry_insert("SCHEDULE-wake_up", __FILE__, __LINE__);
+
+            /* Determine if there is a thread ready to execute AND all ISRs 
+               are complete.  */
+            if ((_tx_thread_execute_ptr != TX_NULL) && (_tx_thread_system_state == 0))
+            {
+
+                /* Get out of this loop and schedule the thread!  */
+                break;
+            }
+            else
+            {
+
+                /* Leave the critical section.  */
+                _tx_win32_critical_section_release(&_tx_win32_critical_section);
+
+                /* Now sleep so we don't block forever.  */
+                Sleep(2);
+            }
+        }
+        
+        /* Yes! We have a thread to execute. Note that the critical section is already 
+           active from the scheduling loop above.  */
+
+        /* Setup the current thread pointer.  */
+        _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+
+        /* Increment the run count for this thread.  */
+        _tx_thread_current_ptr -> tx_thread_run_count++;
+
+        /* Setup time-slice, if present.  */
+        _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+
+        /* Determine how the thread was suspended.  */
+        if (_tx_thread_current_ptr -> tx_thread_win32_suspension_type)
+        {
+
+            /* Debug entry.  */
+            _tx_win32_debug_entry_insert("SCHEDULE-resume_thread", __FILE__, __LINE__);
+
+            /* Pseudo interrupt suspension.  The thread is not waiting on
+               its run semaphore.  */
+            ResumeThread(_tx_thread_current_ptr -> tx_thread_win32_thread_handle);
+        }
+        else
+        {
+
+            /* Debug entry.  */
+            _tx_win32_debug_entry_insert("SCHEDULE-release_sem", __FILE__, __LINE__);
+
+            /* Let the thread run again by releasing its run semaphore.  */
+            ReleaseSemaphore(_tx_thread_current_ptr -> tx_thread_win32_thread_run_semaphore, 1, NULL);
+        }
+
+        /* Debug entry.  */
+        _tx_win32_debug_entry_insert("SCHEDULE-self_suspend_sem", __FILE__, __LINE__);
+
+        /* Exit Win32 critical section.  */
+        _tx_win32_critical_section_release(&_tx_win32_critical_section);
+
+        /* Now suspend the main thread so the application thread can run.  */
+        WaitForSingleObject(_tx_win32_scheduler_semaphore, INFINITE);
+    }
+}
+
+
+/* Define the ThreadX Win32 critical section get, release, and release all functions.  */
+
+void    _tx_win32_critical_section_obtain(TX_WIN32_CRITICAL_SECTION *critical_section)
+{
+
+TX_THREAD     *thread_ptr;
+
+
+    /* Is the protection owned?  */
+    if (critical_section -> tx_win32_critical_section_owner == GetCurrentThreadId())
+    {
+    
+        /* Simply increment the nested counter.  */
+        critical_section -> tx_win32_critical_section_nested_count++;
+    }
+    else
+    {        
+
+        /* Pickup the current thread pointer.  */
+        thread_ptr =  _tx_thread_current_ptr;
+
+        /* Get the Win32 critical section.  */
+        while (WaitForSingleObject(critical_section -> tx_win32_critical_section_mutex_handle, 3) != WAIT_OBJECT_0)
+        {
+        }
+    
+        /* At this point we have the mutex.  */
+    
+        /* Increment the nesting counter.  */
+        critical_section -> tx_win32_critical_section_nested_count =  1;
+    
+        /* Remember the owner.  */
+        critical_section -> tx_win32_critical_section_owner =  GetCurrentThreadId();
+    }
+}
+
+
+void    _tx_win32_critical_section_release(TX_WIN32_CRITICAL_SECTION *critical_section)
+{
+
+
+    /* Ensure the caller is the mutex owner.  */
+    if (critical_section -> tx_win32_critical_section_owner == GetCurrentThreadId())
+    {
+    
+        /* Determine if there is protection.  */
+        if (critical_section -> tx_win32_critical_section_nested_count)
+        {
+    
+            /* Decrement the nesting counter.  */
+            critical_section -> tx_win32_critical_section_nested_count--;
+    
+            /* Determine if the critical section is now being released.  */
+            if (critical_section -> tx_win32_critical_section_nested_count == 0)
+            {
+        
+                /* Yes, it is being released clear the owner.  */
+                critical_section -> tx_win32_critical_section_owner =  0;
+
+                /* Finally, release the mutex.  */
+                if (ReleaseMutex(critical_section -> tx_win32_critical_section_mutex_handle) != TX_TRUE)
+                {
+                
+                    /* Increment the system error counter.  */
+                    _tx_win32_system_error++;
+                }
+
+                /* Just in case, make sure there the mutex is not owned.  */
+                while (ReleaseMutex(critical_section -> tx_win32_critical_section_mutex_handle) == TX_TRUE)
+                {
+
+                    /* Increment the system error counter.  */
+                    _tx_win32_system_error++;
+                }
+
+                /* Sleep for 0, just to relinquish to other ready threads.  */
+                Sleep(0);
+			}
+        }
+    }
+    else
+    {
+    
+        /* Increment the system error counter.  */
+        _tx_win32_system_error++;
+    }
+}
+
+
+void    _tx_win32_critical_section_release_all(TX_WIN32_CRITICAL_SECTION    *critical_section)
+{
+
+    /* Ensure the caller is the mutex owner.  */
+    if (critical_section -> tx_win32_critical_section_owner == GetCurrentThreadId())
+    {
+    
+        /* Determine if there is protection.  */
+        if (critical_section -> tx_win32_critical_section_nested_count)
+        {
+    
+            /* Clear the nesting counter.  */
+            critical_section -> tx_win32_critical_section_nested_count =  0;
+    
+            /* Yes, it is being release clear the owner.  */
+            critical_section -> tx_win32_critical_section_owner =  0;
+
+            /* Finally, release the mutex.  */
+            if (ReleaseMutex(critical_section -> tx_win32_critical_section_mutex_handle) != TX_TRUE)
+            {
+
+                /* Increment the system error counter.  */
+                _tx_win32_system_error++;
+            }
+            
+            /* Just in case, make sure there the mutex is not owned.  */
+            while (ReleaseMutex(critical_section -> tx_win32_critical_section_mutex_handle) == TX_TRUE)
+            {
+
+                /* Increment the system error counter.  */
+                _tx_win32_system_error++;
+            }
+        }
+    }
+    else
+    {
+    
+        /* Increment the system error counter.  */
+        _tx_win32_system_error++;
+    }
+}
+
diff --git a/ports/win32/vs_2019/src/tx_thread_stack_build.c b/ports/win32/vs_2019/src/tx_thread_stack_build.c
new file mode 100644
index 00000000..649a9066
--- /dev/null
+++ b/ports/win32/vs_2019/src/tx_thread_stack_build.c
@@ -0,0 +1,157 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include 
+
+
+/* Prototype for new thread entry function.  */
+
+DWORD WINAPI _tx_win32_thread_entry(LPVOID p);
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_thread_stack_build                            Win32/Visual      */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function builds a stack frame on the supplied thread's stack.  */
+/*    The stack frame results in a fake interrupt return to the supplied  */
+/*    function pointer.                                                   */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    thread_ptr                            Pointer to thread control blk */
+/*    function_ptr                          Pointer to return function    */
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    CreateThread                          Win32 create thread           */ 
+/*    ResumeThread                          Win32 resume thread           */ 
+/*    SetThreadPriority                     Win32 set thread priority     */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    _tx_thread_create                     Create thread service         */
+/*    _tx_thread_reset                      Reset thread service          */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+{
+
+    /* Create a Win32 thread for the application thread.  */
+    thread_ptr -> tx_thread_win32_thread_handle =
+        CreateThread(NULL, 0, _tx_win32_thread_entry, (LPVOID) thread_ptr, CREATE_SUSPENDED, 
+                        &(thread_ptr -> tx_thread_win32_thread_id));
+
+    /* Check for a good thread create.  */
+    if (!thread_ptr -> tx_thread_win32_thread_handle)
+    {
+
+        /* Display an error message.  */
+        printf("ThreadX Win32 error creating thread!\n");
+        while(1)
+        {
+        }
+    }
+
+    /* Otherwise, we have a good thread create.  Now set the priority to
+       a lower level.  */
+    SetThreadPriority(thread_ptr -> tx_thread_win32_thread_handle, THREAD_PRIORITY_LOWEST);
+
+    /* Create the run semaphore for the thread.  This will allow the scheduler
+       control over when the thread actually runs.  */
+    thread_ptr -> tx_thread_win32_thread_run_semaphore =  CreateSemaphore(NULL, 0, 1, NULL);
+
+    /* Determine if the run semaphore was created successfully.  */
+    if (!thread_ptr -> tx_thread_win32_thread_run_semaphore)
+    {
+
+        /* Display an error message.  */
+        printf("ThreadX Win32 error creating thread running semaphore!\n");
+        while(1)
+        {
+        }
+    }
+
+    /* Setup the thread suspension type to solicited thread suspension.  
+       Pseudo interrupt handlers will suspend with this field set to 1.  */
+    thread_ptr -> tx_thread_win32_suspension_type =  0;
+
+    /* Clear the disabled count that will keep track of the 
+       tx_interrupt_control nesting.  */
+    thread_ptr -> tx_thread_win32_int_disabled_flag =  0;
+
+    /* Setup a fake thread stack pointer.   */
+    thread_ptr -> tx_thread_stack_ptr =  (VOID *) (((CHAR *) thread_ptr -> tx_thread_stack_end) - 8);
+
+    /* Clear the first word of the stack.  */
+    *(((ULONG *) thread_ptr -> tx_thread_stack_ptr) - 1) =  0;
+
+    /* Make the thread initially ready so it will run to the initial wait on
+       its run semaphore.  */
+    ResumeThread(thread_ptr -> tx_thread_win32_thread_handle);
+}
+
+
+DWORD WINAPI _tx_win32_thread_entry(LPVOID ptr)
+{
+
+TX_THREAD  *thread_ptr;
+
+    /* Pickup the current thread pointer.  */
+    thread_ptr =  (TX_THREAD *) ptr;
+
+    /* Now suspend the thread initially.  If the thread has already
+       been scheduled, this will return immediately.  */
+    WaitForSingleObject(thread_ptr -> tx_thread_win32_thread_run_semaphore, INFINITE);
+
+    /* Call ThreadX thread entry point.  */
+    _tx_thread_shell_entry();
+
+    return EXIT_SUCCESS;
+}
+
diff --git a/ports/win32/vs_2019/src/tx_thread_system_return.c b/ports/win32/vs_2019/src/tx_thread_system_return.c
new file mode 100644
index 00000000..921ce850
--- /dev/null
+++ b/ports/win32/vs_2019/src/tx_thread_system_return.c
@@ -0,0 +1,212 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Thread                                                              */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define    TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_thread.h"
+#include "tx_timer.h"
+#include 
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_thread_system_return                          Win32/Visual      */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function is target processor specific.  It is used to transfer */ 
+/*    control from a thread back to the system.  Only a minimal context   */ 
+/*    is saved since the compiler assumes temp registers are going to get */ 
+/*    slicked by a function call anyway.                                  */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    _tx_win32_critical_section_obtain     Obtain critical section       */ 
+/*    _tx_win32_critical_section_release    Release critical section      */ 
+/*    _tx_win32_critical_section_release_all                              */ 
+/*                                          Release critical section      */ 
+/*    ExitThread                            Win32 thread exit             */ 
+/*    GetCurrentThread                      Win32 get current thread      */ 
+/*    GetCurrentThreadId                    Win32 get current thread ID   */ 
+/*    GetThreadPriority                     Win32 get thread priority     */ 
+/*    ReleaseSemaphore                      Win32 release semaphore       */ 
+/*    WaitForSingleObject                   Win32 wait on semaphore       */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    ThreadX components                                                  */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_thread_system_return(VOID)
+{
+
+TX_THREAD   *temp_thread_ptr;
+HANDLE      temp_run_semaphore;
+UINT        temp_thread_state;
+HANDLE      threadhandle;
+int         threadpriority; 
+DWORD       threadid;
+
+
+    /* Enter Win32 critical section.  */
+    _tx_win32_critical_section_obtain(&_tx_win32_critical_section);
+
+    /* Pickup the handle of the current thread.  */
+    threadhandle =  GetCurrentThread();
+
+    /* Debug entry.  */
+    _tx_win32_debug_entry_insert("SYSTEM_RETURN", __FILE__, __LINE__);
+
+    /* First, determine if the thread was terminated.  */
+
+    /* Pickup the priority of the current thread.  */
+    threadpriority =  GetThreadPriority(threadhandle); 
+
+    /* Pickup the ID of the current thread.  */
+    threadid =  GetCurrentThreadId();
+
+    /* Pickup the current thread pointer.  */
+    temp_thread_ptr =  _tx_thread_current_ptr;
+
+    /* Determine if this is a thread (THREAD_PRIORITY_LOWEST) and it does not 
+       match the current thread pointer.  */
+    if ((threadpriority == THREAD_PRIORITY_LOWEST) && 
+        ((!temp_thread_ptr) || (temp_thread_ptr -> tx_thread_win32_thread_id != threadid))) 
+    { 
+
+        /* This indicates the Win32 thread was actually terminated by ThreadX and is only 
+           being allowed to run in order to cleanup its resources.  */
+        
+        /* Release critical section.  */
+        _tx_win32_critical_section_release_all(&_tx_win32_critical_section);
+        
+        /* Exit thread.  */
+        ExitThread(0); 
+    } 
+
+    /* Determine if the time-slice is active.  */
+    if (_tx_timer_time_slice)
+    {
+
+        /* Preserve current remaining time-slice for the thread and clear the current time-slice.  */
+        temp_thread_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+        _tx_timer_time_slice =  0;
+    }
+
+    /* Save the run semaphore into a temporary variable as well.  */
+    temp_run_semaphore =  temp_thread_ptr -> tx_thread_win32_thread_run_semaphore;
+
+    /* Pickup the current thread state.  */
+    temp_thread_state =  temp_thread_ptr -> tx_thread_state;
+
+    /* Setup the suspension type for this thread.  */
+    temp_thread_ptr -> tx_thread_win32_suspension_type  =  0;
+
+    /* Set the current thread pointer to NULL.  */
+    _tx_thread_current_ptr =  TX_NULL;
+
+    /* Debug entry.  */
+    _tx_win32_debug_entry_insert("SYSTEM_RETURN-release_sem", __FILE__, __LINE__);
+
+    /* Release the semaphore that the main scheduling thread is waiting
+       on.  Note that the main scheduling algorithm will take care of
+       setting the current thread pointer to NULL.  */
+    ReleaseSemaphore(_tx_win32_scheduler_semaphore, 1, NULL);
+
+    /* Leave Win32 critical section.  */
+    _tx_win32_critical_section_release_all(&_tx_win32_critical_section);
+
+    /* Determine if the thread was self-terminating.  */
+    if (temp_thread_state ==  TX_TERMINATED)
+    {
+
+        /* Exit the thread instead of waiting on the semaphore!  */
+        ExitThread(0);
+    }
+
+    /* Wait on the run semaphore for this thread.  This won't get set again
+       until the thread is scheduled.  */
+    WaitForSingleObject(temp_run_semaphore, INFINITE);
+
+    /* Enter Win32 critical section.  */
+    _tx_win32_critical_section_obtain(&_tx_win32_critical_section);
+
+    /* Debug entry.  */
+    _tx_win32_debug_entry_insert("SYSTEM_RETURN-wake_up", __FILE__, __LINE__);
+
+    /* Determine if the thread was terminated.  */
+
+    /* Pickup the current thread pointer.  */
+    temp_thread_ptr =  _tx_thread_current_ptr;
+
+    /* Determine if this is a thread (THREAD_PRIORITY_LOWEST) and it does not 
+       match the current thread pointer.  */
+    if ((threadpriority == THREAD_PRIORITY_LOWEST) && 
+        ((!temp_thread_ptr) || (temp_thread_ptr -> tx_thread_win32_thread_id != threadid))) 
+    { 
+
+        /* Leave Win32 critical section.  */
+        _tx_win32_critical_section_release_all(&_tx_win32_critical_section);
+
+        /* This indicates the Win32 thread was actually terminated by ThreadX and is only 
+           being allowed to run in order to cleanup its resources.  */
+        ExitThread(0); 
+    } 
+
+    /* Now determine if the application thread last had interrupts disabled.  */
+
+    /* Debug entry.  */
+    _tx_win32_debug_entry_insert("SYSTEM_RETURN-finish", __FILE__, __LINE__);
+
+    /* Determine if this thread had interrupts disabled.  */
+    if (!_tx_thread_current_ptr -> tx_thread_win32_int_disabled_flag)
+    {
+
+        /* Leave Win32 critical section.  */
+        _tx_win32_critical_section_release(&_tx_win32_critical_section);
+    }
+}
+
diff --git a/ports/win32/vs_2019/src/tx_timer_interrupt.c b/ports/win32/vs_2019/src/tx_timer_interrupt.c
new file mode 100644
index 00000000..83edfa34
--- /dev/null
+++ b/ports/win32/vs_2019/src/tx_timer_interrupt.c
@@ -0,0 +1,153 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   Timer                                                               */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_timer.h"
+#include "tx_thread.h"
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  FUNCTION                                               RELEASE        */ 
+/*                                                                        */ 
+/*    _tx_timer_interrupt                               Win32/Visual      */ 
+/*                                                           6.0.1        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This function processes the hardware timer interrupt.  This         */ 
+/*    processing includes incrementing the system clock and checking for  */ 
+/*    time slice and/or timer expiration.  If either is found, the        */ 
+/*    interrupt context save/restore functions are called along with the  */ 
+/*    expiration functions.                                               */ 
+/*                                                                        */ 
+/*  INPUT                                                                 */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  OUTPUT                                                                */ 
+/*                                                                        */ 
+/*    None                                                                */ 
+/*                                                                        */ 
+/*  CALLS                                                                 */ 
+/*                                                                        */ 
+/*    _tx_thread_time_slice                 Time slice interrupted thread */ 
+/*    _tx_timer_expiration_process          Timer expiration processing   */ 
+/*    _tx_win32_critical_section_obtain     Obtain critical section       */ 
+/*    _tx_win32_critical_section_release    Release critical section      */ 
+/*                                                                        */ 
+/*  CALLED BY                                                             */ 
+/*                                                                        */ 
+/*    interrupt vector                                                    */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+VOID   _tx_timer_interrupt(VOID)
+{
+
+
+    /* Enter critical section to ensure other threads are not playing with
+       the core ThreadX data structures.  */
+    _tx_win32_critical_section_obtain(&_tx_win32_critical_section);
+
+    /* Debug entry.  */
+    _tx_win32_debug_entry_insert("TIMER INTERRUPT", __FILE__, __LINE__);
+
+    /* Increment the system clock.  */
+    _tx_timer_system_clock++;
+
+    /* Test for time-slice expiration.  */
+    if (_tx_timer_time_slice)
+    {
+
+        /* Decrement the time_slice.  */
+        _tx_timer_time_slice--;
+
+        /* Check for expiration.  */
+        if (_tx_timer_time_slice == 0)
+        {
+
+           /* Set the time-slice expired flag.  */
+           _tx_timer_expired_time_slice =  TX_TRUE;
+        }
+    }
+
+    /* Test for timer expiration.  */
+    if (*_tx_timer_current_ptr)
+    {
+
+        /* Set expiration flag.  */
+        _tx_timer_expired =  TX_TRUE;
+    }
+    else
+    {
+
+        /* No timer expired, increment the timer pointer.  */
+        _tx_timer_current_ptr++;
+
+        /* Check for wrap-around.  */
+        if (_tx_timer_current_ptr == _tx_timer_list_end)
+        {
+
+            /* Wrap to beginning of list.  */
+            _tx_timer_current_ptr =  _tx_timer_list_start;
+        }
+    }
+
+    /* See if anything has expired.  */
+    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+    {
+
+        /* Did a timer expire?  */
+        if (_tx_timer_expired)
+        {
+
+            /* Process timer expiration.  */
+            _tx_timer_expiration_process();
+        }
+
+        /* Did time slice expire?  */
+        if (_tx_timer_expired_time_slice)
+        {
+
+            /* Time slice interrupted thread.  */
+            _tx_thread_time_slice();
+        }
+    }
+
+    /* Exit Win32 critical section.  */
+    _tx_win32_critical_section_release(&_tx_win32_critical_section);
+}
+

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diff --git a/ports/cortex_r4/gnu/example_build/libgcc.a b/ports/cortex_r4/gnu/example_build/libgcc.a
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zgUN}ig(+#y5)3b?iCZj=q+Vk&3ZG^)8`a0Chv`Q~q0f#mvk~sx%t$_r0!jKY=>B3R
zLfFZv+m{D$k^_8Xf|5Wq0UnHj*9a+rO8{H+?LalME`JSD%d4Pm&Yt-iIVA?Cl&&^%q;4GpnIs9NX?
zCCU~3X$}+<3TBj+m4&CfqGZ5v*RKyi+B!C-z87@>XLXn1H+a|RU=EJb9W>29+a>6y
zK=S0^=MRrR`wu&H>1w$MCuEwhc7N^+##i{i_GIQF92#mSXMe334X=&NXn2SCXEa!1
z`OD2|4s9B0R)~DIqa8gf+v-*&+LKxfQ8_*HudrbeDnH!($lu-cXahbD6u3d+Pd<(?
ze#bbvq4T3d@v&RmG)zanZ_^{r#toex{Ws!yM_Fh2zKj6>Q#61_=njO9!Ht5ytjSjv-2aCcO!l_4P~U_p&6t{oQ>mN7k+treC5;6
z55!X*uaQjyucA8MIC{j{xIWPIa}Gi`4}2qSBxrj1yGIb9T`3x3xcTM7h=qs_VN)By
zH^~w}D|+bs@;2~2GYlX3&G2g?-$dp3or21)ye>#K?ELb5G}3sJME~1-eL)9>|1IX1
zyyk;0u~c5dm1R37av%P?23us%dHPGDpFT$0GBczAKYnN6rVuiJ<@W-;X3iNSdGtC4
zZc0Al4tY)&I-P!o0#6|ykg|z--55Au=wiVt!DWKHH_4BuyvA0+F2RcgFA>}#_#GlT
dhn|!HpOEmEh$!@SiRZoRqCc?z|Ecwv{|7^Je?
+#include 
+
+
+/* Define ThreadX basic types for this port.  */ 
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */ 
+#endif
+
+
+/* Define various constants for the ThreadX ARM port.  */ 
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_INT_DISABLE                          0xC0        /* Disable IRQ & FIQ interrupts     */
+#else
+#define TX_INT_DISABLE                          0x80        /* Disable IRQ interrupts           */
+#endif
+#define TX_INT_ENABLE                           0x00        /* Enable IRQ interrupts            */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ++_tx_trace_simulated_time
+#endif
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_FIQ_ENABLED                          1
+#else
+#define TX_FIQ_ENABLED                          0
+#endif
+
+#ifdef TX_ENABLE_IRQ_NESTING
+#define TX_IRQ_NESTING_ENABLED                  2
+#else
+#define TX_IRQ_NESTING_ENABLED                  0
+#endif
+
+#ifdef TX_ENABLE_FIQ_NESTING
+#define TX_FIQ_NESTING_ENABLED                  4
+#else
+#define TX_FIQ_NESTING_ENABLED                  0
+#endif
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#define TX_INLINE_INITIALIZATION
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#define TX_THREAD_EXTENSION_2          
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+   
+#if __TARGET_ARCH_ARM > 4
+
+#ifndef __thumb__
+
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       m = m & ((ULONG) (-((LONG) m))); \
+                                                asm volatile (" CLZ  %0,%1 ": "=r" (b) : "r" (m) ); \
+                                                b = 31 - b; 
+#endif
+#endif
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifdef __thumb__
+
+unsigned int   _tx_thread_interrupt_disable(void);
+unsigned int   _tx_thread_interrupt_restore(UINT old_posture);
+
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int interrupt_save;
+
+#define TX_DISABLE                              interrupt_save =  _tx_thread_interrupt_disable();
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+
+#else
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int interrupt_save, tx_temp;
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_DISABLE                              asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) );
+#else
+#define TX_DISABLE                              asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) );
+#endif
+
+#define TX_RESTORE                              asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) );
+
+#endif
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Cortex-R4/GNU Version 6.0 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+
+#endif
+
diff --git a/ports/cortex_r4/gnu/readme_threadx.txt b/ports/cortex_r4/gnu/readme_threadx.txt
new file mode 100644
index 00000000..c89d5940
--- /dev/null
+++ b/ports/cortex_r4/gnu/readme_threadx.txt
@@ -0,0 +1,496 @@
+                     Microsoft's Azure RTOS ThreadX for Cortex-R4 
+
+                              Using the GNU Tools
+
+1.  Building the ThreadX run-time Library
+
+First make sure you are in the "example_build" directory. Also, make sure that 
+you have setup your path and other environment variables necessary for the GNU 
+development environment. 
+
+At this point you may run the build_threadx.bat batch file. This will build the 
+ThreadX run-time environment in the "example_build" directory. 
+
+You should observe assembly and compilation of a series of ThreadX source 
+files. At the end of the batch file, they are all combined into the 
+run-time library file: tx.a. This file must be linked with your 
+application in order to use ThreadX.
+
+
+2.  Demonstration System
+
+Building the demonstration is easy; simply execute the build_threadx_sample.bat 
+batch file while inside the "example_build" directory. 
+
+You should observe the compilation of sample_threadx.c (which is the demonstration 
+application) and linking with TX.A. The resulting file DEMO is a binary file 
+that can be downloaded and executed.
+
+
+3.  System Initialization
+
+The entry point in ThreadX for the Cortex-R4 using GNU tools is at label _start. 
+This is defined within the modified version of the GNU startup code - crt0.S.
+
+The ThreadX tx_initialize_low_level.S file is responsible for setting up various 
+system data structures, the interrupt vectors, and a periodic timer interrupt source. 
+By default, the vector area is defined to be located at the "__vectors" label, 
+which is defined in reset.S. This area is typically located at 0. In situations 
+where this is impossible, the vectors at the "__vectors" label should be copied 
+to address 0.
+
+This is also where initialization of a periodic timer interrupt source should take 
+place.
+
+In addition, _tx_initialize_low_level defines the first available address 
+for use by the application, which is supplied as the sole input parameter 
+to your application definition function, tx_application_define.
+
+
+4.  Assembler / Compiler Switches
+
+The following are compiler switches used in building the demonstration 
+system:
+
+Compiler/Assembler                  Meaning
+    Switches
+
+    -g                      Specifies debug information
+    -c                      Specifies object code generation
+    -mcpu=cortex-r4              Specifies target cpu
+
+Linker Switch                       Meaning
+
+    -o sample_threadx.out     Specifies output file
+    -M > sample_threadx.map   Specifies demo map file
+    -A cortex-r4            Specifies target architecture
+    -T sample_threadx.ld      Specifies the loader control file
+
+Application Defines ( -D option)
+
+    TX_ENABLE_FIQ_SUPPORT                       This assembler define enables FIQ
+                                                interrupt handling support in the
+                                                ThreadX assembly files. If used,
+                                                it should be used on all assembly
+                                                files and the generic C source of
+                                                ThreadX should be compiled with 
+                                                TX_ENABLE_FIQ_SUPPORT defined as well.
+
+    TX_ENABLE_IRQ_NESTING                       This assembler define enables IRQ
+                                                nested support. If IRQ nested 
+                                                interrupt support is needed, this
+                                                define should be applied to 
+                                                tx_initialize_low_level.S.
+
+    TX_ENABLE_FIQ_NESTING                       This assembler define enables FIQ
+                                                nested support. If FIQ nested 
+                                                interrupt support is needed, this
+                                                define should be applied to 
+                                                tx_initialize_low_level.S. In addition,
+                                                IRQ nesting should also be enabled.
+
+    TX_ENABLE_FIQ_SUPPORT                       This compiler define enables FIQ
+                                                interrupt handling in the ThreadX
+                                                generic C source. This define 
+                                                should also be used in conjunction
+                                                with the corresponding assembler
+                                                define.                                               
+
+    TX_DISABLE_ERROR_CHECKING                   If defined before tx_api.h is included,
+                                                this define causes basic ThreadX error
+                                                checking to be disabled. Please see
+                                                Chapter 2 in the "ThreadX User Guide" 
+                                                for more details.
+
+    TX_MAX_PRIORITIES                           Defines the priority levels for ThreadX. 
+                                                Legal values range from 32 through 
+                                                1024 (inclusive) and MUST be evenly divisible 
+                                                by 32. Increasing the number of priority levels 
+                                                supported increases the RAM usage by 128 bytes 
+                                                for every group of 32 priorities. However, there 
+                                                is only a negligible effect on performance. By 
+                                                default, this value is set to 32 priority levels.
+
+    TX_MINIMUM_STACK                            Defines the minimum stack size (in bytes). It is 
+                                                used for error checking when threads are created. 
+                                                The default value is port-specific and is found 
+                                                in tx_port.h.
+
+    TX_TIMER_THREAD_STACK_SIZE                  Defines the stack size (in bytes) of the internal 
+                                                ThreadX timer thread. This thread processes all 
+                                                thread sleep requests as well as all service call 
+                                                timeouts. In addition, all application timer callback 
+                                                routines are invoked from this context. The default 
+                                                value is port-specific and is found in tx_port.h.
+
+    TX_TIMER_THREAD_PRIORITY                    Defines the priority of the internal ThreadX timer 
+                                                thread. The default value is priority 0 - the highest 
+                                                priority in ThreadX. The default value is defined 
+                                                in tx_port.h.
+
+    TX_TIMER_PROCESS_IN_ISR                     Defined, this option eliminates the internal system 
+                                                timer thread for ThreadX. This results in improved 
+                                                performance on timer events and smaller RAM requirements 
+                                                because the timer stack and control block are no 
+                                                longer needed. However, using this option moves all 
+                                                the timer expiration processing to the timer ISR level. 
+                                                By default, this option is not defined.
+
+    TX_REACTIVATE_INLINE                        Defined, this option performs reactivation of ThreadX 
+                                                timers in-line instead of using a function call. This 
+                                                improves performance but slightly increases code size. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_STACK_FILLING                    Defined, placing the 0xEF value in each byte of each 
+                                                thread's stack is disabled. By default, this option is 
+                                                not defined.
+
+    TX_ENABLE_STACK_CHECKING                    Defined, this option enables ThreadX run-time stack checking, 
+                                                which includes analysis of how much stack has been used and 
+                                                examination of data pattern "fences" before and after the 
+                                                stack area. If a stack error is detected, the registered 
+                                                application stack error handler is called. This option does 
+                                                result in slightly increased overhead and code size. Please 
+                                                review the tx_thread_stack_error_notify API for more information. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_PREEMPTION_THRESHOLD             Defined, this option disables the preemption-threshold feature 
+                                                and slightly reduces code size and improves performance. Of course, 
+                                                the preemption-threshold capabilities are no longer available. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_REDUNDANT_CLEARING               Defined, this option removes the logic for initializing ThreadX 
+                                                global C data structures to zero. This should only be used if 
+                                                the compiler's initialization code sets all un-initialized 
+                                                C global data to zero. Using this option slightly reduces 
+                                                code size and improves performance during initialization. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_NOTIFY_CALLBACKS                 Defined, this option disables the notify callbacks for various 
+                                                ThreadX objects. Using this option slightly reduces code size 
+                                                and improves performance.
+
+    TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO       Defined, this option enables the gathering of performance 
+                                                information on block pools. By default, this option is 
+                                                not defined.
+
+    TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO        Defined, this option enables the gathering of performance 
+                                                information on byte pools. By default, this option is 
+                                                not defined.
+
+    TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO      Defined, this option enables the gathering of performance 
+                                                information on event flags groups. By default, this option 
+                                                is not defined.
+
+    TX_MUTEX_ENABLE_PERFORMANCE_INFO            Defined, this option enables the gathering of performance 
+                                                information on mutexes. By default, this option is 
+                                                not defined.
+
+    TX_QUEUE_ENABLE_PERFORMANCE_INFO            Defined, this option enables the gathering of performance 
+                                                information on queues. By default, this option is 
+                                                not defined.
+
+    TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO        Defined, this option enables the gathering of performance 
+                                                information on semaphores. By default, this option is 
+                                                not defined.
+
+    TX_THREAD_ENABLE_PERFORMANCE_INFO           Defined, this option enables the gathering of performance 
+                                                information on threads. By default, this option is 
+                                                not defined.
+
+    TX_TIMER_ENABLE_PERFORMANCE_INFO            Defined, this option enables the gathering of performance 
+                                                information on timers. By default, this option is 
+                                                not defined.
+
+    TX_ENABLE_EVENT_TRACE                       Defined, this option enables the internal ThreadX trace
+                                                feature. The trace buffer is supplied at a later time
+                                                via an application call to tx_trace_enable.
+
+    TX_TRACE_TIME_SOURCE                        This defines the time-stamp source for event tracing. 
+                                                This define is only pertinent if the ThreadX library is 
+                                                built with TX_ENABLE_EVENT_TRACE defined.
+
+    TX_TRACE_TIME_MASK                          This defines the number of valid bits in the event trace 
+                                                time-stamp source defined previously. If the time-stamp 
+                                                source is 16-bits, this value should be 0xFFFF. Alternatively, 
+                                                if the time-stamp source is 32-bits, this value should be 
+                                                0xFFFFFFFF. This define is only pertinent if the ThreadX 
+                                                library is built with TX_ENABLE_EVENT_TRACE defined.
+
+
+5.  Register Usage and Stack Frames
+
+The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch 
+registers for each function. All other registers used by a C function must 
+be preserved by the function. ThreadX takes advantage of this in situations 
+where a context switch happens as a result of making a ThreadX service call 
+(which is itself a C function). In such cases, the saved context of a thread 
+is only the non-scratch registers.
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have one of these two types of stack frames. The top
+of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the 
+associated thread control block TX_THREAD.
+
+
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x00                   1                           0
+     0x04                   CPSR                        CPSR
+     0x08                   r0  (a1)                    r4  (v1)
+     0x0C                   r1  (a2)                    r5  (v2)
+     0x10                   r2  (a3)                    r6  (v3)
+     0x14                   r3  (a4)                    r7  (v4)
+     0x18                   r4  (v1)                    r8  (v5)
+     0x1C                   r5  (v2)                    r9  (v6)
+     0x20                   r6  (v3)                    r10 (v7)
+     0x24                   r7  (v4)                    r11 (fp)
+     0x28                   r8  (v5)                    r14 (lr)
+     0x2C                   r9  (v6)                        
+     0x30                   r10 (v7)                        
+     0x34                   r11 (fp)                        
+     0x38                   r12 (ip)                         
+     0x3C                   r14 (lr)
+     0x40                   PC 
+
+
+6.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+7.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-R4
+targets. There are a certain set of requirements that are defined in the 
+following sub-sections:
+
+
+7.1  Vector Area
+
+The Cortex-R4 vectors start at address zero. The demonstration system startup
+reset.S file contains the vectors and is loaded at address zero. On actual 
+hardware platforms, this area might have to be copied to address 0. 
+
+
+7.2  IRQ ISRs
+
+ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports 
+nested IRQ interrupts. The following sub-sections define the IRQ capabilities.
+
+
+7.2.1 Standard IRQ ISRs
+
+The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ 
+interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following 
+is the default IRQ handler defined in tx_initialize_low_level.S:
+
+    .global __tx_irq_handler
+    .global __tx_irq_processing_return      
+__tx_irq_handler:
+@
+@    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save             @ Jump to the context save
+__tx_irq_processing_return:
+@
+@    /* At this point execution is still in the IRQ mode. The CPSR, point of
+@       interrupt, and all C scratch registers are available for use. Note 
+@       that IRQ interrupts are still disabled upon return from the context
+@       save function.  */
+@
+@    /* Application ISR call(s) go here!  */
+@
+@    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.2.2 Vectored IRQ ISRs
+
+The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified
+by the particular implementation. The following is an example IRQ handler defined in 
+tx_initialize_low_level.S:
+
+    .global __tx_irq_example_handler
+__tx_irq_example_handler:
+@
+@    /* Call context save to save system context.  */
+
+    STMDB   sp!, {r0-r3}                        @ Save some scratch registers
+    MRS     r0, SPSR                            @ Pickup saved SPSR
+    SUB     lr, lr, #4                          @ Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}             @ Store other scratch registers
+    BL      _tx_thread_vectored_context_save    @ Call the vectored IRQ context save
+@
+@    /* At this point execution is still in the IRQ mode. The CPSR, point of
+@       interrupt, and all C scratch registers are available for use. Note 
+@       that IRQ interrupts are still disabled upon return from the context
+@       save function.  */
+@
+@    /* Application ISR call goes here!  */
+@
+@    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.2.3  Nested IRQ Support
+
+By default, nested IRQ interrupt support is not enabled. To enable nested
+IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING
+defined. With this defined, two new IRQ interrupt management services are
+available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end.
+These function should be called between the IRQ context save and restore
+calls. 
+
+Execution between the calls to _tx_thread_irq_nesting_start and 
+_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved 
+by switching from IRQ mode to SYS mode and enabling IRQ interrupts.
+The SYS mode stack is used during the SYS mode operation, which was 
+setup in tx_initialize_low_level.S. When nested IRQ interrupts are no 
+longer required, calling the _tx_thread_irq_nesting_end service disables 
+nesting by disabling IRQ interrupts and switching back to IRQ mode in 
+preparation for the IRQ context restore service.
+
+The following is an example of enabling IRQ nested interrupts in a standard 
+IRQ handler:
+
+    .global __tx_irq_handler
+    .global __tx_irq_processing_return      
+__tx_irq_handler:
+@
+@    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return:
+@
+@    /* Enable nested IRQ interrupts. NOTE:  Since this service returns
+@       with IRQ interrupts enabled, all IRQ interrupt sources must be 
+@       cleared prior to calling this service.  */
+    BL      _tx_thread_irq_nesting_start
+@    
+@    /* Application ISR call(s) go here!  */
+@
+@    /* Disable nested IRQ interrupts. The mode is switched back to
+@       IRQ mode and IRQ interrupts are disable upon return.  */
+    BL      _tx_thread_irq_nesting_end
+@
+@    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.3  FIQ Interrupts
+
+By default, FIQ interrupts are left alone by ThreadX. Of course, this 
+means that the application is fully responsible for enabling the FIQ interrupt 
+and saving/restoring any registers used in the FIQ ISR processing. To globally 
+enable FIQ interrupts, the application should enable FIQ interrupts at the 
+beginning of each thread or before any threads are created in tx_application_define. 
+In addition, the application must ensure that no ThreadX service calls are made 
+from default FIQ ISRs, which is located in tx_initialize_low_level.S.
+
+
+7.3.1  Managed FIQ Interrupts
+
+Full ThreadX management of FIQ interrupts is provided if the ThreadX sources
+are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built
+this way, the FIQ interrupt handlers are very similar to the IRQ interrupt
+handlers defined previously. The following is default FIQ handler 
+defined in tx_initialize_low_level.S:
+
+
+    .global __tx_fiq_handler
+    .global __tx_fiq_processing_return
+__tx_fiq_handler:
+@
+@    /* Jump to fiq context save to save system context.  */
+    B       _tx_thread_fiq_context_save
+__tx_fiq_processing_return:
+@
+@    /* At this point execution is still in the FIQ mode. The CPSR, point of
+@       interrupt, and all C scratch registers are available for use.  */
+@
+@    /* Application FIQ handlers can be called here!  */
+@
+@    /* Jump to fiq context restore to restore system context.  */
+    B       _tx_thread_fiq_context_restore
+
+
+7.3.1.1 Nested FIQ Support
+
+By default, nested FIQ interrupt support is not enabled. To enable nested
+FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING
+defined. With this defined, two new FIQ interrupt management services are
+available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end.
+These function should be called between the FIQ context save and restore
+calls. 
+
+Execution between the calls to _tx_thread_fiq_nesting_start and 
+_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved 
+by switching from FIQ mode to SYS mode and enabling FIQ interrupts.
+The SYS mode stack is used during the SYS mode operation, which was 
+setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required,
+calling the _tx_thread_fiq_nesting_end service disables nesting by disabling
+FIQ interrupts and switching back to FIQ mode in preparation for the FIQ 
+context restore service.
+
+The following is an example of enabling FIQ nested interrupts in the 
+typical FIQ handler:
+
+
+    .global __tx_fiq_handler
+    .global __tx_fiq_processing_return
+__tx_fiq_handler:
+@
+@    /* Jump to fiq context save to save system context.  */
+    B       _tx_thread_fiq_context_save
+__tx_fiq_processing_return:
+@
+@    /* At this point execution is still in the FIQ mode. The CPSR, point of
+@       interrupt, and all C scratch registers are available for use.  */
+@
+@    /* Enable nested FIQ interrupts. NOTE:  Since this service returns
+@       with FIQ interrupts enabled, all FIQ interrupt sources must be 
+@       cleared prior to calling this service.  */
+    BL      _tx_thread_fiq_nesting_start
+@
+@    /* Application FIQ handlers can be called here!  */
+@
+@    /* Disable nested FIQ interrupts. The mode is switched back to
+@       FIQ mode and FIQ interrupts are disable upon return.  */
+    BL      _tx_thread_fiq_nesting_end
+@
+@    /* Jump to fiq context restore to restore system context.  */
+    B       _tx_thread_fiq_context_restore
+
+
+8.  ThreadX Timer Interrupt
+
+ThreadX requires a periodic interrupt source to manage all time-slicing, 
+thread sleeps, timeouts, and application timers. Without such a timer 
+interrupt source, these services are not functional but the remainder of 
+ThreadX will still run.
+
+To add the timer interrupt processing, simply make a call to 
+_tx_timer_interrupt in the IRQ processing. An example of this can be
+found in the file tx_initialize_low_level.S for the demonstration system.
+
+
+9.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX 6.0.1 version for Cortex-R4 using GNU tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_context_restore.S b/ports/cortex_r4/gnu/src/tx_thread_context_restore.S
new file mode 100644
index 00000000..8f37269c
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_context_restore.S
@@ -0,0 +1,256 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@#include "tx_timer.h"
+@
+    .arm
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+SVC_MODE        =     0xD3               @ Disable IRQ/FIQ, SVC mode
+IRQ_MODE        =     0xD2               @ Disable IRQ/FIQ, IRQ mode
+#else
+SVC_MODE        =     0x93               @ Disable IRQ, SVC mode
+IRQ_MODE        =     0x92               @ Disable IRQ, IRQ mode
+#endif
+@
+    .global     _tx_thread_system_state
+    .global     _tx_thread_current_ptr
+    .global     _tx_thread_execute_ptr
+    .global     _tx_timer_time_slice
+    .global     _tx_thread_schedule
+    .global     _tx_thread_preempt_disable
+    .global     _tx_execution_isr_exit
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore
+@   since it will never be called 16-bit mode.  */
+@ 
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_context_restore                        Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function restores the interrupt context if it is processing a  */ 
+@/*    nested interrupt.  If not, it returns to the interrupt thread if no */ 
+@/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+@/*    if no thread was running, the function returns to the scheduler.    */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    _tx_thread_schedule                   Thread scheduling routine     */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                  Interrupt Service Routines    */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_context_restore(VOID)
+@{
+    .global _tx_thread_context_restore
+    .type   _tx_thread_context_restore,function
+_tx_thread_context_restore:
+@
+@    /* Lockout interrupts.  */
+@
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                              @ Disable IRQ and FIQ interrupts
+#else
+    CPSID   i                               @ Disable IRQ interrupts
+#endif
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR exit function to indicate an ISR is complete.  */
+@
+    BL      _tx_execution_isr_exit          @ Call the ISR exit function
+#endif
+@
+@    /* Determine if interrupts are nested.  */
+@    if (--_tx_thread_system_state)
+@    {
+@
+    LDR     r3, =_tx_thread_system_state    @ Pickup address of system state variable
+    LDR     r2, [r3]                        @ Pickup system state
+    SUB     r2, r2, #1                      @ Decrement the counter
+    STR     r2, [r3]                        @ Store the counter 
+    CMP     r2, #0                          @ Was this the first interrupt?
+    BEQ     __tx_thread_not_nested_restore  @ If so, not a nested restore
+@
+@    /* Interrupts are nested.  */
+@
+@    /* Just recover the saved registers and return to the point of 
+@       interrupt.  */
+@
+    LDMIA   sp!, {r0, r10, r12, lr}         @ Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                   @ Put SPSR back
+    LDMIA   sp!, {r0-r3}                    @ Recover r0-r3
+    MOVS    pc, lr                          @ Return to point of interrupt
+@
+@    }
+__tx_thread_not_nested_restore:
+@
+@    /* Determine if a thread was interrupted and no preemption is required.  */
+@    else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) 
+@               || (_tx_thread_preempt_disable))
+@    {
+@
+    LDR     r1, =_tx_thread_current_ptr     @ Pickup address of current thread ptr
+    LDR     r0, [r1]                        @ Pickup actual current thread pointer
+    CMP     r0, #0                          @ Is it NULL?
+    BEQ     __tx_thread_idle_system_restore @ Yes, idle system was interrupted
+@
+    LDR     r3, =_tx_thread_preempt_disable @ Pickup preempt disable address
+    LDR     r2, [r3]                        @ Pickup actual preempt disable flag
+    CMP     r2, #0                          @ Is it set?
+    BNE     __tx_thread_no_preempt_restore  @ Yes, don't preempt this thread
+    LDR     r3, =_tx_thread_execute_ptr     @ Pickup address of execute thread ptr
+    LDR     r2, [r3]                        @ Pickup actual execute thread pointer
+    CMP     r0, r2                          @ Is the same thread highest priority?
+    BNE     __tx_thread_preempt_restore     @ No, preemption needs to happen
+@
+@
+__tx_thread_no_preempt_restore:
+@
+@    /* Restore interrupted thread or ISR.  */
+@
+@    /* Pickup the saved stack pointer.  */
+@    tmp_ptr =  _tx_thread_current_ptr -> tx_thread_stack_ptr;
+@
+@   /* Recover the saved context and return to the point of interrupt.  */
+@
+    LDMIA   sp!, {r0, r10, r12, lr}         @ Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                   @ Put SPSR back
+    LDMIA   sp!, {r0-r3}                    @ Recover r0-r3
+    MOVS    pc, lr                          @ Return to point of interrupt
+@
+@    }
+@    else
+@    {
+__tx_thread_preempt_restore:
+@
+    LDMIA   sp!, {r3, r10, r12, lr}         @ Recover temporarily saved registers
+    MOV     r1, lr                          @ Save lr (point of interrupt)
+    MOV     r2, #SVC_MODE                   @ Build SVC mode CPSR
+    MSR     CPSR_c, r2                      @ Enter SVC mode
+    STR     r1, [sp, #-4]!                  @ Save point of interrupt
+    STMDB   sp!, {r4-r12, lr}               @ Save upper half of registers
+    MOV     r4, r3                          @ Save SPSR in r4
+    MOV     r2, #IRQ_MODE                   @ Build IRQ mode CPSR
+    MSR     CPSR_c, r2                      @ Enter IRQ mode
+    LDMIA   sp!, {r0-r3}                    @ Recover r0-r3
+    MOV     r5, #SVC_MODE                   @ Build SVC mode CPSR
+    MSR     CPSR_c, r5                      @ Enter SVC mode
+    STMDB   sp!, {r0-r3}                    @ Save r0-r3 on thread's stack
+@
+    LDR     r1, =_tx_thread_current_ptr     @ Pickup address of current thread ptr
+    LDR     r0, [r1]                        @ Pickup current thread pointer
+@
+#ifdef TX_ENABLE_VFP_SUPPORT
+    LDR     r2, [r0, #144]                  @ Pickup the VFP enabled flag
+    CMP     r2, #0                          @ Is the VFP enabled?
+    BEQ     _tx_skip_irq_vfp_save           @ No, skip VFP IRQ save
+    VMRS    r2, FPSCR                       @ Pickup the FPSCR
+    STR     r2, [sp, #-4]!                  @ Save FPSCR
+    VSTMDB  sp!, {D0-D15}                   @ Save D0-D15
+_tx_skip_irq_vfp_save:
+#endif
+@
+    MOV     r3, #1                          @ Build interrupt stack type
+    STMDB   sp!, {r3, r4}                   @ Save interrupt stack type and SPSR
+    STR     sp, [r0, #8]                    @ Save stack pointer in thread control
+                                            @   block
+@
+@    /* Save the remaining time-slice and disable it.  */
+@    if (_tx_timer_time_slice)
+@    {
+@
+    LDR     r3, =_tx_timer_time_slice       @ Pickup time-slice variable address
+    LDR     r2, [r3]                        @ Pickup time-slice
+    CMP     r2, #0                          @ Is it active?
+    BEQ     __tx_thread_dont_save_ts        @ No, don't save it
+@
+@        _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+@        _tx_timer_time_slice =  0;
+@
+    STR     r2, [r0, #24]                   @ Save thread's time-slice
+    MOV     r2, #0                          @ Clear value
+    STR     r2, [r3]                        @ Disable global time-slice flag
+@
+@    }
+__tx_thread_dont_save_ts:
+@
+@
+@    /* Clear the current task pointer.  */
+@    _tx_thread_current_ptr =  TX_NULL;
+@
+    MOV     r0, #0                          @ NULL value
+    STR     r0, [r1]                        @ Clear current thread pointer
+@
+@    /* Return to the scheduler.  */
+@    _tx_thread_schedule();
+@
+    B       _tx_thread_schedule             @ Return to scheduler
+@    }
+@
+__tx_thread_idle_system_restore:
+@
+@    /* Just return back to the scheduler!  */
+@
+    MOV     r0, #SVC_MODE                   @ Build SVC mode CPSR
+    MSR     CPSR_c, r0                      @ Enter SVC mode
+    B       _tx_thread_schedule             @ Return to scheduler
+@}
+
+
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_context_save.S b/ports/cortex_r4/gnu/src/tx_thread_context_save.S
new file mode 100644
index 00000000..52447586
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_context_save.S
@@ -0,0 +1,203 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@#include "tx_timer.h"
+@
+@
+    .global     _tx_thread_system_state
+    .global     _tx_thread_current_ptr
+    .global     _tx_irq_processing_return
+    .global     _tx_execution_isr_enter
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save
+@   since it will never be called 16-bit mode.  */
+@ 
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_context_save                           Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function saves the context of an executing thread in the       */ 
+@/*    beginning of interrupt processing.  The function also ensures that  */ 
+@/*    the system stack is used upon return to the calling ISR.            */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                                                */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_context_save(VOID)
+@{
+    .global _tx_thread_context_save
+    .type   _tx_thread_context_save,function
+_tx_thread_context_save:
+@
+@    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+@       out, we are in IRQ mode, and all registers are intact.  */
+@
+@    /* Check for a nested interrupt condition.  */
+@    if (_tx_thread_system_state++)
+@    {
+@
+    STMDB   sp!, {r0-r3}                    @ Save some working registers 
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                              @ Disable FIQ interrupts
+#endif
+    LDR     r3, =_tx_thread_system_state    @ Pickup address of system state variable
+    LDR     r2, [r3]                        @ Pickup system state
+    CMP     r2, #0                          @ Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save     @ Yes, not a nested context save
+@
+@    /* Nested interrupt condition.  */
+@
+    ADD     r2, r2, #1                      @ Increment the interrupt counter
+    STR     r2, [r3]                        @ Store it back in the variable
+@
+@   /* Save the rest of the scratch registers on the stack and return to the
+@      calling ISR.  */
+@
+    MRS     r0, SPSR                        @ Pickup saved SPSR
+    SUB     lr, lr, #4                      @ Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}         @ Store other registers
+@
+@    /* Return to the ISR.  */
+@
+    MOV     r10, #0                         @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                            @ Save ISR lr
+    BL      _tx_execution_isr_enter         @ Call the ISR enter function
+    POP     {lr}                            @ Recover ISR lr
+#endif
+
+    B       __tx_irq_processing_return      @ Continue IRQ processing 
+@
+__tx_thread_not_nested_save:
+@    }
+@
+@    /* Otherwise, not nested, check to see if a thread was running.  */
+@    else if (_tx_thread_current_ptr)
+@    {
+@
+    ADD     r2, r2, #1                      @ Increment the interrupt counter
+    STR     r2, [r3]                        @ Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr     @ Pickup address of current thread ptr
+    LDR     r0, [r1]                        @ Pickup current thread pointer
+    CMP     r0, #0                          @ Is it NULL?
+    BEQ     __tx_thread_idle_system_save    @ If so, interrupt occurred in 
+                                            @   scheduling loop - nothing needs saving!
+@
+@    /* Save minimal context of interrupted thread.  */
+@
+    MRS     r2, SPSR                        @ Pickup saved SPSR
+    SUB     lr, lr, #4                      @ Adjust point of interrupt 
+    STMDB   sp!, {r2, r10, r12, lr}         @ Store other registers
+@
+@    /* Save the current stack pointer in the thread's control block.  */
+@    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+@
+@    /* Switch to the system stack.  */
+@    sp =  _tx_thread_system_stack_ptr@
+@
+    MOV     r10, #0                         @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                            @ Save ISR lr
+    BL      _tx_execution_isr_enter         @ Call the ISR enter function
+    POP     {lr}                            @ Recover ISR lr
+#endif
+
+    B       __tx_irq_processing_return      @ Continue IRQ processing 
+@
+@    }
+@    else
+@    {
+@
+__tx_thread_idle_system_save:
+@
+@    /* Interrupt occurred in the scheduling loop.  */
+@
+@    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+@       processing.  */
+@
+    MOV     r10, #0                         @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                            @ Save ISR lr
+    BL      _tx_execution_isr_enter         @ Call the ISR enter function
+    POP     {lr}                            @ Recover ISR lr
+#endif
+
+    ADD     sp, sp, #16                     @ Recover saved registers
+    B       __tx_irq_processing_return      @ Continue IRQ processing  
+@
+@    }
+@}
+
+
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S
new file mode 100644
index 00000000..5437c7af
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_restore.S
@@ -0,0 +1,247 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@#include "tx_timer.h"
+@
+@
+SVC_MODE        =       0xD3                    @ SVC mode
+FIQ_MODE        =       0xD1                    @ FIQ mode
+MODE_MASK       =       0x1F                    @ Mode mask 
+THUMB_MASK      =       0x20                    @ Thumb bit mask
+IRQ_MODE_BITS   =       0x12                    @ IRQ mode bits
+@
+@
+    .global     _tx_thread_system_state
+    .global     _tx_thread_current_ptr
+    .global     _tx_thread_system_stack_ptr
+    .global     _tx_thread_execute_ptr
+    .global     _tx_timer_time_slice
+    .global     _tx_thread_schedule
+    .global     _tx_thread_preempt_disable
+    .global     _tx_execution_isr_exit
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore
+@   since it will never be called 16-bit mode.  */
+@
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_fiq_context_restore                    Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function restores the fiq interrupt context when processing a  */ 
+@/*    nested interrupt.  If not, it returns to the interrupt thread if no */ 
+@/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+@/*    if no thread was running, the function returns to the scheduler.    */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    _tx_thread_schedule                   Thread scheduling routine     */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    FIQ ISR                               Interrupt Service Routines    */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_fiq_context_restore(VOID)
+@{
+    .global  _tx_thread_fiq_context_restore
+    .type    _tx_thread_fiq_context_restore,function
+_tx_thread_fiq_context_restore:
+@
+@    /* Lockout interrupts.  */
+@
+    CPSID   if                                  @ Disable IRQ and FIQ interrupts
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR exit function to indicate an ISR is complete.  */
+@
+    BL      _tx_execution_isr_exit              @ Call the ISR exit function
+#endif
+@
+@    /* Determine if interrupts are nested.  */
+@    if (--_tx_thread_system_state)
+@    {
+@
+    LDR     r3, =_tx_thread_system_state        @ Pickup address of system state variable
+    LDR     r2, [r3]                            @ Pickup system state
+    SUB     r2, r2, #1                          @ Decrement the counter
+    STR     r2, [r3]                            @ Store the counter 
+    CMP     r2, #0                              @ Was this the first interrupt?
+    BEQ     __tx_thread_fiq_not_nested_restore  @ If so, not a nested restore
+@
+@    /* Interrupts are nested.  */
+@
+@    /* Just recover the saved registers and return to the point of 
+@       interrupt.  */
+@
+    LDMIA   sp!, {r0, r10, r12, lr}             @ Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       @ Put SPSR back
+    LDMIA   sp!, {r0-r3}                        @ Recover r0-r3
+    MOVS    pc, lr                              @ Return to point of interrupt
+@
+@    }
+__tx_thread_fiq_not_nested_restore:
+@
+@    /* Determine if a thread was interrupted and no preemption is required.  */
+@    else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) 
+@               || (_tx_thread_preempt_disable))
+@    {
+@
+    LDR     r1, [sp]                            @ Pickup the saved SPSR
+    MOV     r2, #MODE_MASK                      @ Build mask to isolate the interrupted mode
+    AND     r1, r1, r2                          @ Isolate mode bits
+    CMP     r1, #IRQ_MODE_BITS                  @ Was an interrupt taken in IRQ mode before we
+                                                @   got to context save? */
+    BEQ     __tx_thread_fiq_no_preempt_restore  @ Yes, just go back to point of interrupt
+
+
+    LDR     r1, =_tx_thread_current_ptr         @ Pickup address of current thread ptr
+    LDR     r0, [r1]                            @ Pickup actual current thread pointer
+    CMP     r0, #0                              @ Is it NULL?
+    BEQ     __tx_thread_fiq_idle_system_restore @ Yes, idle system was interrupted
+
+    LDR     r3, =_tx_thread_preempt_disable     @ Pickup preempt disable address
+    LDR     r2, [r3]                            @ Pickup actual preempt disable flag
+    CMP     r2, #0                              @ Is it set?
+    BNE     __tx_thread_fiq_no_preempt_restore  @ Yes, don't preempt this thread
+    LDR     r3, =_tx_thread_execute_ptr         @ Pickup address of execute thread ptr
+    LDR     r2, [r3]                            @ Pickup actual execute thread pointer
+    CMP     r0, r2                              @ Is the same thread highest priority?
+    BNE     __tx_thread_fiq_preempt_restore     @ No, preemption needs to happen
+
+
+__tx_thread_fiq_no_preempt_restore:
+@
+@    /* Restore interrupted thread or ISR.  */
+@
+@    /* Pickup the saved stack pointer.  */
+@    tmp_ptr =  _tx_thread_current_ptr -> tx_thread_stack_ptr;
+@
+@    /* Recover the saved context and return to the point of interrupt.  */
+@
+    LDMIA   sp!, {r0, lr}                       @ Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       @ Put SPSR back
+    LDMIA   sp!, {r0-r3}                        @ Recover r0-r3
+    MOVS    pc, lr                              @ Return to point of interrupt
+@
+@    }
+@    else
+@    {
+__tx_thread_fiq_preempt_restore:
+@
+    LDMIA   sp!, {r3, lr}                       @ Recover temporarily saved registers
+    MOV     r1, lr                              @ Save lr (point of interrupt)
+    MOV     r2, #SVC_MODE                       @ Build SVC mode CPSR
+    MSR     CPSR_c, r2                          @ Enter SVC mode
+    STR     r1, [sp, #-4]!                      @ Save point of interrupt
+    STMDB   sp!, {r4-r12, lr}                   @ Save upper half of registers
+    MOV     r4, r3                              @ Save SPSR in r4
+    MOV     r2, #FIQ_MODE                       @ Build FIQ mode CPSR
+    MSR     CPSR_c, r2                          @ Reenter FIQ mode
+    LDMIA   sp!, {r0-r3}                        @ Recover r0-r3
+    MOV     r5, #SVC_MODE                       @ Build SVC mode CPSR
+    MSR     CPSR_c, r5                          @ Enter SVC mode
+    STMDB   sp!, {r0-r3}                        @ Save r0-r3 on thread's stack
+    MOV     r3, #1                              @ Build interrupt stack type
+    STMDB   sp!, {r3, r4}                       @ Save interrupt stack type and SPSR
+    LDR     r1, =_tx_thread_current_ptr         @ Pickup address of current thread ptr
+    LDR     r0, [r1]                            @ Pickup current thread pointer
+    STR     sp, [r0, #8]                        @ Save stack pointer in thread control
+                                                @   block  */
+@
+@    /* Save the remaining time-slice and disable it.  */
+@    if (_tx_timer_time_slice)
+@    {
+@
+    LDR     r3, =_tx_timer_time_slice           @ Pickup time-slice variable address
+    LDR     r2, [r3]                            @ Pickup time-slice
+    CMP     r2, #0                              @ Is it active?
+    BEQ     __tx_thread_fiq_dont_save_ts        @ No, don't save it
+@
+@        _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+@        _tx_timer_time_slice =  0; 
+@
+    STR     r2, [r0, #24]                       @ Save thread's time-slice
+    MOV     r2, #0                              @ Clear value
+    STR     r2, [r3]                            @ Disable global time-slice flag
+@
+@    }
+__tx_thread_fiq_dont_save_ts:
+@
+@
+@    /* Clear the current task pointer.  */
+@    _tx_thread_current_ptr =  TX_NULL;
+@
+    MOV     r0, #0                              @ NULL value
+    STR     r0, [r1]                            @ Clear current thread pointer
+@
+@    /* Return to the scheduler.  */
+@    _tx_thread_schedule();
+@
+    B       _tx_thread_schedule                 @ Return to scheduler
+@    }
+@
+__tx_thread_fiq_idle_system_restore:
+@
+@    /* Just return back to the scheduler!  */
+@
+    ADD     sp, sp, #24                         @ Recover FIQ stack space
+    MOV     r3, #SVC_MODE                       @ Build SVC mode CPSR
+    MSR     CPSR_c, r3                          @ Lockout interrupts
+    B       _tx_thread_schedule                 @ Return to scheduler
+@
+@}
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S
new file mode 100644
index 00000000..48ebb94f
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_context_save.S
@@ -0,0 +1,204 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+    .global     _tx_thread_system_state
+    .global     _tx_thread_current_ptr
+    .global     __tx_fiq_processing_return
+    .global     _tx_execution_isr_enter
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save
+@   since it will never be called 16-bit mode.  */
+@
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_fiq_context_save                      Cortex-R4/GNU      */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function saves the context of an executing thread in the       */ 
+@/*    beginning of interrupt processing.  The function also ensures that  */ 
+@/*    the system stack is used upon return to the calling ISR.            */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                                                */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@ VOID   _tx_thread_fiq_context_save(VOID)
+@{
+    .global  _tx_thread_fiq_context_save
+    .type    _tx_thread_fiq_context_save,function
+_tx_thread_fiq_context_save:
+@
+@    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+@       out, we are in IRQ mode, and all registers are intact.  */
+@
+@    /* Check for a nested interrupt condition.  */
+@    if (_tx_thread_system_state++)
+@    {
+@
+    STMDB   sp!, {r0-r3}                        @ Save some working registers 
+    LDR     r3, =_tx_thread_system_state        @ Pickup address of system state variable
+    LDR     r2, [r3]                            @ Pickup system state
+    CMP     r2, #0                              @ Is this the first interrupt?
+    BEQ     __tx_thread_fiq_not_nested_save     @ Yes, not a nested context save
+@
+@    /* Nested interrupt condition.  */
+@
+    ADD     r2, r2, #1                          @ Increment the interrupt counter
+    STR     r2, [r3]                            @ Store it back in the variable
+@
+@    /* Save the rest of the scratch registers on the stack and return to the
+@       calling ISR.  */
+@
+    MRS     r0, SPSR                            @ Pickup saved SPSR
+    SUB     lr, lr, #4                          @ Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}             @ Store other registers
+@
+@    /* Return to the ISR.  */
+@
+    MOV     r10, #0                             @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                                @ Save ISR lr
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
+    POP     {lr}                                @ Recover ISR lr
+#endif
+
+    B       __tx_fiq_processing_return          @ Continue FIQ processing 
+@
+__tx_thread_fiq_not_nested_save:
+@    }  
+@
+@    /* Otherwise, not nested, check to see if a thread was running.  */
+@    else if (_tx_thread_current_ptr)
+@    {   
+@
+    ADD     r2, r2, #1                          @ Increment the interrupt counter
+    STR     r2, [r3]                            @ Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         @ Pickup address of current thread ptr
+    LDR     r0, [r1]                            @ Pickup current thread pointer
+    CMP     r0, #0                              @ Is it NULL?
+    BEQ     __tx_thread_fiq_idle_system_save    @ If so, interrupt occurred in 
+@                                               @   scheduling loop - nothing needs saving! 
+@
+@    /* Save minimal context of interrupted thread.  */
+@
+    MRS     r2, SPSR                            @ Pickup saved SPSR
+    SUB     lr, lr, #4                          @ Adjust point of interrupt 
+    STMDB   sp!, {r2, lr}                       @ Store other registers, Note that we don't
+@                                               @   need to save sl and ip since FIQ has 
+@                                               @   copies of these registers.  Nested 
+@                                               @   interrupt processing does need to save
+@                                               @   these registers.
+@
+@    /* Save the current stack pointer in the thread's control block.  */
+@    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp; 
+@
+@    /* Switch to the system stack.  */
+@    sp =  _tx_thread_system_stack_ptr; 
+@
+    MOV     r10, #0                             @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                                @ Save ISR lr
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
+    POP     {lr}                                @ Recover ISR lr
+#endif
+
+    B       __tx_fiq_processing_return          @ Continue FIQ processing 
+@
+@   }
+@   else
+@   {
+@
+__tx_thread_fiq_idle_system_save:
+@
+@    /* Interrupt occurred in the scheduling loop.  */
+@
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                                @ Save ISR lr
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
+    POP     {lr}                                @ Recover ISR lr
+#endif
+@
+@    /* Not much to do here, save the current SPSR and LR for possible
+@       use in IRQ interrupted in idle system conditions, and return to 
+@       FIQ interrupt processing.  */
+@
+    MRS     r0, SPSR                            @ Pickup saved SPSR
+    SUB     lr, lr, #4                          @ Adjust point of interrupt 
+    STMDB   sp!, {r0, lr}                       @ Store other registers that will get used
+@                                               @   or stripped off the stack in context 
+@                                               @   restore 
+    B       __tx_fiq_processing_return          @ Continue FIQ processing  
+@
+@    }
+@}  
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S
new file mode 100644
index 00000000..e30a7146
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_end.S
@@ -0,0 +1,116 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+#ifdef TX_ENABLE_FIQ_SUPPORT
+DISABLE_INTS    =       0xC0                    @ Disable IRQ/FIQ interrupts
+#else
+DISABLE_INTS    =       0x80                    @ Disable IRQ interrupts
+#endif
+MODE_MASK       =       0x1F                    @ Mode mask 
+FIQ_MODE_BITS   =       0x11                    @ FIQ mode bits
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end
+@   since it will never be called 16-bit mode.  */
+@
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_fiq_nesting_end                        Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is called by the application from FIQ mode after      */ 
+@/*    _tx_thread_fiq_nesting_start has been called and switches the FIQ   */ 
+@/*    processing from system mode back to FIQ mode prior to the ISR       */ 
+@/*    calling _tx_thread_fiq_context_restore.  Note that this function    */ 
+@/*    assumes the system stack pointer is in the same position after      */ 
+@/*    nesting start function was called.                                  */ 
+@/*                                                                        */ 
+@/*    This function assumes that the system mode stack pointer was setup  */ 
+@/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+@/*                                                                        */ 
+@/*    This function returns with FIQ interrupts disabled.                 */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                                                */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_fiq_nesting_end(VOID)
+@{
+    .global  _tx_thread_fiq_nesting_end
+    .type    _tx_thread_fiq_nesting_end,function
+_tx_thread_fiq_nesting_end:
+    MOV     r3,lr                               @ Save ISR return address
+    MRS     r0, CPSR                            @ Pickup the CPSR
+    ORR     r0, r0, #DISABLE_INTS               @ Build disable interrupt value
+    MSR     CPSR_c, r0                          @ Disable interrupts
+    LDMIA   sp!, {r1, lr}                       @ Pickup saved lr (and r1 throw-away for 
+                                                @   8-byte alignment logic)
+    BIC     r0, r0, #MODE_MASK                  @ Clear mode bits
+    ORR     r0, r0, #FIQ_MODE_BITS              @ Build IRQ mode CPSR
+    MSR     CPSR_c, r0                          @ Reenter IRQ mode
+
+#ifdef __THUMB_INTERWORK
+    BX      r3                                  @ Return to caller
+#else
+    MOV     pc, r3                              @ Return to caller
+#endif
+@}
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S
new file mode 100644
index 00000000..7679d8aa
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_fiq_nesting_start.S
@@ -0,0 +1,108 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+FIQ_DISABLE     =       0x40                    @ FIQ disable bit
+MODE_MASK       =       0x1F                    @ Mode mask
+SYS_MODE_BITS   =       0x1F                    @ System mode bits
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start
+@   since it will never be called 16-bit mode.  */
+@
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_fiq_nesting_start                      Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is called by the application from FIQ mode after      */ 
+@/*    _tx_thread_fiq_context_save has been called and switches the FIQ    */ 
+@/*    processing to the system mode so nested FIQ interrupt processing    */ 
+@/*    is possible (system mode has its own "lr" register).  Note that     */ 
+@/*    this function assumes that the system mode stack pointer was setup  */ 
+@/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+@/*                                                                        */ 
+@/*    This function returns with FIQ interrupts enabled.                  */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                                                */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_fiq_nesting_start(VOID)
+@{
+    .global  _tx_thread_fiq_nesting_start
+    .type    _tx_thread_fiq_nesting_start,function
+_tx_thread_fiq_nesting_start:
+    MOV     r3,lr                               @ Save ISR return address
+    MRS     r0, CPSR                            @ Pickup the CPSR
+    BIC     r0, r0, #MODE_MASK                  @ Clear the mode bits
+    ORR     r0, r0, #SYS_MODE_BITS              @ Build system mode CPSR
+    MSR     CPSR_c, r0                          @ Enter system mode
+    STMDB   sp!, {r1, lr}                       @ Push the system mode lr on the system mode stack
+                                                @   and push r1 just to keep 8-byte alignment
+    BIC     r0, r0, #FIQ_DISABLE                @ Build enable FIQ CPSR
+    MSR     CPSR_c, r0                          @ Enter system mode
+#ifdef __THUMB_INTERWORK
+    BX      r3                                  @ Return to caller
+#else
+    MOV     pc, r3                              @ Return to caller
+#endif
+@}
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S
new file mode 100644
index 00000000..cbe76857
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_interrupt_control.S
@@ -0,0 +1,115 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"  */
+@
+
+INT_MASK        =   0x03F
+
+@
+@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for
+@   applications calling this function from to 16-bit Thumb mode.  */
+@
+    .text
+    .align 2
+    .global $_tx_thread_interrupt_control
+$_tx_thread_interrupt_control:
+        .thumb
+     BX        pc                               @ Switch to 32-bit mode
+     NOP                                        @ 
+    .arm
+     STMFD     sp!, {lr}                        @ Save return address
+     BL        _tx_thread_interrupt_control     @ Call _tx_thread_interrupt_control function
+     LDMFD     sp!, {lr}                        @ Recover saved return address
+     BX        lr                               @ Return to 16-bit caller
+@
+@
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_interrupt_control                      Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is responsible for changing the interrupt lockout     */ 
+@/*    posture of the system.                                              */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    new_posture                           New interrupt lockout posture */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    old_posture                           Old interrupt lockout posture */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    Application Code                                                    */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@UINT   _tx_thread_interrupt_control(UINT new_posture)
+@{
+    .global _tx_thread_interrupt_control
+    .type   _tx_thread_interrupt_control,function
+_tx_thread_interrupt_control:
+@
+@    /* Pickup current interrupt lockout posture.  */
+@
+    MRS     r3, CPSR                    @ Pickup current CPSR
+    MOV     r2, #INT_MASK               @ Build interrupt mask
+    AND     r1, r3, r2                  @ Clear interrupt lockout bits
+    ORR     r1, r1, r0                  @ Or-in new interrupt lockout bits
+@
+@    /* Apply the new interrupt posture.  */
+@
+    MSR     CPSR_c, r1                  @ Setup new CPSR
+    BIC     r0, r3, r2                  @ Return previous interrupt mask
+#ifdef __THUMB_INTERWORK
+    BX      lr                          @ Return to caller
+#else
+    MOV     pc, lr                      @ Return to caller
+#endif
+@}
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S
new file mode 100644
index 00000000..9fe7a729
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_interrupt_disable.S
@@ -0,0 +1,113 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for
+@   applications calling this function from to 16-bit Thumb mode.  */
+@
+    .text
+    .align 2
+    .global $_tx_thread_interrupt_disable
+$_tx_thread_interrupt_disable:
+        .thumb
+     BX        pc                               @ Switch to 32-bit mode
+     NOP                                        @ 
+    .arm
+     STMFD     sp!, {lr}                        @ Save return address
+     BL        _tx_thread_interrupt_disable     @ Call _tx_thread_interrupt_disable function
+     LDMFD     sp!, {lr}                        @ Recover saved return address
+     BX        lr                               @ Return to 16-bit caller
+@
+@
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_interrupt_disable                      Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is responsible for disabling interrupts               */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    old_posture                           Old interrupt lockout posture */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    Application Code                                                    */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@UINT   _tx_thread_interrupt_disable(void)
+@{
+    .global _tx_thread_interrupt_disable
+    .type   _tx_thread_interrupt_disable,function
+_tx_thread_interrupt_disable:
+@
+@    /* Pickup current interrupt lockout posture.  */
+@
+    MRS     r0, CPSR                            @ Pickup current CPSR
+@
+@    /* Mask interrupts.  */
+@
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  @ Disable IRQ and FIQ
+#else
+    CPSID   i                                   @ Disable IRQ 
+#endif
+
+#ifdef __THUMB_INTERWORK
+    BX      lr                                  @ Return to caller
+#else
+    MOV     pc, lr                              @ Return to caller
+#endif
+@}
+
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S
new file mode 100644
index 00000000..e89b7999
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_interrupt_restore.S
@@ -0,0 +1,104 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for
+@   applications calling this function from to 16-bit Thumb mode.  */
+@
+    .text
+    .align 2
+    .global $_tx_thread_interrupt_restore
+$_tx_thread_interrupt_restore:
+        .thumb
+     BX        pc                               @ Switch to 32-bit mode
+     NOP                                        @ 
+    .arm
+     STMFD     sp!, {lr}                        @ Save return address
+     BL        _tx_thread_interrupt_restore     @ Call _tx_thread_interrupt_restore function
+     LDMFD     sp!, {lr}                        @ Recover saved return address
+     BX        lr                               @ Return to 16-bit caller
+@
+@
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_interrupt_restore                      Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is responsible for restoring interrupts to the state  */
+@/*    returned by a previous _tx_thread_interrupt_disable call.           */
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    old_posture                           Old interrupt lockout posture */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    Application Code                                                    */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@UINT   _tx_thread_interrupt_restore(UINT old_posture)
+@{
+    .global  _tx_thread_interrupt_restore
+    .type    _tx_thread_interrupt_restore,function
+_tx_thread_interrupt_restore:
+@
+@    /* Apply the new interrupt posture.  */
+@
+    MSR     CPSR_c, r0                          @ Setup new CPSR
+#ifdef __THUMB_INTERWORK
+    BX      lr                                  @ Return to caller
+#else
+    MOV     pc, lr                              @ Return to caller
+#endif
+@}
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S
new file mode 100644
index 00000000..c5800dfe
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_end.S
@@ -0,0 +1,115 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+#ifdef TX_ENABLE_FIQ_SUPPORT
+DISABLE_INTS    =       0xC0                    @ Disable IRQ/FIQ interrupts
+#else
+DISABLE_INTS    =       0x80                    @ Disable IRQ interrupts
+#endif
+MODE_MASK       =       0x1F                    @ Mode mask 
+IRQ_MODE_BITS   =       0x12                    @ IRQ mode bits
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end
+@   since it will never be called 16-bit mode.  */
+@
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_irq_nesting_end                        Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is called by the application from IRQ mode after      */ 
+@/*    _tx_thread_irq_nesting_start has been called and switches the IRQ   */ 
+@/*    processing from system mode back to IRQ mode prior to the ISR       */ 
+@/*    calling _tx_thread_context_restore.  Note that this function        */ 
+@/*    assumes the system stack pointer is in the same position after      */ 
+@/*    nesting start function was called.                                  */ 
+@/*                                                                        */ 
+@/*    This function assumes that the system mode stack pointer was setup  */ 
+@/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+@/*                                                                        */ 
+@/*    This function returns with IRQ interrupts disabled.                 */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                                                */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_irq_nesting_end(VOID)
+@{
+    .global  _tx_thread_irq_nesting_end
+    .type    _tx_thread_irq_nesting_end,function
+_tx_thread_irq_nesting_end:
+    MOV     r3,lr                               @ Save ISR return address
+    MRS     r0, CPSR                            @ Pickup the CPSR
+    ORR     r0, r0, #DISABLE_INTS               @ Build disable interrupt value
+    MSR     CPSR_c, r0                          @ Disable interrupts
+    LDMIA   sp!, {r1, lr}                       @ Pickup saved lr (and r1 throw-away for 
+                                                @   8-byte alignment logic)
+    BIC     r0, r0, #MODE_MASK                  @ Clear mode bits
+    ORR     r0, r0, #IRQ_MODE_BITS              @ Build IRQ mode CPSR
+    MSR     CPSR_c, r0                          @ Reenter IRQ mode
+#ifdef __THUMB_INTERWORK
+    BX      r3                                  @ Return to caller
+#else
+    MOV     pc, r3                              @ Return to caller
+#endif
+@}
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S
new file mode 100644
index 00000000..c7675bf2
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_irq_nesting_start.S
@@ -0,0 +1,108 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+IRQ_DISABLE     =       0x80                    @ IRQ disable bit
+MODE_MASK       =       0x1F                    @ Mode mask
+SYS_MODE_BITS   =       0x1F                    @ System mode bits
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start
+@   since it will never be called 16-bit mode.  */
+@
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_irq_nesting_start                      Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is called by the application from IRQ mode after      */ 
+@/*    _tx_thread_context_save has been called and switches the IRQ        */ 
+@/*    processing to the system mode so nested IRQ interrupt processing    */ 
+@/*    is possible (system mode has its own "lr" register).  Note that     */ 
+@/*    this function assumes that the system mode stack pointer was setup  */ 
+@/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+@/*                                                                        */ 
+@/*    This function returns with IRQ interrupts enabled.                  */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                                                */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_irq_nesting_start(VOID)
+@{
+    .global  _tx_thread_irq_nesting_start
+    .type    _tx_thread_irq_nesting_start,function
+_tx_thread_irq_nesting_start:
+    MOV     r3,lr                               @ Save ISR return address
+    MRS     r0, CPSR                            @ Pickup the CPSR
+    BIC     r0, r0, #MODE_MASK                  @ Clear the mode bits
+    ORR     r0, r0, #SYS_MODE_BITS              @ Build system mode CPSR
+    MSR     CPSR_c, r0                          @ Enter system mode
+    STMDB   sp!, {r1, lr}                       @ Push the system mode lr on the system mode stack
+                                                @   and push r1 just to keep 8-byte alignment
+    BIC     r0, r0, #IRQ_DISABLE                @ Build enable IRQ CPSR
+    MSR     CPSR_c, r0                          @ Enter system mode
+#ifdef __THUMB_INTERWORK
+    BX      r3                                  @ Return to caller
+#else
+    MOV     pc, r3                              @ Return to caller
+#endif
+@}
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_schedule.S b/ports/cortex_r4/gnu/src/tx_thread_schedule.S
new file mode 100644
index 00000000..365e5678
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_schedule.S
@@ -0,0 +1,250 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@#include "tx_timer.h"
+@
+@
+    .global     _tx_thread_execute_ptr
+    .global     _tx_thread_current_ptr
+    .global     _tx_timer_time_slice
+    .global     _tx_execution_thread_enter
+@
+@
+@/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for
+@   applications calling this function from to 16-bit Thumb mode.  */
+@
+    .text
+    .align  2
+    .global $_tx_thread_schedule
+    .type   $_tx_thread_schedule,function
+$_tx_thread_schedule:
+         .thumb
+     BX        pc                                   @ Switch to 32-bit mode
+     NOP                                            @ 
+    .arm
+     STMFD     sp!, {lr}                            @ Save return address
+     BL        _tx_thread_schedule                  @ Call _tx_thread_schedule function
+     LDMFD     sp!, {lr}                            @ Recover saved return address
+     BX        lr                                   @ Return to 16-bit caller
+@
+@
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_schedule                               Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function waits for a thread control block pointer to appear in */ 
+@/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */ 
+@/*    in the variable, the corresponding thread is resumed.               */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    _tx_initialize_kernel_enter          ThreadX entry function         */ 
+@/*    _tx_thread_system_return             Return to system from thread   */ 
+@/*    _tx_thread_context_restore           Restore thread's context       */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_schedule(VOID)
+@{
+    .global _tx_thread_schedule
+        .type  _tx_thread_schedule,function
+_tx_thread_schedule:
+@
+@    /* Enable interrupts.  */
+@
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSIE   if                                  @ Enable IRQ and FIQ interrupts
+#else
+    CPSIE   i                                   @ Enable IRQ interrupts
+#endif
+@
+@    /* Wait for a thread to execute.  */
+@    do
+@    {
+    LDR     r1, =_tx_thread_execute_ptr         @ Address of thread execute ptr
+@
+__tx_thread_schedule_loop:
+@
+    LDR     r0, [r1]                            @ Pickup next thread to execute
+    CMP     r0, #0                              @ Is it NULL?
+    BEQ     __tx_thread_schedule_loop           @ If so, keep looking for a thread
+@
+@    }
+@    while(_tx_thread_execute_ptr == TX_NULL);
+@    
+@    /* Yes! We have a thread to execute.  Lockout interrupts and
+@       transfer control to it.  */
+@
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  @ Disable IRQ and FIQ interrupts
+#else
+    CPSID   i                                   @ Disable IRQ interrupts
+#endif
+@
+@    /* Setup the current thread pointer.  */
+@    _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+@
+    LDR     r1, =_tx_thread_current_ptr         @ Pickup address of current thread 
+    STR     r0, [r1]                            @ Setup current thread pointer
+@
+@    /* Increment the run count for this thread.  */
+@    _tx_thread_current_ptr -> tx_thread_run_count++;
+@
+    LDR     r2, [r0, #4]                        @ Pickup run counter
+    LDR     r3, [r0, #24]                       @ Pickup time-slice for this thread
+    ADD     r2, r2, #1                          @ Increment thread run-counter
+    STR     r2, [r0, #4]                        @ Store the new run counter
+@
+@    /* Setup time-slice, if present.  */
+@    _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+@
+    LDR     r2, =_tx_timer_time_slice           @ Pickup address of time-slice 
+                                                @   variable
+    LDR     sp, [r0, #8]                        @ Switch stack pointers
+    STR     r3, [r2]                            @ Setup time-slice
+@
+@    /* Switch to the thread's stack.  */
+@    sp =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;
+@
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the thread entry function to indicate the thread is executing.  */
+@
+    BL      _tx_execution_thread_enter          @ Call the thread execution enter function
+#endif
+@
+@    /* Determine if an interrupt frame or a synchronous task suspension frame
+@   is present.  */
+@
+    LDMIA   sp!, {r4, r5}                       @ Pickup the stack type and saved CPSR
+    CMP     r4, #0                              @ Check for synchronous context switch
+    BEQ     _tx_solicited_return
+    MSR     SPSR_cxsf, r5                       @ Setup SPSR for return
+#ifdef TX_ENABLE_VFP_SUPPORT
+    LDR     r1, [r0, #144]                      @ Pickup the VFP enabled flag
+    CMP     r1, #0                              @ Is the VFP enabled?
+    BEQ     _tx_skip_interrupt_vfp_restore      @ No, skip VFP interrupt restore
+    VLDMIA  sp!, {D0-D15}                       @ Recover D0-D15
+    LDR     r4, [sp], #4                        @ Pickup FPSCR
+    VMSR    FPSCR, r4                           @ Restore FPSCR
+_tx_skip_interrupt_vfp_restore:
+#endif
+    LDMIA   sp!, {r0-r12, lr, pc}^              @ Return to point of thread interrupt
+@
+_tx_solicited_return:
+#ifdef TX_ENABLE_VFP_SUPPORT
+    LDR     r1, [r0, #144]                      @ Pickup the VFP enabled flag
+    CMP     r1, #0                              @ Is the VFP enabled?
+    BEQ     _tx_skip_solicited_vfp_restore      @ No, skip VFP solicited restore
+    VLDMIA  sp!, {D8-D15}                       @ Recover D8-D15
+    LDR     r4, [sp], #4                        @ Pickup FPSCR
+    VMSR    FPSCR, r4                           @ Restore FPSCR
+_tx_skip_solicited_vfp_restore:
+#endif
+    MOV     r0, r5                              @ Move CPSR to scratch register
+    LDMIA   sp!, {r4-r11, lr}                   @ Return to thread synchronously
+    MSR     CPSR_cxsf, r0                       @ Recover CPSR
+@
+#ifdef __THUMB_INTERWORK
+    BX      lr                                  @ Return to caller
+#else
+    MOV     pc, lr                              @ Return to caller
+#endif
+@
+@}
+@
+@
+#ifdef TX_ENABLE_VFP_SUPPORT
+    .global tx_thread_vfp_enable
+    .type  tx_thread_vfp_enable,function
+tx_thread_vfp_enable:
+    MRS     r2, CPSR                            @ Pickup the CPSR
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  @ Disable IRQ and FIQ interrupts
+#else
+    CPSID   i                                   @ Disable IRQ interrupts
+#endif
+    LDR     r0, =_tx_thread_current_ptr         @ Build current thread pointer address
+    LDR     r1, [r0]                            @ Pickup current thread pointer
+    CMP     r1, #0                              @ Check for NULL thread pointer
+    BEQ     __tx_no_thread_to_enable            @ If NULL, skip VFP enable
+    MOV     r0, #1                              @ Build enable value
+    STR     r0, [r1, #144]                      @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
+__tx_no_thread_to_enable:
+    MSR     CPSR_cxsf, r2                       @ Recover CPSR
+    BX      LR                                  @ Return to caller
+@
+    .global tx_thread_vfp_disable
+    .type  tx_thread_vfp_disable,function
+tx_thread_vfp_disable:
+    MRS     r2, CPSR                            @ Pickup the CPSR
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  @ Disable IRQ and FIQ interrupts
+#else
+    CPSID   i                                   @ Disable IRQ interrupts
+#endif
+    LDR     r0, =_tx_thread_current_ptr         @ Build current thread pointer address
+    LDR     r1, [r0]                            @ Pickup current thread pointer
+    CMP     r1, #0                              @ Check for NULL thread pointer
+    BEQ     __tx_no_thread_to_disable           @ If NULL, skip VFP disable
+    MOV     r0, #0                              @ Build disable value
+    STR     r0, [r1, #144]                      @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
+__tx_no_thread_to_disable:
+    MSR     CPSR_cxsf, r2                       @ Recover CPSR
+    BX      LR                                  @ Return to caller
+#endif
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_stack_build.S b/ports/cortex_r4/gnu/src/tx_thread_stack_build.S
new file mode 100644
index 00000000..2b573dce
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_stack_build.S
@@ -0,0 +1,178 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+    .arm
+
+SVC_MODE        =       0x13                    @ SVC mode
+#ifdef TX_ENABLE_FIQ_SUPPORT
+CPSR_MASK       =       0xDF                    @ Mask initial CPSR, IRQ & FIQ interrupts enabled
+#else
+CPSR_MASK       =       0x9F                    @ Mask initial CPSR, IRQ interrupts enabled
+#endif
+@
+@
+@/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for
+@   applications calling this function from to 16-bit Thumb mode.  */
+@
+    .text
+    .align 2
+    .thumb
+    .global $_tx_thread_stack_build
+    .type    $_tx_thread_stack_build,function
+$_tx_thread_stack_build:
+     BX        pc                               @ Switch to 32-bit mode
+     NOP                                        @ 
+    .arm
+     STMFD     sp!, {lr}                        @ Save return address
+     BL        _tx_thread_stack_build           @ Call _tx_thread_stack_build function
+     LDMFD     sp!, {lr}                        @ Recover saved return address
+     BX        lr                               @ Return to 16-bit caller
+@
+@
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_stack_build                            Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function builds a stack frame on the supplied thread's stack.  */
+@/*    The stack frame results in a fake interrupt return to the supplied  */
+@/*    function pointer.                                                   */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    thread_ptr                            Pointer to thread control blk */
+@/*    function_ptr                          Pointer to return function    */
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    _tx_thread_create                     Create thread service         */
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+@{
+    .global  _tx_thread_stack_build
+    .type    _tx_thread_stack_build,function
+_tx_thread_stack_build:
+@
+@       
+@    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+@       on the ARM9 should look like the following after it is built:
+@       
+@       Stack Top:      1           Interrupt stack frame type
+@                       CPSR        Initial value for CPSR
+@                       a1 (r0)     Initial value for a1
+@                       a2 (r1)     Initial value for a2
+@                       a3 (r2)     Initial value for a3
+@                       a4 (r3)     Initial value for a4
+@                       v1 (r4)     Initial value for v1
+@                       v2 (r5)     Initial value for v2
+@                       v3 (r6)     Initial value for v3
+@                       v4 (r7)     Initial value for v4
+@                       v5 (r8)     Initial value for v5
+@                       sb (r9)     Initial value for sb
+@                       sl (r10)    Initial value for sl
+@                       fp (r11)    Initial value for fp
+@                       ip (r12)    Initial value for ip
+@                       lr (r14)    Initial value for lr
+@                       pc (r15)    Initial value for pc
+@                       0       For stack backtracing
+@
+@    Stack Bottom: (higher memory address)  */
+@
+    LDR     r2, [r0, #16]                   @ Pickup end of stack area
+    BIC     r2, r2, #7                      @ Ensure 8-byte alignment
+    SUB     r2, r2, #76                     @ Allocate space for the stack frame
+@
+@    /* Actually build the stack frame.  */
+@
+    MOV     r3, #1                          @ Build interrupt stack type
+    STR     r3, [r2, #0]                    @ Store stack type
+    MOV     r3, #0                          @ Build initial register value
+    STR     r3, [r2, #8]                    @ Store initial r0
+    STR     r3, [r2, #12]                   @ Store initial r1
+    STR     r3, [r2, #16]                   @ Store initial r2
+    STR     r3, [r2, #20]                   @ Store initial r3
+    STR     r3, [r2, #24]                   @ Store initial r4
+    STR     r3, [r2, #28]                   @ Store initial r5
+    STR     r3, [r2, #32]                   @ Store initial r6
+    STR     r3, [r2, #36]                   @ Store initial r7
+    STR     r3, [r2, #40]                   @ Store initial r8
+    STR     r3, [r2, #44]                   @ Store initial r9
+    LDR     r3, [r0, #12]                   @ Pickup stack starting address
+    STR     r3, [r2, #48]                   @ Store initial r10 (sl)
+    LDR     r3,=_tx_thread_schedule         @ Pickup address of _tx_thread_schedule for GDB backtrace
+    STR     r3, [r2, #60]                   @ Store initial r14 (lr)
+    MOV     r3, #0                          @ Build initial register value
+    STR     r3, [r2, #52]                   @ Store initial r11
+    STR     r3, [r2, #56]                   @ Store initial r12
+    STR     r1, [r2, #64]                   @ Store initial pc
+    STR     r3, [r2, #68]                   @ 0 for back-trace
+    MRS     r1, CPSR                        @ Pickup CPSR
+    BIC     r1, r1, #CPSR_MASK              @ Mask mode bits of CPSR
+    ORR     r3, r1, #SVC_MODE               @ Build CPSR, SVC mode, interrupts enabled
+    STR     r3, [r2, #4]                    @ Store initial CPSR
+@
+@    /* Setup stack pointer.  */
+@    thread_ptr -> tx_thread_stack_ptr =  r2;
+@
+    STR     r2, [r0, #8]                    @ Save stack pointer in thread's
+                                            @   control block
+#ifdef __THUMB_INTERWORK
+    BX      lr                              @ Return to caller
+#else
+    MOV     pc, lr                          @ Return to caller
+#endif
+@}
+
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_system_return.S b/ports/cortex_r4/gnu/src/tx_thread_system_return.S
new file mode 100644
index 00000000..9d18837f
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_system_return.S
@@ -0,0 +1,177 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@#include "tx_timer.h"
+@
+    .arm
+@
+@
+    .global     _tx_thread_current_ptr
+    .global     _tx_timer_time_slice
+    .global     _tx_thread_schedule
+    .global     _tx_execution_thread_exit
+@
+@
+@
+@/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for
+@   applications calling this function from to 16-bit Thumb mode.  */
+@
+    .text
+    .align  2
+    .global $_tx_thread_system_return
+    .type   $_tx_thread_system_return,function
+$_tx_thread_system_return:
+    .thumb
+     BX        pc                               @ Switch to 32-bit mode
+     NOP                                        @ 
+    .arm
+     STMFD     sp!, {lr}                        @ Save return address
+     BL        _tx_thread_system_return         @ Call _tx_thread_system_return function
+     LDMFD     sp!, {lr}                        @ Recover saved return address
+     BX        lr                               @ Return to 16-bit caller
+@
+@
+    .text
+    .align  2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_system_return                          Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function is target processor specific.  It is used to transfer */ 
+@/*    control from a thread back to the ThreadX system.  Only a           */ 
+@/*    minimal context is saved since the compiler assumes temp registers  */ 
+@/*    are going to get slicked by a function call anyway.                 */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    _tx_thread_schedule                   Thread scheduling loop        */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ThreadX components                                                  */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_thread_system_return(VOID)
+@{
+    .global _tx_thread_system_return
+    .type   _tx_thread_system_return,function
+_tx_thread_system_return:
+@
+@   /* Lockout interrupts.  */
+@
+    MRS     r1, CPSR                            @ Pickup the CPSR
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  @ Enable IRQ and FIQ interrupts
+#else
+    CPSID   i                                   @ Enable IRQ interrupts
+#endif
+@    /* Save minimal context on the stack.  */
+@
+    STMDB   sp!, {r4-r11, lr}                   @ Save minimal context
+    LDR     r5, =_tx_thread_current_ptr         @ Pickup address of current ptr
+    LDR     r6, [r5]                            @ Pickup current thread pointer
+@
+#ifdef TX_ENABLE_VFP_SUPPORT
+    LDR     r0, [r6, #144]                      @ Pickup the VFP enabled flag
+    CMP     r0, #0                              @ Is the VFP enabled?
+    BEQ     _tx_skip_solicited_vfp_save         @ No, skip VFP solicited save
+    VMRS    r4, FPSCR                           @ Pickup the FPSCR
+    STR     r4, [sp, #-4]!                      @ Save FPSCR
+    VSTMDB  sp!, {D8-D15}                       @ Save D8-D15
+_tx_skip_solicited_vfp_save:
+#endif
+@
+    MOV     r0, #0                              @ Build a solicited stack type
+    STMDB   sp!, {r0-r1}                        @ Save type and CPSR
+@   
+@
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the thread exit function to indicate the thread is no longer executing.  */
+@
+    BL      _tx_execution_thread_exit           @ Call the thread exit function
+#endif
+@
+    LDR     r2, =_tx_timer_time_slice           @ Pickup address of time slice
+    LDR     r1, [r2]                            @ Pickup current time slice
+@
+@    /* Save current stack and switch to system stack.  */
+@    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+@    sp = _tx_thread_system_stack_ptr;
+@
+    STR     sp, [r6, #8]                        @ Save thread stack pointer
+@
+@    /* Determine if the time-slice is active.  */
+@    if (_tx_timer_time_slice)
+@    {
+@
+    MOV     r4, #0                              @ Build clear value
+    CMP     r1, #0                              @ Is a time-slice active?
+    BEQ     __tx_thread_dont_save_ts            @ No, don't save the time-slice
+@
+@       /* Save time-slice for the thread and clear the current time-slice.  */
+@       _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+@       _tx_timer_time_slice =  0;
+@
+    STR     r4, [r2]                            @ Clear time-slice
+    STR     r1, [r6, #24]                       @ Save current time-slice
+@
+@    }
+__tx_thread_dont_save_ts:
+@
+@    /* Clear the current thread pointer.  */
+@    _tx_thread_current_ptr =  TX_NULL;
+@
+    STR     r4, [r5]                            @ Clear current thread pointer
+    B       _tx_thread_schedule                 @ Jump to scheduler!
+@
+@}
+
diff --git a/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S
new file mode 100644
index 00000000..9f69fa32
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_thread_vectored_context_save.S
@@ -0,0 +1,190 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Thread                                                              */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_thread.h"
+@
+@
+    .global     _tx_thread_system_state
+    .global     _tx_thread_current_ptr
+    .global     _tx_execution_isr_enter
+@
+@
+@
+@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save
+@   since it will never be called 16-bit mode.  */
+@ 
+    .arm
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_thread_vectored_context_save                  Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function saves the context of an executing thread in the       */ 
+@/*    beginning of interrupt processing.  The function also ensures that  */ 
+@/*    the system stack is used upon return to the calling ISR.            */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    ISRs                                                                */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID  _tx_thread_vectored_context_save(VOID)
+@{
+    .global  _tx_thread_vectored_context_save
+    .type    _tx_thread_vectored_context_save,function
+_tx_thread_vectored_context_save:
+@
+@    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+@       out, we are in IRQ mode, and all registers are intact.  */
+@
+@    /* Check for a nested interrupt condition.  */
+@    if (_tx_thread_system_state++)
+@    {
+@
+#ifdef TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  @ Disable IRQ and FIQ interrupts
+#endif
+    LDR     r3, =_tx_thread_system_state        @ Pickup address of system state variable
+    LDR     r2, [r3, #0]                        @ Pickup system state
+    CMP     r2, #0                              @ Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         @ Yes, not a nested context save
+@
+@    /* Nested interrupt condition.  */
+@
+    ADD     r2, r2, #1                          @ Increment the interrupt counter
+    STR     r2, [r3, #0]                        @ Store it back in the variable
+@
+@    /* Note: Minimal context of interrupted thread is already saved.  */
+@
+@    /* Return to the ISR.  */
+@
+    MOV     r10, #0                             @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                                @ Save ISR lr
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
+    POP     {lr}                                @ Recover ISR lr
+#endif
+
+    MOV     pc, lr                              @ Return to caller
+@
+__tx_thread_not_nested_save:
+@    }
+@
+@    /* Otherwise, not nested, check to see if a thread was running.  */
+@    else if (_tx_thread_current_ptr)
+@    {
+@
+    ADD     r2, r2, #1                          @ Increment the interrupt counter
+    STR     r2, [r3, #0]                        @ Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         @ Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        @ Pickup current thread pointer
+    CMP     r0, #0                              @ Is it NULL?
+    BEQ     __tx_thread_idle_system_save        @ If so, interrupt occurred in 
+                                                @   scheduling loop - nothing needs saving!
+@
+@    /* Note: Minimal context of interrupted thread is already saved.  */
+@
+@    /* Save the current stack pointer in the thread's control block.  */
+@    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+@
+@    /* Switch to the system stack.  */
+@    sp =  _tx_thread_system_stack_ptr;
+@
+    MOV     r10, #0                             @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                                @ Save ISR lr
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
+    POP     {lr}                                @ Recover ISR lr
+#endif
+
+    MOV     pc, lr                              @ Return to caller
+@
+@    }
+@    else
+@    {
+@
+__tx_thread_idle_system_save:
+@
+@    /* Interrupt occurred in the scheduling loop.  */
+@
+@    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+@       processing.  */
+@
+    MOV     r10, #0                             @ Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+@
+@    /* Call the ISR enter function to indicate an ISR is executing.  */
+@
+    PUSH    {lr}                                @ Save ISR lr
+    BL      _tx_execution_isr_enter             @ Call the ISR enter function
+    POP     {lr}                                @ Recover ISR lr
+#endif
+
+    ADD     sp, sp, #32                         @ Recover saved registers
+    MOV     pc, lr                              @ Return to caller
+@
+@    }
+@}
+
diff --git a/ports/cortex_r4/gnu/src/tx_timer_interrupt.S b/ports/cortex_r4/gnu/src/tx_timer_interrupt.S
new file mode 100644
index 00000000..629e0928
--- /dev/null
+++ b/ports/cortex_r4/gnu/src/tx_timer_interrupt.S
@@ -0,0 +1,279 @@
+@/**************************************************************************/
+@/*                                                                        */
+@/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+@/*                                                                        */
+@/*       This software is licensed under the Microsoft Software License   */
+@/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+@/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+@/*       and in the root directory of this software.                      */
+@/*                                                                        */
+@/**************************************************************************/
+@
+@
+@/**************************************************************************/
+@/**************************************************************************/
+@/**                                                                       */ 
+@/** ThreadX Component                                                     */ 
+@/**                                                                       */
+@/**   Timer                                                               */
+@/**                                                                       */
+@/**************************************************************************/
+@/**************************************************************************/
+@
+@#define TX_SOURCE_CODE
+@
+@
+@/* Include necessary system files.  */
+@
+@#include "tx_api.h"
+@#include "tx_timer.h"
+@#include "tx_thread.h"
+@
+@
+    .arm
+
+@
+@/* Define Assembly language external references...  */
+@
+    .global     _tx_timer_time_slice
+    .global     _tx_timer_system_clock
+    .global     _tx_timer_current_ptr
+    .global     _tx_timer_list_start
+    .global     _tx_timer_list_end
+    .global     _tx_timer_expired_time_slice
+    .global     _tx_timer_expired
+    .global     _tx_thread_time_slice
+@
+@
+@
+@/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for
+@   applications calling this function from to 16-bit Thumb mode.  */
+@
+    .text
+    .align 2
+    .thumb
+    .global $_tx_timer_interrupt
+    .type   $_tx_timer_interrupt,function
+$_tx_timer_interrupt:
+     BX        pc                               @ Switch to 32-bit mode
+     NOP                                        @ 
+    .arm
+     STMFD     sp!, {lr}                        @ Save return address
+     BL        _tx_timer_interrupt              @ Call _tx_timer_interrupt function
+     LDMFD     sp!, {lr}                        @ Recover saved return address
+     BX        lr                               @ Return to 16-bit caller
+@
+@
+    .text
+    .align 2
+@/**************************************************************************/ 
+@/*                                                                        */ 
+@/*  FUNCTION                                               RELEASE        */ 
+@/*                                                                        */ 
+@/*    _tx_timer_interrupt                               Cortex-R4/GNU     */ 
+@/*                                                           6.0.1        */
+@/*  AUTHOR                                                                */
+@/*                                                                        */
+@/*    William E. Lamie, Microsoft Corporation                             */
+@/*                                                                        */
+@/*  DESCRIPTION                                                           */
+@/*                                                                        */ 
+@/*    This function processes the hardware timer interrupt.  This         */ 
+@/*    processing includes incrementing the system clock and checking for  */ 
+@/*    time slice and/or timer expiration.  If either is found, the        */ 
+@/*    interrupt context save/restore functions are called along with the  */ 
+@/*    expiration functions.                                               */ 
+@/*                                                                        */ 
+@/*  INPUT                                                                 */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  OUTPUT                                                                */ 
+@/*                                                                        */ 
+@/*    None                                                                */ 
+@/*                                                                        */ 
+@/*  CALLS                                                                 */ 
+@/*                                                                        */ 
+@/*    _tx_thread_time_slice                 Time slice interrupted thread */ 
+@/*    _tx_timer_expiration_process          Timer expiration processing   */ 
+@/*                                                                        */ 
+@/*  CALLED BY                                                             */ 
+@/*                                                                        */ 
+@/*    interrupt vector                                                    */ 
+@/*                                                                        */ 
+@/*  RELEASE HISTORY                                                       */ 
+@/*                                                                        */ 
+@/*    DATE              NAME                      DESCRIPTION             */
+@/*                                                                        */
+@/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+@/*                                                                        */
+@/**************************************************************************/
+@VOID   _tx_timer_interrupt(VOID)
+@{
+    .global _tx_timer_interrupt
+    .type   _tx_timer_interrupt,function
+_tx_timer_interrupt:
+@
+@    /* Upon entry to this routine, it is assumed that context save has already
+@       been called, and therefore the compiler scratch registers are available
+@       for use.  */
+@
+@    /* Increment the system clock.  */
+@    _tx_timer_system_clock++;
+@
+    LDR     r1, =_tx_timer_system_clock         @ Pickup address of system clock
+    LDR     r0, [r1]                            @ Pickup system clock
+    ADD     r0, r0, #1                          @ Increment system clock
+    STR     r0, [r1]                            @ Store new system clock
+@
+@    /* Test for time-slice expiration.  */
+@    if (_tx_timer_time_slice)
+@    {
+@
+    LDR     r3, =_tx_timer_time_slice           @ Pickup address of time-slice 
+    LDR     r2, [r3]                            @ Pickup time-slice
+    CMP     r2, #0                              @ Is it non-active?
+    BEQ     __tx_timer_no_time_slice            @ Yes, skip time-slice processing
+@
+@       /* Decrement the time_slice.  */
+@       _tx_timer_time_slice--;
+@
+    SUB     r2, r2, #1                          @ Decrement the time-slice
+    STR     r2, [r3]                            @ Store new time-slice value
+@
+@       /* Check for expiration.  */
+@       if (__tx_timer_time_slice == 0)
+@
+    CMP     r2, #0                              @ Has it expired?
+    BNE     __tx_timer_no_time_slice            @ No, skip expiration processing
+@
+@       /* Set the time-slice expired flag.  */
+@       _tx_timer_expired_time_slice =  TX_TRUE;
+@
+    LDR     r3, =_tx_timer_expired_time_slice   @ Pickup address of expired flag
+    MOV     r0, #1                              @ Build expired value
+    STR     r0, [r3]                            @ Set time-slice expiration flag
+@
+@    }
+@
+__tx_timer_no_time_slice:
+@
+@    /* Test for timer expiration.  */
+@    if (*_tx_timer_current_ptr)
+@    {
+@
+    LDR     r1, =_tx_timer_current_ptr          @ Pickup current timer pointer address
+    LDR     r0, [r1]                            @ Pickup current timer
+    LDR     r2, [r0]                            @ Pickup timer list entry
+    CMP     r2, #0                              @ Is there anything in the list?
+    BEQ     __tx_timer_no_timer                 @ No, just increment the timer
+@
+@        /* Set expiration flag.  */
+@        _tx_timer_expired =  TX_TRUE;
+@
+    LDR     r3, =_tx_timer_expired              @ Pickup expiration flag address
+    MOV     r2, #1                              @ Build expired value
+    STR     r2, [r3]                            @ Set expired flag
+    B       __tx_timer_done                     @ Finished timer processing
+@
+@    }
+@    else
+@    {
+__tx_timer_no_timer:
+@
+@        /* No timer expired, increment the timer pointer.  */
+@        _tx_timer_current_ptr++;
+@
+    ADD     r0, r0, #4                          @ Move to next timer
+@
+@        /* Check for wraparound.  */
+@        if (_tx_timer_current_ptr == _tx_timer_list_end)
+@
+    LDR     r3, =_tx_timer_list_end             @ Pickup address of timer list end
+    LDR     r2, [r3]                            @ Pickup list end
+    CMP     r0, r2                              @ Are we at list end?
+    BNE     __tx_timer_skip_wrap                @ No, skip wraparound logic
+@
+@            /* Wrap to beginning of list.  */
+@            _tx_timer_current_ptr =  _tx_timer_list_start;
+@
+    LDR     r3, =_tx_timer_list_start           @ Pickup address of timer list start
+    LDR     r0, [r3]                            @ Set current pointer to list start
+@
+__tx_timer_skip_wrap:
+@
+    STR     r0, [r1]                            @ Store new current timer pointer
+@    }
+@
+__tx_timer_done:
+@
+@
+@    /* See if anything has expired.  */
+@    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+@    {
+@
+    LDR     r3, =_tx_timer_expired_time_slice   @ Pickup address of expired flag
+    LDR     r2, [r3]                            @ Pickup time-slice expired flag
+    CMP     r2, #0                              @ Did a time-slice expire?
+    BNE     __tx_something_expired              @ If non-zero, time-slice expired
+    LDR     r1, =_tx_timer_expired              @ Pickup address of other expired flag
+    LDR     r0, [r1]                            @ Pickup timer expired flag
+    CMP     r0, #0                              @ Did a timer expire?
+    BEQ     __tx_timer_nothing_expired          @ No, nothing expired
+@
+__tx_something_expired:
+@
+@
+    STMDB   sp!, {r0, lr}                       @ Save the lr register on the stack
+                                                @   and save r0 just to keep 8-byte alignment
+@
+@    /* Did a timer expire?  */
+@    if (_tx_timer_expired)
+@    {
+@
+    LDR     r1, =_tx_timer_expired              @ Pickup address of expired flag
+    LDR     r0, [r1]                            @ Pickup timer expired flag
+    CMP     r0, #0                              @ Check for timer expiration
+    BEQ     __tx_timer_dont_activate            @ If not set, skip timer activation
+@
+@        /* Process timer expiration.  */
+@        _tx_timer_expiration_process();
+@
+    BL      _tx_timer_expiration_process        @ Call the timer expiration handling routine
+@
+@    }
+__tx_timer_dont_activate:
+@
+@    /* Did time slice expire?  */
+@    if (_tx_timer_expired_time_slice)
+@    {
+@
+    LDR     r3, =_tx_timer_expired_time_slice   @ Pickup address of time-slice expired 
+    LDR     r2, [r3]                            @ Pickup the actual flag
+    CMP     r2, #0                              @ See if the flag is set
+    BEQ     __tx_timer_not_ts_expiration        @ No, skip time-slice processing
+@
+@        /* Time slice interrupted thread.  */
+@        _tx_thread_time_slice();
+@
+    BL      _tx_thread_time_slice               @ Call time-slice processing
+@
+@    }
+@
+__tx_timer_not_ts_expiration:
+@
+    LDMIA   sp!, {r0, lr}                       @ Recover lr register (r0 is just there for
+                                                @   the 8-byte stack alignment
+@
+@    }
+@
+__tx_timer_nothing_expired:
+@
+#ifdef __THUMB_INTERWORK
+    BX      lr                                  @ Return to caller
+#else
+    MOV     pc, lr                              @ Return to caller
+#endif
+@
+@}
+
diff --git a/ports/cortex_r4/iar/example_build/azure_rtos.eww b/ports/cortex_r4/iar/example_build/azure_rtos.eww
new file mode 100644
index 00000000..17e0d329
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/azure_rtos.eww
@@ -0,0 +1,13 @@
+
+
+
+  
+    $WS_DIR$\sample_threadx.ewp
+  
+  
+    $WS_DIR$\tx.ewp
+  
+  
+
+
+
diff --git a/ports/cortex_r4/iar/example_build/cstartup.s b/ports/cortex_r4/iar/example_build/cstartup.s
new file mode 100644
index 00000000..7a46bec0
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/cstartup.s
@@ -0,0 +1,163 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Part one of the system initialization code,
+;; contains low-level
+;; initialization.
+;;
+;; Copyright 2007 IAR Systems. All rights reserved.
+;;
+;; $Revision: 49919 $
+;;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION IRQ_STACK:DATA:NOROOT(3)
+        SECTION FIQ_STACK:DATA:NOROOT(3)
+        SECTION CSTACK:DATA:NOROOT(3)
+
+;
+; The module in this file are included in the libraries, and may be
+; replaced by any user-defined modules that define the PUBLIC symbol
+; __iar_program_start or a user defined start symbol.
+;
+; To override the cstartup defined in the library, simply add your
+; modified version to the workbench project.
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        PUBLIC  __vector
+        PUBLIC  __iar_program_start
+        EXTERN  Undefined_Handler
+        EXTERN  SWI_Handler
+        EXTERN  Prefetch_Handler
+        EXTERN  Abort_Handler
+        EXTERN  IRQ_Handler
+        EXTERN  FIQ_Handler
+
+        DATA
+
+__iar_init$$done:               ; The vector table is not needed
+                                ; until after copy initialization is done
+
+__vector:                       ; Make this a DATA label, so that stack usage
+                                ; analysis doesn't consider it an uncalled fun
+
+        ARM
+
+        ; All default exception handlers (except reset) are
+        ; defined as weak symbol definitions.
+        ; If a handler is defined by the application it will take precedence.
+        LDR     PC,Reset_Addr           ; Reset
+        LDR     PC,Undefined_Addr       ; Undefined instructions
+        LDR     PC,SWI_Addr             ; Software interrupt (SWI/SVC)
+        LDR     PC,Prefetch_Addr        ; Prefetch abort
+        LDR     PC,Abort_Addr           ; Data abort
+        DCD     0                       ; RESERVED
+        LDR     PC,IRQ_Addr             ; IRQ
+        LDR     PC,FIQ_Addr             ; FIQ
+
+        DATA
+
+Reset_Addr:     DCD   __iar_program_start
+Undefined_Addr: DCD   Undefined_Handler
+SWI_Addr:       DCD   SWI_Handler
+Prefetch_Addr:  DCD   Prefetch_Handler
+Abort_Addr:     DCD   Abort_Handler
+IRQ_Addr:       DCD   IRQ_Handler
+FIQ_Addr:       DCD   FIQ_Handler
+
+
+; --------------------------------------------------
+; ?cstartup -- low-level system initialization code.
+;
+; After a reset execution starts here, the mode is ARM, supervisor
+; with interrupts disabled.
+;
+
+
+
+        SECTION .text:CODE:NOROOT(2)
+
+        EXTERN  __cmain
+        REQUIRE __vector
+        EXTWEAK __iar_init_core
+        EXTWEAK __iar_init_vfp
+
+
+        ARM
+
+__iar_program_start:
+?cstartup:
+
+;
+; Add initialization needed before setup of stackpointers here.
+;
+
+;
+; Initialize the stack pointers.
+; The pattern below can be used for any of the exception stacks:
+; FIQ, IRQ, SVC, ABT, UND, SYS.
+; The USR mode uses the same stack as SYS.
+; The stack segments must be defined in the linker command file,
+; and be declared above.
+;
+
+
+; --------------------
+; Mode, correspords to bits 0-5 in CPSR
+
+#define MODE_MSK 0x1F            ; Bit mask for mode bits in CPSR
+
+#define USR_MODE 0x10            ; User mode
+#define FIQ_MODE 0x11            ; Fast Interrupt Request mode
+#define IRQ_MODE 0x12            ; Interrupt Request mode
+#define SVC_MODE 0x13            ; Supervisor mode
+#define ABT_MODE 0x17            ; Abort mode
+#define UND_MODE 0x1B            ; Undefined Instruction mode
+#define SYS_MODE 0x1F            ; System mode
+
+        MRS     r0, cpsr                ; Original PSR value
+
+        ;; Set up the interrupt stack pointer.
+
+        BIC     r0, r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0, r0, #IRQ_MODE       ; Set IRQ mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(IRQ_STACK)     ; End of IRQ_STACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+        ;; Set up the fast interrupt stack pointer.
+
+        BIC     r0, r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0, r0, #FIQ_MODE       ; Set FIR mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(FIQ_STACK)     ; End of FIQ_STACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+        ;; Set up the normal stack pointer.
+
+        BIC     r0 ,r0, #MODE_MSK       ; Clear the mode bits
+        ORR     r0 ,r0, #SYS_MODE       ; Set System mode bits
+        MSR     cpsr_c, r0              ; Change the mode
+        LDR     sp, =SFE(CSTACK)        ; End of CSTACK
+        BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
+
+        ;; Turn on core features assumed to be enabled.
+          FUNCALL __iar_program_start, __iar_init_core
+        BL      __iar_init_core
+
+        ;; Initialize VFP (if needed).
+          FUNCALL __iar_program_start, __iar_init_vfp
+        BL      __iar_init_vfp
+
+;;;
+;;; Add more initialization here
+;;;
+
+;;; Continue to __cmain for C-level initialization.
+
+          FUNCALL __iar_program_start, __cmain
+        B       __cmain
+
+        END
diff --git a/ports/cortex_r4/iar/example_build/sample_threadx.c b/ports/cortex_r4/iar/example_build/sample_threadx.c
new file mode 100644
index 00000000..983109cc
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/sample_threadx.c
@@ -0,0 +1,376 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include   "tx_api.h"
+
+#define     DEMO_STACK_SIZE         1024
+#define     DEMO_BYTE_POOL_SIZE     9120
+#define     DEMO_BLOCK_POOL_SIZE    100
+#define     DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+
+/* Define byte pool memory.  */
+
+UCHAR                   byte_pool_memory[DEMO_BYTE_POOL_SIZE];
+
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG           thread_0_counter;
+ULONG           thread_1_counter;
+ULONG           thread_1_messages_sent;
+ULONG           thread_2_counter;
+ULONG           thread_2_messages_received;
+ULONG           thread_3_counter;
+ULONG           thread_4_counter;
+ULONG           thread_5_counter;
+ULONG           thread_6_counter;
+ULONG           thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+/* Define main entry point.  */
+
+int main()
+{
+   
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/cortex_r4/iar/example_build/sample_threadx.dep b/ports/cortex_r4/iar/example_build/sample_threadx.dep
new file mode 100644
index 00000000..6c811ae0
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/sample_threadx.dep
@@ -0,0 +1,253 @@
+
+
+    4
+    1024685290
+    
+        Debug
+        
+            $TOOLKIT_DIR$\inc\c\DLib_Defaults.h
+            $PROJ_DIR$\Debug\Exe\sample_threadx.out
+            $TOOLKIT_DIR$\inc\c\ysizet.h
+            $TOOLKIT_DIR$\inc\c\string.h
+            $PROJ_DIR$\rti.h
+            $TOOLKIT_DIR$\inc\c\ycheck.h
+            $TOOLKIT_DIR$\inc\xencoding_limits.h
+            $PROJ_DIR$\Debug\Obj\rti.__cstat.et
+            $TOOLKIT_DIR$\inc\yvals.h
+            $PROJ_DIR$\Debug\Obj\demo.r79
+            $TOOLKIT_DIR$\lib\sh7Sxs_b.a
+            $PROJ_DIR$\tx_api.h
+            $TOOLKIT_DIR$\inc\DLib_Defaults.h
+            $TOOLKIT_DIR$\inc\c\intrinsics.h
+            $TOOLKIT_DIR$\inc\DLib_Threads.h
+            $PROJ_DIR$\Debug\List\cstartup.lst
+            $TOOLKIT_DIR$\inc\intrinsics.h
+            $PROJ_DIR$\Debug\Obj\rti.o
+            $PROJ_DIR$\tx_port.h
+            $PROJ_DIR$\Debug\Obj\sample_threadx.o
+            $PROJ_DIR$\Debug\List\tx_initialize_low_level.lst
+            $TOOLKIT_DIR$\inc\ysizet.h
+            $TOOLKIT_DIR$\inc\c\stdlib.h
+            $TOOLKIT_DIR$\inc\ycheck.h
+            $PROJ_DIR$\tx_execution_profile.c
+            $TOOLKIT_DIR$\lib\rt7Sx_tb.a
+            $PROJ_DIR$\tx_cstartup.s79
+            $PROJ_DIR$\tx_initialize_low_level.s
+            $PROJ_DIR$\Debug\Obj\cstartup.o
+            $PROJ_DIR$\Debug\Obj\rti.pbi
+            $PROJ_DIR$\Debug\Obj\tx_execution_profile.pbi
+            $PROJ_DIR$\tx_initialize_low_level.s79
+            $PROJ_DIR$\sample_threadx.c
+            $PROJ_DIR$\Debug\Exe\tx.a
+            $PROJ_DIR$\cstartup.s
+            $TOOLKIT_DIR$\inc\c\iccarm_builtin.h
+            $TOOLKIT_DIR$\inc\c\iar_intrinsics_common.h
+            $PROJ_DIR$\..\inc\tx_port.h
+            $PROJ_DIR$\..\..\..\..\common\inc\tx_api.h
+            $PROJ_DIR$\Debug\Obj\tx_cstartup.r79
+            $PROJ_DIR$\sample_threadx.icf
+            $PROJ_DIR$\Debug\Obj\TX_ILL.r79
+            $PROJ_DIR$\Debug\Obj\sample_threadx.pbd
+            $TOOLKIT_DIR$\lib\dl7Sx_tbn.a
+            $PROJ_DIR$\cstartup.s79
+            $TOOLKIT_DIR$\inc\c\DLib_Product.h
+            $PROJ_DIR$\TX_ILL.s79
+            $TOOLKIT_DIR$\inc\c\yvals.h
+            $PROJ_DIR$\Debug\List\sample_threadx.map
+            $TOOLKIT_DIR$\inc\DLib_Config_Normal.h
+            $PROJ_DIR$\Debug\Obj\tx_execution_profile.o
+            $PROJ_DIR$\Debug\Obj\sample_threadx.xcl
+            $PROJ_DIR$\DEMO.C
+            $PROJ_DIR$\rti.c
+            $TOOLKIT_DIR$\inc\string.h
+            $TOOLKIT_DIR$\inc\c\DLib_Product_string.h
+            $TOOLKIT_DIR$\inc\DLib_Product_string.h
+            $TOOLKIT_DIR$\inc\c\DLib_Product_stdlib.h
+            $PROJ_DIR$\Debug\Obj\tx_initialize_low_level.o
+            $TOOLKIT_DIR$\lib\m7Sx_tbv.a
+            $TOOLKIT_DIR$\inc\stdlib.h
+            $TOOLKIT_DIR$\inc\DLib_Product.h
+            $PROJ_DIR$\Debug\Obj\sample_threadx.__cstat.et
+            $TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send.c
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_receive.c
+        
+        
+            [ROOT_NODE]
+            
+                
+                    ILINK
+                     1 48
+                
+            
+        
+        
+            $PROJ_DIR$\Debug\Exe\sample_threadx.out
+            
+                
+                    ILINK
+                     48
+                
+            
+            
+                
+                    ILINK
+                     40 28 19 33 58 10 25 59 43
+                
+            
+        
+        
+            $PROJ_DIR$\tx_execution_profile.c
+            
+                
+                    ICCARM
+                     50
+                
+                
+                    BICOMP
+                     30
+                
+            
+            
+                
+                    ICCARM
+                     11 18 60 23 8 12 49 61 6 14 21 54 56 16
+                
+                
+                    BICOMP
+                     11 18 60 23 8 12 61 6 14 21 54 56 16
+                
+            
+        
+        
+            $PROJ_DIR$\tx_cstartup.s79
+            
+                
+                    AARM
+                     39
+                
+            
+        
+        
+            $PROJ_DIR$\tx_initialize_low_level.s
+            
+                
+                    AARM
+                     58 20
+                
+            
+        
+        
+            $PROJ_DIR$\tx_initialize_low_level.s79
+            
+                
+                    AARM
+                     58 20
+                
+            
+        
+        
+            $PROJ_DIR$\sample_threadx.c
+            
+                
+                    ICCARM
+                     19
+                
+                
+                    BICOMP
+                     51
+                
+                
+                    __cstat
+                     62
+                
+            
+            
+                
+                    ICCARM
+                     38 37 22 5 47 0 63 45 2 57 3 55 13 35 36
+                
+            
+        
+        
+            $PROJ_DIR$\cstartup.s
+            
+                
+                    AARM
+                     28 15
+                
+            
+        
+        
+            $PROJ_DIR$\cstartup.s79
+            
+                
+                    AARM
+                     28
+                
+            
+        
+        
+            $PROJ_DIR$\TX_ILL.s79
+            
+                
+                    AARM
+                     41
+                
+            
+        
+        
+            $PROJ_DIR$\DEMO.C
+            
+                
+                    ICCARM
+                     9
+                
+            
+            
+                
+                    ICCARM
+                     11 18
+                
+            
+        
+        
+            $PROJ_DIR$\rti.c
+            
+                
+                    ICCARM
+                     17
+                
+                
+                    BICOMP
+                     29
+                
+                
+                    __cstat
+                     7
+                
+            
+            
+                
+                    ICCARM
+                     4
+                
+                
+                    BICOMP
+                     4
+                
+            
+        
+    
+    
+        Release
+        
+        
+            [MULTI_TOOL]
+            ILINK
+        
+        
+            [REBUILD_ALL]
+        
+    
+
diff --git a/ports/cortex_r4/iar/example_build/sample_threadx.ewd b/ports/cortex_r4/iar/example_build/sample_threadx.ewd
new file mode 100644
index 00000000..28a9ad4c
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/sample_threadx.ewd
@@ -0,0 +1,2974 @@
+
+
+    3
+    
+        Debug
+        
+            ARM
+        
+        1
+        
+            C-SPY
+            2
+            
+                32
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+        
+            ARMSIM_ID
+            2
+            
+                1
+                1
+                1
+                
+                
+                
+                
+            
+        
+        
+            CADI_ID
+            2
+            
+                0
+                1
+                1
+                
+                
+                
+                
+                
+            
+        
+        
+            CMSISDAP_ID
+            2
+            
+                4
+                1
+                1
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
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diff --git a/ports/cortex_r4/iar/example_build/sample_threadx.ewp b/ports/cortex_r4/iar/example_build/sample_threadx.ewp
new file mode 100644
index 00000000..7557efe5
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/sample_threadx.ewp
@@ -0,0 +1,2140 @@
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+            $PROJ_DIR$\sample_threadx.c
+        
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+            $PROJ_DIR$\Debug\Exe\tx.a
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+            $PROJ_DIR$\tx_initialize_low_level.s
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diff --git a/ports/cortex_r4/iar/example_build/sample_threadx.ewt b/ports/cortex_r4/iar/example_build/sample_threadx.ewt
new file mode 100644
index 00000000..77fe620f
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/sample_threadx.ewt
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+                    
+                
+            
+        
+        
+            RuntimeChecking
+            0
+            
+                2
+                1
+                0
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+                
+            
+        
+    
+    
+        Common sources
+        
+            $PROJ_DIR$\cstartup.s
+        
+        
+            $PROJ_DIR$\sample_threadx.c
+        
+        
+            $PROJ_DIR$\Debug\Exe\tx.a
+        
+        
+            $PROJ_DIR$\tx_initialize_low_level.s
+        
+    
+
diff --git a/ports/cortex_r4/iar/example_build/sample_threadx.icf b/ports/cortex_r4/iar/example_build/sample_threadx.icf
new file mode 100644
index 00000000..13723763
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/sample_threadx.icf
@@ -0,0 +1,49 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__       = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x00000040;
+define symbol __ICFEDIT_region_ROM_end__     = 0x0013FFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x08000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x0802FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x200;
+define symbol __ICFEDIT_size_svcstack__ = 0x100;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x100;
+define symbol __ICFEDIT_size_undstack__ = 0x100;
+define symbol __ICFEDIT_size_abtstack__ = 0x100;
+define symbol __ICFEDIT_size_heap__     = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define symbol __region_DRAM_start__   = 0x80000000;
+define symbol __region_DRAM_end__     = 0x807FFFFF;
+define region DRAM_region  = mem:[from __region_DRAM_start__   to __region_DRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+                        block UND_STACK, block ABT_STACK, block HEAP};
+place in DRAM_region  { section DRAM };
+
+place in RAM_region { last section FREE_MEM};
\ No newline at end of file
diff --git a/ports/cortex_r4/iar/example_build/settings/azure_rtos.wsdt b/ports/cortex_r4/iar/example_build/settings/azure_rtos.wsdt
new file mode 100644
index 00000000..d635fcef
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/azure_rtos.wsdt
@@ -0,0 +1,535 @@
+
+
+    
+        
+            sample_threadx/Debug
+            tx/Debug
+        
+        sample_threadx
+        1
+    
+    
+        
+            
+                21
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+            
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+                0400048400004C000000068400004E0000000B8100001B0000000D8100001D000000
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diff --git a/ports/cortex_r4/iar/example_build/settings/sample_threadx.Debug.cspy.bat b/ports/cortex_r4/iar/example_build/settings/sample_threadx.Debug.cspy.bat
new file mode 100644
index 00000000..2c5210a4
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/sample_threadx.Debug.cspy.bat
@@ -0,0 +1,40 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+@echo off 
+
+if not "%~1" == "" goto debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r4\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r4\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r4\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r4\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+
+@echo off 
+:end
\ No newline at end of file
diff --git a/ports/cortex_r4/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports/cortex_r4/iar/example_build/settings/sample_threadx.Debug.cspy.ps1
new file mode 100644
index 00000000..1abcd287
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/sample_threadx.Debug.cspy.ps1
@@ -0,0 +1,31 @@
+param([String]$debugfile = "");
+
+# This powershell file has been generated by the IAR Embedded Workbench
+# C - SPY Debugger, as an aid to preparing a command line for running
+# the cspybat command line utility using the appropriate settings.
+#
+# Note that this file is generated every time a new debug session
+# is initialized, so you may want to move or rename the file before
+# making changes.
+#
+# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
+# by the name of the debug file (usually an ELF / DWARF or UBROF file).
+#
+# Read about available command line parameters in the C - SPY Debugging
+# Guide. Hints about additional command line parameters that may be
+# useful in specific cases :
+#   --download_only   Downloads a code image without starting a debug
+#                     session afterwards.
+#   --silent          Omits the sign - on message.
+#   --timeout         Limits the maximum allowed execution time.
+#
+
+
+if ($debugfile -eq "")
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r4\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r4\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+}
+else
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r4\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r4\iar\example_build\settings\sample_threadx.Debug.driver.xcl" 
+}
diff --git a/ports/cortex_r4/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports/cortex_r4/iar/example_build/settings/sample_threadx.Debug.driver.xcl
new file mode 100644
index 00000000..529ac91f
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/sample_threadx.Debug.driver.xcl
@@ -0,0 +1,15 @@
+"--endian=big" 
+
+"--cpu=Cortex-R4" 
+
+"--fpu=VFPv3" 
+
+"--semihosting" 
+
+"--BE32" 
+
+"--multicore_nr_of_cores=1" 
+
+
+
+
diff --git a/ports/cortex_r4/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports/cortex_r4/iar/example_build/settings/sample_threadx.Debug.general.xcl
new file mode 100644
index 00000000..9ea83d29
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/sample_threadx.Debug.general.xcl
@@ -0,0 +1,11 @@
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" 
+
+"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_r4\iar\example_build\Debug\Exe\sample_threadx.out" 
+
+--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" 
+
+
+
+
diff --git a/ports/cortex_r4/iar/example_build/settings/sample_threadx.crun b/ports/cortex_r4/iar/example_build/settings/sample_threadx.crun
new file mode 100644
index 00000000..d71ea555
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/sample_threadx.crun
@@ -0,0 +1,13 @@
+
+
+    1
+    
+        
+            *
+            *
+            *
+            0
+            1
+        
+    
+
diff --git a/ports/cortex_r4/iar/example_build/settings/sample_threadx.dbgdt b/ports/cortex_r4/iar/example_build/settings/sample_threadx.dbgdt
new file mode 100644
index 00000000..87de74d4
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/sample_threadx.dbgdt
@@ -0,0 +1,1797 @@
+
+
+    
+        
+            
+                
+                    447
+                    27
+                    27
+                    2010398909
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+                    thread_5_counter
+                    thread_6_counter
+                    thread_7_counter
+                    
+                
+                
+                    Expression
+                    Location
+                    Type
+                    Value
+                
+                
+                    161
+                    150
+                    100
+                    100
+                
+            
+        
+        
+            
+                
+                    
+                        TabID-32281-8114
+                        Workspace
+                        Workspace
+                        
+                            
+                                <ws>
+                                <ws>/sample_threadx
+                                <ws>/sample_threadx/Common sources
+                                <ws>/sample_threadx/Common sources/tx_cstartup.s79
+                                sample_threadx
+                                sample_threadx/Output
+                                sample_threadx/Output/sample_threadx.out
+                                sample_threadx/Output/sample_threadx.out/Output
+                            
+                        
+                    
+                
+                0
+            
+            
+                
+                    
+                        TabID-31758-8124
+                        Debug Log
+                        Debug-Log
+                        
+                    
+                    
+                        TabID-9738-8128
+                        Build
+                        Build
+                        
+                    
+                    
+                        TabID-20156-25745
+                        Breakpoints
+                        Breakpoints
+                    
+                
+                0
+            
+            
+                
+                    
+                        TabID-19697-5905
+                        Thread List
+                        TX-THREAD
+                        
+                            1
+                        
+                    
+                    
+                        TabID-19175-5914
+                        Message Queues
+                        TX-MESSAGEQUEUE
+                    
+                    
+                        TabID-29400-5927
+                        Semaphores
+                        TX-SEMAPHORE
+                    
+                    
+                        TabID-6858-5940
+                        Mutexes
+                        TX-MUTEX
+                    
+                    
+                        TabID-6335-5950
+                        Byte Pools
+                        TX-BYTEPOOL
+                    
+                    
+                        TabID-16561-5963
+                        Block Pools
+                        TX-BLOCKPOOL
+                    
+                    
+                        TabID-26786-5976
+                        Timers
+                        TX-TIMER
+                    
+                    
+                        TabID-26264-5986
+                        Event Flag Groups
+                        TX-EVENTFLAG
+                    
+                
+                0
+            
+            
+                
+                    
+                        TabID-4531-19825
+                        Watch 1
+                        WATCH_1
+                    
+                
+                0
+            
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+        
+            
+                
+                    TextEditor
+                    $WS_DIR$\sample_threadx.c
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+                    
+                        
+                            iaridepm.enu1
+                        
+                    
+                
+                
+                    
+                        
+                            debuggergui.enu1
+                        
+                    
+                
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+                        
+                            threadxarmplugin.enu1
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+                    _I0
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diff --git a/ports/cortex_r4/iar/example_build/settings/sample_threadx.dnx b/ports/cortex_r4/iar/example_build/settings/sample_threadx.dnx
new file mode 100644
index 00000000..a6623ee1
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/sample_threadx.dnx
@@ -0,0 +1,130 @@
+
+
+    
+        0
+        1
+        90
+        1
+        1
+        1
+        main
+        0
+        50
+    
+    
+        0
+        1
+    
+    
+        2137572426
+    
+    
+        0
+    
+    
+        HL512000
+        
+        0
+        2
+        _ 0
+        _ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+        _ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+        _ 0
+        _ 0
+    
+    
+        _ 0
+        _ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+        _ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
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+        1
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+        _ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
+        _ 0 "" 0 "" 0 "" 0 "" 0 0 0 0
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+        _ 0
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+        0
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+    
+    
+        0
+    
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+        1
+        _ 0 9999 0 9999 1 0 0 100 0 1 "IRQ 1 0x18 CPSR.I"
+        1
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+        1
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+
diff --git a/ports/cortex_r4/iar/example_build/settings/sample_threadx.reggroups b/ports/cortex_r4/iar/example_build/settings/sample_threadx.reggroups
new file mode 100644
index 00000000..5f282702
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/sample_threadx.reggroups
@@ -0,0 +1 @@
+
\ No newline at end of file
diff --git a/ports/cortex_r4/iar/example_build/settings/sample_threadx_Debug_xds100board.dat b/ports/cortex_r4/iar/example_build/settings/sample_threadx_Debug_xds100board.dat
new file mode 100644
index 00000000..192ce771
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/sample_threadx_Debug_xds100board.dat
@@ -0,0 +1,32 @@
+# config version=3.5
+$ sepk
+  pod_drvr=jioxds110.dll
+  pod_port=0
+  pod_serial=HL512000
+$ /
+$ product
+  title="Texas Instruments XDS110 USB"
+  alias=TI_XDS110_USB
+  name=XDS110
+$ /
+$ uscif
+  tdoedge=FALL
+  tclk_program=DEFAULT
+  tclk_frequency=2.5MHz
+$ /
+$ dot7
+  dts_usage=nothing
+$ /
+$ swd
+  swd_debug=disabled
+  swo_data=aux_uart
+$ /
+@ icepick family=icepick_c irbits=6 drbits=1 subpaths=2
+  & port17 address=17 default=no custom=no force=yes pseudo=no
+  & port16 address=16 default=no custom=no force=yes pseudo=no
+    @ dap family=cs_dap irbits=4 drbits=1 subpaths=1 identify=0
+      & portr4 type=debug address=0 default=no custom=no force=no pseudo=no
+        @ cortexr4 family=cortex_rxx irbits=0 drbits=0 address=0x80001000 identify=0x02000100 traceid=0x0
+      & /
+  & /
+# /
diff --git a/ports/cortex_r4/iar/example_build/settings/tx.Debug.cspy.bat b/ports/cortex_r4/iar/example_build/settings/tx.Debug.cspy.bat
new file mode 100644
index 00000000..d76cfad9
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/tx.Debug.cspy.bat
@@ -0,0 +1,40 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+@echo off 
+
+if not "%~1" == "" goto debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+
+@echo off 
+:end
\ No newline at end of file
diff --git a/ports/cortex_r4/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports/cortex_r4/iar/example_build/settings/tx.Debug.cspy.ps1
new file mode 100644
index 00000000..1c1ba13b
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/tx.Debug.cspy.ps1
@@ -0,0 +1,31 @@
+param([String]$debugfile = "");
+
+# This powershell file has been generated by the IAR Embedded Workbench
+# C - SPY Debugger, as an aid to preparing a command line for running
+# the cspybat command line utility using the appropriate settings.
+#
+# Note that this file is generated every time a new debug session
+# is initialized, so you may want to move or rename the file before
+# making changes.
+#
+# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
+# by the name of the debug file (usually an ELF / DWARF or UBROF file).
+#
+# Read about available command line parameters in the C - SPY Debugging
+# Guide. Hints about additional command line parameters that may be
+# useful in specific cases :
+#   --download_only   Downloads a code image without starting a debug
+#                     session afterwards.
+#   --silent          Omits the sign - on message.
+#   --timeout         Limits the maximum allowed execution time.
+#
+
+
+if ($debugfile -eq "")
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+}
+else
+{
+& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" 
+}
diff --git a/ports/cortex_r4/iar/example_build/settings/tx.Debug.driver.xcl b/ports/cortex_r4/iar/example_build/settings/tx.Debug.driver.xcl
new file mode 100644
index 00000000..529ac91f
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/tx.Debug.driver.xcl
@@ -0,0 +1,15 @@
+"--endian=big" 
+
+"--cpu=Cortex-R4" 
+
+"--fpu=VFPv3" 
+
+"--semihosting" 
+
+"--BE32" 
+
+"--multicore_nr_of_cores=1" 
+
+
+
+
diff --git a/ports/cortex_r4/iar/example_build/settings/tx.Debug.general.xcl b/ports/cortex_r4/iar/example_build/settings/tx.Debug.general.xcl
new file mode 100644
index 00000000..ef6d6dd5
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/tx.Debug.general.xcl
@@ -0,0 +1,11 @@
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armproc.dll" 
+
+"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armsim2.dll" 
+
+"C:\release\threadx\Debug\Exe\tx.out" 
+
+--plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armbat.dll" 
+
+
+
+
diff --git a/ports/cortex_r4/iar/example_build/settings/tx.crun b/ports/cortex_r4/iar/example_build/settings/tx.crun
new file mode 100644
index 00000000..d71ea555
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/tx.crun
@@ -0,0 +1,13 @@
+
+
+    1
+    
+        
+            *
+            *
+            *
+            0
+            1
+        
+    
+
diff --git a/ports/cortex_r4/iar/example_build/settings/tx.dbgdt b/ports/cortex_r4/iar/example_build/settings/tx.dbgdt
new file mode 100644
index 00000000..9e08d965
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/tx.dbgdt
@@ -0,0 +1,4 @@
+
+
+    
+
diff --git a/ports/cortex_r4/iar/example_build/settings/tx.dnx b/ports/cortex_r4/iar/example_build/settings/tx.dnx
new file mode 100644
index 00000000..25e4c4ba
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/settings/tx.dnx
@@ -0,0 +1,58 @@
+
+
+    
+        0
+        1
+        90
+        1
+        1
+        1
+        main
+        0
+        50
+    
+    
+        0
+        1
+    
+    
+        0
+        0
+        1
+        0
+        1
+        0
+    
+    
+        0
+        0
+        1
+        0
+        1
+    
+    
+        0
+    
+    
+        0
+    
+    
+        1
+    
+    
+        1
+        0
+        1
+        0
+        1
+    
+    
+        0
+        0
+    
+    
+        10000000
+        0
+        1
+    
+
diff --git a/ports/cortex_r4/iar/example_build/tx.dep b/ports/cortex_r4/iar/example_build/tx.dep
new file mode 100644
index 00000000..09806296
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/tx.dep
@@ -0,0 +1,10488 @@
+
+
+    4
+    554479155
+    
+        Debug
+        
+            $PROJ_DIR$\..\inc\tx_port.h
+            $PROJ_DIR$\Debug\Obj\tx_timer_performance_system_info_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_thread_fiq_context_restore.o
+            $PROJ_DIR$\Txe_bytp.c
+            $PROJ_DIR$\Debug\Obj\tx_time_get.pbi
+            $PROJ_DIR$\Txe_bytr.c
+            $PROJ_DIR$\Debug\Obj\tx_initialize_high_level.pbi
+            $PROJ_DIR$\Debug\Obj\tx_thread_wait_abort.pbi
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_create.pbi
+            $PROJ_DIR$\Debug\Obj\tx_timer_delete.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_thread_time_slice_change.o
+            $PROJ_DIR$\Debug\Obj\tx_timer_info_get.__cstat.et
+            $PROJ_DIR$\Tx_tts.c
+            $PROJ_DIR$\Debug\Obj\tx_timer_expiration_process.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_block_release.o
+            $PROJ_DIR$\Debug\Obj\txe_semaphore_ceiling_put.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_get.pbi
+            $PROJ_DIR$\Tx_qi.c
+            $PROJ_DIR$\Debug\Obj\tx.pbd
+            $PROJ_DIR$\Debug\Obj\tx_trace_isr_enter_insert.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_block_pool_create.o
+            $PROJ_DIR$\Debug\Obj\tx_block_release.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_time_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_mutex_create.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_queue_receive.o
+            $PROJ_DIR$\Txe_sig.c
+            $PROJ_DIR$\Debug\Obj\txe_semaphore_prioritize.pbi
+            $PROJ_DIR$\Debug\Obj\tx_queue_prioritize.pbi
+            $PROJ_DIR$\Debug\Obj\tx_mutex_priority_change.__cstat.et
+            $PROJ_DIR$\Tx_efg.c
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_set_notify.__cstat.et
+            $PROJ_DIR$\Tx_ike.c
+            $PROJ_DIR$\Debug\Obj\tx_trace_initialize.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_delete.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_byte_pool_info_get.o
+            $PROJ_DIR$\Debug\Obj\txe_queue_send_notify.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_timer_system_activate.pbi
+            $PROJ_DIR$\Txe_efig.c
+            $PROJ_DIR$\Debug\Obj\tx_thread_shell_entry.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_semaphore_cleanup.pbi
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\tx_byte_pool_initialize.pbi
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_delete.o
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_cleanup.pbi
+            $PROJ_DIR$\Tx_tprch.c
+            $PROJ_DIR$\Debug\Obj\tx_semaphore_put.pbi
+            $PROJ_DIR$\Debug\Obj\tx_event_flags_delete.pbi
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_set.o
+            $PROJ_DIR$\Debug\Obj\txe_semaphore_create.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_thread_wait_abort.pbi
+            $PROJ_DIR$\Debug\Obj\tx_trace_isr_exit_insert.pbi
+            $PROJ_DIR$\Debug\Obj\txe_thread_info_get.o
+            $PROJ_DIR$\Debug\Obj\txe_queue_delete.o
+            $PROJ_DIR$\Debug\Obj\txe_mutex_delete.pbi
+            $PROJ_DIR$\Debug\Obj\tx_thread_resume.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_timer_create.pbi
+            $PROJ_DIR$\Tx_bytc.c
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_delete.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_queue_send_notify.o
+            $PROJ_DIR$\Debug\Obj\tx_trace_disable.__cstat.et
+            $PROJ_DIR$\Tx_mut.h
+            $PROJ_DIR$\Txe_ba.c
+            $PROJ_DIR$\Debug\Obj\txe_thread_wait_abort.__cstat.et
+            $PROJ_DIR$\tx_api.h
+            $PROJ_DIR$\tx_block_pool.h
+            $PROJ_DIR$\tx_block_allocate.c
+            $PROJ_DIR$\tx_block_pool_cleanup.c
+            $PROJ_DIR$\tx_event_flags_set.c
+            $PROJ_DIR$\tx_block_pool_info_get.c
+            $PROJ_DIR$\tx_byte_pool_cleanup.c
+            $PROJ_DIR$\tx_byte_pool_create.c
+            $PROJ_DIR$\tx_byte_pool_performance_info_get.c
+            $PROJ_DIR$\tx_byte_pool_initialize.c
+            $PROJ_DIR$\tx_byte_pool_delete.c
+            $PROJ_DIR$\tx_byte_release.c
+            $PROJ_DIR$\tx_byte_pool_info_get.c
+            $PROJ_DIR$\tx_event_flags_cleanup.c
+            $PROJ_DIR$\tx_block_pool_performance_info_get.c
+            $PROJ_DIR$\tx_block_pool_create.c
+            $PROJ_DIR$\tx_byte_pool_performance_system_info_get.c
+            $PROJ_DIR$\tx_byte_pool.h
+            $PROJ_DIR$\tx_byte_pool_prioritize.c
+            $PROJ_DIR$\tx_block_release.c
+            $PROJ_DIR$\tx_event_flags.h
+            $PROJ_DIR$\tx_block_pool_delete.c
+            $PROJ_DIR$\tx_byte_allocate.c
+            $PROJ_DIR$\tx_block_pool_prioritize.c
+            $PROJ_DIR$\tx_event_flags_create.c
+            $PROJ_DIR$\tx_event_flags_delete.c
+            $PROJ_DIR$\tx_event_flags_get.c
+            $PROJ_DIR$\tx_event_flags_info_get.c
+            $PROJ_DIR$\tx_event_flags_performance_info_get.c
+            $PROJ_DIR$\tx_block_pool_initialize.c
+            $PROJ_DIR$\tx_event_flags_performance_system_info_get.c
+            $PROJ_DIR$\tx_block_pool_performance_system_info_get.c
+            $PROJ_DIR$\tx_event_flags_set_notify.c
+            $PROJ_DIR$\tx_byte_pool_search.c
+            $PROJ_DIR$\tx_event_flags_initialize.c
+            $PROJ_DIR$\tx_thread_delete.c
+            $PROJ_DIR$\tx_thread_interrupt_control.s
+            $PROJ_DIR$\tx_thread_interrupt_disable.s
+            $PROJ_DIR$\tx_semaphore_ceiling_put.c
+            $PROJ_DIR$\tx_thread_context_restore.s
+            $PROJ_DIR$\tx_thread_interrupt_restore.s
+            $PROJ_DIR$\tx_thread_irq_nesting_end.s
+            $PROJ_DIR$\tx_thread_irq_nesting_start.s
+            $PROJ_DIR$\tx_semaphore_prioritize.c
+            $PROJ_DIR$\tx_thread_performance_info_get.c
+            $PROJ_DIR$\tx_thread_performance_system_info_get.c
+            $PROJ_DIR$\tx_thread_identify.c
+            $PROJ_DIR$\tx_semaphore_performance_info_get.c
+            $PROJ_DIR$\tx_thread_preemption_change.c
+            $PROJ_DIR$\tx_thread_priority_change.c
+            $PROJ_DIR$\tx_semaphore_performance_system_info_get.c
+            $PROJ_DIR$\tx_queue_send_notify.c
+            $PROJ_DIR$\tx_semaphore_create.c
+            $PROJ_DIR$\tx_semaphore_delete.c
+            $PROJ_DIR$\tx_semaphore_get.c
+            $PROJ_DIR$\tx_semaphore_initialize.c
+            $PROJ_DIR$\tx_thread.h
+            $PROJ_DIR$\tx_semaphore.h
+            $PROJ_DIR$\tx_semaphore_put_notify.c
+            $PROJ_DIR$\tx_thread_create.c
+            $PROJ_DIR$\tx_semaphore_info_get.c
+            $PROJ_DIR$\tx_thread_initialize.c
+            $PROJ_DIR$\tx_semaphore_cleanup.c
+            $PROJ_DIR$\tx_semaphore_put.c
+            $PROJ_DIR$\tx_thread_context_save.s
+            $PROJ_DIR$\tx_thread_info_get.c
+            $PROJ_DIR$\tx_thread_entry_exit_notify.c
+            $PROJ_DIR$\tx_queue.h
+            $PROJ_DIR$\tx_queue_performance_info_get.c
+            $PROJ_DIR$\tx_mutex_info_get.c
+            $PROJ_DIR$\tx_queue_performance_system_info_get.c
+            $PROJ_DIR$\tx_queue_send.c
+            $PROJ_DIR$\tx_initialize.h
+            $PROJ_DIR$\tx_initialize_high_level.c
+            $PROJ_DIR$\tx_mutex.h
+            $PROJ_DIR$\tx_initialize_kernel_setup.c
+            $PROJ_DIR$\tx_mutex_delete.c
+            $PROJ_DIR$\tx_mutex_get.c
+            $PROJ_DIR$\tx_mutex_cleanup.c
+            $PROJ_DIR$\tx_mutex_prioritize.c
+            $PROJ_DIR$\tx_initialize_kernel_enter.c
+            $PROJ_DIR$\tx_mutex_priority_change.c
+            $PROJ_DIR$\tx_iar.c
+            $PROJ_DIR$\tx_mutex_performance_info_get.c
+            $PROJ_DIR$\tx_mutex_put.c
+            $PROJ_DIR$\tx_queue_create.c
+            $PROJ_DIR$\tx_mutex_performance_system_info_get.c
+            $PROJ_DIR$\tx_queue_front_send.c
+            $PROJ_DIR$\tx_queue_initialize.c
+            $PROJ_DIR$\tx_queue_receive.c
+            $PROJ_DIR$\tx_queue_info_get.c
+            $PROJ_DIR$\tx_mutex_initialize.c
+            $PROJ_DIR$\tx_mutex_create.c
+            $PROJ_DIR$\tx_port.h
+            $PROJ_DIR$\tx_queue_cleanup.c
+            $PROJ_DIR$\tx_queue_delete.c
+            $PROJ_DIR$\tx_queue_flush.c
+            $PROJ_DIR$\tx_queue_prioritize.c
+            $PROJ_DIR$\tx_thread_wait_abort.c
+            $PROJ_DIR$\tx_timer_activate.c
+            $PROJ_DIR$\tx_timer_change.c
+            $PROJ_DIR$\tx_thread_system_suspend.c
+            $PROJ_DIR$\tx_timer_delete.c
+            $PROJ_DIR$\tx_timer_expiration_process.c
+            $PROJ_DIR$\tx_timer_info_get.c
+            $PROJ_DIR$\tx_timer_create.c
+            $PROJ_DIR$\tx_timer_initialize.c
+            $PROJ_DIR$\tx_time_set.c
+            $PROJ_DIR$\tx_thread_terminate.c
+            $PROJ_DIR$\tx_thread_stack_error_handler.c
+            $PROJ_DIR$\tx_timer_deactivate.c
+            $PROJ_DIR$\tx_thread_resume.c
+            $PROJ_DIR$\tx_thread_relinquish.c
+            $PROJ_DIR$\tx_thread_system_preempt_check.c
+            $PROJ_DIR$\tx_thread_stack_build.s
+            $PROJ_DIR$\tx_time_get.c
+            $PROJ_DIR$\tx_thread_time_slice.c
+            $PROJ_DIR$\tx_timer.h
+            $PROJ_DIR$\tx_thread_system_return.s
+            $PROJ_DIR$\tx_thread_reset.c
+            $PROJ_DIR$\tx_thread_sleep.c
+            $PROJ_DIR$\tx_thread_stack_analyze.c
+            $PROJ_DIR$\tx_thread_shell_entry.c
+            $PROJ_DIR$\tx_thread_stack_error_notify.c
+            $PROJ_DIR$\tx_thread_suspend.c
+            $PROJ_DIR$\tx_thread_system_resume.c
+            $PROJ_DIR$\tx_thread_time_slice_change.c
+            $PROJ_DIR$\tx_thread_timeout.c
+            $PROJ_DIR$\tx_thread_schedule.s
+            $PROJ_DIR$\tx_thread_vectored_context_save.s
+            $PROJ_DIR$\tx_trace_isr_enter_insert.c
+            $PROJ_DIR$\tx_trace_object_register.c
+            $PROJ_DIR$\tx_timer_system_activate.c
+            $PROJ_DIR$\tx_trace_object_unregister.c
+            $PROJ_DIR$\tx_trace_isr_exit_insert.c
+            $PROJ_DIR$\txe_block_allocate.c
+            $PROJ_DIR$\tx_user.h
+            $PROJ_DIR$\txe_block_pool_delete.c
+            $PROJ_DIR$\txe_block_pool_info_get.c
+            $PROJ_DIR$\tx_timer_thread_entry.c
+            $PROJ_DIR$\tx_trace_buffer_full_notify.c
+            $PROJ_DIR$\tx_timer_performance_system_info_get.c
+            $PROJ_DIR$\tx_trace_event_filter.c
+            $PROJ_DIR$\tx_trace_user_event_insert.c
+            $PROJ_DIR$\txe_block_pool_prioritize.c
+            $PROJ_DIR$\tx_trace_initialize.c
+            $PROJ_DIR$\txe_block_release.c
+            $PROJ_DIR$\txe_byte_pool_create.c
+            $PROJ_DIR$\txe_byte_pool_info_get.c
+            $PROJ_DIR$\txe_byte_pool_prioritize.c
+            $PROJ_DIR$\txe_byte_allocate.c
+            $PROJ_DIR$\txe_byte_pool_delete.c
+            $PROJ_DIR$\txe_block_pool_create.c
+            $PROJ_DIR$\tx_trace.h
+            $PROJ_DIR$\tx_trace_disable.c
+            $PROJ_DIR$\tx_timer_interrupt.s
+            $PROJ_DIR$\tx_trace_event_unfilter.c
+            $PROJ_DIR$\tx_trace_interrupt_control.c
+            $PROJ_DIR$\tx_trace_enable.c
+            $PROJ_DIR$\tx_timer_system_deactivate.c
+            $PROJ_DIR$\tx_timer_performance_info_get.c
+            $PROJ_DIR$\txe_semaphore_info_get.c
+            $PROJ_DIR$\txe_semaphore_prioritize.c
+            $PROJ_DIR$\txe_semaphore_put.c
+            $PROJ_DIR$\txe_semaphore_delete.c
+            $PROJ_DIR$\txe_semaphore_put_notify.c
+            $PROJ_DIR$\txe_mutex_create.c
+            $PROJ_DIR$\txe_queue_flush.c
+            $PROJ_DIR$\txe_thread_create.c
+            $PROJ_DIR$\txe_thread_delete.c
+            $PROJ_DIR$\txe_mutex_prioritize.c
+            $PROJ_DIR$\txe_queue_info_get.c
+            $PROJ_DIR$\txe_event_flags_create.c
+            $PROJ_DIR$\txe_mutex_put.c
+            $PROJ_DIR$\txe_event_flags_delete.c
+            $PROJ_DIR$\txe_queue_send.c
+            $PROJ_DIR$\txe_semaphore_create.c
+            $PROJ_DIR$\txe_event_flags_get.c
+            $PROJ_DIR$\txe_event_flags_info_get.c
+            $PROJ_DIR$\txe_queue_create.c
+            $PROJ_DIR$\txe_mutex_get.c
+            $PROJ_DIR$\txe_semaphore_get.c
+            $PROJ_DIR$\txe_semaphore_ceiling_put.c
+            $PROJ_DIR$\txe_byte_release.c
+            $PROJ_DIR$\txe_event_flags_set_notify.c
+            $PROJ_DIR$\txe_mutex_delete.c
+            $PROJ_DIR$\txe_mutex_info_get.c
+            $PROJ_DIR$\txe_event_flags_set.c
+            $PROJ_DIR$\txe_queue_delete.c
+            $PROJ_DIR$\txe_queue_front_send.c
+            $PROJ_DIR$\txe_queue_prioritize.c
+            $PROJ_DIR$\txe_queue_receive.c
+            $PROJ_DIR$\txe_queue_send_notify.c
+            $PROJ_DIR$\txe_timer_delete.c
+            $PROJ_DIR$\txe_thread_terminate.c
+            $PROJ_DIR$\txe_thread_priority_change.c
+            $PROJ_DIR$\txe_thread_relinquish.c
+            $PROJ_DIR$\txe_thread_wait_abort.c
+            $PROJ_DIR$\txe_timer_deactivate.c
+            $PROJ_DIR$\Debug\Obj\tx_thread_fiq_nesting_start.o
+            $PROJ_DIR$\Debug\Obj\txe_queue_receive.__cstat.et
+            $PROJ_DIR$\txe_thread_preemption_change.c
+            $PROJ_DIR$\txe_thread_entry_exit_notify.c
+            $PROJ_DIR$\Debug\Obj\tx_trace_buffer_full_notify.__cstat.et
+            $PROJ_DIR$\txe_timer_create.c
+            $PROJ_DIR$\txe_thread_info_get.c
+            $PROJ_DIR$\txe_timer_info_get.c
+            $PROJ_DIR$\Debug\Obj\txe_block_pool_info_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_time_set.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_queue_send_notify.o
+            $TOOLKIT_DIR$\inc\c\stdlib.h
+            $PROJ_DIR$\Debug\Obj\tx_semaphore_initialize.o
+            $PROJ_DIR$\Debug\Obj\tx_thread_terminate.o
+            $PROJ_DIR$\txe_thread_suspend.c
+            $PROJ_DIR$\Debug\Obj\txe_byte_pool_info_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\tx_queue_flush.pbi
+            $PROJ_DIR$\Debug\Obj\tx_block_pool_info_get.pbi
+            $PROJ_DIR$\Debug\Obj\txe_byte_release.__cstat.et
+            $PROJ_DIR$\Tx_bpi.c
+            $PROJ_DIR$\txe_thread_resume.c
+            $PROJ_DIR$\txe_thread_time_slice_change.c
+            $PROJ_DIR$\txe_timer_activate.c
+            $PROJ_DIR$\txe_thread_reset.c
+            $PROJ_DIR$\txe_timer_change.c
+            $PROJ_DIR$\Debug\Obj\tx_block_pool_prioritize.__cstat.et
+            $PROJ_DIR$\Tx_twa.c
+            $PROJ_DIR$\Debug\Obj\tx_timer_performance_info_get.__cstat.et
+            $PROJ_DIR$\Debug\Obj\txe_block_release.o
+            $PROJ_DIR$\Debug\Obj\txe_event_flags_create.o
+            $TOOLKIT_DIR$\inc\c\DLib_Threads.h
+            $PROJ_DIR$\Debug\Obj\txe_thread_delete.pbi
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c
+        
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c
+        
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c
+        
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+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c
+        
+    
+
diff --git a/ports/cortex_r4/iar/example_build/tx.ewt b/ports/cortex_r4/iar/example_build/tx.ewt
new file mode 100644
index 00000000..016f76bc
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/tx.ewt
@@ -0,0 +1,3415 @@
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+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_semaphore_put_notify.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_context_restore.s
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_context_save.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_entry_exit_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_identify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_initialize.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_interrupt_control.s
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_interrupt_disable.s
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_interrupt_restore.s
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_irq_nesting_end.s
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_irq_nesting_start.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_performance_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_performance_system_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_preemption_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_priority_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_relinquish.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_reset.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_resume.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_schedule.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_shell_entry.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_sleep.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_analyze.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_stack_build.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_error_handler.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_stack_error_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_suspend.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_preempt_check.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_resume.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_system_return.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_system_suspend.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_terminate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_time_slice.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_time_slice_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_timeout.c
+        
+        
+            $PROJ_DIR$\..\src\tx_thread_vectored_context_save.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_thread_wait_abort.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_time_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_time_set.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_activate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_deactivate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_expiration_process.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_initialize.c
+        
+        
+            $PROJ_DIR$\..\src\tx_timer_interrupt.s
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_performance_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_performance_system_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_system_activate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_system_deactivate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_timer_thread_entry.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_buffer_full_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_disable.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_enable.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_filter.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_event_unfilter.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_initialize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_interrupt_control.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_enter_insert.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_isr_exit_insert.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_register.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_object_unregister.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\tx_trace_user_event_insert.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_allocate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_pool_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_block_release.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_allocate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_pool_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_byte_release.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_event_flags_set_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_mutex_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_flush.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_front_send.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_receive.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_queue_send_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_ceiling_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_prioritize.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_semaphore_put_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_entry_exit_notify.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_info_get.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_preemption_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_priority_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_relinquish.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_reset.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_resume.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_suspend.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_terminate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_time_slice_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_thread_wait_abort.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_activate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_change.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_create.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_deactivate.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_delete.c
+        
+        
+            $PROJ_DIR$\..\..\..\..\common\src\txe_timer_info_get.c
+        
+    
+
diff --git a/ports/cortex_r4/iar/example_build/tx_initialize_low_level.s b/ports/cortex_r4/iar/example_build/tx_initialize_low_level.s
new file mode 100644
index 00000000..a05d79d1
--- /dev/null
+++ b/ports/cortex_r4/iar/example_build/tx_initialize_low_level.s
@@ -0,0 +1,277 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Initialize                                                          */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_initialize.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+SVC_MODE        DEFINE  0x13                    ; SVC mode
+;
+
+    EXTERN      _tx_thread_system_stack_ptr
+    EXTERN      _tx_initialize_unused_memory
+    EXTERN      _tx_thread_context_save
+;    EXTERN      _tx_thread_vectored_context_save
+    EXTERN      _tx_thread_context_restore
+
+#ifdef TX_ENABLE_IRQ_NESTING
+    EXTERN      _tx_thread_irq_nesting_start
+    EXTERN      _tx_thread_irq_nesting_end
+#endif
+
+    EXTERN      _tx_timer_interrupt
+    EXTERN      ?cstartup
+    EXTERN      _tx_build_options
+    EXTERN      _tx_version_id
+;
+;
+;
+;/* Define the FREE_MEM segment that will specify where free memory is 
+;   defined.  This must also be located in at the end of other RAM segments
+;   in the linker control file.  The value of this segment is what is passed
+;   to tx_application_define.  */
+;
+    RSEG    FREE_MEM:DATA
+    PUBLIC  __tx_free_memory_start
+__tx_free_memory_start
+    DS32    4
+;
+;
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_low_level                           Cortex-R4/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for any low-level processor            */ 
+;/*    initialization, including setting up interrupt vectors, setting     */ 
+;/*    up a periodic timer interrupt source, saving the system stack       */ 
+;/*    pointer for use in ISR processing later, and finding the first      */ 
+;/*    available RAM memory address for tx_application_define.             */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_initialize_low_level(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    ARM
+    PUBLIC  _tx_initialize_low_level
+_tx_initialize_low_level
+;
+;    /****** NOTE ****** The IAR 4.11a and above releases call main in SYS mode.  */
+;
+;    /* Remember the stack pointer, link register, and switch to SVC mode.  */
+;
+    MOV     r0, sp                              ; Remember the SP
+    MOV     r1, lr                              ; Remember the LR
+    CPS     #SVC_MODE                           ; Switch to SVC mode
+    MOV     sp, r0                              ; Inherit the stack pointer setup by cstartup
+    MOV     lr, r1                              ; Inherit the link register
+;
+;    /* Pickup the start of free memory.  */
+;
+    LDR     r0, =__tx_free_memory_start         ; Get end of non-initialized RAM area
+;
+;    /* Save the system stack pointer.  */
+;    _tx_thread_system_stack_ptr = (VOID_PTR) (sp);
+;
+;    /* Save the first available memory address.  */
+;    _tx_initialize_unused_memory =  (VOID_PTR) FREE_MEM;
+;
+    LDR     r2, =_tx_initialize_unused_memory   ; Pickup unused memory ptr address
+    STR     r0, [r2, #0]                        ; Save first free memory address
+;                      
+;    /* Setup Timer for periodic interrupts.  */
+;
+;    /* Done, return to caller.  */
+;
+    BX      lr                                  ; Return to caller
+;}
+;
+;/* Define shells for each of the interrupt vectors.  */
+;
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_undefined
+__tx_undefined
+    B       __tx_undefined                      ; Undefined handler
+;
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_swi_interrupt
+__tx_swi_interrupt
+    B       __tx_swi_interrupt                  ; Software interrupt handler
+;
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_prefetch_handler
+__tx_prefetch_handler
+    B       __tx_prefetch_handler               ; Prefetch exception handler
+;
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_abort_handler
+__tx_abort_handler
+    B       __tx_abort_handler                  ; Abort exception handler
+;
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_reserved_handler
+__tx_reserved_handler
+    B       __tx_reserved_handler               ; Reserved exception handler
+;
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_irq_handler
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_irq_processing_return
+    PUBLIC  IRQ_Handler
+__tx_irq_handler
+IRQ_Handler
+;
+;    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return
+;
+;    /* At this point execution is still in the IRQ mode.  The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  In 
+;       addition, IRQ interrupts may be re-enabled - with certain restrictions -
+;       if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
+;       small code sequences where lr is saved before enabling interrupts and 
+;       restored after interrupts are again disabled.  */
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start 
+;       from IRQ mode with interrupts disabled.  This routine switches to the
+;       system mode and returns with IRQ interrupts enabled.  
+;       
+;       NOTE:  It is very important to ensure all IRQ interrupts are cleared 
+;       prior to enabling nested IRQ interrupts.  */
+#ifdef TX_ENABLE_IRQ_NESTING
+    BL      _tx_thread_irq_nesting_start
+#endif
+;
+;    /* For debug purpose, execute the timer interrupt processing here.  In
+;       a real system, some kind of status indication would have to be checked
+;       before the timer interrupt handler could be called.  */
+;
+    BL      _tx_timer_interrupt                 ; Timer interrupt handler
+;
+;    /* Application IRQ handlers can be called here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_context_restore.  
+;       This routine returns in processing in IRQ mode with interrupts disabled.  */
+#ifdef TX_ENABLE_IRQ_NESTING
+    BL      _tx_thread_irq_nesting_end
+#endif
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+;
+;
+;    /* This is an example of a vectored IRQ handler.  */
+;
+;    RSEG    .text:CODE:NOROOT(2)
+;    PUBLIC  __tx_example_vectored_irq_handler
+;__tx_example_vectored_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+;    STMDB   sp!, {r0-r3}                    ; Save some scratch registers
+;    MRS     r0, SPSR                        ; Pickup saved SPSR
+;    SUB     lr, lr, #4                      ; Adjust point of interrupt 
+;    STMDB   sp!, {r0, r10, r12, lr}         ; Store other registers
+;    BL      _tx_thread_vectored_context_save
+;
+;    /* At this point execution is still in the IRQ mode.  The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  In 
+;       addition, IRQ interrupts may be re-enabled - with certain restrictions -
+;       if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
+;       small code sequences where lr is saved before enabling interrupts and 
+;       restored after interrupts are again disabled.  */
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start 
+;       from IRQ mode with interrupts disabled.  This routine switches to the
+;       system mode and returns with IRQ interrupts enabled.  
+;       
+;       NOTE:  It is very important to ensure all IRQ interrupts are cleared 
+;       prior to enabling nested IRQ interrupts.  */
+;#ifdef TX_ENABLE_IRQ_NESTING
+;    BL      _tx_thread_irq_nesting_start
+;#endif
+;
+;    /* Application IRQ handler is called here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_context_restore.  
+;       This routine returns in processing in IRQ mode with interrupts disabled.  */
+;#ifdef TX_ENABLE_IRQ_NESTING
+;    BL      _tx_thread_irq_nesting_end
+;#endif
+;
+;    /* Jump to context restore to restore system context.  */
+;    B       _tx_thread_context_restore
+;
+;
+;    /* FIQ Handler */
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_fiq_handler
+__tx_fiq_handler
+    B       __tx_fiq_handler                    ; FIQ interrupt handler
+;
+;
+BUILD_OPTIONS
+    DC32    _tx_build_options                   ; Reference to ensure it comes in
+VERSION_ID
+    DC32    _tx_version_id                      ; Reference to ensure it comes in
+    END
+
diff --git a/ports/cortex_r4/iar/inc/tx_port.h b/ports/cortex_r4/iar/inc/tx_port.h
new file mode 100644
index 00000000..362edaf5
--- /dev/null
+++ b/ports/cortex_r4/iar/inc/tx_port.h
@@ -0,0 +1,380 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */ 
+/*                                                                        */ 
+/*    tx_port.h                                         Cortex-R4/IAR     */ 
+/*                                                           6.0.1        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This file contains data type definitions that make the ThreadX      */ 
+/*    real-time kernel function identically on a variety of different     */ 
+/*    processor architectures.  For example, the size or number of bits   */ 
+/*    in an "int" data type vary between microprocessor architectures and */ 
+/*    even C compilers for the same microprocessor.  ThreadX does not     */ 
+/*    directly use native C data types.  Instead, ThreadX creates its     */ 
+/*    own special types that can be mapped to actual data types by this   */ 
+/*    file to guarantee consistency in the interface and functionality.   */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include 
+#include 
+#include 
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#include 
+#endif
+
+
+/* Define ThreadX basic types for this port.  */ 
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */ 
+#endif
+
+
+/* Define various constants for the ThreadX ARM port.  */ 
+
+#define TX_INT_DISABLE                          0x80        /* Disable IRQ interrupts           */
+#define TX_INT_ENABLE                           0x00        /* Enable IRQ interrupts            */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_MISRA_ENABLE
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ++_tx_trace_simulated_time
+#endif
+#else
+ULONG   _tx_misra_time_stamp_get(VOID);
+#define TX_TRACE_TIME_SOURCE                    _tx_misra_time_stamp_get()
+#endif
+
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#ifdef TX_ENABLE_IRQ_NESTING
+#define TX_IRQ_NESTING_ENABLED                  1
+#else
+#define TX_IRQ_NESTING_ENABLED                  0
+#endif
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          (TX_IRQ_NESTING_ENABLED)
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#ifdef TX_MISRA_ENABLE
+#define TX_DISABLE_INLINE
+#else
+#define TX_INLINE_INITIALIZATION
+#endif
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifndef TX_MISRA_ENABLE
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_EXTENSION_2                               ULONG       tx_thread_vfp_enable; \
+                                                            VOID        *tx_thread_iar_tls_pointer;          
+#else
+#define TX_THREAD_EXTENSION_2                               ULONG       tx_thread_vfp_enable;
+#endif
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#if (__VER__ < 8000000)
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  __iar_dlib_perthread_allocate();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                    thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL;            
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               __iar_dlib_perthread_access(0);
+#else
+void    *_tx_iar_create_per_thread_tls_area(void);
+void    _tx_iar_destroy_per_thread_tls_area(void *tls_ptr);
+void    __iar_Initlocks(void);
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  _tx_iar_create_per_thread_tls_area();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                        thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL; } while(0);
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               do {__iar_Initlocks();} while(0); 
+#endif
+#else
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#endif
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef TX_DISABLE_INLINE
+
+#if __CORE__ > __ARM4TM__
+
+#if __CPU_MODE__ == 2
+
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       m = m & ((ULONG) (-((LONG) m))); \
+                                                b = (UINT) __CLZ(m); \
+                                                b = 31 - b; 
+#endif
+#endif
+#endif
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+
+/* First, check and see what mode the file is being compiled in. The IAR compiler
+   defines __CPU_MODE__ to 1, if the Thumb mode is present, and 2 if ARM 32-bit mode 
+   is present.  If ARM 32-bit mode is present, the fast CPSR manipulation macros
+   are available. Otherwise, if Thumb mode is present, we must use function calls.  */
+
+#ifdef TX_DISABLE_INLINE
+
+UINT  _tx_thread_interrupt_disable(void);
+void  _tx_thread_interrupt_restore(UINT old_posture);
+
+
+#define TX_INTERRUPT_SAVE_AREA      UINT  interrupt_save;
+
+#define TX_DISABLE                  interrupt_save =  _tx_thread_interrupt_disable();
+#define TX_RESTORE                  _tx_thread_interrupt_restore(interrupt_save);
+
+#else
+#if __CPU_MODE__ == 2
+
+#if (__VER__ < 8002000)
+__intrinsic unsigned long __get_CPSR();
+__intrinsic void          __set_CPSR( unsigned long );
+#endif
+
+
+#if (__VER__ < 8002000)
+#define TX_INTERRUPT_SAVE_AREA      unsigned long interrupt_save;
+#else
+#define TX_INTERRUPT_SAVE_AREA      unsigned int interrupt_save;
+#endif
+
+#define TX_DISABLE                  interrupt_save =  __get_CPSR(); \
+                                    __set_CPSR(interrupt_save | TX_INT_DISABLE);
+#define TX_RESTORE                  __set_CPSR(interrupt_save);
+
+#else
+
+UINT  _tx_thread_interrupt_disable(void);
+void  _tx_thread_interrupt_restore(UINT old_posture);
+
+
+#define TX_INTERRUPT_SAVE_AREA      UINT  interrupt_save;
+
+#define TX_DISABLE                  interrupt_save =  _tx_thread_interrupt_disable();
+#define TX_RESTORE                  _tx_thread_interrupt_restore(interrupt_save);
+
+#endif
+#endif
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define VFP extension for the Cortex-R4.  Each is assumed to be called in the context of the executing
+   thread.  */
+
+void    tx_thread_vfp_enable(void);
+void    tx_thread_vfp_disable(void);
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX Cortex-R4/IAR Version 6.0 *";
+#else
+#ifdef TX_MISRA_ENABLE
+extern  CHAR                    _tx_version_id[100];
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+#endif
+
+
+#endif
+
+
+
diff --git a/ports/cortex_r4/iar/readme_threadx.txt b/ports/cortex_r4/iar/readme_threadx.txt
new file mode 100644
index 00000000..dbf6f32b
--- /dev/null
+++ b/ports/cortex_r4/iar/readme_threadx.txt
@@ -0,0 +1,426 @@
+                       Microsoft's Azure RTOS ThreadX for Cortex-R4 
+
+                                 Thumb & 32-bit Mode
+
+                                 Using the IAR Tools
+
+1.  Building the ThreadX run-time Library
+
+Building the ThreadX library is easy. First, open the Azure RTOS workspace
+azure_rtos.eww. Next, make the TX project the "active project" in the 
+IAR Embedded Workbench and select the "Make" button. You should observe 
+assembly and compilation of a series of ThreadX source files. This 
+results in the ThreadX run-time library file tx.a, which is needed by 
+the application.
+
+
+2.  Demonstration System
+
+The ThreadX demonstration is designed to execute under the IAR
+Windows-based Cortex-R4 simulator.
+
+Building the demonstration is easy; simply make the sample_threadx.ewp project
+the "active project" in the IAR Embedded Workbench and select the 
+"Make" button.
+
+You should observe the compilation of sample_threadx.c (which is the demonstration 
+application) and linking with tx.a. The resulting file sample_threadx.out is a
+binary file that can be downloaded and executed on IAR's Cortex-R4 simulator.
+
+
+3.  System Initialization
+
+The entry point in ThreadX for the Cortex-R4 using IAR tools is at label 
+?cstartup. This is defined within the IAR compiler's startup code. In 
+addition, this is where all static and global preset C variable 
+initialization processing takes place.
+
+The ThreadX tx_initialize_low_level.s file is responsible for setting up 
+various system data structures, and a periodic timer interrupt source. 
+By default, the vector area is defined at the top of cstartup.s, which is
+a slightly modified from the base IAR file. 
+
+The _tx_initialize_low_level function inside of tx_initialize_low_level.s
+also determines the first available address for use by the application, which 
+is supplied as the sole input parameter to your application definition function, 
+tx_application_define. To accomplish this, a section is created in 
+tx_initialize_low_level.s called FREE_MEM, which must be located after all 
+other RAM sections in memory.
+
+
+4.  Register Usage and Stack Frames
+
+The IAR ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are 
+scratch registers for each function. All other registers used by a C function 
+must be preserved by the function. ThreadX takes advantage of this in 
+situations where a context switch happens as a result of making a ThreadX 
+service call (which is itself a C function). In such cases, the saved 
+context of a thread is only the non-scratch registers.
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have one of these two types of stack frames. The top
+of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the 
+associated thread control block TX_THREAD.
+
+
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x00                   1                           0
+     0x04                   CPSR                        CPSR
+     0x08                   r0  (a1)                    r4  (v1)
+     0x0C                   r1  (a2)                    r5  (v2)
+     0x10                   r2  (a3)                    r6  (v3)
+     0x14                   r3  (a4)                    r7  (v4)
+     0x18                   r4  (v1)                    r8  (v5)
+     0x1C                   r5  (v2)                    r9  (v6)
+     0x20                   r6  (v3)                    r10 (v7)
+     0x24                   r7  (v4)                    r11 (fp)
+     0x28                   r8  (v5)                    r14 (lr)
+     0x2C                   r9  (v6)                        
+     0x30                   r10 (v7)                        
+     0x34                   r11 (fp)                        
+     0x38                   r12 (ip)                         
+     0x3C                   r14 (lr)
+     0x40                   PC 
+
+
+5.  Conditional Compilation Switches
+
+The following are conditional compilation options for building the ThreadX library
+and application:
+
+    TX_ENABLE_IRQ_NESTING                       This assembler define enables IRQ
+                                                nested support. If IRQ nested 
+                                                interrupt support is needed, this
+                                                define should be applied to 
+                                                tx_initialize_low_level.s.
+
+    TX_DISABLE_ERROR_CHECKING                   If defined before tx_api.h is included,
+                                                this define causes basic ThreadX error
+                                                checking to be disabled. Please see
+                                                Chapter 2 in the "ThreadX User Guide" 
+                                                for more details.
+
+    TX_MAX_PRIORITIES                           Defines the priority levels for ThreadX. 
+                                                Legal values range from 32 through 
+                                                1024 (inclusive) and MUST be evenly divisible 
+                                                by 32. Increasing the number of priority levels 
+                                                supported increases the RAM usage by 128 bytes 
+                                                for every group of 32 priorities. However, there 
+                                                is only a negligible effect on performance. By 
+                                                default, this value is set to 32 priority levels.
+
+    TX_MINIMUM_STACK                            Defines the minimum stack size (in bytes). It is 
+                                                used for error checking when threads are created. 
+                                                The default value is port-specific and is found 
+                                                in tx_port.h.
+
+    TX_TIMER_THREAD_STACK_SIZE                  Defines the stack size (in bytes) of the internal 
+                                                ThreadX timer thread. This thread processes all 
+                                                thread sleep requests as well as all service call 
+                                                timeouts. In addition, all application timer callback 
+                                                routines are invoked from this context. The default 
+                                                value is port-specific and is found in tx_port.h.
+
+    TX_TIMER_THREAD_PRIORITY                    Defines the priority of the internal ThreadX timer 
+                                                thread. The default value is priority 0 - the highest 
+                                                priority in ThreadX. The default value is defined 
+                                                in tx_port.h.
+
+    TX_TIMER_PROCESS_IN_ISR                     Defined, this option eliminates the internal system 
+                                                timer thread for ThreadX. This results in improved 
+                                                performance on timer events and smaller RAM requirements 
+                                                because the timer stack and control block are no 
+                                                longer needed. However, using this option moves all 
+                                                the timer expiration processing to the timer ISR level. 
+                                                By default, this option is not defined.
+
+    TX_REACTIVATE_INLINE                        Defined, this option performs reactivation of ThreadX 
+                                                timers in-line instead of using a function call. This 
+                                                improves performance but slightly increases code size. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_STACK_FILLING                    Defined, placing the 0xEF value in each byte of each 
+                                                thread's stack is disabled. By default, this option is 
+                                                not defined.
+
+    TX_ENABLE_STACK_CHECKING                    Defined, this option enables ThreadX run-time stack checking, 
+                                                which includes analysis of how much stack has been used and 
+                                                examination of data pattern "fences" before and after the 
+                                                stack area. If a stack error is detected, the registered 
+                                                application stack error handler is called. This option does 
+                                                result in slightly increased overhead and code size. Please 
+                                                review the tx_thread_stack_error_notify API for more information. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_PREEMPTION_THRESHOLD             Defined, this option disables the preemption-threshold feature 
+                                                and slightly reduces code size and improves performance. Of course, 
+                                                the preemption-threshold capabilities are no longer available. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_REDUNDANT_CLEARING               Defined, this option removes the logic for initializing ThreadX 
+                                                global C data structures to zero. This should only be used if 
+                                                the compiler's initialization code sets all un-initialized 
+                                                C global data to zero. Using this option slightly reduces 
+                                                code size and improves performance during initialization. 
+                                                By default, this option is not defined.
+
+    TX_DISABLE_NOTIFY_CALLBACKS                 Defined, this option disables the notify callbacks for various 
+                                                ThreadX objects. Using this option slightly reduces code size 
+                                                and improves performance.
+
+    TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO       Defined, this option enables the gathering of performance 
+                                                information on block pools. By default, this option is 
+                                                not defined.
+
+    TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO        Defined, this option enables the gathering of performance 
+                                                information on byte pools. By default, this option is 
+                                                not defined.
+
+    TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO      Defined, this option enables the gathering of performance 
+                                                information on event flags groups. By default, this option 
+                                                is not defined.
+
+    TX_MUTEX_ENABLE_PERFORMANCE_INFO            Defined, this option enables the gathering of performance 
+                                                information on mutexes. By default, this option is 
+                                                not defined.
+
+    TX_QUEUE_ENABLE_PERFORMANCE_INFO            Defined, this option enables the gathering of performance 
+                                                information on queues. By default, this option is 
+                                                not defined.
+
+    TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO        Defined, this option enables the gathering of performance 
+                                                information on semaphores. By default, this option is 
+                                                not defined.
+
+    TX_THREAD_ENABLE_PERFORMANCE_INFO           Defined, this option enables the gathering of performance 
+                                                information on threads. By default, this option is 
+                                                not defined.
+
+    TX_TIMER_ENABLE_PERFORMANCE_INFO            Defined, this option enables the gathering of performance 
+                                                information on timers. By default, this option is 
+                                                not defined.
+
+    TX_ENABLE_EVENT_TRACE                       Defined, this option enables the internal ThreadX trace
+                                                feature. The trace buffer is supplied at a later time
+                                                via an application call to tx_trace_enable.
+
+    TX_TRACE_TIME_SOURCE                        This defines the time-stamp source for event tracing. 
+                                                This define is only pertinent if the ThreadX library is 
+                                                built with TX_ENABLE_EVENT_TRACE defined.
+
+    TX_TRACE_TIME_MASK                          This defines the number of valid bits in the event trace 
+                                                time-stamp source defined previously. If the time-stamp 
+                                                source is 16-bits, this value should be 0xFFFF. Alternatively, 
+                                                if the time-stamp source is 32-bits, this value should be 
+                                                0xFFFFFFFF. This define is only pertinent if the ThreadX 
+                                                library is built with TX_ENABLE_EVENT_TRACE defined.
+
+
+
+6.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+breakpoints inside of ThreadX itself. Of course, this costs some 
+performance. To make it run faster, you can change the ThreadX library
+project to enable various compiler optimizations. 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+7.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-R4
+targets. There are a certain set of requirements that are defined in the 
+following sub-sections:
+
+
+7.1  Vector Area
+
+The Cortex-R4 vectors start at address zero. The demonstration system startup
+cstartup.s file contains the vectors and is loaded at address zero. 
+On actual hardware platforms, this area might have to be copied to address 0. 
+
+
+7.2  IRQ ISRs
+
+ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested
+IRQ interrupts. The following sub-sections define the IRQ capabilities.
+
+
+7.2.1 Standard IRQ ISRs
+
+The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ 
+interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following 
+is the default IRQ handler defined in tx_initialize_low_level.s:
+
+    PUBLIC  __tx_irq_handler
+    PUBLIC  __tx_irq_processing_return      
+__tx_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return
+;
+;    /* At this point execution is still in the IRQ mode. The CPSR, point of
+;       interrupt, and all C scratch registers are available for use. Note 
+;       that IRQ interrupts are still disabled upon return from the context
+;       save function.  */
+;
+;    /* Application ISR dispatch call goes here!  */
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.2.2 Vectored IRQ ISRs
+
+The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified
+by the particular implementation. The following is an example IRQ handler defined in 
+tx_initialize_low_level.s:
+
+
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_example_vectored_irq_handler
+__tx_example_vectored_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+    STMDB   sp!, {r0-r3}                    ; Save some scratch registers
+    MRS     r0, SPSR                        ; Pickup saved SPSR
+    SUB     lr, lr, #4                      ; Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}         ; Store other registers
+    BL      _tx_thread_vectored_context_save
+;
+;    /* At this point execution is still in the IRQ mode. The CPSR, point of
+;       interrupt, and all C scratch registers are available for use. Note 
+;       that IRQ interrupts are still disabled upon return from the context
+;       save function.  */
+;
+;    /* Application ISR dispatch call goes here!  */
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.2.3  Nested IRQ Support
+
+By default, nested IRQ interrupt support is not enabled. To enable nested
+IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING
+defined. With this defined, two new IRQ interrupt management services are
+available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end.
+These function should be called between the IRQ context save and restore
+calls. 
+
+Execution between the calls to _tx_thread_irq_nesting_start and 
+_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved 
+by switching from IRQ mode to SYS mode and enabling IRQ interrupts.
+The SYS mode stack is used during the SYS mode operation, which was 
+setup in tx_initialize_low_level.s. When nested IRQ interrupts are no 
+longer required, calling the _tx_thread_irq_nesting_end service disables 
+nesting by disabling IRQ interrupts and switching back to IRQ mode in 
+preparation for the IRQ context restore service.
+
+The following is an example of enabling IRQ nested interrupts in a standard 
+IRQ handler:
+
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_irq_handler
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  __tx_irq_processing_return      
+__tx_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return
+;
+;    /* At this point execution is still in the IRQ mode. The CPSR, point of
+;       interrupt, and all C scratch registers are available for use. Note 
+;       that IRQ interrupts are still disabled upon return from the context
+;       save function.  */
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start 
+;       from IRQ mode with interrupts disabled. This routine switches to the
+;       system mode and returns with IRQ interrupts enabled. 
+;       
+;       NOTE:  It is very important to ensure all IRQ interrupts are cleared 
+;       prior to enabling nested IRQ interrupts. */
+;
+    BL      _tx_thread_irq_nesting_start
+
+;    /* Application ISR dispatch call goes here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_context_restore. 
+;       This routine returns in processing in IRQ mode with interrupts disabled.  */
+;
+    BL      _tx_thread_irq_nesting_end
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.3  FIQ Interrupts
+
+By default, Cortex-R4 FIQ interrupts are left alone by ThreadX. Of course, this 
+means that the application is fully responsible for enabling the FIQ interrupt 
+and saving/restoring any registers used in the FIQ ISR processing. To globally 
+enable FIQ interrupts, the application should enable FIQ interrupts at the 
+beginning of a thread or before any threads are created in tx_application_define. 
+In addition, the application must ensure that no ThreadX service calls are made 
+from default FIQ ISRs, which is located in tx_initialize_low_level.s.
+
+
+7.3.1  Managed FIQ Interrupts
+
+ThreadX management of FIQ interrupts is not provided because FIQ interrupts
+cannot be disabled. The hardware does not support nested FIQ interrupts.
+
+
+8.  ThreadX Timer Interrupt
+
+ThreadX requires a periodic interrupt source to manage all time-slicing, 
+thread sleeps, timeouts, and application timers. Without such a timer 
+interrupt source, these services are not functional. However, all other
+ThreadX services are operational without a periodic timer source.
+
+To add the timer interrupt processing, simply make a call to _tx_timer_interrupt 
+in the IRQ processing.
+
+
+9.  Thumb/Cortex-R4 Mixed Mode
+
+By default, ThreadX is setup for running in Cortex-R4 32-bit mode. This is 
+also true for the demonstration system. It is possible to build any 
+ThreadX file and/or the application in Thumb mode. The only exception
+to this is the file tx_thread_shell_entry.c. This file must always be 
+built in 32-bit mode.
+
+
+10.  IAR Thread-safe Library Support
+
+Thread-safe support for the IAR tools is easily enabled by building the ThreadX library
+and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file
+should have the following line added (if not already in place):
+
+initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
+
+
+11.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX version 6.0.1 for Cortex-R4 using IAR's ARM tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_r4/iar/src/tx_iar.c b/ports/cortex_r4/iar/src/tx_iar.c
new file mode 100644
index 00000000..11fcefb3
--- /dev/null
+++ b/ports/cortex_r4/iar/src/tx_iar.c
@@ -0,0 +1,804 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */ 
+/**                                                                       */
+/**   IAR Multithreaded Library Support                                   */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+#define TX_SOURCE_CODE
+
+
+/* Define IAR library for tools prior to version 8.  */
+
+#if (__VER__ < 8000000)
+
+
+/* IAR version 7 and below.  */
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_initialize.h"
+#include "tx_thread.h"
+#include "tx_mutex.h"
+
+
+/* This implementation requires that the following macros are defined in the 
+   tx_port.h file and  is included with the following code segments:
+   
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#include 
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_EXTENSION_2           VOID    *tx_thread_iar_tls_pointer;          
+#else
+#define TX_THREAD_EXTENSION_2          
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  __iar_dlib_perthread_allocate();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                    thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL;            
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               __iar_dlib_perthread_access(0);
+#else
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#endif
+
+    This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the 
+    application.  
+
+    Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected.
+*/
+
+#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
+
+#include 
+
+
+#if _MULTI_THREAD
+
+TX_MUTEX    __tx_iar_system_lock_mutexes[_MAX_LOCK];
+UINT        __tx_iar_system_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_system_lock_no_mutexes;
+UINT        __tx_iar_system_lock_internal_errors;
+UINT        __tx_iar_system_lock_isr_caller;
+
+
+/* Define the TLS access function for the IAR library.  */
+
+void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp)
+{
+
+char _DLIB_TLS_MEMORY   *p = 0;
+    
+    /* Is there a current thread?  */
+    if (_tx_thread_current_ptr)
+      p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer;
+    else
+      p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD");
+    p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp);
+    return (void _DLIB_TLS_MEMORY *) p;
+}
+
+
+/* Define mutexes for IAR library.  */
+
+void __iar_system_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_LOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_system_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_system_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_system_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_system_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_system_Mtxlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+}
+
+void __iar_system_Mtxunlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+}
+
+
+#if _DLIB_FILE_DESCRIPTOR
+
+TX_MUTEX    __tx_iar_file_lock_mutexes[_MAX_FLOCK];
+UINT        __tx_iar_file_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_file_lock_no_mutexes;
+UINT        __tx_iar_file_lock_internal_errors;
+UINT        __tx_iar_file_lock_isr_caller;
+
+
+void __iar_file_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_FLOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_file_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_file_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_file_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_file_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_file_Mtxlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+
+void __iar_file_Mtxunlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+#endif  /* _DLIB_FILE_DESCRIPTOR */
+
+#endif  /* _MULTI_THREAD  */
+
+#endif  /* TX_ENABLE_IAR_LIBRARY_SUPPORT  */
+
+#else   /* IAR version 8 and above.  */
+
+
+/* Include necessary system files.  */
+
+#include "tx_api.h"
+#include "tx_initialize.h"
+#include "tx_thread.h"
+#include "tx_mutex.h"
+
+/* This implementation requires that the following macros are defined in the 
+   tx_port.h file and  is included with the following code segments:
+   
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#include 
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+#define TX_THREAD_EXTENSION_2           VOID    *tx_thread_iar_tls_pointer;          
+#else
+#define TX_THREAD_EXTENSION_2          
+#endif
+
+#ifdef  TX_ENABLE_IAR_LIBRARY_SUPPORT
+void    *_tx_iar_create_per_thread_tls_area(void);
+void    _tx_iar_destroy_per_thread_tls_area(void *tls_ptr);
+void    __iar_Initlocks(void);
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                      thread_ptr -> tx_thread_iar_tls_pointer =  __iar_dlib_perthread_allocate();                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                      do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \
+                                                                        thread_ptr -> tx_thread_iar_tls_pointer =  TX_NULL; } while(0);
+#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION               do {__iar_Initlocks();} while(0);
+#else
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#endif
+
+    This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the 
+    application.  
+
+    Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected.
+*/
+
+#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT
+
+#include 
+
+
+void * __aeabi_read_tp();
+
+void* _tx_iar_create_per_thread_tls_area();
+void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr);
+
+#pragma section="__iar_tls$$DATA"
+
+/* Define the TLS access function for the IAR library.  */
+void * __aeabi_read_tp(void)
+{
+  void *p = 0;
+  TX_THREAD *thread_ptr = _tx_thread_current_ptr;
+  if (thread_ptr)
+  {
+    p = thread_ptr->tx_thread_iar_tls_pointer;      
+  }
+  else
+  {
+    p = __section_begin("__iar_tls$$DATA");
+  }
+  return p;
+}
+
+/* Define the TLS creation and destruction to use malloc/free.  */
+
+void* _tx_iar_create_per_thread_tls_area()
+{
+  UINT tls_size = __iar_tls_size();  
+  
+  /* Get memory for TLS.  */  
+  void *p = malloc(tls_size);
+
+  /* Initialize TLS-area and run constructors for objects in TLS */
+  __iar_tls_init(p);
+  return p;
+}
+
+void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr)
+{
+  /* Destroy objects living in TLS */
+  __call_thread_dtors();
+  free(tls_ptr);  
+}
+
+#ifndef _MAX_LOCK
+#define _MAX_LOCK 4
+#endif
+
+static TX_MUTEX    __tx_iar_system_lock_mutexes[_MAX_LOCK];
+static UINT        __tx_iar_system_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_system_lock_no_mutexes;
+UINT        __tx_iar_system_lock_internal_errors;
+UINT        __tx_iar_system_lock_isr_caller;
+
+
+/* Define mutexes for IAR library.  */
+
+void __iar_system_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_LOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_system_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_system_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_system_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_system_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_system_Mtxlock(__iar_Rmtx *m)
+{
+  if (*m)
+  {  
+    UINT    status;
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+  }
+}
+
+void __iar_system_Mtxunlock(__iar_Rmtx *m)
+{
+  if (*m)
+  {
+    UINT    status;
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_system_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_system_lock_isr_caller++;
+    }
+  }
+}
+
+
+#if _DLIB_FILE_DESCRIPTOR
+
+#include                         /* Added to get access to FOPEN_MAX */
+#ifndef _MAX_FLOCK
+#define _MAX_FLOCK FOPEN_MAX              /* Define _MAX_FLOCK as the maximum number of open files */
+#endif
+
+
+TX_MUTEX    __tx_iar_file_lock_mutexes[_MAX_FLOCK];
+UINT        __tx_iar_file_lock_next_free_mutex =  0;
+
+
+/* Define error counters, just for debug purposes.  */
+
+UINT        __tx_iar_file_lock_no_mutexes;
+UINT        __tx_iar_file_lock_internal_errors;
+UINT        __tx_iar_file_lock_isr_caller;
+
+
+void __iar_file_Mtxinit(__iar_Rmtx *m)
+{
+
+UINT        i;
+UINT        status;
+TX_MUTEX    *mutex_ptr;
+
+
+    /* First, find a free mutex in the list.  */
+    for (i = 0; i < _MAX_FLOCK; i++)
+    {
+
+        /* Setup a pointer to the start of the next free mutex.  */
+        mutex_ptr =  &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++];
+    
+        /* Check for wrap-around on the next free mutex.  */
+        if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK)
+        {
+        
+            /* Yes, set the free index back to 0.  */
+            __tx_iar_file_lock_next_free_mutex =  0;
+        }
+    
+        /* Is this mutex free?  */
+        if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID)
+        {
+        
+            /* Yes, this mutex is free, get out of the loop!  */
+            break;
+        }
+    }
+
+    /* Determine if a free mutex was found.   */
+    if (i >= _MAX_LOCK)
+    {
+    
+        /* Error!  No more free mutexes!  */
+        
+        /* Increment the no mutexes error counter.  */
+        __tx_iar_file_lock_no_mutexes++;
+        
+        /* Set return pointer to NULL.  */
+        *m =  TX_NULL;
+        
+        /* Return.  */
+        return;
+    }
+    
+    /* Now create the ThreadX mutex for the IAR library.  */
+    status =  _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT);
+    
+    /* Determine if the creation was successful.  */
+    if (status == TX_SUCCESS)
+    {
+    
+        /* Yes, successful creation, return mutex pointer.  */
+        *m =  (VOID *) mutex_ptr;
+    }
+    else
+    {
+    
+        /* Increment the internal error counter.  */
+        __tx_iar_file_lock_internal_errors++;
+    
+        /* Return a NULL pointer to indicate an error.  */
+        *m =  TX_NULL;
+    }
+}
+
+void __iar_file_Mtxdst(__iar_Rmtx *m)
+{
+
+    /* Simply delete the mutex.  */
+    _tx_mutex_delete((TX_MUTEX *) *m);
+}
+
+void __iar_file_Mtxlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex locks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Get the mutex.  */
+        status =  _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER);
+
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+
+void __iar_file_Mtxunlock(__iar_Rmtx *m)
+{
+
+UINT    status;
+
+
+    /* Determine the caller's context. Mutex unlocks are only available from initialization and 
+       threads.  */
+    if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS))
+    {
+    
+        /* Release the mutex.  */
+        status =  _tx_mutex_put((TX_MUTEX *) *m);
+        
+        /* Check the status of the mutex release.  */
+        if (status)
+        {
+        
+            /* Internal error, increment the counter.  */
+            __tx_iar_file_lock_internal_errors++;
+        }
+    }
+    else
+    {
+        
+        /* Increment the ISR caller error.  */
+        __tx_iar_file_lock_isr_caller++;
+    }
+}
+#endif  /* _DLIB_FILE_DESCRIPTOR */
+
+#endif  /* TX_ENABLE_IAR_LIBRARY_SUPPORT  */
+
+#endif /* IAR version 8 and above.  */
diff --git a/ports/cortex_r4/iar/src/tx_thread_context_restore.s b/ports/cortex_r4/iar/src/tx_thread_context_restore.s
new file mode 100644
index 00000000..eb9c7446
--- /dev/null
+++ b/ports/cortex_r4/iar/src/tx_thread_context_restore.s
@@ -0,0 +1,247 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+
+SVC_MODE        DEFINE  0x13                    ; SVC mode
+IRQ_MODE        DEFINE  0x12                    ; IRQ mode
+DISABLE_INTS    DEFINE  0x80                    ; Disable IRQ interrupts
+THUMB_MASK      DEFINE  0x20                    ; Thumb bit mask
+
+;
+    EXTERN      _tx_thread_system_state
+    EXTERN      _tx_thread_current_ptr
+    EXTERN      _tx_thread_execute_ptr
+    EXTERN      _tx_timer_time_slice
+    EXTERN      _tx_thread_schedule
+    EXTERN      _tx_thread_preempt_disable
+    EXTERN      _tx_execution_isr_exit
+;
+;
+
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_context_restore                         Cortex-R4/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function restores the interrupt context if it is processing a  */ 
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */ 
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+;/*    if no thread was running, the function returns to the scheduler.    */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                   Thread scheduling routine     */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                  Interrupt Service Routines    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_restore(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_context_restore
+    ARM
+_tx_thread_context_restore
+;
+;    /* Lockout interrupts.  */
+;
+    CPSID   i                                   ; Disable IRQ interrupts
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR exit function to indicate an ISR is complete.  */
+;
+    BL      _tx_execution_isr_exit              ; Call the ISR exit function
+#endif
+;
+;    /* Determine if interrupts are nested.  */
+;    if (--_tx_thread_system_state)
+;    {
+;
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3]                            ; Pickup system state
+    SUB     r2, r2, #1                          ; Decrement the counter
+    STR     r2, [r3]                            ; Store the counter 
+    CMP     r2, #0                              ; Was this the first interrupt?
+    BEQ     __tx_thread_not_nested_restore      ; If so, not a nested restore
+;
+;    /* Interrupts are nested.  */
+;
+;    /* Just recover the saved registers and return to the point of 
+;       interrupt.  */
+;
+    LDMIA   sp!, {r0, r10, r12, lr}             ; Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       ; Put SPSR back
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOVS    pc, lr                              ; Return to point of interrupt
+;
+;    }
+__tx_thread_not_nested_restore
+;
+;    /* Determine if a thread was interrupted and no preemption is required.  */
+;    else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) 
+;               || (_tx_thread_preempt_disable))
+;    {
+;
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1]                            ; Pickup actual current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_idle_system_restore     ; Yes, idle system was interrupted
+;
+    LDR     r3, =_tx_thread_preempt_disable     ; Pickup preempt disable address
+    LDR     r2, [r3]                            ; Pickup actual preempt disable flag
+    CMP     r2, #0                              ; Is it set?
+    BNE     __tx_thread_no_preempt_restore      ; Yes, don't preempt this thread
+    LDR     r3, =_tx_thread_execute_ptr         ; Pickup address of execute thread ptr
+    LDR     r2, [r3]                            ; Pickup actual execute thread pointer
+    CMP     r0, r2                              ; Is the same thread highest priority?
+    BNE     __tx_thread_preempt_restore         ; No, preemption needs to happen
+;
+;
+__tx_thread_no_preempt_restore
+;
+;    /* Restore interrupted thread or ISR.  */
+;
+;    /* Pickup the saved stack pointer.  */
+;    tmp_ptr =  _tx_thread_current_ptr -> tx_thread_stack_ptr;
+;
+;   /* Recover the saved context and return to the point of interrupt.  */
+;
+    LDMIA   sp!, {r0, r10, r12, lr}             ; Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       ; Put SPSR back
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOVS    pc, lr                              ; Return to point of interrupt
+;
+;    }
+;    else
+;    {
+__tx_thread_preempt_restore
+;
+    LDMIA   sp!, {r3, r10, r12, lr}             ; Recover temporarily saved registers
+    MOV     r1, lr                              ; Save lr (point of interrupt)
+    CPS     #SVC_MODE                           ; Enter SVC mode
+    STR     r1, [sp, #-4]!                      ; Save point of interrupt
+    STMDB   sp!, {r4-r12, lr}                   ; Save upper half of registers
+    MOV     r4, r3                              ; Save SPSR in r4
+    CPS     #IRQ_MODE                           ; Enter IRQ mode
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    CPS     #SVC_MODE                           ; Enter SVC mode
+    STMDB   sp!, {r0-r3}                        ; Save r0-r3 on thread's stack
+
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        ; Pickup current thread pointer
+    
+#ifdef __ARMVFP__
+    LDR     r2, [r0, #144]                      ; Pickup the VFP enabled flag
+    CMP     r2, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_irq_vfp_save               ; No, skip VFP IRQ save
+    VMRS    r2, FPSCR                           ; Pickup the FPSCR
+    STR     r2, [sp, #-4]!                      ; Save FPSCR
+    VSTMDB  sp!, {D0-D15}                       ; Save D0-D15
+_tx_skip_irq_vfp_save
+#endif
+    
+    MOV     r3, #1                              ; Build interrupt stack type
+    STMDB   sp!, {r3, r4}                       ; Save interrupt stack type and SPSR
+    STR     sp, [r0, #8]                        ; Save stack pointer in thread control
+                                                ;   block
+    BIC     r4, r4, #THUMB_MASK                 ; Clear the Thumb bit of CPSR
+    ORR     r3, r4, #DISABLE_INTS               ; Or-in interrupt lockout bit(s)
+    MSR     CPSR_cxsf, r3                       ; Lockout interrupts
+;
+;    /* Save the remaining time-slice and disable it.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    LDR     r3, =_tx_timer_time_slice           ; Pickup time-slice variable address
+    LDR     r2, [r3]                            ; Pickup time-slice
+    CMP     r2, #0                              ; Is it active?
+    BEQ     __tx_thread_dont_save_ts            ; No, don't save it
+;
+;        _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+;        _tx_timer_time_slice =  0;
+;
+    STR     r2, [r0, #24]                       ; Save thread's time-slice
+    MOV     r2, #0                              ; Clear value
+    STR     r2, [r3]                            ; Disable global time-slice flag
+;
+;    }
+__tx_thread_dont_save_ts
+;
+;
+;    /* Clear the current task pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;
+    MOV     r0, #0                              ; NULL value
+    STR     r0, [r1]                            ; Clear current thread pointer
+;
+;    /* Return to the scheduler.  */
+;    _tx_thread_schedule();
+;
+    B       _tx_thread_schedule                 ; Return to scheduler
+;    }
+;
+__tx_thread_idle_system_restore
+;
+;    /* Just return back to the scheduler!  */
+;
+    CPS     #SVC_MODE                           ; Enter SVC mode
+    
+    B       _tx_thread_schedule                 ; Return to scheduler
+;}
+;
+;
+    END
+
diff --git a/ports/cortex_r4/iar/src/tx_thread_context_save.s b/ports/cortex_r4/iar/src/tx_thread_context_save.s
new file mode 100644
index 00000000..9c28acb1
--- /dev/null
+++ b/ports/cortex_r4/iar/src/tx_thread_context_save.s
@@ -0,0 +1,198 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    EXTERN      _tx_thread_system_state
+    EXTERN      _tx_thread_current_ptr
+    EXTERN      __tx_irq_processing_return
+    EXTERN      _tx_execution_isr_enter
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_context_save                            Cortex-R4/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function saves the context of an executing thread in the       */ 
+;/*    beginning of interrupt processing.  The function also ensures that  */ 
+;/*    the system stack is used upon return to the calling ISR.            */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_save(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_context_save
+    ARM
+_tx_thread_context_save
+;
+;    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+;       out, we are in IRQ mode, and all registers are intact.  */
+;
+;    /* Check for a nested interrupt condition.  */
+;    if (_tx_thread_system_state++)
+;    {
+;
+    STMDB   sp!, {r0-r3}                        ; Save some working registers 
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3, #0]                        ; Pickup system state
+    CMP     r2, #0                              ; Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         ; Yes, not a nested context save
+;
+;    /* Nested interrupt condition.  */
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+;
+;   /* Save the rest of the scratch registers on the stack and return to the
+;      calling ISR.  */
+;
+    MRS     r0, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}             ; Store other registers
+;
+;    /* Return to the ISR.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+#endif
+
+    B       __tx_irq_processing_return          ; Continue IRQ processing 
+;
+__tx_thread_not_nested_save
+;    }
+;
+;    /* Otherwise, not nested, check to see if a thread was running.  */
+;    else if (_tx_thread_current_ptr)
+;    {
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        ; Pickup current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_idle_system_save        ; If so, interrupt occured in 
+                                                ;   scheduling loop - nothing needs saving!
+;
+;    /* Save minimal context of interrupted thread.  */
+;
+    MRS     r2, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r2, r10, r12, lr}             ; Store other registers
+;
+;    /* Save the current stack pointer in the thread's control block.  */
+;    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+;
+;    /* Switch to the system stack.  */
+;    sp =  _tx_thread_system_stack_ptr;
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+#endif
+
+    B       __tx_irq_processing_return          ; Continue IRQ processing 
+;
+;    }
+;    else
+;    {
+;
+__tx_thread_idle_system_save
+;
+;    /* Interrupt occurred in the scheduling loop.  */
+;
+;    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+;       processing.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+#endif
+
+    ADD     sp, sp, #16                         ; Recover saved registers
+    B       __tx_irq_processing_return          ; Continue IRQ processing  
+;
+;    }
+;}
+;
+
+;
+;
+    END
+
diff --git a/ports/cortex_r4/iar/src/tx_thread_interrupt_control.s b/ports/cortex_r4/iar/src/tx_thread_interrupt_control.s
new file mode 100644
index 00000000..934de0dd
--- /dev/null
+++ b/ports/cortex_r4/iar/src/tx_thread_interrupt_control.s
@@ -0,0 +1,97 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+
+INT_MASK        DEFINE      0x80                ; Interrupt bit mask
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_interrupt_control                       Cortex-R4/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for changing the interrupt lockout     */ 
+;/*    posture of the system.                                              */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    new_posture                           New interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    old_posture                           Old interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    Application Code                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_control(UINT new_posture)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_interrupt_control
+    ARM
+_tx_thread_interrupt_control
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    MRS     r3, CPSR                            ; Pickup current CPSR
+    BIC     r1, r3, #INT_MASK                   ; Clear interrupt lockout bits
+    ORR     r1, r1, r0                          ; Or-in new interrupt lockout bits
+;
+;    /* Apply the new interrupt posture.  */
+;
+    MSR     CPSR_cxsf, r1                       ; Setup new CPSR
+    AND     r0, r3, #INT_MASK                   ; Return previous interrupt mask
+    
+    BX      lr                                  ; Return to caller
+;
+;}
+;
+;
+    END
diff --git a/ports/cortex_r4/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_r4/iar/src/tx_thread_interrupt_disable.s
new file mode 100644
index 00000000..64c26b4b
--- /dev/null
+++ b/ports/cortex_r4/iar/src/tx_thread_interrupt_disable.s
@@ -0,0 +1,89 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+DISABLE_INTS    DEFINE      0x80                ; IRQ interrupts disabled
+;
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_interrupt_disable                       Cortex-R4/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for disabling interrupts               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    old_posture                           Old interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    Application Code                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_disable(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC _tx_thread_interrupt_disable
+    ARM
+_tx_thread_interrupt_disable??rA
+_tx_thread_interrupt_disable
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    MRS     r0, CPSR                            ; Pickup current CPSR
+    CPSID   i                                   ; Mask interrupts
+    BX      lr                                  ; Return to caller
+;}
+;
+;
+    END
diff --git a/ports/cortex_r4/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_r4/iar/src/tx_thread_interrupt_restore.s
new file mode 100644
index 00000000..f128b115
--- /dev/null
+++ b/ports/cortex_r4/iar/src/tx_thread_interrupt_restore.s
@@ -0,0 +1,84 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_interrupt_restore                       Cortex-R4/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for restoring interrupts to the state  */ 
+;/*    returned by a previous _tx_thread_interrupt_disable call.           */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    old_posture                           Old interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    Application Code                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;void   _tx_thread_interrupt_restore(UINT old_posture)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_interrupt_restore
+    ARM
+_tx_thread_interrupt_restore
+;
+;    /* Apply the new interrupt posture.  */
+;
+    MSR     CPSR_cxsf, r0                       ; Setup new CPSR
+
+    BX      lr                                  ; Return to caller
+;}
+;
+    END
diff --git a/ports/cortex_r4/iar/src/tx_thread_irq_nesting_end.s b/ports/cortex_r4/iar/src/tx_thread_irq_nesting_end.s
new file mode 100644
index 00000000..04bc7792
--- /dev/null
+++ b/ports/cortex_r4/iar/src/tx_thread_irq_nesting_end.s
@@ -0,0 +1,99 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+IRQ_MODE        DEFINE  0x12                    ; IRQ mode
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_irq_nesting_end                         Cortex-R4/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is called by the application from IRQ mode after      */ 
+;/*    _tx_thread_irq_nesting_start has been called and switches the IRQ   */ 
+;/*    processing from system mode back to IRQ mode prior to the ISR       */ 
+;/*    calling _tx_thread_context_restore.  Note that this function        */ 
+;/*    assumes the system stack pointer is in the same position after      */ 
+;/*    nesting start function was called.                                  */ 
+;/*                                                                        */ 
+;/*    This function assumes that the system mode stack pointer was setup  */ 
+;/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+;/*                                                                        */ 
+;/*    This function returns with IRQ interrupts disabled.                 */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_irq_nesting_end(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_irq_nesting_end
+    ARM
+_tx_thread_irq_nesting_end
+    MOV     r3, lr                              ; Save ISR return address
+    CPSID   i                                   ; Disable interrupts
+    POP     {lr}                                ; Pickup saved lr
+    CPS     #IRQ_MODE                           ; Switch to IRQ mode
+    MOV     pc, r3                              ; Return to ISR
+;}
+;
+;
+    END
+
diff --git a/ports/cortex_r4/iar/src/tx_thread_irq_nesting_start.s b/ports/cortex_r4/iar/src/tx_thread_irq_nesting_start.s
new file mode 100644
index 00000000..21dc597b
--- /dev/null
+++ b/ports/cortex_r4/iar/src/tx_thread_irq_nesting_start.s
@@ -0,0 +1,96 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+SYS_MODE        DEFINE  0x1F                    ; System mode
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_irq_nesting_start                       Cortex-R4/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is called by the application from IRQ mode after      */ 
+;/*    _tx_thread_context_save has been called and switches the IRQ        */ 
+;/*    processing to the system mode so nested IRQ interrupt processing    */ 
+;/*    is possible (system mode has its own "lr" register).  Note that     */ 
+;/*    this function assumes that the system mode stack pointer was setup  */ 
+;/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+;/*                                                                        */ 
+;/*    This function returns with IRQ interrupts enabled.                  */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_irq_nesting_start(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_irq_nesting_start
+    ARM
+_tx_thread_irq_nesting_start
+    MOV     r3, lr                              ; Save ISR return address
+    CPS     #SYS_MODE                           ; Enter SYS mode
+    PUSH    {lr}                                ; Save system mode lr on the system mode stack
+    CPSIE   i                                   ; Enable interrupts
+    MOV     pc, r3                              ; Return to ISR
+;}
+;
+;
+    END
+
diff --git a/ports/cortex_r4/iar/src/tx_thread_schedule.s b/ports/cortex_r4/iar/src/tx_thread_schedule.s
new file mode 100644
index 00000000..58092c84
--- /dev/null
+++ b/ports/cortex_r4/iar/src/tx_thread_schedule.s
@@ -0,0 +1,220 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    EXTERN     _tx_thread_execute_ptr
+    EXTERN     _tx_thread_current_ptr
+    EXTERN     _tx_timer_time_slice
+    EXTERN     _tx_execution_thread_enter
+;
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                                Cortex-R4/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function waits for a thread control block pointer to appear in */ 
+;/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */ 
+;/*    in the variable, the corresponding thread is resumed.               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_kernel_enter          ThreadX entry function         */ 
+;/*    _tx_thread_system_return             Return to system from thread   */ 
+;/*    _tx_thread_context_restore           Restore thread's context       */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_schedule(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_schedule
+    ARM
+_tx_thread_schedule??rA
+_tx_thread_schedule
+;
+;    /* Enable interrupts.  */
+;
+    CPSIE   i                                   ; Enable IRQ interrupts
+
+;
+;    /* Wait for a thread to execute.  */
+;    do
+;    {
+    LDR     r1, =_tx_thread_execute_ptr         ; Address of thread execute ptr
+;
+__tx_thread_schedule_loop
+;
+    LDR     r0, [r1, #0]                        ; Pickup next thread to execute
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_schedule_loop           ; If so, keep looking for a thread
+;
+;    }
+;    while(_tx_thread_execute_ptr == TX_NULL);
+;    
+;    /* Yes! We have a thread to execute.  Lockout interrupts and
+;       transfer control to it.  */
+;
+    CPSID   i                                   ; Disable interrupts
+;
+;    /* Setup the current thread pointer.  */
+;    _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+;
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread 
+    STR     r0, [r1, #0]                        ; Setup current thread pointer
+;
+;    /* Increment the run count for this thread.  */
+;    _tx_thread_current_ptr -> tx_thread_run_count++;
+;
+    LDR     r2, [r0, #4]                        ; Pickup run counter
+    LDR     r3, [r0, #24]                       ; Pickup time-slice for this thread
+    ADD     r2, r2, #1                          ; Increment thread run-counter
+    STR     r2, [r0, #4]                        ; Store the new run counter
+;
+;    /* Setup time-slice, if present.  */
+;    _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+;
+    LDR     r2, =_tx_timer_time_slice           ; Pickup address of time slice 
+                                                ;   variable
+    LDR     sp, [r0, #8]                        ; Switch stack pointers
+    STR     r3, [r2, #0]                        ; Setup time-slice
+;
+;    /* Switch to the thread's stack.  */
+;    sp =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;
+;
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread entry function to indicate the thread is executing.  */
+;
+    MOV     r5, r0                              ; Save r0
+    BL      _tx_execution_thread_enter          ; Call the thread execution enter function
+    MOV     r0, r5                              ; Restore r0
+#endif
+;
+;    /* Determine if an interrupt frame or a synchronous task suspension frame
+;   is present.  */
+;
+    LDMIA   sp!, {r4, r5}                       ; Pickup the stack type and saved CPSR
+    CMP     r4, #0                              ; Check for synchronous context switch
+    BEQ     _tx_solicited_return
+    MSR     SPSR_cxsf, r5                       ; Setup SPSR for return
+#ifdef __ARMVFP__
+    LDR     r1, [r0, #144]                      ; Pickup the VFP enabled flag
+    CMP     r1, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_interrupt_vfp_restore      ; No, skip VFP interrupt restore
+    VLDMIA  sp!, {D0-D15}                       ; Recover D0-D15
+    LDR     r4, [sp], #4                        ; Pickup FPSCR
+    VMSR    FPSCR, r4                           ; Restore FPSCR
+_tx_skip_interrupt_vfp_restore:
+#endif
+    LDMIA   sp!, {r0-r12, lr, pc}^              ; Return to point of thread interrupt
+
+_tx_solicited_return:
+#ifdef __ARMVFP__
+    LDR     r1, [r0, #144]                      ; Pickup the VFP enabled flag
+    CMP     r1, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_solicited_vfp_restore      ; No, skip VFP solicited restore
+    VLDMIA  sp!, {D8-D15}                       ; Recover D8-D15
+    LDR     r4, [sp], #4                        ; Pickup FPSCR
+    VMSR    FPSCR, r4                           ; Restore FPSCR
+_tx_skip_solicited_vfp_restore:
+#endif
+    MOV     r0, r5                              ; Move CPSR to scratch register
+    LDMIA   sp!, {r4-r11, lr}                   ; Return to thread synchronously
+    MSR     CPSR_cxsf, r0                       ; Recover CPSR
+
+    BX      lr                                  ; Return to caller
+;
+;}
+;
+
+#ifdef __ARMVFP__
+    PUBLIC  tx_thread_vfp_enable
+    CODE32
+tx_thread_vfp_enable??rA    
+tx_thread_vfp_enable
+    MRS     r2, CPSR                            ; Pickup the CPSR
+    CPSID   i                                   ; Disable IRQ interrupts
+    LDR     r0, =_tx_thread_current_ptr         ; Build current thread pointer address
+    LDR     r1, [r0]                            ; Pickup current thread pointer
+    CMP     r1, #0                              ; Check for NULL thread pointer
+    BEQ     __tx_no_thread_to_enable            ; If NULL, skip VFP enable
+    MOV     r0, #1                              ; Build enable value
+    STR     r0, [r1, #144]                      ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
+__tx_no_thread_to_enable:
+    MSR     CPSR_cxsf, r2                       ; Recover CPSR
+    BX      LR                                  ; Return to caller
+
+    PUBLIC  tx_thread_vfp_disable
+    CODE32
+tx_thread_vfp_disable??rA    
+tx_thread_vfp_disable
+    MRS     r2, CPSR                            ; Pickup the CPSR
+    CPSID   i                                   ; Disable IRQ interrupts
+    LDR     r0, =_tx_thread_current_ptr         ; Build current thread pointer address
+    LDR     r1, [r0]                            ; Pickup current thread pointer
+    CMP     r1, #0                              ; Check for NULL thread pointer
+    BEQ     __tx_no_thread_to_disable           ; If NULL, skip VFP disable
+    MOV     r0, #0                              ; Build disable value
+    STR     r0, [r1, #144]                      ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
+__tx_no_thread_to_disable:
+    MSR     CPSR_cxsf, r2                       ; Recover CPSR
+    BX      LR                                  ; Return to caller
+#endif
+
+    END
+
diff --git a/ports/cortex_r4/iar/src/tx_thread_stack_build.s b/ports/cortex_r4/iar/src/tx_thread_stack_build.s
new file mode 100644
index 00000000..253006fc
--- /dev/null
+++ b/ports/cortex_r4/iar/src/tx_thread_stack_build.s
@@ -0,0 +1,151 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+SVC_MODE        DEFINE  0x13                    ; SVC mode
+CPSR_MASK       DEFINE  0x9F                    ; Mask initial CPSR, IRQ ints enabled
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_stack_build                             Cortex-R4/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function builds a stack frame on the supplied thread's stack.  */ 
+;/*    The stack frame results in a fake interrupt return to the supplied  */ 
+;/*    function pointer.                                                   */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    thread_ptr                            Pointer to thread control blk */ 
+;/*    function_ptr                          Pointer to return function    */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_thread_create                     Create thread service         */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_stack_build
+    
+    ARM
+_tx_thread_stack_build
+;
+;       
+;    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+;       on the Cortex-R4 should look like the following after it is built:
+;       
+;       Stack Top:      1           Interrupt stack frame type
+;                       CPSR        Initial value for CPSR
+;                       a1 (r0)     Initial value for a1
+;                       a2 (r1)     Initial value for a2
+;                       a3 (r2)     Initial value for a3
+;                       a4 (r3)     Initial value for a4
+;                       v1 (r4)     Initial value for v1
+;                       v2 (r5)     Initial value for v2
+;                       v3 (r6)     Initial value for v3
+;                       v4 (r7)     Initial value for v4
+;                       v5 (r8)     Initial value for v5
+;                       sb (r9)     Initial value for sb
+;                       sl (r10)    Initial value for sl
+;                       fp (r11)    Initial value for fp
+;                       ip (r12)    Initial value for ip
+;                       lr (r14)    Initial value for lr
+;                       pc (r15)    Initial value for pc
+;                       0           For stack backtracing
+;
+;    Stack Bottom: (higher memory address)  */
+;
+    LDR     r2, [r0, #16]                       ; Pickup end of stack area
+    BIC     r2, r2, #7                          ; Ensure 8-byte alignment
+    SUB     r2, r2, #76                         ; Allocate space for the stack frame
+;
+;    /* Actually build the stack frame.  */
+;
+    MOV     r3, #1                              ; Build interrupt stack type
+    STR     r3, [r2, #0]                        ; Store stack type
+    MOV     r3, #0                              ; Build initial register value
+    STR     r3, [r2, #8]                        ; Store initial r0
+    STR     r3, [r2, #12]                       ; Store initial r1
+    STR     r3, [r2, #16]                       ; Store initial r2
+    STR     r3, [r2, #20]                       ; Store initial r3
+    STR     r3, [r2, #24]                       ; Store initial r4
+    STR     r3, [r2, #28]                       ; Store initial r5
+    STR     r3, [r2, #32]                       ; Store initial r6
+    STR     r3, [r2, #36]                       ; Store initial r7
+    STR     r3, [r2, #40]                       ; Store initial r8
+    STR     r3, [r2, #44]                       ; Store initial r9
+    LDR     r3, [r0, #12]                       ; Pickup stack starting address
+    STR     r3, [r2, #48]                       ; Store initial r10 (sl)
+    MOV     r3, #0                              ; Build initial register value
+    STR     r3, [r2, #52]                       ; Store initial r11
+    STR     r3, [r2, #56]                       ; Store initial r12
+    STR     r3, [r2, #60]                       ; Store initial lr
+    STR     r1, [r2, #64]                       ; Store initial pc
+    STR     r3, [r2, #68]                       ; 0 for back-trace
+    MRS     r1, CPSR                            ; Pickup CPSR
+    BIC     r1, r1, #CPSR_MASK                  ; Mask mode bits of CPSR
+    ORR     r3, r1, #SVC_MODE                   ; Build CPSR, SVC mode, interrupts enabled
+    STR     r3, [r2, #4]                        ; Store initial CPSR
+;
+;    /* Setup stack pointer.  */
+;    thread_ptr -> tx_thread_stack_ptr =  r2;
+;
+    STR     r2, [r0, #8]                        ; Save stack pointer in thread's
+                                                ;   control block
+
+    BX      lr                                  ; Return to caller
+;}
+    END
+
diff --git a/ports/cortex_r4/iar/src/tx_thread_system_return.s b/ports/cortex_r4/iar/src/tx_thread_system_return.s
new file mode 100644
index 00000000..c0014a8b
--- /dev/null
+++ b/ports/cortex_r4/iar/src/tx_thread_system_return.s
@@ -0,0 +1,155 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+;
+    EXTERN      _tx_thread_current_ptr
+    EXTERN      _tx_timer_time_slice
+    EXTERN      _tx_thread_schedule
+    EXTERN      _tx_execution_thread_exit
+;
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_system_return                           Cortex-R4/IAR    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is target processor specific.  It is used to transfer */ 
+;/*    control from a thread back to the ThreadX system.  Only a           */ 
+;/*    minimal context is saved since the compiler assumes temp registers  */ 
+;/*    are going to get slicked by a function call anyway.                 */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                   Thread scheduling loop        */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ThreadX components                                                  */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_system_return(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_system_return
+    ARM
+_tx_thread_system_return??rA
+_tx_thread_system_return
+;
+;   /* Lockout interrupts.  */
+;
+    MRS     r1, CPSR                            ; Pickup the CPSR
+    CPSID   i                                   ; Disable interrupts
+;    /* Save minimal context on the stack.  */
+;
+    STMDB   sp!, {r4-r11, lr}                   ; Save minimal context
+    LDR     r5, =_tx_thread_current_ptr         ; Pickup address of current ptr
+    LDR     r6, [r5, #0]                        ; Pickup current thread pointer
+
+#ifdef __ARMVFP__
+    LDR     r0, [r6, #144]                      ; Pickup the VFP enabled flag
+    CMP     r0, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_solicited_vfp_save         ; No, skip VFP solicited save
+    VMRS    r4, FPSCR                           ; Pickup the FPSCR
+    STR     r4, [sp, #-4]!                      ; Save FPSCR
+    VSTMDB  sp!, {D8-D15}                       ; Save D8-D15
+_tx_skip_solicited_vfp_save:
+#endif
+
+    MOV     r0, #0                              ; Build a solicited stack type
+    STMDB   sp!, {r0-r1}                        ; Save type and CPSR
+;   
+;
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread exit function to indicate the thread is no longer executing.  */
+;
+    BL      _tx_execution_thread_exit           ; Call the thread exit function
+#endif
+
+    LDR     r2, =_tx_timer_time_slice           ; Pickup address of time slice
+    LDR     r1, [r2, #0]                        ; Pickup current time slice
+;
+;    /* Save current stack and switch to system stack.  */
+;    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+;    sp = _tx_thread_system_stack_ptr;
+;
+    STR     sp, [r6, #8]                        ; Save thread stack pointer
+;
+;    /* Determine if the time-slice is active.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    MOV     r4, #0                              ; Build clear value
+    CMP     r1, #0                              ; Is a time-slice active?
+    BEQ     __tx_thread_dont_save_ts            ; No, don't save the time-slice
+;
+;       /* Save time-slice for the thread and clear the current time-slice.  */
+;       _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+;       _tx_timer_time_slice =  0;
+;
+    STR     r4, [r2, #0]                        ; Clear time-slice
+    STR     r1, [r6, #24]                       ; Save current time-slice
+;
+;    }
+__tx_thread_dont_save_ts
+;
+;    /* Clear the current thread pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;
+    STR     r4, [r5, #0]                        ; Clear current thread pointer
+    B       _tx_thread_schedule                 ; Jump to scheduler!
+;
+;}
+    END
+
diff --git a/ports/cortex_r4/iar/src/tx_thread_vectored_context_save.s b/ports/cortex_r4/iar/src/tx_thread_vectored_context_save.s
new file mode 100644
index 00000000..07b5cc5f
--- /dev/null
+++ b/ports/cortex_r4/iar/src/tx_thread_vectored_context_save.s
@@ -0,0 +1,184 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Thread                                                              */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    EXTERN      _tx_thread_system_state
+    EXTERN      _tx_thread_current_ptr
+    EXTERN      _tx_execution_isr_enter
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_vectored_context_save                  Cortex-R4/IAR     */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function saves the context of an executing thread in the       */ 
+;/*    beginning of interrupt processing.  The function also ensures that  */ 
+;/*    the system stack is used upon return to the calling ISR.            */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_vectored_context_save(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_thread_vectored_context_save
+    ARM
+_tx_thread_vectored_context_save
+;
+;    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+;       out, we are in IRQ mode, the minimal context is already saved, and the
+;       lr register contains the return ISR address.  */
+;
+;    /* Check for a nested interrupt condition.  */
+;    if (_tx_thread_system_state++)
+;    {
+;
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3, #0]                        ; Pickup system state
+    CMP     r2, #0                              ; Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         ; Yes, not a nested context save
+;
+;    /* Nested interrupt condition.  */
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+;
+;    /* Note: Minimal context of interrupted thread is already saved.  */
+;
+;    /* Return to the ISR.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+#endif
+
+    BX      lr                                  ; Return to caller
+;
+__tx_thread_not_nested_save
+;    }
+;
+;    /* Otherwise, not nested, check to see if a thread was running.  */
+;    else if (_tx_thread_current_ptr)
+;    {
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        ; Pickup current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_idle_system_save        ; If so, interrupt occured in 
+                                                ;   scheduling loop - nothing needs saving!
+;
+;    /* Note: Minimal context of interrupted thread is already saved.  */
+;
+;    /* Save the current stack pointer in the thread's control block.  */
+;    _tx_thread_current_ptr -> tx_stack_ptr =  sp;
+;
+;    /* Switch to the system stack.  */
+;    sp =  _tx_thread_system_stack_ptr;
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+#endif
+
+    BX      lr                                  ; Return to caller
+;
+;    }
+;    else
+;    {
+;
+__tx_thread_idle_system_save
+;
+;    /* Interrupt occurred in the scheduling loop.  */
+;
+;    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+;       processing.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+#endif
+
+    ADD     sp, sp, #32                         ; Recover saved registers
+    MOV     pc, lr                              ; Return to caller
+;
+;    }
+;}
+    END
+
diff --git a/ports/cortex_r4/iar/src/tx_timer_interrupt.s b/ports/cortex_r4/iar/src/tx_timer_interrupt.s
new file mode 100644
index 00000000..420e42ad
--- /dev/null
+++ b/ports/cortex_r4/iar/src/tx_timer_interrupt.s
@@ -0,0 +1,256 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */ 
+;/**   Timer                                                               */ 
+;/**                                                                       */ 
+;/**************************************************************************/ 
+;/**************************************************************************/ 
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_timer.h"
+;#include "tx_thread.h"
+;
+;
+;Define Assembly language external references...
+;
+    EXTERN      _tx_timer_time_slice
+    EXTERN      _tx_timer_system_clock
+    EXTERN      _tx_timer_current_ptr
+    EXTERN      _tx_timer_list_start
+    EXTERN      _tx_timer_list_end
+    EXTERN      _tx_timer_expired_time_slice
+    EXTERN      _tx_timer_expired
+    EXTERN      _tx_thread_time_slice
+    EXTERN      _tx_timer_expiration_process
+;
+;
+;
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_timer_interrupt                               Cortex-R4/IAR     */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function processes the hardware timer interrupt.  This         */ 
+;/*    processing includes incrementing the system clock and checking for  */ 
+;/*    time slice and/or timer expiration.  If either is found, the        */ 
+;/*    interrupt context save/restore functions are called along with the  */ 
+;/*    expiration functions.                                               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_timer_expiration_process          Timer expiration processing   */ 
+;/*    _tx_thread_time_slice                 Time-slice interrupted thread */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    interrupt vector                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_timer_interrupt(VOID)
+;{
+    RSEG    .text:CODE:NOROOT(2)
+    PUBLIC  _tx_timer_interrupt
+    ARM
+_tx_timer_interrupt
+;
+;    /* Upon entry to this routine, it is assumed that context save has already
+;       been called, and therefore the compiler scratch registers are available
+;       for use.  */
+;
+;    /* Increment the system clock.  */
+;    _tx_timer_system_clock++;
+;
+    LDR     r1, =_tx_timer_system_clock         ; Pickup address of system clock
+    LDR     r0, [r1, #0]                        ; Pickup system clock
+    ADD     r0, r0, #1                          ; Increment system clock
+    STR     r0, [r1, #0]                        ; Store new system clock
+;
+;    /* Test for time-slice expiration.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    LDR     r3, =_tx_timer_time_slice           ; Pickup address of time-slice 
+    LDR     r2, [r3, #0]                        ; Pickup time-slice
+    CMP     r2, #0                              ; Is it non-active?
+    BEQ     __tx_timer_no_time_slice            ; Yes, skip time-slice processing
+;
+;       /* Decrement the time_slice.  */
+;       _tx_timer_time_slice--;
+;
+    SUB     r2, r2, #1                          ; Decrement the time-slice
+    STR     r2, [r3, #0]                        ; Store new time-slice value
+;
+;       /* Check for expiration.  */
+;       if (__tx_timer_time_slice == 0)
+;
+    CMP     r2, #0                              ; Has it expired?
+    BNE     __tx_timer_no_time_slice            ; No, skip expiration processing
+;
+;       /* Set the time-slice expired flag.  */
+;       _tx_timer_expired_time_slice =  TX_TRUE;
+;
+    LDR     r3, =_tx_timer_expired_time_slice   ; Pickup address of expired flag
+    MOV     r0, #1                              ; Build expired value
+    STR     r0, [r3, #0]                        ; Set time-slice expiration flag
+;
+;    }
+;
+__tx_timer_no_time_slice
+;
+;    /* Test for timer expiration.  */
+;    if (*_tx_timer_current_ptr)
+;    {
+;
+    LDR     r1, =_tx_timer_current_ptr          ; Pickup current timer pointer addr
+    LDR     r0, [r1, #0]                        ; Pickup current timer
+    LDR     r2, [r0, #0]                        ; Pickup timer list entry
+    CMP     r2, #0                              ; Is there anything in the list?
+    BEQ     __tx_timer_no_timer                 ; No, just increment the timer
+;
+;        /* Set expiration flag.  */
+;        _tx_timer_expired =  TX_TRUE;
+;
+    LDR     r3, =_tx_timer_expired              ; Pickup expiration flag address
+    MOV     r2, #1                              ; Build expired value
+    STR     r2, [r3, #0]                        ; Set expired flag
+    B       __tx_timer_done                     ; Finished timer processing
+;
+;    }
+;    else
+;    {
+__tx_timer_no_timer
+;
+;        /* No timer expired, increment the timer pointer.  */
+;        _tx_timer_current_ptr++;
+;
+    ADD     r0, r0, #4                          ; Move to next timer
+;
+;        /* Check for wrap-around.  */
+;        if (_tx_timer_current_ptr == _tx_timer_list_end)
+;
+    LDR     r3, =_tx_timer_list_end             ; Pickup addr of timer list end
+    LDR     r2, [r3, #0]                        ; Pickup list end
+    CMP     r0, r2                              ; Are we at list end?
+    BNE     __tx_timer_skip_wrap                ; No, skip wrap-around logic
+;
+;            /* Wrap to beginning of list.  */
+;            _tx_timer_current_ptr =  _tx_timer_list_start;
+;
+    LDR     r3, =_tx_timer_list_start           ; Pickup addr of timer list start
+    LDR     r0, [r3, #0]                        ; Set current pointer to list start
+;
+__tx_timer_skip_wrap
+;
+    STR     r0, [r1, #0]                        ; Store new current timer pointer
+;    }
+;
+__tx_timer_done
+;
+;
+;    /* See if anything has expired.  */
+;    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+;    {
+;
+    LDR     r3, =_tx_timer_expired_time_slice   ; Pickup addr of expired flag
+    LDR     r2, [r3, #0]                        ; Pickup time-slice expired flag
+    CMP     r2, #0                              ; Did a time-slice expire?
+    BNE     __tx_something_expired              ; If non-zero, time-slice expired
+    LDR     r1, =_tx_timer_expired              ; Pickup addr of other expired flag
+    LDR     r0, [r1, #0]                        ; Pickup timer expired flag
+    CMP     r0, #0                              ; Did a timer expire?
+    BEQ     __tx_timer_nothing_expired          ; No, nothing expired
+;
+__tx_something_expired
+;
+;
+    STMDB   sp!, {r0, lr}                       ; Save the lr register on the stack
+                                                ;   and save r0 just to keep 8-byte alignment
+;
+;    /* Did a timer expire?  */
+;    if (_tx_timer_expired)
+;    {
+;
+    LDR     r1, =_tx_timer_expired              ; Pickup addr of expired flag
+    LDR     r0, [r1, #0]                        ; Pickup timer expired flag
+    CMP     r0, #0                              ; Check for timer expiration
+    BEQ     __tx_timer_dont_activate            ; If not set, skip timer activation
+;
+;        /* Process timer expiration.  */
+;        _tx_timer_expiration_process();
+;
+    BL      _tx_timer_expiration_process        ; Call the timer expiration handling routine
+;
+;    }
+__tx_timer_dont_activate
+;
+;    /* Did time slice expire?  */
+;    if (_tx_timer_expired_time_slice)
+;    {
+;
+    LDR     r3, =_tx_timer_expired_time_slice   ; Pickup addr of time-slice expired 
+    LDR     r2, [r3, #0]                        ; Pickup the actual flag
+    CMP     r2, #0                              ; See if the flag is set
+    BEQ     __tx_timer_not_ts_expiration        ; No, skip time-slice processing
+;
+;        /* Time slice interrupted thread.  */
+;        _tx_thread_time_slice(); 
+
+    BL      _tx_thread_time_slice               ; Call time-slice processing
+;
+;    }
+;
+__tx_timer_not_ts_expiration
+;
+;
+    LDMIA   sp!, {r0, lr}                       ; Recover lr register (r0 is just there for
+                                                ;   the 8-byte stack alignment
+;
+;    }
+;
+__tx_timer_nothing_expired
+;
+    BX      lr                                  ; Return to caller
+;
+;}
+    END
+
diff --git a/ports/cortex_r5/ac5/example_build/build_threadx.bat b/ports/cortex_r5/ac5/example_build/build_threadx.bat
new file mode 100644
index 00000000..c30b6643
--- /dev/null
+++ b/ports/cortex_r5/ac5/example_build/build_threadx.bat
@@ -0,0 +1,238 @@
+del tx.a
+armasm -g --cpu=cortex-r5 --apcs=interwork tx_initialize_low_level.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_stack_build.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_schedule.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_system_return.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_context_save.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_context_restore.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_interrupt_control.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_timer_interrupt.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_fiq_context_restore.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_fiq_context_save.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_fiq_nesting_end.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_fiq_nesting_start.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_interrupt_disable.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_interrupt_restore.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_irq_nesting_end.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_irq_nesting_start.s
+armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_vectored_context_save.s
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c
+armcc -g --cpu=cortex-r5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c
+armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
+armar -r tx.a tx_initialize_low_level.o tx_thread_fiq_context_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_end.o tx_thread_fiq_nesting_start.o tx_thread_interrupt_disable.o 
+armar -r tx.a tx_thread_interrupt_restore.o tx_thread_irq_nesting_end.o tx_thread_irq_nesting_start.o
+armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
+armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
+armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
+armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
+armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
+armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
+armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
+armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
+armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
+armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o 
+armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
+armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
+armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
+armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
+armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
+armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
+armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
+armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
+armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
+armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
+armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o 
+armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
+armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
+armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o 
+armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o 
+armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o 
+armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
+armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
+armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
+armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
+armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o 
+armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
+armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o
diff --git a/ports/cortex_r5/ac5/example_build/build_threadx_sample.bat b/ports/cortex_r5/ac5/example_build/build_threadx_sample.bat
new file mode 100644
index 00000000..3adb3bab
--- /dev/null
+++ b/ports/cortex_r5/ac5/example_build/build_threadx_sample.bat
@@ -0,0 +1,4 @@
+armasm -g --cpu=cortex-r5 --apcs=interwork tx_initialize_low_level.s
+armcc -c -g --cpu=cortex-r5 -I../../../../common/inc -I../inc sample_threadx.c
+armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --rw-base=0x20000000 --first tx_initialize_low_level.o(Init) --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a
+
diff --git a/ports/cortex_r5/ac5/example_build/sample_threadx.c b/ports/cortex_r5/ac5/example_build/sample_threadx.c
new file mode 100644
index 00000000..418ec634
--- /dev/null
+++ b/ports/cortex_r5/ac5/example_build/sample_threadx.c
@@ -0,0 +1,369 @@
+/* This is a small demo of the high-performance ThreadX kernel.  It includes examples of eight
+   threads of different priorities, using a message queue, semaphore, mutex, event flags group, 
+   byte pool, and block pool.  */
+
+#include "tx_api.h"
+
+#define DEMO_STACK_SIZE         1024
+#define DEMO_BYTE_POOL_SIZE     9120
+#define DEMO_BLOCK_POOL_SIZE    100
+#define DEMO_QUEUE_SIZE         100
+
+
+/* Define the ThreadX object control blocks...  */
+
+TX_THREAD               thread_0;
+TX_THREAD               thread_1;
+TX_THREAD               thread_2;
+TX_THREAD               thread_3;
+TX_THREAD               thread_4;
+TX_THREAD               thread_5;
+TX_THREAD               thread_6;
+TX_THREAD               thread_7;
+TX_QUEUE                queue_0;
+TX_SEMAPHORE            semaphore_0;
+TX_MUTEX                mutex_0;
+TX_EVENT_FLAGS_GROUP    event_flags_0;
+TX_BYTE_POOL            byte_pool_0;
+TX_BLOCK_POOL           block_pool_0;
+
+
+/* Define the counters used in the demo application...  */
+
+ULONG                   thread_0_counter;
+ULONG                   thread_1_counter;
+ULONG                   thread_1_messages_sent;
+ULONG                   thread_2_counter;
+ULONG                   thread_2_messages_received;
+ULONG                   thread_3_counter;
+ULONG                   thread_4_counter;
+ULONG                   thread_5_counter;
+ULONG                   thread_6_counter;
+ULONG                   thread_7_counter;
+
+
+/* Define thread prototypes.  */
+
+void    thread_0_entry(ULONG thread_input);
+void    thread_1_entry(ULONG thread_input);
+void    thread_2_entry(ULONG thread_input);
+void    thread_3_and_4_entry(ULONG thread_input);
+void    thread_5_entry(ULONG thread_input);
+void    thread_6_and_7_entry(ULONG thread_input);
+
+
+/* Define main entry point.  */
+
+int main()
+{
+
+    /* Enter the ThreadX kernel.  */
+    tx_kernel_enter();
+}
+
+
+/* Define what the initial system looks like.  */
+
+void    tx_application_define(void *first_unused_memory)
+{
+
+CHAR    *pointer = TX_NULL;
+
+
+    /* Create a byte memory pool from which to allocate the thread stacks.  */
+    tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE);
+
+    /* Put system definition stuff in here, e.g. thread creates and other assorted
+       create information.  */
+
+    /* Allocate the stack for thread 0.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create the main thread.  */
+    tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,  
+            pointer, DEMO_STACK_SIZE, 
+            1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+
+    /* Allocate the stack for thread 1.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 1 and 2. These threads pass information through a ThreadX 
+       message queue.  It is also interesting to note that these threads have a time
+       slice.  */
+    tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 2.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,  
+            pointer, DEMO_STACK_SIZE, 
+            16, 16, 4, TX_AUTO_START);
+
+    /* Allocate the stack for thread 3.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 3 and 4.  These threads compete for a ThreadX counting semaphore.  
+       An interesting thing here is that both threads share the same instruction area.  */
+    tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 4.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 5.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create thread 5.  This thread simply pends on an event flag which will be set
+       by thread_0.  */
+    tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,  
+            pointer, DEMO_STACK_SIZE, 
+            4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 6.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    /* Create threads 6 and 7.  These threads compete for a ThreadX mutex.  */
+    tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the stack for thread 7.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
+
+    tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,  
+            pointer, DEMO_STACK_SIZE, 
+            8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
+
+    /* Allocate the message queue.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
+
+    /* Create the message queue shared by threads 1 and 2.  */
+    tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
+
+    /* Create the semaphore used by threads 3 and 4.  */
+    tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
+
+    /* Create the event flags group used by threads 1 and 5.  */
+    tx_event_flags_create(&event_flags_0, "event flags 0");
+
+    /* Create the mutex used by thread 6 and 7 without priority inheritance.  */
+    tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
+
+    /* Allocate the memory for a small block pool.  */
+    tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
+
+    /* Create a block memory pool to allocate a message buffer from.  */
+    tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
+
+    /* Allocate a block and release the block memory.  */
+    tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
+
+    /* Release the block back to the pool.  */
+    tx_block_release(pointer);
+}
+
+
+
+/* Define the test threads.  */
+
+void    thread_0_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sits in while-forever-sleep loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_0_counter++;
+
+        /* Sleep for 10 ticks.  */
+        tx_thread_sleep(10);
+
+        /* Set event flag 0 to wakeup thread 5.  */
+        status =  tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_1_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This thread simply sends messages to a queue shared by thread 2.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_1_counter++;
+
+        /* Send message to queue 0.  */
+        status =  tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
+
+        /* Check completion status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Increment the message sent.  */
+        thread_1_messages_sent++;
+    }
+}
+
+
+void    thread_2_entry(ULONG thread_input)
+{
+
+ULONG   received_message;
+UINT    status;
+
+    /* This thread retrieves messages placed on the queue by thread 1.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_2_counter++;
+
+        /* Retrieve a message from the queue.  */
+        status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
+
+        /* Check completion status and make sure the message is what we 
+           expected.  */
+        if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
+            break;
+        
+        /* Otherwise, all is okay.  Increment the received message count.  */
+        thread_2_messages_received++;
+    }
+}
+
+
+void    thread_3_and_4_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 3 and thread 4.  As the loop
+       below shows, these function compete for ownership of semaphore_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 3)
+            thread_3_counter++;
+        else
+            thread_4_counter++;
+
+        /* Get the semaphore with suspension.  */
+        status =  tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the semaphore.  */
+        tx_thread_sleep(2);
+
+        /* Release the semaphore.  */
+        status =  tx_semaphore_put(&semaphore_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
+
+
+void    thread_5_entry(ULONG thread_input)
+{
+
+UINT    status;
+ULONG   actual_flags;
+
+
+    /* This thread simply waits for an event in a forever loop.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        thread_5_counter++;
+
+        /* Wait for event flag 0.  */
+        status =  tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, 
+                                                &actual_flags, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if ((status != TX_SUCCESS) || (actual_flags != 0x1))
+            break;
+    }
+}
+
+
+void    thread_6_and_7_entry(ULONG thread_input)
+{
+
+UINT    status;
+
+
+    /* This function is executed from thread 6 and thread 7.  As the loop
+       below shows, these function compete for ownership of mutex_0.  */
+    while(1)
+    {
+
+        /* Increment the thread counter.  */
+        if (thread_input == 6)
+            thread_6_counter++;
+        else
+            thread_7_counter++;
+
+        /* Get the mutex with suspension.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Get the mutex again with suspension.  This shows
+           that an owning thread may retrieve the mutex it
+           owns multiple times.  */
+        status =  tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Sleep for 2 ticks to hold the mutex.  */
+        tx_thread_sleep(2);
+
+        /* Release the mutex.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+
+        /* Release the mutex again.  This will actually 
+           release ownership since it was obtained twice.  */
+        status =  tx_mutex_put(&mutex_0);
+
+        /* Check status.  */
+        if (status != TX_SUCCESS)
+            break;
+    }
+}
diff --git a/ports/cortex_r5/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_r5/ac5/example_build/tx_initialize_low_level.s
new file mode 100644
index 00000000..b4cbb423
--- /dev/null
+++ b/ports/cortex_r5/ac5/example_build/tx_initialize_low_level.s
@@ -0,0 +1,394 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Initialize                                                          */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_initialize.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+DISABLE_INTS    EQU     0xC0                    ; Disable IRQ & FIQ interrupts
+FIQ_MODE        EQU     0xD1                    ; FIQ mode
+IRQ_MODE        EQU     0xD2                    ; IRQ mode
+SVC_MODE        EQU     0xD3                    ; SVC mode
+SYS_MODE        EQU     0xDF                    ; SYS mode
+    ELSE
+DISABLE_INTS    EQU     0x80                    ; Disable IRQ interrupts
+FIQ_MODE        EQU     0x91                    ; FIQ mode
+IRQ_MODE        EQU     0x92                    ; IRQ mode
+SVC_MODE        EQU     0x93                    ; SVC mode
+SYS_MODE        EQU     0x9F                    ; SYS mode
+    ENDIF
+HEAP_SIZE       EQU     4096                    ; Heap size
+FIQ_STACK_SIZE  EQU     512                     ; FIQ stack size
+SYS_STACK_SIZE  EQU     1024                    ; SYS stack size (used for nested interrupts)
+IRQ_STACK_SIZE  EQU     1024                    ; IRQ stack size
+;
+;
+    IMPORT      _tx_thread_system_stack_ptr
+    IMPORT      _tx_initialize_unused_memory
+    IMPORT      _tx_thread_context_save
+    IMPORT      _tx_thread_context_restore
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+    IMPORT      _tx_thread_fiq_context_save
+    IMPORT      _tx_thread_fiq_context_restore
+    ENDIF
+    IF  :DEF:TX_ENABLE_IRQ_NESTING
+    IMPORT      _tx_thread_irq_nesting_start
+    IMPORT      _tx_thread_irq_nesting_end
+    ENDIF
+    IF  :DEF:TX_ENABLE_FIQ_NESTING
+    IMPORT      _tx_thread_fiq_nesting_start
+    IMPORT      _tx_thread_fiq_nesting_end
+    ENDIF
+    IMPORT      _tx_timer_interrupt
+    IMPORT      __main
+    IMPORT      _tx_version_id
+    IMPORT      _tx_build_options
+    IMPORT      |Image$$ZI$$Limit|
+;
+;
+        AREA  Init, CODE, READONLY
+;
+;/* Define the default Cortex-R5 vector area.  This should be located or copied to 0.  */
+;
+    EXPORT  __vectors
+__vectors
+    LDR     pc,=__main                          ; Reset goes to startup function
+    LDR     pc,=__tx_undefined                  ; Undefined handler
+    LDR     pc,=__tx_swi_interrupt              ; Software interrupt handler
+    LDR     pc,=__tx_prefetch_handler           ; Prefetch exception handler
+    LDR     pc,=__tx_abort_handler              ; Abort exception handler
+    LDR     pc,=__tx_reserved_handler           ; Reserved exception handler
+    LDR     pc,=__tx_irq_handler                ; IRQ interrupt handler
+    LDR     pc,=__tx_fiq_handler                ; FIQ interrupt handler
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_low_level                           Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for any low-level processor            */ 
+;/*    initialization, including setting up interrupt vectors, setting     */ 
+;/*    up a periodic timer interrupt source, saving the system stack       */ 
+;/*    pointer for use in ISR processing later, and finding the first      */ 
+;/*    available RAM memory address for tx_application_define.             */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_kernel_enter           ThreadX entry function        */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_initialize_low_level(VOID)
+;{
+    EXPORT  _tx_initialize_low_level
+_tx_initialize_low_level
+;
+;
+;    /****** NOTE ****** We must be in SVC MODE at this point.  Some monitors
+;       enter this routine in USER mode and require a software interrupt to
+;       change into SVC mode.  */
+;
+    LDR     r1, =|Image$$ZI$$Limit|             ; Get end of non-initialized RAM area
+    LDR     r2, =HEAP_SIZE                      ; Pickup the heap size
+    ADD     r1, r2, r1                          ; Setup heap limit
+    ADD     r1, r1, #4                          ; Setup stack limit
+;
+    IF :DEF:TX_ENABLE_IRQ_NESTING
+;    /* Setup the system mode stack for nested interrupt support  */
+    LDR     r2, =SYS_STACK_SIZE                 ; Pickup stack size
+    MOV     r3, #SYS_MODE                       ; Build SYS mode CPSR
+    MSR     CPSR_c, r3                          ; Enter SYS mode
+    ADD     r1, r1, r2                          ; Calculate start of SYS stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    MOV     sp, r1                              ; Setup SYS stack pointer
+    ENDIF
+;
+    LDR     r2, =FIQ_STACK_SIZE                 ; Pickup stack size
+    MOV     r0, #FIQ_MODE                       ; Build FIQ mode CPSR
+    MSR     CPSR_c, r0                          ; Enter FIQ mode
+    ADD     r1, r1, r2                          ; Calculate start of FIQ stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    MOV     sp, r1                              ; Setup FIQ stack pointer
+    MOV     sl, #0                              ; Clear sl
+    MOV     fp, #0                              ; Clear fp
+    LDR     r2, =IRQ_STACK_SIZE                 ; Pickup IRQ (system stack size)
+    MOV     r0, #IRQ_MODE                       ; Build IRQ mode CPSR
+    MSR     CPSR_c, r0                          ; Enter IRQ mode
+    ADD     r1, r1, r2                          ; Calculate start of IRQ stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    MOV     sp, r1                              ; Setup IRQ stack pointer
+    MOV     r0, #SVC_MODE                       ; Build SVC mode CPSR
+    MSR     CPSR_c, r0                          ; Enter SVC mode
+    LDR     r3, =_tx_thread_system_stack_ptr    ; Pickup stack pointer
+    STR     r1, [r3, #0]                        ; Save the system stack
+;
+;    /* Save the system stack pointer.  */
+;    _tx_thread_system_stack_ptr = (VOID_PTR) (sp);
+;
+    LDR     r1, =_tx_thread_system_stack_ptr    ; Pickup address of system stack ptr
+    LDR     r0, [r1, #0]                        ; Pickup system stack 
+    ADD     r0, r0, #4                          ; Increment to next free word
+;
+;    /* Save the first available memory address.  */
+;    _tx_initialize_unused_memory =  (VOID_PTR) |Image$$ZI$$Limit| + HEAP + [SYS_STACK] + FIQ_STACK + IRQ_STACK;
+;
+    LDR     r2, =_tx_initialize_unused_memory   ; Pickup unused memory ptr address
+    STR     r0, [r2, #0]                        ; Save first free memory address
+;
+;    /* Setup Timer for periodic interrupts.  */
+;
+;    /* Done, return to caller.  */
+;
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;}
+;
+;
+;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code.  This
+;   routine will set the initial stack to use the ThreadX IRQ & FIQ & 
+;   (optionally SYS) stack areas.  */
+;
+    EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+    LDR     r0, =|Image$$ZI$$Limit|             ; Get end of non-initialized RAM area
+    LDR     r2, =HEAP_SIZE                      ; Pickup the heap size
+    ADD     r2, r2, r0                          ; Setup heap limit
+    ADD     r3, r2, #4                          ; Setup stack limit
+    MOV     r1, r3                              ; Setup start of stack
+    IF :DEF:TX_ENABLE_IRQ_NESTING
+    LDR     r12, =SYS_STACK_SIZE                ; Pickup IRQ system stack
+    ADD     r1, r1, r12                         ; Setup the return system stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    ENDIF
+    LDR     r12, =FIQ_STACK_SIZE                ; Pickup FIQ stack size
+    ADD     r1, r1, r12                         ; Setup the return system stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    LDR     r12, =IRQ_STACK_SIZE                ; Pickup IRQ system stack
+    ADD     r1, r1, r12                         ; Setup the return system stack
+    BIC     r1, r1, #7                          ; Ensure 8-byte alignment
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+;
+;/* Define shells for each of the interrupt vectors.  */
+;
+    EXPORT  __tx_undefined
+__tx_undefined
+    B       __tx_undefined                      ; Undefined handler
+;
+    EXPORT  __tx_swi_interrupt
+__tx_swi_interrupt
+    B       __tx_swi_interrupt                  ; Software interrupt handler
+;
+    EXPORT  __tx_prefetch_handler
+__tx_prefetch_handler
+    B       __tx_prefetch_handler               ; Prefetch exception handler
+;
+    EXPORT  __tx_abort_handler
+__tx_abort_handler
+    B       __tx_abort_handler                  ; Abort exception handler
+;
+    EXPORT  __tx_reserved_handler
+__tx_reserved_handler
+    B       __tx_reserved_handler               ; Reserved exception handler
+;
+;
+    EXPORT  __tx_irq_handler
+    EXPORT  __tx_irq_processing_return      
+__tx_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return
+;
+;    /* At this point execution is still in the IRQ mode.  The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  In 
+;       addition, IRQ interrupts may be re-enabled - with certain restrictions -
+;       if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
+;       small code sequences where lr is saved before enabling interrupts and 
+;       restored after interrupts are again disabled.  */
+;
+;
+    BL      _tx_timer_interrupt                 ; Timer interrupt handler
+_tx_not_timer_interrupt
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start 
+;       from IRQ mode with interrupts disabled.  This routine switches to the
+;       system mode and returns with IRQ interrupts enabled.  
+;       
+;       NOTE:  It is very important to ensure all IRQ interrupts are cleared 
+;       prior to enabling nested IRQ interrupts.  */
+    IF :DEF:TX_ENABLE_IRQ_NESTING
+    BL      _tx_thread_irq_nesting_start
+    ENDIF
+;
+;
+;    /* Application IRQ handlers can be called here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_context_restore.  
+;       This routine returns in processing in IRQ mode with interrupts disabled.  */
+    IF :DEF:TX_ENABLE_IRQ_NESTING
+    BL      _tx_thread_irq_nesting_end
+    ENDIF
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+;
+;
+;    /* This is an example of a vectored IRQ handler.  */
+;
+    EXPORT  __tx_example_vectored_irq_handler
+__tx_example_vectored_irq_handler
+;
+;
+;    /* Save initial context and call context save to prepare for 
+;       vectored ISR execution.  */
+;
+;    STMDB   sp!, {r0-r3}                        ; Save some scratch registers
+;    MRS     r0, SPSR                            ; Pickup saved SPSR
+;    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+;    STMDB   sp!, {r0, r10, r12, lr}             ; Store other scratch registers
+;    BL      _tx_thread_vectored_context_save    ; Vectored context save
+;
+;    /* At this point execution is still in the IRQ mode.  The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  In 
+;       addition, IRQ interrupts may be re-enabled - with certain restrictions -
+;       if nested IRQ interrupts are desired.  Interrupts may be re-enabled over
+;       small code sequences where lr is saved before enabling interrupts and 
+;       restored after interrupts are again disabled.  */
+;
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start 
+;       from IRQ mode with interrupts disabled.  This routine switches to the
+;       system mode and returns with IRQ interrupts enabled.  
+;       
+;       NOTE:  It is very important to ensure all IRQ interrupts are cleared 
+;       prior to enabling nested IRQ interrupts.  */
+;    IF :DEF:TX_ENABLE_IRQ_NESTING
+;    BL      _tx_thread_irq_nesting_start
+;    ENDIF
+;
+;    /* Application IRQ handlers can be called here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_context_restore.  
+;       This routine returns in processing in IRQ mode with interrupts disabled.  */
+;    IF :DEF:TX_ENABLE_IRQ_NESTING
+;    BL      _tx_thread_irq_nesting_end
+;    ENDIF
+;
+;    /* Jump to context restore to restore system context.  */
+;    B       _tx_thread_context_restore
+;
+;
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+    EXPORT  __tx_fiq_handler
+    EXPORT  __tx_fiq_processing_return
+__tx_fiq_handler
+;
+;    /* Jump to fiq context save to save system context.  */
+    B       _tx_thread_fiq_context_save
+__tx_fiq_processing_return
+;
+;    /* At this point execution is still in the FIQ mode.  The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  */
+;
+;    /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start 
+;       from FIQ mode with interrupts disabled.  This routine switches to the
+;       system mode and returns with FIQ interrupts enabled. 
+;
+;       NOTE:  It is very important to ensure all FIQ interrupts are cleared 
+;       prior to enabling nested FIQ interrupts.  */
+    IF  :DEF:TX_ENABLE_FIQ_NESTING
+    BL      _tx_thread_fiq_nesting_start
+    ENDIF
+;
+;    /* Application FIQ handlers can be called here!  */
+;
+;    /* If interrupt nesting was started earlier, the end of interrupt nesting
+;       service must be called before returning to _tx_thread_fiq_context_restore.  */
+    IF  :DEF:TX_ENABLE_FIQ_NESTING
+    BL      _tx_thread_fiq_nesting_end
+    ENDIF
+;
+;    /* Jump to fiq context restore to restore system context.  */
+    B       _tx_thread_fiq_context_restore
+;
+;
+    ELSE
+    EXPORT  __tx_fiq_handler
+__tx_fiq_handler
+    B       __tx_fiq_handler                    ; FIQ interrupt handler
+    ENDIF
+;
+;    /* Reference build options and version ID to ensure they come in.  */
+;
+    LDR     r2, =_tx_build_options              ; Pickup build options variable address
+    LDR     r0, [r2, #0]                        ; Pickup build options content
+    LDR     r2, =_tx_version_id                 ; Pickup version ID variable address
+    LDR     r0, [r2, #0]                        ; Pickup version ID content
+;
+;
+    END
+
diff --git a/ports/cortex_r5/ac5/inc/tx_port.h b/ports/cortex_r5/ac5/inc/tx_port.h
new file mode 100644
index 00000000..459a9a94
--- /dev/null
+++ b/ports/cortex_r5/ac5/inc/tx_port.h
@@ -0,0 +1,327 @@
+/**************************************************************************/
+/*                                                                        */
+/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+/*                                                                        */
+/*       This software is licensed under the Microsoft Software License   */
+/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+/*       and in the root directory of this software.                      */
+/*                                                                        */
+/**************************************************************************/
+
+
+/**************************************************************************/
+/**************************************************************************/
+/**                                                                       */ 
+/** ThreadX Component                                                     */
+/**                                                                       */
+/**   Port Specific                                                       */
+/**                                                                       */
+/**************************************************************************/
+/**************************************************************************/
+
+
+/**************************************************************************/ 
+/*                                                                        */ 
+/*  PORT SPECIFIC C INFORMATION                            RELEASE        */ 
+/*                                                                        */ 
+/*    tx_port.h                                          Cortex-R5/AC5    */ 
+/*                                                           6.0.1        */
+/*                                                                        */
+/*  AUTHOR                                                                */
+/*                                                                        */
+/*    William E. Lamie, Microsoft Corporation                             */
+/*                                                                        */
+/*  DESCRIPTION                                                           */
+/*                                                                        */ 
+/*    This file contains data type definitions that make the ThreadX      */ 
+/*    real-time kernel function identically on a variety of different     */ 
+/*    processor architectures.  For example, the size or number of bits   */ 
+/*    in an "int" data type vary between microprocessor architectures and */ 
+/*    even C compilers for the same microprocessor.  ThreadX does not     */ 
+/*    directly use native C data types.  Instead, ThreadX creates its     */ 
+/*    own special types that can be mapped to actual data types by this   */ 
+/*    file to guarantee consistency in the interface and functionality.   */ 
+/*                                                                        */ 
+/*  RELEASE HISTORY                                                       */ 
+/*                                                                        */ 
+/*    DATE              NAME                      DESCRIPTION             */
+/*                                                                        */
+/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+/*                                                                        */
+/**************************************************************************/
+
+#ifndef TX_PORT_H
+#define TX_PORT_H
+
+
+/* Determine if the optional ThreadX user define file should be used.  */
+
+#ifdef TX_INCLUDE_USER_DEFINE_FILE
+
+
+/* Yes, include the user defines in tx_user.h. The defines in this file may 
+   alternately be defined on the command line.  */
+
+#include "tx_user.h"
+#endif
+
+
+/* Define compiler library include files.  */
+
+#include 
+#include 
+
+
+/* Define ThreadX basic types for this port.  */ 
+
+#define VOID                                    void
+typedef char                                    CHAR;
+typedef unsigned char                           UCHAR;
+typedef int                                     INT;
+typedef unsigned int                            UINT;
+typedef long                                    LONG;
+typedef unsigned long                           ULONG;
+typedef short                                   SHORT;
+typedef unsigned short                          USHORT;
+
+
+/* Define the priority levels for ThreadX.  Legal values range
+   from 32 to 1024 and MUST be evenly divisible by 32.  */
+
+#ifndef TX_MAX_PRIORITIES
+#define TX_MAX_PRIORITIES                       32
+#endif
+
+
+/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
+   thread creation is less than this value, the thread create call will return an error.  */
+
+#ifndef TX_MINIMUM_STACK
+#define TX_MINIMUM_STACK                        200         /* Minimum stack size for this port  */
+#endif
+
+
+/* Define the system timer thread's default stack size and priority.  These are only applicable
+   if TX_TIMER_PROCESS_IN_ISR is not defined.  */
+
+#ifndef TX_TIMER_THREAD_STACK_SIZE
+#define TX_TIMER_THREAD_STACK_SIZE              1024        /* Default timer thread stack size  */
+#endif
+
+#ifndef TX_TIMER_THREAD_PRIORITY    
+#define TX_TIMER_THREAD_PRIORITY                0           /* Default timer thread priority    */ 
+#endif
+
+
+/* Define various constants for the ThreadX ARM port.  */ 
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_INT_DISABLE                          0xC0        /* Disable IRQ & FIQ interrupts     */
+#else
+#define TX_INT_DISABLE                          0x80        /* Disable IRQ interrupts           */
+#endif
+#define TX_INT_ENABLE                           0x00        /* Enable IRQ interrupts            */
+
+
+/* Define the clock source for trace event entry time stamp. The following two item are port specific.  
+   For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock 
+   source constants would be:
+
+#define TX_TRACE_TIME_SOURCE                    *((ULONG *) 0x0a800024)
+#define TX_TRACE_TIME_MASK                      0x0000FFFFUL
+
+*/
+
+#ifndef TX_TRACE_TIME_SOURCE
+#define TX_TRACE_TIME_SOURCE                    ++_tx_trace_simulated_time
+#endif
+#ifndef TX_TRACE_TIME_MASK
+#define TX_TRACE_TIME_MASK                      0xFFFFFFFFUL
+#endif
+
+
+/* Define the port specific options for the _tx_build_options variable. This variable indicates
+   how the ThreadX library was built.  */
+
+#ifdef TX_ENABLE_FIQ_SUPPORT
+#define TX_FIQ_ENABLED                          1
+#else
+#define TX_FIQ_ENABLED                          0
+#endif
+
+#ifdef TX_ENABLE_IRQ_NESTING
+#define TX_IRQ_NESTING_ENABLED                  2
+#else
+#define TX_IRQ_NESTING_ENABLED                  0
+#endif
+
+#ifdef TX_ENABLE_FIQ_NESTING
+#define TX_FIQ_NESTING_ENABLED                  4
+#else
+#define TX_FIQ_NESTING_ENABLED                  0
+#endif
+
+#define TX_PORT_SPECIFIC_BUILD_OPTIONS          TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED
+
+
+/* Define the in-line initialization constant so that modules with in-line
+   initialization capabilities can prevent their initialization from being
+   a function call.  */
+
+#define TX_INLINE_INITIALIZATION
+
+
+/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is 
+   disabled. When the following is defined, ThreadX thread stack checking is enabled.  If stack
+   checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
+   define is negated, thereby forcing the stack fill which is necessary for the stack checking
+   logic.  */
+
+#ifdef TX_ENABLE_STACK_CHECKING
+#undef TX_DISABLE_STACK_FILLING
+#endif
+
+
+/* Define the TX_THREAD control block extensions for this port. The main reason
+   for the multiple macros is so that backward compatibility can be maintained with 
+   existing ThreadX kernel awareness modules.  */
+
+#define TX_THREAD_EXTENSION_0          
+#define TX_THREAD_EXTENSION_1                  
+#define TX_THREAD_EXTENSION_2          
+#define TX_THREAD_EXTENSION_3          
+
+
+/* Define the port extensions of the remaining ThreadX objects.  */
+
+#define TX_BLOCK_POOL_EXTENSION
+#define TX_BYTE_POOL_EXTENSION
+#define TX_EVENT_FLAGS_GROUP_EXTENSION
+#define TX_MUTEX_EXTENSION
+#define TX_QUEUE_EXTENSION
+#define TX_SEMAPHORE_EXTENSION
+#define TX_TIMER_EXTENSION
+
+
+/* Define the user extension field of the thread control block.  Nothing 
+   additional is needed for this port so it is defined as white space.  */
+
+#ifndef TX_THREAD_USER_EXTENSION
+#define TX_THREAD_USER_EXTENSION    
+#endif
+
+
+/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
+   tx_thread_shell_entry, and tx_thread_terminate.  */
+
+
+#define TX_THREAD_CREATE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_DELETE_EXTENSION(thread_ptr)                                  
+#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
+#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
+
+
+/* Define the ThreadX object creation extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
+#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
+
+
+/* Define the ThreadX object deletion extensions for the remaining objects.  */
+
+#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
+#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
+#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
+#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
+#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
+#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
+
+
+/* Determine if the ARM architecture has the CLZ instruction. This is available on 
+   architectures v5 and above. If available, redefine the macro for calculating the 
+   lowest bit set.  */
+
+#ifndef __thumb
+
+#define TX_LOWEST_SET_BIT_CALCULATE(m, b)       m = m & ((ULONG) (-((LONG) m))); \
+                                                b = (ULONG) __clz((unsigned int) m); \
+                                                b = 31 - b; 
+#endif
+
+
+/* Define ThreadX interrupt lockout and restore macros for protection on 
+   access of critical kernel information.  The restore interrupt macro must 
+   restore the interrupt posture of the running thread prior to the value 
+   present prior to the disable macro.  In most cases, the save area macro
+   is used to define a local function save area for the disable and restore
+   macros.  */
+
+#ifndef __thumb
+
+#define TX_INTERRUPT_SAVE_AREA                  register unsigned int interrupt_save_disabled;
+
+#ifdef  TX_ENABLE_FIQ_SUPPORT
+
+/* IRQ and FIQ support.  */
+
+#define TX_DISABLE                              __memory_changed(), interrupt_save_disabled =  __disable_irq(); \
+                                                __disable_fiq();
+
+#define TX_RESTORE                              if (!interrupt_save_disabled) \
+                                                { \
+                                                    __enable_irq(); \
+                                                    __enable_fiq(); \
+                                                } 
+
+#else
+
+#define TX_DISABLE                              __memory_changed(), interrupt_save_disabled =  __disable_irq();
+
+#define TX_RESTORE                              if (!interrupt_save_disabled) \
+                                                { \
+                                                    __enable_irq(); \
+                                                } 
+#endif
+
+#else
+
+unsigned int   _tx_thread_interrupt_disable(void);
+unsigned int   _tx_thread_interrupt_restore(UINT old_posture);
+
+
+#define TX_INTERRUPT_SAVE_AREA                  unsigned int interrupt_save;
+
+#define TX_DISABLE                              interrupt_save =  _tx_thread_interrupt_disable();
+#define TX_RESTORE                              _tx_thread_interrupt_restore(interrupt_save);
+#endif
+
+
+/* Define the interrupt lockout macros for each ThreadX object.  */
+
+#define TX_BLOCK_POOL_DISABLE                   TX_DISABLE
+#define TX_BYTE_POOL_DISABLE                    TX_DISABLE
+#define TX_EVENT_FLAGS_GROUP_DISABLE            TX_DISABLE
+#define TX_MUTEX_DISABLE                        TX_DISABLE
+#define TX_QUEUE_DISABLE                        TX_DISABLE
+#define TX_SEMAPHORE_DISABLE                    TX_DISABLE
+
+
+/* Define the version ID of ThreadX.  This may be utilized by the application.  */
+
+#ifdef TX_THREAD_INIT
+CHAR                            _tx_version_id[] = 
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX  Cortex-R5/AC5 Version 6.0 *";
+#else
+extern  CHAR                    _tx_version_id[];
+#endif
+
+
+#endif
+
diff --git a/ports/cortex_r5/ac5/readme_threadx.txt b/ports/cortex_r5/ac5/readme_threadx.txt
new file mode 100644
index 00000000..bc4d497d
--- /dev/null
+++ b/ports/cortex_r5/ac5/readme_threadx.txt
@@ -0,0 +1,529 @@
+                     Microsoft's Azure RTOS ThreadX for Cortex-R5 
+
+                               Thumb & 32-bit Mode
+
+                            Using ARM Compiler 5 (AC5)
+
+1.  Building the ThreadX run-time Library
+
+First make sure you are in the "example_build" directory. Also, make sure that 
+you have setup your path and other environment variables necessary for the ARM 
+AC5 development environment. At this point you may run the build_threadx.bat 
+batch file. This will build the ThreadX run-time environment in the 
+"example_build" directory. 
+
+You should observe assembly and compilation of a series of ThreadX source 
+files. At the end of the batch file, they are all combined into the 
+run-time library file: tx.a. This file must be linked with your 
+application in order to use ThreadX.
+
+1.1  Building with Project Files
+
+The ThreadX library can also be built via project files. Simply open 
+the tx.mcp file with project builder and select make. This will place 
+the tx.a library file into the Debug sub-directory.
+
+
+2.  Demonstration System
+
+The ThreadX demonstration is designed to execute under the ARM
+Windows-based simulator.
+
+Building the demonstration is easy; simply execute the build_threadx_demo.bat 
+batch file while inside the "example_build" directory. 
+
+You should observe the compilation of sample_threadx.c (which is the demonstration 
+application) and linking with tx.a. The resulting file sample_threadx.axf 
+is a binary file that can be downloaded and executed on the ARM simulator.
+
+2.0.1  Building with Project Files
+
+The ThreadX demonstration can also be built via project files. Simply open 
+the sample_threadx.mcp file with project builder and select make. This will place 
+the sample_threadx.axf output image into the Debug sub-directory.
+
+
+3.  System Initialization
+
+The entry point in ThreadX for the Cortex-R5 using AC5 tools is at label 
+__main. This is defined within the AC5 compiler's startup code. In 
+addition, this is where all static and global pre-set C variable 
+initialization processing takes place.
+
+The ThreadX tx_initialize_low_level.s file is responsible for setting up 
+various system data structures, the vector area, and a periodic timer interrupt 
+source. By default, the vector area is defined to be located in the Init area, 
+which is defined at the top of tx_initialize_low_level.s. This area is typically 
+located at 0. In situations where this is impossible, the vectors at the beginning 
+of the Init area should be copied to address 0.
+
+This is also where initialization of a periodic timer interrupt source
+should take place.
+
+In addition, _tx_initialize_low_level determines the first available 
+address for use by the application, which is supplied as the sole input 
+parameter to your application definition function, tx_application_define.
+
+
+4.  Assembler / Compiler Switches
+
+The following are compiler switches used in building the demonstration 
+system:
+
+Compiler Switch                 Meaning
+
+    -g                  Specifies debug information
+    -c                  Specifies object code generation
+    --cpu Cortex-R5     Specifies Cortex-R5 instruction set
+    --apcs /interwork   Specifies Thumb/32-bit compatibility
+
+Linker Switch                   Meaning
+
+    -d                  Specifies to retain debug information in output file
+    -o demo.axf         Specifies demo output file name
+    --elf               Specifies elf output file format
+    --ro                Specifies that Read-Only memory starts at address 0
+    --first tx_initialize_low_level.o(Init) 
+                        Specifies that the first area loaded is Init
+    --remove            Remove unused areas
+    --list              Specifies map file name 
+    --symbols           Specifies symbols for map file
+    --map               Creates a map file
+
+Application Defines
+
+    --PD "TX_ENABLE_FIQ_SUPPORT SETL {TRUE}"    This assembler define enables FIQ
+                                                interrupt handling support in the
+                                                ThreadX assembly files. If used,
+                                                it should be used on all assembly
+                                                files and the generic C source of
+                                                ThreadX should be compiled with 
+                                                TX_ENABLE_FIQ_SUPPORT defined as well.
+    --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}"    This assembler define enables IRQ
+                                                nested support. If IRQ nested 
+                                                interrupt support is needed, this
+                                                define should be applied to 
+                                                tx_initialize_low_level.s.
+    --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}"    This assembler define enables FIQ
+                                                nested support. If FIQ nested 
+                                                interrupt support is needed, this
+                                                define should be applied to 
+                                                tx_initialize_low_level.s. In addition,
+                                                IRQ nesting should also be enabled.
+    -DTX_ENABLE_FIQ_SUPPORT                     This compiler define enables FIQ
+                                                interrupt handling in the ThreadX
+                                                generic C source. This define 
+                                                should also be used in conjunction
+                                                with the corresponding assembler
+                                                define.                                               
+    -DTX_DISABLE_ERROR_CHECKING                 If defined before tx_api.h is included,
+                                                this define causes basic ThreadX error
+                                                checking to be disabled. Please see
+                                                Chapter 2 in the "ThreadX User Guide" 
+                                                for more details.
+
+    -DTX_MAX_PRIORITIES                         Defines the priority levels for ThreadX. 
+                                                Legal values range from 32 through 
+                                                1024 (inclusive) and MUST be evenly divisible 
+                                                by 32. Increasing the number of priority levels 
+                                                supported increases the RAM usage by 128 bytes 
+                                                for every group of 32 priorities. However, there 
+                                                is only a negligible effect on performance. By 
+                                                default, this value is set to 32 priority levels.
+
+    -DTX_MINIMUM_STACK                          Defines the minimum stack size (in bytes). It is 
+                                                used for error checking when threads are created. 
+                                                The default value is port-specific and is found 
+                                                in tx_port.h.
+
+    -DTX_TIMER_THREAD_STACK_SIZE                Defines the stack size (in bytes) of the internal 
+                                                ThreadX timer thread. This thread processes all 
+                                                thread sleep requests as well as all service call 
+                                                timeouts. In addition, all application timer callback 
+                                                routines are invoked from this context. The default 
+                                                value is port-specific and is found in tx_port.h.
+
+    -DTX_TIMER_THREAD_PRIORITY                  Defines the priority of the internal ThreadX timer 
+                                                thread. The default value is priority 0 - the highest 
+                                                priority in ThreadX. The default value is defined 
+                                                in tx_port.h.
+
+    -DTX_TIMER_PROCESS_IN_ISR                   Defined, this option eliminates the internal system 
+                                                timer thread for ThreadX. This results in improved 
+                                                performance on timer events and smaller RAM requirements 
+                                                because the timer stack and control block are no 
+                                                longer needed. However, using this option moves all 
+                                                the timer expiration processing to the timer ISR level. 
+                                                By default, this option is not defined.
+
+    -DTX_REACTIVATE_INLINE                      Defined, this option performs reactivation of ThreadX 
+                                                timers in-line instead of using a function call. This 
+                                                improves performance but slightly increases code size. 
+                                                By default, this option is not defined.
+
+    -DTX_DISABLE_STACK_FILLING                  Defined, placing the 0xEF value in each byte of each 
+                                                thread's stack is disabled. By default, this option is 
+                                                not defined.
+
+    -DTX_ENABLE_STACK_CHECKING                  Defined, this option enables ThreadX run-time stack checking, 
+                                                which includes analysis of how much stack has been used and 
+                                                examination of data pattern "fences" before and after the 
+                                                stack area. If a stack error is detected, the registered 
+                                                application stack error handler is called. This option does 
+                                                result in slightly increased overhead and code size. Please 
+                                                review the tx_thread_stack_error_notify API for more information. 
+                                                By default, this option is not defined.
+
+    -DTX_DISABLE_PREEMPTION_THRESHOLD           Defined, this option disables the preemption-threshold feature 
+                                                and slightly reduces code size and improves performance. Of course, 
+                                                the preemption-threshold capabilities are no longer available. 
+                                                By default, this option is not defined.
+
+    -DTX_DISABLE_REDUNDANT_CLEARING             Defined, this option removes the logic for initializing ThreadX 
+                                                global C data structures to zero. This should only be used if 
+                                                the compiler's initialization code sets all un-initialized 
+                                                C global data to zero. Using this option slightly reduces 
+                                                code size and improves performance during initialization. 
+                                                By default, this option is not defined.
+
+    -DTX_DISABLE_NOTIFY_CALLBACKS               Defined, this option disables the notify callbacks for various 
+                                                ThreadX objects. Using this option slightly reduces code size 
+                                                and improves performance.
+
+    -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO     Defined, this option enables the gathering of performance 
+                                                information on block pools. By default, this option is 
+                                                not defined.
+
+    -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO      Defined, this option enables the gathering of performance 
+                                                information on byte pools. By default, this option is 
+                                                not defined.
+
+    -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO    Defined, this option enables the gathering of performance 
+                                                information on event flags groups. By default, this option 
+                                                is not defined.
+
+    -DTX_MUTEX_ENABLE_PERFORMANCE_INFO          Defined, this option enables the gathering of performance 
+                                                information on mutexes. By default, this option is 
+                                                not defined.
+
+    -DTX_QUEUE_ENABLE_PERFORMANCE_INFO          Defined, this option enables the gathering of performance 
+                                                information on queues. By default, this option is 
+                                                not defined.
+
+    -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO      Defined, this option enables the gathering of performance 
+                                                information on semaphores. By default, this option is 
+                                                not defined.
+
+    -DTX_THREAD_ENABLE_PERFORMANCE_INFO         Defined, this option enables the gathering of performance 
+                                                information on threads. By default, this option is 
+                                                not defined.
+
+    -DTX_TIMER_ENABLE_PERFORMANCE_INFO          Defined, this option enables the gathering of performance 
+                                                information on timers. By default, this option is 
+                                                not defined.
+
+    -DTX_ENABLE_EVENT_TRACE                     Defined, this option enables the internal ThreadX trace
+                                                feature. The trace buffer is supplied at a later time
+                                                via an application call to tx_trace_enable.
+
+    -DTX_TRACE_TIME_SOURCE                      This defines the time-stamp source for event tracing. 
+                                                This define is only pertinent if the ThreadX library is 
+                                                built with TX_ENABLE_EVENT_TRACE defined.
+
+    -DTX_TRACE_TIME_MASK                        This defines the number of valid bits in the event trace 
+                                                time-stamp source defined previously. If the time-stamp 
+                                                source is 16-bits, this value should be 0xFFFF. Alternatively, 
+                                                if the time-stamp source is 32-bits, this value should be 
+                                                0xFFFFFFFF. This define is only pertinent if the ThreadX 
+                                                library is built with TX_ENABLE_EVENT_TRACE defined.
+
+
+
+5.  Register Usage and Stack Frames
+
+The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch 
+registers for each function. All other registers used by a C function must 
+be preserved by the function. ThreadX takes advantage of this in situations 
+where a context switch happens as a result of making a ThreadX service call 
+(which is itself a C function). In such cases, the saved context of a thread 
+is only the non-scratch registers.
+
+The following defines the saved context stack frames for context switches
+that occur as a result of interrupt handling or from thread-level API calls.
+All suspended threads have one of these two types of stack frames. The top
+of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the 
+associated thread control block TX_THREAD.
+
+
+
+    Offset        Interrupted Stack Frame        Non-Interrupt Stack Frame
+
+     0x00                   1                           0
+     0x04                   CPSR                        CPSR
+     0x08                   r0  (a1)                    r4  (v1)
+     0x0C                   r1  (a2)                    r5  (v2)
+     0x10                   r2  (a3)                    r6  (v3)
+     0x14                   r3  (a4)                    r7  (v4)
+     0x18                   r4  (v1)                    r8  (v5)
+     0x1C                   r5  (v2)                    r9  (v6)
+     0x20                   r6  (v3)                    r10 (v7)
+     0x24                   r7  (v4)                    r11 (fp)
+     0x28                   r8  (v5)                    r14 (lr)
+     0x2C                   r9  (v6)                        
+     0x30                   r10 (v7)                        
+     0x34                   r11 (fp)                        
+     0x38                   r12 (ip)                         
+     0x3C                   r14 (lr)
+     0x40                   PC 
+
+
+6.  Improving Performance
+
+The distribution version of ThreadX is built without any compiler 
+optimizations. This makes it easy to debug because you can trace or set 
+breakpoints inside of ThreadX itself. Of course, this costs some 
+performance. To make it run faster, you can change the build_threadx.bat file to 
+remove the -g option and enable all compiler optimizations. 
+
+In addition, you can eliminate the ThreadX basic API error checking by 
+compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
+defined. 
+
+
+7.  Interrupt Handling
+
+ThreadX provides complete and high-performance interrupt handling for Cortex-R5
+targets. There are a certain set of requirements that are defined in the 
+following sub-sections:
+
+
+7.1  Vector Area
+
+The Cortex-R5 vectors start at address zero. The demonstration system startup
+Init area contains the vectors and is loaded at address zero. On actual 
+hardware platforms, this area might have to be copied to address 0. 
+
+
+7.2  IRQ ISRs
+
+ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested
+IRQ interrupts. The following sub-sections define the IRQ capabilities.
+
+
+7.2.1 Standard IRQ ISRs
+
+The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ 
+interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following 
+is the default IRQ handler defined in tx_initialize_low_level.s:
+
+    EXPORT  __tx_irq_handler
+    EXPORT  __tx_irq_processing_return      
+__tx_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save             ; Jump to the context save
+__tx_irq_processing_return
+;
+;    /* At this point execution is still in the IRQ mode. The CPSR, point of
+;       interrupt, and all C scratch registers are available for use. Note 
+;       that IRQ interrupts are still disabled upon return from the context
+;       save function.  */
+;
+;    /* Application ISR call(s) go here!  */
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.2.2 Vectored IRQ ISRs
+
+The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified
+by the particular implementation. The following is an example IRQ handler defined in 
+tx_initialize_low_level.s:
+
+    EXPORT  __tx_irq_example_handler
+__tx_irq_example_handler
+;
+;    /* Call context save to save system context.  */
+
+    STMDB   sp!, {r0-r3}                        ; Save some scratch registers
+    MRS     r0, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}             ; Store other scratch registers
+    BL      _tx_thread_vectored_context_save    ; Call the vectored IRQ context save
+;
+;    /* At this point execution is still in the IRQ mode. The CPSR, point of
+;       interrupt, and all C scratch registers are available for use. Note 
+;       that IRQ interrupts are still disabled upon return from the context
+;       save function.  */
+;
+;    /* Application ISR call goes here!  */
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.2.3  Nested IRQ Support
+
+By default, nested IRQ interrupt support is not enabled. To enable nested
+IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING
+defined. With this defined, two new IRQ interrupt management services are
+available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end.
+These function should be called between the IRQ context save and restore
+calls. 
+
+Execution between the calls to _tx_thread_irq_nesting_start and 
+_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved 
+by switching from IRQ mode to SYS mode and enabling IRQ interrupts.
+The SYS mode stack is used during the SYS mode operation, which was 
+setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required,
+calling the _tx_thread_irq_nesting_end service disables nesting by disabling
+IRQ interrupts and switching back to IRQ mode in preparation for the IRQ 
+context restore service.
+
+The following is an example of enabling IRQ nested interrupts in a standard 
+IRQ handler:
+
+    EXPORT  __tx_irq_handler
+    EXPORT  __tx_irq_processing_return      
+__tx_irq_handler
+;
+;    /* Jump to context save to save system context.  */
+    B       _tx_thread_context_save
+__tx_irq_processing_return
+;
+;    /* Enable nested IRQ interrupts. NOTE:  Since this service returns
+;       with IRQ interrupts enabled, all IRQ interrupt sources must be 
+;       cleared prior to calling this service.  */
+    BL      _tx_thread_irq_nesting_start
+;    
+;    /* Application ISR call(s) go here!  */
+;
+;    /* Disable nested IRQ interrupts. The mode is switched back to
+;       IRQ mode and IRQ interrupts are disable upon return.  */
+    BL      _tx_thread_irq_nesting_end
+;
+;    /* Jump to context restore to restore system context.  */
+    B       _tx_thread_context_restore
+
+
+7.3  FIQ Interrupts
+
+By default, Cortex-R5 FIQ interrupts are left alone by ThreadX. Of course, this 
+means that the application is fully responsible for enabling the FIQ interrupt 
+and saving/restoring any registers used in the FIQ ISR processing. To globally 
+enable FIQ interrupts, the application should enable FIQ interrupts at the 
+beginning of each thread or before any threads are created in tx_application_define. 
+In addition, the application must ensure that no ThreadX service calls are made 
+from default FIQ ISRs, which is located in tx_initialize_low_level.s.
+
+
+7.3.1  Managed FIQ Interrupts
+
+Full ThreadX management of FIQ interrupts is provided if the ThreadX sources
+are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built
+this way, the FIQ interrupt handlers are very similar to the IRQ interrupt
+handlers defined previously. The following is default FIQ handler 
+defined in tx_initialize_low_level.s:
+
+
+    EXPORT  __tx_fiq_handler
+    EXPORT  __tx_fiq_processing_return
+__tx_fiq_handler
+;
+;    /* Jump to fiq context save to save system context.  */
+    B       _tx_thread_fiq_context_save
+__tx_fiq_processing_return:
+;
+;    /* At this point execution is still in the FIQ mode. The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  */
+;
+;    /* Application FIQ handlers can be called here!  */
+;
+;    /* Jump to fiq context restore to restore system context.  */
+    B       _tx_thread_fiq_context_restore
+
+
+7.3.1.1 Nested FIQ Support
+
+By default, nested FIQ interrupt support is not enabled. To enable nested
+FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING
+defined. With this defined, two new FIQ interrupt management services are
+available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end.
+These function should be called between the FIQ context save and restore
+calls. 
+
+Execution between the calls to _tx_thread_fiq_nesting_start and 
+_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved 
+by switching from FIQ mode to SYS mode and enabling FIQ interrupts.
+The SYS mode stack is used during the SYS mode operation, which was 
+setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required,
+calling the _tx_thread_fiq_nesting_end service disables nesting by disabling
+FIQ interrupts and switching back to FIQ mode in preparation for the FIQ 
+context restore service.
+
+The following is an example of enabling FIQ nested interrupts in the 
+typical FIQ handler:
+
+
+    EXPORT  __tx_fiq_handler
+    EXPORT  __tx_fiq_processing_return
+__tx_fiq_handler
+;
+;    /* Jump to fiq context save to save system context.  */
+    B       _tx_thread_fiq_context_save
+__tx_fiq_processing_return
+;
+;    /* At this point execution is still in the FIQ mode. The CPSR, point of
+;       interrupt, and all C scratch registers are available for use.  */
+;
+;    /* Enable nested FIQ interrupts. NOTE:  Since this service returns
+;       with FIQ interrupts enabled, all FIQ interrupt sources must be 
+;       cleared prior to calling this service.  */
+    BL      _tx_thread_fiq_nesting_start
+;
+;    /* Application FIQ handlers can be called here!  */
+;
+;    /* Disable nested FIQ interrupts. The mode is switched back to
+;       FIQ mode and FIQ interrupts are disable upon return.  */
+    BL      _tx_thread_fiq_nesting_end
+;
+;    /* Jump to fiq context restore to restore system context.  */
+    B       _tx_thread_fiq_context_restore
+
+
+8.  ThreadX Timer Interrupt
+
+ThreadX requires a periodic interrupt source to manage all time-slicing, 
+thread sleeps, timeouts, and application timers. Without such a timer 
+interrupt source, these services are not functional. However, all other
+ThreadX services are operational without a periodic timer source.
+
+To add the timer interrupt processing, simply make a call to 
+_tx_timer_interrupt in the IRQ processing. An example of this can be
+found in the file tx_initialize_low_level.s in the Integrator sub-directories.
+
+
+9.  Thumb/Cortex-R5 Mixed Mode
+
+By default, ThreadX is setup for running in Cortex-R5 32-bit mode. This is 
+also true for the demonstration system. It is possible to build any 
+ThreadX file and/or the application in Thumb mode. If any Thumb code 
+is used the entire ThreadX source- both C and assembly - should be built 
+with the "-apcs /interwork" option.
+
+
+10.  Revision History
+
+For generic code revision information, please refer to the readme_threadx_generic.txt
+file, which is included in your distribution. The following details the revision
+information associated with this specific port of ThreadX:
+
+06/30/2020  Initial ThreadX 6.0.1 version for Cortex-R5 using AC5 tools.
+
+
+Copyright(c) 1996-2020 Microsoft Corporation
+
+
+https://azure.com/rtos
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_context_restore.s b/ports/cortex_r5/ac5/src/tx_thread_context_restore.s
new file mode 100644
index 00000000..1a1e3c0c
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_context_restore.s
@@ -0,0 +1,255 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+DISABLE_INTS    EQU     0xC0                    ; Disable IRQ & FIQ interrupts
+IRQ_MODE        EQU     0xD2                    ; IRQ mode
+SVC_MODE        EQU     0xD3                    ; SVC mode
+    ELSE
+DISABLE_INTS    EQU     0x80                    ; Disable IRQ interrupts
+IRQ_MODE        EQU     0x92                    ; IRQ mode
+SVC_MODE        EQU     0x93                    ; SVC mode
+    ENDIF
+;
+;
+    IMPORT      _tx_thread_system_state
+    IMPORT      _tx_thread_current_ptr
+    IMPORT      _tx_thread_execute_ptr
+    IMPORT      _tx_timer_time_slice
+    IMPORT      _tx_thread_schedule
+    IMPORT      _tx_thread_preempt_disable
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT      _tx_execution_isr_exit
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_context_restore                         Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function restores the interrupt context if it is processing a  */ 
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */ 
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+;/*    if no thread was running, the function returns to the scheduler.    */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                   Thread scheduling routine     */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                  Interrupt Service Routines    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_restore(VOID)
+;{
+    EXPORT  _tx_thread_context_restore
+_tx_thread_context_restore
+;
+;    /* Lockout interrupts.  */
+;
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Disable IRQ and FIQ interrupts
+    ELSE
+    CPSID   i                                   ; Disable IRQ interrupts
+    ENDIF
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR exit function to indicate an ISR is complete.  */
+;
+    BL      _tx_execution_isr_exit              ; Call the ISR exit function
+    ENDIF
+;
+;    /* Determine if interrupts are nested.  */
+;    if (--_tx_thread_system_state)
+;    {
+;
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3, #0]                        ; Pickup system state
+    SUB     r2, r2, #1                          ; Decrement the counter
+    STR     r2, [r3, #0]                        ; Store the counter 
+    CMP     r2, #0                              ; Was this the first interrupt?
+    BEQ     __tx_thread_not_nested_restore      ; If so, not a nested restore
+;
+;    /* Interrupts are nested.  */
+;
+;    /* Just recover the saved registers and return to the point of 
+;       interrupt.  */
+;
+    LDMIA   sp!, {r0, r10, r12, lr}             ; Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       ; Put SPSR back
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOVS    pc, lr                              ; Return to point of interrupt
+;
+;    }
+__tx_thread_not_nested_restore
+;
+;    /* Determine if a thread was interrupted and no preemption is required.  */
+;    else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) 
+;               || (_tx_thread_preempt_disable))
+;    {
+;
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        ; Pickup actual current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_idle_system_restore     ; Yes, idle system was interrupted
+;
+    LDR     r3, =_tx_thread_preempt_disable     ; Pickup preempt disable address
+    LDR     r2, [r3, #0]                        ; Pickup actual preempt disable flag
+    CMP     r2, #0                              ; Is it set?
+    BNE     __tx_thread_no_preempt_restore      ; Yes, don't preempt this thread
+    LDR     r3, =_tx_thread_execute_ptr         ; Pickup address of execute thread ptr
+    LDR     r2, [r3, #0]                        ; Pickup actual execute thread pointer
+    CMP     r0, r2                              ; Is the same thread highest priority?
+    BNE     __tx_thread_preempt_restore         ; No, preemption needs to happen
+;
+;
+__tx_thread_no_preempt_restore
+;
+;    /* Restore interrupted thread or ISR.  */
+;
+;    /* Pickup the saved stack pointer.  */
+;    tmp_ptr =  _tx_thread_current_ptr -> tx_thread_stack_ptr;
+;
+;   /* Recover the saved context and return to the point of interrupt.  */
+;
+    LDMIA   sp!, {r0, r10, r12, lr}             ; Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       ; Put SPSR back
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOVS    pc, lr                              ; Return to point of interrupt
+;
+;    }
+;    else
+;    {
+__tx_thread_preempt_restore
+;
+    LDMIA   sp!, {r3, r10, r12, lr}             ; Recover temporarily saved registers
+    MOV     r1, lr                              ; Save lr (point of interrupt)
+    MOV     r2, #SVC_MODE                       ; Build SVC mode CPSR
+    MSR     CPSR_c, r2                          ; Enter SVC mode
+    STR     r1, [sp, #-4]!                      ; Save point of interrupt
+    STMDB   sp!, {r4-r12, lr}                   ; Save upper half of registers
+    MOV     r4, r3                              ; Save SPSR in r4
+    MOV     r2, #IRQ_MODE                       ; Build IRQ mode CPSR
+    MSR     CPSR_c, r2                          ; Enter IRQ mode
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOV     r5, #SVC_MODE                       ; Build SVC mode CPSR
+    MSR     CPSR_c, r5                          ; Enter SVC mode
+    STMDB   sp!, {r0-r3}                        ; Save r0-r3 on thread's stack
+
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        ; Pickup current thread pointer
+    
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    LDR     r2, [r0, #144]                      ; Pickup the VFP enabled flag
+    CMP     r2, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_irq_vfp_save               ; No, skip VFP IRQ save
+    VMRS    r2, FPSCR                           ; Pickup the FPSCR
+    STR     r2, [sp, #-4]!                      ; Save FPSCR
+    VSTMDB  sp!, {D0-D15}                       ; Save D0-D15
+_tx_skip_irq_vfp_save
+    ENDIF
+
+    MOV     r3, #1                              ; Build interrupt stack type
+    STMDB   sp!, {r3, r4}                       ; Save interrupt stack type and SPSR
+    STR     sp, [r0, #8]                        ; Save stack pointer in thread control
+                                                ;   block
+;
+;    /* Save the remaining time-slice and disable it.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    LDR     r3, =_tx_timer_time_slice           ; Pickup time-slice variable address
+    LDR     r2, [r3, #0]                        ; Pickup time-slice
+    CMP     r2, #0                              ; Is it active?
+    BEQ     __tx_thread_dont_save_ts            ; No, don't save it
+;
+;        _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+;        _tx_timer_time_slice =  0;
+;
+    STR     r2, [r0, #24]                       ; Save thread's time-slice
+    MOV     r2, #0                              ; Clear value
+    STR     r2, [r3, #0]                        ; Disable global time-slice flag
+;
+;    }
+__tx_thread_dont_save_ts
+;
+;
+;    /* Clear the current task pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;
+    MOV     r0, #0                              ; NULL value
+    STR     r0, [r1, #0]                        ; Clear current thread pointer
+;
+;    /* Return to the scheduler.  */
+;    _tx_thread_schedule();
+;
+    B       _tx_thread_schedule                 ; Return to scheduler
+;    }
+;
+__tx_thread_idle_system_restore
+;
+;    /* Just return back to the scheduler!  */
+;
+    MOV     r3, #SVC_MODE                       ; Build SVC mode with interrupts disabled
+    MSR     CPSR_c, r3                          ; Change to SVC mode
+    B       _tx_thread_schedule                 ; Return to scheduler
+;}
+;
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_context_save.s b/ports/cortex_r5/ac5/src/tx_thread_context_save.s
new file mode 100644
index 00000000..d7d5d406
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_context_save.s
@@ -0,0 +1,199 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    IMPORT      _tx_thread_system_state
+    IMPORT      _tx_thread_current_ptr
+    IMPORT      __tx_irq_processing_return
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT      _tx_execution_isr_enter
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_context_save                            Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function saves the context of an executing thread in the       */ 
+;/*    beginning of interrupt processing.  The function also ensures that  */ 
+;/*    the system stack is used upon return to the calling ISR.            */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_context_save(VOID)
+;{
+    EXPORT  _tx_thread_context_save
+_tx_thread_context_save
+;
+;    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+;       out, we are in IRQ mode, and all registers are intact.  */
+;
+;    /* Check for a nested interrupt condition.  */
+;    if (_tx_thread_system_state++)
+;    {
+;
+    STMDB   sp!, {r0-r3}                        ; Save some working registers 
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Disable FIQ interrupts
+    ENDIF
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3, #0]                        ; Pickup system state
+    CMP     r2, #0                              ; Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         ; Yes, not a nested context save
+;
+;    /* Nested interrupt condition.  */
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+;
+;   /* Save the rest of the scratch registers on the stack and return to the
+;      calling ISR.  */
+;
+    MRS     r0, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}             ; Store other registers
+;
+;    /* Return to the ISR.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    B       __tx_irq_processing_return          ; Continue IRQ processing 
+;
+__tx_thread_not_nested_save
+;    }
+;
+;    /* Otherwise, not nested, check to see if a thread was running.  */
+;    else if (_tx_thread_current_ptr)
+;    {
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        ; Pickup current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_idle_system_save        ; If so, interrupt occurred in 
+                                                ;   scheduling loop - nothing needs saving!
+;
+;    /* Save minimal context of interrupted thread.  */
+;
+    MRS     r2, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r2, r10, r12, lr}             ; Store other registers
+;
+;    /* Save the current stack pointer in the thread's control block.  */
+;    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+;
+;    /* Switch to the system stack.  */
+;    sp =  _tx_thread_system_stack_ptr;
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    B       __tx_irq_processing_return          ; Continue IRQ processing 
+;
+;    }
+;    else
+;    {
+;
+__tx_thread_idle_system_save
+;
+;    /* Interrupt occurred in the scheduling loop.  */
+;
+;    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+;       processing.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    ADD     sp, sp, #16                         ; Recover saved registers
+    B       __tx_irq_processing_return          ; Continue IRQ processing  
+;
+;    }
+;}
+;
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s
new file mode 100644
index 00000000..c80122bb
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_restore.s
@@ -0,0 +1,245 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+SVC_MODE        EQU     0xD3                    ; SVC mode
+FIQ_MODE        EQU     0xD1                    ; FIQ mode
+MODE_MASK       EQU     0x1F                    ; Mode mask 
+IRQ_MODE_BITS   EQU     0x12                    ; IRQ mode bits
+;
+;
+    IMPORT      _tx_thread_system_state
+    IMPORT      _tx_thread_current_ptr
+    IMPORT      _tx_thread_system_stack_ptr
+    IMPORT      _tx_thread_execute_ptr
+    IMPORT      _tx_timer_time_slice
+    IMPORT      _tx_thread_schedule
+    IMPORT      _tx_thread_preempt_disable
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT      _tx_execution_isr_exit
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_fiq_context_restore                     Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function restores the fiq interrupt context when processing a  */ 
+;/*    nested interrupt.  If not, it returns to the interrupt thread if no */ 
+;/*    preemption is necessary.  Otherwise, if preemption is necessary or  */ 
+;/*    if no thread was running, the function returns to the scheduler.    */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                   Thread scheduling routine     */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    FIQ ISR                               Interrupt Service Routines    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_fiq_context_restore(VOID)
+;{
+    EXPORT  _tx_thread_fiq_context_restore
+_tx_thread_fiq_context_restore
+;
+;    /* Lockout interrupts.  */
+;
+    CPSID   if                                  ; Disable IRQ and FIQ interrupts
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR exit function to indicate an ISR is complete.  */
+;
+    BL      _tx_execution_isr_exit              ; Call the ISR exit function
+    ENDIF
+;
+;    /* Determine if interrupts are nested.  */
+;    if (--_tx_thread_system_state)
+;    {
+;
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3]                            ; Pickup system state
+    SUB     r2, r2, #1                          ; Decrement the counter
+    STR     r2, [r3]                            ; Store the counter 
+    CMP     r2, #0                              ; Was this the first interrupt?
+    BEQ     __tx_thread_fiq_not_nested_restore  ; If so, not a nested restore
+;
+;    /* Interrupts are nested.  */
+;
+;    /* Just recover the saved registers and return to the point of 
+;       interrupt.  */
+;
+    LDMIA   sp!, {r0, r10, r12, lr}             ; Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       ; Put SPSR back
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOVS    pc, lr                              ; Return to point of interrupt
+;
+;    }
+__tx_thread_fiq_not_nested_restore
+;
+;    /* Determine if a thread was interrupted and no preemption is required.  */
+;    else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) 
+;               || (_tx_thread_preempt_disable))
+;    {
+;
+    LDR     r1, [sp]                            ; Pickup the saved SPSR
+    MOV     r2, #MODE_MASK                      ; Build mask to isolate the interrupted mode
+    AND     r1, r1, r2                          ; Isolate mode bits
+    CMP     r1, #IRQ_MODE_BITS                  ; Was an interrupt taken in IRQ mode before we
+                                                ;   got to context save? */
+    BEQ     __tx_thread_fiq_no_preempt_restore  ; Yes, just go back to point of interrupt
+
+
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1]                            ; Pickup actual current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted
+
+    LDR     r3, =_tx_thread_preempt_disable     ; Pickup preempt disable address
+    LDR     r2, [r3]                            ; Pickup actual preempt disable flag
+    CMP     r2, #0                              ; Is it set?
+    BNE     __tx_thread_fiq_no_preempt_restore  ; Yes, don't preempt this thread
+    LDR     r3, =_tx_thread_execute_ptr         ; Pickup address of execute thread ptr
+    LDR     r2, [r3]                            ; Pickup actual execute thread pointer
+    CMP     r0, r2                              ; Is the same thread highest priority?
+    BNE     __tx_thread_fiq_preempt_restore     ; No, preemption needs to happen
+
+
+__tx_thread_fiq_no_preempt_restore
+;
+;    /* Restore interrupted thread or ISR.  */
+;
+;    /* Pickup the saved stack pointer.  */
+;    tmp_ptr =  _tx_thread_current_ptr -> tx_thread_stack_ptr; 
+;
+;    /* Recover the saved context and return to the point of interrupt.  */
+;
+    LDMIA   sp!, {r0, lr}                       ; Recover SPSR, POI, and scratch regs
+    MSR     SPSR_cxsf, r0                       ; Put SPSR back
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOVS    pc, lr                              ; Return to point of interrupt
+;
+;    }
+;    else
+;    {
+__tx_thread_fiq_preempt_restore
+;
+    LDMIA   sp!, {r3, lr}                       ; Recover temporarily saved registers
+    MOV     r1, lr                              ; Save lr (point of interrupt)
+    MOV     r2, #SVC_MODE                       ; Build SVC mode CPSR
+    MSR     CPSR_c, r2                          ; Enter SVC mode
+    STR     r1, [sp, #-4]!                      ; Save point of interrupt
+    STMDB   sp!, {r4-r12, lr}                   ; Save upper half of registers
+    MOV     r4, r3                              ; Save SPSR in r4
+    MOV     r2, #FIQ_MODE                       ; Build FIQ mode CPSR
+    MSR     CPSR_c, r2                          ; Re-enter FIQ mode
+    LDMIA   sp!, {r0-r3}                        ; Recover r0-r3
+    MOV     r5, #SVC_MODE                       ; Build SVC mode CPSR
+    MSR     CPSR_c, r5                          ; Enter SVC mode
+    STMDB   sp!, {r0-r3}                        ; Save r0-r3 on thread's stack
+    MOV     r3, #1                              ; Build interrupt stack type
+    STMDB   sp!, {r3, r4}                       ; Save interrupt stack type and SPSR
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1]                            ; Pickup current thread pointer
+    STR     sp, [r0, #8]                        ; Save stack pointer in thread control
+                                                ;   block  
+;
+;    /* Save the remaining time-slice and disable it.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    LDR     r3, =_tx_timer_time_slice           ; Pickup time-slice variable address
+    LDR     r2, [r3]                            ; Pickup time-slice
+    CMP     r2, #0                              ; Is it active?
+    BEQ     __tx_thread_fiq_dont_save_ts        ; No, don't save it
+;
+;        _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+;        _tx_timer_time_slice =  0; 
+;
+    STR     r2, [r0, #24]                       ; Save thread's time-slice
+    MOV     r2, #0                              ; Clear value
+    STR     r2, [r3]                            ; Disable global time-slice flag
+;
+;    }
+__tx_thread_fiq_dont_save_ts
+;
+;
+;    /* Clear the current task pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;
+    MOV     r0, #0                              ; NULL value
+    STR     r0, [r1]                            ; Clear current thread pointer
+;
+;    /* Return to the scheduler.  */
+;    _tx_thread_schedule();
+;
+    B       _tx_thread_schedule                 ; Return to scheduler
+;    }
+;
+__tx_thread_fiq_idle_system_restore
+;
+;    /* Just return back to the scheduler!  */
+;
+    ADD     sp, sp, #24                         ; Recover FIQ stack space
+    MOV     r3, #SVC_MODE                       ; Build SVC mode CPSR
+    MSR     CPSR_c, r3                          ; Enter SVC mode
+    B       _tx_thread_schedule                 ; Return to scheduler
+;
+;}
+;
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s
new file mode 100644
index 00000000..d3fceec4
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_context_save.s
@@ -0,0 +1,203 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    IMPORT      _tx_thread_system_state
+    IMPORT      _tx_thread_current_ptr
+    IMPORT      __tx_fiq_processing_return
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT      _tx_execution_isr_enter
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_fiq_context_save                        Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function saves the context of an executing thread in the       */ 
+;/*    beginning of interrupt processing.  The function also ensures that  */ 
+;/*    the system stack is used upon return to the calling ISR.            */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+; VOID   _tx_thread_fiq_context_save(VOID)
+;{
+    EXPORT  _tx_thread_fiq_context_save
+_tx_thread_fiq_context_save
+;
+;    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+;       out, we are in IRQ mode, and all registers are intact.  */
+;
+;    /* Check for a nested interrupt condition.  */
+;    if (_tx_thread_system_state++)
+;    {
+;
+    STMDB   sp!, {r0-r3}                        ; Save some working registers 
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3]                            ; Pickup system state
+    CMP     r2, #0                              ; Is this the first interrupt?
+    BEQ     __tx_thread_fiq_not_nested_save     ; Yes, not a nested context save
+;
+;    /* Nested interrupt condition.  */
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3]                            ; Store it back in the variable
+;
+;    /* Save the rest of the scratch registers on the stack and return to the
+;       calling ISR.  */
+;
+    MRS     r0, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r0, r10, r12, lr}             ; Store other registers
+;
+;    /* Return to the ISR.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    B       __tx_fiq_processing_return          ; Continue FIQ processing 
+;
+__tx_thread_fiq_not_nested_save
+;    }  
+;
+;    /* Otherwise, not nested, check to see if a thread was running.  */
+;    else if (_tx_thread_current_ptr)
+;    {   
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3]                            ; Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1]                            ; Pickup current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_fiq_idle_system_save    ; If so, interrupt occurred in 
+;                                               ;   scheduling loop - nothing needs saving! 
+;
+;    /* Save minimal context of interrupted thread.  */
+;
+    MRS     r2, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r2, lr}                       ; Store other registers, Note that we don't
+;                                               ;   need to save sl and ip since FIQ has 
+;                                               ;   copies of these registers.  Nested 
+;                                               ;   interrupt processing does need to save
+;                                               ;   these registers.
+;
+;    /* Save the current stack pointer in the thread's control block.  */
+;    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp; 
+;
+;    /* Switch to the system stack.  */
+;    sp =  _tx_thread_system_stack_ptr; 
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    B       __tx_fiq_processing_return          ; Continue FIQ processing 
+;
+;   }
+;   else
+;   {
+;
+__tx_thread_fiq_idle_system_save
+;
+;    /* Interrupt occurred in the scheduling loop.  */
+;
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+;
+;    /* Not much to do here, save the current SPSR and LR for possible
+;       use in IRQ interrupted in idle system conditions, and return to 
+;       FIQ interrupt processing.  */
+;
+    MRS     r0, SPSR                            ; Pickup saved SPSR
+    SUB     lr, lr, #4                          ; Adjust point of interrupt 
+    STMDB   sp!, {r0, lr}                       ; Store other registers that will get used
+;                                               ;   or stripped off the stack in context 
+;                                               ;   restore 
+    B       __tx_fiq_processing_return          ; Continue FIQ processing  
+;
+;    }
+;}  
+;
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_end.s
new file mode 100644
index 00000000..0bfad1ba
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_end.s
@@ -0,0 +1,111 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+DISABLE_INTS    EQU     0xC0                    ; Disable IRQ & FIQ interrupts
+    ELSE
+DISABLE_INTS    EQU     0x80                    ; Disable IRQ interrupts
+    ENDIF
+MODE_MASK       EQU     0x1F                    ; Mode mask 
+FIQ_MODE_BITS   EQU     0x11                    ; FIQ mode bits
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_fiq_nesting_end                         Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is called by the application from FIQ mode after      */ 
+;/*    _tx_thread_fiq_nesting_start has been called and switches the FIQ   */ 
+;/*    processing from system mode back to FIQ mode prior to the ISR       */ 
+;/*    calling _tx_thread_fiq_context_restore.  Note that this function    */ 
+;/*    assumes the system stack pointer is in the same position after      */ 
+;/*    nesting start function was called.                                  */ 
+;/*                                                                        */ 
+;/*    This function assumes that the system mode stack pointer was setup  */ 
+;/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+;/*                                                                        */ 
+;/*    This function returns with FIQ interrupts disabled.                 */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_fiq_nesting_end(VOID)
+;{
+    EXPORT  _tx_thread_fiq_nesting_end
+_tx_thread_fiq_nesting_end
+    MOV     r3,lr                               ; Save ISR return address
+    MRS     r0, CPSR                            ; Pickup the CPSR
+    ORR     r0, r0, #DISABLE_INTS               ; Build disable interrupt value
+    MSR     CPSR_c, r0                          ; Disable interrupts
+    LDMIA   sp!, {r1, lr}                       ; Pickup saved lr (and r1 throw-away for 
+                                                ;   8-byte alignment logic)
+    BIC     r0, r0, #MODE_MASK                  ; Clear mode bits
+    ORR     r0, r0, #FIQ_MODE_BITS              ; Build IRQ mode CPSR
+    MSR     CPSR_c, r0                          ; Re-enter IRQ mode
+    IF  {INTER} = {TRUE}
+    BX      r3                                  ; Return to caller
+    ELSE
+    MOV     pc, r3                              ; Return to caller
+    ENDIF
+;}
+;
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_start.s
new file mode 100644
index 00000000..fc9c725e
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_fiq_nesting_start.s
@@ -0,0 +1,104 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+FIQ_DISABLE     EQU     0x40                    ; FIQ disable bit
+MODE_MASK       EQU     0x1F                    ; Mode mask
+SYS_MODE_BITS   EQU     0x1F                    ; System mode bits
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_fiq_nesting_start                       Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is called by the application from FIQ mode after      */ 
+;/*    _tx_thread_fiq_context_save has been called and switches the FIQ    */ 
+;/*    processing to the system mode so nested FIQ interrupt processing    */ 
+;/*    is possible (system mode has its own "lr" register).  Note that     */ 
+;/*    this function assumes that the system mode stack pointer was setup  */ 
+;/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+;/*                                                                        */ 
+;/*    This function returns with FIQ interrupts enabled.                  */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_fiq_nesting_start(VOID)
+;{
+    EXPORT  _tx_thread_fiq_nesting_start
+_tx_thread_fiq_nesting_start
+    MOV     r3,lr                               ; Save ISR return address
+    MRS     r0, CPSR                            ; Pickup the CPSR
+    BIC     r0, r0, #MODE_MASK                  ; Clear the mode bits
+    ORR     r0, r0, #SYS_MODE_BITS              ; Build system mode CPSR
+    MSR     CPSR_c, r0                          ; Enter system mode
+    STMDB   sp!, {r1, lr}                       ; Push the system mode lr on the system mode stack
+                                                ;   and push r1 just to keep 8-byte alignment
+    BIC     r0, r0, #FIQ_DISABLE                ; Build enable FIQ CPSR
+    MSR     CPSR_c, r0                          ; Enter system mode
+    IF  {INTER} = {TRUE}
+    BX      r3                                  ; Return to caller
+    ELSE
+    MOV     pc, r3                              ; Return to caller
+    ENDIF
+;}
+;
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_r5/ac5/src/tx_thread_interrupt_control.s
new file mode 100644
index 00000000..856eae8d
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_interrupt_control.s
@@ -0,0 +1,102 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+INT_MASK        EQU         0xC0                ; Interrupt bit mask
+    ELSE
+INT_MASK        EQU         0x80                ; Interrupt bit mask
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_interrupt_control                       Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for changing the interrupt lockout     */ 
+;/*    posture of the system.                                              */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    new_posture                           New interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    old_posture                           Old interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    Application Code                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_control(UINT new_posture)
+;{
+    EXPORT  _tx_thread_interrupt_control
+_tx_thread_interrupt_control
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    MRS     r3, CPSR                            ; Pickup current CPSR
+    BIC     r1, r3, #INT_MASK                   ; Clear interrupt lockout bits
+    ORR     r1, r1, r0                          ; Or-in new interrupt lockout bits
+;
+;    /* Apply the new interrupt posture.  */
+;
+    MSR     CPSR_c, r1                          ; Setup new CPSR
+    AND     r0, r3, #INT_MASK                   ; Return previous interrupt mask
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+;}
+;
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_r5/ac5/src/tx_thread_interrupt_disable.s
new file mode 100644
index 00000000..f558daa3
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_interrupt_disable.s
@@ -0,0 +1,95 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_interrupt_disable                       Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for disabling interrupts               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    old_posture                           Old interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    Application Code                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_disable(void)
+;{
+    EXPORT _tx_thread_interrupt_disable
+_tx_thread_interrupt_disable
+;
+;    /* Pickup current interrupt lockout posture.  */
+;
+    MRS     r0, CPSR                            ; Pickup current CPSR
+;
+;    /* Mask interrupts.  */
+;
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Disable IRQ and FIQ
+    ELSE
+    CPSID   i                                   ; Disable IRQ 
+    ENDIF
+
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;}
+;
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_r5/ac5/src/tx_thread_interrupt_restore.s
new file mode 100644
index 00000000..e0b1e8ef
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_interrupt_restore.s
@@ -0,0 +1,87 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_interrupt_restore                       Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is responsible for restoring interrupts to the state  */
+;/*    returned by a previous _tx_thread_interrupt_disable call.           */
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    old_posture                           Old interrupt lockout posture */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    Application Code                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;UINT   _tx_thread_interrupt_restore(UINT old_posture)
+;{
+    EXPORT  _tx_thread_interrupt_restore
+_tx_thread_interrupt_restore
+;
+;    /* Apply the new interrupt posture.  */
+;
+    MSR     CPSR_c, r0                          ; Setup new CPSR
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;}
+;
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_end.s
new file mode 100644
index 00000000..67a6526d
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_end.s
@@ -0,0 +1,110 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+DISABLE_INTS    EQU     0xC0                    ; Disable IRQ & FIQ interrupts
+    ELSE
+DISABLE_INTS    EQU     0x80                    ; Disable IRQ interrupts
+    ENDIF
+MODE_MASK       EQU     0x1F                    ; Mode mask 
+IRQ_MODE_BITS   EQU     0x12                    ; IRQ mode bits
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_irq_nesting_end                         Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is called by the application from IRQ mode after      */ 
+;/*    _tx_thread_irq_nesting_start has been called and switches the IRQ   */ 
+;/*    processing from system mode back to IRQ mode prior to the ISR       */ 
+;/*    calling _tx_thread_context_restore.  Note that this function        */ 
+;/*    assumes the system stack pointer is in the same position after      */ 
+;/*    nesting start function was called.                                  */ 
+;/*                                                                        */ 
+;/*    This function assumes that the system mode stack pointer was setup  */ 
+;/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+;/*                                                                        */ 
+;/*    This function returns with IRQ interrupts disabled.                 */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_irq_nesting_end(VOID)
+;{
+    EXPORT  _tx_thread_irq_nesting_end
+_tx_thread_irq_nesting_end
+    MOV     r3,lr                               ; Save ISR return address
+    MRS     r0, CPSR                            ; Pickup the CPSR
+    ORR     r0, r0, #DISABLE_INTS               ; Build disable interrupt value
+    MSR     CPSR_c, r0                          ; Disable interrupts
+    LDMIA   sp!, {r1, lr}                       ; Pickup saved lr (and r1 throw-away for 
+                                                ;   8-byte alignment logic)
+    BIC     r0, r0, #MODE_MASK                  ; Clear mode bits
+    ORR     r0, r0, #IRQ_MODE_BITS              ; Build IRQ mode CPSR
+    MSR     CPSR_c, r0                          ; Re-enter IRQ mode
+    IF  {INTER} = {TRUE}
+    BX      r3                                  ; Return to caller
+    ELSE
+    MOV     pc, r3                              ; Return to caller
+    ENDIF
+;}
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_start.s
new file mode 100644
index 00000000..9096f016
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_irq_nesting_start.s
@@ -0,0 +1,104 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+IRQ_DISABLE     EQU     0x80                    ; IRQ disable bit
+MODE_MASK       EQU     0x1F                    ; Mode mask
+SYS_MODE_BITS   EQU     0x1F                    ; System mode bits
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_irq_nesting_start                       Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is called by the application from IRQ mode after      */ 
+;/*    _tx_thread_context_save has been called and switches the IRQ        */ 
+;/*    processing to the system mode so nested IRQ interrupt processing    */ 
+;/*    is possible (system mode has its own "lr" register).  Note that     */ 
+;/*    this function assumes that the system mode stack pointer was setup  */ 
+;/*    during low-level initialization (tx_initialize_low_level.s).        */ 
+;/*                                                                        */ 
+;/*    This function returns with IRQ interrupts enabled.                  */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_irq_nesting_start(VOID)
+;{
+    EXPORT  _tx_thread_irq_nesting_start
+_tx_thread_irq_nesting_start
+    MOV     r3,lr                               ; Save ISR return address
+    MRS     r0, CPSR                            ; Pickup the CPSR
+    BIC     r0, r0, #MODE_MASK                  ; Clear the mode bits
+    ORR     r0, r0, #SYS_MODE_BITS              ; Build system mode CPSR
+    MSR     CPSR_c, r0                          ; Enter system mode
+    STMDB   sp!, {r1, lr}                       ; Push the system mode lr on the system mode stack
+                                                ;   and push r1 just to keep 8-byte alignment
+    BIC     r0, r0, #IRQ_DISABLE                ; Build enable IRQ CPSR
+    MSR     CPSR_c, r0                          ; Enter system mode
+    IF  {INTER} = {TRUE}
+    BX      r3                                  ; Return to caller
+    ELSE
+    MOV     pc, r3                              ; Return to caller
+    ENDIF
+;}
+;
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_schedule.s b/ports/cortex_r5/ac5/src/tx_thread_schedule.s
new file mode 100644
index 00000000..f4857766
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_schedule.s
@@ -0,0 +1,233 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IMPORT     _tx_thread_execute_ptr
+    IMPORT     _tx_thread_current_ptr
+    IMPORT     _tx_timer_time_slice
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT     _tx_execution_thread_enter
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                                Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function waits for a thread control block pointer to appear in */ 
+;/*    the _tx_thread_execute_ptr variable.  Once a thread pointer appears */ 
+;/*    in the variable, the corresponding thread is resumed.               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_initialize_kernel_enter          ThreadX entry function         */ 
+;/*    _tx_thread_system_return             Return to system from thread   */ 
+;/*    _tx_thread_context_restore           Restore thread's context       */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_schedule(VOID)
+;{
+    EXPORT  _tx_thread_schedule
+_tx_thread_schedule
+;
+;    /* Enable interrupts.  */
+;
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSIE   if                                  ; Enable IRQ and FIQ interrupts
+    ELSE
+    CPSIE   i                                   ; Enable IRQ interrupts
+    ENDIF
+;
+;    /* Wait for a thread to execute.  */
+;    do
+;    {
+    LDR     r1, =_tx_thread_execute_ptr         ; Address of thread execute ptr
+;
+__tx_thread_schedule_loop
+;
+    LDR     r0, [r1, #0]                        ; Pickup next thread to execute
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_schedule_loop           ; If so, keep looking for a thread
+;
+;    }
+;    while(_tx_thread_execute_ptr == TX_NULL);
+;    
+;    /* Yes! We have a thread to execute.  Lockout interrupts and
+;       transfer control to it.  */
+;
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Enable IRQ and FIQ interrupts
+    ELSE
+    CPSID   i                                   ; Enable IRQ interrupts
+    ENDIF
+;
+;    /* Setup the current thread pointer.  */
+;    _tx_thread_current_ptr =  _tx_thread_execute_ptr;
+;
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread 
+    STR     r0, [r1, #0]                        ; Setup current thread pointer
+;
+;    /* Increment the run count for this thread.  */
+;    _tx_thread_current_ptr -> tx_thread_run_count++;
+;
+    LDR     r2, [r0, #4]                        ; Pickup run counter
+    LDR     r3, [r0, #24]                       ; Pickup time-slice for this thread
+    ADD     r2, r2, #1                          ; Increment thread run-counter
+    STR     r2, [r0, #4]                        ; Store the new run counter
+;
+;    /* Setup time-slice, if present.  */
+;    _tx_timer_time_slice =  _tx_thread_current_ptr -> tx_thread_time_slice;
+;
+    LDR     r2, =_tx_timer_time_slice           ; Pickup address of time slice 
+                                                ;   variable
+    LDR     sp, [r0, #8]                        ; Switch stack pointers
+    STR     r3, [r2, #0]                        ; Setup time-slice
+;
+;    /* Switch to the thread's stack.  */
+;    sp =  _tx_thread_execute_ptr -> tx_thread_stack_ptr;
+;
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread entry function to indicate the thread is executing.  */
+;
+    BL      _tx_execution_thread_enter          ; Call the thread execution enter function
+    ENDIF
+;
+;    /* Determine if an interrupt frame or a synchronous task suspension frame
+;       is present.  */
+;
+    LDMIA   sp!, {r4, r5}                       ; Pickup the stack type and saved CPSR
+    CMP     r4, #0                              ; Check for synchronous context switch
+    BEQ     _tx_solicited_return
+    MSR     SPSR_cxsf, r5                       ; Setup SPSR for return
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    LDR     r1, [r0, #144]                      ; Pickup the VFP enabled flag
+    CMP     r1, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_interrupt_vfp_restore      ; No, skip VFP interrupt restore
+    VLDMIA  sp!, {D0-D15}                       ; Recover D0-D15
+    LDR     r4, [sp], #4                        ; Pickup FPSCR
+    VMSR    FPSCR, r4                           ; Restore FPSCR
+_tx_skip_interrupt_vfp_restore
+    ENDIF
+    LDMIA   sp!, {r0-r12, lr, pc}^              ; Return to point of thread interrupt
+
+_tx_solicited_return
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    LDR     r1, [r0, #144]                      ; Pickup the VFP enabled flag
+    CMP     r1, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_solicited_vfp_restore      ; No, skip VFP solicited restore
+    VLDMIA  sp!, {D8-D15}                       ; Recover D8-D15
+    LDR     r4, [sp], #4                        ; Pickup FPSCR
+    VMSR    FPSCR, r4                           ; Restore FPSCR
+_tx_skip_solicited_vfp_restore
+    ENDIF
+    MOV     r0, r5                              ; Move CPSR to scratch register
+    LDMIA   sp!, {r4-r11, lr}                   ; Return to thread synchronously
+    MSR     CPSR_cxsf, r0                       ; Recover CPSR
+
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+;}
+;
+
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    EXPORT  tx_thread_vfp_enable
+tx_thread_vfp_enable
+    MRS     r2, CPSR                            ; Pickup the CPSR
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Enable IRQ and FIQ interrupts
+    ELSE
+    CPSID   i                                   ; Enable IRQ interrupts
+    ENDIF
+    LDR     r0, =_tx_thread_current_ptr         ; Build current thread pointer address
+    LDR     r1, [r0]                            ; Pickup current thread pointer
+    CMP     r1, #0                              ; Check for NULL thread pointer
+    BEQ     __tx_no_thread_to_enable            ; If NULL, skip VFP enable
+    MOV     r0, #1                              ; Build enable value
+    STR     r0, [r1, #144]                      ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
+__tx_no_thread_to_enable
+    MSR     CPSR_cxsf, r2                       ; Recover CPSR
+    BX      LR                                  ; Return to caller
+
+    EXPORT  tx_thread_vfp_disable
+tx_thread_vfp_disable
+    MRS     r2, CPSR                            ; Pickup the CPSR
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Enable IRQ and FIQ interrupts
+    ELSE
+    CPSID   i                                   ; Enable IRQ interrupts
+    ENDIF
+    LDR     r0, =_tx_thread_current_ptr         ; Build current thread pointer address
+    LDR     r1, [r0]                            ; Pickup current thread pointer
+    CMP     r1, #0                              ; Check for NULL thread pointer
+    BEQ     __tx_no_thread_to_disable           ; If NULL, skip VFP disable
+    MOV     r0, #0                              ; Build disable value
+    STR     r0, [r1, #144]                      ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
+__tx_no_thread_to_disable
+    MSR     CPSR_cxsf, r2                       ; Recover CPSR
+    BX      LR                                  ; Return to caller
+    ENDIF
+
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_stack_build.s b/ports/cortex_r5/ac5/src/tx_thread_stack_build.s
new file mode 100644
index 00000000..26281be6
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_stack_build.s
@@ -0,0 +1,164 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+SVC_MODE        EQU     0x13                    ; SVC mode
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+CPSR_MASK       EQU     0xDF                    ; Mask initial CPSR, IRQ & FIQ ints enabled
+    ELSE
+CPSR_MASK       EQU     0x9F                    ; Mask initial CPSR, IRQ ints enabled
+    ENDIF
+
+THUMB_BIT       EQU     0x20                    ; Thumb-bit
+
+;
+;
+        AREA ||.text||, CODE, READONLY
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_stack_build                             Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function builds a stack frame on the supplied thread's stack.  */
+;/*    The stack frame results in a fake interrupt return to the supplied  */
+;/*    function pointer.                                                   */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    thread_ptr                            Pointer to thread control blk */
+;/*    function_ptr                          Pointer to return function    */
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    _tx_thread_create                     Create thread service         */
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
+;{
+    EXPORT  _tx_thread_stack_build
+_tx_thread_stack_build
+;
+;       
+;    /* Build a fake interrupt frame.  The form of the fake interrupt stack
+;       on the Cortex-R5 should look like the following after it is built:
+;       
+;       Stack Top:      1           Interrupt stack frame type
+;                       CPSR        Initial value for CPSR
+;                       a1 (r0)     Initial value for a1
+;                       a2 (r1)     Initial value for a2
+;                       a3 (r2)     Initial value for a3
+;                       a4 (r3)     Initial value for a4
+;                       v1 (r4)     Initial value for v1
+;                       v2 (r5)     Initial value for v2
+;                       v3 (r6)     Initial value for v3
+;                       v4 (r7)     Initial value for v4
+;                       v5 (r8)     Initial value for v5
+;                       sb (r9)     Initial value for sb
+;                       sl (r10)    Initial value for sl
+;                       fp (r11)    Initial value for fp
+;                       ip (r12)    Initial value for ip
+;                       lr (r14)    Initial value for lr
+;                       pc (r15)    Initial value for pc
+;                       0           For stack backtracing
+;
+;    Stack Bottom: (higher memory address)  */
+;
+    LDR     r2, [r0, #16]                       ; Pickup end of stack area
+    BIC     r2, r2, #7                          ; Ensure 8-byte alignment
+    SUB     r2, r2, #76                         ; Allocate space for the stack frame
+;
+;    /* Actually build the stack frame.  */
+;
+    MOV     r3, #1                              ; Build interrupt stack type
+    STR     r3, [r2, #0]                        ; Store stack type
+    MOV     r3, #0                              ; Build initial register value
+    STR     r3, [r2, #8]                        ; Store initial r0
+    STR     r3, [r2, #12]                       ; Store initial r1
+    STR     r3, [r2, #16]                       ; Store initial r2
+    STR     r3, [r2, #20]                       ; Store initial r3
+    STR     r3, [r2, #24]                       ; Store initial r4
+    STR     r3, [r2, #28]                       ; Store initial r5
+    STR     r3, [r2, #32]                       ; Store initial r6
+    STR     r3, [r2, #36]                       ; Store initial r7
+    STR     r3, [r2, #40]                       ; Store initial r8
+    STR     r3, [r2, #44]                       ; Store initial r9
+    LDR     r3, [r0, #12]                       ; Pickup stack starting address
+    STR     r3, [r2, #48]                       ; Store initial r10 (sl)
+    MOV     r3, #0                              ; Build initial register value
+    STR     r3, [r2, #52]                       ; Store initial r11
+    STR     r3, [r2, #56]                       ; Store initial r12
+    STR     r3, [r2, #60]                       ; Store initial lr
+    STR     r1, [r2, #64]                       ; Store initial pc
+    STR     r3, [r2, #68]                       ; 0 for back-trace
+
+    MRS     r3, CPSR                            ; Pickup CPSR
+    BIC     r3, r3, #CPSR_MASK                  ; Mask mode bits of CPSR
+    ORR     r3, r3, #SVC_MODE                   ; Build CPSR, SVC mode, interrupts enabled
+    BIC     r3, r3, #THUMB_BIT                  ; Clear Thumb-bit by default
+    AND     r1, r1, #1                          ; Determine if the entry function is in Thumb mode
+    CMP     r1, #1                              ; Is the Thumb-bit set?
+    ORREQ   r3, r3, #THUMB_BIT                  ; Yes, set the Thumb-bit
+    STR     r3, [r2, #4]                        ; Store initial CPSR
+;
+;    /* Setup stack pointer.  */
+;    thread_ptr -> tx_thread_stack_ptr =  r2;
+;
+    STR     r2, [r0, #8]                        ; Save stack pointer in thread's
+                                                ;   control block
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;}
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_system_return.s b/ports/cortex_r5/ac5/src/tx_thread_system_return.s
new file mode 100644
index 00000000..5ecd61fd
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_system_return.s
@@ -0,0 +1,158 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;#include "tx_timer.h"
+;
+;
+    IMPORT      _tx_thread_current_ptr
+    IMPORT      _tx_timer_time_slice
+    IMPORT      _tx_thread_schedule
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT      _tx_execution_thread_exit        
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_system_return                           Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function is target processor specific.  It is used to transfer */ 
+;/*    control from a thread back to the ThreadX system.  Only a           */ 
+;/*    minimal context is saved since the compiler assumes temp registers  */ 
+;/*    are going to get slicked by a function call anyway.                 */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_thread_schedule                   Thread scheduling loop        */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ThreadX components                                                  */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_thread_system_return(VOID)
+;{
+    EXPORT  _tx_thread_system_return
+_tx_thread_system_return
+;
+;   /* Lockout interrupts.  */
+;
+    MRS     r1, CPSR                            ; Pickup the CPSR
+    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Disable IRQ and FIQ interrupts
+    ELSE
+    CPSID   i                                   ; Disable IRQ interrupts
+    ENDIF
+;    /* Save minimal context on the stack.  */
+;
+    STMDB   sp!, {r4-r11, lr}                   ; Save minimal context
+    LDR     r5, =_tx_thread_current_ptr         ; Pickup address of current ptr
+    LDR     r6, [r5, #0]                        ; Pickup current thread pointer
+
+    IF  {TARGET_FPU_VFP} = {TRUE}
+    LDR     r0, [r6, #144]                      ; Pickup the VFP enabled flag
+    CMP     r0, #0                              ; Is the VFP enabled?
+    BEQ     _tx_skip_solicited_vfp_save         ; No, skip VFP solicited save
+    VMRS    r4, FPSCR                           ; Pickup the FPSCR
+    STR     r4, [sp, #-4]!                      ; Save FPSCR
+    VSTMDB  sp!, {D8-D15}                       ; Save D8-D15
+_tx_skip_solicited_vfp_save
+    ENDIF
+
+    MOV     r0, #0                              ; Build a solicited stack type
+    STMDB   sp!, {r0-r1}                        ; Save type and CPSR
+;   
+;
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the thread exit function to indicate the thread is no longer executing.  */
+;
+    BL      _tx_execution_thread_exit           ; Call the thread exit function
+    ENDIF
+
+    LDR     r2, =_tx_timer_time_slice           ; Pickup address of time slice
+    LDR     r1, [r2, #0]                        ; Pickup current time slice
+;
+;    /* Save current stack and switch to system stack.  */
+;    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+;    sp = _tx_thread_system_stack_ptr;
+;
+    STR     sp, [r6, #8]                        ; Save thread stack pointer
+;
+;    /* Determine if the time-slice is active.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    MOV     r4, #0                              ; Build clear value
+    CMP     r1, #0                              ; Is a time-slice active?
+    BEQ     __tx_thread_dont_save_ts            ; No, don't save the time-slice
+;
+;       /* Save time-slice for the thread and clear the current time-slice.  */
+;       _tx_thread_current_ptr -> tx_thread_time_slice =  _tx_timer_time_slice;
+;       _tx_timer_time_slice =  0;
+;
+    STR     r4, [r2, #0]                        ; Clear time-slice
+    STR     r1, [r6, #24]                       ; Save current time-slice
+;
+;    }
+__tx_thread_dont_save_ts
+;
+;    /* Clear the current thread pointer.  */
+;    _tx_thread_current_ptr =  TX_NULL;
+;
+    STR     r4, [r5, #0]                        ; Clear current thread pointer
+    B       _tx_thread_schedule                 ; Jump to scheduler!
+;
+;}
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s
new file mode 100644
index 00000000..77015e9a
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_thread_vectored_context_save.s
@@ -0,0 +1,200 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Thread                                                              */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_thread.h"
+;
+;
+    IMPORT      _tx_thread_system_state
+    IMPORT      _tx_thread_current_ptr
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+    IMPORT      _tx_execution_isr_enter
+    ENDIF
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_thread_vectored_context_save                   Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function saves the context of an executing thread in the       */ 
+;/*    beginning of interrupt processing.  The function also ensures that  */ 
+;/*    the system stack is used upon return to the calling ISR.            */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    ISRs                                                                */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID  _tx_thread_vectored_context_save(VOID)
+;{
+    EXPORT  _tx_thread_vectored_context_save
+_tx_thread_vectored_context_save
+;
+;    /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
+;       out, we are in IRQ mode, and all registers are intact.  */
+;
+;    /* Check for a nested interrupt condition.  */
+;    if (_tx_thread_system_state++)
+;    {
+;
+    IF :DEF:TX_ENABLE_FIQ_SUPPORT
+    CPSID   if                                  ; Disable IRQ and FIQ interrupts
+    ENDIF
+    LDR     r3, =_tx_thread_system_state        ; Pickup address of system state var
+    LDR     r2, [r3, #0]                        ; Pickup system state
+    CMP     r2, #0                              ; Is this the first interrupt?
+    BEQ     __tx_thread_not_nested_save         ; Yes, not a nested context save
+;
+;    /* Nested interrupt condition.  */
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+;
+;    /* Note: Minimal context of interrupted thread is already saved.  */
+;
+;    /* Return to the ISR.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+    
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+__tx_thread_not_nested_save
+;    }
+;
+;    /* Otherwise, not nested, check to see if a thread was running.  */
+;    else if (_tx_thread_current_ptr)
+;    {
+;
+    ADD     r2, r2, #1                          ; Increment the interrupt counter
+    STR     r2, [r3, #0]                        ; Store it back in the variable
+    LDR     r1, =_tx_thread_current_ptr         ; Pickup address of current thread ptr
+    LDR     r0, [r1, #0]                        ; Pickup current thread pointer
+    CMP     r0, #0                              ; Is it NULL?
+    BEQ     __tx_thread_idle_system_save        ; If so, interrupt occurred in 
+                                                ;   scheduling loop - nothing needs saving!
+;
+;    /* Note: Minimal context of interrupted thread is already saved.  */
+;
+;    /* Save the current stack pointer in the thread's control block.  */
+;    _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
+;
+;    /* Switch to the system stack.  */
+;    sp =  _tx_thread_system_stack_ptr;
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+;    }
+;    else
+;    {
+;
+__tx_thread_idle_system_save
+;
+;    /* Interrupt occurred in the scheduling loop.  */
+;
+;    /* Not much to do here, just adjust the stack pointer, and return to IRQ 
+;       processing.  */
+;
+    MOV     r10, #0                             ; Clear stack limit
+
+    IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
+;
+;    /* Call the ISR enter function to indicate an ISR is executing.  */
+;
+    PUSH    {lr}                                ; Save ISR lr
+    BL      _tx_execution_isr_enter             ; Call the ISR enter function
+    POP     {lr}                                ; Recover ISR lr
+    ENDIF
+
+    ADD     sp, sp, #32                         ; Recover saved registers
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+;    }
+;}
+;
+    END
+
diff --git a/ports/cortex_r5/ac5/src/tx_timer_interrupt.s b/ports/cortex_r5/ac5/src/tx_timer_interrupt.s
new file mode 100644
index 00000000..d498e16f
--- /dev/null
+++ b/ports/cortex_r5/ac5/src/tx_timer_interrupt.s
@@ -0,0 +1,258 @@
+;/**************************************************************************/
+;/*                                                                        */
+;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
+;/*                                                                        */
+;/*       This software is licensed under the Microsoft Software License   */
+;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
+;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
+;/*       and in the root directory of this software.                      */
+;/*                                                                        */
+;/**************************************************************************/
+;
+;
+;/**************************************************************************/
+;/**************************************************************************/
+;/**                                                                       */ 
+;/** ThreadX Component                                                     */ 
+;/**                                                                       */
+;/**   Timer                                                               */
+;/**                                                                       */
+;/**************************************************************************/
+;/**************************************************************************/
+;
+;#define TX_SOURCE_CODE
+;
+;
+;/* Include necessary system files.  */
+;
+;#include "tx_api.h"
+;#include "tx_timer.h"
+;#include "tx_thread.h"
+;
+;
+;Define Assembly language external references...
+;
+    IMPORT      _tx_timer_time_slice
+    IMPORT      _tx_timer_system_clock
+    IMPORT      _tx_timer_current_ptr
+    IMPORT      _tx_timer_list_start
+    IMPORT      _tx_timer_list_end
+    IMPORT      _tx_timer_expired_time_slice
+    IMPORT      _tx_timer_expired
+    IMPORT      _tx_thread_time_slice
+    IMPORT      _tx_timer_expiration_process
+;
+;
+        AREA ||.text||, CODE, READONLY
+        PRESERVE8
+;/**************************************************************************/ 
+;/*                                                                        */ 
+;/*  FUNCTION                                               RELEASE        */ 
+;/*                                                                        */ 
+;/*    _tx_timer_interrupt                                Cortex-R5/AC5    */ 
+;/*                                                           6.0.1        */
+;/*  AUTHOR                                                                */
+;/*                                                                        */
+;/*    William E. Lamie, Microsoft Corporation                             */
+;/*                                                                        */
+;/*  DESCRIPTION                                                           */
+;/*                                                                        */ 
+;/*    This function processes the hardware timer interrupt.  This         */ 
+;/*    processing includes incrementing the system clock and checking for  */ 
+;/*    time slice and/or timer expiration.  If either is found, the        */ 
+;/*    interrupt context save/restore functions are called along with the  */ 
+;/*    expiration functions.                                               */ 
+;/*                                                                        */ 
+;/*  INPUT                                                                 */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  OUTPUT                                                                */ 
+;/*                                                                        */ 
+;/*    None                                                                */ 
+;/*                                                                        */ 
+;/*  CALLS                                                                 */ 
+;/*                                                                        */ 
+;/*    _tx_timer_expiration_process          Timer expiration processing   */ 
+;/*    _tx_thread_time_slice                 Time slice interrupted thread */ 
+;/*                                                                        */ 
+;/*  CALLED BY                                                             */ 
+;/*                                                                        */ 
+;/*    interrupt vector                                                    */ 
+;/*                                                                        */ 
+;/*  RELEASE HISTORY                                                       */ 
+;/*                                                                        */ 
+;/*    DATE              NAME                      DESCRIPTION             */
+;/*                                                                        */
+;/*  06-30-2020     William E. Lamie         Initial Version 6.0.1         */
+;/*                                                                        */
+;/**************************************************************************/
+;VOID   _tx_timer_interrupt(VOID)
+;{
+    EXPORT  _tx_timer_interrupt
+_tx_timer_interrupt
+;
+;    /* Upon entry to this routine, it is assumed that context save has already
+;       been called, and therefore the compiler scratch registers are available
+;       for use.  */
+;
+;    /* Increment the system clock.  */
+;    _tx_timer_system_clock++;
+;
+    LDR     r1, =_tx_timer_system_clock         ; Pickup address of system clock
+    LDR     r0, [r1, #0]                        ; Pickup system clock
+    ADD     r0, r0, #1                          ; Increment system clock
+    STR     r0, [r1, #0]                        ; Store new system clock
+;
+;    /* Test for time-slice expiration.  */
+;    if (_tx_timer_time_slice)
+;    {
+;
+    LDR     r3, =_tx_timer_time_slice           ; Pickup address of time-slice 
+    LDR     r2, [r3, #0]                        ; Pickup time-slice
+    CMP     r2, #0                              ; Is it non-active?
+    BEQ     __tx_timer_no_time_slice            ; Yes, skip time-slice processing
+;
+;       /* Decrement the time_slice.  */
+;       _tx_timer_time_slice--;
+;
+    SUB     r2, r2, #1                          ; Decrement the time-slice
+    STR     r2, [r3, #0]                        ; Store new time-slice value
+;
+;       /* Check for expiration.  */
+;       if (__tx_timer_time_slice == 0)
+;
+    CMP     r2, #0                              ; Has it expired?
+    BNE     __tx_timer_no_time_slice            ; No, skip expiration processing
+;
+;       /* Set the time-slice expired flag.  */
+;       _tx_timer_expired_time_slice =  TX_TRUE;
+;
+    LDR     r3, =_tx_timer_expired_time_slice   ; Pickup address of expired flag
+    MOV     r0, #1                              ; Build expired value
+    STR     r0, [r3, #0]                        ; Set time-slice expiration flag
+;
+;    }
+;
+__tx_timer_no_time_slice
+;
+;    /* Test for timer expiration.  */
+;    if (*_tx_timer_current_ptr)
+;    {
+;
+    LDR     r1, =_tx_timer_current_ptr          ; Pickup current timer pointer addr
+    LDR     r0, [r1, #0]                        ; Pickup current timer
+    LDR     r2, [r0, #0]                        ; Pickup timer list entry
+    CMP     r2, #0                              ; Is there anything in the list?
+    BEQ     __tx_timer_no_timer                 ; No, just increment the timer
+;
+;        /* Set expiration flag.  */
+;        _tx_timer_expired =  TX_TRUE;
+;
+    LDR     r3, =_tx_timer_expired              ; Pickup expiration flag address
+    MOV     r2, #1                              ; Build expired value
+    STR     r2, [r3, #0]                        ; Set expired flag
+    B       __tx_timer_done                     ; Finished timer processing
+;
+;    }
+;    else
+;    {
+__tx_timer_no_timer
+;
+;        /* No timer expired, increment the timer pointer.  */
+;        _tx_timer_current_ptr++;
+;
+    ADD     r0, r0, #4                          ; Move to next timer
+;
+;        /* Check for wrap-around.  */
+;        if (_tx_timer_current_ptr == _tx_timer_list_end)
+;
+    LDR     r3, =_tx_timer_list_end             ; Pickup addr of timer list end
+    LDR     r2, [r3, #0]                        ; Pickup list end
+    CMP     r0, r2                              ; Are we at list end?
+    BNE     __tx_timer_skip_wrap                ; No, skip wrap-around logic
+;
+;            /* Wrap to beginning of list.  */
+;            _tx_timer_current_ptr =  _tx_timer_list_start;
+;
+    LDR     r3, =_tx_timer_list_start           ; Pickup addr of timer list start
+    LDR     r0, [r3, #0]                        ; Set current pointer to list start
+;
+__tx_timer_skip_wrap
+;
+    STR     r0, [r1, #0]                        ; Store new current timer pointer
+;    }
+;
+__tx_timer_done
+;
+;
+;    /* See if anything has expired.  */
+;    if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
+;    {
+;
+    LDR     r3, =_tx_timer_expired_time_slice   ; Pickup addr of expired flag
+    LDR     r2, [r3, #0]                        ; Pickup time-slice expired flag
+    CMP     r2, #0                              ; Did a time-slice expire?
+    BNE     __tx_something_expired              ; If non-zero, time-slice expired
+    LDR     r1, =_tx_timer_expired              ; Pickup addr of other expired flag
+    LDR     r0, [r1, #0]                        ; Pickup timer expired flag
+    CMP     r0, #0                              ; Did a timer expire?
+    BEQ     __tx_timer_nothing_expired          ; No, nothing expired
+;
+__tx_something_expired
+;
+;
+    STMDB   sp!, {r0, lr}                       ; Save the lr register on the stack
+                                                ;   and save r0 just to keep 8-byte alignment
+;
+;    /* Did a timer expire?  */
+;    if (_tx_timer_expired)
+;    {
+;
+    LDR     r1, =_tx_timer_expired              ; Pickup addr of expired flag
+    LDR     r0, [r1, #0]                        ; Pickup timer expired flag
+    CMP     r0, #0                              ; Check for timer expiration
+    BEQ     __tx_timer_dont_activate            ; If not set, skip timer activation
+;
+;        /* Process timer expiration.  */
+;        _tx_timer_expiration_process();
+;
+    BL      _tx_timer_expiration_process        ; Call the timer expiration handling routine
+;
+;    }
+__tx_timer_dont_activate
+;
+;    /* Did time slice expire?  */
+;    if (_tx_timer_expired_time_slice)
+;    {
+;
+    LDR     r3, =_tx_timer_expired_time_slice   ; Pickup addr of time-slice expired 
+    LDR     r2, [r3, #0]                        ; Pickup the actual flag
+    CMP     r2, #0                              ; See if the flag is set
+    BEQ     __tx_timer_not_ts_expiration        ; No, skip time-slice processing
+;
+;        /* Time slice interrupted thread.  */
+;        _tx_thread_time_slice(); 
+
+    BL      _tx_thread_time_slice               ; Call time-slice processing
+;
+;    }
+;
+__tx_timer_not_ts_expiration
+;
+    LDMIA   sp!, {r0, lr}                       ; Recover lr register (r0 is just there for
+                                                ;   the 8-byte stack alignment
+;
+;    }
+;
+__tx_timer_nothing_expired
+;
+    IF  {INTER} = {TRUE}
+    BX      lr                                  ; Return to caller
+    ELSE
+    MOV     pc, lr                              ; Return to caller
+    ENDIF
+;
+;}
+    END
+
diff --git a/ports/cortex_r5/gnu/example_build/build_threadx.bat b/ports/cortex_r5/gnu/example_build/build_threadx.bat
new file mode 100644
index 00000000..210b9999
--- /dev/null
+++ b/ports/cortex_r5/gnu/example_build/build_threadx.bat
@@ -0,0 +1,238 @@
+del tx.a
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 tx_initialize_low_level.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_stack_build.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_schedule.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_system_return.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_context_save.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_context_restore.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_interrupt_control.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_timer_interrupt.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_interrupt_disable.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_interrupt_restore.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_fiq_context_save.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_fiq_nesting_start.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_irq_nesting_start.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_irq_nesting_end.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_fiq_nesting_end.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_fiq_context_restore.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_vectored_context_save.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c
+arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
+arm-none-eabi-ar -r tx.a tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_start.o tx_thread_irq_nesting_start.o tx_thread_irq_nesting_end.o
+arm-none-eabi-ar -r tx.a tx_thread_fiq_nesting_end.o tx_thread_fiq_context_restore.o tx_thread_vectored_context_save.o tx_initialize_low_level.o
+arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
+arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
+arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
+arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
+arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
+arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
+arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
+arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
+arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
+arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o 
+arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
+arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
+arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
+arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
+arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
+arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
+arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
+arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
+arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
+arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
+arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o 
+arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
+arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
+arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o 
+arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o 
+arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o 
+arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
+arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
+arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
+arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
+arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o 
+arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
+arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o
diff --git a/ports/cortex_r5/gnu/example_build/build_threadx_sample.bat b/ports/cortex_r5/gnu/example_build/build_threadx_sample.bat
new file mode 100644
index 00000000..2ded427d
--- /dev/null
+++ b/ports/cortex_r5/gnu/example_build/build_threadx_sample.bat
@@ -0,0 +1,6 @@
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 reset.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 crt0.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 tx_initialize_low_level.S
+arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc sample_threadx.c
+arm-none-eabi-ld -A cortex-r5 -T sample_threadx.ld reset.o crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libc.a libgcc.a -o sample_threadx.out -M > sample_threadx.map
+
diff --git a/ports/cortex_r5/gnu/example_build/crt0.S b/ports/cortex_r5/gnu/example_build/crt0.S
new file mode 100644
index 00000000..aa0f3239
--- /dev/null
+++ b/ports/cortex_r5/gnu/example_build/crt0.S
@@ -0,0 +1,90 @@
+
+/* .text is used instead of .section .text so it works with arm-aout too.  */
+    .text
+    .code 32
+    .align  0
+
+    .global _mainCRTStartup
+    .global _start
+    .global start
+start:
+_start:
+_mainCRTStartup:
+
+/* Start by setting up a stack */
+    /*  Set up the stack pointer to a fixed value */
+    ldr r3, .LC0
+    mov     sp, r3
+    /* Setup a default stack-limit in case the code has been
+       compiled with "-mapcs-stack-check".  Hard-wiring this value
+       is not ideal, since there is currently no support for
+       checking that the heap and stack have not collided, or that
+       this default 64k is enough for the program being executed.
+       However, it ensures that this simple crt0 world will not
+       immediately cause an overflow event:  */
+    sub sl, sp, #64 << 10   /* Still assumes 256bytes below sl */
+    mov     a2, #0          /* Second arg: fill value */
+    mov fp, a2          /* Null frame pointer */
+    mov r7, a2          /* Null frame pointer for Thumb */
+    
+    ldr a1, .LC1        /* First arg: start of memory block */
+    ldr a3, .LC2    
+    sub a3, a3, a1      /* Third arg: length of block */
+    
+
+    
+        bl      memset
+    mov r0, #0      /*  no arguments  */
+    mov r1, #0      /*  no argv either */
+#ifdef __USES_INITFINI__
+    /* Some arm/elf targets use the .init and .fini sections
+       to create constructors and destructors, and for these
+       targets we need to call the _init function and arrange
+       for _fini to be called at program exit.  */
+    mov r4, r0
+    mov r5, r1
+/*        ldr     r0, .Lfini */
+        bl      atexit
+/*        bl      init */
+    mov r0, r4
+    mov r1, r5
+#endif  
+        bl      main
+
+        bl      exit         /* Should not return.  */
+
+    
+    /* For Thumb, constants must be after the code since only 
+       positive offsets are supported for PC relative addresses.  */
+    
+    .align 0
+.LC0:
+.LC1:
+    .word   __bss_start__
+.LC2:
+    .word   __bss_end__
+/*
+#ifdef __USES_INITFINI__
+.Lfini:
+    .word   _fini
+#endif  */
+    /* Return ...  */
+#ifdef __APCS_26__
+    movs    pc, lr
+#else
+#ifdef __THUMB_INTERWORK
+    bx  lr
+#else
+    mov pc, lr
+#endif
+#endif
+
+
+/*  Workspace for Angel calls.  */
+    .data
+/*  Data returned by monitor SWI.  */
+.global __stack_base__
+HeapBase:   .word   0
+HeapLimit:  .word   0
+__stack_base__: .word   0
+StackLimit: .word   0
diff --git a/ports/cortex_r5/gnu/example_build/libc.a b/ports/cortex_r5/gnu/example_build/libc.a
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zyyk;0u~c5dm1R37av%P?23us%dHPGDpFT$0GBczAKYnN6rVuiJ<@W-;X3iNSdGtC4 zZc0Al4tY)&I-P!o0#6|ykg|z--55Au=wiVt!DWKHH_4BuyvA0+F2RcgFA>}#_#GlT dhn|!HpOEmEh$!@SiRZoRqCc?z|Ecwv{|7^Je? +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef __thumb__ + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); +#else +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) ); +#endif + +#define TX_RESTORE asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) ); + +#endif + + +/* Define VFP extension for the Cortex-A15. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/GNU Version 6.0 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a15/gnu/readme_threadx.txt b/ports/cortex_a15/gnu/readme_threadx.txt new file mode 100644 index 00000000..45fabd8e --- /dev/null +++ b/ports/cortex_a15/gnu/readme_threadx.txt @@ -0,0 +1,513 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A15 + + Using the GNU Tools + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. + +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + + +2. Demonstration System + +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file +that can be downloaded and executed. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A15 using GNU tools is at label _start. +This is defined within the modified version of the GNU startup code - crt0.S. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up various +system data structures, the interrupt vectors, and a periodic timer interrupt source. +By default, the vector area is defined to be located at the "__vectors" label, +which is defined in reset.S. This area is typically located at 0. In situations +where this is impossible, the vectors at the "__vectors" label should be copied +to address 0. + +This is also where initialization of a periodic timer interrupt source should take +place. + +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter +to your application definition function, tx_application_define. + + +4. Assembler / Compiler Switches + +The following are compiler switches used in building the demonstration +system: + +Compiler/Assembler Meaning + Switches + + -g Specifies debug information + -c Specifies object code generation + -mcpu=cortex-a15 Specifies target cpu + +Linker Switch Meaning + + -o sample_threadx.out Specifies output file + -M > sample_threadx.map Specifies demo map file + -A cortex-a15 Specifies target architecture + -T sample_threadx.ld Specifies the loader control file + +Application Defines ( -D option) + + TX_ENABLE_FIQ_SUPPORT This assembler define enables FIQ + interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + + TX_ENABLE_IRQ_NESTING This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.S. + + TX_ENABLE_FIQ_NESTING This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.S. In addition, + IRQ nesting should also be enabled. + + TX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ + interrupt handling in the ThreadX + generic C source. This define + should also be used in conjunction + with the corresponding assembler + define. + + TX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + TX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + TX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + TX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + TX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + TX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + TX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + TX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + TX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + TX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + TX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + TX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + TX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + TX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + TX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + TX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + TX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + TX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + TX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + +5. Register Usage and Stack Frames + +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) a15 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 a15 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A15 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A15 vectors start at address zero. The demonstration system startup +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +nested IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.S: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save @ Jump to the context save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.S: + + .global __tx_irq_example_handler +__tx_irq_example_handler: +@ +@ /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} @ Save some scratch registers + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers + BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call goes here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* Enable nested IRQ interrupts. NOTE: Since this service returns +@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Disable nested IRQ interrupts. The mode is switched back to +@ IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.S. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.S: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Enable nested FIQ interrupts. NOTE: Since this service returns +@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Disable nested FIQ interrupts. The mode is switched back to +@ FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of +ThreadX will still run. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.S for the demonstration system. + + +9. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A15 using GNU tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a15/gnu/src/tx_thread_context_restore.S b/ports/cortex_a15/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..d491780a --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,257 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE = 0xD3 @ Disable IRQ/FIQ, SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE = 0x93 @ Disable IRQ, SVC mode +IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode +#endif +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_restore @ Yes, idle system was interrupted +@ + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_preempt_restore @ No, preemption needs to happen +@ +@ +__tx_thread_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_preempt_restore: +@ + LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r2 @ Enter IRQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r0 @ Enter SVC mode + B _tx_thread_schedule @ Return to scheduler +@} + + + diff --git a/ports/cortex_a15/gnu/src/tx_thread_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..c62862cf --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_context_save.S @@ -0,0 +1,203 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_irq_processing_return + .global _tx_execution_isr_enter +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} @ Store other registers +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr@ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #16 @ Recover saved registers + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@} + + + diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S new file mode 100644 index 00000000..7a49178d --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_restore.S @@ -0,0 +1,260 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ +SVC_MODE = 0xD3 @ SVC mode +FIQ_MODE = 0xD1 @ FIQ mode +MODE_MASK = 0x1F @ Mode mask +THUMB_MASK = 0x20 @ Thumb bit mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_execution_isr_exit +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_context_restore(VOID) +@{ + .global _tx_thread_fiq_context_restore + .type _tx_thread_fiq_context_restore,function +_tx_thread_fiq_context_restore: +@ +@ /* Lockout interrupts. */ +@ + CPSID if @ Disable IRQ and FIQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_fiq_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, [sp] @ Pickup the saved SPSR + MOV r2, #MODE_MASK @ Build mask to isolate the interrupted mode + AND r1, r1, r2 @ Isolate mode bits + CMP r1, #IRQ_MODE_BITS @ Was an interrupt taken in IRQ mode before we + @ got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore @ Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore @ Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_fiq_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore @ No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_fiq_preempt_restore: +@ + LDMIA sp!, {r3, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR_c, r2 @ Reenter FIQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block */ +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_fiq_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_fiq_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + ADD sp, sp, #24 @ Recover FIQ stack space + MOV r3, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r3 @ Lockout interrupts + B _tx_thread_schedule @ Return to scheduler +@ +@} + diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S new file mode 100644 index 00000000..2ce9dc46 --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_context_save.S @@ -0,0 +1,204 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_fiq_processing_return + .global _tx_execution_isr_enter +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@ VOID _tx_thread_fiq_context_save(VOID) +@{ + .global _tx_thread_fiq_context_save + .type _tx_thread_fiq_context_save,function +_tx_thread_fiq_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +__tx_thread_fiq_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, lr} @ Store other registers, Note that we don't +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested +@ @ interrupt processing does need to save +@ @ these registers. +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_fiq_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif +@ +@ /* Not much to do here, save the current SPSR and LR for possible +@ use in IRQ interrupted in idle system conditions, and return to +@ FIQ interrupt processing. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, lr} @ Store other registers that will get used +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@} + diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S new file mode 100644 index 00000000..d1f31183 --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_end.S @@ -0,0 +1,116 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +FIQ_MODE_BITS = 0x11 @ FIQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_end(VOID) +@{ + .global _tx_thread_fiq_nesting_end + .type _tx_thread_fiq_nesting_end,function +_tx_thread_fiq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode + +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S new file mode 100644 index 00000000..8f6c34bf --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_fiq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +FIQ_DISABLE = 0x40 @ FIQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_start(VOID) +@{ + .global _tx_thread_fiq_nesting_start + .type _tx_thread_fiq_nesting_start,function +_tx_thread_fiq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..7ca32c7b --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" */ +@ + +INT_MASK = 0x03F + +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_control +$_tx_thread_interrupt_control: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_control(UINT new_posture) +@{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r3, CPSR @ Pickup current CPSR + MOV r2, #INT_MASK @ Build interrupt mask + AND r1, r3, r2 @ Clear interrupt lockout bits + ORR r1, r1, r0 @ Or-in new interrupt lockout bits +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r1 @ Setup new CPSR + BIC r0, r3, r2 @ Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..78a89b80 --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_disable.S @@ -0,0 +1,113 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_disable +$_tx_thread_interrupt_disable: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_disable(void) +@{ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r0, CPSR @ Pickup current CPSR +@ +@ /* Mask interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ +#else + CPSID i @ Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S b/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..8614e43a --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_interrupt_restore.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_restore +$_tx_thread_interrupt_restore: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring interrupts to the state */ +@/* returned by a previous _tx_thread_interrupt_disable call. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_restore(UINT old_posture) +@{ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r0 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..c414ab0b --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_end(VOID) +@{ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..6c433de5 --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +IRQ_DISABLE = 0x80 @ IRQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_start(VOID) +@{ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a15/gnu/src/tx_thread_schedule.S b/ports/cortex_a15/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..550e71ac --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_schedule.S @@ -0,0 +1,255 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_execution_thread_enter +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_schedule + .type $_tx_thread_schedule,function +$_tx_thread_schedule: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_schedule @ Call _tx_thread_schedule function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: +@ +@ /* Enable interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if @ Enable IRQ and FIQ interrupts +#else + CPSIE i @ Enable IRQ interrupts +#endif +@ +@ /* Wait for a thread to execute. */ +@ do +@ { + LDR r1, =_tx_thread_execute_ptr @ Address of thread execute ptr +@ +__tx_thread_schedule_loop: +@ + LDR r0, [r1] @ Pickup next thread to execute + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_schedule_loop @ If so, keep looking for a thread +@ +@ } +@ while(_tx_thread_execute_ptr == TX_NULL); +@ +@ /* Yes! We have a thread to execute. Lockout interrupts and +@ transfer control to it. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Setup the current thread pointer. */ +@ _tx_thread_current_ptr = _tx_thread_execute_ptr; +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + STR r0, [r1] @ Setup current thread pointer +@ +@ /* Increment the run count for this thread. */ +@ _tx_thread_current_ptr -> tx_thread_run_count++; +@ + LDR r2, [r0, #4] @ Pickup run counter + LDR r3, [r0, #24] @ Pickup time-slice for this thread + ADD r2, r2, #1 @ Increment thread run-counter + STR r2, [r0, #4] @ Store the new run counter +@ +@ /* Setup time-slice, if present. */ +@ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + @ variable + LDR sp, [r0, #8] @ Switch stack pointers + STR r3, [r2] @ Setup time-slice +@ +@ /* Switch to the thread's stack. */ +@ sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + MOV r5, r0 @ Save r0 + BL _tx_execution_thread_enter @ Call the thread execution enter function + MOV r0, r5 @ Restore r0 +#endif +@ +@ /* Determine if an interrupt frame or a synchronous task suspension frame +@ is present. */ +@ + LDMIA sp!, {r4, r5} @ Pickup the stack type and saved CPSR + CMP r4, #0 @ Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 @ Setup SPSR for return +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore @ No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} @ Recover D0-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt + +_tx_solicited_return: + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore @ No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} @ Recover D8-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 @ Recover CPSR + LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ + +#ifdef TX_ENABLE_VFP_SUPPORT + + .global tx_thread_vfp_enable + .type tx_thread_vfp_enable,function +tx_thread_vfp_enable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable + MOV r0, #1 @ Build enable value + STR r0, [r1, #144] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + + .global tx_thread_vfp_disable + .type tx_thread_vfp_disable,function +tx_thread_vfp_disable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable + MOV r0, #0 @ Build disable value + STR r0, [r1, #144] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + +#endif + diff --git a/ports/cortex_a15/gnu/src/tx_thread_stack_build.S b/ports/cortex_a15/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..3b3b75b4 --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,178 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ + .arm + +SVC_MODE = 0x13 @ SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ interrupts enabled +#else +CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interrupts enabled +#endif +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_thread_stack_build + .type $_tx_thread_stack_build,function +$_tx_thread_stack_build: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_stack_build @ Call _tx_thread_stack_build function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-A15 should look like the following after it is built: +@ +@ Stack Top: 1 Interrupt stack frame type +@ CPSR Initial value for CPSR +@ a1 (r0) Initial value for a1 +@ a2 (r1) Initial value for a2 +@ a3 (r2) Initial value for a3 +@ a4 (r3) Initial value for a4 +@ v1 (r4) Initial value for v1 +@ v2 (r5) Initial value for v2 +@ v3 (r6) Initial value for v3 +@ v4 (r7) Initial value for v4 +@ v5 (r8) Initial value for v5 +@ sb (r9) Initial value for sb +@ sl (r10) Initial value for sl +@ fp (r11) Initial value for fp +@ ip (r12) Initial value for ip +@ lr (r14) Initial value for lr +@ pc (r15) Initial value for pc +@ 0 For stack backtracing +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #7 @ Ensure 8-byte alignment + SUB r2, r2, #76 @ Allocate space for the stack frame +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #1 @ Build interrupt stack type + STR r3, [r2, #0] @ Store stack type + MOV r3, #0 @ Build initial register value + STR r3, [r2, #8] @ Store initial r0 + STR r3, [r2, #12] @ Store initial r1 + STR r3, [r2, #16] @ Store initial r2 + STR r3, [r2, #20] @ Store initial r3 + STR r3, [r2, #24] @ Store initial r4 + STR r3, [r2, #28] @ Store initial r5 + STR r3, [r2, #32] @ Store initial r6 + STR r3, [r2, #36] @ Store initial r7 + STR r3, [r2, #40] @ Store initial r8 + STR r3, [r2, #44] @ Store initial r9 + LDR r3, [r0, #12] @ Pickup stack starting address + STR r3, [r2, #48] @ Store initial r10 (sl) + LDR r3,=_tx_thread_schedule @ Pickup address of _tx_thread_schedule for GDB backtrace + STR r3, [r2, #60] @ Store initial r14 (lr) + MOV r3, #0 @ Build initial register value + STR r3, [r2, #52] @ Store initial r11 + STR r3, [r2, #56] @ Store initial r12 + STR r1, [r2, #64] @ Store initial pc + STR r3, [r2, #68] @ 0 for back-trace + MRS r1, CPSR @ Pickup CPSR + BIC r1, r1, #CPSR_MASK @ Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] @ Store initial CPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a15/gnu/src/tx_thread_system_return.S b/ports/cortex_a15/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..b3a3fe65 --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_system_return.S @@ -0,0 +1,180 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm +@ +@ + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_execution_thread_exit +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_system_return + .type $_tx_thread_system_return,function +$_tx_thread_system_return: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_system_return @ Call _tx_thread_system_return function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_system_return(VOID) +@{ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: +@ +@ /* Save minimal context on the stack. */ +@ + STMDB sp!, {r4-r11, lr} @ Save minimal context + + LDR r4, =_tx_thread_current_ptr @ Pickup address of current ptr + LDR r5, [r4] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r5, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save @ No, skip VFP solicited save + VMRS r1, FPSCR @ Pickup the FPSCR + STR r1, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D8-D15} @ Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 @ Build a solicited stack type + MRS r1, CPSR @ Pickup the CPSR + STMDB sp!, {r0-r1} @ Save type and CPSR +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + BL _tx_execution_thread_exit @ Call the thread exit function +#endif + MOV r3, r4 @ Pickup address of current ptr + MOV r0, r5 @ Pickup current thread pointer + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + LDR r1, [r2] @ Pickup current time slice +@ +@ /* Save current stack and switch to system stack. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ sp = _tx_thread_system_stack_ptr; +@ + STR sp, [r0, #8] @ Save thread stack pointer +@ +@ /* Determine if the time-slice is active. */ +@ if (_tx_timer_time_slice) +@ { +@ + MOV r4, #0 @ Build clear value + CMP r1, #0 @ Is a time-slice active? + BEQ __tx_thread_dont_save_ts @ No, don't save the time-slice +@ +@ /* Save time-slice for the thread and clear the current time-slice. */ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r4, [r2] @ Clear time-slice + STR r1, [r0, #24] @ Save current time-slice +@ +@ } +__tx_thread_dont_save_ts: +@ +@ /* Clear the current thread pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + STR r4, [r3] @ Clear current thread pointer + B _tx_thread_schedule @ Jump to scheduler! +@ +@} + diff --git a/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S b/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..7b7a5d9f --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_thread_vectored_context_save.S @@ -0,0 +1,190 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_execution_isr_enter +@ +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_vectored_context_save(VOID) +@{ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #32 @ Recover saved registers + MOV pc, lr @ Return to caller +@ +@ } +@} + diff --git a/ports/cortex_a15/gnu/src/tx_timer_interrupt.S b/ports/cortex_a15/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..1dc0e511 --- /dev/null +++ b/ports/cortex_a15/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,279 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ + .arm + +@ +@/* Define Assembly language external references... */ +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_timer_interrupt + .type $_tx_timer_interrupt,function +$_tx_timer_interrupt: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_timer_interrupt @ Call _tx_timer_interrupt function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-A15/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1] @ Pickup current timer + LDR r2, [r0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wraparound. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup address of timer list end + LDR r2, [r3] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wraparound logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup address of timer list start + LDR r0, [r3] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + LDR r2, [r3] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup address of other expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup address of expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r2, [r3] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} + diff --git a/ports/cortex_a5/ac5/example_build/build_threadx.bat b/ports/cortex_a5/ac5/example_build/build_threadx.bat new file mode 100644 index 00000000..d0c3a2cb --- /dev/null +++ b/ports/cortex_a5/ac5/example_build/build_threadx.bat @@ -0,0 +1,238 @@ +del tx.a +armasm -g --cpu=cortex-a5 --apcs=interwork tx_initialize_low_level.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_stack_build.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_schedule.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_system_return.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_context_save.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_context_restore.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_interrupt_control.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_timer_interrupt.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_fiq_context_restore.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_fiq_context_save.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_fiq_nesting_end.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_fiq_nesting_start.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_interrupt_disable.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_interrupt_restore.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_irq_nesting_end.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_irq_nesting_start.s +armasm -g --cpu=cortex-a5 --apcs=interwork ../src/tx_thread_vectored_context_save.s +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +armcc -g --cpu=cortex-a5 -c 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--cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +armcc -g --cpu=cortex-a5 -c -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +armar -r tx.a tx_initialize_low_level.o tx_thread_fiq_context_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_end.o tx_thread_fiq_nesting_start.o tx_thread_interrupt_disable.o +armar -r tx.a tx_thread_interrupt_restore.o tx_thread_irq_nesting_end.o tx_thread_irq_nesting_start.o +armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_a5/ac5/example_build/build_threadx_sample.bat b/ports/cortex_a5/ac5/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..6ef816c4 --- /dev/null +++ b/ports/cortex_a5/ac5/example_build/build_threadx_sample.bat @@ -0,0 +1,4 @@ +armasm -g --cpu=cortex-a5 --apcs=interwork tx_initialize_low_level.s +armcc -c -g --cpu=cortex-a5 -I../../../../common/inc -I../inc sample_threadx.c +armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --first tx_initialize_low_level.o(Init) --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a + diff --git a/ports/cortex_a5/ac5/example_build/sample_threadx.c b/ports/cortex_a5/ac5/example_build/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_a5/ac5/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a5/ac5/example_build/tx_initialize_low_level.s b/ports/cortex_a5/ac5/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..03505b66 --- /dev/null +++ b/ports/cortex_a5/ac5/example_build/tx_initialize_low_level.s @@ -0,0 +1,394 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +FIQ_MODE EQU 0xD1 ; FIQ mode +IRQ_MODE EQU 0xD2 ; IRQ mode +SVC_MODE EQU 0xD3 ; SVC mode +SYS_MODE EQU 0xDF ; SYS mode + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +FIQ_MODE EQU 0x91 ; FIQ mode +IRQ_MODE EQU 0x92 ; IRQ mode +SVC_MODE EQU 0x93 ; SVC mode +SYS_MODE EQU 0x9F ; SYS mode + ENDIF +HEAP_SIZE EQU 4096 ; Heap size +FIQ_STACK_SIZE EQU 512 ; FIQ stack size +SYS_STACK_SIZE EQU 1024 ; SYS stack size (used for nested interrupts) +IRQ_STACK_SIZE EQU 1024 ; IRQ stack size +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IF :DEF:TX_ENABLE_FIQ_SUPPORT + IMPORT _tx_thread_fiq_context_save + IMPORT _tx_thread_fiq_context_restore + ENDIF + IF :DEF:TX_ENABLE_IRQ_NESTING + IMPORT _tx_thread_irq_nesting_start + IMPORT _tx_thread_irq_nesting_end + ENDIF + IF :DEF:TX_ENABLE_FIQ_NESTING + IMPORT _tx_thread_fiq_nesting_start + IMPORT _tx_thread_fiq_nesting_end + ENDIF + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT _tx_version_id + IMPORT _tx_build_options + IMPORT |Image$$ZI$$Limit| +; +; + AREA Init, CODE, READONLY +; +;/* Define the default Cortex-A5 vector area. This should be located or copied to 0. */ +; + EXPORT __vectors +__vectors + LDR pc,=__main ; Reset goes to startup function + LDR pc,=__tx_undefined ; Undefined handler + LDR pc,=__tx_swi_interrupt ; Software interrupt handler + LDR pc,=__tx_prefetch_handler ; Prefetch exception handler + LDR pc,=__tx_abort_handler ; Abort exception handler + LDR pc,=__tx_reserved_handler ; Reserved exception handler + LDR pc,=__tx_irq_handler ; IRQ interrupt handler + LDR pc,=__tx_fiq_handler ; FIQ interrupt handler +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; +; /****** NOTE ****** We must be in SVC MODE at this point. Some monitors +; enter this routine in USER mode and require a software interrupt to +; change into SVC mode. */ +; + LDR r1, =|Image$$ZI$$Limit| ; Get end of non-initialized RAM area + LDR r2, =HEAP_SIZE ; Pickup the heap size + ADD r1, r2, r1 ; Setup heap limit + ADD r1, r1, #4 ; Setup stack limit +; + IF :DEF:TX_ENABLE_IRQ_NESTING +; /* Setup the system mode stack for nested interrupt support */ + LDR r2, =SYS_STACK_SIZE ; Pickup stack size + MOV r3, #SYS_MODE ; Build SYS mode CPSR + MSR CPSR_c, r3 ; Enter SYS mode + ADD r1, r1, r2 ; Calculate start of SYS stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup SYS stack pointer + ENDIF +; + LDR r2, =FIQ_STACK_SIZE ; Pickup stack size + MOV r0, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_c, r0 ; Enter FIQ mode + ADD r1, r1, r2 ; Calculate start of FIQ stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup FIQ stack pointer + MOV sl, #0 ; Clear sl + MOV fp, #0 ; Clear fp + LDR r2, =IRQ_STACK_SIZE ; Pickup IRQ (system stack size) + MOV r0, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Enter IRQ mode + ADD r1, r1, r2 ; Calculate start of IRQ stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + MOV sp, r1 ; Setup IRQ stack pointer + MOV r0, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r0 ; Enter SVC mode + LDR r3, =_tx_thread_system_stack_ptr ; Pickup stack pointer + STR r1, [r3, #0] ; Save the system stack +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +; + LDR r1, =_tx_thread_system_stack_ptr ; Pickup address of system stack ptr + LDR r0, [r1, #0] ; Pickup system stack + ADD r0, r0, #4 ; Increment to next free word +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) |Image$$ZI$$Limit| + HEAP + [SYS_STACK] + FIQ_STACK + IRQ_STACK; +; + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; /* Setup Timer for periodic interrupts. */ +; +; /* Done, return to caller. */ +; + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; +; +;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This +; routine will set the initial stack to use the ThreadX IRQ & FIQ & +; (optionally SYS) stack areas. */ +; + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR r0, =|Image$$ZI$$Limit| ; Get end of non-initialized RAM area + LDR r2, =HEAP_SIZE ; Pickup the heap size + ADD r2, r2, r0 ; Setup heap limit + ADD r3, r2, #4 ; Setup stack limit + MOV r1, r3 ; Setup start of stack + IF :DEF:TX_ENABLE_IRQ_NESTING + LDR r12, =SYS_STACK_SIZE ; Pickup IRQ system stack + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + ENDIF + LDR r12, =FIQ_STACK_SIZE ; Pickup FIQ stack size + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + LDR r12, =IRQ_STACK_SIZE ; Pickup IRQ system stack + ADD r1, r1, r12 ; Setup the return system stack + BIC r1, r1, #7 ; Ensure 8-byte alignment + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; +;/* Define shells for each of the interrupt vectors. */ +; + EXPORT __tx_undefined +__tx_undefined + B __tx_undefined ; Undefined handler +; + EXPORT __tx_swi_interrupt +__tx_swi_interrupt + B __tx_swi_interrupt ; Software interrupt handler +; + EXPORT __tx_prefetch_handler +__tx_prefetch_handler + B __tx_prefetch_handler ; Prefetch exception handler +; + EXPORT __tx_abort_handler +__tx_abort_handler + B __tx_abort_handler ; Abort exception handler +; + EXPORT __tx_reserved_handler +__tx_reserved_handler + B __tx_reserved_handler ; Reserved exception handler +; +; + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; + BL _tx_timer_interrupt ; Timer interrupt handler +_tx_not_timer_interrupt +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ + IF :DEF:TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start + ENDIF +; +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ + IF :DEF:TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end + ENDIF +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +; +; +; /* This is an example of a vectored IRQ handler. */ +; + EXPORT __tx_example_vectored_irq_handler +__tx_example_vectored_irq_handler +; +; +; /* Save initial context and call context save to prepare for +; vectored ISR execution. */ +; +; STMDB sp!, {r0-r3} ; Save some scratch registers +; MRS r0, SPSR ; Pickup saved SPSR +; SUB lr, lr, #4 ; Adjust point of interrupt +; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers +; BL _tx_thread_vectored_context_save ; Vectored context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. In +; addition, IRQ interrupts may be re-enabled - with certain restrictions - +; if nested IRQ interrupts are desired. Interrupts may be re-enabled over +; small code sequences where lr is saved before enabling interrupts and +; restored after interrupts are again disabled. */ +; +; +; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +; from IRQ mode with interrupts disabled. This routine switches to the +; system mode and returns with IRQ interrupts enabled. +; +; NOTE: It is very important to ensure all IRQ interrupts are cleared +; prior to enabling nested IRQ interrupts. */ +; IF :DEF:TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_start +; ENDIF +; +; /* Application IRQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_context_restore. +; This routine returns in processing in IRQ mode with interrupts disabled. */ +; IF :DEF:TX_ENABLE_IRQ_NESTING +; BL _tx_thread_irq_nesting_end +; ENDIF +; +; /* Jump to context restore to restore system context. */ +; B _tx_thread_context_restore +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +; from FIQ mode with interrupts disabled. This routine switches to the +; system mode and returns with FIQ interrupts enabled. +; +; NOTE: It is very important to ensure all FIQ interrupts are cleared +; prior to enabling nested FIQ interrupts. */ + IF :DEF:TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start + ENDIF +; +; /* Application FIQ handlers can be called here! */ +; +; /* If interrupt nesting was started earlier, the end of interrupt nesting +; service must be called before returning to _tx_thread_fiq_context_restore. */ + IF :DEF:TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end + ENDIF +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +; +; + ELSE + EXPORT __tx_fiq_handler +__tx_fiq_handler + B __tx_fiq_handler ; FIQ interrupt handler + ENDIF +; +; /* Reference build options and version ID to ensure they come in. */ +; + LDR r2, =_tx_build_options ; Pickup build options variable address + LDR r0, [r2, #0] ; Pickup build options content + LDR r2, =_tx_version_id ; Pickup version ID variable address + LDR r0, [r2, #0] ; Pickup version ID content +; +; + END + diff --git a/ports/cortex_a5/ac5/inc/tx_port.h b/ports/cortex_a5/ac5/inc/tx_port.h new file mode 100644 index 00000000..d2f09195 --- /dev/null +++ b/ports/cortex_a5/ac5/inc/tx_port.h @@ -0,0 +1,334 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A5/AC5 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef __thumb + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (ULONG) __clz((unsigned int) m); \ + b = 31 - b; +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifndef __thumb + +#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; + +#ifdef TX_ENABLE_FIQ_SUPPORT + +/* IRQ and FIQ support. */ + +#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); \ + __disable_fiq(); + +#define TX_RESTORE if (!interrupt_save_disabled) \ + { \ + __enable_irq(); \ + __enable_fiq(); \ + } + +#else + +#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); + +#define TX_RESTORE if (!interrupt_save_disabled) \ + { \ + __enable_irq(); \ + } +#endif + +#else + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); +#endif + + +/* Define VFP extension for the Cortex-A5. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/AC5 Version 6.0 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a5/ac5/readme_threadx.txt b/ports/cortex_a5/ac5/readme_threadx.txt new file mode 100644 index 00000000..4dcbf556 --- /dev/null +++ b/ports/cortex_a5/ac5/readme_threadx.txt @@ -0,0 +1,545 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A5 + + Thumb & 32-bit Mode + + Using ARM Compiler 5 (AC5) + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the ARM +AC5 development environment. At this point you may run the build_threadx.bat +batch file. This will build the ThreadX run-time environment in the +"example_build" directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + +1.1 Building with Project Files + +The ThreadX library can also be built via project files. Simply open +the tx.mcp file with project builder and select make. This will place +the tx.a library file into the Debug sub-directory. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the ARM +Windows-based simulator. + +Building the demonstration is easy; simply execute the build_threadx_demo.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with tx.a. The resulting file sample_threadx.axf +is a binary file that can be downloaded and executed on the ARM simulator. + +2.0.1 Building with Project Files + +The ThreadX demonstration can also be built via project files. Simply open +the sample_threadx.mcp file with project builder and select make. This will place +the sample_threadx.axf output image into the Debug sub-directory. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A5 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning +of the Init area should be copied to address 0. + +This is also where initialization of a periodic timer interrupt source +should take place. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Assembler / Compiler Switches + +The following are compiler switches used in building the demonstration +system: + +Compiler Switch Meaning + + -g Specifies debug information + -c Specifies object code generation + --cpu Cortex-A5 Specifies Cortex-A5 instruction set + --apcs /interwork Specifies Thumb/32-bit compatibility + +Linker Switch Meaning + + -d Specifies to retain debug information in output file + -o demo.axf Specifies demo output file name + --elf Specifies elf output file format + --ro Specifies that Read-Only memory starts at address 0 + --first tx_initialize_low_level.o(Init) + Specifies that the first area loaded is Init + --remove Remove unused areas + --list Specifies map file name + --symbols Specifies symbols for map file + --map Creates a map file + +Application Defines + + --PD "TX_ENABLE_FIQ_SUPPORT SETL {TRUE}" This assembler define enables FIQ + interrupt handling support in the + ThreadX assembly files. If used, + it should be used on all assembly + files and the generic C source of + ThreadX should be compiled with + TX_ENABLE_FIQ_SUPPORT defined as well. + --PD "TX_ENABLE_IRQ_NESTING SETL {TRUE}" This assembler define enables IRQ + nested support. If IRQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. + --PD "TX_ENABLE_FIQ_NESTING SETL {TRUE}" This assembler define enables FIQ + nested support. If FIQ nested + interrupt support is needed, this + define should be applied to + tx_initialize_low_level.s. In addition, + IRQ nesting should also be enabled. + -DTX_ENABLE_FIQ_SUPPORT This compiler define enables FIQ + interrupt handling in the ThreadX + generic C source. This define + should also be used in conjunction + with the corresponding assembler + define. + -DTX_DISABLE_ERROR_CHECKING If defined before tx_api.h is included, + this define causes basic ThreadX error + checking to be disabled. Please see + Chapter 2 in the "ThreadX User Guide" + for more details. + + -DTX_MAX_PRIORITIES Defines the priority levels for ThreadX. + Legal values range from 32 through + 1024 (inclusive) and MUST be evenly divisible + by 32. Increasing the number of priority levels + supported increases the RAM usage by 128 bytes + for every group of 32 priorities. However, there + is only a negligible effect on performance. By + default, this value is set to 32 priority levels. + + -DTX_MINIMUM_STACK Defines the minimum stack size (in bytes). It is + used for error checking when threads are created. + The default value is port-specific and is found + in tx_port.h. + + -DTX_TIMER_THREAD_STACK_SIZE Defines the stack size (in bytes) of the internal + ThreadX timer thread. This thread processes all + thread sleep requests as well as all service call + timeouts. In addition, all application timer callback + routines are invoked from this context. The default + value is port-specific and is found in tx_port.h. + + -DTX_TIMER_THREAD_PRIORITY Defines the priority of the internal ThreadX timer + thread. The default value is priority 0 - the highest + priority in ThreadX. The default value is defined + in tx_port.h. + + -DTX_TIMER_PROCESS_IN_ISR Defined, this option eliminates the internal system + timer thread for ThreadX. This results in improved + performance on timer events and smaller RAM requirements + because the timer stack and control block are no + longer needed. However, using this option moves all + the timer expiration processing to the timer ISR level. + By default, this option is not defined. + + -DTX_REACTIVATE_INLINE Defined, this option performs reactivation of ThreadX + timers in-line instead of using a function call. This + improves performance but slightly increases code size. + By default, this option is not defined. + + -DTX_DISABLE_STACK_FILLING Defined, placing the 0xEF value in each byte of each + thread's stack is disabled. By default, this option is + not defined. + + -DTX_ENABLE_STACK_CHECKING Defined, this option enables ThreadX run-time stack checking, + which includes analysis of how much stack has been used and + examination of data pattern "fences" before and after the + stack area. If a stack error is detected, the registered + application stack error handler is called. This option does + result in slightly increased overhead and code size. Please + review the tx_thread_stack_error_notify API for more information. + By default, this option is not defined. + + -DTX_DISABLE_PREEMPTION_THRESHOLD Defined, this option disables the preemption-threshold feature + and slightly reduces code size and improves performance. Of course, + the preemption-threshold capabilities are no longer available. + By default, this option is not defined. + + -DTX_DISABLE_REDUNDANT_CLEARING Defined, this option removes the logic for initializing ThreadX + global C data structures to zero. This should only be used if + the compiler's initialization code sets all un-initialized + C global data to zero. Using this option slightly reduces + code size and improves performance during initialization. + By default, this option is not defined. + + -DTX_DISABLE_NOTIFY_CALLBACKS Defined, this option disables the notify callbacks for various + ThreadX objects. Using this option slightly reduces code size + and improves performance. + + -DTX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on block pools. By default, this option is + not defined. + + -DTX_BYTE_POOL_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on byte pools. By default, this option is + not defined. + + -DTX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on event flags groups. By default, this option + is not defined. + + -DTX_MUTEX_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on mutexes. By default, this option is + not defined. + + -DTX_QUEUE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on queues. By default, this option is + not defined. + + -DTX_SEMAPHORE_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on semaphores. By default, this option is + not defined. + + -DTX_THREAD_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on threads. By default, this option is + not defined. + + -DTX_TIMER_ENABLE_PERFORMANCE_INFO Defined, this option enables the gathering of performance + information on timers. By default, this option is + not defined. + + -DTX_ENABLE_EVENT_TRACE Defined, this option enables the internal ThreadX trace + feature. The trace buffer is supplied at a later time + via an application call to tx_trace_enable. + + -DTX_TRACE_TIME_SOURCE This defines the time-stamp source for event tracing. + This define is only pertinent if the ThreadX library is + built with TX_ENABLE_EVENT_TRACE defined. + + -DTX_TRACE_TIME_MASK This defines the number of valid bits in the event trace + time-stamp source defined previously. If the time-stamp + source is 16-bits, this value should be 0xFFFF. Alternatively, + if the time-stamp source is 32-bits, this value should be + 0xFFFFFFFF. This define is only pertinent if the ThreadX + library is built with TX_ENABLE_EVENT_TRACE defined. + + + +5. Register Usage and Stack Frames + +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A5 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A5 vectors start at address zero. The demonstration system startup +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save ; Jump to the context save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call(s) go here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + EXPORT __tx_irq_example_handler +__tx_irq_example_handler +; +; /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers + BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, +calling the _tx_thread_irq_nesting_end service disables nesting by disabling +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* Enable nested IRQ interrupts. NOTE: Since this service returns +; with IRQ interrupts enabled, all IRQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +; +; /* Application ISR call(s) go here! */ +; +; /* Disable nested IRQ interrupts. The mode is switched back to +; IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ handlers can be called here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ handlers can be called here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.s in the Integrator sub-directories. + + +9. Thumb/Cortex-A5 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built +with the "-apcs /interwork" option. + +11. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +12. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A5 using AC5 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a5/ac5/src/tx_thread_context_restore.s b/ports/cortex_a5/ac5/src/tx_thread_context_restore.s new file mode 100644 index 00000000..1434cb44 --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_context_restore.s @@ -0,0 +1,256 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +IRQ_MODE EQU 0xD2 ; IRQ mode +SVC_MODE EQU 0xD3 ; SVC mode + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +IRQ_MODE EQU 0x92 ; IRQ mode +SVC_MODE EQU 0x93 ; SVC mode + ENDIF +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save + ENDIF + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1, #0] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MOV r3, #SVC_MODE ; Build SVC mode with interrupts disabled + MSR CPSR_c, r3 ; Change to SVC mode + B _tx_thread_schedule ; Return to scheduler +;} +; + END + diff --git a/ports/cortex_a5/ac5/src/tx_thread_context_save.s b/ports/cortex_a5/ac5/src/tx_thread_context_save.s new file mode 100644 index 00000000..fac7c5a4 --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_context_save.s @@ -0,0 +1,200 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_irq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable FIQ interrupts + ENDIF + + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} ; Store other registers +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + ADD sp, sp, #16 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + END + diff --git a/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s b/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s new file mode 100644 index 00000000..66186e5a --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_fiq_context_restore.s @@ -0,0 +1,259 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +SVC_MODE EQU 0xD3 ; SVC mode +FIQ_MODE EQU 0xD1 ; FIQ mode +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_restore Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the fiq interrupt context when processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* FIQ ISR Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_context_restore(VOID) +;{ + EXPORT _tx_thread_fiq_context_restore +_tx_thread_fiq_context_restore +; +; /* Lockout interrupts. */ +; + CPSID if ; Disable IRQ and FIQ interrupts + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_fiq_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, [sp] ; Pickup the saved SPSR + MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode + AND r1, r1, r2 ; Isolate mode bits + CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we + ; got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + LDR r2, [r3] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore + +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_fiq_preempt_restore +; + LDMIA sp!, {r3, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #FIQ_MODE ; Build FIQ mode CPSR + MSR CPSR_c, r2 ; Re-enter FIQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r2, [r0, #144] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save ; No, skip VFP FIQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_fiq_vfp_save + ENDIF + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + LDR r2, [r3] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3] ; Disable global time-slice flag +; +; } +__tx_thread_fiq_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + MOV r0, #0 ; NULL value + STR r0, [r1] ; Clear current thread pointer +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_fiq_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + ADD sp, sp, #24 ; Recover FIQ stack space + MOV r3, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r3 ; Enter SVC mode + B _tx_thread_schedule ; Return to scheduler +; +;} +; + END + diff --git a/ports/cortex_a5/ac5/src/tx_thread_fiq_context_save.s b/ports/cortex_a5/ac5/src/tx_thread_fiq_context_save.s new file mode 100644 index 00000000..198ea091 --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_fiq_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_fiq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_context_save Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +; VOID _tx_thread_fiq_context_save(VOID) +;{ + EXPORT _tx_thread_fiq_context_save +_tx_thread_fiq_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_fiq_processing_return ; Continue FIQ processing +; +__tx_thread_fiq_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in +; ; scheduling loop - nothing needs saving! +; +; /* Save minimal context of interrupted thread. */ +; + MRS r2, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r2, lr} ; Store other registers, Note that we don't +; ; need to save sl and ip since FIQ has +; ; copies of these registers. Nested +; ; interrupt processing does need to save +; ; these registers. +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +; else +; { +; +__tx_thread_fiq_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF +; +; /* Not much to do here, save the current SPSR and LR for possible +; use in IRQ interrupted in idle system conditions, and return to +; FIQ interrupt processing. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, lr} ; Store other registers that will get used +; ; or stripped off the stack in context +; ; restore + B __tx_fiq_processing_return ; Continue FIQ processing +; +; } +;} +; + END + diff --git a/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_end.s b/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_end.s new file mode 100644 index 00000000..d1007354 --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_end.s @@ -0,0 +1,111 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_end Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +;/* processing from system mode back to FIQ mode prior to the ISR */ +;/* calling _tx_thread_fiq_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_end(VOID) +;{ + EXPORT _tx_thread_fiq_nesting_end +_tx_thread_fiq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_start.s b/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_start.s new file mode 100644 index 00000000..aa8e30bd --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_fiq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +FIQ_DISABLE EQU 0x40 ; FIQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_fiq_nesting_start Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from FIQ mode after */ +;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +;/* processing to the system mode so nested FIQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with FIQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_fiq_nesting_start(VOID) +;{ + EXPORT _tx_thread_fiq_nesting_start +_tx_thread_fiq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR + MSR CPSR_c, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a5/ac5/src/tx_thread_interrupt_control.s b/ports/cortex_a5/ac5/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..9c48eea6 --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_interrupt_control.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +INT_MASK EQU 0xC0 ; Interrupt bit mask + ELSE +INT_MASK EQU 0x80 ; Interrupt bit mask + ENDIF +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} +; + END + diff --git a/ports/cortex_a5/ac5/src/tx_thread_interrupt_disable.s b/ports/cortex_a5/ac5/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..b9996a64 --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_interrupt_disable.s @@ -0,0 +1,95 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(void) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ + ELSE + CPSID i ; Disable IRQ + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a5/ac5/src/tx_thread_interrupt_restore.s b/ports/cortex_a5/ac5/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..a331c9df --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_restore(UINT old_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r0 ; Setup new CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_end.s b/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..42d3fca2 --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + EXPORT _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} + END + diff --git a/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_start.s b/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..eb7c2952 --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +IRQ_DISABLE EQU 0x80 ; IRQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + EXPORT _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_c, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports/cortex_a5/ac5/src/tx_thread_schedule.s b/ports/cortex_a5/ac5/src/tx_thread_schedule.s new file mode 100644 index 00000000..6e250a23 --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_schedule.s @@ -0,0 +1,236 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_execute_ptr + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSIE if ; Enable IRQ and FIQ interrupts + ELSE + CPSIE i ; Enable IRQ interrupts + ENDIF +; +; /* Wait for a thread to execute. */ +; do +; { + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr +; +__tx_thread_schedule_loop +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr == TX_NULL); +; +; /* Yes! We have a thread to execute. Lockout interrupts and +; transfer control to it. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Enable IRQ and FIQ interrupts + ELSE + CPSID i ; Enable IRQ interrupts + ENDIF +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr = _tx_thread_execute_ptr; +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread + STR r0, [r1, #0] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ; variable + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 + ENDIF +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 ; Setup SPSR for return + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_interrupt_vfp_restore + ENDIF + LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + +_tx_solicited_return + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #144] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore + ENDIF + MSR CPSR_cxsf, r5 ; Recover CPSR + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} +; + + IF {TARGET_FPU_VFP} = {TRUE} + EXPORT tx_thread_vfp_enable +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + EXPORT tx_thread_vfp_disable +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + ENDIF + + END + diff --git a/ports/cortex_a5/ac5/src/tx_thread_stack_build.s b/ports/cortex_a5/ac5/src/tx_thread_stack_build.s new file mode 100644 index 00000000..00764f2b --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_stack_build.s @@ -0,0 +1,164 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE EQU 0x13 ; SVC mode + IF :DEF:TX_ENABLE_FIQ_SUPPORT +CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled + ELSE +CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled + ENDIF + +THUMB_BIT EQU 0x20 ; Thumb-bit + +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A5 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + + MRS r3, CPSR ; Pickup CPSR + BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r3, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT ; Clear Thumb-bit by default + AND r1, r1, #1 ; Determine if the entry function is in Thumb mode + CMP r1, #1 ; Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT ; Yes, set the Thumb-bit + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} + END + diff --git a/ports/cortex_a5/ac5/src/tx_thread_system_return.s b/ports/cortex_a5/ac5/src/tx_thread_system_return.s new file mode 100644 index 00000000..a5e3120b --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_system_return.s @@ -0,0 +1,159 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context + LDR r5, =_tx_thread_current_ptr ; Pickup address of current ptr + LDR r6, [r5, #0] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r0, [r6, #144] ; Pickup the VFP enabled flag + CMP r0, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save + ENDIF + + MOV r0, #0 ; Build a solicited stack type + MRS r1, CPSR ; Pickup the CPSR + STMDB sp!, {r0-r1} ; Save type and CPSR +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + BL _tx_execution_thread_exit ; Call the thread exit function + ENDIF + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr; +; + STR sp, [r6, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save the current remaining time-slice. */ +; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +; _tx_timer_time_slice = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r6, #24] ; Store current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr = TX_NULL; +; + STR r4, [r5, #0] ; Clear current thread pointer + + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports/cortex_a5/ac5/src/tx_thread_vectored_context_save.s b/ports/cortex_a5/ac5/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..375b9fad --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_thread_vectored_context_save.s @@ -0,0 +1,200 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + EXPORT _tx_thread_vectored_context_save +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ENDIF + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr} ; Recover ISR lr + ENDIF + + ADD sp, sp, #32 ; Recover saved registers + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +;} +; + END + diff --git a/ports/cortex_a5/ac5/src/tx_timer_interrupt.s b/ports/cortex_a5/ac5/src/tx_timer_interrupt.s new file mode 100644 index 00000000..422e3576 --- /dev/null +++ b/ports/cortex_a5/ac5/src/tx_timer_interrupt.s @@ -0,0 +1,258 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; +__tx_timer_not_ts_expiration +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired +; + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} + END + diff --git a/ports/cortex_a5/gnu/example_build/build_threadx.bat b/ports/cortex_a5/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..cad49aca --- /dev/null +++ b/ports/cortex_a5/gnu/example_build/build_threadx.bat @@ -0,0 +1,238 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_interrupt_disable.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_interrupt_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_fiq_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_fiq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_irq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_irq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_fiq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_fiq_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 ../src/tx_thread_vectored_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_high_level.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_enter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_initialize_kernel_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_analyze.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_preempt_check.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_timeout.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_expiration_process.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_system_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_timer_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_register.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_object_unregister.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_user_event_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/tx_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_start.o tx_thread_irq_nesting_start.o tx_thread_irq_nesting_end.o +arm-none-eabi-ar -r tx.a tx_thread_fiq_nesting_end.o tx_thread_fiq_context_restore.o tx_thread_vectored_context_save.o tx_initialize_low_level.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports/cortex_a5/gnu/example_build/build_threadx_sample.bat b/ports/cortex_a5/gnu/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..123a84c8 --- /dev/null +++ b/ports/cortex_a5/gnu/example_build/build_threadx_sample.bat @@ -0,0 +1,6 @@ +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 reset.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 crt0.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a5 -I../../../../common/inc -I../inc sample_threadx.c +arm-none-eabi-ld -A cortex-a5 -T sample_threadx.ld reset.o crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libc.a libgcc.a -o sample_threadx.out -M > sample_threadx.map + diff --git a/ports/cortex_a5/gnu/example_build/crt0.S b/ports/cortex_a5/gnu/example_build/crt0.S new file mode 100644 index 00000000..aa0f3239 --- /dev/null +++ b/ports/cortex_a5/gnu/example_build/crt0.S @@ -0,0 +1,90 @@ + +/* .text is used instead of .section .text so it works with arm-aout too. */ + .text + .code 32 + .align 0 + + .global _mainCRTStartup + .global _start + .global start +start: +_start: +_mainCRTStartup: + +/* Start by setting up a stack */ + /* Set up the stack pointer to a fixed value */ + ldr r3, .LC0 + mov sp, r3 + /* Setup a default stack-limit in case the code has been + compiled with "-mapcs-stack-check". Hard-wiring this value + is not ideal, since there is currently no support for + checking that the heap and stack have not collided, or that + this default 64k is enough for the program being executed. + However, it ensures that this simple crt0 world will not + immediately cause an overflow event: */ + sub sl, sp, #64 << 10 /* Still assumes 256bytes below sl */ + mov a2, #0 /* Second arg: fill value */ + mov fp, a2 /* Null frame pointer */ + mov r7, a2 /* Null frame pointer for Thumb */ + + ldr a1, .LC1 /* First arg: start of memory block */ + ldr a3, .LC2 + sub a3, a3, a1 /* Third arg: length of block */ + + + + bl memset + mov r0, #0 /* no arguments */ + mov r1, #0 /* no argv either */ +#ifdef __USES_INITFINI__ + /* Some arm/elf targets use the .init and .fini sections + to create constructors and destructors, and for these + targets we need to call the _init function and arrange + for _fini to be called at program exit. */ + mov r4, r0 + mov r5, r1 +/* ldr r0, .Lfini */ + bl atexit +/* bl init */ + mov r0, r4 + mov r1, r5 +#endif + bl main + + bl exit /* Should not return. */ + + + /* For Thumb, constants must be after the code since only + positive offsets are supported for PC relative addresses. */ + + .align 0 +.LC0: +.LC1: + .word __bss_start__ +.LC2: + .word __bss_end__ +/* +#ifdef __USES_INITFINI__ +.Lfini: + .word _fini +#endif */ + /* Return ... */ +#ifdef __APCS_26__ + movs pc, lr +#else +#ifdef __THUMB_INTERWORK + bx lr +#else + mov pc, lr +#endif +#endif + + +/* Workspace for Angel calls. */ + .data +/* Data returned by monitor SWI. */ +.global __stack_base__ +HeapBase: .word 0 +HeapLimit: .word 0 +__stack_base__: .word 0 +StackLimit: .word 0 diff --git a/ports/cortex_a5/gnu/example_build/libc.a b/ports/cortex_a5/gnu/example_build/libc.a new file mode 100644 index 0000000000000000000000000000000000000000..5b04fa4ed9b6479f70979f5577dd0705d1f6d1d7 GIT binary patch literal 2447586 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