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Release 6.2.1 on 08 Mar 2023. Expand to see details.
cee19603d Include tx_user.h conditionally. e40e08007 Update owners d69641273 Update release date and version 394aee52f Add tx_user.h to GNU port assembly files 5cca2ddd0 RISC-V 64 bit port for Microchip e0f2c373c Link Winmm.lib that required by the high-resolution timer. 6af472a68 Update Win32 port with high resolution timer. aea7b556a Add DMB ISH barrier inst in ARMv8-A SMP scheduler 19091a262 Add .section .preamble to m3 m4 m7 module ports ced60e1b7 Add missing parenthesis in ports assembly file 309dc77ca Modules Cortex-A7 IAR new port c752a4063 Modules Cortex-A7 GNU new port dc224b90f Fix race condition in tx_thread_wait_abort and update regression test 6e261f5b7 create threadx cmsis-pack
This commit is contained in:
Tiejun Zhou
302
ports/risc-v64/gnu/src/tx_thread_schedule.S
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302
ports/risc-v64/gnu/src/tx_thread_schedule.S
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/**************************************************************************/
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/* */
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/* Copyright (c) Microsoft Corporation. All rights reserved. */
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/* */
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/* This software is licensed under the Microsoft Software License */
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/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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/* and in the root directory of this software. */
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/* */
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/**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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/** */
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/** ThreadX Component */
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/** */
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/** Thread */
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/** */
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/**************************************************************************/
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/**************************************************************************/
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#include "tx_port.h"
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.section .text
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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/* */
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/* _tx_thread_schedule RISC-V64/GNU */
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/* 6.2.1 */
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/* AUTHOR */
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/* */
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/* Scott Larson, Microsoft Corporation */
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/* */
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/* DESCRIPTION */
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/* */
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/* This function waits for a thread control block pointer to appear in */
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/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
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/* in the variable, the corresponding thread is resumed. */
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/* */
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/* INPUT */
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/* */
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/* None */
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/* */
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/* OUTPUT */
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/* */
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/* None */
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/* */
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/* CALLS */
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/* */
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/* None */
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/* */
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/* CALLED BY */
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/* */
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/* _tx_initialize_kernel_enter ThreadX entry function */
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/* _tx_thread_system_return Return to system from thread */
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/* _tx_thread_context_restore Restore thread's context */
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/* */
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/* RELEASE HISTORY */
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 03-08-2023 Scott Larson Initial Version 6.2.1 */
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/* */
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/**************************************************************************/
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/* VOID _tx_thread_schedule(VOID)
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{ */
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.global _tx_thread_schedule
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_tx_thread_schedule:
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/* Enable interrupts. */
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csrsi mstatus, 0x08 // Enable interrupts
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/* Wait for a thread to execute. */
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/* do
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{ */
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la t0, _tx_thread_execute_ptr // Pickup address of execute ptr
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_tx_thread_schedule_loop:
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LOAD t1, 0(t0) // Pickup next thread to execute
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beqz t1, _tx_thread_schedule_loop // If NULL, wait for thread to execute
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/* }
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while(_tx_thread_execute_ptr == TX_NULL); */
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/* Yes! We have a thread to execute. Lockout interrupts and
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transfer control to it. */
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csrci mstatus, 0x08 // Lockout interrupts
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/* Setup the current thread pointer. */
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/* _tx_thread_current_ptr = _tx_thread_execute_ptr; */
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la t0, _tx_thread_current_ptr // Pickup current thread pointer address
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STORE t1, 0(t0) // Set current thread pointer
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/* Increment the run count for this thread. */
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/* _tx_thread_current_ptr -> tx_thread_run_count++; */
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LOAD t2, 1*REGBYTES(t1) // Pickup run count
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LOAD t3, 6*REGBYTES(t1) // Pickup time slice value
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addi t2, t2, 1 // Increment run count
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STORE t2, 1*REGBYTES(t1) // Store new run count
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/* Setup time-slice, if present. */
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/* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */
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la t2, _tx_timer_time_slice // Pickup time-slice variable address
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/* Switch to the thread's stack. */
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/* SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */
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LOAD sp, 2*REGBYTES(t1) // Switch to thread's stack
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STORE t3, 0(t2) // Store new time-slice*/
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
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call _tx_execution_thread_enter // Call the thread execution enter function
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#endif
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/* Determine if an interrupt frame or a synchronous task suspension frame
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is present. */
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LOAD t2, 0(sp) // Pickup stack type
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beqz t2, _tx_thread_synch_return // If 0, solicited thread return
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/* Determine if floating point registers need to be recovered. */
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#if defined(__riscv_float_abi_single)
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flw f0, 31*REGBYTES(sp) // Recover ft0
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flw f1, 32*REGBYTES(sp) // Recover ft1
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flw f2, 33*REGBYTES(sp) // Recover ft2
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flw f3, 34*REGBYTES(sp) // Recover ft3
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flw f4, 35*REGBYTES(sp) // Recover ft4
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flw f5, 36*REGBYTES(sp) // Recover ft5
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flw f6, 37*REGBYTES(sp) // Recover ft6
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flw f7, 38*REGBYTES(sp) // Recover ft7
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flw f8, 39*REGBYTES(sp) // Recover fs0
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flw f9, 40*REGBYTES(sp) // Recover fs1
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flw f10,41*REGBYTES(sp) // Recover fa0
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flw f11,42*REGBYTES(sp) // Recover fa1
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flw f12,43*REGBYTES(sp) // Recover fa2
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flw f13,44*REGBYTES(sp) // Recover fa3
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flw f14,45*REGBYTES(sp) // Recover fa4
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flw f15,46*REGBYTES(sp) // Recover fa5
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flw f16,47*REGBYTES(sp) // Recover fa6
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flw f17,48*REGBYTES(sp) // Recover fa7
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flw f18,49*REGBYTES(sp) // Recover fs2
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flw f19,50*REGBYTES(sp) // Recover fs3
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flw f20,51*REGBYTES(sp) // Recover fs4
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flw f21,52*REGBYTES(sp) // Recover fs5
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flw f22,53*REGBYTES(sp) // Recover fs6
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flw f23,54*REGBYTES(sp) // Recover fs7
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flw f24,55*REGBYTES(sp) // Recover fs8
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flw f25,56*REGBYTES(sp) // Recover fs9
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flw f26,57*REGBYTES(sp) // Recover fs10
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flw f27,58*REGBYTES(sp) // Recover fs11
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flw f28,59*REGBYTES(sp) // Recover ft8
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flw f29,60*REGBYTES(sp) // Recover ft9
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flw f30,61*REGBYTES(sp) // Recover ft10
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flw f31,62*REGBYTES(sp) // Recover ft11
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LOAD t0, 63*REGBYTES(sp) // Recover fcsr
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csrw fcsr, t0 //
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#elif defined(__riscv_float_abi_double)
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fld f0, 31*REGBYTES(sp) // Recover ft0
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fld f1, 32*REGBYTES(sp) // Recover ft1
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fld f2, 33*REGBYTES(sp) // Recover ft2
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fld f3, 34*REGBYTES(sp) // Recover ft3
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fld f4, 35*REGBYTES(sp) // Recover ft4
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fld f5, 36*REGBYTES(sp) // Recover ft5
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fld f6, 37*REGBYTES(sp) // Recover ft6
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fld f7, 38*REGBYTES(sp) // Recover ft7
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fld f8, 39*REGBYTES(sp) // Recover fs0
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fld f9, 40*REGBYTES(sp) // Recover fs1
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fld f10,41*REGBYTES(sp) // Recover fa0
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fld f11,42*REGBYTES(sp) // Recover fa1
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fld f12,43*REGBYTES(sp) // Recover fa2
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fld f13,44*REGBYTES(sp) // Recover fa3
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fld f14,45*REGBYTES(sp) // Recover fa4
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fld f15,46*REGBYTES(sp) // Recover fa5
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fld f16,47*REGBYTES(sp) // Recover fa6
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fld f17,48*REGBYTES(sp) // Recover fa7
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fld f18,49*REGBYTES(sp) // Recover fs2
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fld f19,50*REGBYTES(sp) // Recover fs3
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fld f20,51*REGBYTES(sp) // Recover fs4
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fld f21,52*REGBYTES(sp) // Recover fs5
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fld f22,53*REGBYTES(sp) // Recover fs6
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fld f23,54*REGBYTES(sp) // Recover fs7
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fld f24,55*REGBYTES(sp) // Recover fs8
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fld f25,56*REGBYTES(sp) // Recover fs9
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fld f26,57*REGBYTES(sp) // Recover fs10
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fld f27,58*REGBYTES(sp) // Recover fs11
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fld f28,59*REGBYTES(sp) // Recover ft8
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fld f29,60*REGBYTES(sp) // Recover ft9
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fld f30,61*REGBYTES(sp) // Recover ft10
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fld f31,62*REGBYTES(sp) // Recover ft11
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LOAD t0, 63*REGBYTES(sp) // Recover fcsr
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#endif
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/* Recover standard registers. */
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LOAD t0, 30*REGBYTES(sp) // Recover mepc
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csrw mepc, t0 // Store mepc
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li t0, 0x1880 // Prepare MPIP
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csrw mstatus, t0 // Enable MPIP
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LOAD x1, 28*REGBYTES(sp) // Recover RA
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LOAD x5, 19*REGBYTES(sp) // Recover t0
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LOAD x6, 18*REGBYTES(sp) // Recover t1
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LOAD x7, 17*REGBYTES(sp) // Recover t2
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LOAD x8, 12*REGBYTES(sp) // Recover s0
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LOAD x9, 11*REGBYTES(sp) // Recover s1
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LOAD x10, 27*REGBYTES(sp) // Recover a0
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LOAD x11, 26*REGBYTES(sp) // Recover a1
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LOAD x12, 25*REGBYTES(sp) // Recover a2
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LOAD x13, 24*REGBYTES(sp) // Recover a3
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LOAD x14, 23*REGBYTES(sp) // Recover a4
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LOAD x15, 22*REGBYTES(sp) // Recover a5
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LOAD x16, 21*REGBYTES(sp) // Recover a6
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LOAD x17, 20*REGBYTES(sp) // Recover a7
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LOAD x18, 10*REGBYTES(sp) // Recover s2
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LOAD x19, 9*REGBYTES(sp) // Recover s3
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LOAD x20, 8*REGBYTES(sp) // Recover s4
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LOAD x21, 7*REGBYTES(sp) // Recover s5
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LOAD x22, 6*REGBYTES(sp) // Recover s6
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LOAD x23, 5*REGBYTES(sp) // Recover s7
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LOAD x24, 4*REGBYTES(sp) // Recover s8
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LOAD x25, 3*REGBYTES(sp) // Recover s9
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LOAD x26, 2*REGBYTES(sp) // Recover s10
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LOAD x27, 1*REGBYTES(sp) // Recover s11
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LOAD x28, 16*REGBYTES(sp) // Recover t3
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LOAD x29, 15*REGBYTES(sp) // Recover t4
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LOAD x30, 14*REGBYTES(sp) // Recover t5
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LOAD x31, 13*REGBYTES(sp) // Recover t6
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#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
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addi sp, sp, 65*REGBYTES // Recover stack frame - with floating point registers
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#else
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addi sp, sp, 32*REGBYTES // Recover stack frame - without floating point registers
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#endif
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mret // Return to point of interrupt
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_tx_thread_synch_return:
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#if defined(__riscv_float_abi_single)
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flw f8, 15*REGBYTES(sp) // Recover fs0
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flw f9, 16*REGBYTES(sp) // Recover fs1
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flw f18,17*REGBYTES(sp) // Recover fs2
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flw f19,18*REGBYTES(sp) // Recover fs3
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flw f20,19*REGBYTES(sp) // Recover fs4
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flw f21,20*REGBYTES(sp) // Recover fs5
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flw f22,21*REGBYTES(sp) // Recover fs6
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flw f23,22*REGBYTES(sp) // Recover fs7
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flw f24,23*REGBYTES(sp) // Recover fs8
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flw f25,24*REGBYTES(sp) // Recover fs9
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flw f26,25*REGBYTES(sp) // Recover fs10
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flw f27,26*REGBYTES(sp) // Recover fs11
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LOAD t0, 27*REGBYTES(sp) // Recover fcsr
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csrw fcsr, t0 //
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#elif defined(__riscv_float_abi_double)
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fld f8, 15*REGBYTES(sp) // Recover fs0
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fld f9, 16*REGBYTES(sp) // Recover fs1
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fld f18,17*REGBYTES(sp) // Recover fs2
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fld f19,18*REGBYTES(sp) // Recover fs3
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fld f20,19*REGBYTES(sp) // Recover fs4
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fld f21,20*REGBYTES(sp) // Recover fs5
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fld f22,21*REGBYTES(sp) // Recover fs6
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fld f23,22*REGBYTES(sp) // Recover fs7
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fld f24,23*REGBYTES(sp) // Recover fs8
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fld f25,24*REGBYTES(sp) // Recover fs9
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fld f26,25*REGBYTES(sp) // Recover fs10
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fld f27,26*REGBYTES(sp) // Recover fs11
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LOAD t0, 27*REGBYTES(sp) // Recover fcsr
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csrw fcsr, t0 //
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#endif
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/* Recover standard preserved registers. */
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/* Recover standard registers. */
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LOAD x1, 13*REGBYTES(sp) // Recover RA
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LOAD x8, 12*REGBYTES(sp) // Recover s0
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LOAD x9, 11*REGBYTES(sp) // Recover s1
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LOAD x18, 10*REGBYTES(sp) // Recover s2
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LOAD x19, 9*REGBYTES(sp) // Recover s3
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LOAD x20, 8*REGBYTES(sp) // Recover s4
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LOAD x21, 7*REGBYTES(sp) // Recover s5
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LOAD x22, 6*REGBYTES(sp) // Recover s6
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LOAD x23, 5*REGBYTES(sp) // Recover s7
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LOAD x24, 4*REGBYTES(sp) // Recover s8
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LOAD x25, 3*REGBYTES(sp) // Recover s9
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LOAD x26, 2*REGBYTES(sp) // Recover s10
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LOAD x27, 1*REGBYTES(sp) // Recover s11
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LOAD t0, 14*REGBYTES(sp) // Recover mstatus
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csrw mstatus, t0 // Store mstatus, enables interrupt
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#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
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addi sp, sp, 29*REGBYTES // Recover stack frame
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#else
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addi sp, sp, 16*REGBYTES // Recover stack frame
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#endif
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ret // Return to thread
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/* } */
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