mirror of
https://github.com/eclipse-threadx/threadx.git
synced 2025-11-16 04:24:48 +00:00
6.1 minor release
This commit is contained in:
Scott Larson
7
ports_module/cortex-a7/ac5/example_build/build_all.bat
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7
ports_module/cortex-a7/ac5/example_build/build_all.bat
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@@ -0,0 +1,7 @@
|
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|
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call build_threadx.bat
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call build_threadx_module_library.bat
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call build_threadx_module_sample.bat
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call ..\..\..\..\common_modules\utilities\module_to_c_array.exe sample_threadx_module.axf module_code.c
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powershell -Command "(gc module_code.c) -replace 'unsigned', '__align(4096) unsigned' | Out-File module_code.c"
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call build_threadx_module_manager_sample.bat
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290
ports_module/cortex-a7/ac5/example_build/build_threadx.bat
Normal file
290
ports_module/cortex-a7/ac5/example_build/build_threadx.bat
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@@ -0,0 +1,290 @@
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del tx.a
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork tx_initialize_low_level.s
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_stack_build.s
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_schedule.s
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_system_return.s
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_context_save.s
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_context_restore.s
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_control.s
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_timer_interrupt.s
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_fiq_context_restore.s
|
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_fiq_context_save.s
|
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_fiq_nesting_end.s
|
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_fiq_nesting_start.s
|
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_disable.s
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_interrupt_restore.s
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_irq_nesting_end.s
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_irq_nesting_start.s
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armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/tx_thread_vectored_context_save.s
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armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_allocate.c
|
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armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_cleanup.c
|
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armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_create.c
|
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armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_info_get.c
|
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armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_release.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_search.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_release.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set_notify.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_high_level.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_enter.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_setup.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_initialize.c
|
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armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_info_get.c
|
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armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_system_info_get.c
|
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armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_prioritize.c
|
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armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_priority_change.c
|
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armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_put.c
|
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armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_cleanup.c
|
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armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_flush.c
|
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armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_front_send.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_receive.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send_notify.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_ceiling_put.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put_notify.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_entry_exit_notify.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_identify.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_preemption_change.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_priority_change.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_relinquish.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_reset.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_resume.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_shell_entry.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_sleep.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_analyze.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_handler.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_notify.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_suspend.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_preempt_check.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_resume.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_suspend.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_terminate.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice_change.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_timeout.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_wait_abort.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_time_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_time_set.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_activate.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_change.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_deactivate.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_expiration_process.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_activate.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_deactivate.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_thread_entry.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_enable.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_disable.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_interrupt_control.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_enter_insert.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_exit_insert.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_register.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_unregister.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_user_event_insert.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_buffer_full_notify.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_filter.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_unfilter.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_release.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_release.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set_notify.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_put.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_flush.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_front_send.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_receive.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send_notify.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_ceiling_put.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put_notify.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_entry_exit_notify.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_preemption_change.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_priority_change.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_relinquish.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_reset.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_resume.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_suspend.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_terminate.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_time_slice_change.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_wait_abort.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_activate.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_change.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_deactivate.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_delete.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_alignment_adjust.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_application_request.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_callback_request.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_external_memory_enable.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_file_load.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_in_place_load.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_internal_load.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_mm_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_memory_fault_handler.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_memory_fault_notify.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_memory_load.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_deallocate.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_properties_get.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_manager/src/txm_module_manager_mm_register_setup.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_start.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_stop.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_create.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_reset.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_unload.c
|
||||
armcc -g -O0 --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_manager/src/txm_module_manager_util.c
|
||||
armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/txm_module_manager_thread_stack_build.s
|
||||
armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork ../module_manager/src/txm_module_manager_user_mode_entry.s
|
||||
|
||||
armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o
|
||||
armar -r tx.a tx_initialize_low_level.o tx_thread_fiq_context_restore.o tx_thread_fiq_context_save.o tx_thread_fiq_nesting_end.o tx_thread_fiq_nesting_start.o tx_thread_interrupt_disable.o
|
||||
armar -r tx.a tx_thread_interrupt_restore.o tx_thread_irq_nesting_end.o tx_thread_irq_nesting_start.o
|
||||
armar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o
|
||||
armar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o
|
||||
armar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o
|
||||
armar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o
|
||||
armar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o
|
||||
armar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o
|
||||
armar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o
|
||||
armar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o
|
||||
armar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o
|
||||
armar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o
|
||||
armar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o
|
||||
armar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o
|
||||
armar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o
|
||||
armar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o
|
||||
armar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o
|
||||
armar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o
|
||||
armar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o
|
||||
armar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o
|
||||
armar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o
|
||||
armar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
|
||||
armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o
|
||||
armar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o
|
||||
armar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o
|
||||
armar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o
|
||||
armar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o
|
||||
armar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o
|
||||
armar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o
|
||||
armar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o
|
||||
armar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o
|
||||
armar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o
|
||||
armar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o
|
||||
armar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o
|
||||
armar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o
|
||||
|
||||
armar -r tx.a txm_module_manager_alignment_adjust.o txm_module_manager_application_request.o txm_module_manager_callback_request.o
|
||||
armar -r tx.a txm_module_manager_event_flags_notify_trampoline.o txm_module_manager_external_memory_enable.o txm_module_manager_file_load.o
|
||||
armar -r tx.a txm_module_manager_in_place_load.o txm_module_manager_initialize.o txm_module_manager_mm_initialize.o
|
||||
armar -r tx.a txm_module_manager_kernel_dispatch.o txm_module_manager_maximum_module_priority_set.o txm_module_manager_memory_fault_handler.o
|
||||
armar -r tx.a txm_module_manager_memory_fault_notify.o txm_module_manager_memory_load.o txm_module_manager_object_pointer_get.o
|
||||
armar -r tx.a txm_module_manager_object_pool_create.o txm_module_manager_queue_notify_trampoline.o txm_module_manager_semaphore_notify_trampoline.o
|
||||
armar -r tx.a txm_module_manager_mm_register_setup.o txm_module_manager_start.o txm_module_manager_stop.o
|
||||
armar -r tx.a txm_module_manager_thread_create.o txm_module_manager_thread_notify_trampoline.o txm_module_manager_thread_reset.o
|
||||
armar -r tx.a txm_module_manager_timer_notify_trampoline.o txm_module_manager_unload.o txm_module_manager_thread_stack_build.o
|
||||
armar -r tx.a txm_module_manager_user_mode_entry.o
|
||||
armar -r tx.a txm_module_manager_internal_load.o
|
||||
armar -r tx.a txm_module_manager_object_allocate.o
|
||||
armar -r tx.a txm_module_manager_object_deallocate.o
|
||||
armar -r tx.a txm_module_manager_object_pointer_get_extended.o
|
||||
armar -r tx.a txm_module_manager_properties_get.o
|
||||
armar -r tx.a txm_module_manager_util.o
|
||||
@@ -0,0 +1,120 @@
|
||||
del txm.a
|
||||
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_allocate.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_create.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_delete.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_pool_prioritize.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_block_release.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_allocate.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_create.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_delete.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_pool_prioritize.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_byte_release.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_create.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_delete.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_set.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_event_flags_set_notify.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_application_request.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_callback_request_thread_entry.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_object_allocate.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_object_deallocate.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_object_pointer_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../module_lib/src/txm_module_thread_shell_entry.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_module_thread_system_suspend.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_create.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_delete.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_prioritize.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_mutex_put.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_create.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_delete.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_flush.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_front_send.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_performance_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_prioritize.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_receive.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_send.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_queue_send_notify.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_ceiling_put.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_create.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_delete.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_prioritize.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_put.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_semaphore_put_notify.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_create.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_delete.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_entry_exit_notify.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_identify.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_interrupt_control.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_performance_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_preemption_change.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_priority_change.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_relinquish.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_reset.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_resume.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_sleep.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_stack_error_notify.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_suspend.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_terminate.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_time_slice_change.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_thread_wait_abort.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_time_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_time_set.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_activate.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_change.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_create.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_deactivate.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_delete.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_performance_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_timer_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_buffer_full_notify.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_disable.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_enable.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_event_filter.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_event_unfilter.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_isr_enter_insert.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_isr_exit_insert.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc ../../../../common_modules/module_lib/src/txm_trace_user_event_insert.c
|
||||
|
||||
armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork/ropi/rwpi ../module_lib/src/txm_module_initialize.s
|
||||
|
||||
armar --create txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o
|
||||
armar -r txm.a txm_block_pool_prioritize.o txm_block_release.o
|
||||
armar -r txm.a txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o
|
||||
armar -r txm.a txm_byte_pool_prioritize.o txm_byte_release.o
|
||||
armar -r txm.a txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o
|
||||
armar -r txm.a txm_event_flags_set.o txm_event_flags_set_notify.o
|
||||
armar -r txm.a txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_initialize.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o
|
||||
armar -r txm.a txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o
|
||||
armar -r txm.a txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o
|
||||
armar -r txm.a txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o
|
||||
armar -r txm.a txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o
|
||||
armar -r txm.a txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o
|
||||
armar -r txm.a txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o
|
||||
armar -r txm.a txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o
|
||||
armar -r txm.a txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o
|
||||
armar -r txm.a txm_time_get.o txm_time_set.o
|
||||
armar -r txm.a txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o
|
||||
armar -r txm.a txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o
|
||||
@@ -0,0 +1,5 @@
|
||||
armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=interwork tx_initialize_low_level.s
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc sample_threadx_module_manager.c
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c module_code.c
|
||||
armlink -d -o sample_threadx_module_manager.axf --elf --ro 0x80000000 --first tx_initialize_low_level.o(VECTORS) --remove --map --symbols --list sample_threadx_module_manager.map tx_initialize_low_level.o sample_threadx_module_manager.o module_code.o tx.a
|
||||
|
||||
@@ -0,0 +1,4 @@
|
||||
armasm -g --cpu=cortex-a7.no_neon --fpu=softvfp --apcs=/interwork/ropi/rwpi txm_module_preamble.s
|
||||
armcc -g --cpu=cortex-a7.no_neon --fpu=softvfp -c --apcs=/interwork/ropi/rwpi --lower_ropi -I../inc -I../../../../common/inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc sample_threadx_module.c
|
||||
armlink -d -o sample_threadx_module.axf --elf --ro 0 --first txm_module_preamble.o(Init) --entry=_txm_module_thread_shell_entry --ropi --rwpi --remove --map --symbols --list sample_threadx_module.map txm_module_preamble.o sample_threadx_module.o txm.a
|
||||
|
||||
BIN
ports_module/cortex-a7/ac5/example_build/module_code.c
Normal file
BIN
ports_module/cortex-a7/ac5/example_build/module_code.c
Normal file
Binary file not shown.
427
ports_module/cortex-a7/ac5/example_build/sample_threadx_module.c
Normal file
427
ports_module/cortex-a7/ac5/example_build/sample_threadx_module.c
Normal file
@@ -0,0 +1,427 @@
|
||||
/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes
|
||||
examples of eight threads of different priorities, using a message queue, semaphore, mutex,
|
||||
event flags group, byte pool, and block pool. */
|
||||
|
||||
/* Specify that this is a module! */
|
||||
|
||||
#define TXM_MODULE
|
||||
|
||||
|
||||
/* Include the ThreadX module definitions. */
|
||||
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/* Define constants. */
|
||||
|
||||
#define DEMO_STACK_SIZE 1024
|
||||
#define DEMO_BYTE_POOL_SIZE 9120
|
||||
#define DEMO_BLOCK_POOL_SIZE 100
|
||||
#define DEMO_QUEUE_SIZE 100
|
||||
|
||||
|
||||
/* Define the pool space in the bss section of the module. ULONG is used to
|
||||
get the word alignment. */
|
||||
|
||||
ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4];
|
||||
|
||||
|
||||
/* Define the ThreadX object control blocks... */
|
||||
|
||||
TX_THREAD *thread_0;
|
||||
TX_THREAD *thread_1;
|
||||
TX_THREAD *thread_2;
|
||||
TX_THREAD *thread_3;
|
||||
TX_THREAD *thread_4;
|
||||
TX_THREAD *thread_5;
|
||||
TX_THREAD *thread_6;
|
||||
TX_THREAD *thread_7;
|
||||
TX_QUEUE *queue_0;
|
||||
TX_SEMAPHORE *semaphore_0;
|
||||
TX_MUTEX *mutex_0;
|
||||
TX_EVENT_FLAGS_GROUP *event_flags_0;
|
||||
TX_BYTE_POOL *byte_pool_0;
|
||||
TX_BLOCK_POOL *block_pool_0;
|
||||
|
||||
|
||||
/* Define the counters used in the demo application... */
|
||||
|
||||
ULONG thread_0_counter;
|
||||
ULONG thread_1_counter;
|
||||
ULONG thread_1_messages_sent;
|
||||
ULONG thread_2_counter;
|
||||
ULONG thread_2_messages_received;
|
||||
ULONG thread_3_counter;
|
||||
ULONG thread_4_counter;
|
||||
ULONG thread_5_counter;
|
||||
ULONG thread_6_counter;
|
||||
ULONG thread_7_counter;
|
||||
ULONG semaphore_0_puts;
|
||||
ULONG event_0_sets;
|
||||
ULONG queue_0_sends;
|
||||
|
||||
/* Define thread prototypes. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input);
|
||||
void thread_1_entry(ULONG thread_input);
|
||||
void thread_2_entry(ULONG thread_input);
|
||||
void thread_3_and_4_entry(ULONG thread_input);
|
||||
void thread_5_entry(ULONG thread_input);
|
||||
void thread_6_and_7_entry(ULONG thread_input);
|
||||
|
||||
void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr)
|
||||
{
|
||||
|
||||
if (semaphore_ptr == semaphore_0)
|
||||
semaphore_0_puts++;
|
||||
}
|
||||
|
||||
|
||||
void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr)
|
||||
{
|
||||
|
||||
if (event_flag_group_ptr == event_flags_0)
|
||||
event_0_sets++;
|
||||
}
|
||||
|
||||
|
||||
void queue_0_notify(TX_QUEUE *queue_ptr)
|
||||
{
|
||||
|
||||
if (queue_ptr == queue_0)
|
||||
queue_0_sends++;
|
||||
}
|
||||
|
||||
|
||||
/* Define the module start function. */
|
||||
|
||||
void demo_module_start(ULONG id)
|
||||
{
|
||||
|
||||
CHAR *pointer;
|
||||
|
||||
/* Allocate all the objects. In MMU mode, modules cannot allocate control blocks within
|
||||
their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting
|
||||
the control block(s). */
|
||||
txm_module_object_allocate((void *) &thread_0, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void *) &thread_1, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void *) &thread_2, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void *) &thread_3, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void *) &thread_4, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void *) &thread_5, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void *) &thread_6, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void *) &thread_7, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void *) &queue_0, sizeof(TX_QUEUE));
|
||||
txm_module_object_allocate((void *) &semaphore_0, sizeof(TX_SEMAPHORE));
|
||||
txm_module_object_allocate((void *) &mutex_0, sizeof(TX_MUTEX));
|
||||
txm_module_object_allocate((void *) &event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP));
|
||||
txm_module_object_allocate((void *) &byte_pool_0, sizeof(TX_BYTE_POOL));
|
||||
txm_module_object_allocate((void *) &block_pool_0, sizeof(TX_BLOCK_POOL));
|
||||
|
||||
/* Create a byte memory pool from which to allocate the thread stacks. */
|
||||
tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE);
|
||||
|
||||
/* Put system definition stuff in here, e.g. thread creates and other assorted
|
||||
create information. */
|
||||
|
||||
/* Allocate the stack for thread 0. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create the main thread. */
|
||||
tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
|
||||
/* Allocate the stack for thread 1. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 1 and 2. These threads pass information through a ThreadX
|
||||
message queue. It is also interesting to note that these threads have a time
|
||||
slice. */
|
||||
tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 2. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 3. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
|
||||
An interesting thing here is that both threads share the same instruction area. */
|
||||
tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 4. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 5. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create thread 5. This thread simply pends on an event flag which will be set
|
||||
by thread_0. */
|
||||
tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 6. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
|
||||
tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 7. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the message queue. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
|
||||
|
||||
/* Create the message queue shared by threads 1 and 2. */
|
||||
tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
|
||||
|
||||
tx_queue_send_notify(queue_0, queue_0_notify);
|
||||
|
||||
/* Create the semaphore used by threads 3 and 4. */
|
||||
tx_semaphore_create(semaphore_0, "module semaphore 0", 1);
|
||||
|
||||
tx_semaphore_put_notify(semaphore_0, semaphore_0_notify);
|
||||
|
||||
/* Create the event flags group used by threads 1 and 5. */
|
||||
tx_event_flags_create(event_flags_0, "module event flags 0");
|
||||
|
||||
tx_event_flags_set_notify(event_flags_0, event_0_notify);
|
||||
|
||||
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
|
||||
tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT);
|
||||
|
||||
/* Allocate the memory for a small block pool. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create a block memory pool to allocate a message buffer from. */
|
||||
tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
|
||||
|
||||
/* Allocate a block and release the block memory. */
|
||||
tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
|
||||
|
||||
/* Release the block back to the pool. */
|
||||
tx_block_release(pointer);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Define the test threads. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
/* Test external/shared memory. */
|
||||
*(ULONG *) 0x90000000 = 0xdeadbeef;
|
||||
*(ULONG *) 0x90000FFC = 0xfeed0add;
|
||||
*(ULONG *) 0x90001000 = 0xfedcba01;
|
||||
|
||||
/* This thread simply sits in while-forever-sleep loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_0_counter++;
|
||||
|
||||
/* Sleep for 10 ticks. */
|
||||
tx_thread_sleep(10);
|
||||
|
||||
/* Set event flag 0 to wakeup thread 5. */
|
||||
status = tx_event_flags_set(event_flags_0, 0x1, TX_OR);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_1_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This thread simply sends messages to a queue shared by thread 2. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_1_counter++;
|
||||
|
||||
/* Send message to queue 0. */
|
||||
status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Increment the message sent. */
|
||||
thread_1_messages_sent++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_2_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
ULONG received_message;
|
||||
UINT status;
|
||||
|
||||
/* This thread retrieves messages placed on the queue by thread 1. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_2_counter++;
|
||||
|
||||
/* Retrieve a message from the queue. */
|
||||
status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status and make sure the message is what we
|
||||
expected. */
|
||||
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
|
||||
break;
|
||||
|
||||
/* Otherwise, all is okay. Increment the received message count. */
|
||||
thread_2_messages_received++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_3_and_4_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 3 and thread 4. As the loop
|
||||
below shows, these function compete for ownership of semaphore_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 3)
|
||||
thread_3_counter++;
|
||||
else
|
||||
thread_4_counter++;
|
||||
|
||||
/* Get the semaphore with suspension. */
|
||||
status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the semaphore. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the semaphore. */
|
||||
status = tx_semaphore_put(semaphore_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_5_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
ULONG actual_flags;
|
||||
|
||||
|
||||
/* This thread simply waits for an event in a forever loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_5_counter++;
|
||||
|
||||
/* Wait for event flag 0. */
|
||||
status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR,
|
||||
&actual_flags, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_6_and_7_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 6 and thread 7. As the loop
|
||||
below shows, these function compete for ownership of mutex_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 6)
|
||||
thread_6_counter++;
|
||||
else
|
||||
thread_7_counter++;
|
||||
|
||||
/* Get the mutex with suspension. */
|
||||
status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Get the mutex again with suspension. This shows
|
||||
that an owning thread may retrieve the mutex it
|
||||
owns multiple times. */
|
||||
status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the mutex. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the mutex. */
|
||||
status = tx_mutex_put(mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Release the mutex again. This will actually
|
||||
release ownership since it was obtained twice. */
|
||||
status = tx_mutex_put(mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,132 @@
|
||||
/* Small demonstration of the ThreadX module manager. This demonstration assumes the program
|
||||
manager is loaded at 0 and that RAM addresses 0x200000 through 0x400000 are available for
|
||||
use. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
#define DEMO_STACK_SIZE 1024
|
||||
|
||||
|
||||
/* Define the ThreadX object control blocks... */
|
||||
|
||||
TX_THREAD module_manager;
|
||||
|
||||
/* Define thread prototypes. */
|
||||
|
||||
void module_manager_entry(ULONG thread_input);
|
||||
|
||||
/* Define the module object pool area. */
|
||||
UCHAR object_memory[16384];
|
||||
|
||||
/* Define the module data pool area. */
|
||||
#define MODULE_DATA_SIZE 65536
|
||||
unsigned char module_data_area[MODULE_DATA_SIZE];
|
||||
|
||||
/* Define a module instance. */
|
||||
TXM_MODULE_INSTANCE my_module1;
|
||||
TXM_MODULE_INSTANCE my_module2;
|
||||
|
||||
/* Module code is in an array created by module_to_c_array utility. */
|
||||
extern unsigned char module_code[];
|
||||
|
||||
/* Define the count of memory faults. */
|
||||
ULONG memory_faults;
|
||||
|
||||
/* Define fault handler. */
|
||||
VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module)
|
||||
{
|
||||
/* Just increment the fault counter. */
|
||||
memory_faults++;
|
||||
}
|
||||
|
||||
/* Define main entry point. */
|
||||
|
||||
int main()
|
||||
{
|
||||
|
||||
/* Enter the ThreadX kernel. */
|
||||
tx_kernel_enter();
|
||||
}
|
||||
|
||||
|
||||
/* Define what the initial system looks like. */
|
||||
|
||||
void tx_application_define(void *first_unused_memory)
|
||||
{
|
||||
|
||||
/* Create the module manager thread. */
|
||||
tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0,
|
||||
first_unused_memory, DEMO_STACK_SIZE,
|
||||
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Define the test threads. */
|
||||
|
||||
void module_manager_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
/* Initialize the module manager. */
|
||||
txm_module_manager_initialize((VOID *) module_data_area, MODULE_DATA_SIZE);
|
||||
|
||||
/* Create a pool for module objects. */
|
||||
txm_module_manager_object_pool_create(object_memory, sizeof(object_memory));
|
||||
|
||||
/* Register a fault handler. */
|
||||
txm_module_manager_memory_fault_notify(module_fault_handler);
|
||||
|
||||
/* Initialize MMU. */
|
||||
txm_module_manager_mm_initialize();
|
||||
|
||||
/* Load the module that is already there, in this example it is placed there by the multiple image download. */
|
||||
txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) module_code);
|
||||
|
||||
/* Load a second instance of the module. */
|
||||
//txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code);
|
||||
|
||||
/* Enable shared memory regions for one module. */
|
||||
//txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F);
|
||||
|
||||
/* Start the modules. */
|
||||
txm_module_manager_start(&my_module1);
|
||||
//txm_module_manager_start(&my_module2);
|
||||
|
||||
/* Sleep for a while and let the modules run.... */
|
||||
tx_thread_sleep(50);
|
||||
|
||||
/* Thread 0 in module1 should be terminated due to violating the MMU. */
|
||||
|
||||
/* Stop the modules. */
|
||||
txm_module_manager_stop(&my_module1);
|
||||
txm_module_manager_stop(&my_module2);
|
||||
|
||||
/* Unload the modules. */
|
||||
txm_module_manager_unload(&my_module1);
|
||||
txm_module_manager_unload(&my_module2);
|
||||
|
||||
/* Reload the modules. */
|
||||
txm_module_manager_in_place_load(&my_module2, "my module2", (VOID *) module_code);
|
||||
txm_module_manager_in_place_load(&my_module1, "my module1", (VOID *) module_code);
|
||||
|
||||
/* Give both modules shared memory. */
|
||||
txm_module_manager_external_memory_enable(&my_module2, (void*)0x90000000, 0x010000, 0x3F);
|
||||
txm_module_manager_external_memory_enable(&my_module1, (void*)0x90000000, 0x010000, 0x3F);
|
||||
|
||||
/* Start the module again. */
|
||||
txm_module_manager_start(&my_module2);
|
||||
txm_module_manager_start(&my_module1);
|
||||
|
||||
/* Now just spin... */
|
||||
while(1)
|
||||
{
|
||||
tx_thread_sleep(100);
|
||||
/* Thread 0 and 5 in module1 should not exist because they violate the maximum priority. */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
41
ports_module/cortex-a7/ac5/example_build/scatter.scat
Normal file
41
ports_module/cortex-a7/ac5/example_build/scatter.scat
Normal file
@@ -0,0 +1,41 @@
|
||||
;**************************************************
|
||||
; Copyright (c) 2011 ARM Ltd. All rights reserved.
|
||||
;**************************************************
|
||||
|
||||
; This scatter-file places application code, data, stack and heap at base address 0x80000000.
|
||||
; Using a scatter-file with ARM_LIB_STACKHEAP eliminates the need to set stack-limit or heap-base in the debugger.
|
||||
|
||||
|
||||
SDRAM 0x80000000
|
||||
{
|
||||
VECTORS +0
|
||||
{
|
||||
* (VECTORS, +FIRST) ; Vector table and other (assembler) startup code
|
||||
* (InRoot$$Sections) ; All (library) code that must be in a root region
|
||||
}
|
||||
|
||||
RO_CODE +0
|
||||
{ * (+RO-CODE) } ; Application RO code (.text)
|
||||
|
||||
RO_DATA +0
|
||||
{ * (+RO-DATA) } ; Application RO data (.constdata)
|
||||
|
||||
RW_DATA +0
|
||||
{ * (+RW) } ; Application RW data (.data)
|
||||
|
||||
ZI_DATA +0
|
||||
{ * (+ZI) } ; Application ZI data (.bss)
|
||||
|
||||
ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap
|
||||
{ }
|
||||
|
||||
ARM_LIB_STACK 0x80090000 EMPTY -0x00010000 ; Application (SVC mode) stack
|
||||
{ }
|
||||
|
||||
IRQ_STACK 0x800A0000 EMPTY -0x00010000 ; IRQ mode stack
|
||||
{ }
|
||||
|
||||
TTB 0x80100000 EMPTY 0x4000 ; Level-1 Translation Table for MMU
|
||||
{ }
|
||||
|
||||
}
|
||||
@@ -0,0 +1,659 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Initialize */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_initialize.h"
|
||||
;#include "tx_thread.h"
|
||||
;#include "tx_timer.h"
|
||||
;
|
||||
;
|
||||
|
||||
THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR
|
||||
FIQ_MODE EQU 0x11 ; FIQ mode
|
||||
IRQ_MODE EQU 0x12 ; IRQ mode
|
||||
SVC_MODE EQU 0x13 ; SVC mode
|
||||
ABT_MODE EQU 0x17 ; ABT mode
|
||||
SYS_MODE EQU 0x1F ; SYS mode
|
||||
|
||||
HEAP_SIZE EQU 4096 ; Heap size
|
||||
FIQ_STACK_SIZE EQU 512 ; FIQ stack size
|
||||
SYS_STACK_SIZE EQU 1024 ; SYS stack size
|
||||
IRQ_STACK_SIZE EQU 1024 ; IRQ stack size
|
||||
SVC_STACK_SIZE EQU 512 ; SVC stack size
|
||||
ABT_STACK_SIZE EQU 512 ; ABT stack size
|
||||
|
||||
VFPEnable EQU 0x40000000 ; VFP enable value
|
||||
|
||||
;
|
||||
;
|
||||
IMPORT __tx_swi_interrupt
|
||||
IMPORT _tx_thread_system_stack_ptr
|
||||
IMPORT _tx_initialize_unused_memory
|
||||
IMPORT _tx_thread_context_save
|
||||
IMPORT _tx_thread_context_restore
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
IMPORT _tx_thread_fiq_context_save
|
||||
IMPORT _tx_thread_fiq_context_restore
|
||||
ENDIF
|
||||
IF :DEF:TX_ENABLE_IRQ_NESTING
|
||||
IMPORT _tx_thread_irq_nesting_start
|
||||
IMPORT _tx_thread_irq_nesting_end
|
||||
ENDIF
|
||||
IF :DEF:TX_ENABLE_FIQ_NESTING
|
||||
IMPORT _tx_thread_fiq_nesting_start
|
||||
IMPORT _tx_thread_fiq_nesting_end
|
||||
ENDIF
|
||||
IMPORT _tx_timer_interrupt
|
||||
IMPORT __main
|
||||
IMPORT _tx_version_id
|
||||
IMPORT _tx_build_options
|
||||
IMPORT |Image$$ZI$$Limit|
|
||||
;
|
||||
;
|
||||
AREA VECTORS, CODE, READONLY
|
||||
PRESERVE8
|
||||
;
|
||||
;/* Define the default Cortex-A7 vector area. This should be located or copied to 0. */
|
||||
;
|
||||
EXPORT __vectors
|
||||
__vectors
|
||||
LDR pc,=Reset_Vector ; Reset goes to startup function
|
||||
LDR pc,=__tx_undefined ; Undefined handler
|
||||
LDR pc,=__tx_swi_interrupt ; Software interrupt handler
|
||||
LDR pc,=__tx_prefetch_handler ; Prefetch exception handler
|
||||
LDR pc,=__tx_abort_handler ; Abort exception handler
|
||||
LDR pc,=__tx_reserved_handler ; Reserved exception handler
|
||||
LDR pc,=__tx_irq_handler ; IRQ interrupt handler
|
||||
LDR pc,=__tx_fiq_handler ; FIQ interrupt handler
|
||||
;
|
||||
;
|
||||
EXPORT Reset_Vector
|
||||
Reset_Vector
|
||||
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
MRC p15, 0, r1, c1, c0, 2 ; r1 = Access Control Register
|
||||
ORR r1, r1, #(0xf << 20) ; Enable full access for p10,11
|
||||
MCR p15, 0, r1, c1, c0, 2 ; Access Control Register = r1
|
||||
MOV r1, #0
|
||||
MCR p15, 0, r1, c7, c5, 4 ; Flush prefetch buffer because of FMXR below and
|
||||
; CP 10 & 11 were only just enabled
|
||||
MOV r0, #VFPEnable ; Enable VFP itself
|
||||
FMXR FPEXC, r0 ; FPEXC = r0
|
||||
ENDIF
|
||||
|
||||
B __main
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_initialize_low_level Cortex-A7/MMU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for any low-level processor */
|
||||
;/* initialization, including setting up interrupt vectors, setting */
|
||||
;/* up a periodic timer interrupt source, saving the system stack */
|
||||
;/* pointer for use in ISR processing later, and finding the first */
|
||||
;/* available RAM memory address for tx_application_define. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_initialize_low_level(VOID)
|
||||
;{
|
||||
EXPORT _tx_initialize_low_level
|
||||
_tx_initialize_low_level
|
||||
;
|
||||
;
|
||||
; /****** NOTE ****** We must be in SVC MODE at this point. Some monitors
|
||||
; enter this routine in USER mode and require a software interrupt to
|
||||
; change into SVC mode. */
|
||||
;
|
||||
|
||||
; Set vector table.
|
||||
LDR r0, = __vectors
|
||||
MCR p15, 0, r0, c12, c0, 0
|
||||
|
||||
|
||||
LDR r1, =|Image$$ZI$$Limit| ; Get end of non-initialized RAM area
|
||||
LDR r2, =HEAP_SIZE ; Pickup the heap size
|
||||
ADD r1, r2, r1 ; Setup heap limit
|
||||
ADD r1, r1, #4 ; Setup stack limit
|
||||
MOV r3, lr ; Save LR
|
||||
|
||||
LDR r2, =SYS_STACK_SIZE ; Pickup stack size
|
||||
CPS #SYS_MODE ; Enter SYS mode
|
||||
ADD r1, r1, r2 ; Calculate start of SYS stack
|
||||
BIC r1, r1, #7 ; Ensure 8-byte alignment
|
||||
MOV sp, r1 ; Setup SYS stack pointer
|
||||
MOV lr, r3 ; Restore LR
|
||||
|
||||
LDR r2, =SVC_STACK_SIZE ; Pickup SVC stack size
|
||||
CPS #SVC_MODE ; Enter SVC mode
|
||||
ADD r1, r1, r2 ; Calculate start of SVC stack
|
||||
BIC r1, r1, #7 ; Ensure 8-byte alignment
|
||||
MOV sp, r1 ; Setup SVC stack pointer
|
||||
|
||||
LDR r2, =IRQ_STACK_SIZE ; Pickup IRQ stack size
|
||||
CPS #IRQ_MODE ; Enter IRQ mode
|
||||
ADD r1, r1, r2 ; Calculate start of IRQ stack
|
||||
BIC r1, r1, #7 ; Ensure 8-byte alignment
|
||||
MOV sp, r1 ; Setup IRQ stack pointer
|
||||
|
||||
LDR r2, =FIQ_STACK_SIZE ; Pickup FIQ stack size
|
||||
CPS #FIQ_MODE ; Enter FIQ mode
|
||||
ADD r1, r1, r2 ; Calculate start of FIQ stack
|
||||
BIC r1, r1, #7 ; Ensure 8-byte alignment
|
||||
MOV sp, r1 ; Setup FIQ stack pointer
|
||||
MOV sl, #0 ; Clear sl
|
||||
MOV fp, #0 ; Clear fp
|
||||
|
||||
LDR r2, =ABT_STACK_SIZE ; Pickup ABT stack size
|
||||
CPS #ABT_MODE ; Enter ABT mode
|
||||
ADD r1, r1, r2 ; Calculate start of ABT stack
|
||||
BIC r1, r1, #7 ; Ensure 8-byte alignment
|
||||
MOV sp, r1 ; Setup ABT stack pointer
|
||||
|
||||
CPS #SYS_MODE ; Enter SYS mode
|
||||
;
|
||||
; /* Save the first available memory address. */
|
||||
; _tx_initialize_unused_memory = (VOID_PTR) |Image$$ZI$$Limit| + HEAP + SYS_STACK + SVC_STACK + IRQ_STACK + FIQ_STACK + ABT_STACK;
|
||||
;
|
||||
ADD r0, r1, #4 ; Increment to next free word
|
||||
LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address
|
||||
STR r0, [r2, #0] ; Save first free memory address
|
||||
;
|
||||
; /* Setup Timer for periodic interrupts. */
|
||||
;
|
||||
|
||||
GIC1_CPU_INTERFACE_BASE EQU 0x2C002000
|
||||
GIC1_DIST_INTERFACE_BASE EQU 0x2C001000
|
||||
|
||||
PUSH {r4-r12, lr}
|
||||
ldr r2, =GIC1_CPU_INTERFACE_BASE
|
||||
ldr r7, =GIC1_DIST_INTERFACE_BASE
|
||||
; Enable GIC
|
||||
mov r3, #0x1
|
||||
str r3, [r2, #0x0000]
|
||||
; Enable GIC forwarding
|
||||
str r3, [r7, #0x000]
|
||||
; Set Binary Point Register to 0
|
||||
eor r3, r3, r3
|
||||
str r3, [r2, #0x0008]
|
||||
|
||||
; At this point GIC is enabled
|
||||
; All INTS are disabled / not configured
|
||||
|
||||
; r0 - interrupt number
|
||||
; r1 - priority
|
||||
; r2 - interrupt type (edge / level trig.)
|
||||
ldr r0, =34
|
||||
ldr r1, =0xF0
|
||||
ldr r2, =1
|
||||
|
||||
ldr r7, =GIC1_DIST_INTERFACE_BASE
|
||||
|
||||
; enable the interrupt in isenable register
|
||||
mov r4, #0x100 ; ISEN REG offset base
|
||||
mov r5, r0, LSR #5 ; Interrupt_Number DIV 5
|
||||
add r4, r4, r5, LSL #2 ; final offset from GIC DIST BASE
|
||||
and r5, r0, #31 ; bit number
|
||||
mov r8, #1
|
||||
|
||||
|
||||
ldr r6, [r7, r4]
|
||||
orr r6, r6, r8, LSL r5
|
||||
str r6, [r7, r4]
|
||||
|
||||
; setup priority
|
||||
mov r4, #0x400
|
||||
mov r5, r0, LSR #2 ; Interrupt_Number DIV 4
|
||||
add r4, r4, r5, LSL #2 ; final offset from GIC DIST BASE
|
||||
and r5, r0, #3 ; Int_Num MOD 4
|
||||
lsl r5, #3
|
||||
lsl r1, r5
|
||||
|
||||
ldr r6, [r7, r4]
|
||||
orr r1, r6, r1
|
||||
str r1, [r7, r4]
|
||||
|
||||
; set up processor target
|
||||
mov r4, #0x800
|
||||
mov r5, r0, LSR #2 ; Interrupt_Number DIV 4
|
||||
add r4, r4, r5, LSL #2 ; final offset from GIC DIST BASE
|
||||
and r5, r0, #3 ; Int_Num MOD 4
|
||||
lsl r5, #3
|
||||
mov r1, #0xff
|
||||
lsl r1, r5
|
||||
|
||||
ldr r6, [r7, r4]
|
||||
orr r1, r6, r1
|
||||
str r1, [r7, r4]
|
||||
|
||||
; set up interrupt type
|
||||
mov r4, #0xC00
|
||||
mov r5, r0, LSR #4
|
||||
add r4, r4, r5, LSL #2 ; offset from base
|
||||
|
||||
; field
|
||||
and r5, r0, #15
|
||||
lsl r5, #1
|
||||
lsl r2, r5
|
||||
|
||||
ldr r6, [r7, r4]
|
||||
orr r2, r6, r2
|
||||
str r2, [r7, r4]
|
||||
|
||||
ldr r2, =GIC1_CPU_INTERFACE_BASE
|
||||
|
||||
; set the interrupt id prio mask
|
||||
; Max Priorities = 32.
|
||||
; mask = (32 - 1) << 3
|
||||
mov r3, #0xF8
|
||||
str r3, [r2, #0x0004]
|
||||
|
||||
CPSIE if
|
||||
|
||||
; Timer base
|
||||
ldr r0, =0x1C110000
|
||||
|
||||
; get the timer id
|
||||
ldr r1, [r0, #0xfe0]
|
||||
|
||||
; set count value in load register
|
||||
ldr r1, =0x00000020
|
||||
str r1, [r0, #00]
|
||||
|
||||
; enable the timer
|
||||
; periodic mode
|
||||
mov r1, #0xe2
|
||||
str r1, [r0, #08]
|
||||
|
||||
POP {r4-r12, lr}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
;
|
||||
; /* Done, return to caller. */
|
||||
;
|
||||
BX lr ; Return to caller
|
||||
;}
|
||||
;
|
||||
;
|
||||
;/* Define initial heap/stack routine for the ARM RealView (and ADS) startup code. This
|
||||
; routine will set the initial stack to use the ThreadX IRQ & FIQ &
|
||||
; (optionally SYS) stack areas. */
|
||||
;
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
LDR r0, =|Image$$ZI$$Limit| ; Get end of non-initialized RAM area
|
||||
LDR r2, =HEAP_SIZE ; Pickup the heap size
|
||||
ADD r2, r2, r0 ; Setup heap limit
|
||||
ADD r3, r2, #4 ; Setup stack limit
|
||||
MOV r1, r3 ; Setup start of stack
|
||||
IF :DEF:TX_ENABLE_IRQ_NESTING
|
||||
LDR r12, =SYS_STACK_SIZE ; Pickup IRQ system stack
|
||||
ADD r1, r1, r12 ; Setup the return system stack
|
||||
BIC r1, r1, #7 ; Ensure 8-byte alignment
|
||||
ENDIF
|
||||
LDR r12, =FIQ_STACK_SIZE ; Pickup FIQ stack size
|
||||
ADD r1, r1, r12 ; Setup the return system stack
|
||||
BIC r1, r1, #7 ; Ensure 8-byte alignment
|
||||
LDR r12, =IRQ_STACK_SIZE ; Pickup IRQ system stack
|
||||
ADD r1, r1, r12 ; Setup the return system stack
|
||||
BIC r1, r1, #7 ; Ensure 8-byte alignment
|
||||
IF {INTER} = {TRUE}
|
||||
BX lr ; Return to caller
|
||||
ELSE
|
||||
MOV pc, lr ; Return to caller
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
;/* Define shells for each of the interrupt vectors. */
|
||||
;
|
||||
EXPORT __tx_undefined
|
||||
__tx_undefined
|
||||
B __tx_undefined ; Undefined handler
|
||||
;
|
||||
EXPORT __tx_reserved_handler
|
||||
__tx_reserved_handler
|
||||
B __tx_reserved_handler ; Reserved exception handler
|
||||
;
|
||||
;
|
||||
EXPORT __tx_irq_handler
|
||||
EXPORT __tx_irq_processing_return
|
||||
__tx_irq_handler
|
||||
;
|
||||
; /* Jump to context save to save system context. */
|
||||
B _tx_thread_context_save
|
||||
__tx_irq_processing_return
|
||||
;
|
||||
; /* At this point execution is still in the IRQ mode. The CPSR, point of
|
||||
; interrupt, and all C scratch registers are available for use. In
|
||||
; addition, IRQ interrupts may be re-enabled - with certain restrictions -
|
||||
; if nested IRQ interrupts are desired. Interrupts may be re-enabled over
|
||||
; small code sequences where lr is saved before enabling interrupts and
|
||||
; restored after interrupts are again disabled. */
|
||||
;
|
||||
;
|
||||
BL _tx_timer_interrupt ; Timer interrupt handler
|
||||
|
||||
; clear timer interrupt
|
||||
ldr r0, =0x1C110000
|
||||
eor r1, r1, r1
|
||||
str r1, [r0, #0x0C]
|
||||
|
||||
_tx_not_timer_interrupt
|
||||
;
|
||||
; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start
|
||||
; from IRQ mode with interrupts disabled. This routine switches to the
|
||||
; system mode and returns with IRQ interrupts enabled.
|
||||
;
|
||||
; NOTE: It is very important to ensure all IRQ interrupts are cleared
|
||||
; prior to enabling nested IRQ interrupts. */
|
||||
IF :DEF:TX_ENABLE_IRQ_NESTING
|
||||
BL _tx_thread_irq_nesting_start
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
; /* Application IRQ handlers can be called here! */
|
||||
;
|
||||
; /* If interrupt nesting was started earlier, the end of interrupt nesting
|
||||
; service must be called before returning to _tx_thread_context_restore.
|
||||
; This routine returns in processing in IRQ mode with interrupts disabled. */
|
||||
IF :DEF:TX_ENABLE_IRQ_NESTING
|
||||
BL _tx_thread_irq_nesting_end
|
||||
ENDIF
|
||||
;
|
||||
; /* Jump to context restore to restore system context. */
|
||||
B _tx_thread_context_restore
|
||||
;
|
||||
;
|
||||
; /* This is an example of a vectored IRQ handler. */
|
||||
;
|
||||
EXPORT __tx_example_vectored_irq_handler
|
||||
__tx_example_vectored_irq_handler
|
||||
;
|
||||
;
|
||||
; /* Save initial context and call context save to prepare for
|
||||
; vectored ISR execution. */
|
||||
;
|
||||
; STMDB sp!, {r0-r3} ; Save some scratch registers
|
||||
; MRS r0, SPSR ; Pickup saved SPSR
|
||||
; SUB lr, lr, #4 ; Adjust point of interrupt
|
||||
; STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers
|
||||
; BL _tx_thread_vectored_context_save ; Vectored context save
|
||||
;
|
||||
; /* At this point execution is still in the IRQ mode. The CPSR, point of
|
||||
; interrupt, and all C scratch registers are available for use. In
|
||||
; addition, IRQ interrupts may be re-enabled - with certain restrictions -
|
||||
; if nested IRQ interrupts are desired. Interrupts may be re-enabled over
|
||||
; small code sequences where lr is saved before enabling interrupts and
|
||||
; restored after interrupts are again disabled. */
|
||||
;
|
||||
;
|
||||
; /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start
|
||||
; from IRQ mode with interrupts disabled. This routine switches to the
|
||||
; system mode and returns with IRQ interrupts enabled.
|
||||
;
|
||||
; NOTE: It is very important to ensure all IRQ interrupts are cleared
|
||||
; prior to enabling nested IRQ interrupts. */
|
||||
; IF :DEF:TX_ENABLE_IRQ_NESTING
|
||||
; BL _tx_thread_irq_nesting_start
|
||||
; ENDIF
|
||||
;
|
||||
; /* Application IRQ handlers can be called here! */
|
||||
;
|
||||
; /* If interrupt nesting was started earlier, the end of interrupt nesting
|
||||
; service must be called before returning to _tx_thread_context_restore.
|
||||
; This routine returns in processing in IRQ mode with interrupts disabled. */
|
||||
; IF :DEF:TX_ENABLE_IRQ_NESTING
|
||||
; BL _tx_thread_irq_nesting_end
|
||||
; ENDIF
|
||||
;
|
||||
; /* Jump to context restore to restore system context. */
|
||||
; B _tx_thread_context_restore
|
||||
;
|
||||
;
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
EXPORT __tx_fiq_handler
|
||||
EXPORT __tx_fiq_processing_return
|
||||
__tx_fiq_handler
|
||||
;
|
||||
; /* Jump to fiq context save to save system context. */
|
||||
B _tx_thread_fiq_context_save
|
||||
__tx_fiq_processing_return
|
||||
;
|
||||
; /* At this point execution is still in the FIQ mode. The CPSR, point of
|
||||
; interrupt, and all C scratch registers are available for use. */
|
||||
;
|
||||
; /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start
|
||||
; from FIQ mode with interrupts disabled. This routine switches to the
|
||||
; system mode and returns with FIQ interrupts enabled.
|
||||
;
|
||||
; NOTE: It is very important to ensure all FIQ interrupts are cleared
|
||||
; prior to enabling nested FIQ interrupts. */
|
||||
IF :DEF:TX_ENABLE_FIQ_NESTING
|
||||
BL _tx_thread_fiq_nesting_start
|
||||
ENDIF
|
||||
;
|
||||
; /* Application FIQ handlers can be called here! */
|
||||
;
|
||||
; /* If interrupt nesting was started earlier, the end of interrupt nesting
|
||||
; service must be called before returning to _tx_thread_fiq_context_restore. */
|
||||
IF :DEF:TX_ENABLE_FIQ_NESTING
|
||||
BL _tx_thread_fiq_nesting_end
|
||||
ENDIF
|
||||
;
|
||||
; /* Jump to fiq context restore to restore system context. */
|
||||
B _tx_thread_fiq_context_restore
|
||||
;
|
||||
;
|
||||
ELSE
|
||||
EXPORT __tx_fiq_handler
|
||||
__tx_fiq_handler
|
||||
B __tx_fiq_handler ; FIQ interrupt handler
|
||||
ENDIF
|
||||
|
||||
|
||||
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* __tx_prefetch_handler & __tx_abort_handler Cortex-A7/MMU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function handles MMU exceptions and fills the */
|
||||
;/* _txm_module_manager_memory_fault_info struct. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _txm_module_manager_memory_fault_handler */
|
||||
;/* _tx_execution_thread_exit */
|
||||
;/* _tx_thread_schedule */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* MMU exceptions */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
|
||||
; *******************************************************************
|
||||
; MMU Exception Handling
|
||||
; *******************************************************************
|
||||
EXTERN _tx_thread_system_state
|
||||
EXTERN _txm_module_manager_memory_fault_info
|
||||
EXTERN _tx_thread_current_ptr
|
||||
EXTERN _txm_module_manager_memory_fault_handler
|
||||
EXTERN _tx_execution_thread_exit
|
||||
EXTERN _tx_thread_schedule
|
||||
|
||||
EXPORT __tx_prefetch_handler
|
||||
EXPORT __tx_abort_handler
|
||||
__tx_prefetch_handler
|
||||
__tx_abort_handler
|
||||
STMDB sp!, {r0-r3} ; Save some working registers
|
||||
LDR r3, =_tx_thread_system_state ; Pickup address of system state var
|
||||
LDR r2, [r3, #0] ; Pickup system state
|
||||
ADD r2, r2, #1 ; Increment the interrupt counter
|
||||
STR r2, [r3, #0] ; Store it back in the variable
|
||||
SUB lr, lr, #4 ; Adjust point of exception
|
||||
;
|
||||
; /* Now pickup and store all the fault related information. */
|
||||
;
|
||||
; Pickup the memory fault info struct
|
||||
LDR r3, =_txm_module_manager_memory_fault_info
|
||||
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r1, [r0] ; Pickup the current thread pointer
|
||||
STR r1, [r3, #0] ; Save current thread pointer
|
||||
STR lr, [r3, #4] ; Save point of fault
|
||||
MRC p15, 0, r0, c6, c0, 0 ; Read DFAR
|
||||
STR r0, [r3, #8] ; Save DFAR
|
||||
MRC p15, 0, r0, c5, c0, 0 ; Read DFSR
|
||||
STR r0, [r3, #12] ; Save DFSR
|
||||
MRC p15, 0, r0, c6, c0, 2 ; Read IFAR
|
||||
STR r0, [r3, #16] ; Save IFAR
|
||||
MRC p15, 0, r0, c5, c0, 1 ; Read IFSR
|
||||
STR r0, [r3, #20] ; Save IFSR
|
||||
|
||||
; Save registers r0-r12
|
||||
POP {r0-r2}
|
||||
STR r0, [r3, #28] ; Save r0
|
||||
STR r1, [r3, #32] ; Save r1
|
||||
STR r2, [r3, #36] ; Save r2
|
||||
POP {r0}
|
||||
STR r0, [r3, #40] ; Save r3
|
||||
STR r4, [r3, #44] ; Save r4
|
||||
STR r5, [r3, #48] ; Save r5
|
||||
STR r6, [r3, #52] ; Save r6
|
||||
STR r7, [r3, #56] ; Save r7
|
||||
STR r8, [r3, #60] ; Save r8
|
||||
STR r9, [r3, #64] ; Save r9
|
||||
STR r10,[r3, #68] ; Save r10
|
||||
STR r11,[r3, #72] ; Save r11
|
||||
STR r12,[r3, #76] ; Save r12
|
||||
|
||||
CPS #SYS_MODE ; Enter SYS mode
|
||||
MOV r0, lr ; Pickup lr
|
||||
MOV r1, sp ; Pickup sp
|
||||
CPS #ABT_MODE ; Back to ABT mode
|
||||
STR r0, [r3, #80] ; Save lr
|
||||
STR r1, [r3, #24] ; Save sp
|
||||
MRS r0, SPSR ; Pickup SPSR
|
||||
STR r0, [r3, #84] ; Save SPSR
|
||||
ORR r0, r0, #SYS_MODE ; Return into SYS mode
|
||||
BIC r0, r0, #THUMB_MASK ; Clear THUMB mode
|
||||
MSR SPSR_c, r0 ; Save SPSR
|
||||
|
||||
; Call memory manager fault handler
|
||||
BL _txm_module_manager_memory_fault_handler
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
;
|
||||
BL _tx_execution_thread_exit ; Call the thread exit function
|
||||
ENDIF
|
||||
|
||||
LDR r0, =_tx_thread_system_state ; Pickup address of system state
|
||||
LDR r1, [r0] ; Pickup system state
|
||||
SUB r1, r1, #1 ; Decrement
|
||||
STR r1, [r0] ; Store new system state
|
||||
|
||||
MOV r1, #0 ; Build NULL value
|
||||
LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer
|
||||
STR r1, [r0] ; Clear current thread pointer
|
||||
|
||||
; Return from exception
|
||||
LDR lr, =_tx_thread_schedule ; Load scheduler address
|
||||
MOVS pc, lr ; Return to scheduler
|
||||
; *******************************************************************
|
||||
; End of MMU exception handling.
|
||||
; *******************************************************************
|
||||
|
||||
;
|
||||
; /* Reference build options and version ID to ensure they come in. */
|
||||
;
|
||||
LDR r2, =_tx_build_options ; Pickup build options variable address
|
||||
LDR r0, [r2, #0] ; Pickup build options content
|
||||
LDR r2, =_tx_version_id ; Pickup version ID variable address
|
||||
LDR r0, [r2, #0] ; Pickup version ID content
|
||||
;
|
||||
;
|
||||
END
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
AREA Init, CODE, READONLY
|
||||
|
||||
; /* Define public symbols. */
|
||||
|
||||
EXPORT __txm_module_preamble
|
||||
|
||||
|
||||
; /* Define application-specific start/stop entry points for the module. */
|
||||
|
||||
IMPORT demo_module_start
|
||||
|
||||
|
||||
; /* Define common external refrences. */
|
||||
|
||||
IMPORT _txm_module_thread_shell_entry
|
||||
IMPORT _txm_module_callback_request_thread_entry
|
||||
IMPORT |Image$$ER_RO$$Length|
|
||||
IMPORT |Image$$ER_RW$$Length|
|
||||
|
||||
|
||||
__txm_module_preamble
|
||||
DCD 0x4D4F4455 ; Module ID
|
||||
DCD 0x6 ; Module Major Version
|
||||
DCD 0x1 ; Module Minor Version
|
||||
DCD 32 ; Module Preamble Size in 32-bit words
|
||||
DCD 0x12345678 ; Module ID (application defined)
|
||||
DCD 0x01000001 ; Module Properties where:
|
||||
; Bits 31-24: Compiler ID
|
||||
; 0 -> IAR
|
||||
; 1 -> RVDS
|
||||
; 2 -> GNU
|
||||
; Bits 23-1: Reserved
|
||||
; Bit 0: 0 -> Privileged mode execution (no MMU protection)
|
||||
; 1 -> User mode execution (MMU protection)
|
||||
DCD _txm_module_thread_shell_entry - . + . ; Module Shell Entry Point
|
||||
DCD demo_module_start - . + . ; Module Start Thread Entry Point
|
||||
DCD 0 ; Module Stop Thread Entry Point
|
||||
DCD 1 ; Module Start/Stop Thread Priority
|
||||
DCD 2046 ; Module Start/Stop Thread Stack Size
|
||||
DCD _txm_module_callback_request_thread_entry - . + . ; Module Callback Thread Entry
|
||||
DCD 1 ; Module Callback Thread Priority
|
||||
DCD 2046 ; Module Callback Thread Stack Size
|
||||
DCD |Image$$ER_RO$$Length| + |Image$$ER_RW$$Length| ; Module Code Size
|
||||
DCD 0x4000 ; Module Data Size - default to 16K (need to make sure this is large enough for module's data needs!)
|
||||
DCD 0 ; Reserved 0
|
||||
DCD 0 ; Reserved 1
|
||||
DCD 0 ; Reserved 2
|
||||
DCD 0 ; Reserved 3
|
||||
DCD 0 ; Reserved 4
|
||||
DCD 0 ; Reserved 5
|
||||
DCD 0 ; Reserved 6
|
||||
DCD 0 ; Reserved 7
|
||||
DCD 0 ; Reserved 8
|
||||
DCD 0 ; Reserved 9
|
||||
DCD 0 ; Reserved 10
|
||||
DCD 0 ; Reserved 11
|
||||
DCD 0 ; Reserved 12
|
||||
DCD 0 ; Reserved 13
|
||||
DCD 0 ; Reserved 14
|
||||
DCD 0 ; Reserved 15
|
||||
|
||||
END
|
||||
|
||||
|
||||
352
ports_module/cortex-a7/ac5/inc/tx_port.h
Normal file
352
ports_module/cortex-a7/ac5/inc/tx_port.h
Normal file
@@ -0,0 +1,352 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Port Specific */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* PORT SPECIFIC C INFORMATION RELEASE */
|
||||
/* */
|
||||
/* tx_port.h Cortex-A7/AC5 */
|
||||
/* 6.1 */
|
||||
/* */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* William E. Lamie, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This file contains data type definitions that make the ThreadX */
|
||||
/* real-time kernel function identically on a variety of different */
|
||||
/* processor architectures. For example, the size or number of bits */
|
||||
/* in an "int" data type vary between microprocessor architectures and */
|
||||
/* even C compilers for the same microprocessor. ThreadX does not */
|
||||
/* directly use native C data types. Instead, ThreadX creates its */
|
||||
/* own special types that can be mapped to actual data types by this */
|
||||
/* file to guarantee consistency in the interface and functionality. */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TX_PORT_H
|
||||
#define TX_PORT_H
|
||||
|
||||
|
||||
/* Determine if the optional ThreadX user define file should be used. */
|
||||
|
||||
#ifdef TX_INCLUDE_USER_DEFINE_FILE
|
||||
|
||||
|
||||
/* Yes, include the user defines in tx_user.h. The defines in this file may
|
||||
alternately be defined on the command line. */
|
||||
|
||||
#include "tx_user.h"
|
||||
#endif
|
||||
|
||||
|
||||
/* Define compiler library include files. */
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
|
||||
/* Define ThreadX basic types for this port. */
|
||||
|
||||
#define VOID void
|
||||
typedef char CHAR;
|
||||
typedef unsigned char UCHAR;
|
||||
typedef int INT;
|
||||
typedef unsigned int UINT;
|
||||
typedef long LONG;
|
||||
typedef unsigned long ULONG;
|
||||
typedef short SHORT;
|
||||
typedef unsigned short USHORT;
|
||||
|
||||
|
||||
/* Define the priority levels for ThreadX. Legal values range
|
||||
from 32 to 1024 and MUST be evenly divisible by 32. */
|
||||
|
||||
#ifndef TX_MAX_PRIORITIES
|
||||
#define TX_MAX_PRIORITIES 32
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
|
||||
thread creation is less than this value, the thread create call will return an error. */
|
||||
|
||||
#ifndef TX_MINIMUM_STACK
|
||||
#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the system timer thread's default stack size and priority. These are only applicable
|
||||
if TX_TIMER_PROCESS_IN_ISR is not defined. */
|
||||
|
||||
#ifndef TX_TIMER_THREAD_STACK_SIZE
|
||||
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
|
||||
#endif
|
||||
|
||||
#ifndef TX_TIMER_THREAD_PRIORITY
|
||||
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
|
||||
#endif
|
||||
|
||||
|
||||
/* Define various constants for the ThreadX ARM port. */
|
||||
|
||||
#ifdef TX_ENABLE_FIQ_SUPPORT
|
||||
#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */
|
||||
#else
|
||||
#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */
|
||||
#endif
|
||||
#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */
|
||||
|
||||
|
||||
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
|
||||
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
|
||||
source constants would be:
|
||||
|
||||
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
|
||||
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
|
||||
|
||||
*/
|
||||
|
||||
#ifndef TX_TRACE_TIME_SOURCE
|
||||
#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time
|
||||
#endif
|
||||
#ifndef TX_TRACE_TIME_MASK
|
||||
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the port specific options for the _tx_build_options variable. This variable indicates
|
||||
how the ThreadX library was built. */
|
||||
|
||||
#ifdef TX_ENABLE_FIQ_SUPPORT
|
||||
#define TX_FIQ_ENABLED 1
|
||||
#else
|
||||
#define TX_FIQ_ENABLED 0
|
||||
#endif
|
||||
|
||||
#ifdef TX_ENABLE_IRQ_NESTING
|
||||
#define TX_IRQ_NESTING_ENABLED 2
|
||||
#else
|
||||
#define TX_IRQ_NESTING_ENABLED 0
|
||||
#endif
|
||||
|
||||
#ifdef TX_ENABLE_FIQ_NESTING
|
||||
#define TX_FIQ_NESTING_ENABLED 4
|
||||
#else
|
||||
#define TX_FIQ_NESTING_ENABLED 0
|
||||
#endif
|
||||
|
||||
#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED
|
||||
|
||||
|
||||
/* Define the in-line initialization constant so that modules with in-line
|
||||
initialization capabilities can prevent their initialization from being
|
||||
a function call. */
|
||||
|
||||
#define TX_INLINE_INITIALIZATION
|
||||
|
||||
|
||||
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
|
||||
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
|
||||
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
|
||||
define is negated, thereby forcing the stack fill which is necessary for the stack checking
|
||||
logic. */
|
||||
|
||||
#ifdef TX_ENABLE_STACK_CHECKING
|
||||
#undef TX_DISABLE_STACK_FILLING
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the TX_THREAD control block extensions for this port. The main reason
|
||||
for the multiple macros is so that backward compatibility can be maintained with
|
||||
existing ThreadX kernel awareness modules. */
|
||||
|
||||
#define TX_THREAD_EXTENSION_0
|
||||
#define TX_THREAD_EXTENSION_1
|
||||
#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \
|
||||
VOID *tx_thread_module_instance_ptr; \
|
||||
VOID *tx_thread_module_entry_info_ptr; \
|
||||
ULONG tx_thread_module_current_user_mode; \
|
||||
ULONG tx_thread_module_user_mode; \
|
||||
VOID *tx_thread_module_kernel_stack_start; \
|
||||
VOID *tx_thread_module_kernel_stack_end; \
|
||||
ULONG tx_thread_module_kernel_stack_size; \
|
||||
VOID *tx_thread_module_stack_ptr; \
|
||||
VOID *tx_thread_module_stack_start; \
|
||||
VOID *tx_thread_module_stack_end; \
|
||||
ULONG tx_thread_module_stack_size; \
|
||||
VOID *tx_thread_module_reserved;
|
||||
#define TX_THREAD_EXTENSION_3
|
||||
|
||||
|
||||
/* Define the port extensions of the remaining ThreadX objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_EXTENSION
|
||||
#define TX_BYTE_POOL_EXTENSION
|
||||
#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \
|
||||
VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
|
||||
#define TX_MUTEX_EXTENSION
|
||||
#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \
|
||||
VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
|
||||
|
||||
#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \
|
||||
VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
|
||||
|
||||
#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \
|
||||
VOID (*tx_timer_module_expiration_function)(ULONG id);
|
||||
|
||||
|
||||
/* Define the user extension field of the thread control block. Nothing
|
||||
additional is needed for this port so it is defined as white space. */
|
||||
|
||||
#ifndef TX_THREAD_USER_EXTENSION
|
||||
#define TX_THREAD_USER_EXTENSION
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
|
||||
tx_thread_shell_entry, and tx_thread_terminate. */
|
||||
|
||||
|
||||
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
|
||||
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
|
||||
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
|
||||
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
|
||||
|
||||
|
||||
/* Define the ThreadX object creation extensions for the remaining objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
|
||||
#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
|
||||
#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
|
||||
#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
|
||||
#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
|
||||
#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
|
||||
#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
|
||||
|
||||
|
||||
/* Define the ThreadX object deletion extensions for the remaining objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
|
||||
#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
|
||||
#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
|
||||
#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
|
||||
#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
|
||||
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
|
||||
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
|
||||
|
||||
|
||||
/* Determine if the ARM architecture has the CLZ instruction. This is available on
|
||||
architectures v5 and above. If available, redefine the macro for calculating the
|
||||
lowest bit set. */
|
||||
|
||||
#ifndef __thumb
|
||||
|
||||
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \
|
||||
b = (ULONG) __clz((unsigned int) m); \
|
||||
b = 31 - b;
|
||||
#endif
|
||||
|
||||
|
||||
/* Define ThreadX interrupt lockout and restore macros for protection on
|
||||
access of critical kernel information. The restore interrupt macro must
|
||||
restore the interrupt posture of the running thread prior to the value
|
||||
present prior to the disable macro. In most cases, the save area macro
|
||||
is used to define a local function save area for the disable and restore
|
||||
macros. */
|
||||
|
||||
#ifndef __thumb
|
||||
|
||||
#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled;
|
||||
|
||||
#ifdef TX_ENABLE_FIQ_SUPPORT
|
||||
|
||||
/* IRQ and FIQ support. */
|
||||
|
||||
#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq(); \
|
||||
__disable_fiq();
|
||||
|
||||
#define TX_RESTORE if (!interrupt_save_disabled) \
|
||||
{ \
|
||||
__enable_irq(); \
|
||||
__enable_fiq(); \
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define TX_DISABLE __memory_changed(), interrupt_save_disabled = __disable_irq();
|
||||
|
||||
#define TX_RESTORE if (!interrupt_save_disabled) \
|
||||
{ \
|
||||
__enable_irq(); \
|
||||
}
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
unsigned int _tx_thread_interrupt_disable(void);
|
||||
unsigned int _tx_thread_interrupt_restore(UINT old_posture);
|
||||
|
||||
|
||||
#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save;
|
||||
|
||||
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable();
|
||||
#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save);
|
||||
#endif
|
||||
|
||||
|
||||
/* Define VFP extension for the Cortex-A5. Each is assumed to be called in the context of the executing
|
||||
thread. */
|
||||
|
||||
void tx_thread_vfp_enable(void);
|
||||
void tx_thread_vfp_disable(void);
|
||||
|
||||
|
||||
/* Define the interrupt lockout macros for each ThreadX object. */
|
||||
|
||||
#define TX_BLOCK_POOL_DISABLE TX_DISABLE
|
||||
#define TX_BYTE_POOL_DISABLE TX_DISABLE
|
||||
#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE
|
||||
#define TX_MUTEX_DISABLE TX_DISABLE
|
||||
#define TX_QUEUE_DISABLE TX_DISABLE
|
||||
#define TX_SEMAPHORE_DISABLE TX_DISABLE
|
||||
|
||||
|
||||
/* Define the version ID of ThreadX. This may be utilized by the application. */
|
||||
|
||||
#ifdef TX_THREAD_INIT
|
||||
CHAR _tx_version_id[] =
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.1 *";
|
||||
#else
|
||||
extern CHAR _tx_version_id[];
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
413
ports_module/cortex-a7/ac5/inc/txm_module_port.h
Normal file
413
ports_module/cortex-a7/ac5/inc/txm_module_port.h
Normal file
@@ -0,0 +1,413 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Interface (API) */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* APPLICATION INTERFACE DEFINITION RELEASE */
|
||||
/* */
|
||||
/* txm_module_port.h Cortex-A7/MMU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This file defines the basic module constants, interface structures, */
|
||||
/* and function prototypes. */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TXM_MODULE_PORT_H
|
||||
#define TXM_MODULE_PORT_H
|
||||
|
||||
/* It is assumed that the base ThreadX tx_port.h file has been modified to add the
|
||||
following extensions to the ThreadX thread control block (this code should replace
|
||||
the corresponding macro define in tx_port.h):
|
||||
|
||||
#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; \
|
||||
VOID *tx_thread_module_instance_ptr; \
|
||||
VOID *tx_thread_module_entry_info_ptr; \
|
||||
ULONG tx_thread_module_current_user_mode; \
|
||||
ULONG tx_thread_module_user_mode; \
|
||||
VOID *tx_thread_module_kernel_stack_start; \
|
||||
VOID *tx_thread_module_kernel_stack_end; \
|
||||
ULONG tx_thread_module_kernel_stack_size; \
|
||||
VOID *tx_thread_module_stack_ptr; \
|
||||
VOID *tx_thread_module_stack_start; \
|
||||
VOID *tx_thread_module_stack_end; \
|
||||
ULONG tx_thread_module_stack_size; \
|
||||
VOID *tx_thread_module_reserved;
|
||||
|
||||
|
||||
The following extensions must also be defined in tx_port.h:
|
||||
|
||||
#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \
|
||||
VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
|
||||
|
||||
#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \
|
||||
VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
|
||||
|
||||
#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \
|
||||
VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
|
||||
|
||||
#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \
|
||||
VOID (*tx_timer_module_expiration_function)(ULONG id);
|
||||
*/
|
||||
|
||||
/* Define the kernel stack size for a module thread. */
|
||||
#ifndef TXM_MODULE_KERNEL_STACK_SIZE
|
||||
#define TXM_MODULE_KERNEL_STACK_SIZE 512
|
||||
#endif
|
||||
|
||||
/* Defined, this option enables the MMU hardware and requires memory protected
|
||||
module objects to be allocated from the module manager object pool.
|
||||
If this is undefined, module objects can be created in the module's data area
|
||||
or in the module manager object pool. If this is not defined (MMU hardware
|
||||
is disabled), a module requiring memory protection will not run (the load
|
||||
functions will return a TXM_MODULE_INVALID_PROPERTIES error).
|
||||
Default setting for this value is defined. */
|
||||
#define TXM_MODULE_MEMORY_PROTECTION_ENABLED
|
||||
|
||||
/* Define constants specific to the tools the module can be built with for this particular modules port. */
|
||||
|
||||
#define TXM_MODULE_IAR_COMPILER 0x00000000
|
||||
#define TXM_MODULE_RVDS_COMPILER 0x01000000
|
||||
#define TXM_MODULE_GNU_COMPILER 0x02000000
|
||||
#define TXM_MODULE_COMPILER_MASK 0xFF000000
|
||||
#define TXM_MODULE_OPTIONS_MASK 0x000000FF
|
||||
|
||||
|
||||
/* Define the properties for this particular module port. */
|
||||
#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED
|
||||
#define TXM_MODULE_MEMORY_PROTECTION 0x00000001
|
||||
#else
|
||||
#define TXM_MODULE_MEMORY_PROTECTION 0x00000000
|
||||
#endif
|
||||
|
||||
#define TXM_MODULE_USER_MODE 0x00000001
|
||||
|
||||
/* Define the supported options for this module. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_MEMORY_PROTECTION)
|
||||
#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0
|
||||
|
||||
|
||||
/* Define offset adjustments according to the compiler used to build the module. */
|
||||
|
||||
#define TXM_MODULE_IAR_SHELL_ADJUST 24
|
||||
#define TXM_MODULE_IAR_START_ADJUST 28
|
||||
#define TXM_MODULE_IAR_STOP_ADJUST 32
|
||||
#define TXM_MODULE_IAR_CALLBACK_ADJUST 44
|
||||
|
||||
#define TXM_MODULE_RVDS_SHELL_ADJUST 0
|
||||
#define TXM_MODULE_RVDS_START_ADJUST 0
|
||||
#define TXM_MODULE_RVDS_STOP_ADJUST 0
|
||||
#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0
|
||||
|
||||
#define TXM_MODULE_GNU_SHELL_ADJUST 24
|
||||
#define TXM_MODULE_GNU_START_ADJUST 28
|
||||
#define TXM_MODULE_GNU_STOP_ADJUST 32
|
||||
#define TXM_MODULE_GNU_CALLBACK_ADJUST 44
|
||||
|
||||
|
||||
/* Define other module port-specific constants. */
|
||||
|
||||
/* Define INLINE_DECLARE to whitespace for ARM compiler. */
|
||||
#define INLINE_DECLARE
|
||||
|
||||
#define TXM_MAXIMUM_MODULES 16
|
||||
#define TXM_MODULE_LEVEL1_PAGE_TABLE_SIZE 32
|
||||
#define TXM_ASID_TABLE_LENGTH 256
|
||||
|
||||
#define TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET (TXM_MAXIMUM_MODULES * 0)
|
||||
#define TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET (TXM_MAXIMUM_MODULES * 1)
|
||||
#define TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET (TXM_MAXIMUM_MODULES * 2)
|
||||
#define TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET (TXM_MAXIMUM_MODULES * 3)
|
||||
|
||||
#define TXM_MASTER_PAGE_TABLE_INDEX 0
|
||||
|
||||
/* 1 entry per 1MB, so this covers 4G address space */
|
||||
#define TXM_MASTER_PAGE_TABLE_ENTRIES 4096
|
||||
|
||||
/* Smallest MMU page size is 4kB. */
|
||||
#define TXM_MODULE_MEMORY_ALIGNMENT 4096
|
||||
#define TXM_MMU_LEVEL1_PAGE_SHIFT 20
|
||||
#define TXM_MMU_LEVEL2_PAGE_SHIFT 12
|
||||
#define TXM_LEVEL_2_PAGE_TABLE_ENTRIES 256
|
||||
|
||||
/* Level 1 section base address mask. */
|
||||
#define TXM_MMU_LEVEL1_MASK 0xFFF00000
|
||||
|
||||
/* Level 2 section base address mask. */
|
||||
#define TXM_MMU_LEVEL2_MASK 0xFFFFF000
|
||||
|
||||
/* Non-global, outer & inner write-back, write-allocate, user read, no write. */
|
||||
#define TXM_MMU_LEVEL1_CODE_ATTRIBUTES 0x000219EE
|
||||
/* Non-global, outer & inner write-back, write-allocate, user read, write, no-execute. */
|
||||
#define TXM_MMU_LEVEL1_DATA_ATTRIBUTES 0x00021DFE
|
||||
|
||||
/* Level 1 "level 2 descriptor base address" mask. */
|
||||
#define TXM_MMU_LEVEL1_SECOND_MASK 0xFFFFFC00
|
||||
|
||||
/* Level 1 "level 2 descriptor" attributes. */
|
||||
#define TXM_MMU_LEVEL1_SECOND_ATTRIBUTES 0x0000001E1
|
||||
|
||||
/* Kernel level 2 attributes: global, outer & inner write-back, write-allocate, user read/write */
|
||||
#define TXM_MMU_KERNEL_LEVEL2_CODE_ATTRIBUTES 0x0000006E
|
||||
#define TXM_MMU_KERNEL_LEVEL2_DATA_ATTRIBUTES 0x0000005E
|
||||
|
||||
/* Module level 2 attributes: non-global, outer & inner write-back, write-allocate, user read, no write. */
|
||||
#define TXM_MMU_LEVEL2_CODE_ATTRIBUTES 0x0000086E
|
||||
#define TXM_MMU_LEVEL2_DATA_ATTRIBUTES 0x0000087F
|
||||
|
||||
|
||||
/* Settings the user can use to set up shared memory attributes. */
|
||||
#define TXM_MMU_ATTRIBUTE_XN 0x00000001
|
||||
#define TXM_MMU_ATTRIBUTE_B 0x00000002
|
||||
#define TXM_MMU_ATTRIBUTE_C 0x00000004
|
||||
#define TXM_MMU_ATTRIBUTE_AP 0x00000018
|
||||
#define TXM_MMU_ATTRIBUTE_TEX 0x000000E0
|
||||
|
||||
/* Masks for each attribute. */
|
||||
#define TXM_MMU_ATTRIBUTE_XN_MASK 0x00000001
|
||||
#define TXM_MMU_ATTRIBUTE_B_MASK 0x00000001
|
||||
#define TXM_MMU_ATTRIBUTE_C_MASK 0x00000001
|
||||
#define TXM_MMU_ATTRIBUTE_AP_MASK 0x00000003
|
||||
#define TXM_MMU_ATTRIBUTE_TEX_MASK 0x00000007
|
||||
|
||||
/* Shift amounts for bitfields above to correct register locations. */
|
||||
#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_XN_SHIFT 4
|
||||
#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_B_SHIFT 1
|
||||
#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_C_SHIFT 1
|
||||
#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_AP_SHIFT 7
|
||||
#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_TEX_SHIFT 7
|
||||
#define TXM_MMU_LEVEL1_USER_ATTRIBUTE_BASE 0x000201E2
|
||||
|
||||
#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_XN_SHIFT 0
|
||||
#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_B_SHIFT 1
|
||||
#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_C_SHIFT 1
|
||||
#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_AP_SHIFT 1
|
||||
#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_TEX_SHIFT 1
|
||||
#define TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE 0x00000802
|
||||
|
||||
/* Shift amounts from bit 0 position. */
|
||||
#define TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT 4
|
||||
#define TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT 2
|
||||
#define TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT 3
|
||||
#define TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT 10
|
||||
#define TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT 12
|
||||
|
||||
#define TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT 0
|
||||
#define TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT 2
|
||||
#define TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT 3
|
||||
#define TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT 4
|
||||
#define TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT 6
|
||||
|
||||
/* Masks for L1 page attributes. */
|
||||
#define TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK (TXM_MMU_ATTRIBUTE_XN_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT)
|
||||
#define TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK (TXM_MMU_ATTRIBUTE_B_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT)
|
||||
#define TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK (TXM_MMU_ATTRIBUTE_C_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT)
|
||||
#define TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK (TXM_MMU_ATTRIBUTE_AP_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT)
|
||||
#define TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK (TXM_MMU_ATTRIBUTE_TEX_MASK << TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT)
|
||||
|
||||
/* Masks for L2 page attributes. */
|
||||
#define TXM_MMU_LEVEL2_ATTRIBUTE_XN_MASK (TXM_MMU_ATTRIBUTE_XN_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT)
|
||||
#define TXM_MMU_LEVEL2_ATTRIBUTE_B_MASK (TXM_MMU_ATTRIBUTE_B_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT)
|
||||
#define TXM_MMU_LEVEL2_ATTRIBUTE_C_MASK (TXM_MMU_ATTRIBUTE_C_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT)
|
||||
#define TXM_MMU_LEVEL2_ATTRIBUTE_AP_MASK (TXM_MMU_ATTRIBUTE_AP_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT)
|
||||
#define TXM_MMU_LEVEL2_ATTRIBUTE_TEX_MASK (TXM_MMU_ATTRIBUTE_TEX_MASK << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT)
|
||||
|
||||
#define TXM_ADDRESS_TRANSLATION_FAULT_BIT 1
|
||||
|
||||
#define TXM_ASID_RESERVED 0xFFFFFFFF
|
||||
|
||||
#define TXM_MODULE_ASID_ERROR 0xF6
|
||||
#define TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR 0xF7
|
||||
|
||||
/* Number of L2 pages each module can have. */
|
||||
#define TXM_MODULE_LEVEL2_EXTERNAL_PAGES 16
|
||||
/* Size, in pages, of the L2 page pool. */
|
||||
#define TXM_LEVEL2_EXTERNAL_POOL_PAGES (TXM_MODULE_LEVEL2_EXTERNAL_PAGES * TXM_MAXIMUM_MODULES)
|
||||
|
||||
|
||||
/* Define the port-extensions to the module manager instance structure. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_PORT_EXTENSION \
|
||||
ULONG txm_module_instance_asid; \
|
||||
ULONG *txm_external_page_table[TXM_MODULE_LEVEL2_EXTERNAL_PAGES];
|
||||
|
||||
/* Define the memory fault information structure that is populated when a memory fault occurs. */
|
||||
|
||||
|
||||
typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
|
||||
{
|
||||
TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr;
|
||||
VOID *txm_module_manager_memory_fault_info_code_location;
|
||||
ULONG txm_module_manager_memory_fault_info_dfar;
|
||||
ULONG txm_module_manager_memory_fault_info_dfsr;
|
||||
ULONG txm_module_manager_memory_fault_info_ifar;
|
||||
ULONG txm_module_manager_memory_fault_info_ifsr;
|
||||
ULONG txm_module_manager_memory_fault_info_sp;
|
||||
ULONG txm_module_manager_memory_fault_info_r0;
|
||||
ULONG txm_module_manager_memory_fault_info_r1;
|
||||
ULONG txm_module_manager_memory_fault_info_r2;
|
||||
ULONG txm_module_manager_memory_fault_info_r3;
|
||||
ULONG txm_module_manager_memory_fault_info_r4;
|
||||
ULONG txm_module_manager_memory_fault_info_r5;
|
||||
ULONG txm_module_manager_memory_fault_info_r6;
|
||||
ULONG txm_module_manager_memory_fault_info_r7;
|
||||
ULONG txm_module_manager_memory_fault_info_r8;
|
||||
ULONG txm_module_manager_memory_fault_info_r9;
|
||||
ULONG txm_module_manager_memory_fault_info_r10;
|
||||
ULONG txm_module_manager_memory_fault_info_r11;
|
||||
ULONG txm_module_manager_memory_fault_info_r12;
|
||||
ULONG txm_module_manager_memory_fault_info_lr;
|
||||
ULONG txm_module_manager_memory_fault_info_cpsr;
|
||||
} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO;
|
||||
|
||||
|
||||
#define TXM_MODULE_MANAGER_FAULT_INFO \
|
||||
TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info;
|
||||
|
||||
/* Define the macro to check the stack available in dispatch. */
|
||||
#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE
|
||||
|
||||
|
||||
/* Define the macro to check the code alignment. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \
|
||||
{ \
|
||||
ULONG temp; \
|
||||
temp = (ULONG) module_location; \
|
||||
temp = temp & (TXM_MODULE_MEMORY_ALIGNMENT - 1); \
|
||||
if (temp) \
|
||||
{ \
|
||||
_tx_mutex_put(&_txm_module_manager_mutex); \
|
||||
return(TXM_MODULE_ALIGNMENT_ERROR); \
|
||||
} \
|
||||
}
|
||||
|
||||
|
||||
/* Define the macro to adjust the alignment and size for code/data areas. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment);
|
||||
|
||||
|
||||
/* Define the macro to adjust the symbols in the module preamble. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \
|
||||
if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \
|
||||
{ \
|
||||
shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \
|
||||
start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \
|
||||
stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \
|
||||
callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \
|
||||
} \
|
||||
else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \
|
||||
{ \
|
||||
shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \
|
||||
start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \
|
||||
stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \
|
||||
callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \
|
||||
start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \
|
||||
stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \
|
||||
callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \
|
||||
}
|
||||
|
||||
|
||||
/* Define the macro to populate the thread control block with module port-specific information. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \
|
||||
thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION; \
|
||||
thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION; \
|
||||
if (thread_ptr -> tx_thread_module_user_mode) \
|
||||
{ \
|
||||
thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \
|
||||
}
|
||||
|
||||
|
||||
/* Define the macro to populate the module control block with module port-specific information.
|
||||
If memory protection is enabled, set up the MMU registers.
|
||||
*/
|
||||
#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \
|
||||
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \
|
||||
{ \
|
||||
_txm_module_manager_mm_register_setup(module_instance); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
/* Do nothing. */ \
|
||||
}
|
||||
|
||||
/* Define the macro to perform port-specific functions when unloading the module. */
|
||||
#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) \
|
||||
_txm_level2_page_clear(module_instance); \
|
||||
_txm_module_manager_remove_asid(module_instance);
|
||||
|
||||
/* Define the macros to perform port-specific checks when passing pointers to the kernel. */
|
||||
|
||||
/* Define macro to make sure object is inside the module's data or shared memory. */
|
||||
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
|
||||
_txm_module_manager_inside_data_check((ULONG) obj_ptr)
|
||||
|
||||
|
||||
/* Define some internal prototypes to this module port. */
|
||||
|
||||
#ifndef TX_SOURCE_CODE
|
||||
#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify
|
||||
#define txm_module_manager_mm_initialize _txm_module_manager_mm_initialize
|
||||
#endif
|
||||
|
||||
|
||||
#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \
|
||||
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \
|
||||
ULONG _txm_module_manager_data_pointer_check(ULONG pointer); \
|
||||
VOID _txm_module_manager_memory_fault_handler(VOID); \
|
||||
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \
|
||||
UINT _txm_module_manager_mm_initialize(VOID); \
|
||||
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \
|
||||
VOID _txm_level2_page_clear(TXM_MODULE_INSTANCE *module_instance); \
|
||||
VOID _txm_module_manager_remove_asid(TXM_MODULE_INSTANCE *module_instance); \
|
||||
UINT _txm_module_manager_inside_data_check(ULONG pointer);
|
||||
|
||||
#define TXM_MODULE_MANAGER_VERSION_ID \
|
||||
CHAR _txm_module_manager_version_id[] = \
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-A7/MMU/AC5 Version 6.1 *";
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,91 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Module */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
;
|
||||
IMPORT __scatterload
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _txm_module_initialize Cortex-A7/MMU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function initializes the module c runtime. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* __scatterload Initialize C runtime */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _txm_module_thread_shell_entry Start module thread */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _txm_module_initialize(VOID)
|
||||
;{
|
||||
EXPORT _txm_module_initialize
|
||||
_txm_module_initialize
|
||||
PUSH {r4-r12,lr} ; Save dregs and LR
|
||||
|
||||
B __scatterload ; Call ARM func to initialize variables
|
||||
|
||||
;/* Override __rt_exit function. */
|
||||
EXPORT __rt_exit
|
||||
__rt_exit
|
||||
|
||||
POP {r4-r12,lr} ; Restore dregs and LR
|
||||
BX lr ; Return to caller
|
||||
;}
|
||||
|
||||
END
|
||||
|
||||
@@ -0,0 +1,175 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TXM_MODULE
|
||||
#define TXM_MODULE
|
||||
#endif
|
||||
|
||||
#ifndef TX_SOURCE_CODE
|
||||
#define TX_SOURCE_CODE
|
||||
#endif
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/* Define the global module entry pointer from the start thread of the module. */
|
||||
|
||||
TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info;
|
||||
|
||||
|
||||
/* Define the dispatch function pointer used in the module implementation. */
|
||||
|
||||
ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3);
|
||||
|
||||
|
||||
|
||||
/* Define the RVDS startup code that clears the uninitialized global data and sets up the
|
||||
preset global variables. */
|
||||
extern VOID _txm_module_initialize(VOID);
|
||||
int main(VOID){return 0;}
|
||||
VOID __user_setup_stackheap(VOID){return;}
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_thread_shell_entry Cortex-A7/MMU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function calls the specified entry function of the thread. It */
|
||||
/* also provides a place for the thread's entry function to return. */
|
||||
/* If the thread returns, this function places the thread in a */
|
||||
/* "COMPLETED" state. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Pointer to current thread */
|
||||
/* thread_info Pointer to thread entry info */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* __rt_lib_init RVDS global init function */
|
||||
/* thread_entry Thread's entry function */
|
||||
/* tx_thread_resume Resume the module callback thread */
|
||||
/* txm_module_thread_system_suspend Module thread suspension routine */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Initial thread stack frame */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
|
||||
{
|
||||
|
||||
#ifndef TX_DISABLE_NOTIFY_CALLBACKS
|
||||
VOID (*entry_exit_notify)(TX_THREAD *, UINT);
|
||||
#endif
|
||||
|
||||
|
||||
/* Determine if this is the start thread. If so, we must prepare the module for
|
||||
execution. If not, simply skip the C startup code. */
|
||||
if (thread_info -> txm_module_thread_entry_info_start_thread)
|
||||
{
|
||||
/* Initialize the RVDS C environment. */
|
||||
_txm_module_initialize();
|
||||
|
||||
/* Save the entry info pointer, for later use. */
|
||||
_txm_module_entry_info = thread_info;
|
||||
|
||||
/* Save the kernel function dispatch address. This is used to make all resident calls from
|
||||
the module. */
|
||||
_txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher;
|
||||
|
||||
/* Ensure that we have a valid pointer. */
|
||||
while (!_txm_module_kernel_call_dispatcher)
|
||||
{
|
||||
/* Loop here, if an error is present getting the dispatch function pointer!
|
||||
An error here typically indicates the resident portion of _tx_thread_schedule
|
||||
is not supporting the trap to obtain the function pointer. */
|
||||
}
|
||||
|
||||
/* Resume the module's callback thread, already created in the manager. */
|
||||
_txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread);
|
||||
}
|
||||
|
||||
#ifndef TX_DISABLE_NOTIFY_CALLBACKS
|
||||
|
||||
/* Pickup the entry/exit application callback routine. */
|
||||
entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify;
|
||||
|
||||
/* Determine if an application callback routine is specified. */
|
||||
if (entry_exit_notify != TX_NULL)
|
||||
{
|
||||
|
||||
/* Yes, notify application that this thread has been entered! */
|
||||
(entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Call current thread's entry function. */
|
||||
(thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter);
|
||||
|
||||
/* Suspend thread with a "completed" state. */
|
||||
|
||||
|
||||
#ifndef TX_DISABLE_NOTIFY_CALLBACKS
|
||||
|
||||
/* Pickup the entry/exit application callback routine again. */
|
||||
entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify;
|
||||
|
||||
/* Determine if an application callback routine is specified. */
|
||||
if (entry_exit_notify != TX_NULL)
|
||||
{
|
||||
|
||||
/* Yes, notify application that this thread has exited! */
|
||||
(entry_exit_notify)(thread_ptr, TX_THREAD_EXIT);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Call actual thread suspension routine. */
|
||||
_txm_module_thread_system_suspend(thread_ptr);
|
||||
|
||||
#ifdef TX_SAFETY_CRITICAL
|
||||
|
||||
/* If we ever get here, raise safety critical exception. */
|
||||
TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -0,0 +1,260 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;#include "tx_timer.h"
|
||||
;
|
||||
;
|
||||
|
||||
IRQ_MODE EQU 0x12 ; IRQ mode
|
||||
SVC_MODE EQU 0x13 ; SVC mode
|
||||
SYS_MODE EQU 0x1F ; SYS mode
|
||||
THUMB_MASK EQU 0x20 ; Thumb bit mask
|
||||
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts
|
||||
ELSE
|
||||
DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
IMPORT _tx_thread_system_state
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IMPORT _tx_thread_execute_ptr
|
||||
IMPORT _tx_timer_time_slice
|
||||
IMPORT _tx_thread_schedule
|
||||
IMPORT _tx_thread_preempt_disable
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_isr_exit
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_context_restore Cortex-A7/MMU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function restores the interrupt context if it is processing a */
|
||||
;/* nested interrupt. If not, it returns to the interrupt thread if no */
|
||||
;/* preemption is necessary. Otherwise, if preemption is necessary or */
|
||||
;/* if no thread was running, the function returns to the scheduler. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Thread scheduling routine */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs Interrupt Service Routines */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_context_restore(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_context_restore
|
||||
_tx_thread_context_restore
|
||||
;
|
||||
; /* Lockout interrupts. */
|
||||
;
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
CPSID if ; Disable IRQ and FIQ interrupts
|
||||
ELSE
|
||||
CPSID i ; Disable IRQ interrupts
|
||||
ENDIF
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR exit function to indicate an ISR is complete. */
|
||||
;
|
||||
BL _tx_execution_isr_exit ; Call the ISR exit function
|
||||
ENDIF
|
||||
;
|
||||
; /* Determine if interrupts are nested. */
|
||||
; if (--_tx_thread_system_state)
|
||||
; {
|
||||
;
|
||||
LDR r3, =_tx_thread_system_state ; Pickup address of system state var
|
||||
LDR r2, [r3, #0] ; Pickup system state
|
||||
SUB r2, r2, #1 ; Decrement the counter
|
||||
STR r2, [r3, #0] ; Store the counter
|
||||
CMP r2, #0 ; Was this the first interrupt?
|
||||
BEQ __tx_thread_not_nested_restore ; If so, not a nested restore
|
||||
;
|
||||
; /* Interrupts are nested. */
|
||||
;
|
||||
; /* Just recover the saved registers and return to the point of
|
||||
; interrupt. */
|
||||
;
|
||||
LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs
|
||||
MSR SPSR_cxsf, r0 ; Put SPSR back
|
||||
LDMIA sp!, {r0-r3} ; Recover r0-r3
|
||||
MOVS pc, lr ; Return to point of interrupt
|
||||
;
|
||||
; }
|
||||
__tx_thread_not_nested_restore
|
||||
;
|
||||
; /* Determine if a thread was interrupted and no preemption is required. */
|
||||
; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
|
||||
; || (_tx_thread_preempt_disable))
|
||||
; {
|
||||
;
|
||||
LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr
|
||||
LDR r0, [r1, #0] ; Pickup actual current thread pointer
|
||||
CMP r0, #0 ; Is it NULL?
|
||||
BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted
|
||||
;
|
||||
LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address
|
||||
LDR r2, [r3, #0] ; Pickup actual preempt disable flag
|
||||
CMP r2, #0 ; Is it set?
|
||||
BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread
|
||||
LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr
|
||||
LDR r2, [r3, #0] ; Pickup actual execute thread pointer
|
||||
CMP r0, r2 ; Is the same thread highest priority?
|
||||
BNE __tx_thread_preempt_restore ; No, preemption needs to happen
|
||||
;
|
||||
;
|
||||
__tx_thread_no_preempt_restore
|
||||
;
|
||||
; /* Restore interrupted thread or ISR. */
|
||||
;
|
||||
; /* Pickup the saved stack pointer. */
|
||||
; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr;
|
||||
;
|
||||
; /* Recover the saved context and return to the point of interrupt. */
|
||||
;
|
||||
LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs
|
||||
MSR SPSR_cxsf, r0 ; Put SPSR back
|
||||
LDMIA sp!, {r0-r3} ; Recover r0-r3
|
||||
MOVS pc, lr ; Return to point of interrupt
|
||||
;
|
||||
; }
|
||||
; else
|
||||
; {
|
||||
__tx_thread_preempt_restore
|
||||
;
|
||||
LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers
|
||||
MOV r1, lr ; Save lr (point of interrupt)
|
||||
CPS #SYS_MODE ; Enter SYS mode
|
||||
STR r1, [sp, #-4]! ; Save point of interrupt on thread's stack
|
||||
STMDB sp!, {r4-r12, lr} ; Save upper half of registers on thread's stack
|
||||
MOV r4, r3 ; Save SPSR in r4
|
||||
CPS #IRQ_MODE ; Enter IRQ mode
|
||||
LDMIA sp!, {r0-r3} ; Recover r0-r3
|
||||
CPS #SYS_MODE ; Enter SYS mode
|
||||
STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack
|
||||
|
||||
LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr
|
||||
LDR r0, [r1, #0] ; Pickup current thread pointer
|
||||
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
LDR r2, [r0, #144] ; Pickup the VFP enabled flag
|
||||
CMP r2, #0 ; Is the VFP enabled?
|
||||
BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save
|
||||
VMRS r2, FPSCR ; Pickup the FPSCR
|
||||
STR r2, [sp, #-4]! ; Save FPSCR
|
||||
VSTMDB sp!, {D16-D31} ; Save D16-D31
|
||||
VSTMDB sp!, {D0-D15} ; Save D0-D15
|
||||
_tx_skip_irq_vfp_save
|
||||
ENDIF
|
||||
|
||||
MOV r3, #1 ; Build interrupt stack type
|
||||
STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR
|
||||
STR sp, [r0, #8] ; Save stack pointer in thread control
|
||||
; block
|
||||
;
|
||||
; /* Save the remaining time-slice and disable it. */
|
||||
; if (_tx_timer_time_slice)
|
||||
; {
|
||||
;
|
||||
LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address
|
||||
LDR r2, [r3, #0] ; Pickup time-slice
|
||||
CMP r2, #0 ; Is it active?
|
||||
BEQ __tx_thread_dont_save_ts ; No, don't save it
|
||||
;
|
||||
; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
|
||||
; _tx_timer_time_slice = 0;
|
||||
;
|
||||
STR r2, [r0, #24] ; Save thread's time-slice
|
||||
MOV r2, #0 ; Clear value
|
||||
STR r2, [r3, #0] ; Disable global time-slice flag
|
||||
;
|
||||
; }
|
||||
__tx_thread_dont_save_ts
|
||||
;
|
||||
;
|
||||
; /* Clear the current task pointer. */
|
||||
; _tx_thread_current_ptr = TX_NULL;
|
||||
;
|
||||
MOV r0, #0 ; NULL value
|
||||
STR r0, [r1, #0] ; Clear current thread pointer
|
||||
;
|
||||
; /* Return to the scheduler. */
|
||||
; _tx_thread_schedule();
|
||||
;
|
||||
CPS #IRQ_MODE ; Enter IRQ mode
|
||||
MRS r1, SPSR ; Get SPSR
|
||||
ORR r1, r1, #SYS_MODE ; Change to SYS Mode
|
||||
BIC r1, r1, #THUMB_MASK ; Clear thumb bit
|
||||
MSR SPSR_cxsf, r1 ; Put SYS Mode in SPSR
|
||||
LDR lr, =_tx_thread_schedule ; Load scheduler address
|
||||
MOVS pc, lr ; Return to scheduler
|
||||
; }
|
||||
;
|
||||
__tx_thread_idle_system_restore
|
||||
;
|
||||
; /* Just return back to the scheduler! */
|
||||
;
|
||||
LDR lr, =_tx_thread_schedule ; Load scheduler address
|
||||
MOVS pc, lr ; Return to scheduler
|
||||
;}
|
||||
;
|
||||
END
|
||||
|
||||
@@ -0,0 +1,199 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
IMPORT _tx_thread_system_state
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IMPORT __tx_irq_processing_return
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_isr_enter
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_context_save Cortex-A7/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function saves the context of an executing thread in the */
|
||||
;/* beginning of interrupt processing. The function also ensures that */
|
||||
;/* the system stack is used upon return to the calling ISR. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_context_save(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_context_save
|
||||
_tx_thread_context_save
|
||||
;
|
||||
; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
|
||||
; out, we are in IRQ mode, and all registers are intact. */
|
||||
;
|
||||
; /* Check for a nested interrupt condition. */
|
||||
; if (_tx_thread_system_state++)
|
||||
; {
|
||||
;
|
||||
STMDB sp!, {r0-r3} ; Save some working registers
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
CPSID if ; Disable FIQ interrupts
|
||||
ENDIF
|
||||
LDR r3, =_tx_thread_system_state ; Pickup address of system state var
|
||||
LDR r2, [r3, #0] ; Pickup system state
|
||||
CMP r2, #0 ; Is this the first interrupt?
|
||||
BEQ __tx_thread_not_nested_save ; Yes, not a nested context save
|
||||
;
|
||||
; /* Nested interrupt condition. */
|
||||
;
|
||||
ADD r2, r2, #1 ; Increment the interrupt counter
|
||||
STR r2, [r3, #0] ; Store it back in the variable
|
||||
;
|
||||
; /* Save the rest of the scratch registers on the stack and return to the
|
||||
; calling ISR. */
|
||||
;
|
||||
MRS r0, SPSR ; Pickup saved SPSR
|
||||
SUB lr, lr, #4 ; Adjust point of interrupt
|
||||
STMDB sp!, {r0, r10, r12, lr} ; Store other registers
|
||||
;
|
||||
; /* Return to the ISR. */
|
||||
;
|
||||
MOV r10, #0 ; Clear stack limit
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
PUSH {lr} ; Save ISR lr
|
||||
BL _tx_execution_isr_enter ; Call the ISR enter function
|
||||
POP {lr} ; Recover ISR lr
|
||||
ENDIF
|
||||
|
||||
B __tx_irq_processing_return ; Continue IRQ processing
|
||||
;
|
||||
__tx_thread_not_nested_save
|
||||
; }
|
||||
;
|
||||
; /* Otherwise, not nested, check to see if a thread was running. */
|
||||
; else if (_tx_thread_current_ptr)
|
||||
; {
|
||||
;
|
||||
ADD r2, r2, #1 ; Increment the interrupt counter
|
||||
STR r2, [r3, #0] ; Store it back in the variable
|
||||
LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr
|
||||
LDR r0, [r1, #0] ; Pickup current thread pointer
|
||||
CMP r0, #0 ; Is it NULL?
|
||||
BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in
|
||||
; scheduling loop - nothing needs saving!
|
||||
;
|
||||
; /* Save minimal context of interrupted thread. */
|
||||
;
|
||||
MRS r2, SPSR ; Pickup saved SPSR
|
||||
SUB lr, lr, #4 ; Adjust point of interrupt
|
||||
STMDB sp!, {r2, r10, r12, lr} ; Store other registers
|
||||
;
|
||||
; /* Save the current stack pointer in the thread's control block. */
|
||||
; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
|
||||
;
|
||||
; /* Switch to the system stack. */
|
||||
; sp = _tx_thread_system_stack_ptr;
|
||||
;
|
||||
MOV r10, #0 ; Clear stack limit
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
PUSH {lr} ; Save ISR lr
|
||||
BL _tx_execution_isr_enter ; Call the ISR enter function
|
||||
POP {lr} ; Recover ISR lr
|
||||
ENDIF
|
||||
|
||||
B __tx_irq_processing_return ; Continue IRQ processing
|
||||
;
|
||||
; }
|
||||
; else
|
||||
; {
|
||||
;
|
||||
__tx_thread_idle_system_save
|
||||
;
|
||||
; /* Interrupt occurred in the scheduling loop. */
|
||||
;
|
||||
; /* Not much to do here, just adjust the stack pointer, and return to IRQ
|
||||
; processing. */
|
||||
;
|
||||
MOV r10, #0 ; Clear stack limit
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
PUSH {lr} ; Save ISR lr
|
||||
BL _tx_execution_isr_enter ; Call the ISR enter function
|
||||
POP {lr} ; Recover ISR lr
|
||||
ENDIF
|
||||
|
||||
ADD sp, sp, #16 ; Recover saved registers
|
||||
B __tx_irq_processing_return ; Continue IRQ processing
|
||||
;
|
||||
; }
|
||||
;}
|
||||
;
|
||||
END
|
||||
|
||||
@@ -0,0 +1,258 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;#include "tx_timer.h"
|
||||
;
|
||||
;
|
||||
SVC_MODE EQU 0xD3 ; SVC mode
|
||||
FIQ_MODE EQU 0xD1 ; FIQ mode
|
||||
MODE_MASK EQU 0x1F ; Mode mask
|
||||
IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits
|
||||
;
|
||||
;
|
||||
IMPORT _tx_thread_system_state
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IMPORT _tx_thread_system_stack_ptr
|
||||
IMPORT _tx_thread_execute_ptr
|
||||
IMPORT _tx_timer_time_slice
|
||||
IMPORT _tx_thread_schedule
|
||||
IMPORT _tx_thread_preempt_disable
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_isr_exit
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_fiq_context_restore Cortex-A7/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function restores the fiq interrupt context when processing a */
|
||||
;/* nested interrupt. If not, it returns to the interrupt thread if no */
|
||||
;/* preemption is necessary. Otherwise, if preemption is necessary or */
|
||||
;/* if no thread was running, the function returns to the scheduler. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Thread scheduling routine */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* FIQ ISR Interrupt Service Routines */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_fiq_context_restore(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_fiq_context_restore
|
||||
_tx_thread_fiq_context_restore
|
||||
;
|
||||
; /* Lockout interrupts. */
|
||||
;
|
||||
CPSID if ; Disable IRQ and FIQ interrupts
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR exit function to indicate an ISR is complete. */
|
||||
;
|
||||
BL _tx_execution_isr_exit ; Call the ISR exit function
|
||||
ENDIF
|
||||
;
|
||||
; /* Determine if interrupts are nested. */
|
||||
; if (--_tx_thread_system_state)
|
||||
; {
|
||||
;
|
||||
LDR r3, =_tx_thread_system_state ; Pickup address of system state var
|
||||
LDR r2, [r3] ; Pickup system state
|
||||
SUB r2, r2, #1 ; Decrement the counter
|
||||
STR r2, [r3] ; Store the counter
|
||||
CMP r2, #0 ; Was this the first interrupt?
|
||||
BEQ __tx_thread_fiq_not_nested_restore ; If so, not a nested restore
|
||||
;
|
||||
; /* Interrupts are nested. */
|
||||
;
|
||||
; /* Just recover the saved registers and return to the point of
|
||||
; interrupt. */
|
||||
;
|
||||
LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs
|
||||
MSR SPSR_cxsf, r0 ; Put SPSR back
|
||||
LDMIA sp!, {r0-r3} ; Recover r0-r3
|
||||
MOVS pc, lr ; Return to point of interrupt
|
||||
;
|
||||
; }
|
||||
__tx_thread_fiq_not_nested_restore
|
||||
;
|
||||
; /* Determine if a thread was interrupted and no preemption is required. */
|
||||
; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
|
||||
; || (_tx_thread_preempt_disable))
|
||||
; {
|
||||
;
|
||||
LDR r1, [sp] ; Pickup the saved SPSR
|
||||
MOV r2, #MODE_MASK ; Build mask to isolate the interrupted mode
|
||||
AND r1, r1, r2 ; Isolate mode bits
|
||||
CMP r1, #IRQ_MODE_BITS ; Was an interrupt taken in IRQ mode before we
|
||||
; got to context save? */
|
||||
BEQ __tx_thread_fiq_no_preempt_restore ; Yes, just go back to point of interrupt
|
||||
|
||||
|
||||
LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr
|
||||
LDR r0, [r1] ; Pickup actual current thread pointer
|
||||
CMP r0, #0 ; Is it NULL?
|
||||
BEQ __tx_thread_fiq_idle_system_restore ; Yes, idle system was interrupted
|
||||
|
||||
LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address
|
||||
LDR r2, [r3] ; Pickup actual preempt disable flag
|
||||
CMP r2, #0 ; Is it set?
|
||||
BNE __tx_thread_fiq_no_preempt_restore ; Yes, don't preempt this thread
|
||||
LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr
|
||||
LDR r2, [r3] ; Pickup actual execute thread pointer
|
||||
CMP r0, r2 ; Is the same thread highest priority?
|
||||
BNE __tx_thread_fiq_preempt_restore ; No, preemption needs to happen
|
||||
|
||||
|
||||
__tx_thread_fiq_no_preempt_restore
|
||||
;
|
||||
; /* Restore interrupted thread or ISR. */
|
||||
;
|
||||
; /* Pickup the saved stack pointer. */
|
||||
; tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr;
|
||||
;
|
||||
; /* Recover the saved context and return to the point of interrupt. */
|
||||
;
|
||||
LDMIA sp!, {r0, lr} ; Recover SPSR, POI, and scratch regs
|
||||
MSR SPSR_cxsf, r0 ; Put SPSR back
|
||||
LDMIA sp!, {r0-r3} ; Recover r0-r3
|
||||
MOVS pc, lr ; Return to point of interrupt
|
||||
;
|
||||
; }
|
||||
; else
|
||||
; {
|
||||
__tx_thread_fiq_preempt_restore
|
||||
;
|
||||
LDMIA sp!, {r3, lr} ; Recover temporarily saved registers
|
||||
MOV r1, lr ; Save lr (point of interrupt)
|
||||
MOV r2, #SVC_MODE ; Build SVC mode CPSR
|
||||
MSR CPSR_c, r2 ; Enter SVC mode
|
||||
STR r1, [sp, #-4]! ; Save point of interrupt
|
||||
STMDB sp!, {r4-r12, lr} ; Save upper half of registers
|
||||
MOV r4, r3 ; Save SPSR in r4
|
||||
MOV r2, #FIQ_MODE ; Build FIQ mode CPSR
|
||||
MSR CPSR_c, r2 ; Re-enter FIQ mode
|
||||
LDMIA sp!, {r0-r3} ; Recover r0-r3
|
||||
MOV r5, #SVC_MODE ; Build SVC mode CPSR
|
||||
MSR CPSR_c, r5 ; Enter SVC mode
|
||||
STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack
|
||||
|
||||
LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr
|
||||
LDR r0, [r1] ; Pickup current thread pointer
|
||||
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
LDR r2, [r0, #144] ; Pickup the VFP enabled flag
|
||||
CMP r2, #0 ; Is the VFP enabled?
|
||||
BEQ _tx_skip_fiq_vfp_save ; No, skip VFP FIQ save
|
||||
VMRS r2, FPSCR ; Pickup the FPSCR
|
||||
STR r2, [sp, #-4]! ; Save FPSCR
|
||||
VSTMDB sp!, {D16-D31} ; Save D16-D31
|
||||
VSTMDB sp!, {D0-D15} ; Save D0-D15
|
||||
_tx_skip_fiq_vfp_save
|
||||
ENDIF
|
||||
|
||||
MOV r3, #1 ; Build interrupt stack type
|
||||
STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR
|
||||
STR sp, [r0, #8] ; Save stack pointer in thread control
|
||||
; block
|
||||
;
|
||||
; /* Save the remaining time-slice and disable it. */
|
||||
; if (_tx_timer_time_slice)
|
||||
; {
|
||||
;
|
||||
LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address
|
||||
LDR r2, [r3] ; Pickup time-slice
|
||||
CMP r2, #0 ; Is it active?
|
||||
BEQ __tx_thread_fiq_dont_save_ts ; No, don't save it
|
||||
;
|
||||
; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
|
||||
; _tx_timer_time_slice = 0;
|
||||
;
|
||||
STR r2, [r0, #24] ; Save thread's time-slice
|
||||
MOV r2, #0 ; Clear value
|
||||
STR r2, [r3] ; Disable global time-slice flag
|
||||
;
|
||||
; }
|
||||
__tx_thread_fiq_dont_save_ts
|
||||
;
|
||||
;
|
||||
; /* Clear the current task pointer. */
|
||||
; _tx_thread_current_ptr = TX_NULL;
|
||||
;
|
||||
MOV r0, #0 ; NULL value
|
||||
STR r0, [r1] ; Clear current thread pointer
|
||||
;
|
||||
; /* Return to the scheduler. */
|
||||
; _tx_thread_schedule();
|
||||
;
|
||||
B _tx_thread_schedule ; Return to scheduler
|
||||
; }
|
||||
;
|
||||
__tx_thread_fiq_idle_system_restore
|
||||
;
|
||||
; /* Just return back to the scheduler! */
|
||||
;
|
||||
ADD sp, sp, #24 ; Recover FIQ stack space
|
||||
MOV r3, #SVC_MODE ; Build SVC mode CPSR
|
||||
MSR CPSR_c, r3 ; Enter SVC mode
|
||||
B _tx_thread_schedule ; Return to scheduler
|
||||
;
|
||||
;}
|
||||
;
|
||||
END
|
||||
|
||||
@@ -0,0 +1,203 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
IMPORT _tx_thread_system_state
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IMPORT __tx_fiq_processing_return
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_isr_enter
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_fiq_context_save Cortex-A7/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function saves the context of an executing thread in the */
|
||||
;/* beginning of interrupt processing. The function also ensures that */
|
||||
;/* the system stack is used upon return to the calling ISR. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
; VOID _tx_thread_fiq_context_save(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_fiq_context_save
|
||||
_tx_thread_fiq_context_save
|
||||
;
|
||||
; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
|
||||
; out, we are in IRQ mode, and all registers are intact. */
|
||||
;
|
||||
; /* Check for a nested interrupt condition. */
|
||||
; if (_tx_thread_system_state++)
|
||||
; {
|
||||
;
|
||||
STMDB sp!, {r0-r3} ; Save some working registers
|
||||
LDR r3, =_tx_thread_system_state ; Pickup address of system state var
|
||||
LDR r2, [r3] ; Pickup system state
|
||||
CMP r2, #0 ; Is this the first interrupt?
|
||||
BEQ __tx_thread_fiq_not_nested_save ; Yes, not a nested context save
|
||||
;
|
||||
; /* Nested interrupt condition. */
|
||||
;
|
||||
ADD r2, r2, #1 ; Increment the interrupt counter
|
||||
STR r2, [r3] ; Store it back in the variable
|
||||
;
|
||||
; /* Save the rest of the scratch registers on the stack and return to the
|
||||
; calling ISR. */
|
||||
;
|
||||
MRS r0, SPSR ; Pickup saved SPSR
|
||||
SUB lr, lr, #4 ; Adjust point of interrupt
|
||||
STMDB sp!, {r0, r10, r12, lr} ; Store other registers
|
||||
;
|
||||
; /* Return to the ISR. */
|
||||
;
|
||||
MOV r10, #0 ; Clear stack limit
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
PUSH {lr} ; Save ISR lr
|
||||
BL _tx_execution_isr_enter ; Call the ISR enter function
|
||||
POP {lr} ; Recover ISR lr
|
||||
ENDIF
|
||||
|
||||
B __tx_fiq_processing_return ; Continue FIQ processing
|
||||
;
|
||||
__tx_thread_fiq_not_nested_save
|
||||
; }
|
||||
;
|
||||
; /* Otherwise, not nested, check to see if a thread was running. */
|
||||
; else if (_tx_thread_current_ptr)
|
||||
; {
|
||||
;
|
||||
ADD r2, r2, #1 ; Increment the interrupt counter
|
||||
STR r2, [r3] ; Store it back in the variable
|
||||
LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr
|
||||
LDR r0, [r1] ; Pickup current thread pointer
|
||||
CMP r0, #0 ; Is it NULL?
|
||||
BEQ __tx_thread_fiq_idle_system_save ; If so, interrupt occurred in
|
||||
; ; scheduling loop - nothing needs saving!
|
||||
;
|
||||
; /* Save minimal context of interrupted thread. */
|
||||
;
|
||||
MRS r2, SPSR ; Pickup saved SPSR
|
||||
SUB lr, lr, #4 ; Adjust point of interrupt
|
||||
STMDB sp!, {r2, lr} ; Store other registers, Note that we don't
|
||||
; ; need to save sl and ip since FIQ has
|
||||
; ; copies of these registers. Nested
|
||||
; ; interrupt processing does need to save
|
||||
; ; these registers.
|
||||
;
|
||||
; /* Save the current stack pointer in the thread's control block. */
|
||||
; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
|
||||
;
|
||||
; /* Switch to the system stack. */
|
||||
; sp = _tx_thread_system_stack_ptr;
|
||||
;
|
||||
MOV r10, #0 ; Clear stack limit
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
PUSH {lr} ; Save ISR lr
|
||||
BL _tx_execution_isr_enter ; Call the ISR enter function
|
||||
POP {lr} ; Recover ISR lr
|
||||
ENDIF
|
||||
|
||||
B __tx_fiq_processing_return ; Continue FIQ processing
|
||||
;
|
||||
; }
|
||||
; else
|
||||
; {
|
||||
;
|
||||
__tx_thread_fiq_idle_system_save
|
||||
;
|
||||
; /* Interrupt occurred in the scheduling loop. */
|
||||
;
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
PUSH {lr} ; Save ISR lr
|
||||
BL _tx_execution_isr_enter ; Call the ISR enter function
|
||||
POP {lr} ; Recover ISR lr
|
||||
ENDIF
|
||||
;
|
||||
; /* Not much to do here, save the current SPSR and LR for possible
|
||||
; use in IRQ interrupted in idle system conditions, and return to
|
||||
; FIQ interrupt processing. */
|
||||
;
|
||||
MRS r0, SPSR ; Pickup saved SPSR
|
||||
SUB lr, lr, #4 ; Adjust point of interrupt
|
||||
STMDB sp!, {r0, lr} ; Store other registers that will get used
|
||||
; ; or stripped off the stack in context
|
||||
; ; restore
|
||||
B __tx_fiq_processing_return ; Continue FIQ processing
|
||||
;
|
||||
; }
|
||||
;}
|
||||
;
|
||||
END
|
||||
|
||||
@@ -0,0 +1,111 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts
|
||||
ELSE
|
||||
DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts
|
||||
ENDIF
|
||||
MODE_MASK EQU 0x1F ; Mode mask
|
||||
FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_fiq_nesting_end Cortex-A7/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is called by the application from FIQ mode after */
|
||||
;/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */
|
||||
;/* processing from system mode back to FIQ mode prior to the ISR */
|
||||
;/* calling _tx_thread_fiq_context_restore. Note that this function */
|
||||
;/* assumes the system stack pointer is in the same position after */
|
||||
;/* nesting start function was called. */
|
||||
;/* */
|
||||
;/* This function assumes that the system mode stack pointer was setup */
|
||||
;/* during low-level initialization (tx_initialize_low_level.s). */
|
||||
;/* */
|
||||
;/* This function returns with FIQ interrupts disabled. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_fiq_nesting_end(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_fiq_nesting_end
|
||||
_tx_thread_fiq_nesting_end
|
||||
MOV r3,lr ; Save ISR return address
|
||||
MRS r0, CPSR ; Pickup the CPSR
|
||||
ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value
|
||||
MSR CPSR_c, r0 ; Disable interrupts
|
||||
LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for
|
||||
; 8-byte alignment logic)
|
||||
BIC r0, r0, #MODE_MASK ; Clear mode bits
|
||||
ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR
|
||||
MSR CPSR_c, r0 ; Re-enter IRQ mode
|
||||
IF {INTER} = {TRUE}
|
||||
BX r3 ; Return to caller
|
||||
ELSE
|
||||
MOV pc, r3 ; Return to caller
|
||||
ENDIF
|
||||
;}
|
||||
;
|
||||
END
|
||||
|
||||
@@ -0,0 +1,104 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
FIQ_DISABLE EQU 0x40 ; FIQ disable bit
|
||||
MODE_MASK EQU 0x1F ; Mode mask
|
||||
SYS_MODE_BITS EQU 0x1F ; System mode bits
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_fiq_nesting_start Cortex-A7/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is called by the application from FIQ mode after */
|
||||
;/* _tx_thread_fiq_context_save has been called and switches the FIQ */
|
||||
;/* processing to the system mode so nested FIQ interrupt processing */
|
||||
;/* is possible (system mode has its own "lr" register). Note that */
|
||||
;/* this function assumes that the system mode stack pointer was setup */
|
||||
;/* during low-level initialization (tx_initialize_low_level.s). */
|
||||
;/* */
|
||||
;/* This function returns with FIQ interrupts enabled. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_fiq_nesting_start(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_fiq_nesting_start
|
||||
_tx_thread_fiq_nesting_start
|
||||
MOV r3,lr ; Save ISR return address
|
||||
MRS r0, CPSR ; Pickup the CPSR
|
||||
BIC r0, r0, #MODE_MASK ; Clear the mode bits
|
||||
ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR
|
||||
MSR CPSR_c, r0 ; Enter system mode
|
||||
STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack
|
||||
; and push r1 just to keep 8-byte alignment
|
||||
BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR
|
||||
MSR CPSR_c, r0 ; Enter system mode
|
||||
IF {INTER} = {TRUE}
|
||||
BX r3 ; Return to caller
|
||||
ELSE
|
||||
MOV pc, r3 ; Return to caller
|
||||
ENDIF
|
||||
;}
|
||||
;
|
||||
END
|
||||
|
||||
@@ -0,0 +1,102 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
INT_MASK EQU 0xC0 ; Interrupt bit mask
|
||||
ELSE
|
||||
INT_MASK EQU 0x80 ; Interrupt bit mask
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_interrupt_control Cortex-A7/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for changing the interrupt lockout */
|
||||
;/* posture of the system. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* new_posture New interrupt lockout posture */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* old_posture Old interrupt lockout posture */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;UINT _tx_thread_interrupt_control(UINT new_posture)
|
||||
;{
|
||||
EXPORT _tx_thread_interrupt_control
|
||||
_tx_thread_interrupt_control
|
||||
;
|
||||
; /* Pickup current interrupt lockout posture. */
|
||||
;
|
||||
MRS r3, CPSR ; Pickup current CPSR
|
||||
BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
|
||||
ORR r1, r1, r0 ; Or-in new interrupt lockout bits
|
||||
;
|
||||
; /* Apply the new interrupt posture. */
|
||||
;
|
||||
MSR CPSR_c, r1 ; Setup new CPSR
|
||||
AND r0, r3, #INT_MASK ; Return previous interrupt mask
|
||||
IF {INTER} = {TRUE}
|
||||
BX lr ; Return to caller
|
||||
ELSE
|
||||
MOV pc, lr ; Return to caller
|
||||
ENDIF
|
||||
;
|
||||
;}
|
||||
;
|
||||
END
|
||||
|
||||
@@ -0,0 +1,95 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_interrupt_disable Cortex-A7/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for disabling interrupts */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* old_posture Old interrupt lockout posture */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;UINT _tx_thread_interrupt_disable(void)
|
||||
;{
|
||||
EXPORT _tx_thread_interrupt_disable
|
||||
_tx_thread_interrupt_disable
|
||||
;
|
||||
; /* Pickup current interrupt lockout posture. */
|
||||
;
|
||||
MRS r0, CPSR ; Pickup current CPSR
|
||||
;
|
||||
; /* Mask interrupts. */
|
||||
;
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
CPSID if ; Disable IRQ and FIQ
|
||||
ELSE
|
||||
CPSID i ; Disable IRQ
|
||||
ENDIF
|
||||
|
||||
IF {INTER} = {TRUE}
|
||||
BX lr ; Return to caller
|
||||
ELSE
|
||||
MOV pc, lr ; Return to caller
|
||||
ENDIF
|
||||
;}
|
||||
;
|
||||
END
|
||||
|
||||
@@ -0,0 +1,87 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_interrupt_restore Cortex-A7/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for restoring interrupts to the state */
|
||||
;/* returned by a previous _tx_thread_interrupt_disable call. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* old_posture Old interrupt lockout posture */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;UINT _tx_thread_interrupt_restore(UINT old_posture)
|
||||
;{
|
||||
EXPORT _tx_thread_interrupt_restore
|
||||
_tx_thread_interrupt_restore
|
||||
;
|
||||
; /* Apply the new interrupt posture. */
|
||||
;
|
||||
MSR CPSR_c, r0 ; Setup new CPSR
|
||||
IF {INTER} = {TRUE}
|
||||
BX lr ; Return to caller
|
||||
ELSE
|
||||
MOV pc, lr ; Return to caller
|
||||
ENDIF
|
||||
;}
|
||||
;
|
||||
END
|
||||
|
||||
@@ -0,0 +1,110 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts
|
||||
ELSE
|
||||
DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts
|
||||
ENDIF
|
||||
MODE_MASK EQU 0x1F ; Mode mask
|
||||
IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_irq_nesting_end Cortex-A7/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is called by the application from IRQ mode after */
|
||||
;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */
|
||||
;/* processing from system mode back to IRQ mode prior to the ISR */
|
||||
;/* calling _tx_thread_context_restore. Note that this function */
|
||||
;/* assumes the system stack pointer is in the same position after */
|
||||
;/* nesting start function was called. */
|
||||
;/* */
|
||||
;/* This function assumes that the system mode stack pointer was setup */
|
||||
;/* during low-level initialization (tx_initialize_low_level.s). */
|
||||
;/* */
|
||||
;/* This function returns with IRQ interrupts disabled. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_irq_nesting_end(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_irq_nesting_end
|
||||
_tx_thread_irq_nesting_end
|
||||
MOV r3,lr ; Save ISR return address
|
||||
MRS r0, CPSR ; Pickup the CPSR
|
||||
ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value
|
||||
MSR CPSR_c, r0 ; Disable interrupts
|
||||
LDMIA sp!, {r1, lr} ; Pickup saved lr (and r1 throw-away for
|
||||
; 8-byte alignment logic)
|
||||
BIC r0, r0, #MODE_MASK ; Clear mode bits
|
||||
ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR
|
||||
MSR CPSR_c, r0 ; Re-enter IRQ mode
|
||||
IF {INTER} = {TRUE}
|
||||
BX r3 ; Return to caller
|
||||
ELSE
|
||||
MOV pc, r3 ; Return to caller
|
||||
ENDIF
|
||||
;}
|
||||
END
|
||||
|
||||
@@ -0,0 +1,104 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
IRQ_DISABLE EQU 0x80 ; IRQ disable bit
|
||||
MODE_MASK EQU 0x1F ; Mode mask
|
||||
SYS_MODE_BITS EQU 0x1F ; System mode bits
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_irq_nesting_start Cortex-A7/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is called by the application from IRQ mode after */
|
||||
;/* _tx_thread_context_save has been called and switches the IRQ */
|
||||
;/* processing to the system mode so nested IRQ interrupt processing */
|
||||
;/* is possible (system mode has its own "lr" register). Note that */
|
||||
;/* this function assumes that the system mode stack pointer was setup */
|
||||
;/* during low-level initialization (tx_initialize_low_level.s). */
|
||||
;/* */
|
||||
;/* This function returns with IRQ interrupts enabled. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_irq_nesting_start(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_irq_nesting_start
|
||||
_tx_thread_irq_nesting_start
|
||||
MOV r3,lr ; Save ISR return address
|
||||
MRS r0, CPSR ; Pickup the CPSR
|
||||
BIC r0, r0, #MODE_MASK ; Clear the mode bits
|
||||
ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR
|
||||
MSR CPSR_c, r0 ; Enter system mode
|
||||
STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack
|
||||
; and push r1 just to keep 8-byte alignment
|
||||
BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR
|
||||
MSR CPSR_c, r0 ; Enter system mode
|
||||
IF {INTER} = {TRUE}
|
||||
BX r3 ; Return to caller
|
||||
ELSE
|
||||
MOV pc, r3 ; Return to caller
|
||||
ENDIF
|
||||
;}
|
||||
;
|
||||
END
|
||||
|
||||
@@ -0,0 +1,458 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;#include "tx_timer.h"
|
||||
;
|
||||
;
|
||||
IMPORT _tx_thread_execute_ptr
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IMPORT _tx_timer_time_slice
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_thread_enter
|
||||
ENDIF
|
||||
|
||||
IRQ_MODE EQU 0xD2 ; IRQ mode
|
||||
USR_MODE EQU 0x10 ; USR mode
|
||||
SVC_MODE EQU 0x13 ; SVC mode
|
||||
SYS_MODE EQU 0x1F ; SYS mode
|
||||
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask
|
||||
ELSE
|
||||
ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask
|
||||
ENDIF
|
||||
|
||||
MODE_MASK EQU 0x1F ; Mode mask
|
||||
THUMB_MASK EQU 0x20 ; Thumb bit mask
|
||||
|
||||
IMPORT _txm_system_mode_enter
|
||||
IMPORT _txm_system_mode_exit
|
||||
IMPORT _txm_ttbr1_page_table
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Cortex-A7/MMU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function waits for a thread control block pointer to appear in */
|
||||
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
|
||||
;/* in the variable, the corresponding thread is resumed. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
;/* _tx_thread_system_return Return to system from thread */
|
||||
;/* _tx_thread_context_restore Restore thread's context */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_schedule(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_schedule
|
||||
_tx_thread_schedule
|
||||
|
||||
; Enter the scheduler.
|
||||
SVC 0
|
||||
|
||||
; We should never get here - ever!
|
||||
_tx_scheduler_fault__
|
||||
B _tx_scheduler_fault__
|
||||
;}
|
||||
; ****************************************************************************
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; SWI_Handler
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
EXPORT __tx_swi_interrupt ; Software interrupt handler
|
||||
__tx_swi_interrupt
|
||||
|
||||
STMFD sp!, {r0-r3, r12, lr} ; Store the registers
|
||||
MOV r1, sp ; Set pointer to parameters
|
||||
MRS r0, spsr ; Get spsr
|
||||
STMFD sp!, {r0, r3} ; Store spsr onto stack and another
|
||||
; register to maintain 8-byte-aligned stack
|
||||
TST r0, #THUMB_MASK ; Occurred in Thumb state?
|
||||
LDRNEH r0, [lr,#-2] ; Yes: Load halfword and...
|
||||
BICNE r0, r0, #0xFF00 ; ...extract comment field
|
||||
LDREQ r0, [lr,#-4] ; No: Load word and...
|
||||
BICEQ r0, r0, #0xFF000000 ; ...extract comment field
|
||||
|
||||
; r0 now contains SVC number
|
||||
; r1 now contains pointer to stacked registers
|
||||
|
||||
;
|
||||
; The service call is handled here
|
||||
;
|
||||
|
||||
CMP r0, #0 ; Is it a schedule request?
|
||||
BEQ _tx_handler_svc_schedule ; Yes, go there
|
||||
|
||||
CMP r0, #1 ; Is it a system mode enter request?
|
||||
BEQ _tx_handler_svc_super_enter ; Yes, go there
|
||||
|
||||
CMP r0, #2 ; Is it a system mode exit request?
|
||||
BEQ _tx_handler_svc_super_exit ; Yes, go there
|
||||
|
||||
LDR r2, =0x123456
|
||||
CMP r0, r2 ; Is it an ARM request?
|
||||
BEQ _tx_handler_svc_arm ; Yes, go there
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; Unknown SVC argument
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; Unrecognized service call
|
||||
_tx_handler_svc_unrecognized
|
||||
|
||||
_tx_handler_svc_unrecognized_loop ; We should never get here
|
||||
B _tx_handler_svc_unrecognized_loop
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; SVC 1
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; At this point we have an SVC 1, which means we are entering the system mode to service a kernel call
|
||||
_tx_handler_svc_super_enter
|
||||
; Make sure that we have been called from the system mode enter location (security)
|
||||
LDR r2, =_txm_system_mode_enter ; Load the address of the known call point
|
||||
SUB r1, lr, #4 ; Calculate the address of the actual call
|
||||
CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry?
|
||||
BNE _tx_handler_svc_unrecognized ; Return to where we came
|
||||
|
||||
; Clear the user mode flag in the thread structure
|
||||
LDR r1, =_tx_thread_current_ptr ; Load the current thread pointer address
|
||||
LDR r2, [r1] ; Load current thread location from the pointer (pointer indirection)
|
||||
MOV r1, #0 ; Load the new user mode flag value (user mode flag clear -> not user mode -> system)
|
||||
STR r1, [r2, #0x9C] ; Clear tx_thread_module_current_user_mode for thread
|
||||
|
||||
; Now we enter the system mode and return
|
||||
LDMFD sp!, {r0, r3} ; Get spsr from the stack
|
||||
BIC r0, r0, #MODE_MASK ; clear mode field
|
||||
ORR r0, r0, #SYS_MODE ; system mode code
|
||||
MSR SPSR_cxsf, r0 ; Restore the spsr
|
||||
|
||||
LDR r1, [r2, #0xA8] ; Load the module kernel stack pointer
|
||||
CPS #SYS_MODE ; Switch to SYS mode
|
||||
MOV r3, sp ; Grab thread stack pointer
|
||||
MOV sp, r1 ; Set SP to kernel stack pointer
|
||||
CPS #SVC_MODE ; Switch back to SVC mode
|
||||
STR r3, [r2, #0xB0] ; Save thread stack pointer
|
||||
IF :DEF:TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
|
||||
ELSE
|
||||
LDR r3, [r2, #0xAC] ; Load the module kernel stack size
|
||||
STR r3, [r2, #20] ; Set stack size
|
||||
LDRD r0, r1, [r2, #0xA4] ; Load the module kernel stack start and end
|
||||
STRD r0, r1, [r2, #0x0C] ; Set stack start and end
|
||||
ENDIF
|
||||
|
||||
LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; SVC 2
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; At this point we have an SVC 2, which means we are exiting the system mode after servicing a kernel call
|
||||
_tx_handler_svc_super_exit
|
||||
; Make sure that we have been called from the system mode exit location (security)
|
||||
LDR r2, =_txm_system_mode_exit ; Load the address of the known call point
|
||||
SUB r1, lr, #4 ; Calculate the address of the actual call
|
||||
CMP r1, r2 ; Did we come from txm_module_manager_user_mode_entry?
|
||||
BNE _tx_handler_svc_unrecognized ; Return to where we came
|
||||
|
||||
; Set the user mode flag into the thread structure
|
||||
LDR r1, =_tx_thread_current_ptr ; Load the current thread pointer address
|
||||
LDR r2, [r1] ; Load the current thread location from the pointer (pointer indirection)
|
||||
MOV r1, #1 ; Load the new user mode flag value (user mode enabled -> not system anymore)
|
||||
STR r1, [r2, #0x9C] ; Set tx_thread_module_current_user_mode for thread
|
||||
|
||||
; Now we enter user mode (exit the system mode) and return
|
||||
LDMFD sp!, {r0, r3} ; Get spsr from the stack
|
||||
BIC r0, r0, #MODE_MASK ; clear mode field
|
||||
ORR r0, r0, #USR_MODE ; user mode code
|
||||
MSR SPSR_cxsf, r0 ; Restore the spsr
|
||||
|
||||
LDR r1, [r2, #0xB0] ; Load the module thread stack pointer
|
||||
CPS #SYS_MODE ; Switch to SYS mode
|
||||
MOV r3, sp ; Grab kernel stack pointer
|
||||
MOV sp, r1 ; Set SP back to thread stack pointer
|
||||
CPS #SVC_MODE ; Switch back to SVC mode
|
||||
IF :DEF:TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
|
||||
ELSE
|
||||
LDR r3, [r2, #0xBC] ; Load the module thread stack size
|
||||
STR r3, [r2, #20] ; Set stack size
|
||||
LDRD r0, r1, [r2, #0xB4] ; Load the module thread stack start and end
|
||||
STRD r0, r1, [r2, #0x0C] ; Set stack start and end
|
||||
ENDIF
|
||||
LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; ARM Semihosting
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
_tx_handler_svc_arm
|
||||
|
||||
; *** TODO: handle semihosting requests or ARM angel requests ***
|
||||
|
||||
; just return
|
||||
LDMFD sp!, {r0, r3} ; Get spsr from the stack
|
||||
MSR SPSR_cxsf, r0 ; Restore the spsr
|
||||
LDMFD sp!, {r0-r3, r12, pc}^ ; Restore the registers and return
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; SVC 0
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; At this point we have an SVC 0: enter the scheduler.
|
||||
_tx_handler_svc_schedule
|
||||
|
||||
LDMFD sp!, {r0, r3} ; Get spsr from stack
|
||||
MSR SPSR_cxsf, r0 ; Restore spsr
|
||||
LDMFD sp!, {r0-r3, r12, lr} ; Restore the registers
|
||||
|
||||
; This code waits for a thread control block pointer to appear in
|
||||
; the _tx_thread_execute_ptr variable. Once a thread pointer appears
|
||||
; in the variable, the corresponding thread is resumed.
|
||||
;
|
||||
; /* Enable interrupts. */
|
||||
;
|
||||
MRS r2, CPSR ; Pickup CPSR
|
||||
BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
|
||||
MSR CPSR_cxsf, r0 ; Enable interrupts
|
||||
|
||||
;
|
||||
; /* Wait for a thread to execute. */
|
||||
; do
|
||||
; {
|
||||
LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr
|
||||
__tx_thread_schedule_loop
|
||||
LDR r0, [r1, #0] ; Pickup next thread to execute
|
||||
CMP r0, #0 ; Is it NULL?
|
||||
BEQ __tx_thread_schedule_loop ; If so, keep looking for a thread
|
||||
; }
|
||||
; while(_tx_thread_execute_ptr == TX_NULL);
|
||||
|
||||
; Yes! We have a thread to execute. Lockout interrupts and transfer control to it.
|
||||
MSR CPSR_cxsf, r2 ; Disable interrupts
|
||||
;
|
||||
; /* Setup the current thread pointer. */
|
||||
; _tx_thread_current_ptr = _tx_thread_execute_ptr;
|
||||
;
|
||||
LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread
|
||||
STR r0, [r1, #0] ; Setup current thread pointer
|
||||
;
|
||||
; /* Increment the run count for this thread. */
|
||||
; _tx_thread_current_ptr -> tx_thread_run_count++;
|
||||
;
|
||||
LDR r2, [r0, #4] ; Pickup run counter
|
||||
LDR r3, [r0, #24] ; Pickup time-slice for this thread
|
||||
ADD r2, r2, #1 ; Increment thread run-counter
|
||||
STR r2, [r0, #4] ; Store the new run counter
|
||||
;
|
||||
; /* Setup time-slice, if present. */
|
||||
; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice;
|
||||
;
|
||||
LDR r2, =_tx_timer_time_slice ; Pickup address of time slice variable
|
||||
STR r3, [r2, #0] ; Setup time-slice
|
||||
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread entry function to indicate the thread is executing. */
|
||||
;
|
||||
MOV r5, r0 ; Save r0
|
||||
BL _tx_execution_thread_enter ; Call the thread execution enter function
|
||||
MOV r0, r5 ; Restore r0
|
||||
ENDIF
|
||||
|
||||
; Determine if an interrupt frame or a synchronous task suspension frame is present.
|
||||
CPS #SYS_MODE ; Enter SYS mode
|
||||
LDR sp, [r0, #8] ; Switch to thread stack pointer
|
||||
LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR
|
||||
CPS #SVC_MODE ; Enter SVC mode
|
||||
|
||||
; **************************************************************************
|
||||
; Set up MMU for module.
|
||||
LDR r2, [r0, #0x94] ; Pickup the module pointer
|
||||
CMP r2, #0 ; Valid module pointer?
|
||||
LDRNE r2, [r2, #0x64] ; Load ASID
|
||||
; Otherwise, ASID 0 & master table will be loaded.
|
||||
; Is ASID already loaded?
|
||||
MRC p15, 0, r1, c13, c0, 1 ; Read CONTEXTIDR into r1
|
||||
CMP r1, r2
|
||||
; If so, skip MMU setup.
|
||||
BEQ _tx_skip_mmu_update
|
||||
; New ASID & TTBR values to load
|
||||
DSB
|
||||
ISB
|
||||
; Load new ASID and TTBR
|
||||
LDR r1, =_txm_ttbr1_page_table ; Load master TTBR
|
||||
ORR r1, r1, #0x48 ; OR it with #TTBR0_ATTRIBUTES
|
||||
MCR p15, 0, r1, c2, c0, 0 ; Change TTBR to master
|
||||
ISB
|
||||
DSB
|
||||
MCR p15, 0, r2, c13, c0, 1 ; Change ASID to new value
|
||||
ISB
|
||||
; Change TTBR to new value
|
||||
MOV r3, #14
|
||||
ADD r1, r1, r2, LSL r3
|
||||
MCR p15, 0, r1, c2, c0, 0 ; Change TTBR to new value
|
||||
|
||||
; refresh TLB
|
||||
MOV r2, #0
|
||||
DSB
|
||||
MCR p15, 0, r2, c8, c7, 0 ; Invalidate entire unified TLB
|
||||
MCR p15, 0, r2, c7, c5, 0 ; Invalidate all instruction caches to PoU
|
||||
MCR p15, 0, r2, c7, c5, 6 ; Invalidate branch predictor
|
||||
DSB
|
||||
ISB
|
||||
|
||||
;test address translation
|
||||
;mcr p15, 0, r0, c7, c8, 0
|
||||
|
||||
_tx_skip_mmu_update
|
||||
; **************************************************************************
|
||||
|
||||
CMP r4, #0 ; Check for synchronous context switch
|
||||
BEQ _tx_solicited_return
|
||||
|
||||
MSR SPSR_cxsf, r5 ; Setup SPSR for return
|
||||
LDR r1, [r0, #8] ; Get thread SP
|
||||
LDR lr, [r1, #0x40] ; Get thread PC
|
||||
CPS #SYS_MODE ; Enter SYS mode
|
||||
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
LDR r2, [r0, #144] ; Pickup the VFP enabled flag
|
||||
CMP r2, #0 ; Is the VFP enabled?
|
||||
BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore
|
||||
VLDMIA sp!, {D0-D15} ; Recover D0-D15
|
||||
VLDMIA sp!, {D16-D31} ; Recover D16-D31
|
||||
LDR r4, [sp], #4 ; Pickup FPSCR
|
||||
VMSR FPSCR, r4 ; Restore FPSCR
|
||||
CPS #SVC_MODE ; Enter SVC mode
|
||||
LDR lr, [r1, #0x144] ; Get thread PC
|
||||
CPS #SYS_MODE ; Enter SYS mode
|
||||
_tx_skip_interrupt_vfp_restore
|
||||
ENDIF
|
||||
|
||||
LDMIA sp!, {r0-r12, lr} ; Restore registers
|
||||
ADD sp, sp, #4 ; Fix stack pointer
|
||||
CPS #SVC_MODE ; Enter SVC mode
|
||||
SUBS pc, lr, #0 ; Return to point of thread interrupt
|
||||
|
||||
_tx_solicited_return
|
||||
MOV r2, r5 ; Move CPSR to scratch register
|
||||
CPS #SYS_MODE ; Enter SYS mode
|
||||
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
LDR r1, [r0, #144] ; Pickup the VFP enabled flag
|
||||
CMP r1, #0 ; Is the VFP enabled?
|
||||
BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore
|
||||
VLDMIA sp!, {D8-D15} ; Recover D8-D15
|
||||
VLDMIA sp!, {D16-D31} ; Recover D16-D31
|
||||
LDR r4, [sp], #4 ; Pickup FPSCR
|
||||
VMSR FPSCR, r4 ; Restore FPSCR
|
||||
_tx_skip_solicited_vfp_restore
|
||||
ENDIF
|
||||
|
||||
LDMIA sp!, {r4-r11, lr} ; Restore registers
|
||||
MOV r1, lr ; Copy lr to r1 to preserve across mode change
|
||||
CPS #SVC_MODE ; Enter SVC mode
|
||||
MSR SPSR_cxsf, r2 ; Recover CPSR
|
||||
MOV lr, r1 ; Deprecated return via r1, so copy r1 to lr and return via lr
|
||||
SUBS pc, lr, #0 ; Return to thread synchronously
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; End __tx_handler_swi
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
EXPORT tx_thread_vfp_enable
|
||||
tx_thread_vfp_enable
|
||||
MRS r2, CPSR ; Pickup the CPSR
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
CPSID if ; Disable IRQ and FIQ interrupts
|
||||
ELSE
|
||||
CPSID i ; Disable IRQ interrupts
|
||||
ENDIF
|
||||
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r1, [r0] ; Pickup current thread pointer
|
||||
CMP r1, #0 ; Check for NULL thread pointer
|
||||
BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable
|
||||
MOV r0, #1 ; Build enable value
|
||||
STR r0, [r1, #144] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
|
||||
__tx_no_thread_to_enable
|
||||
MSR CPSR_cxsf, r2 ; Recover CPSR
|
||||
BX LR ; Return to caller
|
||||
|
||||
EXPORT tx_thread_vfp_disable
|
||||
tx_thread_vfp_disable
|
||||
MRS r2, CPSR ; Pickup the CPSR
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
CPSID if ; Disable IRQ and FIQ interrupts
|
||||
ELSE
|
||||
CPSID i ; Disable IRQ interrupts
|
||||
ENDIF
|
||||
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r1, [r0] ; Pickup current thread pointer
|
||||
CMP r1, #0 ; Check for NULL thread pointer
|
||||
BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable
|
||||
MOV r0, #0 ; Build disable value
|
||||
STR r0, [r1, #144] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD)
|
||||
__tx_no_thread_to_disable
|
||||
MSR CPSR_cxsf, r2 ; Recover CPSR
|
||||
BX LR ; Return to caller
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
@@ -0,0 +1,166 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
SVC_MODE EQU 0x13 ; SVC mode
|
||||
SYS_MODE EQU 0x1F ; SYS mode
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled
|
||||
ELSE
|
||||
CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled
|
||||
ENDIF
|
||||
|
||||
THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR
|
||||
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_stack_build Cortex-A7/MMU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function builds a stack frame on the supplied thread's stack. */
|
||||
;/* The stack frame results in a fake interrupt return to the supplied */
|
||||
;/* function pointer. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* thread_ptr Pointer to thread control blk */
|
||||
;/* function_ptr Pointer to return function */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_thread_create Create thread service */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
|
||||
;{
|
||||
EXPORT _tx_thread_stack_build
|
||||
_tx_thread_stack_build
|
||||
;
|
||||
;
|
||||
; /* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
; on the Cortex-A7 should look like the following after it is built:
|
||||
;
|
||||
; Stack Top: 1 Interrupt stack frame type
|
||||
; CPSR Initial value for CPSR
|
||||
; a1 (r0) Initial value for a1
|
||||
; a2 (r1) Initial value for a2
|
||||
; a3 (r2) Initial value for a3
|
||||
; a4 (r3) Initial value for a4
|
||||
; v1 (r4) Initial value for v1
|
||||
; v2 (r5) Initial value for v2
|
||||
; v3 (r6) Initial value for v3
|
||||
; v4 (r7) Initial value for v4
|
||||
; v5 (r8) Initial value for v5
|
||||
; sb (r9) Initial value for sb
|
||||
; sl (r10) Initial value for sl
|
||||
; fp (r11) Initial value for fp
|
||||
; ip (r12) Initial value for ip
|
||||
; lr (r14) Initial value for lr
|
||||
; pc (r15) Initial value for pc
|
||||
; 0 For stack backtracing
|
||||
;
|
||||
; Stack Bottom: (higher memory address) */
|
||||
;
|
||||
LDR r2, [r0, #16] ; Pickup end of stack area
|
||||
BIC r2, r2, #7 ; Ensure 8-byte alignment
|
||||
SUB r2, r2, #76 ; Allocate space for the stack frame
|
||||
;
|
||||
; /* Actually build the stack frame. */
|
||||
;
|
||||
MOV r3, #1 ; Build interrupt stack type
|
||||
STR r3, [r2, #0] ; Store stack type
|
||||
MOV r3, #0 ; Build initial register value
|
||||
STR r3, [r2, #8] ; Store initial r0
|
||||
STR r3, [r2, #12] ; Store initial r1
|
||||
STR r3, [r2, #16] ; Store initial r2
|
||||
STR r3, [r2, #20] ; Store initial r3
|
||||
STR r3, [r2, #24] ; Store initial r4
|
||||
STR r3, [r2, #28] ; Store initial r5
|
||||
STR r3, [r2, #32] ; Store initial r6
|
||||
STR r3, [r2, #36] ; Store initial r7
|
||||
STR r3, [r2, #40] ; Store initial r8
|
||||
STR r3, [r2, #44] ; Store initial r9
|
||||
LDR r3, [r0, #12] ; Pickup stack starting address
|
||||
STR r3, [r2, #48] ; Store initial r10 (sl)
|
||||
MOV r3, #0 ; Build initial register value
|
||||
STR r3, [r2, #52] ; Store initial r11
|
||||
STR r3, [r2, #56] ; Store initial r12
|
||||
STR r3, [r2, #60] ; Store initial lr
|
||||
STR r1, [r2, #64] ; Store initial pc
|
||||
STR r3, [r2, #68] ; 0 for back-trace
|
||||
|
||||
MRS r3, CPSR ; Pickup CPSR
|
||||
BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR
|
||||
ORR r3, r3, #SYS_MODE ; Build CPSR, SYS mode, interrupts enabled
|
||||
BIC r3, r3, #THUMB_MASK ; Clear Thumb bit by default
|
||||
AND r1, r1, #1 ; Determine if the entry function is in Thumb mode
|
||||
CMP r1, #1 ; Is the Thumb bit set?
|
||||
ORREQ r3, r3, #THUMB_MASK ; Yes, set the Thumb bit
|
||||
STR r3, [r2, #4] ; Store initial CPSR
|
||||
;
|
||||
; /* Setup stack pointer. */
|
||||
; thread_ptr -> tx_thread_stack_ptr = r2;
|
||||
;
|
||||
STR r2, [r0, #8] ; Save stack pointer in thread's
|
||||
; control block
|
||||
IF {INTER} = {TRUE}
|
||||
BX lr ; Return to caller
|
||||
ELSE
|
||||
MOV pc, lr ; Return to caller
|
||||
ENDIF
|
||||
|
||||
;}
|
||||
END
|
||||
|
||||
@@ -0,0 +1,159 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;#include "tx_timer.h"
|
||||
;
|
||||
;
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IMPORT _tx_timer_time_slice
|
||||
IMPORT _tx_thread_schedule
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_thread_exit
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_system_return Cortex-A7/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is target processor specific. It is used to transfer */
|
||||
;/* control from a thread back to the ThreadX system. Only a */
|
||||
;/* minimal context is saved since the compiler assumes temp registers */
|
||||
;/* are going to get slicked by a function call anyway. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Thread scheduling loop */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ThreadX components */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_system_return(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_system_return
|
||||
_tx_thread_system_return
|
||||
;
|
||||
; /* Save minimal context on the stack. */
|
||||
;
|
||||
STMDB sp!, {r4-r11, lr} ; Save minimal context
|
||||
LDR r5, =_tx_thread_current_ptr ; Pickup address of current ptr
|
||||
LDR r6, [r5, #0] ; Pickup current thread pointer
|
||||
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
LDR r0, [r6, #144] ; Pickup the VFP enabled flag
|
||||
CMP r0, #0 ; Is the VFP enabled?
|
||||
BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save
|
||||
VMRS r4, FPSCR ; Pickup the FPSCR
|
||||
STR r4, [sp, #-4]! ; Save FPSCR
|
||||
VSTMDB sp!, {D16-D31} ; Save D16-D31
|
||||
VSTMDB sp!, {D8-D15} ; Save D8-D15
|
||||
_tx_skip_solicited_vfp_save
|
||||
ENDIF
|
||||
|
||||
MOV r0, #0 ; Build a solicited stack type
|
||||
MRS r1, CPSR ; Pickup the CPSR
|
||||
STMDB sp!, {r0-r1} ; Save type and CPSR
|
||||
;
|
||||
; /* Lockout interrupts. */
|
||||
;
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
CPSID if ; Disable IRQ and FIQ interrupts
|
||||
ELSE
|
||||
CPSID i ; Disable IRQ interrupts
|
||||
ENDIF
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
;
|
||||
BL _tx_execution_thread_exit ; Call the thread exit function
|
||||
ENDIF
|
||||
LDR r2, =_tx_timer_time_slice ; Pickup address of time slice
|
||||
LDR r1, [r2, #0] ; Pickup current time slice
|
||||
;
|
||||
; /* Save current stack and switch to system stack. */
|
||||
; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
|
||||
; sp = _tx_thread_system_stack_ptr;
|
||||
;
|
||||
STR sp, [r6, #8] ; Save thread stack pointer
|
||||
;
|
||||
; /* Determine if the time-slice is active. */
|
||||
; if (_tx_timer_time_slice)
|
||||
; {
|
||||
;
|
||||
MOV r4, #0 ; Build clear value
|
||||
CMP r1, #0 ; Is a time-slice active?
|
||||
BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice
|
||||
;
|
||||
; /* Save the current remaining time-slice. */
|
||||
; _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
|
||||
; _tx_timer_time_slice = 0;
|
||||
;
|
||||
STR r4, [r2, #0] ; Clear time-slice
|
||||
STR r1, [r6, #24] ; Store current time-slice
|
||||
;
|
||||
; }
|
||||
__tx_thread_dont_save_ts
|
||||
;
|
||||
; /* Clear the current thread pointer. */
|
||||
; _tx_thread_current_ptr = TX_NULL;
|
||||
;
|
||||
STR r4, [r5, #0] ; Clear current thread pointer
|
||||
|
||||
B _tx_thread_schedule ; Jump to scheduler!
|
||||
;
|
||||
;}
|
||||
END
|
||||
|
||||
@@ -0,0 +1,200 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
IMPORT _tx_thread_system_state
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_isr_enter
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_vectored_context_save Cortex-A7/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function saves the context of an executing thread in the */
|
||||
;/* beginning of interrupt processing. The function also ensures that */
|
||||
;/* the system stack is used upon return to the calling ISR. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_vectored_context_save(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_vectored_context_save
|
||||
_tx_thread_vectored_context_save
|
||||
;
|
||||
; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
|
||||
; out, we are in IRQ mode, and all registers are intact. */
|
||||
;
|
||||
; /* Check for a nested interrupt condition. */
|
||||
; if (_tx_thread_system_state++)
|
||||
; {
|
||||
;
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
CPSID if ; Disable IRQ and FIQ interrupts
|
||||
ENDIF
|
||||
LDR r3, =_tx_thread_system_state ; Pickup address of system state var
|
||||
LDR r2, [r3, #0] ; Pickup system state
|
||||
CMP r2, #0 ; Is this the first interrupt?
|
||||
BEQ __tx_thread_not_nested_save ; Yes, not a nested context save
|
||||
;
|
||||
; /* Nested interrupt condition. */
|
||||
;
|
||||
ADD r2, r2, #1 ; Increment the interrupt counter
|
||||
STR r2, [r3, #0] ; Store it back in the variable
|
||||
;
|
||||
; /* Note: Minimal context of interrupted thread is already saved. */
|
||||
;
|
||||
; /* Return to the ISR. */
|
||||
;
|
||||
MOV r10, #0 ; Clear stack limit
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
PUSH {lr} ; Save ISR lr
|
||||
BL _tx_execution_isr_enter ; Call the ISR enter function
|
||||
POP {lr} ; Recover ISR lr
|
||||
ENDIF
|
||||
|
||||
IF {INTER} = {TRUE}
|
||||
BX lr ; Return to caller
|
||||
ELSE
|
||||
MOV pc, lr ; Return to caller
|
||||
ENDIF
|
||||
;
|
||||
__tx_thread_not_nested_save
|
||||
; }
|
||||
;
|
||||
; /* Otherwise, not nested, check to see if a thread was running. */
|
||||
; else if (_tx_thread_current_ptr)
|
||||
; {
|
||||
;
|
||||
ADD r2, r2, #1 ; Increment the interrupt counter
|
||||
STR r2, [r3, #0] ; Store it back in the variable
|
||||
LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr
|
||||
LDR r0, [r1, #0] ; Pickup current thread pointer
|
||||
CMP r0, #0 ; Is it NULL?
|
||||
BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in
|
||||
; scheduling loop - nothing needs saving!
|
||||
;
|
||||
; /* Note: Minimal context of interrupted thread is already saved. */
|
||||
;
|
||||
; /* Save the current stack pointer in the thread's control block. */
|
||||
; _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
|
||||
;
|
||||
; /* Switch to the system stack. */
|
||||
; sp = _tx_thread_system_stack_ptr;
|
||||
;
|
||||
MOV r10, #0 ; Clear stack limit
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
PUSH {lr} ; Save ISR lr
|
||||
BL _tx_execution_isr_enter ; Call the ISR enter function
|
||||
POP {lr} ; Recover ISR lr
|
||||
ENDIF
|
||||
|
||||
IF {INTER} = {TRUE}
|
||||
BX lr ; Return to caller
|
||||
ELSE
|
||||
MOV pc, lr ; Return to caller
|
||||
ENDIF
|
||||
;
|
||||
; }
|
||||
; else
|
||||
; {
|
||||
;
|
||||
__tx_thread_idle_system_save
|
||||
;
|
||||
; /* Interrupt occurred in the scheduling loop. */
|
||||
;
|
||||
; /* Not much to do here, just adjust the stack pointer, and return to IRQ
|
||||
; processing. */
|
||||
;
|
||||
MOV r10, #0 ; Clear stack limit
|
||||
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
PUSH {lr} ; Save ISR lr
|
||||
BL _tx_execution_isr_enter ; Call the ISR enter function
|
||||
POP {lr} ; Recover ISR lr
|
||||
ENDIF
|
||||
|
||||
ADD sp, sp, #32 ; Recover saved registers
|
||||
IF {INTER} = {TRUE}
|
||||
BX lr ; Return to caller
|
||||
ELSE
|
||||
MOV pc, lr ; Return to caller
|
||||
ENDIF
|
||||
;
|
||||
; }
|
||||
;}
|
||||
;
|
||||
END
|
||||
|
||||
@@ -0,0 +1,258 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Timer */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_timer.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
;Define Assembly language external references...
|
||||
;
|
||||
IMPORT _tx_timer_time_slice
|
||||
IMPORT _tx_timer_system_clock
|
||||
IMPORT _tx_timer_current_ptr
|
||||
IMPORT _tx_timer_list_start
|
||||
IMPORT _tx_timer_list_end
|
||||
IMPORT _tx_timer_expired_time_slice
|
||||
IMPORT _tx_timer_expired
|
||||
IMPORT _tx_thread_time_slice
|
||||
IMPORT _tx_timer_expiration_process
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_timer_interrupt Cortex-A7/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function processes the hardware timer interrupt. This */
|
||||
;/* processing includes incrementing the system clock and checking for */
|
||||
;/* time slice and/or timer expiration. If either is found, the */
|
||||
;/* interrupt context save/restore functions are called along with the */
|
||||
;/* expiration functions. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_timer_expiration_process Timer expiration processing */
|
||||
;/* _tx_thread_time_slice Time slice interrupted thread */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* interrupt vector */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_timer_interrupt(VOID)
|
||||
;{
|
||||
EXPORT _tx_timer_interrupt
|
||||
_tx_timer_interrupt
|
||||
;
|
||||
; /* Upon entry to this routine, it is assumed that context save has already
|
||||
; been called, and therefore the compiler scratch registers are available
|
||||
; for use. */
|
||||
;
|
||||
; /* Increment the system clock. */
|
||||
; _tx_timer_system_clock++;
|
||||
;
|
||||
LDR r1, =_tx_timer_system_clock ; Pickup address of system clock
|
||||
LDR r0, [r1, #0] ; Pickup system clock
|
||||
ADD r0, r0, #1 ; Increment system clock
|
||||
STR r0, [r1, #0] ; Store new system clock
|
||||
;
|
||||
; /* Test for time-slice expiration. */
|
||||
; if (_tx_timer_time_slice)
|
||||
; {
|
||||
;
|
||||
LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice
|
||||
LDR r2, [r3, #0] ; Pickup time-slice
|
||||
CMP r2, #0 ; Is it non-active?
|
||||
BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing
|
||||
;
|
||||
; /* Decrement the time_slice. */
|
||||
; _tx_timer_time_slice--;
|
||||
;
|
||||
SUB r2, r2, #1 ; Decrement the time-slice
|
||||
STR r2, [r3, #0] ; Store new time-slice value
|
||||
;
|
||||
; /* Check for expiration. */
|
||||
; if (__tx_timer_time_slice == 0)
|
||||
;
|
||||
CMP r2, #0 ; Has it expired?
|
||||
BNE __tx_timer_no_time_slice ; No, skip expiration processing
|
||||
;
|
||||
; /* Set the time-slice expired flag. */
|
||||
; _tx_timer_expired_time_slice = TX_TRUE;
|
||||
;
|
||||
LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag
|
||||
MOV r0, #1 ; Build expired value
|
||||
STR r0, [r3, #0] ; Set time-slice expiration flag
|
||||
;
|
||||
; }
|
||||
;
|
||||
__tx_timer_no_time_slice
|
||||
;
|
||||
; /* Test for timer expiration. */
|
||||
; if (*_tx_timer_current_ptr)
|
||||
; {
|
||||
;
|
||||
LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr
|
||||
LDR r0, [r1, #0] ; Pickup current timer
|
||||
LDR r2, [r0, #0] ; Pickup timer list entry
|
||||
CMP r2, #0 ; Is there anything in the list?
|
||||
BEQ __tx_timer_no_timer ; No, just increment the timer
|
||||
;
|
||||
; /* Set expiration flag. */
|
||||
; _tx_timer_expired = TX_TRUE;
|
||||
;
|
||||
LDR r3, =_tx_timer_expired ; Pickup expiration flag address
|
||||
MOV r2, #1 ; Build expired value
|
||||
STR r2, [r3, #0] ; Set expired flag
|
||||
B __tx_timer_done ; Finished timer processing
|
||||
;
|
||||
; }
|
||||
; else
|
||||
; {
|
||||
__tx_timer_no_timer
|
||||
;
|
||||
; /* No timer expired, increment the timer pointer. */
|
||||
; _tx_timer_current_ptr++;
|
||||
;
|
||||
ADD r0, r0, #4 ; Move to next timer
|
||||
;
|
||||
; /* Check for wrap-around. */
|
||||
; if (_tx_timer_current_ptr == _tx_timer_list_end)
|
||||
;
|
||||
LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end
|
||||
LDR r2, [r3, #0] ; Pickup list end
|
||||
CMP r0, r2 ; Are we at list end?
|
||||
BNE __tx_timer_skip_wrap ; No, skip wrap-around logic
|
||||
;
|
||||
; /* Wrap to beginning of list. */
|
||||
; _tx_timer_current_ptr = _tx_timer_list_start;
|
||||
;
|
||||
LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start
|
||||
LDR r0, [r3, #0] ; Set current pointer to list start
|
||||
;
|
||||
__tx_timer_skip_wrap
|
||||
;
|
||||
STR r0, [r1, #0] ; Store new current timer pointer
|
||||
; }
|
||||
;
|
||||
__tx_timer_done
|
||||
;
|
||||
;
|
||||
; /* See if anything has expired. */
|
||||
; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
|
||||
; {
|
||||
;
|
||||
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag
|
||||
LDR r2, [r3, #0] ; Pickup time-slice expired flag
|
||||
CMP r2, #0 ; Did a time-slice expire?
|
||||
BNE __tx_something_expired ; If non-zero, time-slice expired
|
||||
LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag
|
||||
LDR r0, [r1, #0] ; Pickup timer expired flag
|
||||
CMP r0, #0 ; Did a timer expire?
|
||||
BEQ __tx_timer_nothing_expired ; No, nothing expired
|
||||
;
|
||||
__tx_something_expired
|
||||
;
|
||||
;
|
||||
STMDB sp!, {r0, lr} ; Save the lr register on the stack
|
||||
; and save r0 just to keep 8-byte alignment
|
||||
;
|
||||
; /* Did a timer expire? */
|
||||
; if (_tx_timer_expired)
|
||||
; {
|
||||
;
|
||||
LDR r1, =_tx_timer_expired ; Pickup addr of expired flag
|
||||
LDR r0, [r1, #0] ; Pickup timer expired flag
|
||||
CMP r0, #0 ; Check for timer expiration
|
||||
BEQ __tx_timer_dont_activate ; If not set, skip timer activation
|
||||
;
|
||||
; /* Process timer expiration. */
|
||||
; _tx_timer_expiration_process();
|
||||
;
|
||||
BL _tx_timer_expiration_process ; Call the timer expiration handling routine
|
||||
;
|
||||
; }
|
||||
__tx_timer_dont_activate
|
||||
;
|
||||
; /* Did time slice expire? */
|
||||
; if (_tx_timer_expired_time_slice)
|
||||
; {
|
||||
;
|
||||
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired
|
||||
LDR r2, [r3, #0] ; Pickup the actual flag
|
||||
CMP r2, #0 ; See if the flag is set
|
||||
BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing
|
||||
;
|
||||
; /* Time slice interrupted thread. */
|
||||
; _tx_thread_time_slice();
|
||||
|
||||
BL _tx_thread_time_slice ; Call time-slice processing
|
||||
;
|
||||
; }
|
||||
;
|
||||
__tx_timer_not_ts_expiration
|
||||
;
|
||||
LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for
|
||||
; the 8-byte stack alignment
|
||||
;
|
||||
; }
|
||||
;
|
||||
__tx_timer_nothing_expired
|
||||
;
|
||||
IF {INTER} = {TRUE}
|
||||
BX lr ; Return to caller
|
||||
ELSE
|
||||
MOV pc, lr ; Return to caller
|
||||
ENDIF
|
||||
;
|
||||
;}
|
||||
END
|
||||
|
||||
@@ -0,0 +1,90 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_alignment_adjust Cortex-A7/MMU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function adjusts the alignment and size of the code and data */
|
||||
/* section for a given module implementation. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* code_size Size of the code area (updated) */
|
||||
/* code_alignment Code area alignment (updated) */
|
||||
/* data_size Size of data area (updated) */
|
||||
/* data_alignment Data area alignment (updated) */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Initial thread stack frame */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment)
|
||||
{
|
||||
|
||||
ULONG local_code_size;
|
||||
ULONG local_code_alignment;
|
||||
ULONG local_data_size;
|
||||
ULONG local_data_alignment;
|
||||
|
||||
|
||||
/* Copy the input parameters into local variables for ease of use. */
|
||||
local_code_size = *code_size;
|
||||
local_code_alignment = TXM_MODULE_MEMORY_ALIGNMENT;
|
||||
local_data_size = *data_size;
|
||||
local_data_alignment = TXM_MODULE_MEMORY_ALIGNMENT;
|
||||
|
||||
/* Return all the information to the caller. */
|
||||
*code_size = ((local_code_size + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT;
|
||||
*code_alignment = local_code_alignment;
|
||||
*data_size = ((local_data_size + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT;
|
||||
*data_alignment = local_data_alignment;
|
||||
}
|
||||
@@ -0,0 +1,483 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_mutex.h"
|
||||
#include "tx_queue.h"
|
||||
#include "tx_thread.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
/* External page tables. */
|
||||
extern ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES];
|
||||
extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES];
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_level2_page_get Cortex-A7/MMU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function gets an available L2 page table and places it in the */
|
||||
/* module external page table list. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_instance Module instance pointer */
|
||||
/* page_addr Address of L2 page */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* Completion Status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _txm_module_manager_external_memory_enable */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
ULONG _txm_level2_page_get(TXM_MODULE_INSTANCE *module_instance, ULONG *page_addr)
|
||||
{
|
||||
|
||||
UINT i;
|
||||
UINT status;
|
||||
UINT table_index;
|
||||
UINT pool_index;
|
||||
|
||||
/* Default status to success. */
|
||||
status = TX_SUCCESS;
|
||||
|
||||
/* Find first free table slot in module control block. */
|
||||
for(i = 0; i < TXM_MODULE_LEVEL2_EXTERNAL_PAGES; i++)
|
||||
{
|
||||
if(module_instance->txm_external_page_table[i] == TX_NULL)
|
||||
{
|
||||
table_index = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if(i >= TXM_MODULE_LEVEL2_EXTERNAL_PAGES)
|
||||
{
|
||||
status = TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
/* Find first free table in pool. */
|
||||
for(i = 0; i < TXM_LEVEL2_EXTERNAL_POOL_PAGES; i++)
|
||||
{
|
||||
if(_txm_level2_external_page_pool[i][0] == (ULONG) TX_NULL)
|
||||
{
|
||||
pool_index = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if(i >= TXM_LEVEL2_EXTERNAL_POOL_PAGES)
|
||||
{
|
||||
status = TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if(status == TX_SUCCESS)
|
||||
{
|
||||
/* Place page address in table slot. Return page address. */
|
||||
module_instance->txm_external_page_table[table_index] = _txm_level2_external_page_pool[pool_index];
|
||||
*page_addr = (ULONG)_txm_level2_external_page_pool[pool_index];
|
||||
}
|
||||
|
||||
return(status);
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_level2_page_clear Cortex-A7/MMU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function clears the first entry in a L2 page table and clears */
|
||||
/* the table entry from the module external page table list. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_instance Module instance pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* TXM_MODULE_MANAGER_MODULE_UNLOAD */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_level2_page_clear(TXM_MODULE_INSTANCE *module_instance)
|
||||
{
|
||||
UINT i;
|
||||
|
||||
/* Clear table slots and zero out L2 entry. */
|
||||
for(i = 0; i < TXM_MODULE_LEVEL2_EXTERNAL_PAGES; i++)
|
||||
{
|
||||
if(module_instance->txm_external_page_table[i])
|
||||
{
|
||||
*(ULONG *)module_instance->txm_external_page_table[i] = (ULONG)TX_NULL;
|
||||
module_instance->txm_external_page_table[i] = TX_NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_external_memory_enable Cortex-A7/MMU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function creates an entry in the MMU table for a shared */
|
||||
/* memory space. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_instance Module instance pointer */
|
||||
/* start_address Start address of memory */
|
||||
/* length Length of external memory */
|
||||
/* attributes Memory attributes */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* Completion Status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_mutex_get Get protection mutex */
|
||||
/* _tx_mutex_put Release protection mutex */
|
||||
/* TX_MEMSET Fill memory with constant */
|
||||
/* _txm_level2_page_get Get L2 page table */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txm_module_manager_external_memory_enable( TXM_MODULE_INSTANCE *module_instance,
|
||||
VOID *start_address,
|
||||
ULONG length,
|
||||
UINT attributes)
|
||||
{
|
||||
|
||||
ULONG start_addr = (ULONG) start_address;
|
||||
ULONG end_addr;
|
||||
ULONG mmu_l1_entries;
|
||||
ULONG mmu_l2_entries = 0;
|
||||
ULONG level1_index;
|
||||
ULONG level2_index;
|
||||
ULONG temp_index;
|
||||
ULONG temp_addr;
|
||||
ULONG page_addr;
|
||||
ULONG asid;
|
||||
ULONG level1_attributes;
|
||||
ULONG level2_attributes;
|
||||
UINT status;
|
||||
UINT i;
|
||||
|
||||
/* Determine if the module manager has not been initialized yet. */
|
||||
if (_txm_module_manager_ready != TX_TRUE)
|
||||
{
|
||||
/* Module manager has not been initialized. */
|
||||
return(TX_NOT_AVAILABLE);
|
||||
}
|
||||
|
||||
/* Determine if the module is valid. */
|
||||
if (module_instance == TX_NULL)
|
||||
{
|
||||
/* Invalid module pointer. */
|
||||
return(TX_PTR_ERROR);
|
||||
}
|
||||
|
||||
/* Get module manager protection mutex. */
|
||||
_tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER);
|
||||
|
||||
/* Determine if the module instance is valid. */
|
||||
if (module_instance -> txm_module_instance_id != TXM_MODULE_ID)
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Invalid module pointer. */
|
||||
return(TX_PTR_ERROR);
|
||||
}
|
||||
|
||||
/* Determine if the module instance is in the loaded state. */
|
||||
if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED)
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Return error if the module is not ready. */
|
||||
return(TX_START_ERROR);
|
||||
}
|
||||
|
||||
/* Determine if the module instance is memory protected. */
|
||||
if (module_instance -> txm_module_instance_asid == 0)
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Return error if the module is not protected. */
|
||||
return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR);
|
||||
}
|
||||
|
||||
/* Start address must be aligned to MMU block size (4 kB).
|
||||
Length will be rounded up to 4 kB alignment. */
|
||||
if(start_addr & ~TXM_MMU_LEVEL2_MASK)
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Return alignment error. */
|
||||
return(TXM_MODULE_ALIGNMENT_ERROR);
|
||||
}
|
||||
|
||||
/**************************************************************************/
|
||||
/* At this point, we have a valid address. Set up MMU. */
|
||||
/**************************************************************************/
|
||||
|
||||
/* Round length up to 4 kB alignment. */
|
||||
if(length & ~TXM_MMU_LEVEL2_MASK)
|
||||
{
|
||||
length = ((length + TXM_MODULE_MEMORY_ALIGNMENT - 1)/TXM_MODULE_MEMORY_ALIGNMENT) * TXM_MODULE_MEMORY_ALIGNMENT;
|
||||
}
|
||||
|
||||
/* Get end address. */
|
||||
end_addr = start_addr + length - 1;
|
||||
|
||||
/* How many level 1 table entries does data span? */
|
||||
mmu_l1_entries = (end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1;
|
||||
|
||||
/* Add 1 to align. */
|
||||
end_addr++;
|
||||
|
||||
/* How many level 2 table entries does data need?
|
||||
* 0: start and end addresses both aligned.
|
||||
* 1: either start or end address aligned.
|
||||
* 2: start and end addresses both not aligned. */
|
||||
if(start_addr & ~TXM_MMU_LEVEL1_MASK)
|
||||
{
|
||||
/* If start address is not aligned, increment. */
|
||||
mmu_l2_entries++;
|
||||
}
|
||||
if(end_addr & ~TXM_MMU_LEVEL1_MASK)
|
||||
{
|
||||
/* If end address is not aligned, increment. */
|
||||
mmu_l2_entries++;
|
||||
}
|
||||
|
||||
/* Get index into L1 table. */
|
||||
level1_index = (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT);
|
||||
|
||||
/* Get module ASID. */
|
||||
asid = module_instance -> txm_module_instance_asid;
|
||||
|
||||
/* Do start and end entries need level 2 pages? */
|
||||
if(mmu_l2_entries > 0)
|
||||
{
|
||||
/* Build L2 attributes. */
|
||||
level2_attributes = ((attributes & TXM_MMU_ATTRIBUTE_XN) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_XN_SHIFT) |
|
||||
((attributes & TXM_MMU_ATTRIBUTE_B) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_B_SHIFT) |
|
||||
((attributes & TXM_MMU_ATTRIBUTE_C) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_C_SHIFT) |
|
||||
((attributes & TXM_MMU_ATTRIBUTE_AP) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_AP_SHIFT) |
|
||||
((attributes & TXM_MMU_ATTRIBUTE_TEX) << TXM_MMU_LEVEL2_USER_ATTRIBUTE_TEX_SHIFT) |
|
||||
TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE;
|
||||
|
||||
/* If start_addr is not aligned, we need a L2 page. */
|
||||
if(start_addr & ~TXM_MMU_LEVEL1_MASK)
|
||||
{
|
||||
|
||||
/* Is there already an L2 page in the L1 table? */
|
||||
if((_txm_ttbr1_page_table[asid][level1_index] & ~TXM_MMU_LEVEL1_SECOND_MASK) == TXM_MMU_LEVEL1_SECOND_ATTRIBUTES)
|
||||
{
|
||||
page_addr = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get L2 table from pool. */
|
||||
status = _txm_level2_page_get(module_instance, &page_addr);
|
||||
|
||||
if(status != TX_SUCCESS)
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR);
|
||||
}
|
||||
|
||||
/* Clear L2 table. */
|
||||
TX_MEMSET((void *)page_addr, 0, TXM_LEVEL_2_PAGE_TABLE_ENTRIES);
|
||||
|
||||
/* Put L2 page in L1 table. */
|
||||
_txm_ttbr1_page_table[asid][level1_index] = (page_addr & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES;
|
||||
}
|
||||
|
||||
/* Decrement number of L1 entries remaining. */
|
||||
mmu_l1_entries--;
|
||||
|
||||
/* Set up L2 start table. */
|
||||
/* Determine how many entries in L2 table. */
|
||||
if((end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT))
|
||||
{
|
||||
/* End address goes to next L1 page (or beyond). */
|
||||
temp_addr = ((start_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT);
|
||||
mmu_l2_entries = (temp_addr - start_addr) >> TXM_MMU_LEVEL2_PAGE_SHIFT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* End address is on the same L1 page. */
|
||||
mmu_l2_entries = (end_addr >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_addr >> TXM_MMU_LEVEL2_PAGE_SHIFT);
|
||||
}
|
||||
|
||||
/* Insert module settings into start table. */
|
||||
level2_index = ((start_addr & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT);
|
||||
for(i = 0; i < mmu_l2_entries; i++, level2_index++)
|
||||
{
|
||||
((ULONG *) page_addr)[level2_index] = (start_addr & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | level2_attributes;
|
||||
}
|
||||
|
||||
level1_index++;
|
||||
}
|
||||
|
||||
/* Does last entry need a level 2 page? */
|
||||
/* If end_address is not aligned, we need a L2 page. */
|
||||
if((end_addr & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0))
|
||||
{
|
||||
/* Get index into L1 table. */
|
||||
temp_index = (end_addr >> TXM_MMU_LEVEL1_PAGE_SHIFT);
|
||||
|
||||
/* Is there already an L2 page in the L1 table? */
|
||||
if((_txm_ttbr1_page_table[asid][temp_index] & ~TXM_MMU_LEVEL1_SECOND_MASK) == TXM_MMU_LEVEL1_SECOND_ATTRIBUTES)
|
||||
{
|
||||
page_addr = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get L2 table from pool. */
|
||||
status = _txm_level2_page_get(module_instance, &page_addr);
|
||||
|
||||
if(status != TX_SUCCESS)
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
return(TXM_MODULE_EXTERNAL_MEMORY_ENABLE_ERROR);
|
||||
}
|
||||
|
||||
/* Clear L2 table. */
|
||||
TX_MEMSET((void *)page_addr, 0, TXM_LEVEL_2_PAGE_TABLE_ENTRIES);
|
||||
|
||||
/* Put L2 page in L1 table. */
|
||||
_txm_ttbr1_page_table[asid][temp_index] = (page_addr & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES;
|
||||
}
|
||||
|
||||
/* Decrement number of L1 entries remaining. */
|
||||
mmu_l1_entries--;
|
||||
|
||||
/* Determine how many entries in L2 table. */
|
||||
mmu_l2_entries = ((end_addr & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT);
|
||||
|
||||
/* Set up L2 end table. */
|
||||
for(i = 0; i < mmu_l2_entries; i++)
|
||||
{
|
||||
((ULONG *) page_addr)[i] = (end_addr & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | level2_attributes;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Fill any L1 entries between start and end pages of module data range. */
|
||||
for(i = 0; i < mmu_l1_entries; i++, level1_index++)
|
||||
{
|
||||
/* Build L1 attributes. */
|
||||
level1_attributes = ((attributes & TXM_MMU_ATTRIBUTE_XN) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_XN_SHIFT) |
|
||||
((attributes & TXM_MMU_ATTRIBUTE_B) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_B_SHIFT) |
|
||||
((attributes & TXM_MMU_ATTRIBUTE_C) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_C_SHIFT) |
|
||||
((attributes & TXM_MMU_ATTRIBUTE_AP) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_AP_SHIFT) |
|
||||
((attributes & TXM_MMU_ATTRIBUTE_TEX) << TXM_MMU_LEVEL1_USER_ATTRIBUTE_TEX_SHIFT) |
|
||||
TXM_MMU_LEVEL1_USER_ATTRIBUTE_BASE;
|
||||
|
||||
/* Place address and attributes in table. */
|
||||
_txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | level1_attributes;
|
||||
}
|
||||
|
||||
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Return success. */
|
||||
return(TX_SUCCESS);
|
||||
}
|
||||
@@ -0,0 +1,111 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_thread.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/* Define the user's fault notification callback function pointer. This is
|
||||
setup via the txm_module_manager_memory_fault_notify API. */
|
||||
|
||||
VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *);
|
||||
|
||||
|
||||
/* Define a macro that can be used to allocate global variables useful to
|
||||
store information about the last fault. This macro is defined in
|
||||
txm_module_port.h and is usually populated in the assembly language
|
||||
fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */
|
||||
|
||||
TXM_MODULE_MANAGER_FAULT_INFO
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_memory_fault_handler Cortex-A7/MMU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function handles a fault associated with a memory protected */
|
||||
/* module. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_terminate Terminate thread */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Fault handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_manager_memory_fault_handler(VOID)
|
||||
{
|
||||
|
||||
TXM_MODULE_INSTANCE *module_instance_ptr;
|
||||
TX_THREAD *thread_ptr;
|
||||
|
||||
|
||||
/* Pickup the current thread. */
|
||||
thread_ptr = _tx_thread_current_ptr;
|
||||
|
||||
/* Initialize the module instance pointer to NULL. */
|
||||
module_instance_ptr = TX_NULL;
|
||||
|
||||
/* Is there a thread? */
|
||||
if (thread_ptr)
|
||||
{
|
||||
/* Pickup the module instance. */
|
||||
module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr;
|
||||
|
||||
/* Terminate the current thread. */
|
||||
_tx_thread_terminate(_tx_thread_current_ptr);
|
||||
}
|
||||
|
||||
/* Determine if there is a user memory fault notification callback. */
|
||||
if (_txm_module_manager_fault_notify)
|
||||
{
|
||||
/* Yes, call the user's notification memory fault callback. */
|
||||
(_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,84 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_thread.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/* Define the external user's fault notification callback function pointer. This is
|
||||
setup via the txm_module_manager_memory_fault_notify API. */
|
||||
|
||||
extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *);
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_memory_fault_notify Cortex-A7/MMU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function registers an application callback when/if a memory */
|
||||
/* fault occurs. The supplied thread is automatically terminated, but */
|
||||
/* any other threads in the same module may still execute. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* notify_function Memory fault notification */
|
||||
/* function, NULL disables. */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* Status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *))
|
||||
{
|
||||
/* Setup notification function. */
|
||||
_txm_module_manager_fault_notify = notify_function;
|
||||
|
||||
/* Return success. */
|
||||
return(TX_SUCCESS);
|
||||
}
|
||||
@@ -0,0 +1,301 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
#define CACHE_DISABLED 0x12
|
||||
#define SDRAM_START 0x00000000
|
||||
#define SDRAM_END 0x1fffffff
|
||||
#define CACHE_WRITEBACK 0x1e
|
||||
|
||||
#define SECTION_DESCRIPTOR 0x00000002
|
||||
#define DACR_CLIENT_MODE 0x55555555
|
||||
|
||||
|
||||
/*** Page table attributes TTBR0 ***********************************************
|
||||
* IRGN = 01 - Normal memory, Inner Write-Back Write-Allocate Cacheable
|
||||
* S - non-shareable
|
||||
* RGN = 01 - Normal memory, Outer Write-Back Write-Allocate Cacheable
|
||||
* NOS - outer-shareable
|
||||
*******************************************************************************/
|
||||
#define TTBR0_ATTRIBUTES 0x48
|
||||
|
||||
|
||||
|
||||
/* ASID table, index is ASID number and contents hold pointer to module. */
|
||||
TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH];
|
||||
|
||||
/* Master page table, 2^14 (16kB) alignment.
|
||||
* First table is the master level 1 table, the rest are for each module. */
|
||||
__align(16384) ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES];
|
||||
|
||||
/* Module start and end level 2 page tables, 2^10 (1kB) alignment.
|
||||
* First set of 4 tables are the master level 2 tables, the rest are for each module.
|
||||
* Each module needs two L2 tables for code and two L2 tables for data. */
|
||||
__align(1024) ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES * 4][TXM_LEVEL_2_PAGE_TABLE_ENTRIES];
|
||||
|
||||
/* Module external memory level 2 page tables, 2^10 (1kB) alignment. */
|
||||
__align(1024) ULONG _txm_level2_external_page_pool[TXM_LEVEL2_EXTERNAL_POOL_PAGES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES];
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_mm_initialize Cortex-A7/MMU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function performs the initial set up of the the A7 MMU. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* Completion Status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txm_module_manager_mm_initialize(VOID)
|
||||
{
|
||||
|
||||
#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED
|
||||
UINT i;
|
||||
ULONG cp15reg;
|
||||
UINT user_mode_index;
|
||||
UINT counter_limit;
|
||||
|
||||
/* Clear ASID table. */
|
||||
for (i = 0; i < TXM_ASID_TABLE_LENGTH; i++)
|
||||
{
|
||||
_txm_asid_table[i] = 0;
|
||||
}
|
||||
_txm_asid_table[0] = (TXM_MODULE_INSTANCE *)TXM_ASID_RESERVED;
|
||||
|
||||
|
||||
/********************************************************************************/
|
||||
/* This is an example showing how to set up the cache attributes. */
|
||||
/********************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* PAGE TABLE generation
|
||||
* Generate the page tables
|
||||
* Build a flat translation table for the whole address space.
|
||||
* ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx
|
||||
* 31 20|19 18|17|16| 15|14 12|11 10|9|8 5|4 |3 2|1 0|
|
||||
* |base address | 0 0|nG| S|AP2|TEX |AP |P|Domain|XN|CB |1 0|
|
||||
*
|
||||
* Bits[31:20] - Top 12 bits of VA is pointer into table
|
||||
* nG[17]=0 - Non global, enables matching against ASID in the TLB when set.
|
||||
* S[16]=0 - Indicates normal memory is shared when set.
|
||||
* AP2[15]=0
|
||||
* TEX[14:12]=000
|
||||
* AP[11:10]=11 - Configure for full read/write access in all modes
|
||||
* IMPP[9]=0 - Ignored
|
||||
* Domain[5:8]=1111 - Set all pages to use domain 15
|
||||
* XN[4]=0 - Execute never disabled
|
||||
* CB[3:2]= 00 - Set attributes to Strongly-ordered memory.
|
||||
* (except for the descriptor where code segment is based,
|
||||
* see below)
|
||||
* Bits[1:0]=10 - Indicate entry is a 1MB section
|
||||
*******************************************************************************/
|
||||
|
||||
/* ---- Parameter setting to level1 descriptor (bits 19:0) ---- */
|
||||
/* setting for Strongly-ordered memory
|
||||
B-00000000000000000000010111100010 */
|
||||
#define TTB_PARA_STRGLY 0x05E2
|
||||
|
||||
/* setting for Outer and inner not cache normal memory
|
||||
B-00000000000000000001010111100010 */
|
||||
#define TTB_PARA_NORMAL_NOT_CACHE 0x15E2
|
||||
|
||||
/* setting for Outer and inner write back, write allocate normal memory
|
||||
(Cacheable)
|
||||
B-00000000000000000001010111101110 */
|
||||
#define TTB_PARA_NORMAL_CACHE 0x15EE //0x15EE
|
||||
|
||||
/* In this chip (RZA1) there are the following 12 sections with the defined memory size (MB) */
|
||||
#define M_SIZE_NOR 128 /* [Area00] CS0, CS1 area (for NOR flash) */
|
||||
#define M_SIZE_SDRAM 128 /* [Area01] CS2, CS3 area (for SDRAM) */
|
||||
#define M_SIZE_CS45 128 /* [Area02] CS4, CS5 area */
|
||||
#define M_SIZE_SPI 128 /* [Area03] SPI, SP2 area (for Serial flash) */
|
||||
#define M_SIZE_RAM 10 /* [Area04] Internal RAM */
|
||||
#define M_SIZE_IO_1 502 /* [Area05] I/O area 1 */
|
||||
#define M_SIZE_NOR_M 128 /* [Area06] CS0, CS1 area (for NOR flash) (mirror) */
|
||||
#define M_SIZE_SDRAM_M 128 /* [Area07] CS2, CS3 area (for SDRAM) (mirror) */
|
||||
#define M_SIZE_CS45_M 128 /* [Area08] CS4, CS5 area (mirror) */
|
||||
#define M_SIZE_SPI_M 128 /* [Area09] SPI, SP2 area (for Serial flash) (mirror) */
|
||||
#define M_SIZE_RAM_M 10 /* [Area10] Internal RAM (mirror) */
|
||||
#define M_SIZE_IO_2 2550 /* [Area11] I/O area 2 */
|
||||
/* Should add to: 4096 */
|
||||
|
||||
counter_limit = M_SIZE_NOR;
|
||||
for (i = 0; i < counter_limit; i++)
|
||||
{
|
||||
_txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE;
|
||||
}
|
||||
|
||||
counter_limit += M_SIZE_SDRAM;
|
||||
for (; i < counter_limit; i++)
|
||||
{
|
||||
_txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE;
|
||||
}
|
||||
|
||||
counter_limit += M_SIZE_CS45;
|
||||
for (; i < counter_limit; i++)
|
||||
{
|
||||
_txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY;
|
||||
}
|
||||
|
||||
counter_limit += M_SIZE_SPI;
|
||||
for (; i < counter_limit; i++)
|
||||
{
|
||||
_txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE;
|
||||
}
|
||||
|
||||
counter_limit += M_SIZE_RAM;
|
||||
for (; i < counter_limit; i++)
|
||||
{
|
||||
_txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_CACHE;
|
||||
}
|
||||
|
||||
counter_limit += M_SIZE_IO_1;
|
||||
for (; i < counter_limit; i++)
|
||||
{
|
||||
_txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY;
|
||||
}
|
||||
|
||||
counter_limit += M_SIZE_NOR_M;
|
||||
for (; i < counter_limit; i++)
|
||||
{
|
||||
_txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE;
|
||||
}
|
||||
|
||||
counter_limit += M_SIZE_SDRAM_M;
|
||||
for (; i < counter_limit; i++)
|
||||
{
|
||||
_txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE;
|
||||
}
|
||||
|
||||
counter_limit += M_SIZE_CS45_M;
|
||||
for (; i < counter_limit; i++)
|
||||
{
|
||||
_txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY;
|
||||
}
|
||||
|
||||
counter_limit += M_SIZE_SPI_M;
|
||||
for (; i < counter_limit; i++)
|
||||
{
|
||||
_txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE;
|
||||
}
|
||||
|
||||
counter_limit += M_SIZE_RAM_M;
|
||||
for (; i < counter_limit; i++)
|
||||
{
|
||||
_txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_NORMAL_NOT_CACHE;
|
||||
}
|
||||
|
||||
counter_limit += M_SIZE_IO_2;
|
||||
for (; i < counter_limit; i++)
|
||||
{
|
||||
_txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = (i << TXM_MMU_LEVEL1_PAGE_SHIFT) | TTB_PARA_STRGLY;
|
||||
}
|
||||
|
||||
/********************************************************************************/
|
||||
/* This is the end of the example showing how to set up the cache attributes. */
|
||||
/********************************************************************************/
|
||||
|
||||
|
||||
/* Clear ASID. */
|
||||
cp15reg = 0;
|
||||
__asm("mcr p15, 0, cp15reg, c13, c0, 1");
|
||||
__asm("isb");
|
||||
|
||||
/* Put the page table address in TTBR. */
|
||||
cp15reg = (int)(VOID*)_txm_ttbr1_page_table;
|
||||
cp15reg |= TTBR0_ATTRIBUTES;
|
||||
__asm("mcr p15, 0, cp15reg, c2, c0, 0");
|
||||
|
||||
/* Set the domain to client mode. */
|
||||
cp15reg = DACR_CLIENT_MODE;
|
||||
__asm("mcr p15, 0, cp15reg, c3, c0, 0");
|
||||
|
||||
|
||||
/* Level 2 small page attributes: normal memory, cache & buffer enabled, priviledged access. */
|
||||
#define TTB_LEVEL2_NORMAL_CACHE 0x05E
|
||||
|
||||
/* Level 2 clear AP attributes mask. */
|
||||
#define TTB_LEVEL2_AP_CLEAR_MASK 0xFFFFFFCF
|
||||
|
||||
/* Attributes for user mode table entry in level 2 table. */
|
||||
#define TTB_LEVEL2_USER_MODE_ENTRY 0x06E
|
||||
|
||||
/* Set up Level 2 table for user to kernel mode entry trampoline. */
|
||||
/* Find which table entry _txm_module_manager_user_mode_entry is in. */
|
||||
user_mode_index = (ULONG)_txm_module_manager_user_mode_entry >> TXM_MMU_LEVEL1_PAGE_SHIFT;
|
||||
/* Fill table. */
|
||||
for (i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++)
|
||||
{
|
||||
_txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i] = ((ULONG)_txm_module_manager_user_mode_entry & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TTB_LEVEL2_NORMAL_CACHE;
|
||||
}
|
||||
|
||||
/* Enter Level 2 table in to master table. */
|
||||
_txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = ((ULONG)_txm_level2_module_page_table & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES;
|
||||
|
||||
/* Find level 2 entry that holds _txm_module_manager_user_mode_entry. */
|
||||
user_mode_index = ((ULONG)_txm_module_manager_user_mode_entry & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT;
|
||||
|
||||
/* Set attribute bits for the user mode entry page. */
|
||||
_txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] = (_txm_level2_module_page_table[TXM_MASTER_PAGE_TABLE_INDEX][user_mode_index] & TTB_LEVEL2_AP_CLEAR_MASK) | TTB_LEVEL2_USER_MODE_ENTRY;
|
||||
|
||||
/* Enable the MMU. */
|
||||
__asm("mrc p15, 0, cp15reg, c1, c0, 0");
|
||||
cp15reg |= 0x1;
|
||||
__asm("mcr p15, 0, cp15reg, c1, c0, 0");
|
||||
|
||||
return(TX_SUCCESS);
|
||||
|
||||
#else
|
||||
return(TX_FEATURE_NOT_ENABLED);
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,589 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
extern TXM_MODULE_INSTANCE *_txm_asid_table[TXM_ASID_TABLE_LENGTH];
|
||||
extern ULONG _txm_level2_module_page_table[TXM_MAXIMUM_MODULES][TXM_LEVEL_2_PAGE_TABLE_ENTRIES];
|
||||
extern ULONG _txm_ttbr1_page_table[TXM_MAXIMUM_MODULES][TXM_MASTER_PAGE_TABLE_ENTRIES];
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_inside_data_check Cortex-A7/MMU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function determines if pointer is within the module's data or */
|
||||
/* shared memory. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* pointer Data pointer */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* Completion Status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* TXM_MODULE_MANAGER_DATA_POINTER_CHECK */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txm_module_manager_inside_data_check(ULONG pointer)
|
||||
{
|
||||
|
||||
ULONG translation;
|
||||
|
||||
/* ATS1CUR operation on address supplied in pointer, Stage 1 unprivileged read. */
|
||||
__asm("MCR p15, 0, pointer, c7, c8, 2");
|
||||
__asm("ISB"); /* Ensure completion of the MCR write to CP15. */
|
||||
__asm("MRC p15, 0, translation, c7, c4, 0"); /* Read result from 32-bit PAR into translation. */
|
||||
|
||||
if (translation & TXM_ADDRESS_TRANSLATION_FAULT_BIT)
|
||||
{
|
||||
return(TX_FALSE);
|
||||
}
|
||||
|
||||
return(TX_TRUE);
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_assign_asid Cortex-A7/MMU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function assigns an Application Specific ID (ASID) to a */
|
||||
/* module. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_instance Pointer to module instance */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* Completion Status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _txm_module_manager_mm_register_setup */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txm_module_manager_assign_asid(TXM_MODULE_INSTANCE *module_instance)
|
||||
{
|
||||
UINT i = 1;
|
||||
|
||||
/* Find first non-zero ASID, starting at index 1. */
|
||||
while(i < TXM_ASID_TABLE_LENGTH)
|
||||
{
|
||||
if(_txm_asid_table[i] != 0)
|
||||
{
|
||||
i++;
|
||||
}
|
||||
else
|
||||
{
|
||||
module_instance -> txm_module_instance_asid = i;
|
||||
_txm_asid_table[i] = module_instance;
|
||||
return(TX_SUCCESS);
|
||||
}
|
||||
}
|
||||
|
||||
return(TXM_MODULE_ASID_ERROR);
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_remove_asid Cortex-A7/MMU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function removes a module from the ASID list. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_instance Pointer to module instance */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* TXM_MODULE_MANAGER_MODULE_UNLOAD */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_manager_remove_asid(TXM_MODULE_INSTANCE *module_instance)
|
||||
{
|
||||
if(module_instance -> txm_module_instance_asid)
|
||||
{
|
||||
_txm_asid_table[module_instance -> txm_module_instance_asid] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_mm_register_setup Cortex-A7/MMU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function sets up the Cortex-A7 MMU register definitions based */
|
||||
/* on the module's memory characteristics. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_instance Pointer to module instance */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _txm_module_manager_assign_asid */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* TXM_MODULE_MANAGER_MODULE_SETUP */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
|
||||
{
|
||||
#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED
|
||||
|
||||
ULONG start_address;
|
||||
ULONG end_address;
|
||||
ULONG mmu_l1_entries;
|
||||
ULONG mmu_l2_entries = 0;
|
||||
ULONG level1_index;
|
||||
ULONG level2_index;
|
||||
ULONG temp_index;
|
||||
ULONG temp_address;
|
||||
ULONG l2_address;
|
||||
ULONG attributes = 0;
|
||||
ULONG asid;
|
||||
UINT i;
|
||||
|
||||
|
||||
/* Assign an ASID to this module. */
|
||||
_txm_module_manager_assign_asid(module_instance);
|
||||
|
||||
asid = module_instance -> txm_module_instance_asid;
|
||||
|
||||
/* Copy master level 1 page table to module's page table. */
|
||||
for(i = 0; i < TXM_MASTER_PAGE_TABLE_ENTRIES; i++)
|
||||
{
|
||||
_txm_ttbr1_page_table[asid][i] = _txm_ttbr1_page_table[TXM_MASTER_PAGE_TABLE_INDEX][i];
|
||||
}
|
||||
|
||||
/* Clear level 2 tables. */
|
||||
for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++)
|
||||
{
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = 0;
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = 0;
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = 0;
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = 0;
|
||||
}
|
||||
|
||||
/* Get code start and end addresses. */
|
||||
start_address = (ULONG)module_instance -> txm_module_instance_code_start;
|
||||
/* Extend end address to end of page (TXM_MODULE_MEMORY_ALIGNMENT-1). */
|
||||
end_address = ((((ULONG)module_instance -> txm_module_instance_code_end) + TXM_MODULE_MEMORY_ALIGNMENT-1) & ~((ULONG)TXM_MODULE_MEMORY_ALIGNMENT-1)) - 1;
|
||||
|
||||
/* How many level 1 table entries does code span? */
|
||||
mmu_l1_entries = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1;
|
||||
|
||||
/* Add 1 to align. */
|
||||
end_address++;
|
||||
|
||||
/* How many level 2 table entries does code need?
|
||||
* 0: start and end addresses both aligned.
|
||||
* 1: either start or end address aligned.
|
||||
* 2: start and end addresses both not aligned. */
|
||||
if(start_address & ~TXM_MMU_LEVEL1_MASK)
|
||||
{
|
||||
/* If start address is not aligned, increment. */
|
||||
mmu_l2_entries++;
|
||||
}
|
||||
if(end_address & ~TXM_MMU_LEVEL1_MASK)
|
||||
{
|
||||
/* If end address is not aligned, increment. */
|
||||
mmu_l2_entries++;
|
||||
}
|
||||
|
||||
/* Get index into L1 table. */
|
||||
level1_index = (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT);
|
||||
|
||||
/* Set up level 1 table. */
|
||||
/* Do start and end entries need level 2 pages? */
|
||||
if(mmu_l2_entries > 0)
|
||||
{
|
||||
/* If start_address is not aligned, we need a L2 page. */
|
||||
if(start_address & ~TXM_MMU_LEVEL1_MASK)
|
||||
{
|
||||
/* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */
|
||||
if(_txm_ttbr1_page_table[asid][level1_index] & 0x01)
|
||||
{
|
||||
/* Get L2 page address from L1 table. */
|
||||
l2_address = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK;
|
||||
|
||||
/* Copy the existing L2 page into the module L2 page. */
|
||||
for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++)
|
||||
{
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Translate attributes from L1 entry to an L2 entry. */
|
||||
attributes = (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) |
|
||||
TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE;
|
||||
|
||||
/* Build L2 page with attributes inherited from L1 entry. */
|
||||
for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++)
|
||||
{
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes;
|
||||
}
|
||||
}
|
||||
|
||||
/* Put L2 page in L1 table. */
|
||||
_txm_ttbr1_page_table[asid][level1_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES;
|
||||
|
||||
/* Decrement number of L1 entries remaining. */
|
||||
mmu_l1_entries--;
|
||||
|
||||
/* Set up L2 start table. */
|
||||
/* Determine how many entries in L2 table. */
|
||||
if((end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT))
|
||||
{
|
||||
/* End address goes to next L1 page (or beyond). */
|
||||
temp_address = ((start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT);
|
||||
mmu_l2_entries = (temp_address - start_address) >> TXM_MMU_LEVEL2_PAGE_SHIFT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* End address is on the same L1 page. */
|
||||
mmu_l2_entries = (end_address >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL2_PAGE_SHIFT);
|
||||
}
|
||||
|
||||
/* Insert module settings into start table. */
|
||||
level2_index = ((start_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT);
|
||||
for(i = 0; i < mmu_l2_entries; i++, level2_index++)
|
||||
{
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_START_OFFSET][level2_index] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_CODE_ATTRIBUTES;
|
||||
}
|
||||
|
||||
level1_index++;
|
||||
}
|
||||
|
||||
/* Does last entry need a level 2 page? */
|
||||
/* If end_address is not aligned, we need a L2 page. */
|
||||
if((end_address & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0))
|
||||
{
|
||||
/* Get index into L1 table. */
|
||||
temp_index = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT);
|
||||
|
||||
/* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */
|
||||
if(_txm_ttbr1_page_table[asid][temp_index] & 0x01)
|
||||
{
|
||||
/* Get L2 page address from L1 table. */
|
||||
l2_address = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK;
|
||||
|
||||
/* Copy the existing L2 page into the module L2 page. */
|
||||
for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++)
|
||||
{
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Translate attributes from L1 entry to an L2 entry. */
|
||||
attributes = (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) |
|
||||
TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE;
|
||||
|
||||
/* Build L2 page with attributes inherited from L1 entry. */
|
||||
for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++)
|
||||
{
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes;
|
||||
}
|
||||
}
|
||||
|
||||
/* Put L2 page in L1 table. */
|
||||
_txm_ttbr1_page_table[asid][temp_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES;
|
||||
|
||||
/* Decrement number of L1 entries remaining. */
|
||||
mmu_l1_entries--;
|
||||
|
||||
/* Determine how many entries in L2 table. */
|
||||
mmu_l2_entries = ((end_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT);
|
||||
|
||||
/* Set up L2 end table. */
|
||||
for(i = 0; i < mmu_l2_entries; i++)
|
||||
{
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_CODE_PAGE_TABLE_END_OFFSET][i] = ((ULONG)end_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_CODE_ATTRIBUTES;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Fill any L1 entries between start and end pages of module code range. */
|
||||
for(i = 0; i < mmu_l1_entries; i++, level1_index++)
|
||||
{
|
||||
/* Place address and attributes in table. */
|
||||
_txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | TXM_MMU_LEVEL1_CODE_ATTRIBUTES;
|
||||
}
|
||||
|
||||
/**************************************************************************/
|
||||
/* At this point, code protection is set up. */
|
||||
/* Data protection is set up below. */
|
||||
/**************************************************************************/
|
||||
|
||||
/* Get data start and end addresses. */
|
||||
start_address = (ULONG)module_instance -> txm_module_instance_data_start;
|
||||
end_address = (ULONG)module_instance -> txm_module_instance_data_end;
|
||||
|
||||
/* How many level 1 table entries does data span? */
|
||||
mmu_l1_entries = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1;
|
||||
|
||||
/* Add 1 to align. */
|
||||
end_address++;
|
||||
|
||||
/* How many level 2 table entries does data need?
|
||||
* 0: start and end addresses both aligned.
|
||||
* 1: either start or end address aligned.
|
||||
* 2: start and end addresses both not aligned. */
|
||||
if(start_address & ~TXM_MMU_LEVEL1_MASK)
|
||||
{
|
||||
/* If start address is not aligned, increment. */
|
||||
mmu_l2_entries++;
|
||||
}
|
||||
if(end_address & ~TXM_MMU_LEVEL1_MASK)
|
||||
{
|
||||
/* If end address is not aligned, increment. */
|
||||
mmu_l2_entries++;
|
||||
}
|
||||
|
||||
/* Get index into L1 table. */
|
||||
level1_index = (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT);
|
||||
|
||||
/* Set up level 1 table. */
|
||||
/* Do start and end entries need level 2 pages? */
|
||||
if(mmu_l2_entries > 0)
|
||||
{
|
||||
/* If start_address is not aligned, we need a L2 page. */
|
||||
if(start_address & ~TXM_MMU_LEVEL1_MASK)
|
||||
{
|
||||
/* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */
|
||||
if(_txm_ttbr1_page_table[asid][level1_index] & 0x01)
|
||||
{
|
||||
/* Get L2 page address from L1 table. */
|
||||
l2_address = _txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_SECOND_MASK;
|
||||
|
||||
/* Copy the existing L2 page into the module L2 page. */
|
||||
for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++)
|
||||
{
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Translate attributes from L1 entry to an L2 entry. */
|
||||
attributes = (((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][level1_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) |
|
||||
TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE;
|
||||
|
||||
/* Build L2 page with attributes inherited from L1 entry. */
|
||||
for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++)
|
||||
{
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes;
|
||||
}
|
||||
}
|
||||
|
||||
/* Put L2 page in L1 table. */
|
||||
_txm_ttbr1_page_table[asid][level1_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES;
|
||||
|
||||
/* Decrement number of L1 entries remaining. */
|
||||
mmu_l1_entries--;
|
||||
|
||||
/* Set up L2 start table. */
|
||||
/* Determine how many entries in L2 table. */
|
||||
if((end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT))
|
||||
{
|
||||
/* End address goes to next L1 page (or beyond). */
|
||||
temp_address = ((start_address >> TXM_MMU_LEVEL1_PAGE_SHIFT) + 1) << (TXM_MMU_LEVEL1_PAGE_SHIFT);
|
||||
mmu_l2_entries = (temp_address - start_address) >> TXM_MMU_LEVEL2_PAGE_SHIFT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* End address is on the same L1 page. */
|
||||
mmu_l2_entries = (end_address >> TXM_MMU_LEVEL2_PAGE_SHIFT) - (start_address >> TXM_MMU_LEVEL2_PAGE_SHIFT);
|
||||
}
|
||||
|
||||
/* Insert module settings into start table. */
|
||||
level2_index = ((start_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT);
|
||||
for(i = 0; i < mmu_l2_entries; i++, level2_index++)
|
||||
{
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_START_OFFSET][level2_index] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (level2_index << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_DATA_ATTRIBUTES;
|
||||
}
|
||||
|
||||
level1_index++;
|
||||
}
|
||||
|
||||
/* Does last entry need a level 2 page? */
|
||||
/* If end_address is not aligned, we need a L2 page. */
|
||||
if((end_address & ~TXM_MMU_LEVEL1_MASK) && (mmu_l1_entries != 0))
|
||||
{
|
||||
/* Get index into L1 table. */
|
||||
temp_index = (end_address >> TXM_MMU_LEVEL1_PAGE_SHIFT);
|
||||
|
||||
/* Is there already a pointer to an L2 page in the L1 table? If bit 0 is set, there is. */
|
||||
if(_txm_ttbr1_page_table[asid][temp_index] & 0x01)
|
||||
{
|
||||
/* Get L2 page address from L1 table. */
|
||||
l2_address = _txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_SECOND_MASK;
|
||||
|
||||
/* Copy the existing L2 page into the module L2 page. */
|
||||
for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++)
|
||||
{
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG *) l2_address)[i] | TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Translate attributes from L1 entry to an L2 entry. */
|
||||
attributes = (((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_XN_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_XN_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_XN_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_B_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_B_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_B_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_C_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_C_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_C_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_AP_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_AP_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_AP_SHIFT) |
|
||||
(((_txm_ttbr1_page_table[asid][temp_index] & TXM_MMU_LEVEL1_ATTRIBUTE_TEX_MASK) >> TXM_MMU_LEVEL1_ATTRIBUTE_TEX_SHIFT) << TXM_MMU_LEVEL2_ATTRIBUTE_TEX_SHIFT) |
|
||||
TXM_MMU_LEVEL2_USER_ATTRIBUTE_BASE;
|
||||
|
||||
/* Build L2 page with attributes inherited from L1 entry. */
|
||||
for(i = 0; i < TXM_LEVEL_2_PAGE_TABLE_ENTRIES; i++)
|
||||
{
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG)start_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | attributes;
|
||||
}
|
||||
}
|
||||
|
||||
/* Put L2 page in L1 table. */
|
||||
_txm_ttbr1_page_table[asid][temp_index] = ((ULONG)_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET] & TXM_MMU_LEVEL1_SECOND_MASK) | TXM_MMU_LEVEL1_SECOND_ATTRIBUTES;
|
||||
|
||||
/* Decrement number of L1 entries remaining. */
|
||||
mmu_l1_entries--;
|
||||
|
||||
/* Determine how many entries in L2 table. */
|
||||
mmu_l2_entries = ((end_address & ~TXM_MMU_LEVEL1_MASK) >> TXM_MMU_LEVEL2_PAGE_SHIFT);
|
||||
|
||||
/* Set up L2 end table. */
|
||||
for(i = 0; i < mmu_l2_entries; i++)
|
||||
{
|
||||
_txm_level2_module_page_table[asid + TXM_MODULE_DATA_PAGE_TABLE_END_OFFSET][i] = ((ULONG)end_address & TXM_MMU_LEVEL1_MASK) | (i << TXM_MMU_LEVEL2_PAGE_SHIFT) | TXM_MMU_LEVEL2_DATA_ATTRIBUTES;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Fill any L1 entries between start and end pages of module data range. */
|
||||
for(i = 0; i < mmu_l1_entries; i++, level1_index++)
|
||||
{
|
||||
/* Place address and attributes in table. */
|
||||
_txm_ttbr1_page_table[asid][level1_index] = (level1_index << TXM_MMU_LEVEL1_PAGE_SHIFT) | TXM_MMU_LEVEL1_DATA_ATTRIBUTES;
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,160 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Module Manager */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_thread.h"
|
||||
;
|
||||
;
|
||||
THUMB_MASK EQU 0x20 ; Thumb bit (5) of CPSR/SPSR
|
||||
USR_MODE EQU 0x10 ; USR mode
|
||||
SYS_MODE EQU 0x1F ; SYS mode
|
||||
IF :DEF:TX_ENABLE_FIQ_SUPPORT
|
||||
CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled
|
||||
ELSE
|
||||
CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _txm_module_manager_thread_stack_build Cortex-A7/MMU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function builds a stack frame on the supplied thread's stack. */
|
||||
;/* The stack frame results in a fake interrupt return to the supplied */
|
||||
;/* function pointer. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* thread_ptr Pointer to thread control blk */
|
||||
;/* function_ptr Pointer to return function */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_thread_create Create thread service */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
|
||||
;{
|
||||
EXPORT _txm_module_manager_thread_stack_build
|
||||
_txm_module_manager_thread_stack_build
|
||||
;
|
||||
;
|
||||
; /* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
; on the Cortex-A7 should look like the following after it is built:
|
||||
;
|
||||
; Stack Top: 1 Interrupt stack frame type
|
||||
; CPSR Initial value for CPSR
|
||||
; r0 Initial value for r0
|
||||
; r1 Initial value for r1
|
||||
; r2 Initial value for r2
|
||||
; r3 Initial value for r3
|
||||
; r4 Initial value for r4
|
||||
; r5 Initial value for r5
|
||||
; r6 Initial value for r6
|
||||
; r7 Initial value for r7
|
||||
; r8 Initial value for r8
|
||||
; r9 Initial value for r9
|
||||
; r10 Initial value for r10
|
||||
; r11 Initial value for r11
|
||||
; r12 Initial value for r12
|
||||
; lr Initial value for lr (r14)
|
||||
; pc Initial value for pc (r15)
|
||||
; 0 For stack backtracing
|
||||
;
|
||||
; Stack Bottom: (higher memory address) */
|
||||
;
|
||||
LDR r2, [r0, #16] ; Pickup end of stack area
|
||||
BIC r2, r2, #7 ; Ensure 8-byte alignment
|
||||
SUB r2, r2, #76 ; Allocate space for the stack frame
|
||||
;
|
||||
; /* Actually build the stack frame. */
|
||||
;
|
||||
MOV r3, #1 ; Build interrupt stack type
|
||||
STR r3, [r2, #0] ; Store stack type
|
||||
STR r0, [r2, #8] ; Store initial r0 (thread pointer)
|
||||
LDR r3, [r0, #8] ; Pickup thread info pointer (it's in the stack pointer location right now)
|
||||
STR r3, [r2, #12] ; Store initial r1
|
||||
LDR r3, [r3, #8] ; Pickup data base register
|
||||
STR r3, [r2, #44] ; Store initial r9
|
||||
MOV r3, #0 ; Build initial register value
|
||||
STR r3, [r2, #16] ; Store initial r2
|
||||
STR r3, [r2, #20] ; Store initial r3
|
||||
STR r3, [r2, #24] ; Store initial r4
|
||||
STR r3, [r2, #28] ; Store initial r5
|
||||
STR r3, [r2, #32] ; Store initial r6
|
||||
STR r3, [r2, #36] ; Store initial r7
|
||||
STR r3, [r2, #40] ; Store initial r8
|
||||
LDR r3, [r0, #12] ; Pickup stack starting address
|
||||
STR r3, [r2, #48] ; Store initial r10 (sl)
|
||||
MOV r3, #0 ; Build initial register value
|
||||
STR r3, [r2, #52] ; Store initial r11
|
||||
STR r3, [r2, #56] ; Store initial r12
|
||||
STR r3, [r2, #60] ; Store initial lr
|
||||
STR r1, [r2, #64] ; Store initial pc
|
||||
STR r3, [r2, #68] ; 0 for back-trace
|
||||
MRS r3, CPSR ; Pickup CPSR
|
||||
BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR
|
||||
TST r1, #1 ; Test if THUMB bit set in initial PC
|
||||
ORRNE r3, r3, #THUMB_MASK ; Set T bit if set
|
||||
LDR r1, [r0, #156] ; Load tx_thread_module_current_user_mode
|
||||
TST r1, #1 ; Test if the flag is set
|
||||
ORREQ r3, r3, #SYS_MODE ; Flag not set: Build CPSR, SYS mode, IRQ enabled
|
||||
ORRNE r3, r3, #USR_MODE ; Flag set: Build CPSR, USR mode, IRQ enabled
|
||||
STR r3, [r2, #4] ; Store initial CPSR
|
||||
;
|
||||
; /* Setup stack pointer. */
|
||||
; thread_ptr -> tx_thread_stack_ptr = r2;
|
||||
;
|
||||
STR r2, [r0, #8] ; Save stack pointer in thread's control block
|
||||
BX lr ; Return to caller
|
||||
;}
|
||||
END
|
||||
|
||||
@@ -0,0 +1,92 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Module Manager */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IMPORT _txm_module_manager_kernel_dispatch
|
||||
|
||||
|
||||
AREA ||.text||, CODE, READONLY, ALIGN=12
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _txm_module_manager_user_mode_entry Cortex-A7/MMU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function allows modules to enter kernel mode. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* SVC 1 Enter kernel mode */
|
||||
;/* SVC 2 Exit kernel mode */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Modules in user mode */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
EXPORT _txm_module_manager_user_mode_entry
|
||||
EXPORT _txm_system_mode_enter
|
||||
_txm_module_manager_user_mode_entry
|
||||
_txm_system_mode_enter
|
||||
SVC 1 ; Get out of user mode
|
||||
_txm_module_priv
|
||||
; At this point, we are in system mode.
|
||||
; Save LR (and r3 for 8 byte aligned stack) and call the kernel dispatch function.
|
||||
PUSH {r3, lr}
|
||||
BL _txm_module_manager_kernel_dispatch
|
||||
POP {r3, lr}
|
||||
|
||||
EXPORT _txm_system_mode_exit
|
||||
_txm_system_mode_exit
|
||||
; Trap to restore user mode while inside of ThreadX
|
||||
SVC 2
|
||||
|
||||
BX lr ; Return to the caller
|
||||
NOP
|
||||
NOP
|
||||
|
||||
; Fill up 4kB page.
|
||||
ALIGN 4096
|
||||
_txm_module_manager_user_mode_end
|
||||
|
||||
END
|
||||
8
ports_module/cortex-m3/ac5/example_build/build.bat
Normal file
8
ports_module/cortex-m3/ac5/example_build/build.bat
Normal file
@@ -0,0 +1,8 @@
|
||||
@ECHO OFF
|
||||
ECHO Starting build...
|
||||
CALL build_threadx.bat
|
||||
CALL build_threadx_demo.bat
|
||||
CALL build_threadx_module_library.bat
|
||||
CALL build_threadx_module_demo.bat
|
||||
CALL build_threadx_module_manager_demo.bat
|
||||
ECHO Build finished.
|
||||
240
ports_module/cortex-m3/ac5/example_build/build_threadx.bat
Normal file
240
ports_module/cortex-m3/ac5/example_build/build_threadx.bat
Normal file
@@ -0,0 +1,240 @@
|
||||
del tx.a
|
||||
armasm -g --cpu=cortex-m3 --apcs=/interwork tx_initialize_low_level.S
|
||||
armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_stack_build.S
|
||||
armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_schedule.S --diag_suppress=A1581W
|
||||
armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_system_return.S
|
||||
armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_context_save.S
|
||||
armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_context_restore.S
|
||||
armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_interrupt_control.S
|
||||
armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_timer_interrupt.S
|
||||
armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_interrupt_disable.S
|
||||
armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/tx_thread_interrupt_restore.S
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_pool_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_block_release.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_pool_search.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_byte_release.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_event_flags_set_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_high_level.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_enter.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_initialize_kernel_setup.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_priority_change.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_mutex_put.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_flush.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_front_send.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_receive.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_queue_send_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_ceiling_put.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_cleanup.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_semaphore_put_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_entry_exit_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_identify.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_preemption_change.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_priority_change.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_relinquish.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_reset.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_resume.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_shell_entry.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_sleep.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_analyze.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_handler.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_stack_error_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_suspend.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_preempt_check.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_resume.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_system_suspend.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_terminate.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_time_slice_change.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_timeout.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_thread_wait_abort.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_time_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_time_set.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_activate.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_change.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_deactivate.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_expiration_process.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_performance_system_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_activate.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_system_deactivate.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_timer_thread_entry.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_enable.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_disable.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_interrupt_control.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_enter_insert.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_isr_exit_insert.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_register.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_object_unregister.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_user_event_insert.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_buffer_full_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_filter.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/tx_trace_event_unfilter.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_pool_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_block_release.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_pool_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_byte_release.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_event_flags_set_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_mutex_put.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_flush.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_front_send.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_receive.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_queue_send_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_ceiling_put.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_prioritize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_semaphore_put_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_entry_exit_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_preemption_change.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_priority_change.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_relinquish.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_reset.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_resume.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_suspend.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_terminate.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_time_slice_change.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_thread_wait_abort.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_activate.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_change.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_deactivate.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_delete.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common/inc ../../../../common/src/txe_timer_info_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_application_request.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_callback_request.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_file_load.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_in_place_load.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_internal_load.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_initialize.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_memory_load.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_allocate.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_deallocate.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_object_pool_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_properties_get.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_start.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_stop.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_create.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_thread_reset.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_unload.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_manager/src/txm_module_manager_util.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_alignment_adjust.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_external_memory_enable.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_handler.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_memory_fault_notify.c
|
||||
armcc -g -O0 --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../module_manager/src/txm_module_manager_mm_register_setup.c
|
||||
armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/txm_module_manager_thread_stack_build.S
|
||||
armasm -g --cpu=cortex-m3 --apcs=/interwork ../module_manager/src/txm_module_manager_user_mode_entry.S
|
||||
|
||||
armar --create tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o tx_initialize_low_level.o tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o
|
||||
|
||||
armar -r tx.a tx_event_flags_performance_system_info_get.o tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o
|
||||
|
||||
armar -r tx.a tx_semaphore_put_notify.o tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o
|
||||
|
||||
armar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o
|
||||
|
||||
armar -r tx.a txe_queue_prioritize.o txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o txm_module_manager_alignment_adjust.o txm_module_manager_application_request.o txm_module_manager_callback_request.o txm_module_manager_event_flags_notify_trampoline.o txm_module_manager_external_memory_enable.o txm_module_manager_file_load.o txm_module_manager_in_place_load.o
|
||||
|
||||
armar -r tx.a txm_module_manager_initialize.o txm_module_manager_kernel_dispatch.o txm_module_manager_maximum_module_priority_set.o txm_module_manager_memory_fault_handler.o txm_module_manager_memory_fault_notify.o txm_module_manager_memory_load.o txm_module_manager_object_pointer_get.o txm_module_manager_object_pool_create.o txm_module_manager_queue_notify_trampoline.o txm_module_manager_semaphore_notify_trampoline.o txm_module_manager_mm_register_setup.o txm_module_manager_start.o txm_module_manager_stop.o txm_module_manager_thread_create.o txm_module_manager_thread_notify_trampoline.o txm_module_manager_thread_reset.o txm_module_manager_timer_notify_trampoline.o txm_module_manager_unload.o txm_module_manager_thread_stack_build.o txm_module_manager_internal_load.o txm_module_manager_object_allocate.o txm_module_manager_object_deallocate.o txm_module_manager_object_pointer_get_extended.o txm_module_manager_properties_get.o txm_module_manager_util.o txm_module_manager_user_mode_entry.o
|
||||
@@ -0,0 +1,4 @@
|
||||
armasm -g --cpu=cortex-m3 --apcs=interwork tx_initialize_low_level.S
|
||||
armcc -c -g --cpu=cortex-m3 -O2 -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx.c
|
||||
armlink -d -o sample_threadx.axf --elf --map --ro-base=0x00000000 --rw-base=0x20000000 --first __tx_vectors --datacompressor=off --inline --info=inline --callgraph --list sample_threadx.map tx_initialize_low_level.o sample_threadx.o tx.a
|
||||
|
||||
@@ -0,0 +1,3 @@
|
||||
armasm -g --cpu=cortex-m3 --apcs=/interwork/ropi/rwpi txm_module_preamble.S
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi --lower_ropi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx_module.c
|
||||
armlink -d -o sample_threadx_module.axf --elf --ro=0x30000 --rw=0x40000 --first txm_module_preamble.o(Init) --entry=_txm_module_thread_shell_entry --ropi --rwpi --remove --map --symbols --list sample_threadx_module.map txm_module_preamble.o sample_threadx_module.o txm.a
|
||||
@@ -0,0 +1,106 @@
|
||||
del txm.a
|
||||
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_allocate.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_create.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_delete.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_pool_prioritize.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_block_release.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_allocate.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_create.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_delete.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_pool_prioritize.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_byte_release.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_create.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_delete.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_set.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_event_flags_set_notify.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_application_request.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_callback_request_thread_entry.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_allocate.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_deallocate.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_object_pointer_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_module_thread_system_suspend.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_create.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_delete.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_prioritize.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_mutex_put.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_create.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_delete.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_flush.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_front_send.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_prioritize.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_receive.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_send.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_queue_send_notify.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_ceiling_put.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_create.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_delete.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_prioritize.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_put.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_semaphore_put_notify.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_create.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_delete.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_entry_exit_notify.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_identify.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_interrupt_control.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_preemption_change.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_priority_change.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_relinquish.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_reset.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_resume.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_sleep.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_stack_error_notify.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_suspend.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_terminate.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_time_slice_change.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_thread_wait_abort.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_time_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_time_set.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_activate.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_change.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_create.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_deactivate.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_delete.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_performance_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_timer_performance_system_info_get.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_buffer_full_notify.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_disable.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_enable.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_event_filter.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_event_unfilter.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_isr_enter_insert.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_isr_exit_insert.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ../../../../common_modules/module_lib/src/txm_trace_user_event_insert.c
|
||||
armcc -g --cpu=cortex-m3 -c --apcs=/interwork/ropi/rwpi -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc ..//module_lib/src/txm_module_thread_shell_entry.c
|
||||
armasm -g --cpu=cortex-m3 --apcs=/interwork/ropi/rwpi --cpreproc --cpreproc_opts=-D,TXM_ASSEMBLY --cpreproc_opts=-D,TXM_MODULE_HEAP_SIZE=512 -I../inc ../module_lib/src/txm_module_initialize.S
|
||||
|
||||
armar --create txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o txm_block_pool_prioritize.o txm_block_release.o txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o txm_byte_pool_prioritize.o txm_byte_release.o txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o txm_event_flags_set.o txm_event_flags_set_notify.o txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_initialize.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o
|
||||
|
||||
armar -r txm.a txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o
|
||||
|
||||
armar -r txm.a txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o txm_time_get.o txm_time_set.o txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o
|
||||
@@ -0,0 +1,3 @@
|
||||
armasm -g --cpu=cortex-m3 --apcs=interwork tx_initialize_low_level.S
|
||||
armcc -g --cpu=cortex-m3 -c -I../inc -I../../../../common_modules/inc -I../../../../common_modules/module_manager/inc -I../../../../common/inc sample_threadx_module_manager.c
|
||||
armlink -d -o sample_threadx_module_manager.axf --elf --ro 0x00000000 --first tx_initialize_low_level.o(RESET) --remove --map --symbols --list sample_threadx_module_manager.map tx_initialize_low_level.o sample_threadx_module_manager.o tx.a
|
||||
2
ports_module/cortex-m3/ac5/example_build/clean.bat
Normal file
2
ports_module/cortex-m3/ac5/example_build/clean.bat
Normal file
@@ -0,0 +1,2 @@
|
||||
@ECHO OFF
|
||||
DEL *.o *.a *.axf *.map
|
||||
369
ports_module/cortex-m3/ac5/example_build/sample_threadx.c
Normal file
369
ports_module/cortex-m3/ac5/example_build/sample_threadx.c
Normal file
@@ -0,0 +1,369 @@
|
||||
/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
|
||||
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
|
||||
byte pool, and block pool. */
|
||||
|
||||
#include "tx_api.h"
|
||||
|
||||
#define DEMO_STACK_SIZE 1024
|
||||
#define DEMO_BYTE_POOL_SIZE 9120
|
||||
#define DEMO_BLOCK_POOL_SIZE 100
|
||||
#define DEMO_QUEUE_SIZE 100
|
||||
|
||||
|
||||
/* Define the ThreadX object control blocks... */
|
||||
|
||||
TX_THREAD thread_0;
|
||||
TX_THREAD thread_1;
|
||||
TX_THREAD thread_2;
|
||||
TX_THREAD thread_3;
|
||||
TX_THREAD thread_4;
|
||||
TX_THREAD thread_5;
|
||||
TX_THREAD thread_6;
|
||||
TX_THREAD thread_7;
|
||||
TX_QUEUE queue_0;
|
||||
TX_SEMAPHORE semaphore_0;
|
||||
TX_MUTEX mutex_0;
|
||||
TX_EVENT_FLAGS_GROUP event_flags_0;
|
||||
TX_BYTE_POOL byte_pool_0;
|
||||
TX_BLOCK_POOL block_pool_0;
|
||||
|
||||
|
||||
/* Define the counters used in the demo application... */
|
||||
|
||||
ULONG thread_0_counter;
|
||||
ULONG thread_1_counter;
|
||||
ULONG thread_1_messages_sent;
|
||||
ULONG thread_2_counter;
|
||||
ULONG thread_2_messages_received;
|
||||
ULONG thread_3_counter;
|
||||
ULONG thread_4_counter;
|
||||
ULONG thread_5_counter;
|
||||
ULONG thread_6_counter;
|
||||
ULONG thread_7_counter;
|
||||
|
||||
|
||||
/* Define thread prototypes. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input);
|
||||
void thread_1_entry(ULONG thread_input);
|
||||
void thread_2_entry(ULONG thread_input);
|
||||
void thread_3_and_4_entry(ULONG thread_input);
|
||||
void thread_5_entry(ULONG thread_input);
|
||||
void thread_6_and_7_entry(ULONG thread_input);
|
||||
|
||||
|
||||
/* Define main entry point. */
|
||||
|
||||
int main()
|
||||
{
|
||||
|
||||
/* Enter the ThreadX kernel. */
|
||||
tx_kernel_enter();
|
||||
}
|
||||
|
||||
|
||||
/* Define what the initial system looks like. */
|
||||
|
||||
void tx_application_define(void *first_unused_memory)
|
||||
{
|
||||
|
||||
CHAR *pointer = TX_NULL;
|
||||
|
||||
|
||||
/* Create a byte memory pool from which to allocate the thread stacks. */
|
||||
tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE);
|
||||
|
||||
/* Put system definition stuff in here, e.g. thread creates and other assorted
|
||||
create information. */
|
||||
|
||||
/* Allocate the stack for thread 0. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create the main thread. */
|
||||
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
|
||||
/* Allocate the stack for thread 1. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 1 and 2. These threads pass information through a ThreadX
|
||||
message queue. It is also interesting to note that these threads have a time
|
||||
slice. */
|
||||
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 2. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 3. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
|
||||
An interesting thing here is that both threads share the same instruction area. */
|
||||
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 4. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 5. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create thread 5. This thread simply pends on an event flag which will be set
|
||||
by thread_0. */
|
||||
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 6. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
|
||||
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 7. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the message queue. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
|
||||
|
||||
/* Create the message queue shared by threads 1 and 2. */
|
||||
tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
|
||||
|
||||
/* Create the semaphore used by threads 3 and 4. */
|
||||
tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
|
||||
|
||||
/* Create the event flags group used by threads 1 and 5. */
|
||||
tx_event_flags_create(&event_flags_0, "event flags 0");
|
||||
|
||||
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
|
||||
tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
|
||||
|
||||
/* Allocate the memory for a small block pool. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create a block memory pool to allocate a message buffer from. */
|
||||
tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
|
||||
|
||||
/* Allocate a block and release the block memory. */
|
||||
tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
|
||||
|
||||
/* Release the block back to the pool. */
|
||||
tx_block_release(pointer);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Define the test threads. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This thread simply sits in while-forever-sleep loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_0_counter++;
|
||||
|
||||
/* Sleep for 10 ticks. */
|
||||
tx_thread_sleep(10);
|
||||
|
||||
/* Set event flag 0 to wakeup thread 5. */
|
||||
status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_1_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This thread simply sends messages to a queue shared by thread 2. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_1_counter++;
|
||||
|
||||
/* Send message to queue 0. */
|
||||
status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Increment the message sent. */
|
||||
thread_1_messages_sent++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_2_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
ULONG received_message;
|
||||
UINT status;
|
||||
|
||||
/* This thread retrieves messages placed on the queue by thread 1. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_2_counter++;
|
||||
|
||||
/* Retrieve a message from the queue. */
|
||||
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status and make sure the message is what we
|
||||
expected. */
|
||||
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
|
||||
break;
|
||||
|
||||
/* Otherwise, all is okay. Increment the received message count. */
|
||||
thread_2_messages_received++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_3_and_4_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 3 and thread 4. As the loop
|
||||
below shows, these function compete for ownership of semaphore_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 3)
|
||||
thread_3_counter++;
|
||||
else
|
||||
thread_4_counter++;
|
||||
|
||||
/* Get the semaphore with suspension. */
|
||||
status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the semaphore. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the semaphore. */
|
||||
status = tx_semaphore_put(&semaphore_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_5_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
ULONG actual_flags;
|
||||
|
||||
|
||||
/* This thread simply waits for an event in a forever loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_5_counter++;
|
||||
|
||||
/* Wait for event flag 0. */
|
||||
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
|
||||
&actual_flags, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_6_and_7_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 6 and thread 7. As the loop
|
||||
below shows, these function compete for ownership of mutex_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 6)
|
||||
thread_6_counter++;
|
||||
else
|
||||
thread_7_counter++;
|
||||
|
||||
/* Get the mutex with suspension. */
|
||||
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Get the mutex again with suspension. This shows
|
||||
that an owning thread may retrieve the mutex it
|
||||
owns multiple times. */
|
||||
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the mutex. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the mutex. */
|
||||
status = tx_mutex_put(&mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Release the mutex again. This will actually
|
||||
release ownership since it was obtained twice. */
|
||||
status = tx_mutex_put(&mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
432
ports_module/cortex-m3/ac5/example_build/sample_threadx_module.c
Normal file
432
ports_module/cortex-m3/ac5/example_build/sample_threadx_module.c
Normal file
@@ -0,0 +1,432 @@
|
||||
/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes
|
||||
examples of eight threads of different priorities, using a message queue, semaphore, mutex,
|
||||
event flags group, byte pool, and block pool. */
|
||||
|
||||
/* Specify that this is a module! */
|
||||
|
||||
#define TXM_MODULE
|
||||
|
||||
|
||||
/* Include the ThreadX module definitions. */
|
||||
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/* Define constants. */
|
||||
|
||||
#define DEMO_STACK_SIZE 1024
|
||||
#define DEMO_BYTE_POOL_SIZE 9120
|
||||
#define DEMO_BLOCK_POOL_SIZE 100
|
||||
#define DEMO_QUEUE_SIZE 100
|
||||
|
||||
|
||||
/* Define the external memory area. */
|
||||
|
||||
#define EXTERNAL_MEMORY_SIZE (64 * 1024)
|
||||
#define EXTERNAL_MEMORY (0x80000)
|
||||
|
||||
|
||||
/* Define the pool space in the bss section of the module. ULONG is used to
|
||||
get the word alignment. */
|
||||
|
||||
ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4];
|
||||
|
||||
|
||||
/* Define the ThreadX object control blocks... */
|
||||
|
||||
TX_THREAD *thread_0;
|
||||
TX_THREAD *thread_1;
|
||||
TX_THREAD *thread_2;
|
||||
TX_THREAD *thread_3;
|
||||
TX_THREAD *thread_4;
|
||||
TX_THREAD *thread_5;
|
||||
TX_THREAD *thread_6;
|
||||
TX_THREAD *thread_7;
|
||||
TX_QUEUE *queue_0;
|
||||
TX_SEMAPHORE *semaphore_0;
|
||||
TX_MUTEX *mutex_0;
|
||||
TX_EVENT_FLAGS_GROUP *event_flags_0;
|
||||
TX_BYTE_POOL *byte_pool_0;
|
||||
TX_BLOCK_POOL *block_pool_0;
|
||||
|
||||
|
||||
/* Define the counters used in the demo application... */
|
||||
|
||||
ULONG thread_0_counter;
|
||||
ULONG thread_1_counter;
|
||||
ULONG thread_1_messages_sent;
|
||||
ULONG thread_2_counter;
|
||||
ULONG thread_2_messages_received;
|
||||
ULONG thread_3_counter;
|
||||
ULONG thread_4_counter;
|
||||
ULONG thread_5_counter;
|
||||
ULONG thread_6_counter;
|
||||
ULONG thread_7_counter;
|
||||
ULONG semaphore_0_puts;
|
||||
ULONG event_0_sets;
|
||||
ULONG queue_0_sends;
|
||||
|
||||
/* Define thread prototypes. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input);
|
||||
void thread_1_entry(ULONG thread_input);
|
||||
void thread_2_entry(ULONG thread_input);
|
||||
void thread_3_and_4_entry(ULONG thread_input);
|
||||
void thread_5_entry(ULONG thread_input);
|
||||
void thread_6_and_7_entry(ULONG thread_input);
|
||||
|
||||
void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr)
|
||||
{
|
||||
|
||||
if (semaphore_ptr == semaphore_0)
|
||||
semaphore_0_puts++;
|
||||
}
|
||||
|
||||
|
||||
void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr)
|
||||
{
|
||||
|
||||
if (event_flag_group_ptr == event_flags_0)
|
||||
event_0_sets++;
|
||||
}
|
||||
|
||||
|
||||
void queue_0_notify(TX_QUEUE *queue_ptr)
|
||||
{
|
||||
|
||||
if (queue_ptr == queue_0)
|
||||
queue_0_sends++;
|
||||
}
|
||||
|
||||
|
||||
/* Define the module start function. */
|
||||
|
||||
void demo_module_start(ULONG id)
|
||||
{
|
||||
|
||||
CHAR *pointer;
|
||||
|
||||
/* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within
|
||||
their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting
|
||||
the control block(s). */
|
||||
txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE));
|
||||
txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE));
|
||||
txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX));
|
||||
txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP));
|
||||
txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL));
|
||||
txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL));
|
||||
|
||||
|
||||
/* Create a byte memory pool from which to allocate the thread stacks. */
|
||||
tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE);
|
||||
|
||||
/* Put system definition stuff in here, e.g. thread creates and other assorted
|
||||
create information. */
|
||||
|
||||
/* Allocate the stack for thread 0. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create the main thread. */
|
||||
tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
|
||||
/* Allocate the stack for thread 1. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 1 and 2. These threads pass information through a ThreadX
|
||||
message queue. It is also interesting to note that these threads have a time
|
||||
slice. */
|
||||
tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 2. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 3. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
|
||||
An interesting thing here is that both threads share the same instruction area. */
|
||||
tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 4. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 5. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create thread 5. This thread simply pends on an event flag which will be set
|
||||
by thread_0. */
|
||||
tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 6. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
|
||||
tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 7. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the message queue. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
|
||||
|
||||
/* Create the message queue shared by threads 1 and 2. */
|
||||
tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
|
||||
|
||||
tx_queue_send_notify(queue_0, queue_0_notify);
|
||||
|
||||
/* Create the semaphore used by threads 3 and 4. */
|
||||
tx_semaphore_create(semaphore_0, "module semaphore 0", 1);
|
||||
|
||||
tx_semaphore_put_notify(semaphore_0, semaphore_0_notify);
|
||||
|
||||
/* Create the event flags group used by threads 1 and 5. */
|
||||
tx_event_flags_create(event_flags_0, "module event flags 0");
|
||||
|
||||
tx_event_flags_set_notify(event_flags_0, event_0_notify);
|
||||
|
||||
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
|
||||
tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT);
|
||||
|
||||
/* Allocate the memory for a small block pool. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create a block memory pool to allocate a message buffer from. */
|
||||
tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
|
||||
|
||||
/* Allocate a block and release the block memory. */
|
||||
tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
|
||||
|
||||
/* Release the block back to the pool. */
|
||||
tx_block_release(pointer);
|
||||
}
|
||||
|
||||
|
||||
/* Define the test threads. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
/* This thread simply sits in while-forever-sleep loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_0_counter++;
|
||||
|
||||
/* Sleep for 10 ticks. */
|
||||
tx_thread_sleep(10);
|
||||
|
||||
/* Set event flag 0 to wakeup thread 5. */
|
||||
status = tx_event_flags_set(event_flags_0, 0x1, TX_OR);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_1_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This thread simply sends messages to a queue shared by thread 2. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_1_counter++;
|
||||
|
||||
/* Send message to queue 0. */
|
||||
status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Increment the message sent. */
|
||||
thread_1_messages_sent++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_2_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
ULONG received_message;
|
||||
UINT status;
|
||||
|
||||
/* This thread retrieves messages placed on the queue by thread 1. */
|
||||
while(1)
|
||||
{
|
||||
/* Test external memory sharing. */
|
||||
*(ULONG *)EXTERNAL_MEMORY = 0xABABABAB;
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_2_counter++;
|
||||
|
||||
/* Retrieve a message from the queue. */
|
||||
status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status and make sure the message is what we
|
||||
expected. */
|
||||
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
|
||||
break;
|
||||
|
||||
/* Otherwise, all is okay. Increment the received message count. */
|
||||
thread_2_messages_received++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_3_and_4_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 3 and thread 4. As the loop
|
||||
below shows, these function compete for ownership of semaphore_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 3)
|
||||
thread_3_counter++;
|
||||
else
|
||||
thread_4_counter++;
|
||||
|
||||
/* Get the semaphore with suspension. */
|
||||
status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the semaphore. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the semaphore. */
|
||||
status = tx_semaphore_put(semaphore_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_5_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
ULONG actual_flags;
|
||||
|
||||
|
||||
/* This thread simply waits for an event in a forever loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_5_counter++;
|
||||
|
||||
/* Wait for event flag 0. */
|
||||
status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR,
|
||||
&actual_flags, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_6_and_7_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 6 and thread 7. As the loop
|
||||
below shows, these function compete for ownership of mutex_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 6)
|
||||
thread_6_counter++;
|
||||
else
|
||||
thread_7_counter++;
|
||||
|
||||
/* Get the mutex with suspension. */
|
||||
status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Get the mutex again with suspension. This shows
|
||||
that an owning thread may retrieve the mutex it
|
||||
owns multiple times. */
|
||||
status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the mutex. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the mutex. */
|
||||
status = tx_mutex_put(mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Release the mutex again. This will actually
|
||||
release ownership since it was obtained twice. */
|
||||
status = tx_mutex_put(mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,126 @@
|
||||
/* Small demonstration of the ThreadX module manager. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
#define DEMO_STACK_SIZE 1024
|
||||
|
||||
/* Define the ThreadX object control blocks... */
|
||||
|
||||
TX_THREAD module_manager;
|
||||
TXM_MODULE_INSTANCE my_module;
|
||||
|
||||
|
||||
/* Define the object pool area. */
|
||||
|
||||
UCHAR object_memory[16384];
|
||||
|
||||
|
||||
/* Define the module data pool area. */
|
||||
|
||||
#define MODULE_DATA_SIZE (256 * 1024)
|
||||
#define MODULE_DATA (0x40000)
|
||||
|
||||
|
||||
/* The module code should be loaded here. */
|
||||
|
||||
#define MODULE_CODE (0x30000)
|
||||
|
||||
|
||||
/* Define the external memory area. */
|
||||
|
||||
#define EXTERNAL_MEMORY_SIZE (64 * 1024)
|
||||
#define EXTERNAL_MEMORY (0x80000)
|
||||
|
||||
|
||||
/* Define the count of memory faults. */
|
||||
|
||||
ULONG memory_faults;
|
||||
|
||||
|
||||
/* Define thread prototypes. */
|
||||
|
||||
void module_manager_entry(ULONG thread_input);
|
||||
|
||||
|
||||
/* Define fault handler. */
|
||||
|
||||
VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module)
|
||||
{
|
||||
|
||||
/* Just increment the fault counter. */
|
||||
memory_faults++;
|
||||
}
|
||||
|
||||
/* Define main entry point. */
|
||||
|
||||
int main()
|
||||
{
|
||||
|
||||
/* Enter the ThreadX kernel. */
|
||||
tx_kernel_enter();
|
||||
}
|
||||
|
||||
|
||||
/* Define what the initial system looks like. */
|
||||
|
||||
void tx_application_define(void *first_unused_memory)
|
||||
{
|
||||
|
||||
CHAR *pointer = (CHAR*)first_unused_memory;
|
||||
|
||||
|
||||
tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
pointer = pointer + DEMO_STACK_SIZE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* Define the test threads. */
|
||||
|
||||
void module_manager_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
/* Initialize the module manager. */
|
||||
txm_module_manager_initialize((void *) MODULE_DATA, MODULE_DATA_SIZE);
|
||||
|
||||
txm_module_manager_object_pool_create(object_memory, sizeof(object_memory));
|
||||
|
||||
/* Register a fault handler. */
|
||||
txm_module_manager_memory_fault_notify(module_fault_handler);
|
||||
|
||||
/* Load the module that is already there, in this example it is placed there by the multiple image download. */
|
||||
txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE);
|
||||
|
||||
/* Enable a read/write shared memory region. */
|
||||
txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE);
|
||||
|
||||
/* Start the module. */
|
||||
txm_module_manager_start(&my_module);
|
||||
|
||||
/* Sleep for a while.... */
|
||||
tx_thread_sleep(1000);
|
||||
|
||||
/* Stop the module. */
|
||||
txm_module_manager_stop(&my_module);
|
||||
|
||||
/* Unload the module. */
|
||||
txm_module_manager_unload(&my_module);
|
||||
|
||||
/* Load the module that is already there. */
|
||||
txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE);
|
||||
|
||||
/* Start the module again. */
|
||||
txm_module_manager_start(&my_module);
|
||||
|
||||
/* Now just spin... */
|
||||
while(1)
|
||||
{
|
||||
|
||||
tx_thread_sleep(100);
|
||||
}
|
||||
}
|
||||
13
ports_module/cortex-m3/ac5/example_build/setenv.bat
Normal file
13
ports_module/cortex-m3/ac5/example_build/setenv.bat
Normal file
@@ -0,0 +1,13 @@
|
||||
@echo off
|
||||
|
||||
REM *** ARM DS 2020
|
||||
REM SET PATH=%ProgramFiles%\Arm\Development Studio 2020.0\sw\ARMCompiler5.06u6\bin;%PATH%
|
||||
REM SET ARMLMD_LICENSE_FILE=%APPDATA%\arm\ds\licenses
|
||||
REM SET ARM_CONFIG_PATH=%APPDATA%\arm\ds\2020.0
|
||||
REM SET ARM_PRODUCT_DEF=%ProgramFiles%\Arm\Development Studio 2020.0\sw\mappings\gold.elmap
|
||||
|
||||
REM *** legacy ARM DS 5
|
||||
SET PATH=%ProgramFiles%\DS-5 v5.29.3\sw\ARMCompiler5.06u6\bin;%PATH%
|
||||
SET ARMLMD_LICENSE_FILE=%APPDATA%\ARM\DS-5\licenses
|
||||
SET ARM_CONFIG_PATH=%APPDATA%\ARM\DS-5_v5.29.3
|
||||
SET ARM_PRODUCT_PATH=%ProgramFiles%\DS-5 v5.29.3\sw\mappings
|
||||
@@ -0,0 +1,285 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Initialize */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;#define TX_SOURCE_CODE
|
||||
;
|
||||
;
|
||||
;/* Include necessary system files. */
|
||||
;
|
||||
;#include "tx_api.h"
|
||||
;#include "tx_initialize.h"
|
||||
;#include "tx_thread.h"
|
||||
;#include "tx_timer.h"
|
||||
;
|
||||
;
|
||||
IMPORT _tx_thread_system_stack_ptr
|
||||
IMPORT _tx_initialize_unused_memory
|
||||
IMPORT _tx_thread_context_save
|
||||
IMPORT _tx_thread_context_restore
|
||||
IMPORT _tx_timer_interrupt
|
||||
IMPORT __main
|
||||
IMPORT |Image$$RO$$Limit|
|
||||
IMPORT |Image$$RW$$Base|
|
||||
IMPORT |Image$$ZI$$Base|
|
||||
IMPORT |Image$$ZI$$Limit|
|
||||
IMPORT __tx_PendSVHandler
|
||||
IMPORT __tx_SVCallHandler
|
||||
IMPORT MemManage_Handler
|
||||
;
|
||||
;
|
||||
SYSTEM_CLOCK EQU 6000000
|
||||
SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1)
|
||||
;
|
||||
;
|
||||
;/* Setup the stack and heap areas. */
|
||||
;
|
||||
STACK_SIZE EQU 0x00000400
|
||||
HEAP_SIZE EQU 0x00000000
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
StackMem
|
||||
SPACE STACK_SIZE
|
||||
__initial_sp
|
||||
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
HeapMem
|
||||
SPACE HEAP_SIZE
|
||||
__heap_limit
|
||||
|
||||
|
||||
AREA RESET, CODE, READONLY
|
||||
;
|
||||
EXPORT __tx_vectors
|
||||
EXPORT __vector_table
|
||||
__vector_table
|
||||
__tx_vectors
|
||||
DCD __initial_sp ; Reset and system stack ptr
|
||||
DCD Reset_Handler ; Reset goes to startup function
|
||||
DCD __tx_NMIHandler ; NMI
|
||||
DCD __tx_BadHandler ; HardFault
|
||||
DCD MemManage_Handler ; MemManage
|
||||
DCD 0 ; BusFault
|
||||
DCD 0 ; UsageFault
|
||||
DCD 0 ; 7
|
||||
DCD 0 ; 8
|
||||
DCD 0 ; 9
|
||||
DCD 0 ; 10
|
||||
DCD __tx_SVCallHandler ; SVCall
|
||||
DCD __tx_DBGHandler ; Monitor
|
||||
DCD 0 ; 13
|
||||
DCD __tx_PendSVHandler ; PendSV
|
||||
DCD __tx_SysTickHandler ; SysTick
|
||||
DCD __tx_IntHandler ; Int 0
|
||||
DCD __tx_IntHandler ; Int 1
|
||||
DCD __tx_IntHandler ; Int 2
|
||||
DCD __tx_IntHandler ; Int 3
|
||||
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
EXPORT Reset_Handler
|
||||
Reset_Handler
|
||||
CPSID i
|
||||
IF {TARGET_FPU_VFP} = {TRUE}
|
||||
LDR r0, =0xE000ED88 ; Pickup address of CPACR
|
||||
LDR r1, [r0] ; Pickup CPACR
|
||||
MOV32 r2, 0x00F00000 ; Build enable value
|
||||
ORR r1, r1, r2 ; Or in enable value
|
||||
STR r1, [r0] ; Setup CPACR
|
||||
ENDIF
|
||||
LDR r0, =__main
|
||||
BX r0
|
||||
|
||||
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_initialize_low_level Cortex-M3/MPU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for any low-level processor */
|
||||
;/* initialization, including setting up interrupt vectors, setting */
|
||||
;/* up a periodic timer interrupt source, saving the system stack */
|
||||
;/* pointer for use in ISR processing later, and finding the first */
|
||||
;/* available RAM memory address for tx_application_define. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_initialize_low_level(VOID)
|
||||
;{
|
||||
EXPORT _tx_initialize_low_level
|
||||
_tx_initialize_low_level
|
||||
;
|
||||
; /* Disable interrupts during ThreadX initialization. */
|
||||
;
|
||||
CPSID i
|
||||
;
|
||||
; /* Set base of available memory to end of non-initialised RAM area. */
|
||||
;
|
||||
LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer
|
||||
LDR r1, =|Image$$ZI$$Limit| ; Build first free address
|
||||
ADD r1, r1, #4 ;
|
||||
STR r1, [r0] ; Setup first unused memory pointer
|
||||
;
|
||||
; /* Setup Vector Table Offset Register. */
|
||||
;
|
||||
MOV r0, #0xE000E000 ; Build address of NVIC registers
|
||||
LDR r1, =__tx_vectors ; Pickup address of vector table
|
||||
STR r1, [r0, #0xD08] ; Set vector table address
|
||||
;
|
||||
; /* Enable the cycle count register. */
|
||||
;
|
||||
; LDR r0, =0xE0001000 ; Build address of DWT register
|
||||
; LDR r1, [r0] ; Pickup the current value
|
||||
; ORR r1, r1, #1 ; Set the CYCCNTENA bit
|
||||
; STR r1, [r0] ; Enable the cycle count register
|
||||
;
|
||||
; /* Set system stack pointer from vector value. */
|
||||
;
|
||||
LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer
|
||||
LDR r1, =__tx_vectors ; Pickup address of vector table
|
||||
LDR r1, [r1] ; Pickup reset stack pointer
|
||||
STR r1, [r0] ; Save system stack pointer
|
||||
;
|
||||
; /* Configure SysTick. */
|
||||
;
|
||||
MOV r0, #0xE000E000 ; Build address of NVIC registers
|
||||
LDR r1, =SYSTICK_CYCLES
|
||||
STR r1, [r0, #0x14] ; Setup SysTick Reload Value
|
||||
MOV r1, #0x7 ; Build SysTick Control Enable Value
|
||||
STR r1, [r0, #0x10] ; Setup SysTick Control
|
||||
;
|
||||
; /* Configure handler priorities. */
|
||||
;
|
||||
LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM
|
||||
STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers
|
||||
|
||||
LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv
|
||||
STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers
|
||||
; Note: SVC must be lowest priority, which is 0xFF
|
||||
|
||||
LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM
|
||||
STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers
|
||||
; Note: PnSV must be lowest priority, which is 0xFF
|
||||
;
|
||||
; /* Return to caller. */
|
||||
;
|
||||
BX lr
|
||||
;}
|
||||
;
|
||||
;
|
||||
;/* Define initial heap/stack routine for the ARM RVCT startup code.
|
||||
; This routine will set the initial stack and heap locations */
|
||||
;
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
LDR r0, =HeapMem
|
||||
LDR r1, =(StackMem + STACK_SIZE)
|
||||
LDR r2, =(HeapMem + HEAP_SIZE)
|
||||
LDR r3, =StackMem
|
||||
BX lr
|
||||
;
|
||||
;
|
||||
;/* Define shells for each of the unused vectors. */
|
||||
;
|
||||
EXPORT __tx_BadHandler
|
||||
__tx_BadHandler
|
||||
B __tx_BadHandler
|
||||
|
||||
; EXPORT __tx_SVCallHandler
|
||||
;__tx_SVCallHandler
|
||||
; B __tx_SVCallHandler
|
||||
|
||||
EXPORT __tx_IntHandler
|
||||
__tx_IntHandler
|
||||
; VOID InterruptHandler (VOID)
|
||||
; {
|
||||
PUSH {lr}
|
||||
|
||||
; /* Do interrupt handler work here */
|
||||
; /* .... */
|
||||
|
||||
POP {lr}
|
||||
BX LR
|
||||
; }
|
||||
|
||||
EXPORT __tx_SysTickHandler
|
||||
__tx_SysTickHandler
|
||||
; VOID TimerInterruptHandler (VOID)
|
||||
; {
|
||||
;
|
||||
PUSH {lr}
|
||||
BL _tx_timer_interrupt
|
||||
POP {lr}
|
||||
BX LR
|
||||
; }
|
||||
|
||||
EXPORT __tx_NMIHandler
|
||||
__tx_NMIHandler
|
||||
B __tx_NMIHandler
|
||||
|
||||
EXPORT __tx_DBGHandler
|
||||
__tx_DBGHandler
|
||||
B __tx_DBGHandler
|
||||
|
||||
EXPORT _tx_execution_thread_enter
|
||||
_tx_execution_thread_enter
|
||||
BX LR
|
||||
|
||||
EXPORT _tx_execution_thread_exit
|
||||
_tx_execution_thread_exit
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
LTORG
|
||||
END
|
||||
|
||||
|
||||
@@ -0,0 +1,69 @@
|
||||
AREA Init, CODE, READONLY
|
||||
|
||||
PRESERVE8
|
||||
|
||||
; Define public symbols
|
||||
|
||||
EXPORT __txm_module_preamble
|
||||
|
||||
|
||||
; Define application-specific start/stop entry points for the module
|
||||
|
||||
EXTERN demo_module_start
|
||||
|
||||
|
||||
; Define common external references
|
||||
|
||||
IMPORT _txm_module_thread_shell_entry
|
||||
IMPORT _txm_module_callback_request_thread_entry
|
||||
IMPORT |Image$$ER_RO$$Length|
|
||||
IMPORT |Image$$ER_RW$$Length|
|
||||
IMPORT |Image$$ER_RW$$RW$$Length|
|
||||
IMPORT |Image$$ER_RW$$ZI$$Length|
|
||||
IMPORT |Image$$ER_ZI$$ZI$$Length|
|
||||
|
||||
__txm_module_preamble
|
||||
DCD 0x4D4F4455 ; Module ID
|
||||
DCD 0x6 ; Module Major Version
|
||||
DCD 0x1 ; Module Minor Version
|
||||
DCD 32 ; Module Preamble Size in 32-bit words
|
||||
DCD 0x12345678 ; Module ID (application defined)
|
||||
DCD 0x01000007 ; Module Properties where:
|
||||
; Bits 31-24: Compiler ID
|
||||
; 0 -> IAR
|
||||
; 1 -> ARM
|
||||
; 2 -> GNU
|
||||
; Bit 0: 0 -> Privileged mode execution
|
||||
; 1 -> User mode execution
|
||||
; Bit 1: 0 -> No MPU protection
|
||||
; 1 -> MPU protection (must have user mode selected)
|
||||
; Bit 2: 0 -> Disable shared/external memory access
|
||||
; 1 -> Enable shared/external memory access
|
||||
DCD _txm_module_thread_shell_entry - __txm_module_preamble ; Module Shell Entry Point
|
||||
DCD demo_module_start - __txm_module_preamble ; Module Start Thread Entry Point
|
||||
DCD 0 ; Module Stop Thread Entry Point
|
||||
DCD 1 ; Module Start/Stop Thread Priority
|
||||
DCD 1024 ; Module Start/Stop Thread Stack Size
|
||||
DCD _txm_module_callback_request_thread_entry - __txm_module_preamble ; Module Callback Thread Entry
|
||||
DCD 1 ; Module Callback Thread Priority
|
||||
DCD 1024 ; Module Callback Thread Stack Size
|
||||
DCD |Image$$ER_RO$$Length| + |Image$$ER_RW$$Length| ; Module Code Size
|
||||
DCD |Image$$ER_RW$$Length| + |Image$$ER_ZI$$ZI$$Length| ; Module Data Size
|
||||
DCD 0 ; Reserved 0
|
||||
DCD 0 ; Reserved 1
|
||||
DCD 0 ; Reserved 2
|
||||
DCD 0 ; Reserved 3
|
||||
DCD 0 ; Reserved 4
|
||||
DCD 0 ; Reserved 5
|
||||
DCD 0 ; Reserved 6
|
||||
DCD 0 ; Reserved 7
|
||||
DCD 0 ; Reserved 8
|
||||
DCD 0 ; Reserved 9
|
||||
DCD 0 ; Reserved 10
|
||||
DCD 0 ; Reserved 11
|
||||
DCD 0 ; Reserved 12
|
||||
DCD 0 ; Reserved 13
|
||||
DCD 0 ; Reserved 14
|
||||
DCD 0 ; Reserved 15
|
||||
|
||||
END
|
||||
470
ports_module/cortex-m3/ac5/inc/tx_port.h
Normal file
470
ports_module/cortex-m3/ac5/inc/tx_port.h
Normal file
@@ -0,0 +1,470 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Port Specific */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* PORT SPECIFIC C INFORMATION RELEASE */
|
||||
/* */
|
||||
/* tx_port.h Cortex-M3/AC5 */
|
||||
/* 6.1 */
|
||||
/* */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* William E. Lamie, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This file contains data type definitions that make the ThreadX */
|
||||
/* real-time kernel function identically on a variety of different */
|
||||
/* processor architectures. For example, the size or number of bits */
|
||||
/* in an "int" data type vary between microprocessor architectures and */
|
||||
/* even C compilers for the same microprocessor. ThreadX does not */
|
||||
/* directly use native C data types. Instead, ThreadX creates its */
|
||||
/* own special types that can be mapped to actual data types by this */
|
||||
/* file to guarantee consistency in the interface and functionality. */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TX_PORT_H
|
||||
#define TX_PORT_H
|
||||
|
||||
|
||||
/* Determine if the optional ThreadX user define file should be used. */
|
||||
|
||||
#ifdef TX_INCLUDE_USER_DEFINE_FILE
|
||||
|
||||
/* Yes, include the user defines in tx_user.h. The defines in this file may
|
||||
alternately be defined on the command line. */
|
||||
|
||||
#include "tx_user.h"
|
||||
#endif
|
||||
|
||||
|
||||
/* Define compiler library include files. */
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
|
||||
/* Define ThreadX basic types for this port. */
|
||||
|
||||
#define VOID void
|
||||
typedef char CHAR;
|
||||
typedef unsigned char UCHAR;
|
||||
typedef int INT;
|
||||
typedef unsigned int UINT;
|
||||
typedef long LONG;
|
||||
typedef unsigned long ULONG;
|
||||
typedef short SHORT;
|
||||
typedef unsigned short USHORT;
|
||||
|
||||
|
||||
/* Define the priority levels for ThreadX. Legal values range
|
||||
from 32 to 1024 and MUST be evenly divisible by 32. */
|
||||
|
||||
#ifndef TX_MAX_PRIORITIES
|
||||
#define TX_MAX_PRIORITIES 32
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during
|
||||
thread creation is less than this value, the thread create call will return an error. */
|
||||
|
||||
#ifndef TX_MINIMUM_STACK
|
||||
#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the system timer thread's default stack size and priority. These are only applicable
|
||||
if TX_TIMER_PROCESS_IN_ISR is not defined. */
|
||||
|
||||
#ifndef TX_TIMER_THREAD_STACK_SIZE
|
||||
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
|
||||
#endif
|
||||
|
||||
#ifndef TX_TIMER_THREAD_PRIORITY
|
||||
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
|
||||
#endif
|
||||
|
||||
|
||||
/* Define various constants for the ThreadX Cortex-M3 port. */
|
||||
|
||||
#define TX_INT_DISABLE 1 /* Disable interrupts */
|
||||
#define TX_INT_ENABLE 0 /* Enable interrupts */
|
||||
|
||||
|
||||
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
|
||||
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
|
||||
source constants would be:
|
||||
|
||||
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
|
||||
#define TX_TRACE_TIME_MASK 0x0000FFFFUL
|
||||
|
||||
*/
|
||||
|
||||
#ifndef TX_TRACE_TIME_SOURCE
|
||||
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004)
|
||||
#endif
|
||||
#ifndef TX_TRACE_TIME_MASK
|
||||
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the port specific options for the _tx_build_options variable. This variable indicates
|
||||
how the ThreadX library was built. */
|
||||
|
||||
#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0
|
||||
|
||||
|
||||
/* Define the in-line initialization constant so that modules with in-line
|
||||
initialization capabilities can prevent their initialization from being
|
||||
a function call. */
|
||||
|
||||
#define TX_INLINE_INITIALIZATION
|
||||
|
||||
|
||||
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
|
||||
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
|
||||
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
|
||||
define is negated, thereby forcing the stack fill which is necessary for the stack checking
|
||||
logic. */
|
||||
|
||||
#ifdef TX_ENABLE_STACK_CHECKING
|
||||
#undef TX_DISABLE_STACK_FILLING
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the TX_THREAD control block extensions for this port. The main reason
|
||||
for the multiple macros is so that backward compatibility can be maintained with
|
||||
existing ThreadX kernel awareness modules. */
|
||||
|
||||
#define TX_THREAD_EXTENSION_0
|
||||
#define TX_THREAD_EXTENSION_1
|
||||
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
|
||||
VOID *tx_thread_module_entry_info_ptr; \
|
||||
ULONG tx_thread_module_current_user_mode; \
|
||||
ULONG tx_thread_module_user_mode; \
|
||||
ULONG tx_thread_module_saved_lr; \
|
||||
VOID *tx_thread_module_kernel_stack_start; \
|
||||
VOID *tx_thread_module_kernel_stack_end; \
|
||||
ULONG tx_thread_module_kernel_stack_size; \
|
||||
VOID *tx_thread_module_stack_ptr; \
|
||||
VOID *tx_thread_module_stack_start; \
|
||||
VOID *tx_thread_module_stack_end; \
|
||||
ULONG tx_thread_module_stack_size; \
|
||||
VOID *tx_thread_module_reserved;
|
||||
#define TX_THREAD_EXTENSION_3
|
||||
|
||||
|
||||
/* Define the port extensions of the remaining ThreadX objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_EXTENSION
|
||||
#define TX_BYTE_POOL_EXTENSION
|
||||
#define TX_MUTEX_EXTENSION
|
||||
#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \
|
||||
VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
|
||||
|
||||
#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \
|
||||
VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
|
||||
|
||||
#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \
|
||||
VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
|
||||
|
||||
#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \
|
||||
VOID (*tx_timer_module_expiration_function)(ULONG id);
|
||||
|
||||
|
||||
/* Define the user extension field of the thread control block. Nothing
|
||||
additional is needed for this port so it is defined as white space. */
|
||||
|
||||
#ifndef TX_THREAD_USER_EXTENSION
|
||||
#define TX_THREAD_USER_EXTENSION
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete,
|
||||
tx_thread_shell_entry, and tx_thread_terminate. */
|
||||
|
||||
|
||||
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
|
||||
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
register unsigned int _ipsr __asm("ipsr");
|
||||
#endif
|
||||
|
||||
#ifdef __TARGET_FPU_VFP
|
||||
|
||||
#ifdef TX_MISRA_ENABLE
|
||||
|
||||
ULONG _tx_misra_control_get(void);
|
||||
void _tx_misra_control_set(ULONG value);
|
||||
ULONG _tx_misra_fpccr_get(void);
|
||||
void _tx_misra_vfp_touch(void);
|
||||
|
||||
#else
|
||||
|
||||
#ifdef TX_SOURCE_CODE
|
||||
|
||||
register ULONG _control __asm("control");
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA
|
||||
in order to ensure no lazy stacking will occur. */
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
|
||||
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _control; \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_control = _tx_vfp_state; \
|
||||
}
|
||||
#else
|
||||
|
||||
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _tx_misra_control_get(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_tx_misra_control_set(_tx_vfp_state); \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR.
|
||||
If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating
|
||||
this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush
|
||||
the lazy FPU save, then restore the CONTROL.FPCA state. */
|
||||
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
|
||||
void _tx_vfp_access(void);
|
||||
|
||||
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \
|
||||
ULONG _tx_system_state; \
|
||||
_tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \
|
||||
if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \
|
||||
{ \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _control; \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_control = _tx_vfp_state; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
ULONG _tx_fpccr; \
|
||||
_tx_fpccr = *((ULONG *) 0xE000EF34); \
|
||||
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
|
||||
if (_tx_fpccr == ((ULONG) 0x01)) \
|
||||
{ \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _control; \
|
||||
_tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \
|
||||
_tx_vfp_access(); \
|
||||
if (_tx_vfp_state == ((ULONG) 0)) \
|
||||
{ \
|
||||
_tx_vfp_state = _control; \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_control = _tx_vfp_state; \
|
||||
} \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
#else
|
||||
|
||||
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \
|
||||
ULONG _tx_system_state; \
|
||||
_tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \
|
||||
if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \
|
||||
{ \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _tx_misra_control_get(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_tx_misra_control_set(_tx_vfp_state); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
ULONG _tx_fpccr; \
|
||||
_tx_fpccr = _tx_misra_fpccr_get(); \
|
||||
_tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \
|
||||
if (_tx_fpccr == ((ULONG) 0x01)) \
|
||||
{ \
|
||||
ULONG _tx_vfp_state; \
|
||||
_tx_vfp_state = _tx_misra_control_get(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \
|
||||
_tx_misra_vfp_touch(); \
|
||||
if (_tx_vfp_state == ((ULONG) 0)) \
|
||||
{ \
|
||||
_tx_vfp_state = _tx_misra_control_get(); \
|
||||
_tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \
|
||||
_tx_misra_control_set(_tx_vfp_state); \
|
||||
} \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
|
||||
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/* Define the ThreadX object creation extensions for the remaining objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr)
|
||||
#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr)
|
||||
#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr)
|
||||
#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr)
|
||||
#define TX_QUEUE_CREATE_EXTENSION(queue_ptr)
|
||||
#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr)
|
||||
#define TX_TIMER_CREATE_EXTENSION(timer_ptr)
|
||||
|
||||
|
||||
/* Define the ThreadX object deletion extensions for the remaining objects. */
|
||||
|
||||
#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr)
|
||||
#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr)
|
||||
#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr)
|
||||
#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr)
|
||||
#define TX_QUEUE_DELETE_EXTENSION(queue_ptr)
|
||||
#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr)
|
||||
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
|
||||
|
||||
|
||||
/* Define the get system state macro. */
|
||||
|
||||
#ifndef TX_THREAD_GET_SYSTEM_STATE
|
||||
#ifndef TX_MISRA_ENABLE
|
||||
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _ipsr)
|
||||
#else
|
||||
ULONG _tx_misra_ipsr_get(VOID);
|
||||
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get())
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value
|
||||
indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h
|
||||
for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always
|
||||
zero after initialization for Cortex-M ports. */
|
||||
|
||||
#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
|
||||
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to
|
||||
prevent early scheduling on Cortex-M parts. */
|
||||
|
||||
#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++;
|
||||
|
||||
|
||||
/* This ARM architecture has the CLZ instruction. This is available on
|
||||
architectures v5 and above. If available, redefine the macro for calculating the
|
||||
lowest bit set. */
|
||||
|
||||
#ifndef TX_DISABLE_INLINE
|
||||
|
||||
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m)));
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/* Define ThreadX interrupt lockout and restore macros for protection on
|
||||
access of critical kernel information. The restore interrupt macro must
|
||||
restore the interrupt posture of the running thread prior to the value
|
||||
present prior to the disable macro. In most cases, the save area macro
|
||||
is used to define a local function save area for the disable and restore
|
||||
macros. */
|
||||
|
||||
#ifdef TX_DISABLE_INLINE
|
||||
|
||||
UINT _tx_thread_interrupt_disable(VOID);
|
||||
VOID _tx_thread_interrupt_restore(UINT previous_posture);
|
||||
|
||||
#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save;
|
||||
|
||||
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable();
|
||||
|
||||
#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save);
|
||||
|
||||
#else
|
||||
|
||||
#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked;
|
||||
#define TX_DISABLE was_masked = __disable_irq();
|
||||
#define TX_RESTORE if (was_masked == 0) __enable_irq();
|
||||
|
||||
#define _tx_thread_system_return _tx_thread_system_return_inline
|
||||
|
||||
|
||||
static void _tx_thread_system_return_inline(void)
|
||||
{
|
||||
unsigned int was_masked;
|
||||
|
||||
|
||||
/* Set PendSV to invoke ThreadX scheduler. */
|
||||
*((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000);
|
||||
if (_ipsr == 0)
|
||||
{
|
||||
was_masked = __disable_irq();
|
||||
__enable_irq();
|
||||
if (was_masked != 0)
|
||||
__disable_irq();
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* Define the version ID of ThreadX. This may be utilized by the application. */
|
||||
|
||||
#ifdef TX_THREAD_INIT
|
||||
CHAR _tx_version_id[] =
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.1 *";
|
||||
#else
|
||||
#ifdef TX_MISRA_ENABLE
|
||||
extern CHAR _tx_version_id[100];
|
||||
#else
|
||||
extern CHAR _tx_version_id[];
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
338
ports_module/cortex-m3/ac5/inc/txm_module_port.h
Normal file
338
ports_module/cortex-m3/ac5/inc/txm_module_port.h
Normal file
@@ -0,0 +1,338 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* APPLICATION INTERFACE DEFINITION RELEASE */
|
||||
/* */
|
||||
/* txm_module_port.h Cortex-M3/MPU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This file defines the basic module constants, interface structures, */
|
||||
/* and function prototypes. */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TXM_MODULE_PORT_H
|
||||
#define TXM_MODULE_PORT_H
|
||||
|
||||
/* Determine if the optional Modules user define file should be used. */
|
||||
|
||||
#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE
|
||||
|
||||
|
||||
/* Yes, include the user defines in txm_module_user.h. The defines in this file may
|
||||
alternately be defined on the command line. */
|
||||
|
||||
#include "txm_module_user.h"
|
||||
#endif
|
||||
|
||||
/* It is assumed that the base ThreadX tx_port.h file has been modified to add the
|
||||
following extensions to the ThreadX thread control block (this code should replace
|
||||
the corresponding macro define in tx_port.h):
|
||||
|
||||
#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \
|
||||
VOID *tx_thread_module_entry_info_ptr; \
|
||||
ULONG tx_thread_module_current_user_mode; \
|
||||
ULONG tx_thread_module_user_mode; \
|
||||
ULONG tx_thread_module_saved_lr; \
|
||||
VOID *tx_thread_module_kernel_stack_start; \
|
||||
VOID *tx_thread_module_kernel_stack_end; \
|
||||
ULONG tx_thread_module_kernel_stack_size; \
|
||||
VOID *tx_thread_module_stack_ptr; \
|
||||
VOID *tx_thread_module_stack_start; \
|
||||
VOID *tx_thread_module_stack_end; \
|
||||
ULONG tx_thread_module_stack_size; \
|
||||
VOID *tx_thread_module_reserved;
|
||||
|
||||
The following extensions must also be defined in tx_port.h:
|
||||
|
||||
#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \
|
||||
VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr);
|
||||
|
||||
#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \
|
||||
VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr);
|
||||
|
||||
#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \
|
||||
VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr);
|
||||
|
||||
#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \
|
||||
VOID (*tx_timer_module_expiration_function)(ULONG id);
|
||||
*/
|
||||
|
||||
|
||||
/* Size of module heap. */
|
||||
#define TXM_MODULE_HEAP_SIZE 512
|
||||
|
||||
|
||||
/* Define the kernel stack size for a module thread. */
|
||||
#ifndef TXM_MODULE_KERNEL_STACK_SIZE
|
||||
#define TXM_MODULE_KERNEL_STACK_SIZE 768
|
||||
#endif
|
||||
|
||||
/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR)
|
||||
* to reflect your system memory attributes (cache, shareable, memory type). */
|
||||
/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */
|
||||
#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000
|
||||
/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */
|
||||
#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000
|
||||
/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */
|
||||
#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000
|
||||
|
||||
|
||||
/* Define constants specific to the tools the module can be built with for this particular modules port. */
|
||||
|
||||
#define TXM_MODULE_IAR_COMPILER 0x00000000
|
||||
#define TXM_MODULE_RVDS_COMPILER 0x01000000
|
||||
#define TXM_MODULE_GNU_COMPILER 0x02000000
|
||||
#define TXM_MODULE_COMPILER_MASK 0xFF000000
|
||||
#define TXM_MODULE_OPTIONS_MASK 0x000000FF
|
||||
|
||||
|
||||
/* Define the properties for this particular module port. */
|
||||
|
||||
#define TXM_MODULE_MEMORY_PROTECTION_ENABLED
|
||||
|
||||
#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED
|
||||
#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY
|
||||
#else
|
||||
#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY
|
||||
#endif
|
||||
|
||||
#define TXM_MODULE_USER_MODE 0x00000001
|
||||
#define TXM_MODULE_MEMORY_PROTECTION 0x00000002
|
||||
#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004
|
||||
|
||||
|
||||
/* Define the supported options for this module. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)
|
||||
#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0
|
||||
|
||||
|
||||
/* Define offset adjustments according to the compiler used to build the module. */
|
||||
|
||||
#define TXM_MODULE_IAR_SHELL_ADJUST 24
|
||||
#define TXM_MODULE_IAR_START_ADJUST 28
|
||||
#define TXM_MODULE_IAR_STOP_ADJUST 32
|
||||
#define TXM_MODULE_IAR_CALLBACK_ADJUST 44
|
||||
|
||||
#define TXM_MODULE_RVDS_SHELL_ADJUST 0
|
||||
#define TXM_MODULE_RVDS_START_ADJUST 0
|
||||
#define TXM_MODULE_RVDS_STOP_ADJUST 0
|
||||
#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0
|
||||
|
||||
#define TXM_MODULE_GNU_SHELL_ADJUST 24
|
||||
#define TXM_MODULE_GNU_START_ADJUST 28
|
||||
#define TXM_MODULE_GNU_STOP_ADJUST 32
|
||||
#define TXM_MODULE_GNU_CALLBACK_ADJUST 44
|
||||
|
||||
|
||||
/* Define other module port-specific constants. */
|
||||
|
||||
/* Define INLINE_DECLARE to inline for ARM compiler. */
|
||||
|
||||
#define INLINE_DECLARE inline
|
||||
|
||||
/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total
|
||||
entries, since ThreadX uses one for access to the kernel dispatch function. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4
|
||||
#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3
|
||||
#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8
|
||||
#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4
|
||||
|
||||
/* Shared memory region attributes. */
|
||||
#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1
|
||||
#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000
|
||||
|
||||
/* Define the port-extensions to the module manager instance structure. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_PORT_EXTENSION \
|
||||
ULONG txm_module_instance_mpu_registers[16]; \
|
||||
ULONG txm_module_instance_shared_memory_address; \
|
||||
ULONG txm_module_instance_shared_memory_length;
|
||||
|
||||
|
||||
/* Define the memory fault information structure that is populated when a memory fault occurs. */
|
||||
|
||||
|
||||
typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT
|
||||
{
|
||||
TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr;
|
||||
VOID *txm_module_manager_memory_fault_info_code_location;
|
||||
ULONG txm_module_manager_memory_fault_info_shcsr;
|
||||
ULONG txm_module_manager_memory_fault_info_cfsr;
|
||||
ULONG txm_module_manager_memory_fault_info_mmfar;
|
||||
ULONG txm_module_manager_memory_fault_info_bfar;
|
||||
ULONG txm_module_manager_memory_fault_info_control;
|
||||
ULONG txm_module_manager_memory_fault_info_sp;
|
||||
ULONG txm_module_manager_memory_fault_info_r0;
|
||||
ULONG txm_module_manager_memory_fault_info_r1;
|
||||
ULONG txm_module_manager_memory_fault_info_r2;
|
||||
ULONG txm_module_manager_memory_fault_info_r3;
|
||||
ULONG txm_module_manager_memory_fault_info_r4;
|
||||
ULONG txm_module_manager_memory_fault_info_r5;
|
||||
ULONG txm_module_manager_memory_fault_info_r6;
|
||||
ULONG txm_module_manager_memory_fault_info_r7;
|
||||
ULONG txm_module_manager_memory_fault_info_r8;
|
||||
ULONG txm_module_manager_memory_fault_info_r9;
|
||||
ULONG txm_module_manager_memory_fault_info_r10;
|
||||
ULONG txm_module_manager_memory_fault_info_r11;
|
||||
ULONG txm_module_manager_memory_fault_info_r12;
|
||||
ULONG txm_module_manager_memory_fault_info_lr;
|
||||
ULONG txm_module_manager_memory_fault_info_xpsr;
|
||||
} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO;
|
||||
|
||||
|
||||
#define TXM_MODULE_MANAGER_FAULT_INFO \
|
||||
TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info;
|
||||
|
||||
/* Define the macro to check the code alignment. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \
|
||||
{ \
|
||||
ULONG temp; \
|
||||
temp = (ULONG) module_location; \
|
||||
temp = temp & (code_alignment - 1); \
|
||||
if (temp) \
|
||||
{ \
|
||||
_tx_mutex_put(&_txm_module_manager_mutex); \
|
||||
return(TXM_MODULE_ALIGNMENT_ERROR); \
|
||||
} \
|
||||
}
|
||||
|
||||
|
||||
/* Define the macro to adjust the alignment and size for code/data areas. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment);
|
||||
|
||||
|
||||
/* Define the macro to adjust the symbols in the module preamble. */
|
||||
|
||||
#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \
|
||||
if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \
|
||||
{ \
|
||||
shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \
|
||||
start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \
|
||||
stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \
|
||||
callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \
|
||||
} \
|
||||
else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \
|
||||
{ \
|
||||
shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \
|
||||
start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \
|
||||
stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \
|
||||
callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \
|
||||
start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \
|
||||
stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \
|
||||
callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \
|
||||
}
|
||||
|
||||
|
||||
/* Define the macro to populate the thread control block with module port-specific information.
|
||||
Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly.
|
||||
*/
|
||||
|
||||
#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \
|
||||
thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \
|
||||
thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \
|
||||
if (thread_ptr -> tx_thread_module_user_mode) \
|
||||
{ \
|
||||
thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \
|
||||
}
|
||||
|
||||
|
||||
/* Define the macro to populate the module control block with module port-specific information.
|
||||
If memory protection is enabled, set up the MPU registers.
|
||||
*/
|
||||
#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \
|
||||
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \
|
||||
{ \
|
||||
if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \
|
||||
{ \
|
||||
_txm_module_manager_mm_register_setup(module_instance); \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
/* Do nothing. */ \
|
||||
}
|
||||
|
||||
/* Define the macro to perform port-specific functions when unloading the module. */
|
||||
/* Nothing needs to be done for this port. */
|
||||
#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance)
|
||||
|
||||
|
||||
/* Define the macros to perform port-specific checks when passing pointers to the kernel. */
|
||||
|
||||
/* Define macro to make sure object is inside the module's data. */
|
||||
#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \
|
||||
/* Check if it's inside module data. */ \
|
||||
((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \
|
||||
(((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \
|
||||
/* Check if it's inside shared memory. */ \
|
||||
(((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \
|
||||
(((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))
|
||||
|
||||
|
||||
/* Define some internal prototypes to this module port. */
|
||||
|
||||
#ifndef TX_SOURCE_CODE
|
||||
#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify
|
||||
#endif
|
||||
|
||||
|
||||
#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \
|
||||
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \
|
||||
VOID _txm_module_manager_memory_fault_handler(VOID); \
|
||||
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \
|
||||
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \
|
||||
ULONG _txm_power_of_two_block_size(ULONG size); \
|
||||
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \
|
||||
ULONG _txm_module_manager_region_size_get(ULONG block_size);
|
||||
|
||||
#define TXM_MODULE_MANAGER_VERSION_ID \
|
||||
CHAR _txm_module_manager_version_id[] = \
|
||||
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/AC5 Version 6.1 *";
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,112 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Module */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
IMPORT __use_two_region_memory
|
||||
IMPORT __scatterload
|
||||
IMPORT txm_heap
|
||||
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _txm_module_initialize Cortex-M3/MPU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function initializes the module c runtime. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* __scatterload Initialize C runtime */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _txm_module_thread_shell_entry Start module thread */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _txm_module_initialize(VOID)
|
||||
|
||||
EXPORT _txm_module_initialize
|
||||
_txm_module_initialize
|
||||
PUSH {r4-r12,lr} ; Save dregs and LR
|
||||
|
||||
B __scatterload ; Call ARM func to initialize variables
|
||||
|
||||
;
|
||||
;/* Override __rt_exit function. */
|
||||
;
|
||||
EXPORT __rt_exit
|
||||
__rt_exit
|
||||
|
||||
POP {r4-r12,lr} ; Restore dregs and LR
|
||||
BX lr ; Return to caller
|
||||
;
|
||||
;
|
||||
;
|
||||
EXPORT __user_setup_stackheap
|
||||
; returns heap start address in R0
|
||||
; returns heap end address in R2
|
||||
; does not touch SP, it is already set up before the module runs
|
||||
|
||||
__user_setup_stackheap
|
||||
LDR r1, _tx_heap_offset ; load heap offset
|
||||
ADD r0, r9, r1 ; calculate heap base address
|
||||
MOV r2, #TXM_MODULE_HEAP_SIZE ; load heap size
|
||||
ADD r2, r2, r0 ; calculate heap end address
|
||||
BX lr
|
||||
|
||||
ALIGN 4
|
||||
_tx_heap_offset
|
||||
DCDO txm_heap
|
||||
AREA ||.arm_vfe_header||, DATA, READONLY, NOALLOC, ALIGN=2
|
||||
|
||||
IMPORT txm_heap [DATA]
|
||||
|
||||
;
|
||||
; Dummy main function
|
||||
;
|
||||
AREA section_main, CODE, READONLY, ALIGN=2
|
||||
EXPORT main
|
||||
main
|
||||
BX lr
|
||||
|
||||
END
|
||||
@@ -0,0 +1,173 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#ifndef TXM_MODULE
|
||||
#define TXM_MODULE
|
||||
#endif
|
||||
|
||||
#ifndef TX_SOURCE_CODE
|
||||
#define TX_SOURCE_CODE
|
||||
#endif
|
||||
|
||||
|
||||
/* Include necessary system files. */
|
||||
|
||||
#include "txm_module.h"
|
||||
#include "tx_thread.h"
|
||||
|
||||
/* Define the global module entry pointer from the start thread of the module. */
|
||||
|
||||
TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info;
|
||||
|
||||
|
||||
/* Define the dispatch function pointer used in the module implementation. */
|
||||
|
||||
ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3);
|
||||
|
||||
|
||||
/* Define the ARM cstartup code. */
|
||||
extern VOID _txm_module_initialize(VOID);
|
||||
|
||||
__align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE];
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_thread_shell_entry Cortex-M3/MPU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function calls the specified entry function of the thread. It */
|
||||
/* also provides a place for the thread's entry function to return. */
|
||||
/* If the thread returns, this function places the thread in a */
|
||||
/* "COMPLETED" state. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* thread_ptr Pointer to current thread */
|
||||
/* thread_info Pointer to thread entry info */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _txm_module_initialize cstartup initialization */
|
||||
/* thread_entry Thread's entry function */
|
||||
/* tx_thread_resume Resume the module callback thread */
|
||||
/* _txm_module_thread_system_suspend Module thread suspension routine */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Initial thread stack frame */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info)
|
||||
{
|
||||
|
||||
#ifndef TX_DISABLE_NOTIFY_CALLBACKS
|
||||
VOID (*entry_exit_notify)(TX_THREAD *, UINT);
|
||||
#endif
|
||||
|
||||
|
||||
/* Determine if this is the start thread. If so, we must prepare the module for
|
||||
execution. If not, simply skip the C startup code. */
|
||||
if (thread_info -> txm_module_thread_entry_info_start_thread)
|
||||
{
|
||||
/* Initialize the ARM C environment. */
|
||||
_txm_module_initialize();
|
||||
|
||||
/* Save the entry info pointer, for later use. */
|
||||
_txm_module_entry_info = thread_info;
|
||||
|
||||
/* Save the kernel function dispatch address. This is used to make all resident calls from
|
||||
the module. */
|
||||
_txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher;
|
||||
|
||||
/* Ensure that we have a valid pointer. */
|
||||
while (!_txm_module_kernel_call_dispatcher)
|
||||
{
|
||||
/* Loop here, if an error is present getting the dispatch function pointer!
|
||||
An error here typically indicates the resident portion of _tx_thread_schedule
|
||||
is not supporting the trap to obtain the function pointer. */
|
||||
}
|
||||
|
||||
/* Resume the module's callback thread, already created in the manager. */
|
||||
_txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread);
|
||||
}
|
||||
|
||||
#ifndef TX_DISABLE_NOTIFY_CALLBACKS
|
||||
|
||||
/* Pickup the entry/exit application callback routine. */
|
||||
entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify;
|
||||
|
||||
/* Determine if an application callback routine is specified. */
|
||||
if (entry_exit_notify != TX_NULL)
|
||||
{
|
||||
|
||||
/* Yes, notify application that this thread has been entered! */
|
||||
(entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Call current thread's entry function. */
|
||||
(thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter);
|
||||
|
||||
/* Suspend thread with a "completed" state. */
|
||||
|
||||
|
||||
#ifndef TX_DISABLE_NOTIFY_CALLBACKS
|
||||
|
||||
/* Pickup the entry/exit application callback routine again. */
|
||||
entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify;
|
||||
|
||||
/* Determine if an application callback routine is specified. */
|
||||
if (entry_exit_notify != TX_NULL)
|
||||
{
|
||||
|
||||
/* Yes, notify application that this thread has exited! */
|
||||
(entry_exit_notify)(thread_ptr, TX_THREAD_EXIT);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Call actual thread suspension routine. */
|
||||
_txm_module_thread_system_suspend(thread_ptr);
|
||||
|
||||
#ifdef TX_SAFETY_CRITICAL
|
||||
|
||||
/* If we ever get here, raise safety critical exception. */
|
||||
TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -0,0 +1,91 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_isr_exit
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_context_restore Cortex-M3/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is only needed for legacy applications and it should */
|
||||
;/* not be called in any new development on a Cortex-M. */
|
||||
;/* This function restores the interrupt context if it is processing a */
|
||||
;/* nested interrupt. If not, it returns to the interrupt thread if no */
|
||||
;/* preemption is necessary. Otherwise, if preemption is necessary or */
|
||||
;/* if no thread was running, the function returns to the scheduler. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Thread scheduling routine */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs Interrupt Service Routines */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_context_restore(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_context_restore
|
||||
_tx_thread_context_restore
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR exit function to indicate an ISR is complete. */
|
||||
;
|
||||
PUSH {r0,lr} ; Save ISR lr
|
||||
BL _tx_execution_isr_exit ; Call the ISR exit function
|
||||
POP {r0,lr} ; Restore ISR lr
|
||||
ENDIF
|
||||
;
|
||||
POP {lr}
|
||||
BX lr
|
||||
;}
|
||||
ALIGN
|
||||
LTORG
|
||||
END
|
||||
@@ -0,0 +1,91 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_isr_enter
|
||||
ENDIF
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_context_save Cortex-M3/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is only needed for legacy applications and it should */
|
||||
;/* not be called in any new development on a Cortex-M. */
|
||||
;/* This function saves the context of an executing thread in the */
|
||||
;/* beginning of interrupt processing. The function also ensures that */
|
||||
;/* the system stack is used upon return to the calling ISR. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ISRs */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_context_save(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_context_save
|
||||
_tx_thread_context_save
|
||||
IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the ISR enter function to indicate an ISR is executing. */
|
||||
;
|
||||
PUSH {r0, lr} ; Save ISR lr
|
||||
BL _tx_execution_isr_enter ; Call the ISR enter function
|
||||
POP {r0, lr} ; Recover ISR lr
|
||||
ENDIF
|
||||
;
|
||||
; /* Return to interrupt processing. */
|
||||
;
|
||||
BX lr ; Return to interrupt processing caller
|
||||
;}
|
||||
ALIGN
|
||||
LTORG
|
||||
END
|
||||
@@ -0,0 +1,76 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_interrupt_control Cortex-M3/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for changing the interrupt lockout */
|
||||
;/* posture of the system. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* new_posture New interrupt lockout posture */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* old_posture Old interrupt lockout posture */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;UINT _tx_thread_interrupt_control(UINT new_posture)
|
||||
;{
|
||||
EXPORT _tx_thread_interrupt_control
|
||||
_tx_thread_interrupt_control
|
||||
;
|
||||
; /* Pickup current interrupt lockout posture. */
|
||||
;
|
||||
MRS r1, PRIMASK
|
||||
MSR PRIMASK, r0
|
||||
MOV r0, r1
|
||||
BX lr
|
||||
;
|
||||
;}
|
||||
END
|
||||
@@ -0,0 +1,75 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_interrupt_disable Cortex-M3/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for disabling interrupts and returning */
|
||||
;/* the previous interrupt lockout posture. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* old_posture Old interrupt lockout posture */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;UINT _tx_thread_interrupt_disable(UINT new_posture)
|
||||
;{
|
||||
EXPORT _tx_thread_interrupt_disable
|
||||
_tx_thread_interrupt_disable
|
||||
;
|
||||
; /* Return current interrupt lockout posture. */
|
||||
;
|
||||
MRS r0, PRIMASK
|
||||
CPSID i
|
||||
BX lr
|
||||
;
|
||||
;}
|
||||
END
|
||||
@@ -0,0 +1,74 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_interrupt_restore Cortex-M3/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for restoring the previous */
|
||||
;/* interrupt lockout posture. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* previous_posture Previous interrupt posture */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Application Code */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_interrupt_restore(UINT new_posture)
|
||||
;{
|
||||
EXPORT _tx_thread_interrupt_restore
|
||||
_tx_thread_interrupt_restore
|
||||
;
|
||||
; /* Restore previous interrupt lockout posture. */
|
||||
;
|
||||
MSR PRIMASK, r0
|
||||
BX lr
|
||||
;
|
||||
;}
|
||||
END
|
||||
@@ -0,0 +1,519 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IMPORT _tx_thread_execute_ptr
|
||||
IMPORT _tx_timer_time_slice
|
||||
IMPORT _tx_thread_system_stack_ptr
|
||||
IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
IMPORT _tx_execution_thread_enter
|
||||
IMPORT _tx_execution_thread_exit
|
||||
ENDIF
|
||||
IMPORT _tx_thread_preempt_disable
|
||||
IMPORT _txm_module_manager_memory_fault_handler
|
||||
IMPORT _txm_module_manager_memory_fault_info
|
||||
IMPORT _txm_module_priv
|
||||
IMPORT _txm_module_user_mode_exit
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
THUMB
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Cortex-M3/MPU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function waits for a thread control block pointer to appear in */
|
||||
;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
|
||||
;/* in the variable, the corresponding thread is resumed. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
;/* _tx_thread_system_return Return to system from thread */
|
||||
;/* _tx_thread_context_restore Restore thread's context */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_schedule(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_schedule
|
||||
_tx_thread_schedule
|
||||
;
|
||||
; /* This function should only ever be called on Cortex-M
|
||||
; from the first schedule request. Subsequent scheduling occurs
|
||||
; from the PendSV handling routines below. */
|
||||
;
|
||||
; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */
|
||||
;
|
||||
MOV r0, #0 ; Build value for TX_FALSE
|
||||
LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag
|
||||
STR r0, [r2, #0] ; Clear preempt disable flag
|
||||
;
|
||||
; /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */
|
||||
;
|
||||
IF :DEF: __ARMVFP__
|
||||
MRS r0, CONTROL ; Pickup current CONTROL register
|
||||
BIC r0, r0, #4 ; Clear the FPCA bit
|
||||
MSR CONTROL, r0 ; Setup new CONTROL register
|
||||
ENDIF
|
||||
;
|
||||
; /* Enable memory fault registers. */
|
||||
;
|
||||
LDR r0, =0xE000ED24 ; Build SHCSR address
|
||||
LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults
|
||||
STR r1, [r0] ;
|
||||
;
|
||||
; /* Enable interrupts */
|
||||
;
|
||||
CPSIE i
|
||||
;
|
||||
; /* Enter the scheduler for the first time. */
|
||||
;
|
||||
MOV r0, #0x10000000 ; Load PENDSVSET bit
|
||||
MOV r1, #0xE000E000 ; Load NVIC base
|
||||
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
|
||||
DSB ; Complete all memory accesses
|
||||
ISB ; Flush pipeline
|
||||
|
||||
; /* Wait here for the PendSV to take place. */
|
||||
|
||||
__tx_wait_here
|
||||
B __tx_wait_here ; Wait for the PendSV to happen
|
||||
;}
|
||||
;
|
||||
|
||||
;
|
||||
; /* Memory Exception Handler. */
|
||||
;
|
||||
EXPORT MemManage_Handler
|
||||
MemManage_Handler
|
||||
;{
|
||||
CPSID i ; Disable interrupts
|
||||
;
|
||||
; /* Now pickup and store all the fault related information. */
|
||||
;
|
||||
LDR r12,=_txm_module_manager_memory_fault_info ; Pickup fault info struct
|
||||
LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r1, [r0] ; Pickup the current thread pointer
|
||||
STR r1, [r12, #0] ; Save current thread pointer in fault info structure
|
||||
LDR r0, =0xE000ED24 ; Build SHCSR address
|
||||
LDR r1, [r0] ; Pickup SHCSR
|
||||
STR r1, [r12, #8] ; Save SHCSR
|
||||
LDR r0, =0xE000ED28 ; Build CFSR address
|
||||
LDR r1, [r0] ; Pickup CFSR
|
||||
STR r1, [r12, #12] ; Save CFSR
|
||||
LDR r0, =0xE000ED34 ; Build MMFAR address
|
||||
LDR r1, [r0] ; Pickup MMFAR
|
||||
STR r1, [r12, #16] ; Save MMFAR
|
||||
LDR r0, =0xE000ED38 ; Build BFAR address
|
||||
LDR r1, [r0] ; Pickup BFAR
|
||||
STR r1, [r12, #20] ; Save BFAR
|
||||
MRS r0, CONTROL ; Pickup current CONTROL register
|
||||
STR r0, [r12, #24] ; Save CONTROL
|
||||
MRS r1, PSP ; Pickup thread stack pointer
|
||||
STR r1, [r12, #28] ; Save thread stack pointer
|
||||
LDR r0, [r1] ; Pickup saved r0
|
||||
STR r0, [r12, #32] ; Save r0
|
||||
LDR r0, [r1, #4] ; Pickup saved r1
|
||||
STR r0, [r12, #36] ; Save r1
|
||||
STR r2, [r12, #40] ; Save r2
|
||||
STR r3, [r12, #44] ; Save r3
|
||||
STR r4, [r12, #48] ; Save r4
|
||||
STR r5, [r12, #52] ; Save r5
|
||||
STR r6, [r12, #56] ; Save r6
|
||||
STR r7, [r12, #60] ; Save r7
|
||||
STR r8, [r12, #64] ; Save r8
|
||||
STR r9, [r12, #68] ; Save r9
|
||||
STR r10,[r12, #72] ; Save r10
|
||||
STR r11,[r12, #76] ; Save r11
|
||||
LDR r0, [r1, #16] ; Pickup saved r12
|
||||
STR r0, [r12, #80] ; Save r12
|
||||
LDR r0, [r1, #20] ; Pickup saved lr
|
||||
STR r0, [r12, #84] ; Save lr
|
||||
LDR r0, [r1, #24] ; Pickup instruction address at point of fault
|
||||
STR r0, [r12, #4] ; Save point of fault
|
||||
LDR r0, [r1, #28] ; Pickup xPSR
|
||||
STR r0, [r12, #88] ; Save xPSR
|
||||
|
||||
MRS r0, CONTROL ; Pickup current CONTROL register
|
||||
BIC r0, r0, #1 ; Clear the UNPRIV bit
|
||||
MSR CONTROL, r0 ; Setup new CONTROL register
|
||||
|
||||
LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR)
|
||||
LDRB r1, [r0] ; Pickup the MMFSR, with the following bit definitions:
|
||||
; Bit 0 = 1 -> Instruction address violation
|
||||
; Bit 1 = 1 -> Load/store address violation
|
||||
; Bit 7 = 1 -> MMFAR is valid
|
||||
STRB r1, [r0] ; Clear the MMFSR
|
||||
|
||||
IF :DEF: __ARMVFP__
|
||||
LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address
|
||||
LDR r1, [r0] ; Load FPCCR
|
||||
BIC r1, r1, #1 ; Clear the lazy preservation active bit
|
||||
STR r1, [r0] ; Store the value
|
||||
ENDIF
|
||||
|
||||
BL _txm_module_manager_memory_fault_handler ; Call memory manager fault handler
|
||||
|
||||
IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
;
|
||||
CPSID i ; Disable interrupts
|
||||
BL _tx_execution_thread_exit ; Call the thread exit function
|
||||
CPSIE i ; Enable interrupts
|
||||
ENDIF
|
||||
|
||||
MOV r1, #0 ; Build NULL value
|
||||
LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer
|
||||
STR r1, [r0] ; Clear current thread pointer
|
||||
|
||||
; Return from MemManage_Handler exception
|
||||
LDR r0, =0xE000ED04 ; Load ICSR
|
||||
LDR r1, =0x10000000 ; Set PENDSVSET bit
|
||||
STR r1, [r0] ; Store ICSR
|
||||
DSB ; Wait for memory access to complete
|
||||
CPSIE i ; Enable interrupts
|
||||
MOV lr, #0xFFFFFFFD ; Load exception return code
|
||||
BX lr ; Return from exception
|
||||
;}
|
||||
|
||||
;
|
||||
; /* Generic context PendSV handler. */
|
||||
;
|
||||
EXPORT PendSV_Handler
|
||||
EXPORT __tx_PendSVHandler
|
||||
PendSV_Handler
|
||||
__tx_PendSVHandler
|
||||
;
|
||||
; /* Get current thread value and new thread pointer. */
|
||||
;
|
||||
__tx_ts_handler
|
||||
|
||||
IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread exit function to indicate the thread is no longer executing. */
|
||||
;
|
||||
CPSID i ; Disable interrupts
|
||||
PUSH {r0, lr} ; Save LR (and r0 just for alignment)
|
||||
BL _tx_execution_thread_exit ; Call the thread exit function
|
||||
POP {r0, lr} ; Recover LR
|
||||
CPSIE i ; Enable interrupts
|
||||
ENDIF
|
||||
MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address
|
||||
MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address
|
||||
MOV r3, #0 ; Build NULL value
|
||||
LDR r1, [r0] ; Pickup current thread pointer
|
||||
;
|
||||
; /* Determine if there is a current thread to finish preserving. */
|
||||
;
|
||||
CBZ r1, __tx_ts_new ; If NULL, skip preservation
|
||||
;
|
||||
; /* Recover PSP and preserve current thread context. */
|
||||
;
|
||||
STR r3, [r0] ; Set _tx_thread_current_ptr to NULL
|
||||
MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer)
|
||||
STMDB r12!, {r4-r11} ; Save its remaining registers
|
||||
IF :DEF: __ARMVFP__
|
||||
TST LR, #0x10 ; Determine if the VFP extended frame is present
|
||||
BNE _skip_vfp_save
|
||||
VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers
|
||||
_skip_vfp_save
|
||||
ENDIF
|
||||
MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable
|
||||
STMDB r12!, {LR} ; Save LR on the stack
|
||||
;
|
||||
; /* Determine if time-slice is active. If it isn't, skip time handling processing. */
|
||||
;
|
||||
LDR r5, [r4] ; Pickup current time-slice
|
||||
STR r12, [r1, #8] ; Save the thread stack pointer
|
||||
CBZ r5, __tx_ts_new ; If not active, skip processing
|
||||
;
|
||||
; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */
|
||||
;
|
||||
STR r5, [r1, #24] ; Save current time-slice
|
||||
;
|
||||
; /* Clear the global time-slice. */
|
||||
;
|
||||
STR r3, [r4] ; Clear time-slice
|
||||
;
|
||||
; /* Executing thread is now completely preserved!!! */
|
||||
;
|
||||
__tx_ts_new
|
||||
;
|
||||
; /* Now we are looking for a new thread to execute! */
|
||||
;
|
||||
CPSID i ; Disable interrupts
|
||||
LDR r1, [r2] ; Is there another thread ready to execute?
|
||||
CBZ r1, __tx_ts_wait ; No, skip to the wait processing
|
||||
;
|
||||
; /* Yes, another thread is ready for else, make the current thread the new thread. */
|
||||
;
|
||||
STR r1, [r0] ; Setup the current thread pointer to the new thread
|
||||
CPSIE i ; Enable interrupts
|
||||
;
|
||||
; /* Increment the thread run count. */
|
||||
;
|
||||
__tx_ts_restore
|
||||
LDR r7, [r1, #4] ; Pickup the current thread run count
|
||||
MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable
|
||||
LDR r5, [r1, #24] ; Pickup thread's current time-slice
|
||||
ADD r7, r7, #1 ; Increment the thread run count
|
||||
STR r7, [r1, #4] ; Store the new run count
|
||||
;
|
||||
; /* Setup global time-slice with thread's current time-slice. */
|
||||
;
|
||||
STR r5, [r4] ; Setup global time-slice
|
||||
|
||||
IF :DEF: TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
;
|
||||
; /* Call the thread entry function to indicate the thread is executing. */
|
||||
;
|
||||
PUSH {r0, r1} ; Save r0 and r1
|
||||
BL _tx_execution_thread_enter ; Call the thread execution enter function
|
||||
POP {r0, r1} ; Recover r0 and r1
|
||||
ENDIF
|
||||
;
|
||||
; /* Restore the thread context and PSP. */
|
||||
;
|
||||
LDR r12, [r1, #8] ; Pickup thread's stack pointer
|
||||
|
||||
MRS r5, CONTROL ; Pickup current CONTROL register
|
||||
LDR r4, [r1, #0x98] ; Pickup current user mode flag
|
||||
BIC r5, r5, #1 ; Clear the UNPRIV bit
|
||||
ORR r4, r4, r5 ; Build new CONTROL register
|
||||
MSR CONTROL, r4 ; Setup new CONTROL register
|
||||
|
||||
LDR r0, =0xE000ED94 ; Build MPU control reg address
|
||||
MOV r3, #0 ; Build disable value
|
||||
STR r3, [r0] ; Disable MPU
|
||||
LDR r0, [r1, #0x90] ; Pickup the module instance pointer
|
||||
CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup
|
||||
LDR r1, [r0, #0x64] ; Pickup MPU register[0]
|
||||
CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup
|
||||
LDR r1, =0xE000ED9C ; Build address of MPU base register
|
||||
|
||||
; Use alias registers to quickly load MPU
|
||||
ADD r0, r0, #100 ; Build address of MPU register start in thread control block
|
||||
LDM r0!,{r2-r9} ; Load MPU regions 0-3
|
||||
STM r1,{r2-r9} ; Store MPU regions 0-3
|
||||
LDM r0!,{r2-r9} ; Load MPU regions 4-7
|
||||
STM r1,{r2-r9} ; Store MPU regions 4-7
|
||||
LDR r0, =0xE000ED94 ; Build MPU control reg address
|
||||
MOV r1, #5 ; Build enable value with background region enabled
|
||||
STR r1, [r0] ; Enable MPU
|
||||
skip_mpu_setup
|
||||
LDMIA r12!, {LR} ; Pickup LR
|
||||
IF :DEF: __ARMVFP__
|
||||
TST LR, #0x10 ; Determine if the VFP extended frame is present
|
||||
BNE _skip_vfp_restore ; If not, skip VFP restore
|
||||
VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers
|
||||
_skip_vfp_restore
|
||||
ENDIF
|
||||
LDMIA r12!, {r4-r11} ; Recover thread's registers
|
||||
MSR PSP, r12 ; Setup the thread's stack pointer
|
||||
;
|
||||
; /* Return to thread. */
|
||||
;
|
||||
BX lr ; Return to thread!
|
||||
;
|
||||
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
|
||||
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
|
||||
; are disabled to allow use of WFI for waiting for a thread to arrive. */
|
||||
;
|
||||
__tx_ts_wait
|
||||
CPSID i ; Disable interrupts
|
||||
LDR r1, [r2] ; Pickup the next thread to execute pointer
|
||||
STR r1, [r0] ; Store it in the current pointer
|
||||
CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready!
|
||||
IF :DEF:TX_ENABLE_WFI
|
||||
DSB ; Ensure no outstanding memory transactions
|
||||
WFI ; Wait for interrupt
|
||||
ISB ; Ensure pipeline is flushed
|
||||
ENDIF
|
||||
CPSIE i ; Enable interrupts
|
||||
B __tx_ts_wait ; Loop to continue waiting
|
||||
;
|
||||
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
|
||||
; already in the handler! */
|
||||
;
|
||||
__tx_ts_ready
|
||||
MOV r7, #0x08000000 ; Build clear PendSV value
|
||||
MOV r8, #0xE000E000 ; Build base NVIC address
|
||||
STR r7, [r8, #0xD04] ; Clear any PendSV
|
||||
;
|
||||
; /* Re-enable interrupts and restore new thread. */
|
||||
;
|
||||
CPSIE i ; Enable interrupts
|
||||
B __tx_ts_restore ; Restore the thread
|
||||
;}
|
||||
|
||||
;
|
||||
; /* SVC Handler. */
|
||||
;
|
||||
EXPORT SVC_Handler
|
||||
EXPORT __tx_SVCallHandler
|
||||
SVC_Handler
|
||||
__tx_SVCallHandler
|
||||
;{
|
||||
MRS r0, PSP ; Pickup the PSP stack
|
||||
LDR r1, [r0, #24] ; Pickup the point of interrupt
|
||||
LDRB r2, [r1, #-2] ; Pickup the SVC parameter
|
||||
;
|
||||
; Determine which SVC trap we are processing
|
||||
;
|
||||
CMP r2, #1 ; Is it the entry into ThreadX?
|
||||
BNE _tx_thread_user_return ; No, return to user mode
|
||||
;
|
||||
; At this point we have an SVC 1, which means we are entering the kernel from a module thread with user mode selected
|
||||
;
|
||||
LDR r2, =_txm_module_priv ; Subtract 1 because of THUMB mode.
|
||||
SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly.
|
||||
CMP r1, r2 ; Did we come from user_mode_entry?
|
||||
IT NE ; If no (not equal), then...
|
||||
BXNE lr ; return from where we came.
|
||||
|
||||
LDR r3, [r0, #20] ; This is the saved LR
|
||||
LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r2, [r1] ; Pickup current thread pointer
|
||||
MOV r1, #0 ; Build clear value
|
||||
STR r1, [r2, #0x98] ; Clear the current user mode selection for thread
|
||||
STR r3, [r2, #0xA0] ; Save the original LR in thread control block
|
||||
|
||||
; If there is memory protection, use kernel stack
|
||||
LDR r0, [r2, #0x90] ; Load the module instance ptr
|
||||
LDR r0, [r0, #0x0C] ; Load the module property flags
|
||||
TST r0, #2 ; Check if memory protected
|
||||
BEQ _tx_skip_kernel_stack_enter
|
||||
|
||||
; Switch to the module thread's kernel stack
|
||||
LDR r0, [r2, #0xA8] ; Load the module kernel stack end
|
||||
IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
|
||||
LDR r1, [r2, #0xA4] ; Load the module kernel stack start
|
||||
LDR r3, [r2, #0xAC] ; Load the module kernel stack size
|
||||
STR r1, [r2, #12] ; Set stack start
|
||||
STR r0, [r2, #16] ; Set stack end
|
||||
STR r3, [r2, #20] ; Set stack size
|
||||
ENDIF
|
||||
|
||||
MRS r3, PSP ; Pickup thread stack pointer
|
||||
STR r3, [r2, #0xB0] ; Save thread stack pointer
|
||||
|
||||
; Build kernel stack by copying thread stack two registers at a time
|
||||
ADD r3, r3, #32 ; start at bottom of hardware stack
|
||||
LDMDB r3!,{r1-r2}
|
||||
STMDB r0!,{r1-r2}
|
||||
LDMDB r3!,{r1-r2}
|
||||
STMDB r0!,{r1-r2}
|
||||
LDMDB r3!,{r1-r2}
|
||||
STMDB r0!,{r1-r2}
|
||||
LDMDB r3!,{r1-r2}
|
||||
STMDB r0!,{r1-r2}
|
||||
|
||||
MSR PSP, r0 ; Set kernel stack pointer
|
||||
|
||||
_tx_skip_kernel_stack_enter
|
||||
MRS r0, CONTROL ; Pickup current CONTROL register
|
||||
BIC r0, r0, #1 ; Clear the UNPRIV bit
|
||||
MSR CONTROL, r0 ; Setup new CONTROL register
|
||||
BX lr ; Return to thread
|
||||
|
||||
_tx_thread_user_return
|
||||
LDR r2, =_txm_module_user_mode_exit ; Subtract 1 because of THUMB mode.
|
||||
SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly.
|
||||
CMP r1, r2 ; Did we come from user_mode_exit?
|
||||
IT NE ; If no (not equal), then...
|
||||
BXNE lr ; return from where we came
|
||||
|
||||
LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r2, [r1] ; Pickup current thread pointer
|
||||
LDR r1, [r2, #0x9C] ; Pick up user mode
|
||||
STR r1, [r2, #0x98] ; Set the current user mode selection for thread
|
||||
|
||||
; If there is memory protection, use kernel stack
|
||||
LDR r0, [r2, #0x90] ; Load the module instance ptr
|
||||
LDR r0, [r0, #0x0C] ; Load the module property flags
|
||||
TST r0, #2 ; Check if memory protected
|
||||
BEQ _tx_skip_kernel_stack_exit
|
||||
|
||||
IF :LNOT: :DEF: TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE
|
||||
LDR r0, [r2, #0xB4] ; Load the module thread stack start
|
||||
LDR r1, [r2, #0xB8] ; Load the module thread stack end
|
||||
LDR r3, [r2, #0xBC] ; Load the module thread stack size
|
||||
STR r0, [r2, #12] ; Set stack start
|
||||
STR r1, [r2, #16] ; Set stack end
|
||||
STR r3, [r2, #20] ; Set stack size
|
||||
ENDIF
|
||||
LDR r0, [r2, #0xB0] ; Load the module thread stack pointer
|
||||
MRS r3, PSP ; Pickup kernel stack pointer
|
||||
|
||||
; Copy kernel hardware stack to module thread stack.
|
||||
LDM r3!,{r1-r2}
|
||||
STM r0!,{r1-r2}
|
||||
LDM r3!,{r1-r2}
|
||||
STM r0!,{r1-r2}
|
||||
LDM r3!,{r1-r2}
|
||||
STM r0!,{r1-r2}
|
||||
LDM r3!,{r1-r2}
|
||||
STM r0!,{r1-r2}
|
||||
SUB r0, r0, #32 ; Subtract 32 to get back to top of stack
|
||||
MSR PSP, r0 ; Set thread stack pointer
|
||||
|
||||
LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r2, [r1] ; Pickup current thread pointer
|
||||
LDR r1, [r2, #0x9C] ; Pick up user mode
|
||||
|
||||
_tx_skip_kernel_stack_exit
|
||||
MRS r0, CONTROL ; Pickup current CONTROL register
|
||||
ORR r0, r0, r1 ; OR in the user mode bit
|
||||
MSR CONTROL, r0 ; Setup new CONTROL register
|
||||
BX lr ; Return to thread
|
||||
;}
|
||||
|
||||
ALIGN 4
|
||||
END
|
||||
@@ -0,0 +1,133 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_stack_build Cortex-M3/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function builds a stack frame on the supplied thread's stack. */
|
||||
;/* The stack frame results in a fake interrupt return to the supplied */
|
||||
;/* function pointer. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* thread_ptr Pointer to thread control blk */
|
||||
;/* function_ptr Pointer to return function */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_thread_create Create thread service */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
|
||||
;{
|
||||
EXPORT _tx_thread_stack_build
|
||||
_tx_thread_stack_build
|
||||
;
|
||||
;
|
||||
; /* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
; on the Cortex-M3 should look like the following after it is built:
|
||||
;
|
||||
; Stack Top:
|
||||
; LR Interrupted LR (LR at time of PENDSV)
|
||||
; r4 Initial value for r4
|
||||
; r5 Initial value for r5
|
||||
; r6 Initial value for r6
|
||||
; r7 Initial value for r7
|
||||
; r8 Initial value for r8
|
||||
; r9 Initial value for r9
|
||||
; r10 Initial value for r10
|
||||
; r11 Initial value for r11
|
||||
; r0 Initial value for r0 (Hardware stack starts here!!)
|
||||
; r1 Initial value for r1
|
||||
; r2 Initial value for r2
|
||||
; r3 Initial value for r3
|
||||
; r12 Initial value for r12
|
||||
; lr Initial value for lr
|
||||
; pc Initial value for pc
|
||||
; xPSR Initial value for xPSR
|
||||
;
|
||||
; Stack Bottom: (higher memory address) */
|
||||
;
|
||||
LDR r2, [r0, #16] ; Pickup end of stack area
|
||||
BIC r2, r2, #0x7 ; Align frame for 8-byte alignment
|
||||
SUB r2, r2, #68 ; Subtract frame size
|
||||
LDR r3, =0xFFFFFFFD ; Build initial LR value
|
||||
STR r3, [r2, #0] ; Save on the stack
|
||||
;
|
||||
; /* Actually build the stack frame. */
|
||||
;
|
||||
MOV r3, #0 ; Build initial register value
|
||||
STR r3, [r2, #4] ; Store initial r4
|
||||
STR r3, [r2, #8] ; Store initial r5
|
||||
STR r3, [r2, #12] ; Store initial r6
|
||||
STR r3, [r2, #16] ; Store initial r7
|
||||
STR r3, [r2, #20] ; Store initial r8
|
||||
STR r3, [r2, #24] ; Store initial r9
|
||||
STR r3, [r2, #28] ; Store initial r10
|
||||
STR r3, [r2, #32] ; Store initial r11
|
||||
;
|
||||
; /* Hardware stack follows. */
|
||||
;
|
||||
STR r3, [r2, #36] ; Store initial r0
|
||||
STR r3, [r2, #40] ; Store initial r1
|
||||
STR r3, [r2, #44] ; Store initial r2
|
||||
STR r3, [r2, #48] ; Store initial r3
|
||||
STR r3, [r2, #52] ; Store initial r12
|
||||
MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value
|
||||
STR r3, [r2, #56] ; Store initial lr
|
||||
STR r1, [r2, #60] ; Store initial pc
|
||||
MOV r3, #0x01000000 ; Only T-bit need be set
|
||||
STR r3, [r2, #64] ; Store initial xPSR
|
||||
;
|
||||
; /* Setup stack pointer. */
|
||||
; thread_ptr -> tx_thread_stack_ptr = r2;
|
||||
;
|
||||
STR r2, [r0, #8] ; Save stack pointer in thread's
|
||||
; control block
|
||||
BX lr ; Return to caller
|
||||
;}
|
||||
END
|
||||
@@ -0,0 +1,85 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Thread */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_thread_system_return Cortex-M3/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is target processor specific. It is used to transfer */
|
||||
;/* control from a thread back to the ThreadX system. Only a */
|
||||
;/* minimal context is saved since the compiler assumes temp registers */
|
||||
;/* are going to get slicked by a function call anyway. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_thread_schedule Thread scheduling loop */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* ThreadX components */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_thread_system_return(VOID)
|
||||
;{
|
||||
EXPORT _tx_thread_system_return
|
||||
_tx_thread_system_return
|
||||
;
|
||||
; /* Return to real scheduler via PendSV. Note that this routine is often
|
||||
; replaced with in-line assembly in tx_port.h to improved performance. */
|
||||
;
|
||||
MOV r0, #0x10000000 ; Load PENDSVSET bit
|
||||
MOV r1, #0xE000E000 ; Load NVIC base
|
||||
STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR
|
||||
MRS r0, IPSR ; Pickup IPSR
|
||||
CMP r0, #0 ; Is it a thread returning?
|
||||
BNE _isr_context ; If ISR, skip interrupt enable
|
||||
MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK
|
||||
CPSIE i ; Enable interrupts
|
||||
MSR PRIMASK, r1 ; Restore original interrupt posture
|
||||
_isr_context
|
||||
BX lr ; Return to caller
|
||||
;}
|
||||
END
|
||||
@@ -0,0 +1,259 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Timer */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
IMPORT _tx_timer_time_slice
|
||||
IMPORT _tx_timer_system_clock
|
||||
IMPORT _tx_timer_current_ptr
|
||||
IMPORT _tx_timer_list_start
|
||||
IMPORT _tx_timer_list_end
|
||||
IMPORT _tx_timer_expired_time_slice
|
||||
IMPORT _tx_timer_expired
|
||||
IMPORT _tx_thread_time_slice
|
||||
IMPORT _tx_timer_expiration_process
|
||||
IMPORT _tx_thread_preempt_disable
|
||||
IMPORT _tx_thread_current_ptr
|
||||
IMPORT _tx_thread_execute_ptr
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
PRESERVE8
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_timer_interrupt Cortex-M3/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* William E. Lamie, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function processes the hardware timer interrupt. This */
|
||||
;/* processing includes incrementing the system clock and checking for */
|
||||
;/* time slice and/or timer expiration. If either is found, the */
|
||||
;/* interrupt context save/restore functions are called along with the */
|
||||
;/* expiration functions. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* _tx_timer_expiration_process Timer expiration processing */
|
||||
;/* _tx_thread_time_slice Time slice interrupted thread */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* interrupt vector */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_timer_interrupt(VOID)
|
||||
;{
|
||||
EXPORT _tx_timer_interrupt
|
||||
_tx_timer_interrupt
|
||||
;
|
||||
; /* Upon entry to this routine, it is assumed that context save has already
|
||||
; been called, and therefore the compiler scratch registers are available
|
||||
; for use. */
|
||||
;
|
||||
; /* Increment the system clock. */
|
||||
; _tx_timer_system_clock++;
|
||||
;
|
||||
MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock
|
||||
LDR r0, [r1, #0] ; Pickup system clock
|
||||
ADD r0, r0, #1 ; Increment system clock
|
||||
STR r0, [r1, #0] ; Store new system clock
|
||||
;
|
||||
; /* Test for time-slice expiration. */
|
||||
; if (_tx_timer_time_slice)
|
||||
; {
|
||||
;
|
||||
MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice
|
||||
LDR r2, [r3, #0] ; Pickup time-slice
|
||||
CBZ r2, __tx_timer_no_time_slice ; Is it non-active?
|
||||
; Yes, skip time-slice processing
|
||||
;
|
||||
; /* Decrement the time_slice. */
|
||||
; _tx_timer_time_slice--;
|
||||
;
|
||||
SUB r2, r2, #1 ; Decrement the time-slice
|
||||
STR r2, [r3, #0] ; Store new time-slice value
|
||||
;
|
||||
; /* Check for expiration. */
|
||||
; if (__tx_timer_time_slice == 0)
|
||||
;
|
||||
CBNZ r2, __tx_timer_no_time_slice ; Has it expired?
|
||||
;
|
||||
; /* Set the time-slice expired flag. */
|
||||
; _tx_timer_expired_time_slice = TX_TRUE;
|
||||
;
|
||||
MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag
|
||||
MOV r0, #1 ; Build expired value
|
||||
STR r0, [r3, #0] ; Set time-slice expiration flag
|
||||
;
|
||||
; }
|
||||
;
|
||||
__tx_timer_no_time_slice
|
||||
;
|
||||
; /* Test for timer expiration. */
|
||||
; if (*_tx_timer_current_ptr)
|
||||
; {
|
||||
;
|
||||
MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address
|
||||
LDR r0, [r1, #0] ; Pickup current timer
|
||||
LDR r2, [r0, #0] ; Pickup timer list entry
|
||||
CBZ r2, __tx_timer_no_timer ; Is there anything in the list?
|
||||
; No, just increment the timer
|
||||
;
|
||||
; /* Set expiration flag. */
|
||||
; _tx_timer_expired = TX_TRUE;
|
||||
;
|
||||
MOV32 r3, _tx_timer_expired ; Pickup expiration flag address
|
||||
MOV r2, #1 ; Build expired value
|
||||
STR r2, [r3, #0] ; Set expired flag
|
||||
B __tx_timer_done ; Finished timer processing
|
||||
;
|
||||
; }
|
||||
; else
|
||||
; {
|
||||
__tx_timer_no_timer
|
||||
;
|
||||
; /* No timer expired, increment the timer pointer. */
|
||||
; _tx_timer_current_ptr++;
|
||||
;
|
||||
ADD r0, r0, #4 ; Move to next timer
|
||||
;
|
||||
; /* Check for wrap-around. */
|
||||
; if (_tx_timer_current_ptr == _tx_timer_list_end)
|
||||
;
|
||||
MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end
|
||||
LDR r2, [r3, #0] ; Pickup list end
|
||||
CMP r0, r2 ; Are we at list end?
|
||||
BNE __tx_timer_skip_wrap ; No, skip wrap-around logic
|
||||
;
|
||||
; /* Wrap to beginning of list. */
|
||||
; _tx_timer_current_ptr = _tx_timer_list_start;
|
||||
;
|
||||
MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start
|
||||
LDR r0, [r3, #0] ; Set current pointer to list start
|
||||
;
|
||||
__tx_timer_skip_wrap
|
||||
;
|
||||
STR r0, [r1, #0] ; Store new current timer pointer
|
||||
; }
|
||||
;
|
||||
__tx_timer_done
|
||||
;
|
||||
;
|
||||
; /* See if anything has expired. */
|
||||
; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
|
||||
; {
|
||||
;
|
||||
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag
|
||||
LDR r2, [r3, #0] ; Pickup time-slice expired flag
|
||||
CBNZ r2, __tx_something_expired ; Did a time-slice expire?
|
||||
; If non-zero, time-slice expired
|
||||
MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag
|
||||
LDR r0, [r1, #0] ; Pickup timer expired flag
|
||||
CBZ r0, __tx_timer_nothing_expired ; Did a timer expire?
|
||||
; No, nothing expired
|
||||
;
|
||||
__tx_something_expired
|
||||
;
|
||||
;
|
||||
STMDB sp!, {r0, lr} ; Save the lr register on the stack
|
||||
; and save r0 just to keep 8-byte alignment
|
||||
;
|
||||
; /* Did a timer expire? */
|
||||
; if (_tx_timer_expired)
|
||||
; {
|
||||
;
|
||||
MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag
|
||||
LDR r0, [r1, #0] ; Pickup timer expired flag
|
||||
CBZ r0, __tx_timer_dont_activate ; Check for timer expiration
|
||||
; If not set, skip timer activation
|
||||
;
|
||||
; /* Process timer expiration. */
|
||||
; _tx_timer_expiration_process();
|
||||
;
|
||||
BL _tx_timer_expiration_process ; Call the timer expiration handling routine
|
||||
;
|
||||
; }
|
||||
__tx_timer_dont_activate
|
||||
;
|
||||
; /* Did time slice expire? */
|
||||
; if (_tx_timer_expired_time_slice)
|
||||
; {
|
||||
;
|
||||
MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired
|
||||
LDR r2, [r3, #0] ; Pickup the actual flag
|
||||
CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set
|
||||
; No, skip time-slice processing
|
||||
;
|
||||
; /* Time slice interrupted thread. */
|
||||
; _tx_thread_time_slice();
|
||||
|
||||
BL _tx_thread_time_slice ; Call time-slice processing
|
||||
MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag
|
||||
LDR r1, [r0] ; Is the preempt disable flag set?
|
||||
CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic
|
||||
MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r1, [r0] ; Pickup the current thread pointer
|
||||
MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address
|
||||
LDR r3, [r2] ; Pickup the execute thread pointer
|
||||
MOV32 r0, 0xE000ED04 ; Build address of control register
|
||||
MOV32 r2, 0x10000000 ; Build value for PendSV bit
|
||||
CMP r1, r3 ; Are they the same?
|
||||
BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed
|
||||
STR r2, [r0] ; Not the same, issue the PendSV for preemption
|
||||
__tx_timer_skip_time_slice
|
||||
;
|
||||
; }
|
||||
;
|
||||
__tx_timer_not_ts_expiration
|
||||
;
|
||||
LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for
|
||||
;
|
||||
; }
|
||||
;
|
||||
__tx_timer_nothing_expired
|
||||
|
||||
DSB ; Complete all memory access
|
||||
BX lr ; Return to caller
|
||||
;
|
||||
;}
|
||||
ALIGN
|
||||
LTORG
|
||||
END
|
||||
@@ -0,0 +1,399 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_power_of_two_block_size Cortex-M3/MPU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function calculates a power of two size at or immediately above*/
|
||||
/* the input size and returns it to the caller. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* size Block size */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* calculated size Rounded up to power of two */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
ULONG _txm_power_of_two_block_size(ULONG size)
|
||||
{
|
||||
/* Check for 0 size. */
|
||||
if(size == 0)
|
||||
return 0;
|
||||
|
||||
/* Minimum MPU block size is 32. */
|
||||
if(size <= 32)
|
||||
return 32;
|
||||
|
||||
/* Bit twiddling trick to round to next high power of 2
|
||||
(if original size is power of 2, it will return original size. Perfect!) */
|
||||
size--;
|
||||
size |= size >> 1;
|
||||
size |= size >> 2;
|
||||
size |= size >> 4;
|
||||
size |= size >> 8;
|
||||
size |= size >> 16;
|
||||
size++;
|
||||
|
||||
/* Return a power of 2 size at or above the input size. */
|
||||
return(size);
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_alignment_adjust Cortex-M3/MPU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function adjusts the alignment and size of the code and data */
|
||||
/* section for a given module implementation. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_preamble Pointer to module preamble */
|
||||
/* code_size Size of the code area (updated) */
|
||||
/* code_alignment Code area alignment (updated) */
|
||||
/* data_size Size of data area (updated) */
|
||||
/* data_alignment Data area alignment (updated) */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _txm_power_of_two_block_size Calculate power of two size */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Initial thread stack frame */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble,
|
||||
ULONG *code_size,
|
||||
ULONG *code_alignment,
|
||||
ULONG *data_size,
|
||||
ULONG *data_alignment)
|
||||
{
|
||||
|
||||
ULONG local_code_size;
|
||||
ULONG local_code_alignment;
|
||||
ULONG local_data_size;
|
||||
ULONG local_data_alignment;
|
||||
ULONG code_block_size;
|
||||
ULONG data_block_size;
|
||||
ULONG code_size_accum;
|
||||
ULONG data_size_accum;
|
||||
|
||||
/* Copy the input parameters into local variables for ease of use. */
|
||||
local_code_size = *code_size;
|
||||
local_code_alignment = *code_alignment;
|
||||
local_data_size = *data_size;
|
||||
local_data_alignment = *data_alignment;
|
||||
|
||||
|
||||
/* Test for external memory enabled in preamble. */
|
||||
if(module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)
|
||||
{
|
||||
/* External/shared memory enabled. TXM_MODULE_MANAGER_CODE_MPU_ENTRIES-1 code entries will be used. */
|
||||
if (local_code_size <= (32*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 32 is best. */
|
||||
code_block_size = 32;
|
||||
}
|
||||
else if (local_code_size <= (64*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 64 is best. */
|
||||
code_block_size = 64;
|
||||
}
|
||||
else if (local_code_size <= (128*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 128 is best. */
|
||||
code_block_size = 128;
|
||||
}
|
||||
else if (local_code_size <= (256*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 256 is best. */
|
||||
code_block_size = 256;
|
||||
}
|
||||
else if (local_code_size <= (512*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 512 is best. */
|
||||
code_block_size = 512;
|
||||
}
|
||||
else if (local_code_size <= (1024*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 1024 is best. */
|
||||
code_block_size = 1024;
|
||||
}
|
||||
else if (local_code_size <= (2048*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 2048 is best. */
|
||||
code_block_size = 2048;
|
||||
}
|
||||
else if (local_code_size <= (4096*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 4096 is best. */
|
||||
code_block_size = 4096;
|
||||
}
|
||||
else if (local_code_size <= (8192*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 8192 is best. */
|
||||
code_block_size = 8192;
|
||||
}
|
||||
else if (local_code_size <= (16384*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 16384 is best. */
|
||||
code_block_size = 16384;
|
||||
}
|
||||
else if (local_code_size <= (32768*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 32768 is best. */
|
||||
code_block_size = 32768;
|
||||
}
|
||||
else if (local_code_size <= (65536*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 65536 is best. */
|
||||
code_block_size = 65536;
|
||||
}
|
||||
else if (local_code_size <= (131072*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 131072 is best. */
|
||||
code_block_size = 131072;
|
||||
}
|
||||
else if (local_code_size <= (262144*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 262144 is best. */
|
||||
code_block_size = 262144;
|
||||
}
|
||||
else if (local_code_size <= (524288*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 524288 is best. */
|
||||
code_block_size = 524288;
|
||||
}
|
||||
else if (local_code_size <= (1048576*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 1048576 is best. */
|
||||
code_block_size = 1048576;
|
||||
}
|
||||
else if (local_code_size <= (2097152*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 2097152 is best. */
|
||||
code_block_size = 2097152;
|
||||
}
|
||||
else if (local_code_size <= (4194304*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)))
|
||||
{
|
||||
/* Block size of 4194304 is best. */
|
||||
code_block_size = 4194304;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Just set block size to 32MB just to create an allocation error! */
|
||||
code_block_size = 33554432;
|
||||
}
|
||||
|
||||
/* Calculate the new code size. */
|
||||
local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1);
|
||||
|
||||
/* Determine if the code block size is greater than the current alignment. If so, use block size
|
||||
as the alignment. */
|
||||
if (code_block_size > local_code_alignment)
|
||||
local_code_alignment = code_block_size;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Determine code block sizes. Minimize the alignment requirement.
|
||||
There are 4 MPU code entries available. The following is how the code size
|
||||
will be distributed:
|
||||
1. 1/4 of the largest power of two that is greater than or equal to code size.
|
||||
2. 1/4 of the largest power of two that is greater than or equal to code size.
|
||||
3. Largest power of 2 that fits in the remaining space.
|
||||
4. Smallest power of 2 that exceeds the remaining space, minimum 32. */
|
||||
local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2;
|
||||
code_size_accum = local_code_alignment + local_code_alignment;
|
||||
code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1);
|
||||
code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum);
|
||||
local_code_size = code_size_accum;
|
||||
}
|
||||
|
||||
/* Determine the best data block size, which in our case is the minimal alignment. */
|
||||
if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 32 is best. */
|
||||
data_block_size = 32;
|
||||
}
|
||||
else if (local_data_size <= (64*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 64 is best. */
|
||||
data_block_size = 64;
|
||||
}
|
||||
else if (local_data_size <= (128*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 128 is best. */
|
||||
data_block_size = 128;
|
||||
}
|
||||
else if (local_data_size <= (256*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 256 is best. */
|
||||
data_block_size = 256;
|
||||
}
|
||||
else if (local_data_size <= (512*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 512 is best. */
|
||||
data_block_size = 512;
|
||||
}
|
||||
else if (local_data_size <= (1024*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 1024 is best. */
|
||||
data_block_size = 1024;
|
||||
}
|
||||
else if (local_data_size <= (2048*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 2048 is best. */
|
||||
data_block_size = 2048;
|
||||
}
|
||||
else if (local_data_size <= (4096*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 4096 is best. */
|
||||
data_block_size = 4096;
|
||||
}
|
||||
else if (local_data_size <= (8192*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 8192 is best. */
|
||||
data_block_size = 8192;
|
||||
}
|
||||
else if (local_data_size <= (16384*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 16384 is best. */
|
||||
data_block_size = 16384;
|
||||
}
|
||||
else if (local_data_size <= (32768*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 32768 is best. */
|
||||
data_block_size = 32768;
|
||||
}
|
||||
else if (local_data_size <= (65536*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 65536 is best. */
|
||||
data_block_size = 65536;
|
||||
}
|
||||
else if (local_data_size <= (131072*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 131072 is best. */
|
||||
data_block_size = 131072;
|
||||
}
|
||||
else if (local_data_size <= (262144*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 262144 is best. */
|
||||
data_block_size = 262144;
|
||||
}
|
||||
else if (local_data_size <= (524288*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 524288 is best. */
|
||||
data_block_size = 524288;
|
||||
}
|
||||
else if (local_data_size <= (1048576*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 1048576 is best. */
|
||||
data_block_size = 1048576;
|
||||
}
|
||||
else if (local_data_size <= (2097152*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 2097152 is best. */
|
||||
data_block_size = 2097152;
|
||||
}
|
||||
else if (local_data_size <= (4194304*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES))
|
||||
{
|
||||
/* Block size of 4194304 is best. */
|
||||
data_block_size = 4194304;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Just set data block size to 32MB just to create an allocation error! */
|
||||
data_block_size = 33554432;
|
||||
}
|
||||
|
||||
/* Calculate the new data size. */
|
||||
data_size_accum = data_block_size;
|
||||
while(data_size_accum < local_data_size)
|
||||
{
|
||||
data_size_accum += data_block_size;
|
||||
}
|
||||
local_data_size = data_size_accum;
|
||||
|
||||
/* Determine if the data block size is greater than the current alignment. If so, use block size
|
||||
as the alignment. */
|
||||
if (data_block_size > local_data_alignment)
|
||||
{
|
||||
local_data_alignment = data_block_size;
|
||||
}
|
||||
|
||||
/* Return all the information to the caller. */
|
||||
*code_size = local_code_size;
|
||||
*code_alignment = local_code_alignment;
|
||||
*data_size = local_data_size;
|
||||
*data_alignment = local_data_alignment;
|
||||
}
|
||||
@@ -0,0 +1,182 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_mutex.h"
|
||||
#include "tx_queue.h"
|
||||
#include "tx_thread.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_external_memory_enable Cortex-M3/MPU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function creates an entry in the MPU table for a shared */
|
||||
/* memory space. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_instance Module instance pointer */
|
||||
/* start_address Start address of memory */
|
||||
/* length Length of external memory */
|
||||
/* attributes Memory attributes (r/w) */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* status Completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_mutex_get Get protection mutex */
|
||||
/* _tx_mutex_put Release protection mutex */
|
||||
/* _txm_power_of_two_block_size Round length to power of two */
|
||||
/* _txm_module_manager_mm_register_setup Reconfigure MPU registers */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance,
|
||||
VOID *start_address,
|
||||
ULONG length,
|
||||
UINT attributes)
|
||||
{
|
||||
|
||||
ULONG block_size;
|
||||
ULONG region_size;
|
||||
ULONG subregion_bits;
|
||||
ULONG address;
|
||||
UINT attributes_check = 0;
|
||||
TXM_MODULE_PREAMBLE *module_preamble;
|
||||
|
||||
/* Determine if the module manager has not been initialized yet. */
|
||||
if (_txm_module_manager_ready != TX_TRUE)
|
||||
{
|
||||
/* Module manager has not been initialized. */
|
||||
return(TX_NOT_AVAILABLE);
|
||||
}
|
||||
|
||||
/* Determine if the module is valid. */
|
||||
if (module_instance == TX_NULL)
|
||||
{
|
||||
/* Invalid module pointer. */
|
||||
return(TX_PTR_ERROR);
|
||||
}
|
||||
|
||||
/* Get module manager protection mutex. */
|
||||
_tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER);
|
||||
|
||||
/* Determine if the module instance is valid. */
|
||||
if (module_instance -> txm_module_instance_id != TXM_MODULE_ID)
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Invalid module pointer. */
|
||||
return(TX_PTR_ERROR);
|
||||
}
|
||||
|
||||
/* Determine if the module instance is in the loaded state. */
|
||||
if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED)
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Return error if the module is not ready. */
|
||||
return(TX_START_ERROR);
|
||||
}
|
||||
|
||||
/* Check if preamble shared mem and mem protection property bits are set. */
|
||||
module_preamble = module_instance -> txm_module_instance_preamble_ptr;
|
||||
if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS))
|
||||
!= (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS))
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Return error if bit not set. */
|
||||
return(TXM_MODULE_INVALID_PROPERTIES);
|
||||
}
|
||||
|
||||
/* Start address and length must adhere to Cortex-M MPU.
|
||||
The address must align with the block size. */
|
||||
|
||||
block_size = _txm_power_of_two_block_size(length);
|
||||
address = (ULONG) start_address;
|
||||
if(address != (address & ~(block_size - 1)))
|
||||
{
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Return alignment error. */
|
||||
return(TXM_MODULE_ALIGNMENT_ERROR);
|
||||
}
|
||||
|
||||
/* At this point, we have a valid address and block size.
|
||||
Set up MPU registers. */
|
||||
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10;
|
||||
|
||||
/* Calculate the region size. */
|
||||
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
|
||||
/* Calculate the subregion bits. */
|
||||
subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length);
|
||||
|
||||
/* Check for valid attributes. */
|
||||
if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE)
|
||||
{
|
||||
attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT;
|
||||
}
|
||||
|
||||
/* Build register with attributes. */
|
||||
module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001;
|
||||
|
||||
/* Keep track of shared memory address and length in module instance. */
|
||||
module_instance -> txm_module_instance_shared_memory_address = address;
|
||||
module_instance -> txm_module_instance_shared_memory_length = length;
|
||||
|
||||
/* Recalculate MPU settings. */
|
||||
_txm_module_manager_mm_register_setup(module_instance);
|
||||
|
||||
/* Release the protection mutex. */
|
||||
_tx_mutex_put(&_txm_module_manager_mutex);
|
||||
|
||||
/* Return success. */
|
||||
return(TX_SUCCESS);
|
||||
}
|
||||
@@ -0,0 +1,110 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_thread.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/* Define the user's fault notification callback function pointer. This is
|
||||
setup via the txm_module_manager_memory_fault_notify API. */
|
||||
|
||||
VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *);
|
||||
|
||||
|
||||
/* Define a macro that can be used to allocate global variables useful to
|
||||
store information about the last fault. This macro is defined in
|
||||
txm_module_port.h and is usually populated in the assembly language
|
||||
fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */
|
||||
|
||||
TXM_MODULE_MANAGER_FAULT_INFO
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_memory_fault_handler Cortex-M3/MPU/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function handles a fault associated with a memory protected */
|
||||
/* module. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _tx_thread_terminate Terminate thread */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Fault handler */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_manager_memory_fault_handler(VOID)
|
||||
{
|
||||
|
||||
TXM_MODULE_INSTANCE *module_instance_ptr;
|
||||
TX_THREAD *thread_ptr;
|
||||
|
||||
/* Pickup the current thread. */
|
||||
thread_ptr = _tx_thread_current_ptr;
|
||||
|
||||
/* Initialize the module instance pointer to NULL. */
|
||||
module_instance_ptr = TX_NULL;
|
||||
|
||||
/* Is there a thread? */
|
||||
if (thread_ptr)
|
||||
{
|
||||
/* Pickup the module instance. */
|
||||
module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr;
|
||||
|
||||
/* Terminate the current thread. */
|
||||
_tx_thread_terminate(_tx_thread_current_ptr);
|
||||
}
|
||||
|
||||
/* Determine if there is a user memory fault notification callback. */
|
||||
if (_txm_module_manager_fault_notify)
|
||||
{
|
||||
/* Yes, call the user's notification memory fault callback. */
|
||||
(_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,84 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "tx_thread.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/* Define the external user's fault notification callback function pointer. This is
|
||||
setup via the txm_module_manager_memory_fault_notify API. */
|
||||
|
||||
extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *);
|
||||
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_memory_fault_notify Cortex-M3/MPU/AC5 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function registers an application callback when/if a memory */
|
||||
/* fault occurs. The supplied thread is automatically terminated, but */
|
||||
/* any other threads in the same module may still execute. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* notify_function Memory fault notification */
|
||||
/* function, NULL disables. */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* status Completion status */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* Application Code */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *))
|
||||
{
|
||||
/* Setup notification function. */
|
||||
_txm_module_manager_fault_notify = notify_function;
|
||||
|
||||
/* Return success. */
|
||||
return(TX_SUCCESS);
|
||||
}
|
||||
@@ -0,0 +1,512 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Module Manager */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
#define TX_SOURCE_CODE
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_region_size_get Cortex-M3/MPU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function converts the region size in bytes to the block size */
|
||||
/* for the Cortex-M3 MPU specification. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* block_size Size of the block in bytes */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* MPU size specification */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _txm_module_manager_mm_register_setup */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
ULONG _txm_module_manager_region_size_get(ULONG block_size)
|
||||
{
|
||||
|
||||
ULONG return_value;
|
||||
|
||||
/* Process relative to the input block size. */
|
||||
if (block_size == 32)
|
||||
{
|
||||
return_value = 0x04;
|
||||
}
|
||||
else if (block_size == 64)
|
||||
{
|
||||
return_value = 0x05;
|
||||
}
|
||||
else if (block_size == 128)
|
||||
{
|
||||
return_value = 0x06;
|
||||
}
|
||||
else if (block_size == 256)
|
||||
{
|
||||
return_value = 0x07;
|
||||
}
|
||||
else if (block_size == 512)
|
||||
{
|
||||
return_value = 0x08;
|
||||
}
|
||||
else if (block_size == 1024)
|
||||
{
|
||||
return_value = 0x09;
|
||||
}
|
||||
else if (block_size == 2048)
|
||||
{
|
||||
return_value = 0x0A;
|
||||
}
|
||||
else if (block_size == 4096)
|
||||
{
|
||||
return_value = 0x0B;
|
||||
}
|
||||
else if (block_size == 8192)
|
||||
{
|
||||
return_value = 0x0C;
|
||||
}
|
||||
else if (block_size == 16384)
|
||||
{
|
||||
return_value = 0x0D;
|
||||
}
|
||||
else if (block_size == 32768)
|
||||
{
|
||||
return_value = 0x0E;
|
||||
}
|
||||
else if (block_size == 65536)
|
||||
{
|
||||
return_value = 0x0F;
|
||||
}
|
||||
else if (block_size == 131072)
|
||||
{
|
||||
return_value = 0x10;
|
||||
}
|
||||
else if (block_size == 262144)
|
||||
{
|
||||
return_value = 0x11;
|
||||
}
|
||||
else if (block_size == 524288)
|
||||
{
|
||||
return_value = 0x12;
|
||||
}
|
||||
else if (block_size == 1048576)
|
||||
{
|
||||
return_value = 0x13;
|
||||
}
|
||||
else if (block_size == 2097152)
|
||||
{
|
||||
return_value = 0x14;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Max 4MB MPU pages for modules. */
|
||||
return_value = 0x15;
|
||||
}
|
||||
|
||||
return(return_value);
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_calculate_srd_bits Cortex-M3/MPU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function calculates the SRD bits that need to be set to */
|
||||
/* protect "length" bytes in a block. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* block_size Size of the block in bytes */
|
||||
/* length Actual length in bytes */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* SRD bits to be OR'ed with region attribute register. */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _txm_module_manager_mm_register_setup */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length)
|
||||
{
|
||||
|
||||
ULONG srd_bits = 0;
|
||||
UINT srd_bit_index;
|
||||
|
||||
/* length is smaller than block_size, set SRD bits if block_size is 256 or more. */
|
||||
if((block_size >= 256) && (length < block_size))
|
||||
{
|
||||
/* Divide block_size by 8 by shifting right 3. Result is size of subregion. */
|
||||
block_size = block_size >> 3;
|
||||
|
||||
/* Set SRD index into attribute register. */
|
||||
srd_bit_index = 8;
|
||||
|
||||
/* If subregion overlaps length, move to the next subregion. */
|
||||
while(length > block_size)
|
||||
{
|
||||
length = length - block_size;
|
||||
srd_bit_index++;
|
||||
}
|
||||
/* Check for a portion of code remaining. */
|
||||
if(length)
|
||||
{
|
||||
srd_bit_index++;
|
||||
}
|
||||
|
||||
/* Set unused subregion bits. */
|
||||
while(srd_bit_index < 16)
|
||||
{
|
||||
srd_bits = srd_bits | (0x1 << srd_bit_index);
|
||||
srd_bit_index++;
|
||||
}
|
||||
}
|
||||
|
||||
return(srd_bits);
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _txm_module_manager_mm_register_setup Cortex-M3/MPU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function sets up the Cortex-M3 MPU register definitions based */
|
||||
/* on the module's memory characteristics. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* module_instance Pointer to module instance */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* MPU specifications for module in module_instance */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* _txm_module_manager_region_size_get */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _txm_module_manager_thread_create */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance)
|
||||
{
|
||||
|
||||
ULONG code_address;
|
||||
ULONG code_size;
|
||||
ULONG data_address;
|
||||
ULONG data_size;
|
||||
ULONG start_stop_stack_size;
|
||||
ULONG callback_stack_size;
|
||||
ULONG block_size;
|
||||
ULONG base_address_register;
|
||||
ULONG base_attribute_register;
|
||||
ULONG region_size;
|
||||
ULONG srd_bits = 0;
|
||||
UINT mpu_register = 0;
|
||||
UINT mpu_table_index;
|
||||
UINT i;
|
||||
|
||||
|
||||
/* Setup the first region for the ThreadX trampoline code. */
|
||||
/* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */
|
||||
base_address_register = (ULONG) _txm_module_manager_user_mode_entry;
|
||||
|
||||
/* Mask address to proper range, region 0, set Valid bit. */
|
||||
base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10;
|
||||
module_instance -> txm_module_instance_mpu_registers[0] = base_address_register;
|
||||
|
||||
/* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */
|
||||
module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009;
|
||||
|
||||
/* Initialize the MPU register. */
|
||||
mpu_register = 1;
|
||||
|
||||
/* Initialize the MPU table index. */
|
||||
mpu_table_index = 2;
|
||||
|
||||
/* Setup values for code area. */
|
||||
code_address = (ULONG) module_instance -> txm_module_instance_code_start;
|
||||
code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size;
|
||||
|
||||
/* Check if shared memory was set up. If so, only 3 entries are available for
|
||||
code protection. If not set up, 4 code entries are available. */
|
||||
if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0)
|
||||
{
|
||||
/* Determine code block sizes. Minimize the alignment requirement.
|
||||
There are 4 MPU code entries available. The following is how the code size
|
||||
will be distributed:
|
||||
1. 1/4 of the largest power of two that is greater than or equal to code size.
|
||||
2. 1/4 of the largest power of two that is greater than or equal to code size.
|
||||
3. Largest power of 2 that fits in the remaining space.
|
||||
4. Smallest power of 2 that exceeds the remaining space, minimum 32. */
|
||||
|
||||
/* Now loop through to setup MPU protection for the code area. */
|
||||
for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++)
|
||||
{
|
||||
/* First two MPU blocks are 1/4 of the largest power of two
|
||||
that is greater than or equal to code size. */
|
||||
if (i < 2)
|
||||
{
|
||||
block_size = _txm_power_of_two_block_size(code_size) >> 2;
|
||||
}
|
||||
|
||||
/* Third MPU block is the largest power of 2 that fits in the remaining space. */
|
||||
else if (i == 2)
|
||||
{
|
||||
/* Subtract (block_size*2) from code_size to calculate remaining space. */
|
||||
code_size = code_size - (block_size << 1);
|
||||
block_size = _txm_power_of_two_block_size(code_size) >> 1;
|
||||
}
|
||||
|
||||
/* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */
|
||||
else
|
||||
{
|
||||
/* Calculate remaining space. */
|
||||
code_size = code_size - block_size;
|
||||
block_size = _txm_power_of_two_block_size(code_size);
|
||||
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size);
|
||||
}
|
||||
|
||||
/* Build the base address register. */
|
||||
base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10;
|
||||
|
||||
/* Calculate the region size information. */
|
||||
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
|
||||
|
||||
/* Build the base attribute register. */
|
||||
base_attribute_register = region_size | srd_bits | 0x06070001;
|
||||
|
||||
/* Setup the MPU Base Address Register. */
|
||||
module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register;
|
||||
|
||||
/* Setup the MPU Base Attribute Register. */
|
||||
module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register;
|
||||
|
||||
/* Adjust the code address. */
|
||||
code_address = code_address + block_size;
|
||||
|
||||
/* Move MPU table index. */
|
||||
mpu_table_index = mpu_table_index + 2;
|
||||
|
||||
/* Increment the MPU register index. */
|
||||
mpu_register++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Only 3 code entries available. */
|
||||
else
|
||||
{
|
||||
/* Calculate block size, one code entry taken up by shared memory. */
|
||||
block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1));
|
||||
|
||||
/* Calculate the region size information. */
|
||||
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
|
||||
|
||||
/* Now loop through to setup MPU protection for the code area. */
|
||||
for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++)
|
||||
{
|
||||
/* Build the base address register. */
|
||||
base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10;
|
||||
|
||||
/* Check if SRD bits need to be set. */
|
||||
if (code_size < block_size)
|
||||
{
|
||||
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size);
|
||||
}
|
||||
|
||||
/* Build the base attribute register. */
|
||||
base_attribute_register = region_size | srd_bits | 0x06070000;
|
||||
|
||||
/* Is there still some code? If so set the region enable bit. */
|
||||
if (code_size)
|
||||
{
|
||||
/* Set the region enable bit. */
|
||||
base_attribute_register = base_attribute_register | 0x1;
|
||||
}
|
||||
/* Setup the MPU Base Address Register. */
|
||||
module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register;
|
||||
|
||||
/* Setup the MPU Base Attribute Register. */
|
||||
module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register;
|
||||
|
||||
/* Adjust the code address. */
|
||||
code_address = code_address + block_size;
|
||||
|
||||
/* Decrement the code size. */
|
||||
if (code_size > block_size)
|
||||
{
|
||||
code_size = code_size - block_size;
|
||||
}
|
||||
else
|
||||
{
|
||||
code_size = 0;
|
||||
}
|
||||
|
||||
/* Move MPU table index. */
|
||||
mpu_table_index = mpu_table_index + 2;
|
||||
|
||||
/* Increment the MPU register index. */
|
||||
mpu_register++;
|
||||
}
|
||||
|
||||
/* Adjust indeces to pass over the shared memory entry. */
|
||||
/* Move MPU table index. */
|
||||
mpu_table_index = mpu_table_index + 2;
|
||||
|
||||
/* Increment the MPU register index. */
|
||||
mpu_register++;
|
||||
}
|
||||
|
||||
/* Setup values for data area. */
|
||||
data_address = (ULONG) module_instance -> txm_module_instance_data_start;
|
||||
|
||||
/* Adjust the size of the module elements to be aligned to the default alignment. We do this
|
||||
so that when we partition the allocated memory, we can simply place these regions right beside
|
||||
each other without having to align their pointers. Note this only works when they all have
|
||||
the same alignment. */
|
||||
|
||||
data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size;
|
||||
start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size;
|
||||
callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size;
|
||||
|
||||
data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
|
||||
|
||||
start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
|
||||
|
||||
callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT;
|
||||
|
||||
/* Update the data size to include thread stacks. */
|
||||
data_size = data_size + start_stop_stack_size + callback_stack_size;
|
||||
|
||||
block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES);
|
||||
|
||||
/* Reset SRD bitfield. */
|
||||
srd_bits = 0;
|
||||
|
||||
/* Calculate the region size information. */
|
||||
region_size = (_txm_module_manager_region_size_get(block_size) << 1);
|
||||
|
||||
/* Now loop through to setup MPU protection for the data area. */
|
||||
for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++)
|
||||
{
|
||||
/* Build the base address register. */
|
||||
base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10;
|
||||
|
||||
/* Check if SRD bits need to be set. */
|
||||
if (data_size < block_size)
|
||||
{
|
||||
srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size);
|
||||
}
|
||||
|
||||
/* Build the base attribute register. */
|
||||
base_attribute_register = region_size | srd_bits | 0x13070000;
|
||||
|
||||
/* Is there still some data? If so set the region enable bit. */
|
||||
if (data_size)
|
||||
{
|
||||
/* Set the region enable bit. */
|
||||
base_attribute_register = base_attribute_register | 0x1;
|
||||
}
|
||||
|
||||
/* Setup the MPU Base Address Register. */
|
||||
module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register;
|
||||
|
||||
/* Setup the MPU Base Attribute Register. */
|
||||
module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register;
|
||||
|
||||
/* Adjust the data address. */
|
||||
data_address = data_address + block_size;
|
||||
|
||||
/* Decrement the data size. */
|
||||
if (data_size > block_size)
|
||||
{
|
||||
data_size = data_size - block_size;
|
||||
}
|
||||
else
|
||||
{
|
||||
data_size = 0;
|
||||
}
|
||||
|
||||
/* Move MPU table index. */
|
||||
mpu_table_index = mpu_table_index + 2;
|
||||
|
||||
/* Increment the MPU register index. */
|
||||
mpu_register++;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,141 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Module Manager */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY
|
||||
THUMB
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function builds a stack frame on the supplied thread's stack. */
|
||||
;/* The stack frame results in a fake interrupt return to the supplied */
|
||||
;/* function pointer. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* thread_ptr Pointer to thread */
|
||||
;/* function_ptr Pointer to shell function */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_thread_create Create thread service */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *))
|
||||
;{
|
||||
EXPORT _txm_module_manager_thread_stack_build
|
||||
_txm_module_manager_thread_stack_build
|
||||
;
|
||||
;
|
||||
; /* Build a fake interrupt frame. The form of the fake interrupt stack
|
||||
; on the Cortex-M should look like the following after it is built:
|
||||
;
|
||||
; Stack Top:
|
||||
; LR Interrupted LR (LR at time of PENDSV)
|
||||
; r4 Initial value for r4
|
||||
; r5 Initial value for r5
|
||||
; r6 Initial value for r6
|
||||
; r7 Initial value for r7
|
||||
; r8 Initial value for r8
|
||||
; r9 Initial value for r9
|
||||
; r10 Initial value for r10
|
||||
; r11 Initial value for r11
|
||||
; r0 Initial value for r0 (Hardware stack starts here!!)
|
||||
; r1 Initial value for r1
|
||||
; r2 Initial value for r2
|
||||
; r3 Initial value for r3
|
||||
; r12 Initial value for r12
|
||||
; lr Initial value for lr
|
||||
; pc Initial value for pc
|
||||
; xPSR Initial value for xPSR
|
||||
;
|
||||
; Stack Bottom: (higher memory address) */
|
||||
;
|
||||
LDR r2, [r0, #16] ; Pickup end of stack area
|
||||
BIC r2, r2, #0x7 ; Align frame
|
||||
SUB r2, r2, #68 ; Subtract frame size
|
||||
LDR r3, =0xFFFFFFFD ; Build initial LR value
|
||||
STR r3, [r2, #0] ; Save on the stack
|
||||
;
|
||||
; /* Actually build the stack frame. */
|
||||
;
|
||||
MOV r3, #0 ; Build initial register value
|
||||
STR r3, [r2, #4] ; Store initial r4
|
||||
STR r3, [r2, #8] ; Store initial r5
|
||||
STR r3, [r2, #12] ; Store initial r6
|
||||
STR r3, [r2, #16] ; Store initial r7
|
||||
STR r3, [r2, #20] ; Store initial r8
|
||||
STR r3, [r2, #28] ; Store initial r10
|
||||
STR r3, [r2, #32] ; Store initial r11
|
||||
;
|
||||
; /* Hardware stack follows. */
|
||||
;
|
||||
STR r0, [r2, #36] ; Store initial r0, which is the thread control block
|
||||
|
||||
LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block.
|
||||
; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this
|
||||
; function with the actual, initial stack pointer.
|
||||
STR r3, [r2, #40] ; Store initial r1, which is the module entry information.
|
||||
LDR r3, [r3, #8] ; Pickup data base register from the module information
|
||||
STR r3, [r2, #24] ; Store initial r9 (data base register)
|
||||
MOV r3, #0 ; Clear r3 again
|
||||
|
||||
STR r3, [r2, #44] ; Store initial r2
|
||||
STR r3, [r2, #48] ; Store initial r3
|
||||
STR r3, [r2, #52] ; Store initial r12
|
||||
MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value
|
||||
STR r3, [r2, #56] ; Store initial lr
|
||||
STR r1, [r2, #60] ; Store initial pc
|
||||
MOV r3, #0x01000000 ; Only T-bit need be set
|
||||
STR r3, [r2, #64] ; Store initial xPSR
|
||||
;
|
||||
; /* Setup stack pointer. */
|
||||
; thread_ptr -> tx_thread_stack_ptr = r2;
|
||||
;
|
||||
STR r2, [r0, #8] ; Save stack pointer in thread's control block
|
||||
BX lr ; Return to caller
|
||||
;}
|
||||
END
|
||||
|
||||
@@ -0,0 +1,88 @@
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Module Manager */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
IMPORT _txm_module_manager_kernel_dispatch
|
||||
IMPORT _tx_thread_current_ptr
|
||||
;
|
||||
AREA ||.text||, CODE, READONLY, ALIGN=5
|
||||
THUMB
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _txm_module_manager_user_mode_entry Cortex-M3/MPU/AC5 */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function allows modules to enter kernel mode. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* SVC 1 Enter kernel mode */
|
||||
;/* SVC 2 Exit kernel mode */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* Modules in user mode */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/;
|
||||
;VOID _txm_module_manager_user_mode_entry(VOID)
|
||||
;{
|
||||
EXPORT _txm_module_manager_user_mode_entry
|
||||
_txm_module_manager_user_mode_entry
|
||||
SVC 1 ; Enter kernel
|
||||
EXPORT _txm_module_priv
|
||||
_txm_module_priv
|
||||
; At this point, we are out of user mode. The original LR has been saved in the
|
||||
; thread control block. Simply call the kernel dispatch function.
|
||||
BL _txm_module_manager_kernel_dispatch
|
||||
|
||||
; Pickup the original LR value while still in privileged mode
|
||||
LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address
|
||||
LDR r3, [r2] ; Pickup current thread pointer
|
||||
LDR lr, [r3, #0xA0] ; Pickup saved LR from original call
|
||||
|
||||
SVC 2 ; Exit kernel and return to user mode
|
||||
EXPORT _txm_module_user_mode_exit
|
||||
_txm_module_user_mode_exit
|
||||
BX lr ; Return to the caller
|
||||
;}
|
||||
ALIGN 32
|
||||
END
|
||||
5
ports_module/cortex-m3/ac6/example_build/all.bat
Normal file
5
ports_module/cortex-m3/ac6/example_build/all.bat
Normal file
@@ -0,0 +1,5 @@
|
||||
@ECHO OFF
|
||||
CALL clean.bat
|
||||
CALL setenv.bat
|
||||
CALL initws.bat
|
||||
CALL build.bat
|
||||
24
ports_module/cortex-m3/ac6/example_build/build.bat
Normal file
24
ports_module/cortex-m3/ac6/example_build/build.bat
Normal file
@@ -0,0 +1,24 @@
|
||||
@ECHO OFF
|
||||
|
||||
ECHO Build starting...
|
||||
|
||||
SETLOCAL ENABLEEXTENSIONS
|
||||
|
||||
IF DEFINED ARMDSIDEC GOTO IARBUILD_DEFINED
|
||||
ECHO ERROR: please set ARMDSIDEC to the path of the ARM Developer Studio eclipsec.exe program
|
||||
EXIT /B 2
|
||||
:IARBUILD_DEFINED
|
||||
|
||||
IF EXIST %ARMDSIDEC% GOTO ARMDSIDEC_FOUND
|
||||
ECHO ERROR: the command ARMDSIDEC doesn't exist: %ARMDSIDEC%
|
||||
EXIT /B 2
|
||||
:ARMDSIDEC_FOUND
|
||||
|
||||
%ARMDSIDEC% -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild -data .\workspace -build all
|
||||
IF %ERRORLEVEL% EQU 0 GOTO BUILD_OK
|
||||
ECHO ERROR: build failed.
|
||||
EXIT /B 1
|
||||
:BUILD_OK
|
||||
|
||||
ECHO Build completed without errors.
|
||||
EXIT /B 0
|
||||
4
ports_module/cortex-m3/ac6/example_build/clean.bat
Normal file
4
ports_module/cortex-m3/ac6/example_build/clean.bat
Normal file
@@ -0,0 +1,4 @@
|
||||
@ECHO OFF
|
||||
ECHO Cleaning...
|
||||
RMDIR /Q /S workspace
|
||||
ECHO Done.
|
||||
14
ports_module/cortex-m3/ac6/example_build/initws.bat
Normal file
14
ports_module/cortex-m3/ac6/example_build/initws.bat
Normal file
@@ -0,0 +1,14 @@
|
||||
@ECHO OFF
|
||||
|
||||
ECHO Initializing the workspace...
|
||||
|
||||
SETLOCAL ENABLEEXTENSIONS
|
||||
|
||||
%ARMDSIDEC% -nosplash -application org.eclipse.cdt.managedbuilder.core.headlessbuild -data .\workspace -import .\tx -import .\txm -import .\sample_threadx -import .\sample_threadx_module -import .\sample_threadx_module_manager
|
||||
IF %ERRORLEVEL% EQU 0 GOTO WS_INITIALIZED
|
||||
ECHO ERROR: failed to initialize the workspace
|
||||
EXIT /B 2
|
||||
|
||||
:WS_INITIALIZED
|
||||
echo Workspace initialized.
|
||||
EXIT /B 0
|
||||
@@ -0,0 +1,192 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
|
||||
<cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
|
||||
<externalSettings/>
|
||||
|
||||
<extensions>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
</extensions>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base">
|
||||
|
||||
<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520." name="/" resourcePath="">
|
||||
|
||||
<toolChain id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.323848371" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.577788986" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-M3.NoFPU" valueType="string"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.floatabi.2114828810" name="Float ABI" superClass="com.arm.toolchain.v6.base.options.floatabi" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.inst.867254844" name="Instruction set" superClass="com.arm.toolchain.v6.base.options.inst" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.debug.level.2012923809" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<targetPlatform id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.323848371.1548806269" name=""/>
|
||||
|
||||
<builder autoBuildTarget="all" buildPath="${workspace_loc:/sample_threadx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1721512389" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.arm.toolchain.v6.builder"/>
|
||||
|
||||
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.114782258" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.target.1761409455" name="Target (--target)" superClass="com.arm.tool.c.compiler.v6.base.option.target" useByScannerDiscovery="true" value="arm-arm-none-eabi" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1798518755" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-m3" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.fpu.1125361312" name="FPU (-mfpu)" superClass="com.arm.tool.c.compiler.v6.base.option.fpu" useByScannerDiscovery="true" value="none" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.floatabi.1070893797" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.c.compiler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.inst.1927884242" name="Instruction set" superClass="com.arm.tool.c.compiler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1498096289" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_generic}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_port}""/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.904753152" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<inputType id="com.arm.tool.c.compiler.v6.base.input.664809547" superClass="com.arm.tool.c.compiler.v6.base.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.924824072" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1069377025" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1555411179" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.target.1007894450" name="Target (--target)" superClass="com.arm.tool.assembler.v6.base.option.target" useByScannerDiscovery="false" value="arm-arm-none-eabi" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.cpu.1820500228" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-m3" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.fpu.969773893" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" useByScannerDiscovery="true" value="none" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.floatabi.776520171" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.assembler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.inst.1333768272" name="Instruction set" superClass="com.arm.tool.assembler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.options.debug.level.429021326" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.assembler.v6.base.option.incpath.663104637" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx}""/>
|
||||
|
||||
</option>
|
||||
|
||||
<inputType id="com.arm.tool.assembler.v6.base.input.1024953339" superClass="com.arm.tool.assembler.v6.base.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.88740108" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.c.linker.option.entry.1032206829" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" useByScannerDiscovery="false" value="" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.linker.option.scatter.1463218579" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" useByScannerDiscovery="false" value="../sample_threadx.scat" valueType="string"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.c.linker.libs.402211535" name="User library files" superClass="com.arm.tool.c.linker.libs" useByScannerDiscovery="false" valueType="libs"/>
|
||||
|
||||
<option id="com.arm.tool.linker.v6.option.suppress.1394753016" name="Suppress (--diag_suppress)" superClass="com.arm.tool.linker.v6.option.suppress" useByScannerDiscovery="false" value="" valueType="string"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.implicit.libs.2146903484" name="Implicit other library files" superClass="com.arm.tool.c.linker.implicit.libs" valueType="libs">
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx/Debug/tx.a}""/>
|
||||
|
||||
</option>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
|
||||
|
||||
</toolChain>
|
||||
|
||||
</folderInfo>
|
||||
|
||||
<sourceEntries>
|
||||
|
||||
<entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
|
||||
</sourceEntries>
|
||||
|
||||
</configuration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings">
|
||||
|
||||
<externalSettings containerId="tx;" factoryId="org.eclipse.cdt.core.cfg.export.settings.sipplier">
|
||||
|
||||
<externalSetting>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
|
||||
|
||||
<entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
|
||||
|
||||
</externalSetting>
|
||||
|
||||
</externalSettings>
|
||||
|
||||
</storageModule>
|
||||
|
||||
</cconfiguration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
|
||||
<storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
|
||||
<configuration configurationName="Debug">
|
||||
|
||||
<resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
|
||||
|
||||
</configuration>
|
||||
|
||||
<configuration configurationName="Release">
|
||||
|
||||
<resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
|
||||
|
||||
</configuration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
</cproject>
|
||||
@@ -0,0 +1,28 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>sample_threadx</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
<project>tx</project>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>com.arm.debug.ds.nature</nature>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
@@ -0,0 +1,96 @@
|
||||
/*
|
||||
** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved.
|
||||
** Use, modification and redistribution of this file is subject to your possession of a
|
||||
** valid End User License Agreement for the Arm Product of which these examples are part of
|
||||
** and your compliance with all applicable terms and conditions of such licence agreement.
|
||||
*/
|
||||
|
||||
/* This file contains the default exception handlers and vector table.
|
||||
All exceptions are handled in Handler mode. Processor state is automatically
|
||||
pushed onto the stack when an exception occurs, and popped from the stack at
|
||||
the end of the handler */
|
||||
|
||||
|
||||
/* Exception Handlers */
|
||||
/* Marking as __attribute__((interrupt)) avoids them being accidentally called from elsewhere */
|
||||
|
||||
__attribute__((interrupt)) void NMIException(void)
|
||||
{ while(1); }
|
||||
|
||||
__attribute__((interrupt)) void HardFaultException(void)
|
||||
{ while(1); }
|
||||
|
||||
__attribute__((interrupt)) void MemManageException(void)
|
||||
{ while(1); }
|
||||
|
||||
__attribute__((interrupt)) void BusFaultException(void)
|
||||
{ while(1); }
|
||||
|
||||
__attribute__((interrupt)) void UsageFaultException(void)
|
||||
{ while(1); }
|
||||
|
||||
void __tx_SVCallHandler(void);
|
||||
|
||||
__attribute__((interrupt)) void DebugMonitor(void)
|
||||
{ while(1); }
|
||||
|
||||
void __tx_PendSVHandler(void);
|
||||
|
||||
void __tx_SysTickHandler(void);
|
||||
|
||||
__attribute__((interrupt)) void InterruptHandler(void)
|
||||
{ while(1); }
|
||||
|
||||
|
||||
/* typedef for the function pointers in the vector table */
|
||||
typedef void(* const ExecFuncPtr)(void) __attribute__((interrupt));
|
||||
|
||||
/* Linker-generated Stack Base address */
|
||||
#ifdef TWO_REGION
|
||||
extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for Two Region model */
|
||||
#else
|
||||
extern unsigned int Image$$ARM_LIB_STACKHEAP$$ZI$$Limit; /* for (default) One Region model */
|
||||
#endif
|
||||
|
||||
/* Entry point for C run-time initialization */
|
||||
extern int __main(void);
|
||||
|
||||
|
||||
/* Vector table
|
||||
Create a named ELF section for the vector table that can be placed in a scatter file.
|
||||
The first two entries are:
|
||||
Initial SP = |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| for (default) One Region model
|
||||
or |Image$$ARM_LIB_STACK$$ZI$$Limit| for Two Region model
|
||||
Initial PC= &__main (with LSB set to indicate Thumb)
|
||||
*/
|
||||
|
||||
ExecFuncPtr vector_table[] __attribute__((section("vectors"))) = {
|
||||
/* Configure Initial Stack Pointer using linker-generated symbol */
|
||||
#ifdef TWO_REGION
|
||||
#pragma import(__use_two_region_memory)
|
||||
(ExecFuncPtr)&Image$$ARM_LIB_STACK$$ZI$$Limit,
|
||||
#else /* (default) One Region model */
|
||||
(ExecFuncPtr)&Image$$ARM_LIB_STACKHEAP$$ZI$$Limit,
|
||||
#endif
|
||||
(ExecFuncPtr)__main, /* Initial PC, set to entry point */
|
||||
NMIException,
|
||||
HardFaultException,
|
||||
MemManageException,
|
||||
BusFaultException,
|
||||
UsageFaultException,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
__tx_SVCallHandler,
|
||||
DebugMonitor,
|
||||
0, /* Reserved */
|
||||
__tx_PendSVHandler,
|
||||
__tx_SysTickHandler,
|
||||
|
||||
/* Add up to 240 interrupt handlers, starting here... */
|
||||
InterruptHandler,
|
||||
InterruptHandler, /* Some dummy interrupt handlers */
|
||||
InterruptHandler
|
||||
/*
|
||||
:
|
||||
*/
|
||||
};
|
||||
|
||||
@@ -0,0 +1,370 @@
|
||||
/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
|
||||
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
|
||||
byte pool, and block pool. */
|
||||
|
||||
#include "tx_api.h"
|
||||
|
||||
#define DEMO_STACK_SIZE 1024
|
||||
#define DEMO_BYTE_POOL_SIZE 9120
|
||||
#define DEMO_BLOCK_POOL_SIZE 100
|
||||
#define DEMO_QUEUE_SIZE 100
|
||||
|
||||
|
||||
/* Define the ThreadX object control blocks... */
|
||||
|
||||
TX_THREAD thread_0;
|
||||
TX_THREAD thread_1;
|
||||
TX_THREAD thread_2;
|
||||
TX_THREAD thread_3;
|
||||
TX_THREAD thread_4;
|
||||
TX_THREAD thread_5;
|
||||
TX_THREAD thread_6;
|
||||
TX_THREAD thread_7;
|
||||
TX_QUEUE queue_0;
|
||||
TX_SEMAPHORE semaphore_0;
|
||||
TX_MUTEX mutex_0;
|
||||
TX_EVENT_FLAGS_GROUP event_flags_0;
|
||||
TX_BYTE_POOL byte_pool_0;
|
||||
TX_BLOCK_POOL block_pool_0;
|
||||
UCHAR memory_area[DEMO_BYTE_POOL_SIZE];
|
||||
|
||||
|
||||
/* Define the counters used in the demo application... */
|
||||
|
||||
ULONG thread_0_counter;
|
||||
ULONG thread_1_counter;
|
||||
ULONG thread_1_messages_sent;
|
||||
ULONG thread_2_counter;
|
||||
ULONG thread_2_messages_received;
|
||||
ULONG thread_3_counter;
|
||||
ULONG thread_4_counter;
|
||||
ULONG thread_5_counter;
|
||||
ULONG thread_6_counter;
|
||||
ULONG thread_7_counter;
|
||||
|
||||
|
||||
/* Define thread prototypes. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input);
|
||||
void thread_1_entry(ULONG thread_input);
|
||||
void thread_2_entry(ULONG thread_input);
|
||||
void thread_3_and_4_entry(ULONG thread_input);
|
||||
void thread_5_entry(ULONG thread_input);
|
||||
void thread_6_and_7_entry(ULONG thread_input);
|
||||
|
||||
|
||||
/* Define main entry point. */
|
||||
|
||||
int main()
|
||||
{
|
||||
|
||||
/* Enter the ThreadX kernel. */
|
||||
tx_kernel_enter();
|
||||
}
|
||||
|
||||
|
||||
/* Define what the initial system looks like. */
|
||||
|
||||
void tx_application_define(void *first_unused_memory)
|
||||
{
|
||||
|
||||
CHAR *pointer = TX_NULL;
|
||||
|
||||
|
||||
/* Create a byte memory pool from which to allocate the thread stacks. */
|
||||
tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE);
|
||||
|
||||
/* Put system definition stuff in here, e.g. thread creates and other assorted
|
||||
create information. */
|
||||
|
||||
/* Allocate the stack for thread 0. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create the main thread. */
|
||||
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
|
||||
/* Allocate the stack for thread 1. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 1 and 2. These threads pass information through a ThreadX
|
||||
message queue. It is also interesting to note that these threads have a time
|
||||
slice. */
|
||||
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 2. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 3. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
|
||||
An interesting thing here is that both threads share the same instruction area. */
|
||||
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 4. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 5. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create thread 5. This thread simply pends on an event flag which will be set
|
||||
by thread_0. */
|
||||
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 6. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
|
||||
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 7. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the message queue. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
|
||||
|
||||
/* Create the message queue shared by threads 1 and 2. */
|
||||
tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
|
||||
|
||||
/* Create the semaphore used by threads 3 and 4. */
|
||||
tx_semaphore_create(&semaphore_0, "semaphore 0", 1);
|
||||
|
||||
/* Create the event flags group used by threads 1 and 5. */
|
||||
tx_event_flags_create(&event_flags_0, "event flags 0");
|
||||
|
||||
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
|
||||
tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT);
|
||||
|
||||
/* Allocate the memory for a small block pool. */
|
||||
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create a block memory pool to allocate a message buffer from. */
|
||||
tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
|
||||
|
||||
/* Allocate a block and release the block memory. */
|
||||
tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
|
||||
|
||||
/* Release the block back to the pool. */
|
||||
tx_block_release(pointer);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Define the test threads. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This thread simply sits in while-forever-sleep loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_0_counter++;
|
||||
|
||||
/* Sleep for 10 ticks. */
|
||||
tx_thread_sleep(10);
|
||||
|
||||
/* Set event flag 0 to wakeup thread 5. */
|
||||
status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_1_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This thread simply sends messages to a queue shared by thread 2. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_1_counter++;
|
||||
|
||||
/* Send message to queue 0. */
|
||||
status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Increment the message sent. */
|
||||
thread_1_messages_sent++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_2_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
ULONG received_message;
|
||||
UINT status;
|
||||
|
||||
/* This thread retrieves messages placed on the queue by thread 1. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_2_counter++;
|
||||
|
||||
/* Retrieve a message from the queue. */
|
||||
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status and make sure the message is what we
|
||||
expected. */
|
||||
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
|
||||
break;
|
||||
|
||||
/* Otherwise, all is okay. Increment the received message count. */
|
||||
thread_2_messages_received++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_3_and_4_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 3 and thread 4. As the loop
|
||||
below shows, these function compete for ownership of semaphore_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 3)
|
||||
thread_3_counter++;
|
||||
else
|
||||
thread_4_counter++;
|
||||
|
||||
/* Get the semaphore with suspension. */
|
||||
status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the semaphore. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the semaphore. */
|
||||
status = tx_semaphore_put(&semaphore_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_5_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
ULONG actual_flags;
|
||||
|
||||
|
||||
/* This thread simply waits for an event in a forever loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_5_counter++;
|
||||
|
||||
/* Wait for event flag 0. */
|
||||
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
|
||||
&actual_flags, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_6_and_7_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 6 and thread 7. As the loop
|
||||
below shows, these function compete for ownership of mutex_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 6)
|
||||
thread_6_counter++;
|
||||
else
|
||||
thread_7_counter++;
|
||||
|
||||
/* Get the mutex with suspension. */
|
||||
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Get the mutex again with suspension. This shows
|
||||
that an owning thread may retrieve the mutex it
|
||||
owns multiple times. */
|
||||
status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the mutex. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the mutex. */
|
||||
status = tx_mutex_put(&mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Release the mutex again. This will actually
|
||||
release ownership since it was obtained twice. */
|
||||
status = tx_mutex_put(&mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,204 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="com.arm.debugger.launcher2">
|
||||
<mapAttribute key="AverageDurationTracker">
|
||||
<mapEntry key="*Fetching Data Model" value="3704067"/>
|
||||
<mapEntry key="*list global low level symbols" value="5160893"/>
|
||||
<mapEntry key="*loading memory from target" value="1021338"/>
|
||||
<mapEntry key="*loading values from target" value="6245592"/>
|
||||
<mapEntry key="*updating expressions" value="10737583"/>
|
||||
<mapEntry key="AddEventObserver" value="5847121"/>
|
||||
<mapEntry key="Evaluate" value="4426509"/>
|
||||
<mapEntry key="areCachesAvailable" value="1289325"/>
|
||||
<mapEntry key="break" value="24576787"/>
|
||||
<mapEntry key="checking tracepoints" value="179912"/>
|
||||
<mapEntry key="compute execution mode" value="1472483"/>
|
||||
<mapEntry key="continue" value="63356751"/>
|
||||
<mapEntry key="core" value="12063200"/>
|
||||
<mapEntry key="disassemble" value="133766350"/>
|
||||
<mapEntry key="get byte order" value="547046"/>
|
||||
<mapEntry key="get capabilities" value="769712"/>
|
||||
<mapEntry key="get cwd" value="257600"/>
|
||||
<mapEntry key="get execution addresss" value="939114"/>
|
||||
<mapEntry key="get source lines" value="910089"/>
|
||||
<mapEntry key="getValidEncodings" value="2701300"/>
|
||||
<mapEntry key="initialize command help" value="89763533"/>
|
||||
<mapEntry key="interrupt" value="5971155"/>
|
||||
<mapEntry key="list breakpoint options" value="1601609"/>
|
||||
<mapEntry key="list breakpoints" value="4818383"/>
|
||||
<mapEntry key="list instruction sets" value="1210293"/>
|
||||
<mapEntry key="list signals" value="57072950"/>
|
||||
<mapEntry key="list watchpoint options" value="8737273"/>
|
||||
<mapEntry key="list watchpoints" value="2037086"/>
|
||||
<mapEntry key="loadfile" value="789023674"/>
|
||||
<mapEntry key="remove" value="2216250"/>
|
||||
<mapEntry key="set CWD" value="7735290"/>
|
||||
<mapEntry key="set breakpoint properties" value="13618931"/>
|
||||
<mapEntry key="set debug-from" value="2268406"/>
|
||||
<mapEntry key="start" value="187042961"/>
|
||||
<mapEntry key="toggleBreakpoint" value="19974512"/>
|
||||
<mapEntry key="waitForTargetToStop" value="62206940"/>
|
||||
</mapAttribute>
|
||||
<intAttribute key="DEBUG_TAB..RESOURCES.COUNT" value="0"/>
|
||||
<intAttribute key="FILES.CONNECT_TO_GDB_SERVER.RESOURCES.COUNT" value="0"/>
|
||||
<intAttribute key="FILES.DEBUG_EXISTING_ANDROID.RESOURCES.COUNT" value="0"/>
|
||||
<listAttribute key="FILES.DEBUG_RESIDENT_ANDROID"/>
|
||||
<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
|
||||
<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.VALUE" value=""/>
|
||||
<intAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.COUNT" value="1"/>
|
||||
<listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
|
||||
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
|
||||
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.VALUE" value=""/>
|
||||
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="APPLICATION_ON_TARGET"/>
|
||||
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
|
||||
<intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
|
||||
<listAttribute key="FILES.DOWNLOAD_AND_DEBUG">
|
||||
<listEntry value="ON_DEMAND_LOAD"/>
|
||||
<listEntry value="ALSO_LOAD_SYMBOLS"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="TARGET_DOWNLOAD_DIR"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
|
||||
<intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
|
||||
<listAttribute key="FILES.DOWNLOAD_DEBUG">
|
||||
<listEntry value="ON_DEMAND_LOAD"/>
|
||||
<listEntry value="ALSO_LOAD_SYMBOLS"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="TARGET_DOWNLOAD_DIR"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
|
||||
<intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
|
||||
<intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
|
||||
<listAttribute key="FILES.ICE_DEBUG">
|
||||
<listEntry value="ON_DEMAND_LOAD"/>
|
||||
<listEntry value="ALSO_LOAD_SYMBOLS"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.VALUE" value="${workspace_loc:/sample_threadx/Debug/sample_threadx.axf}"/>
|
||||
<intAttribute key="FILES.ICE_DEBUG.RESOURCES.COUNT" value="1"/>
|
||||
<listAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE">
|
||||
<listEntry value="ON_DEMAND_LOAD"/>
|
||||
<listEntry value="ALSO_LOAD_SYMBOLS"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.VALUE" value=""/>
|
||||
<intAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.COUNT" value="1"/>
|
||||
<listAttribute key="FILES.ICE_DEBUG_WITH_TRACE">
|
||||
<listEntry value="ON_DEMAND_LOAD"/>
|
||||
<listEntry value="ALSO_LOAD_SYMBOLS"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.VALUE" value=""/>
|
||||
<intAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.COUNT" value="1"/>
|
||||
<stringAttribute key="FILES.SELECTED_DEBUG_OPEATION" value="ICE_DEBUG"/>
|
||||
<stringAttribute key="HOST_WORKING_DIR" value="${workspace_loc}"/>
|
||||
<booleanAttribute key="HOST_WORKING_DIR_USE_DEFAULT" value="true"/>
|
||||
<booleanAttribute key="KEY_COMMANDS_AFTER_CONNECT" value="false"/>
|
||||
<stringAttribute key="KEY_COMMANDS_AFTER_CONNECT_TEXT" value=""/>
|
||||
<booleanAttribute key="KEY_COMMANDS_AS_CONNECT" value="false"/>
|
||||
<intAttribute key="Messages.POST_TRIGGER_CAPTURE_SIZE.getLocalisedValue().FMTrace" value="50"/>
|
||||
<booleanAttribute key="Messages.STOP_ON_TRIGGER.getLocalisedValue().FMTrace" value="false"/>
|
||||
<booleanAttribute key="RSE_USE_HOSTNAME" value="true"/>
|
||||
<stringAttribute key="TCP_DISABLE_EXTENDED_MODE" value="true"/>
|
||||
<booleanAttribute key="TCP_KILL_ON_EXIT" value="false"/>
|
||||
<booleanAttribute key="VFS_ENABLED" value="true"/>
|
||||
<stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
|
||||
<stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
|
||||
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.addresses">
|
||||
<listEntry value="<Next Instruction>"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.ranges">
|
||||
<listEntry value="100"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.MemoryView.addresses">
|
||||
<listEntry value="&(thread_0_counter)"/>
|
||||
<listEntry value=""/>
|
||||
</listAttribute>
|
||||
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.MemoryView.ranges">
|
||||
<listEntry value="sizeof(thread_0_counter)"/>
|
||||
<listEntry value=""/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="config_db_activity_name" value="Debug Cortex-M3"/>
|
||||
<stringAttribute key="config_db_connection_keys" value="dtsl_config dtsl_tracecapture_option dtsl_config_script model_params config_file setup TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
|
||||
<stringAttribute key="config_db_connection_type" value="Bare Metal Debug"/>
|
||||
<stringAttribute key="config_db_platform_name" value="Arm FVP (Installed with Arm DS) - MPS2_Cortex_M3"/>
|
||||
<stringAttribute key="config_db_project_type" value="Bare Metal Debug"/>
|
||||
<stringAttribute key="config_db_project_type_id" value="BARE_METAL"/>
|
||||
<stringAttribute key="config_db_taxonomy_id" value="/platform/armfvp_installedwitharmds_/mps2_cortex_m3"/>
|
||||
<stringAttribute key="config_file" value="CDB://cadi_config.xml"/>
|
||||
<booleanAttribute key="connectOnly" value="false"/>
|
||||
<listAttribute key="debugger.view.DisassemblyView:current">
|
||||
<listEntry value="<Next Instruction>"/>
|
||||
<listEntry value="100"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="debugger.view.ExpressionsView">
|
||||
<listEntry value="thread_0_counter"/>
|
||||
<listEntry value="thread_1_counter"/>
|
||||
<listEntry value="thread_1_messages_sent"/>
|
||||
<listEntry value="thread_2_counter"/>
|
||||
<listEntry value="thread_2_messages_received"/>
|
||||
<listEntry value="thread_3_counter"/>
|
||||
<listEntry value="thread_4_counter"/>
|
||||
<listEntry value="thread_5_counter"/>
|
||||
<listEntry value="thread_6_counter"/>
|
||||
<listEntry value="thread_7_counter"/>
|
||||
</listAttribute>
|
||||
<mapAttribute key="debugger.view.ExpressionsView.ExpressionsData">
|
||||
<mapEntry key="0" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="1" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="2" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="3" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="4" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="5" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="6" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="7" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="8" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="9" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
</mapAttribute>
|
||||
<stringAttribute key="debugger.view.ExpressionsView:DebugOutlineColumnState" value="OutlineConfig1	8	0	true	true	200	-1	true	1	false	true	90	-1	true	2	true	true	108	-1	true	3	true	true	57	-1	true	4	true	true	50	-1	true	5	true	true	37	-1	true	6	true	true	82	-1	true	7	true	true	53	-1	true"/>
|
||||
<stringAttribute key="debugger.view.MemoryView" value="<?xml version="1.0" encoding="UTF-8"?> <page> 	<memoryView/> </page> "/>
|
||||
<listAttribute key="debugger.view.MemoryView:current">
|
||||
<listEntry value="&(thread_0_counter)"/>
|
||||
<listEntry value="sizeof(thread_0_counter)"/>
|
||||
</listAttribute>
|
||||
<booleanAttribute key="debugger.view.expression.DrawAsHex" value="false"/>
|
||||
<stringAttribute key="dtsl_config" value="DtslScript"/>
|
||||
<stringAttribute key="dtsl_config_script" value="CDB://dtsl_config_script.py"/>
|
||||
<stringAttribute key="dtsl_options_file" value="default"/>
|
||||
<stringAttribute key="dtsl_tracecapture_option" value="options.traceBuffer.traceCaptureDevice"/>
|
||||
<stringAttribute key="launch_configuration_version" value="2020.0"/>
|
||||
<booleanAttribute key="linuxOS" value="false"/>
|
||||
<stringAttribute key="model_params" value=""/>
|
||||
<stringAttribute key="os_extension_id" value="com.arm.debug.os.threadx"/>
|
||||
<booleanAttribute key="runAfterConnect" value="false"/>
|
||||
<listAttribute key="setup">
|
||||
<listEntry value="CDB://Scripts/rtsm_launcher.py"/>
|
||||
<listEntry value=""FVP_MPS2_Cortex-M3""/>
|
||||
</listAttribute>
|
||||
<booleanAttribute key="single_platform" value="true"/>
|
||||
<stringAttribute key="stopAtExpression" value="main"/>
|
||||
<stringAttribute key="watchpoints" value="<?xml version="1.0" encoding="UTF-8"?> <watchpoints> </watchpoints> "/>
|
||||
</launchConfiguration>
|
||||
@@ -0,0 +1,44 @@
|
||||
;*******************************************************
|
||||
; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved.
|
||||
; Use, modification and redistribution of this file is subject to your possession of a
|
||||
; valid End User License Agreement for the Arm Product of which these examples are part of
|
||||
; and your compliance with all applicable terms and conditions of such licence agreement.
|
||||
;*******************************************************
|
||||
|
||||
; Scatter-file for Cortex-M3 bare-metal example
|
||||
|
||||
; This scatter-file places the vector table, application code, data, stacks and heap at suitable addresses in the memory map.
|
||||
|
||||
; The vector table is placed first at the start of the image.
|
||||
; Code starts after the last entry in the vector table.
|
||||
; Data is placed at an address that must correspond to RAM.
|
||||
; Stack and Heap are placed using ARM_LIB_STACKHEAP, to eliminate the need to set stack-base or heap-base in the debugger.
|
||||
; System Control Space registers appear at their architecturally-defined addresses, based at 0xE000E000.
|
||||
|
||||
|
||||
LOAD_REGION 0x00000000
|
||||
{
|
||||
VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0
|
||||
{
|
||||
exceptions.o (vectors, +FIRST) ; from exceptions.c
|
||||
}
|
||||
|
||||
; Code is placed immediately (+0) after the previous root region
|
||||
; (so code region will also be a root region)
|
||||
CODE +0
|
||||
{
|
||||
* (+RO) ; All program code, including library code
|
||||
}
|
||||
|
||||
DATA +0
|
||||
{
|
||||
* (+RW, +ZI) ; All RW and ZI data
|
||||
}
|
||||
|
||||
; Heap grows upwards from start of this region and
|
||||
; Stack grows downwards from end of this region
|
||||
; The Main Stack Pointer is initialized on reset to the top addresses of this region
|
||||
ARM_LIB_STACKHEAP +0 EMPTY 0x1000
|
||||
{
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,231 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Initialize */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
.global _tx_thread_system_stack_ptr
|
||||
.global _tx_initialize_unused_memory
|
||||
.global _tx_timer_interrupt
|
||||
.global __main
|
||||
.global __tx_NMIHandler // NMI
|
||||
.global __tx_BadHandler // HardFault
|
||||
.global __tx_SVCallHandler // SVCall
|
||||
.global __tx_DBGHandler // Monitor
|
||||
.global __tx_PendSVHandler // PendSV
|
||||
.global __tx_SysTickHandler // SysTick
|
||||
.global __tx_IntHandler // Int 0
|
||||
|
||||
|
||||
SYSTEM_CLOCK = 6000000
|
||||
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
|
||||
|
||||
|
||||
.text 32
|
||||
.align 4
|
||||
.syntax unified
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_initialize_low_level Cortex-M3/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* William E. Lamie, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for any low-level processor */
|
||||
/* initialization, including setting up interrupt vectors, setting */
|
||||
/* up a periodic timer interrupt source, saving the system stack */
|
||||
/* pointer for use in ISR processing later, and finding the first */
|
||||
/* available RAM memory address for tx_application_define. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_initialize_low_level(VOID)
|
||||
// {
|
||||
.global _tx_initialize_low_level
|
||||
.thumb_func
|
||||
_tx_initialize_low_level:
|
||||
|
||||
/* Disable interrupts during ThreadX initialization. */
|
||||
|
||||
CPSID i
|
||||
|
||||
/* Set base of available memory to end of non-initialised RAM area. */
|
||||
|
||||
LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer
|
||||
LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit // Build first free address
|
||||
ADD r1, r1, #4 //
|
||||
STR r1, [r0] // Setup first unused memory pointer
|
||||
|
||||
/* Setup Vector Table Offset Register. */
|
||||
|
||||
MOV r0, #0xE000E000 // Build address of NVIC registers
|
||||
LDR r1, =vector_table // Pickup address of vector table
|
||||
STR r1, [r0, #0xD08] // Set vector table address
|
||||
|
||||
/* Set system stack pointer from vector value. */
|
||||
|
||||
LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer
|
||||
LDR r1, =vector_table // Pickup address of vector table
|
||||
LDR r1, [r1] // Pickup reset stack pointer
|
||||
STR r1, [r0] // Save system stack pointer
|
||||
|
||||
/* Enable the cycle count register. */
|
||||
|
||||
LDR r0, =0xE0001000 // Build address of DWT register
|
||||
LDR r1, [r0] // Pickup the current value
|
||||
ORR r1, r1, #1 // Set the CYCCNTENA bit
|
||||
STR r1, [r0] // Enable the cycle count register
|
||||
|
||||
/* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */
|
||||
|
||||
MOV r0, #0xE000E000 // Build address of NVIC registers
|
||||
LDR r1, =SYSTICK_CYCLES
|
||||
STR r1, [r0, #0x14] // Setup SysTick Reload Value
|
||||
MOV r1, #0x7 // Build SysTick Control Enable Value
|
||||
STR r1, [r0, #0x10] // Setup SysTick Control
|
||||
|
||||
/* Configure handler priorities. */
|
||||
|
||||
LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM
|
||||
STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers
|
||||
|
||||
LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv
|
||||
STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers
|
||||
// Note: SVC must be lowest priority, which is 0xFF
|
||||
|
||||
LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM
|
||||
STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers
|
||||
// Note: PnSV must be lowest priority, which is 0xFF
|
||||
|
||||
/* Return to caller. */
|
||||
|
||||
BX lr
|
||||
// }
|
||||
|
||||
|
||||
/* Define shells for each of the unused vectors. */
|
||||
|
||||
.global __tx_BadHandler
|
||||
.thumb_func
|
||||
__tx_BadHandler:
|
||||
B __tx_BadHandler
|
||||
|
||||
/* added to catch the hardfault */
|
||||
|
||||
.global __tx_HardfaultHandler
|
||||
.thumb_func
|
||||
__tx_HardfaultHandler:
|
||||
B __tx_HardfaultHandler
|
||||
|
||||
/* Generic interrupt handler template */
|
||||
.global __tx_IntHandler
|
||||
.thumb_func
|
||||
__tx_IntHandler:
|
||||
// VOID InterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0, lr}
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
BL _tx_execution_isr_enter // Call the ISR enter function
|
||||
#endif
|
||||
|
||||
/* Do interrupt handler work here */
|
||||
/* BL <your C Function>.... */
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
BL _tx_execution_isr_exit // Call the ISR exit function
|
||||
#endif
|
||||
POP {r0, lr}
|
||||
BX LR
|
||||
// }
|
||||
|
||||
/* System Tick timer interrupt handler */
|
||||
.global __tx_SysTickHandler
|
||||
.global SysTick_Handler
|
||||
.thumb_func
|
||||
__tx_SysTickHandler:
|
||||
.thumb_func
|
||||
SysTick_Handler:
|
||||
// VOID TimerInterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0, lr}
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
BL _tx_execution_isr_enter // Call the ISR enter function
|
||||
#endif
|
||||
BL _tx_timer_interrupt
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
BL _tx_execution_isr_exit // Call the ISR exit function
|
||||
#endif
|
||||
POP {r0, lr}
|
||||
BX LR
|
||||
// }
|
||||
|
||||
|
||||
/* NMI, DBG handlers */
|
||||
.global __tx_NMIHandler
|
||||
.thumb_func
|
||||
__tx_NMIHandler:
|
||||
B __tx_NMIHandler
|
||||
|
||||
.global __tx_DBGHandler
|
||||
.thumb_func
|
||||
__tx_DBGHandler:
|
||||
B __tx_DBGHandler
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
/* Execution change notify functions */
|
||||
.global _tx_execution_isr_enter
|
||||
.thumb_func
|
||||
_tx_execution_isr_enter:
|
||||
BX LR
|
||||
#endif
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
/* Execution change notify functions */
|
||||
.global _tx_execution_isr_exit
|
||||
.thumb_func
|
||||
_tx_execution_isr_exit:
|
||||
BX LR
|
||||
#endif
|
||||
@@ -0,0 +1,250 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
|
||||
<cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
|
||||
<externalSettings/>
|
||||
|
||||
<extensions>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
</extensions>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base">
|
||||
|
||||
<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520." name="/" resourcePath="">
|
||||
|
||||
<toolChain id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.323848371" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.577788986" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-M3.NoFPU" valueType="string"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.floatabi.2114828810" name="Float ABI" superClass="com.arm.toolchain.v6.base.options.floatabi" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.inst.867254844" name="Instruction set" superClass="com.arm.toolchain.v6.base.options.inst" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.debug.level.2012923809" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.libs.useMicroLib.1770236450" name="Use microlib" superClass="com.arm.toolchain.v6.base.options.libs.useMicroLib" value="false" valueType="boolean"/>
|
||||
|
||||
<targetPlatform id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.323848371.1548806269" name=""/>
|
||||
|
||||
<builder autoBuildTarget="all" buildPath="${workspace_loc:/sample_threadx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1721512389" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.arm.toolchain.v6.builder"/>
|
||||
|
||||
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.114782258" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.target.1761409455" name="Target (--target)" superClass="com.arm.tool.c.compiler.v6.base.option.target" useByScannerDiscovery="true" value="arm-arm-none-eabi" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1798518755" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-m3" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.fpu.1125361312" name="FPU (-mfpu)" superClass="com.arm.tool.c.compiler.v6.base.option.fpu" useByScannerDiscovery="true" value="none" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.floatabi.1070893797" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.c.compiler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.inst.1927884242" name="Instruction set" superClass="com.arm.tool.c.compiler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1498096289" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/txm}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_generic}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_generic_modules}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_port}""/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.904753152" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.flags.277665336" name="Other flags" superClass="com.arm.tool.c.compiler.v6.base.option.flags" useByScannerDiscovery="true" valueType="stringList">
|
||||
|
||||
<listOptionValue builtIn="false" value="-fropi"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="-frwpi"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.useMicroLib.1844015923" name="Use microlib (-D__MICROLIB)" superClass="com.arm.tool.c.compiler.v6.base.useMicroLib" useByScannerDiscovery="false" value="false" valueType="boolean"/>
|
||||
|
||||
<inputType id="com.arm.tool.c.compiler.v6.base.input.664809547" superClass="com.arm.tool.c.compiler.v6.base.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.924824072" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1069377025" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1555411179" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.target.1007894450" name="Target (--target)" superClass="com.arm.tool.assembler.v6.base.option.target" useByScannerDiscovery="false" value="arm-arm-none-eabi" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.cpu.1820500228" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-m3" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.fpu.969773893" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" useByScannerDiscovery="true" value="none" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.floatabi.776520171" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.assembler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.inst.1333768272" name="Instruction set" superClass="com.arm.tool.assembler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.options.debug.level.429021326" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.assembler.v6.base.option.flags.657321992" name="Other flags" superClass="com.arm.tool.assembler.v6.base.option.flags" useByScannerDiscovery="true" valueType="stringList">
|
||||
|
||||
<listOptionValue builtIn="false" value="-fropi"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="-frwpi"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.useMicroLib.555616131" name="Use microlib (-D__MICROLIB)" superClass="com.arm.tool.assembler.v6.base.useMicroLib" useByScannerDiscovery="false" value="false" valueType="boolean"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.assembler.v6.base.option.incpath.681784039" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/txm}""/>
|
||||
|
||||
</option>
|
||||
|
||||
<inputType id="com.arm.tool.assembler.v6.base.input.1024953339" superClass="com.arm.tool.assembler.v6.base.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.88740108" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.c.linker.option.entry.1032206829" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" useByScannerDiscovery="false" value="_txm_module_thread_shell_entry" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.linker.option.scatter.1463218579" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" useByScannerDiscovery="false" value="" valueType="string"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.c.linker.libs.402211535" name="User library files" superClass="com.arm.tool.c.linker.libs" useByScannerDiscovery="false" valueType="libs"/>
|
||||
|
||||
<option id="com.arm.tool.linker.v6.option.suppress.1394753016" name="Suppress (--diag_suppress)" superClass="com.arm.tool.linker.v6.option.suppress" useByScannerDiscovery="false" value="L6412W" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.linker.option.robase.895342117" name="RO base address (--ro_base)" superClass="com.arm.tool.c.linker.option.robase" useByScannerDiscovery="false" value="0x30000" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.linker.option.rwbase.1738741927" name="RW base address (--rw_base)" superClass="com.arm.tool.c.linker.option.rwbase" useByScannerDiscovery="false" value="0x40000" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.linker.option.imagemap.928314316" name="Generate image map (--map)" superClass="com.arm.tool.c.linker.option.imagemap" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
|
||||
<option id="com.arm.tool.c.linker.option.eleminate.572315181" name="Eliminate unused sections (--remove)" superClass="com.arm.tool.c.linker.option.eleminate" useByScannerDiscovery="false" value="false" valueType="boolean"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.option.flags.1527266578" name="Other flags" superClass="com.arm.tool.c.linker.option.flags" useByScannerDiscovery="true" valueType="stringList">
|
||||
|
||||
<listOptionValue builtIn="false" value="--ropi"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="--rwpi"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="--symbols"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="--first "txm_module_preamble.o(Init)""/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="com.arm.tool.c.linker.option.redirectoutput.768531550" name="Redirect diagnostics output to file (--list)" superClass="com.arm.tool.c.linker.option.redirectoutput" useByScannerDiscovery="false" value="sample_threadx_module.map" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.linker.v6.option.useMicroLib.755943199" name="Use microlib" superClass="com.arm.tool.linker.v6.option.useMicroLib" useByScannerDiscovery="false" value="false" valueType="boolean"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.implicit.libs.444377655" name="Implicit other library files" superClass="com.arm.tool.c.linker.implicit.libs" valueType="libs">
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/txm/Debug/txm.a}""/>
|
||||
|
||||
</option>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
|
||||
|
||||
</toolChain>
|
||||
|
||||
</folderInfo>
|
||||
|
||||
<sourceEntries>
|
||||
|
||||
<entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
|
||||
</sourceEntries>
|
||||
|
||||
</configuration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings">
|
||||
|
||||
<externalSettings containerId="txm;" factoryId="org.eclipse.cdt.core.cfg.export.settings.sipplier">
|
||||
|
||||
<externalSetting>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/txm"/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/txm/Debug"/>
|
||||
|
||||
<entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
|
||||
|
||||
<entry flags="RESOLVED" kind="libraryFile" name="txm" srcPrefixMapping="" srcRootPath=""/>
|
||||
|
||||
</externalSetting>
|
||||
|
||||
</externalSettings>
|
||||
|
||||
</storageModule>
|
||||
|
||||
</cconfiguration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
|
||||
<storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
|
||||
<configuration configurationName="Debug">
|
||||
|
||||
<resource resourceType="PROJECT" workspacePath="/sample_threadx_module"/>
|
||||
|
||||
</configuration>
|
||||
|
||||
<configuration configurationName="Release">
|
||||
|
||||
<resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
|
||||
|
||||
</configuration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
</cproject>
|
||||
@@ -0,0 +1,28 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>sample_threadx_module</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
<project>txm</project>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>com.arm.debug.ds.nature</nature>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
@@ -0,0 +1,432 @@
|
||||
/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes
|
||||
examples of eight threads of different priorities, using a message queue, semaphore, mutex,
|
||||
event flags group, byte pool, and block pool. */
|
||||
|
||||
/* Specify that this is a module! */
|
||||
|
||||
#define TXM_MODULE
|
||||
|
||||
|
||||
/* Include the ThreadX module definitions. */
|
||||
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
/* Define constants. */
|
||||
|
||||
#define DEMO_STACK_SIZE 1024
|
||||
#define DEMO_BYTE_POOL_SIZE 9120
|
||||
#define DEMO_BLOCK_POOL_SIZE 100
|
||||
#define DEMO_QUEUE_SIZE 100
|
||||
|
||||
|
||||
/* Define the external memory area. */
|
||||
|
||||
#define EXTERNAL_MEMORY_SIZE (64 * 1024)
|
||||
#define EXTERNAL_MEMORY (0x80000)
|
||||
|
||||
|
||||
/* Define the pool space in the bss section of the module. ULONG is used to
|
||||
get the word alignment. */
|
||||
|
||||
ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4];
|
||||
|
||||
|
||||
/* Define the ThreadX object control blocks... */
|
||||
|
||||
TX_THREAD *thread_0;
|
||||
TX_THREAD *thread_1;
|
||||
TX_THREAD *thread_2;
|
||||
TX_THREAD *thread_3;
|
||||
TX_THREAD *thread_4;
|
||||
TX_THREAD *thread_5;
|
||||
TX_THREAD *thread_6;
|
||||
TX_THREAD *thread_7;
|
||||
TX_QUEUE *queue_0;
|
||||
TX_SEMAPHORE *semaphore_0;
|
||||
TX_MUTEX *mutex_0;
|
||||
TX_EVENT_FLAGS_GROUP *event_flags_0;
|
||||
TX_BYTE_POOL *byte_pool_0;
|
||||
TX_BLOCK_POOL *block_pool_0;
|
||||
|
||||
|
||||
/* Define the counters used in the demo application... */
|
||||
|
||||
ULONG thread_0_counter;
|
||||
ULONG thread_1_counter;
|
||||
ULONG thread_1_messages_sent;
|
||||
ULONG thread_2_counter;
|
||||
ULONG thread_2_messages_received;
|
||||
ULONG thread_3_counter;
|
||||
ULONG thread_4_counter;
|
||||
ULONG thread_5_counter;
|
||||
ULONG thread_6_counter;
|
||||
ULONG thread_7_counter;
|
||||
ULONG semaphore_0_puts;
|
||||
ULONG event_0_sets;
|
||||
ULONG queue_0_sends;
|
||||
|
||||
/* Define thread prototypes. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input);
|
||||
void thread_1_entry(ULONG thread_input);
|
||||
void thread_2_entry(ULONG thread_input);
|
||||
void thread_3_and_4_entry(ULONG thread_input);
|
||||
void thread_5_entry(ULONG thread_input);
|
||||
void thread_6_and_7_entry(ULONG thread_input);
|
||||
|
||||
void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr)
|
||||
{
|
||||
|
||||
if (semaphore_ptr == semaphore_0)
|
||||
semaphore_0_puts++;
|
||||
}
|
||||
|
||||
|
||||
void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr)
|
||||
{
|
||||
|
||||
if (event_flag_group_ptr == event_flags_0)
|
||||
event_0_sets++;
|
||||
}
|
||||
|
||||
|
||||
void queue_0_notify(TX_QUEUE *queue_ptr)
|
||||
{
|
||||
|
||||
if (queue_ptr == queue_0)
|
||||
queue_0_sends++;
|
||||
}
|
||||
|
||||
|
||||
/* Define the module start function. */
|
||||
|
||||
void demo_module_start(ULONG id)
|
||||
{
|
||||
|
||||
CHAR *pointer;
|
||||
|
||||
/* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within
|
||||
their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting
|
||||
the control block(s). */
|
||||
txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD));
|
||||
txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE));
|
||||
txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE));
|
||||
txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX));
|
||||
txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP));
|
||||
txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL));
|
||||
txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL));
|
||||
|
||||
|
||||
/* Create a byte memory pool from which to allocate the thread stacks. */
|
||||
tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE);
|
||||
|
||||
/* Put system definition stuff in here, e.g. thread creates and other assorted
|
||||
create information. */
|
||||
|
||||
/* Allocate the stack for thread 0. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create the main thread. */
|
||||
tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
|
||||
/* Allocate the stack for thread 1. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 1 and 2. These threads pass information through a ThreadX
|
||||
message queue. It is also interesting to note that these threads have a time
|
||||
slice. */
|
||||
tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 2. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
16, 16, 4, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 3. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
|
||||
An interesting thing here is that both threads share the same instruction area. */
|
||||
tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 4. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 5. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create thread 5. This thread simply pends on an event flag which will be set
|
||||
by thread_0. */
|
||||
tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 6. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
|
||||
tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the stack for thread 7. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
|
||||
|
||||
tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
|
||||
/* Allocate the message queue. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT);
|
||||
|
||||
/* Create the message queue shared by threads 1 and 2. */
|
||||
tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG));
|
||||
|
||||
tx_queue_send_notify(queue_0, queue_0_notify);
|
||||
|
||||
/* Create the semaphore used by threads 3 and 4. */
|
||||
tx_semaphore_create(semaphore_0, "module semaphore 0", 1);
|
||||
|
||||
tx_semaphore_put_notify(semaphore_0, semaphore_0_notify);
|
||||
|
||||
/* Create the event flags group used by threads 1 and 5. */
|
||||
tx_event_flags_create(event_flags_0, "module event flags 0");
|
||||
|
||||
tx_event_flags_set_notify(event_flags_0, event_0_notify);
|
||||
|
||||
/* Create the mutex used by thread 6 and 7 without priority inheritance. */
|
||||
tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT);
|
||||
|
||||
/* Allocate the memory for a small block pool. */
|
||||
tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT);
|
||||
|
||||
/* Create a block memory pool to allocate a message buffer from. */
|
||||
tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE);
|
||||
|
||||
/* Allocate a block and release the block memory. */
|
||||
tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT);
|
||||
|
||||
/* Release the block back to the pool. */
|
||||
tx_block_release(pointer);
|
||||
}
|
||||
|
||||
|
||||
/* Define the test threads. */
|
||||
|
||||
void thread_0_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
/* This thread simply sits in while-forever-sleep loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_0_counter++;
|
||||
|
||||
/* Sleep for 10 ticks. */
|
||||
tx_thread_sleep(10);
|
||||
|
||||
/* Set event flag 0 to wakeup thread 5. */
|
||||
status = tx_event_flags_set(event_flags_0, 0x1, TX_OR);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_1_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This thread simply sends messages to a queue shared by thread 2. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_1_counter++;
|
||||
|
||||
/* Send message to queue 0. */
|
||||
status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Increment the message sent. */
|
||||
thread_1_messages_sent++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_2_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
ULONG received_message;
|
||||
UINT status;
|
||||
|
||||
/* This thread retrieves messages placed on the queue by thread 1. */
|
||||
while(1)
|
||||
{
|
||||
/* Test external memory sharing. */
|
||||
*(ULONG *)EXTERNAL_MEMORY = 0xABABABAB;
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_2_counter++;
|
||||
|
||||
/* Retrieve a message from the queue. */
|
||||
status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check completion status and make sure the message is what we
|
||||
expected. */
|
||||
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
|
||||
break;
|
||||
|
||||
/* Otherwise, all is okay. Increment the received message count. */
|
||||
thread_2_messages_received++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_3_and_4_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 3 and thread 4. As the loop
|
||||
below shows, these function compete for ownership of semaphore_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 3)
|
||||
thread_3_counter++;
|
||||
else
|
||||
thread_4_counter++;
|
||||
|
||||
/* Get the semaphore with suspension. */
|
||||
status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the semaphore. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the semaphore. */
|
||||
status = tx_semaphore_put(semaphore_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_5_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
ULONG actual_flags;
|
||||
|
||||
|
||||
/* This thread simply waits for an event in a forever loop. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
thread_5_counter++;
|
||||
|
||||
/* Wait for event flag 0. */
|
||||
status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR,
|
||||
&actual_flags, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if ((status != TX_SUCCESS) || (actual_flags != 0x1))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void thread_6_and_7_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
UINT status;
|
||||
|
||||
|
||||
/* This function is executed from thread 6 and thread 7. As the loop
|
||||
below shows, these function compete for ownership of mutex_0. */
|
||||
while(1)
|
||||
{
|
||||
|
||||
/* Increment the thread counter. */
|
||||
if (thread_input == 6)
|
||||
thread_6_counter++;
|
||||
else
|
||||
thread_7_counter++;
|
||||
|
||||
/* Get the mutex with suspension. */
|
||||
status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Get the mutex again with suspension. This shows
|
||||
that an owning thread may retrieve the mutex it
|
||||
owns multiple times. */
|
||||
status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Sleep for 2 ticks to hold the mutex. */
|
||||
tx_thread_sleep(2);
|
||||
|
||||
/* Release the mutex. */
|
||||
status = tx_mutex_put(mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
|
||||
/* Release the mutex again. This will actually
|
||||
release ownership since it was obtained twice. */
|
||||
status = tx_mutex_put(mutex_0);
|
||||
|
||||
/* Check status. */
|
||||
if (status != TX_SUCCESS)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,62 @@
|
||||
.text
|
||||
.align 4
|
||||
.syntax unified
|
||||
.section Init
|
||||
|
||||
// Define public symbols
|
||||
.global __txm_module_preamble
|
||||
|
||||
// Define application-specific start/stop entry points for the module
|
||||
.global demo_module_start
|
||||
|
||||
// Define common external references
|
||||
.global _txm_module_thread_shell_entry
|
||||
.global _txm_module_callback_request_thread_entry
|
||||
|
||||
.eabi_attribute Tag_ABI_PCS_RO_data, 1
|
||||
.eabi_attribute Tag_ABI_PCS_R9_use, 1
|
||||
.eabi_attribute Tag_ABI_PCS_RW_data, 2
|
||||
|
||||
__txm_module_preamble:
|
||||
.dc.l 0x4D4F4455 // Module ID
|
||||
.dc.l 0x6 // Module Major Version
|
||||
.dc.l 0x1 // Module Minor Version
|
||||
.dc.l 32 // Module Preamble Size in 32-bit words
|
||||
.dc.l 0x12345678 // Module ID (application defined)
|
||||
.dc.l 0x01000007 // Module Properties where:
|
||||
// Bits 31-24: Compiler ID
|
||||
// 0 -> IAR
|
||||
// 1 -> ARM
|
||||
// 2 -> GNU
|
||||
// Bit 0: 0 -> Privileged mode execution
|
||||
// 1 -> User mode execution
|
||||
// Bit 1: 0 -> No MPU protection
|
||||
// 1 -> MPU protection (must have user mode selected)
|
||||
// Bit 2: 0 -> Disable shared/external memory access
|
||||
// 1 -> Enable shared/external memory access
|
||||
.dc.l _txm_module_thread_shell_entry - __txm_module_preamble // Module Shell Entry Point
|
||||
.dc.l demo_module_start - __txm_module_preamble // Module Start Thread Entry Point
|
||||
.dc.l 0 // Module Stop Thread Entry Point
|
||||
.dc.l 1 // Module Start/Stop Thread Priority
|
||||
.dc.l 1024 // Module Start/Stop Thread Stack Size
|
||||
.dc.l _txm_module_callback_request_thread_entry - __txm_module_preamble // Module Callback Thread Entry
|
||||
.dc.l 1 // Module Callback Thread Priority
|
||||
.dc.l 1024 // Module Callback Thread Stack Size
|
||||
.dc.l 0x10000 // Module Code Size
|
||||
.dc.l 0x10000 // Module Data Size
|
||||
.dc.l 0 // Reserved 0
|
||||
.dc.l 0 // Reserved 1
|
||||
.dc.l 0 // Reserved 2
|
||||
.dc.l 0 // Reserved 3
|
||||
.dc.l 0 // Reserved 4
|
||||
.dc.l 0 // Reserved 5
|
||||
.dc.l 0 // Reserved 6
|
||||
.dc.l 0 // Reserved 7
|
||||
.dc.l 0 // Reserved 8
|
||||
.dc.l 0 // Reserved 9
|
||||
.dc.l 0 // Reserved 10
|
||||
.dc.l 0 // Reserved 11
|
||||
.dc.l 0 // Reserved 12
|
||||
.dc.l 0 // Reserved 13
|
||||
.dc.l 0 // Reserved 14
|
||||
.dc.l 0 // Reserved 15
|
||||
@@ -0,0 +1,196 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
|
||||
<cconfiguration id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
|
||||
<externalSettings/>
|
||||
|
||||
<extensions>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
</extensions>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520" name="Debug" parent="com.arm.eclipse.build.config.v6.exe.debug.base">
|
||||
|
||||
<folderInfo id="com.arm.eclipse.build.config.v6.exe.debug.base.1025296520." name="/" resourcePath="">
|
||||
|
||||
<toolChain id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.323848371" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.577788986" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-M3.NoFPU" valueType="string"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.floatabi.2114828810" name="Float ABI" superClass="com.arm.toolchain.v6.base.options.floatabi" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.inst.867254844" name="Instruction set" superClass="com.arm.toolchain.v6.base.options.inst" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.debug.level.2012923809" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<targetPlatform id="com.arm.toolchain.v6.exe.debug.base.var.arm_compiler_6-6.323848371.1548806269" name=""/>
|
||||
|
||||
<builder autoBuildTarget="all" buildPath="${workspace_loc:/sample_threadx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1721512389" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.arm.toolchain.v6.builder"/>
|
||||
|
||||
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.114782258" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.target.1761409455" name="Target (--target)" superClass="com.arm.tool.c.compiler.v6.base.option.target" useByScannerDiscovery="true" value="arm-arm-none-eabi" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.1798518755" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-m3" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.fpu.1125361312" name="FPU (-mfpu)" superClass="com.arm.tool.c.compiler.v6.base.option.fpu" useByScannerDiscovery="true" value="none" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.floatabi.1070893797" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.c.compiler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.inst.1927884242" name="Instruction set" superClass="com.arm.tool.c.compiler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1498096289" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_generic}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_generic_modules}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx/inc_port}""/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.904753152" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<inputType id="com.arm.tool.c.compiler.v6.base.input.664809547" superClass="com.arm.tool.c.compiler.v6.base.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.924824072" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1069377025" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.1555411179" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.target.1007894450" name="Target (--target)" superClass="com.arm.tool.assembler.v6.base.option.target" useByScannerDiscovery="false" value="arm-arm-none-eabi" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.cpu.1820500228" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-m3" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.fpu.969773893" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" useByScannerDiscovery="true" value="none" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.floatabi.776520171" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.assembler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.inst.1333768272" name="Instruction set" superClass="com.arm.tool.assembler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.options.debug.level.429021326" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.assembler.v6.base.option.incpath.982393540" name="Include path (-I)" superClass="com.arm.tool.assembler.v6.base.option.incpath" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx}""/>
|
||||
|
||||
</option>
|
||||
|
||||
<inputType id="com.arm.tool.assembler.v6.base.input.1024953339" superClass="com.arm.tool.assembler.v6.base.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.88740108" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.c.linker.option.entry.1032206829" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" useByScannerDiscovery="false" value="" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.linker.option.scatter.1463218579" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" useByScannerDiscovery="false" value="../sample_threadx.scat" valueType="string"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.arm.tool.c.linker.libs.402211535" name="User library files" superClass="com.arm.tool.c.linker.libs" useByScannerDiscovery="false" valueType="libs"/>
|
||||
|
||||
<option id="com.arm.tool.linker.v6.option.suppress.1394753016" name="Suppress (--diag_suppress)" superClass="com.arm.tool.linker.v6.option.suppress" useByScannerDiscovery="false" value="" valueType="string"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.implicit.libs.1923699585" name="Implicit other library files" superClass="com.arm.tool.c.linker.implicit.libs" valueType="libs">
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/tx/Debug/tx.a}""/>
|
||||
|
||||
</option>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1637267746" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
|
||||
|
||||
</toolChain>
|
||||
|
||||
</folderInfo>
|
||||
|
||||
<sourceEntries>
|
||||
|
||||
<entry excluding="exceptions_old.c|reset.S|crt0.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||
|
||||
</sourceEntries>
|
||||
|
||||
</configuration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings">
|
||||
|
||||
<externalSettings containerId="sample_threadx_module;" factoryId="org.eclipse.cdt.core.cfg.export.settings.sipplier"/>
|
||||
|
||||
<externalSettings containerId="tx;" factoryId="org.eclipse.cdt.core.cfg.export.settings.sipplier">
|
||||
|
||||
<externalSetting>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
|
||||
|
||||
<entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
|
||||
|
||||
</externalSetting>
|
||||
|
||||
</externalSettings>
|
||||
|
||||
</storageModule>
|
||||
|
||||
</cconfiguration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<project id="sample_threadx.com.arm.eclipse.build.project.v6.exe.836597981" name="Executable"/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
|
||||
<storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
|
||||
<configuration configurationName="Debug">
|
||||
|
||||
<resource resourceType="PROJECT" workspacePath="/sample_threadx_module_manager"/>
|
||||
|
||||
</configuration>
|
||||
|
||||
<configuration configurationName="Release">
|
||||
|
||||
<resource resourceType="PROJECT" workspacePath="/sample_threadx"/>
|
||||
|
||||
</configuration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
</cproject>
|
||||
@@ -0,0 +1,29 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>sample_threadx_module_manager</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
<project>sample_threadx_module</project>
|
||||
<project>tx</project>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>com.arm.debug.ds.nature</nature>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
@@ -0,0 +1,93 @@
|
||||
/*
|
||||
** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved.
|
||||
** Use, modification and redistribution of this file is subject to your possession of a
|
||||
** valid End User License Agreement for the Arm Product of which these examples are part of
|
||||
** and your compliance with all applicable terms and conditions of such licence agreement.
|
||||
*/
|
||||
|
||||
/* This file contains the default exception handlers and vector table.
|
||||
All exceptions are handled in Handler mode. Processor state is automatically
|
||||
pushed onto the stack when an exception occurs, and popped from the stack at
|
||||
the end of the handler */
|
||||
|
||||
|
||||
/* Exception Handlers */
|
||||
/* Marking as __attribute__((interrupt)) avoids them being accidentally called from elsewhere */
|
||||
|
||||
__attribute__((interrupt)) void NMIException(void)
|
||||
{ while(1); }
|
||||
|
||||
__attribute__((interrupt)) void HardFaultException(void)
|
||||
{ while(1); }
|
||||
|
||||
void MemManage_Handler(void);
|
||||
|
||||
void BusFault_Handler(void);
|
||||
|
||||
void UsageFault_Handler(void);
|
||||
|
||||
void __tx_SVCallHandler(void);
|
||||
|
||||
__attribute__((interrupt)) void DebugMonitor(void)
|
||||
{ while(1); }
|
||||
|
||||
void __tx_PendSVHandler(void);
|
||||
|
||||
void __tx_SysTickHandler(void);
|
||||
|
||||
__attribute__((interrupt)) void InterruptHandler(void)
|
||||
{ while(1); }
|
||||
|
||||
|
||||
/* typedef for the function pointers in the vector table */
|
||||
typedef void(* const ExecFuncPtr)(void) __attribute__((interrupt));
|
||||
|
||||
/* Linker-generated Stack Base address */
|
||||
#ifdef TWO_REGION
|
||||
extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for Two Region model */
|
||||
#else
|
||||
extern unsigned int Image$$ARM_LIB_STACKHEAP$$ZI$$Limit; /* for (default) One Region model */
|
||||
#endif
|
||||
|
||||
/* Entry point for C run-time initialization */
|
||||
extern int __main(void);
|
||||
|
||||
|
||||
/* Vector table
|
||||
Create a named ELF section for the vector table that can be placed in a scatter file.
|
||||
The first two entries are:
|
||||
Initial SP = |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| for (default) One Region model
|
||||
or |Image$$ARM_LIB_STACK$$ZI$$Limit| for Two Region model
|
||||
Initial PC= &__main (with LSB set to indicate Thumb)
|
||||
*/
|
||||
|
||||
ExecFuncPtr vector_table[] __attribute__((section("vectors"))) = {
|
||||
/* Configure Initial Stack Pointer using linker-generated symbol */
|
||||
#ifdef TWO_REGION
|
||||
#pragma import(__use_two_region_memory)
|
||||
(ExecFuncPtr)&Image$$ARM_LIB_STACK$$ZI$$Limit,
|
||||
#else /* (default) One Region model */
|
||||
(ExecFuncPtr)&Image$$ARM_LIB_STACKHEAP$$ZI$$Limit,
|
||||
#endif
|
||||
(ExecFuncPtr)__main, /* Initial PC, set to entry point */
|
||||
NMIException,
|
||||
HardFaultException,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
__tx_SVCallHandler,
|
||||
DebugMonitor,
|
||||
0, /* Reserved */
|
||||
__tx_PendSVHandler,
|
||||
__tx_SysTickHandler,
|
||||
|
||||
/* Add up to 240 interrupt handlers, starting here... */
|
||||
InterruptHandler,
|
||||
InterruptHandler, /* Some dummy interrupt handlers */
|
||||
InterruptHandler
|
||||
/*
|
||||
:
|
||||
*/
|
||||
};
|
||||
|
||||
@@ -0,0 +1,44 @@
|
||||
;*******************************************************
|
||||
; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved.
|
||||
; Use, modification and redistribution of this file is subject to your possession of a
|
||||
; valid End User License Agreement for the Arm Product of which these examples are part of
|
||||
; and your compliance with all applicable terms and conditions of such licence agreement.
|
||||
;*******************************************************
|
||||
|
||||
; Scatter-file for Cortex-M3 bare-metal example
|
||||
|
||||
; This scatter-file places the vector table, application code, data, stacks and heap at suitable addresses in the memory map.
|
||||
|
||||
; The vector table is placed first at the start of the image.
|
||||
; Code starts after the last entry in the vector table.
|
||||
; Data is placed at an address that must correspond to RAM.
|
||||
; Stack and Heap are placed using ARM_LIB_STACKHEAP, to eliminate the need to set stack-base or heap-base in the debugger.
|
||||
; System Control Space registers appear at their architecturally-defined addresses, based at 0xE000E000.
|
||||
|
||||
|
||||
LOAD_REGION 0x00000000
|
||||
{
|
||||
VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0
|
||||
{
|
||||
exceptions.o (vectors, +FIRST) ; from exceptions.c
|
||||
}
|
||||
|
||||
; Code is placed immediately (+0) after the previous root region
|
||||
; (so code region will also be a root region)
|
||||
CODE +0
|
||||
{
|
||||
* (+RO) ; All program code, including library code
|
||||
}
|
||||
|
||||
DATA +0
|
||||
{
|
||||
* (+RW, +ZI) ; All RW and ZI data
|
||||
}
|
||||
|
||||
; Heap grows upwards from start of this region and
|
||||
; Stack grows downwards from end of this region
|
||||
; The Main Stack Pointer is initialized on reset to the top addresses of this region
|
||||
ARM_LIB_STACKHEAP +0 EMPTY 0x1000
|
||||
{
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,126 @@
|
||||
/* Small demonstration of the ThreadX module manager. */
|
||||
|
||||
#include "tx_api.h"
|
||||
#include "txm_module.h"
|
||||
|
||||
|
||||
#define DEMO_STACK_SIZE 1024
|
||||
|
||||
/* Define the ThreadX object control blocks... */
|
||||
|
||||
TX_THREAD module_manager;
|
||||
TXM_MODULE_INSTANCE my_module;
|
||||
|
||||
|
||||
/* Define the object pool area. */
|
||||
|
||||
UCHAR object_memory[16384];
|
||||
|
||||
|
||||
/* Define the module data pool area. */
|
||||
|
||||
#define MODULE_DATA_SIZE (256 * 1024)
|
||||
#define MODULE_DATA (0x40000)
|
||||
|
||||
|
||||
/* The module code should be loaded here. */
|
||||
|
||||
#define MODULE_CODE (0x30000)
|
||||
|
||||
|
||||
/* Define the external memory area. */
|
||||
|
||||
#define EXTERNAL_MEMORY_SIZE (64 * 1024)
|
||||
#define EXTERNAL_MEMORY (0x80000)
|
||||
|
||||
|
||||
/* Define the count of memory faults. */
|
||||
|
||||
ULONG memory_faults;
|
||||
|
||||
|
||||
/* Define thread prototypes. */
|
||||
|
||||
void module_manager_entry(ULONG thread_input);
|
||||
|
||||
|
||||
/* Define fault handler. */
|
||||
|
||||
VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module)
|
||||
{
|
||||
|
||||
/* Just increment the fault counter. */
|
||||
memory_faults++;
|
||||
}
|
||||
|
||||
/* Define main entry point. */
|
||||
|
||||
int main()
|
||||
{
|
||||
|
||||
/* Enter the ThreadX kernel. */
|
||||
tx_kernel_enter();
|
||||
}
|
||||
|
||||
|
||||
/* Define what the initial system looks like. */
|
||||
|
||||
void tx_application_define(void *first_unused_memory)
|
||||
{
|
||||
|
||||
CHAR *pointer = (CHAR*)first_unused_memory;
|
||||
|
||||
|
||||
tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0,
|
||||
pointer, DEMO_STACK_SIZE,
|
||||
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
|
||||
pointer = pointer + DEMO_STACK_SIZE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* Define the test threads. */
|
||||
|
||||
void module_manager_entry(ULONG thread_input)
|
||||
{
|
||||
|
||||
/* Initialize the module manager. */
|
||||
txm_module_manager_initialize((void *) MODULE_DATA, MODULE_DATA_SIZE);
|
||||
|
||||
txm_module_manager_object_pool_create(object_memory, sizeof(object_memory));
|
||||
|
||||
/* Register a fault handler. */
|
||||
txm_module_manager_memory_fault_notify(module_fault_handler);
|
||||
|
||||
/* Load the module that is already there, in this example it is placed there by the multiple image download. */
|
||||
txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE);
|
||||
|
||||
/* Enable a read/write shared memory region. */
|
||||
txm_module_manager_external_memory_enable(&my_module, (void *) EXTERNAL_MEMORY, EXTERNAL_MEMORY_SIZE, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE);
|
||||
|
||||
/* Start the module. */
|
||||
txm_module_manager_start(&my_module);
|
||||
|
||||
/* Sleep for a while.... */
|
||||
tx_thread_sleep(1000);
|
||||
|
||||
/* Stop the module. */
|
||||
txm_module_manager_stop(&my_module);
|
||||
|
||||
/* Unload the module. */
|
||||
txm_module_manager_unload(&my_module);
|
||||
|
||||
/* Load the module that is already there. */
|
||||
txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE);
|
||||
|
||||
/* Start the module again. */
|
||||
txm_module_manager_start(&my_module);
|
||||
|
||||
/* Now just spin... */
|
||||
while(1)
|
||||
{
|
||||
|
||||
tx_thread_sleep(100);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,3 @@
|
||||
wait
|
||||
load ..\sample_threadx_module\Debug\sample_threadx_module.axf
|
||||
wait
|
||||
@@ -0,0 +1,226 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="com.arm.debugger.launcher2">
|
||||
<mapAttribute key="AverageDurationTracker">
|
||||
<mapEntry key="*Fetching Data Model" value="993162"/>
|
||||
<mapEntry key="*FunctionLoader" value="246688500"/>
|
||||
<mapEntry key="*ListDynamicObjects" value="61100"/>
|
||||
<mapEntry key="*list global low level symbols" value="1537713"/>
|
||||
<mapEntry key="*loading memory from target" value="1110358"/>
|
||||
<mapEntry key="*loading values from target" value="2468128"/>
|
||||
<mapEntry key="*updating expressions" value="54760336"/>
|
||||
<mapEntry key="*updating local_variables" value="870875"/>
|
||||
<mapEntry key="*updating registers" value="3315038"/>
|
||||
<mapEntry key="AddEventObserver" value="5124552"/>
|
||||
<mapEntry key="Evaluate" value="5564553"/>
|
||||
<mapEntry key="areCachesAvailable" value="802125"/>
|
||||
<mapEntry key="backtrace" value="6192200"/>
|
||||
<mapEntry key="break" value="16484316"/>
|
||||
<mapEntry key="checking tracepoints" value="195606"/>
|
||||
<mapEntry key="compute execution mode" value="1878861"/>
|
||||
<mapEntry key="console" value="2807900"/>
|
||||
<mapEntry key="continue" value="55288305"/>
|
||||
<mapEntry key="core" value="6820750"/>
|
||||
<mapEntry key="disassemble" value="200447510"/>
|
||||
<mapEntry key="get byte order" value="322003"/>
|
||||
<mapEntry key="get capabilities" value="553471"/>
|
||||
<mapEntry key="get execution addresss" value="1063320"/>
|
||||
<mapEntry key="get source lines" value="1414927"/>
|
||||
<mapEntry key="getValidEncodings" value="2540450"/>
|
||||
<mapEntry key="initialize command help" value="83179905"/>
|
||||
<mapEntry key="interrupt" value="4382243"/>
|
||||
<mapEntry key="list breakpoint options" value="178240"/>
|
||||
<mapEntry key="list breakpoints" value="1596126"/>
|
||||
<mapEntry key="list instruction sets" value="518219"/>
|
||||
<mapEntry key="list signals" value="17723801"/>
|
||||
<mapEntry key="list watchpoint options" value="2856961"/>
|
||||
<mapEntry key="list watchpoints" value="365674"/>
|
||||
<mapEntry key="loadfile" value="376933316"/>
|
||||
<mapEntry key="next" value="34504663"/>
|
||||
<mapEntry key="remove" value="1930888"/>
|
||||
<mapEntry key="select-frame" value="2720250"/>
|
||||
<mapEntry key="set CWD" value="2772070"/>
|
||||
<mapEntry key="set breakpoint properties" value="9802408"/>
|
||||
<mapEntry key="set debug-from" value="2694197"/>
|
||||
<mapEntry key="source sample_threadx_module_manager.ds" value="48030590"/>
|
||||
<mapEntry key="source sample_threadx_module_manager_debug.ds" value="65215462"/>
|
||||
<mapEntry key="start" value="114163250"/>
|
||||
<mapEntry key="step" value="41375081"/>
|
||||
<mapEntry key="toggleBreakpoint" value="10250570"/>
|
||||
<mapEntry key="waitForTargetToStop" value="17821895"/>
|
||||
</mapAttribute>
|
||||
<intAttribute key="DEBUG_TAB..RESOURCES.COUNT" value="0"/>
|
||||
<intAttribute key="FILES.CONNECT_TO_GDB_SERVER.RESOURCES.COUNT" value="0"/>
|
||||
<intAttribute key="FILES.DEBUG_EXISTING_ANDROID.RESOURCES.COUNT" value="0"/>
|
||||
<listAttribute key="FILES.DEBUG_RESIDENT_ANDROID"/>
|
||||
<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
|
||||
<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.VALUE" value=""/>
|
||||
<intAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.COUNT" value="1"/>
|
||||
<listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
|
||||
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
|
||||
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.VALUE" value=""/>
|
||||
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="APPLICATION_ON_TARGET"/>
|
||||
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
|
||||
<intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
|
||||
<listAttribute key="FILES.DOWNLOAD_AND_DEBUG">
|
||||
<listEntry value="ON_DEMAND_LOAD"/>
|
||||
<listEntry value="ALSO_LOAD_SYMBOLS"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="TARGET_DOWNLOAD_DIR"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
|
||||
<intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
|
||||
<listAttribute key="FILES.DOWNLOAD_DEBUG">
|
||||
<listEntry value="ON_DEMAND_LOAD"/>
|
||||
<listEntry value="ALSO_LOAD_SYMBOLS"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="TARGET_DOWNLOAD_DIR"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
|
||||
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
|
||||
<intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
|
||||
<intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
|
||||
<listAttribute key="FILES.ICE_DEBUG">
|
||||
<listEntry value="ON_DEMAND_LOAD"/>
|
||||
<listEntry value="ALSO_LOAD_SYMBOLS"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG.RESOURCES.0.VALUE" value="${workspace_loc:/sample_threadx_module_manager/Debug/sample_threadx_module_manager.axf}"/>
|
||||
<intAttribute key="FILES.ICE_DEBUG.RESOURCES.COUNT" value="1"/>
|
||||
<listAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE">
|
||||
<listEntry value="ON_DEMAND_LOAD"/>
|
||||
<listEntry value="ALSO_LOAD_SYMBOLS"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.0.VALUE" value=""/>
|
||||
<intAttribute key="FILES.ICE_DEBUG_WITH_ETB_TRACE.RESOURCES.COUNT" value="1"/>
|
||||
<listAttribute key="FILES.ICE_DEBUG_WITH_TRACE">
|
||||
<listEntry value="ON_DEMAND_LOAD"/>
|
||||
<listEntry value="ALSO_LOAD_SYMBOLS"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="true"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
|
||||
<stringAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.0.VALUE" value=""/>
|
||||
<intAttribute key="FILES.ICE_DEBUG_WITH_TRACE.RESOURCES.COUNT" value="1"/>
|
||||
<stringAttribute key="FILES.SELECTED_DEBUG_OPEATION" value="ICE_DEBUG"/>
|
||||
<stringAttribute key="HOST_WORKING_DIR" value="${workspace_loc}"/>
|
||||
<booleanAttribute key="HOST_WORKING_DIR_USE_DEFAULT" value="true"/>
|
||||
<booleanAttribute key="KEY_COMMANDS_AFTER_CONNECT" value="false"/>
|
||||
<stringAttribute key="KEY_COMMANDS_AFTER_CONNECT_TEXT" value=""/>
|
||||
<booleanAttribute key="KEY_COMMANDS_AS_CONNECT" value="false"/>
|
||||
<intAttribute key="Messages.POST_TRIGGER_CAPTURE_SIZE.getLocalisedValue().FMTrace" value="50"/>
|
||||
<booleanAttribute key="Messages.STOP_ON_TRIGGER.getLocalisedValue().FMTrace" value="false"/>
|
||||
<booleanAttribute key="RSE_USE_HOSTNAME" value="true"/>
|
||||
<stringAttribute key="TCP_DISABLE_EXTENDED_MODE" value="true"/>
|
||||
<booleanAttribute key="TCP_KILL_ON_EXIT" value="false"/>
|
||||
<booleanAttribute key="VFS_ENABLED" value="true"/>
|
||||
<stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
|
||||
<stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
|
||||
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.addresses">
|
||||
<listEntry value="<Next Instruction>"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.ranges">
|
||||
<listEntry value="100"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.MemoryView.addresses">
|
||||
<listEntry value=""/>
|
||||
<listEntry value="&(thread_0_counter)"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.MemoryView.ranges">
|
||||
<listEntry value=""/>
|
||||
<listEntry value="sizeof(thread_0_counter)"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="com.arm.debug.views.debugConsole.DebugCommandLine.History" value="load sample_threadx_module_manager/Debug/sample_threadx_module_manager.axf;load /sample_threadx_module_manager/Debug/sample_threadx_module_manager.axf;load ..\sample_threadx_module_manager\Debug\sample_threadx_module_manager.axf;add-symbol-file ..\sample_threadx_module_manager\Debug\sample_threadx_module_manager.axf"/>
|
||||
<stringAttribute key="config_db_activity_name" value="Debug Cortex-M3"/>
|
||||
<stringAttribute key="config_db_connection_keys" value="dtsl_config dtsl_tracecapture_option dtsl_config_script model_params config_file setup TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
|
||||
<stringAttribute key="config_db_connection_type" value="Bare Metal Debug"/>
|
||||
<stringAttribute key="config_db_platform_name" value="Arm FVP (Installed with Arm DS) - MPS2_Cortex_M3"/>
|
||||
<stringAttribute key="config_db_project_type" value="Bare Metal Debug"/>
|
||||
<stringAttribute key="config_db_project_type_id" value="BARE_METAL"/>
|
||||
<stringAttribute key="config_db_taxonomy_id" value="/platform/armfvp_installedwitharmds_/mps2_cortex_m3"/>
|
||||
<stringAttribute key="config_file" value="CDB://cadi_config.xml"/>
|
||||
<booleanAttribute key="connectOnly" value="false"/>
|
||||
<listAttribute key="debugger.view.DisassemblyView:current">
|
||||
<listEntry value="<Next Instruction>"/>
|
||||
<listEntry value="100"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="debugger.view.ExpressionsView">
|
||||
<listEntry value="thread_0_counter"/>
|
||||
<listEntry value="thread_1_counter"/>
|
||||
<listEntry value="thread_1_messages_sent"/>
|
||||
<listEntry value="thread_2_counter"/>
|
||||
<listEntry value="thread_2_messages_received"/>
|
||||
<listEntry value="thread_3_counter"/>
|
||||
<listEntry value="thread_4_counter"/>
|
||||
<listEntry value="thread_5_counter"/>
|
||||
<listEntry value="thread_6_counter"/>
|
||||
<listEntry value="thread_7_counter"/>
|
||||
<listEntry value="combined_flags"/>
|
||||
</listAttribute>
|
||||
<mapAttribute key="debugger.view.ExpressionsView.ExpressionsData">
|
||||
<mapEntry key="0" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="1" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="10" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="2" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="3" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="4" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="5" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="6" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="7" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="8" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
<mapEntry key="9" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
|
||||
</mapAttribute>
|
||||
<stringAttribute key="debugger.view.ExpressionsView:DebugOutlineColumnState" value="OutlineConfig1	8	0	true	true	200	-1	true	1	false	true	90	-1	true	2	true	true	318	-1	true	3	true	true	41	-1	true	4	true	true	50	-1	true	5	true	true	37	-1	true	6	true	true	62	-1	true	7	true	true	53	-1	true"/>
|
||||
<stringAttribute key="debugger.view.MemoryView" value="<?xml version="1.0" encoding="UTF-8"?> <page> 	<memoryView/> </page> "/>
|
||||
<listAttribute key="debugger.view.MemoryView:current">
|
||||
<listEntry value=""/>
|
||||
<listEntry value=""/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="debugger.view.ModulesView:DebugOutlineColumnState" value="OutlineConfig1	5	0	true	true	53	-1	true	1	true	true	66	-1	true	2	true	true	63	-1	true	3	true	true	45	-1	true	4	true	true	67	-1	true"/>
|
||||
<stringAttribute key="debugger.view.NewRegisterView:DebugOutlineColumnState" value="OutlineConfig1	8	0	true	true	49	-1	true	1	false	true	90	-1	true	2	true	true	45	-1	true	3	false	true	41	-1	true	4	false	true	50	-1	true	5	true	true	37	-1	true	6	false	true	62	-1	true	7	true	true	53	-1	true"/>
|
||||
<stringAttribute key="debugger.view.NewRegisterView:_selectedRegisterSet" value="All registers"/>
|
||||
<mapAttribute key="debugger.view.NewRegisterView_registerSets"/>
|
||||
<stringAttribute key="debugger.view.StackView:DebugOutlineColumnState" value="OutlineConfig1	8	0	true	true	49	-1	true	1	false	true	90	-1	true	2	true	true	45	-1	true	3	true	true	41	-1	true	4	true	true	50	-1	true	5	true	true	37	-1	true	6	true	true	62	-1	true	7	true	true	53	-1	true"/>
|
||||
<booleanAttribute key="debugger.view.expression.DrawAsHex" value="false"/>
|
||||
<booleanAttribute key="debugger.view.register.DrawAsHex" value="false"/>
|
||||
<stringAttribute key="debugger.view.symbols.FunctionsView:DebugOutlineColumnState" value="OutlineConfig1	8	0	true	true	400	1	true	1	false	true	103	-1	true	2	false	true	90	-1	true	3	true	true	90	0	true	4	true	true	86	-1	true	5	false	true	41	-1	true	6	true	true	400	-1	true	7	true	true	400	-1	true"/>
|
||||
<stringAttribute key="dtsl_config" value="DtslScript"/>
|
||||
<stringAttribute key="dtsl_config_script" value="CDB://dtsl_config_script.py"/>
|
||||
<stringAttribute key="dtsl_options_file" value="default"/>
|
||||
<stringAttribute key="dtsl_tracecapture_option" value="options.traceBuffer.traceCaptureDevice"/>
|
||||
<stringAttribute key="launch_configuration_version" value="2020.0"/>
|
||||
<booleanAttribute key="linuxOS" value="false"/>
|
||||
<stringAttribute key="model_params" value=""/>
|
||||
<stringAttribute key="os_extension_id" value="com.arm.debug.os.threadx"/>
|
||||
<booleanAttribute key="runAfterConnect" value="false"/>
|
||||
<stringAttribute key="runScriptAfterConnect" value="${workspace_loc:/sample_threadx_module_manager/sample_threadx_module_manager_debug.ds}"/>
|
||||
<stringAttribute key="runTargetInitializationScript" value="${workspace_loc:/sample_threadx_module_manager/sample_threadx_module_manager.ds}"/>
|
||||
<listAttribute key="setup">
|
||||
<listEntry value="CDB://Scripts/rtsm_launcher.py"/>
|
||||
<listEntry value=""FVP_MPS2_Cortex-M3""/>
|
||||
</listAttribute>
|
||||
<booleanAttribute key="single_platform" value="true"/>
|
||||
<stringAttribute key="stopAtExpression" value="main"/>
|
||||
<stringAttribute key="watchpoints" value="<?xml version="1.0" encoding="UTF-8"?> <watchpoints> </watchpoints> "/>
|
||||
</launchConfiguration>
|
||||
@@ -0,0 +1,3 @@
|
||||
wait
|
||||
add-symbol-file ..\sample_threadx_module\Debug\sample_threadx_module.axf
|
||||
wait
|
||||
@@ -0,0 +1,231 @@
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Initialize */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
|
||||
.global _tx_thread_system_stack_ptr
|
||||
.global _tx_initialize_unused_memory
|
||||
.global _tx_timer_interrupt
|
||||
.global __main
|
||||
.global __tx_NMIHandler // NMI
|
||||
.global __tx_BadHandler // HardFault
|
||||
.global __tx_SVCallHandler // SVCall
|
||||
.global __tx_DBGHandler // Monitor
|
||||
.global __tx_PendSVHandler // PendSV
|
||||
.global __tx_SysTickHandler // SysTick
|
||||
.global __tx_IntHandler // Int 0
|
||||
|
||||
|
||||
SYSTEM_CLOCK = 6000000
|
||||
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
|
||||
|
||||
|
||||
.text 32
|
||||
.align 4
|
||||
.syntax unified
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_initialize_low_level Cortex-M3/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* William E. Lamie, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for any low-level processor */
|
||||
/* initialization, including setting up interrupt vectors, setting */
|
||||
/* up a periodic timer interrupt source, saving the system stack */
|
||||
/* pointer for use in ISR processing later, and finding the first */
|
||||
/* available RAM memory address for tx_application_define. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_initialize_low_level(VOID)
|
||||
// {
|
||||
.global _tx_initialize_low_level
|
||||
.thumb_func
|
||||
_tx_initialize_low_level:
|
||||
|
||||
/* Disable interrupts during ThreadX initialization. */
|
||||
|
||||
CPSID i
|
||||
|
||||
/* Set base of available memory to end of non-initialised RAM area. */
|
||||
|
||||
LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer
|
||||
LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit // Build first free address
|
||||
ADD r1, r1, #4 //
|
||||
STR r1, [r0] // Setup first unused memory pointer
|
||||
|
||||
/* Setup Vector Table Offset Register. */
|
||||
|
||||
MOV r0, #0xE000E000 // Build address of NVIC registers
|
||||
LDR r1, =vector_table // Pickup address of vector table
|
||||
STR r1, [r0, #0xD08] // Set vector table address
|
||||
|
||||
/* Set system stack pointer from vector value. */
|
||||
|
||||
LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer
|
||||
LDR r1, =vector_table // Pickup address of vector table
|
||||
LDR r1, [r1] // Pickup reset stack pointer
|
||||
STR r1, [r0] // Save system stack pointer
|
||||
|
||||
/* Enable the cycle count register. */
|
||||
|
||||
LDR r0, =0xE0001000 // Build address of DWT register
|
||||
LDR r1, [r0] // Pickup the current value
|
||||
ORR r1, r1, #1 // Set the CYCCNTENA bit
|
||||
STR r1, [r0] // Enable the cycle count register
|
||||
|
||||
/* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */
|
||||
|
||||
MOV r0, #0xE000E000 // Build address of NVIC registers
|
||||
LDR r1, =SYSTICK_CYCLES
|
||||
STR r1, [r0, #0x14] // Setup SysTick Reload Value
|
||||
MOV r1, #0x7 // Build SysTick Control Enable Value
|
||||
STR r1, [r0, #0x10] // Setup SysTick Control
|
||||
|
||||
/* Configure handler priorities. */
|
||||
|
||||
LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM
|
||||
STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers
|
||||
|
||||
LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv
|
||||
STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers
|
||||
// Note: SVC must be lowest priority, which is 0xFF
|
||||
|
||||
LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM
|
||||
STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers
|
||||
// Note: PnSV must be lowest priority, which is 0xFF
|
||||
|
||||
/* Return to caller. */
|
||||
|
||||
BX lr
|
||||
// }
|
||||
|
||||
|
||||
/* Define shells for each of the unused vectors. */
|
||||
|
||||
.global __tx_BadHandler
|
||||
.thumb_func
|
||||
__tx_BadHandler:
|
||||
B __tx_BadHandler
|
||||
|
||||
/* added to catch the hardfault */
|
||||
|
||||
.global __tx_HardfaultHandler
|
||||
.thumb_func
|
||||
__tx_HardfaultHandler:
|
||||
B __tx_HardfaultHandler
|
||||
|
||||
/* Generic interrupt handler template */
|
||||
.global __tx_IntHandler
|
||||
.thumb_func
|
||||
__tx_IntHandler:
|
||||
// VOID InterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0, lr}
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
BL _tx_execution_isr_enter // Call the ISR enter function
|
||||
#endif
|
||||
|
||||
/* Do interrupt handler work here */
|
||||
/* BL <your C Function>.... */
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
BL _tx_execution_isr_exit // Call the ISR exit function
|
||||
#endif
|
||||
POP {r0, lr}
|
||||
BX LR
|
||||
// }
|
||||
|
||||
/* System Tick timer interrupt handler */
|
||||
.global __tx_SysTickHandler
|
||||
.global SysTick_Handler
|
||||
.thumb_func
|
||||
__tx_SysTickHandler:
|
||||
.thumb_func
|
||||
SysTick_Handler:
|
||||
// VOID TimerInterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0, lr}
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
BL _tx_execution_isr_enter // Call the ISR enter function
|
||||
#endif
|
||||
BL _tx_timer_interrupt
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
BL _tx_execution_isr_exit // Call the ISR exit function
|
||||
#endif
|
||||
POP {r0, lr}
|
||||
BX LR
|
||||
// }
|
||||
|
||||
|
||||
/* NMI, DBG handlers */
|
||||
.global __tx_NMIHandler
|
||||
.thumb_func
|
||||
__tx_NMIHandler:
|
||||
B __tx_NMIHandler
|
||||
|
||||
.global __tx_DBGHandler
|
||||
.thumb_func
|
||||
__tx_DBGHandler:
|
||||
B __tx_DBGHandler
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
/* Execution change notify functions */
|
||||
.global _tx_execution_isr_enter
|
||||
.thumb_func
|
||||
_tx_execution_isr_enter:
|
||||
BX LR
|
||||
#endif
|
||||
|
||||
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
|
||||
/* Execution change notify functions */
|
||||
.global _tx_execution_isr_exit
|
||||
.thumb_func
|
||||
_tx_execution_isr_exit:
|
||||
BX LR
|
||||
#endif
|
||||
16
ports_module/cortex-m3/ac6/example_build/setenv.bat
Normal file
16
ports_module/cortex-m3/ac6/example_build/setenv.bat
Normal file
@@ -0,0 +1,16 @@
|
||||
@ECHO OFF
|
||||
|
||||
SET ARMDSDIR="C:\Program Files\Arm\Development Studio 2020.0"
|
||||
IF EXIST %ARMDSDIR% GOTO FOUND_ARMDS
|
||||
ECHO ARM Development Studio not found.
|
||||
EXIT /B 1
|
||||
|
||||
:FOUND_ARMDS
|
||||
SET ARMDSIDEC=%ARMDSDIR%\bin\armds_idec.exe
|
||||
IF EXIST %ARMDSIDEC% GOTO FOUND_ARMDS_IDEC
|
||||
ECHO armds_idec.exe not found.
|
||||
EXIT /B 1
|
||||
|
||||
:FOUND_ARMDS_IDEC
|
||||
ECHO armds_idec.exe found at %ARMDSIDEC%
|
||||
EXIT /B 0
|
||||
162
ports_module/cortex-m3/ac6/example_build/tx/.cproject
Normal file
162
ports_module/cortex-m3/ac6/example_build/tx/.cproject
Normal file
@@ -0,0 +1,162 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
|
||||
<cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
|
||||
<externalSettings>
|
||||
|
||||
<externalSetting>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
|
||||
|
||||
<entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
|
||||
|
||||
</externalSetting>
|
||||
|
||||
</externalSettings>
|
||||
|
||||
<extensions>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
</extensions>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base">
|
||||
|
||||
<folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551." name="/" resourcePath="">
|
||||
|
||||
<toolChain id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.1022814766" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.688166309" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-M3.NoFPU" valueType="string"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.floatabi.197203083" name="Float ABI" superClass="com.arm.toolchain.v6.base.options.floatabi" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.inst.552700328" name="Instruction set" superClass="com.arm.toolchain.v6.base.options.inst" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.debug.level.1623863720" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<targetPlatform id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.1022814766.195306460" name=""/>
|
||||
|
||||
<builder autoBuildTarget="all" buildPath="${workspace_loc:/tx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1164059605" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.toolchain.v6.builder"/>
|
||||
|
||||
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.100103692" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.target.775437314" name="Target (--target)" superClass="com.arm.tool.c.compiler.v6.base.option.target" useByScannerDiscovery="true" value="arm-arm-none-eabi" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.957518664" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-m3" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.fpu.1476959906" name="FPU (-mfpu)" superClass="com.arm.tool.c.compiler.v6.base.option.fpu" useByScannerDiscovery="true" value="none" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.floatabi.2113301488" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.c.compiler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.inst.36110020" name="Instruction set" superClass="com.arm.tool.c.compiler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1498990421" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_generic}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_port}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_generic_modules}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_generic_module_manager}""/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.536480260" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<inputType id="com.arm.tool.c.compiler.v6.base.input.1961882835" superClass="com.arm.tool.c.compiler.v6.base.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.262825882" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1390685682" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.596919840" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.target.1155866423" name="Target (--target)" superClass="com.arm.tool.assembler.v6.base.option.target" useByScannerDiscovery="false" value="arm-arm-none-eabi" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.cpu.1741335442" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-m3" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.fpu.169397194" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" useByScannerDiscovery="true" value="none" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.floatabi.1378563076" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.assembler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.inst.213408634" name="Instruction set" superClass="com.arm.tool.assembler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.options.debug.level.383141003" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<inputType id="com.arm.tool.assembler.v6.base.input.1847017761" superClass="com.arm.tool.assembler.v6.base.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1124663047" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/>
|
||||
|
||||
<tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1439633481" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
|
||||
|
||||
</toolChain>
|
||||
|
||||
</folderInfo>
|
||||
|
||||
</configuration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
|
||||
</cconfiguration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
|
||||
<configuration configurationName="Debug">
|
||||
|
||||
<resource resourceType="PROJECT" workspacePath="/tx"/>
|
||||
|
||||
</configuration>
|
||||
|
||||
<configuration configurationName="Release">
|
||||
|
||||
<resource resourceType="PROJECT" workspacePath="/tx"/>
|
||||
|
||||
</configuration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
|
||||
</cproject>
|
||||
63
ports_module/cortex-m3/ac6/example_build/tx/.project
Normal file
63
ports_module/cortex-m3/ac6/example_build/tx/.project
Normal file
@@ -0,0 +1,63 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>tx</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<linkedResources>
|
||||
<link>
|
||||
<name>inc_generic</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common/inc</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>inc_generic_module_manager</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/inc</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>inc_generic_modules</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/inc</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>inc_port</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/inc</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>src_generic</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common/src</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>src_generic_module_manager</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-5-PROJECT_LOC%7D/common_modules/module_manager/src</locationURI>
|
||||
</link>
|
||||
<link>
|
||||
<name>src_port_module_manager</name>
|
||||
<type>2</type>
|
||||
<locationURI>$%7BPARENT-2-PROJECT_LOC%7D/module_manager/src</locationURI>
|
||||
</link>
|
||||
</linkedResources>
|
||||
</projectDescription>
|
||||
184
ports_module/cortex-m3/ac6/example_build/txm/.cproject
Normal file
184
ports_module/cortex-m3/ac6/example_build/txm/.cproject
Normal file
@@ -0,0 +1,184 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
|
||||
<cconfiguration id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
|
||||
<externalSettings>
|
||||
|
||||
<externalSetting>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/txm"/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/txm/Debug"/>
|
||||
|
||||
<entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
|
||||
|
||||
<entry flags="RESOLVED" kind="libraryFile" name="txm" srcPrefixMapping="" srcRootPath=""/>
|
||||
|
||||
</externalSetting>
|
||||
|
||||
</externalSettings>
|
||||
|
||||
<extensions>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
</extensions>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551" name="Debug" parent="com.arm.eclipse.build.config.v6.lib.debug.base">
|
||||
|
||||
<folderInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1507005551." name="/" resourcePath="">
|
||||
|
||||
<toolChain id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.1022814766" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.target.cpu_fpu.688166309" superClass="com.arm.toolchain.v6.base.options.target.cpu_fpu" useByScannerDiscovery="false" value="Cortex-M3.NoFPU" valueType="string"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.floatabi.197203083" name="Float ABI" superClass="com.arm.toolchain.v6.base.options.floatabi" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.inst.552700328" name="Instruction set" superClass="com.arm.toolchain.v6.base.options.inst" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.toolchain.v6.base.options.debug.level.1623863720" name="Debug Level" superClass="com.arm.toolchain.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<targetPlatform id="com.arm.toolchain.v6.lib.debug.base.var.arm_compiler_6-6.1022814766.195306460" name=""/>
|
||||
|
||||
<builder autoBuildTarget="all" buildPath="${workspace_loc:/tx}/Debug" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1164059605" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="8" superClass="com.arm.toolchain.v6.builder"/>
|
||||
|
||||
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.100103692" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.target.775437314" name="Target (--target)" superClass="com.arm.tool.c.compiler.v6.base.option.target" useByScannerDiscovery="true" value="arm-arm-none-eabi" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.cpu.957518664" name="CPU (-mcpu)" superClass="com.arm.tool.c.compiler.v6.base.option.cpu" useByScannerDiscovery="true" value="cortex-m3" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.fpu.1476959906" name="FPU (-mfpu)" superClass="com.arm.tool.c.compiler.v6.base.option.fpu" useByScannerDiscovery="true" value="none" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.floatabi.2113301488" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.c.compiler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.option.inst.36110020" name="Instruction set" superClass="com.arm.tool.c.compiler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.incpath.1498990421" name="Include path (-I)" superClass="com.arm.tool.c.compiler.v6.base.option.incpath" useByScannerDiscovery="false" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_generic}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_port}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_generic_modules}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/inc_generic_module_manager}""/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.536480260" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.compiler.v6.base.option.flags.292072134" name="Other flags" superClass="com.arm.tool.c.compiler.v6.base.option.flags" useByScannerDiscovery="true" valueType="stringList">
|
||||
|
||||
<listOptionValue builtIn="false" value="-fropi"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="-frwpi"/>
|
||||
|
||||
</option>
|
||||
|
||||
<inputType id="com.arm.tool.c.compiler.v6.base.input.1961882835" superClass="com.arm.tool.c.compiler.v6.base.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.262825882" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.c.compiler.v6.base.options.debug.level.1390685682" name="Debug Level" superClass="com.arm.tool.c.compiler.v6.base.options.debug.level" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.596919840" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.target.1155866423" name="Target (--target)" superClass="com.arm.tool.assembler.v6.base.option.target" useByScannerDiscovery="false" value="arm-arm-none-eabi" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.cpu.1741335442" name="CPU (-mcpu)" superClass="com.arm.tool.assembler.v6.base.option.cpu" useByScannerDiscovery="false" value="cortex-m3" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.fpu.169397194" name="FPU (-mfpu)" superClass="com.arm.tool.assembler.v6.base.option.fpu" useByScannerDiscovery="true" value="none" valueType="string"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.floatabi.1378563076" name="Float ABI (-mfloat-abi)" superClass="com.arm.tool.assembler.v6.base.option.floatabi" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.floatabi.soft" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.option.inst.213408634" name="Instruction set" superClass="com.arm.tool.assembler.v6.base.option.inst" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.inst.thumb" valueType="enumerated"/>
|
||||
|
||||
<option id="com.arm.tool.assembler.v6.base.options.debug.level.383141003" name="Debug Level" superClass="com.arm.tool.assembler.v6.base.options.debug.level" useByScannerDiscovery="false" value="com.arm.tool.assembler.v6.base.options.debug.level.std" valueType="enumerated"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.assembler.v6.base.option.flags.2011130138" name="Other flags" superClass="com.arm.tool.assembler.v6.base.option.flags" useByScannerDiscovery="true" valueType="stringList">
|
||||
|
||||
<listOptionValue builtIn="false" value="-fropi"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="-frwpi"/>
|
||||
|
||||
</option>
|
||||
|
||||
<inputType id="com.arm.tool.assembler.v6.base.input.1847017761" superClass="com.arm.tool.assembler.v6.base.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1124663047" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/>
|
||||
|
||||
<tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.1439633481" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
|
||||
|
||||
</toolChain>
|
||||
|
||||
</folderInfo>
|
||||
|
||||
</configuration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
|
||||
</cconfiguration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<project id="tx.com.arm.eclipse.build.project.v6.lib.1408735755" name="Static Library"/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
|
||||
<configuration configurationName="Debug">
|
||||
|
||||
<resource resourceType="PROJECT" workspacePath="/txm"/>
|
||||
|
||||
</configuration>
|
||||
|
||||
<configuration configurationName="Release">
|
||||
|
||||
<resource resourceType="PROJECT" workspacePath="/tx"/>
|
||||
|
||||
</configuration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
|
||||
</cproject>
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user