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Release 6.1.9

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Yuxin Zhou
2021-10-14 00:51:26 +00:00
parent 215df45d4b
commit 1af8404c54
1812 changed files with 60698 additions and 249862 deletions
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2
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/.cproject
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@@ -73,7 +73,7 @@
<option id="com.arm.tool.c.linker.option.entry.1473530747" name="Image entry point (--entry)" superClass="com.arm.tool.c.linker.option.entry" useByScannerDiscovery="false" value="start64" valueType="string"/>
<option id="com.arm.tool.c.linker.option.scatter.1215444221" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" useByScannerDiscovery="false" value="..\sample_threadx.sct" valueType="string"/>
<option id="com.arm.tool.c.linker.option.scatter.1215444221" name="Scatter file (--scatter)" superClass="com.arm.tool.c.linker.option.scatter" useByScannerDiscovery="false" value="..\sample_threadx.scat" valueType="string"/>
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.arm.tool.c.linker.libs.473662930" name="User library files" superClass="com.arm.tool.c.linker.libs" useByScannerDiscovery="false" valueType="libs">

6
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3.h
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@@ -2,9 +2,9 @@
* GICv3.h - data types and function prototypes for GICv3 utility routines
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your
* possession of a valid DS-5 end user licence agreement and your compliance
* with all applicable terms and conditions of such licence agreement.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef GICV3_h
#define GICV3_h

113
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_aliases.h Normal file
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@@ -0,0 +1,113 @@
//
// Aliases for GICv3 registers
//
// Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//
#ifndef GICV3_ALIASES_H
#define GICV3_ALIASES_H
#ifndef __clang__
/*
* Mapping of MSR and MRS to physical and virtual CPU interface registers
*
* Arm Generic Interrupt Controller Architecture Specification
* GIC architecture version 3.0 and version 4.0
* Table 8-5
*/
#define ICC_AP0R0_EL1 S3_0_C12_C8_4
#define ICC_AP0R1_EL1 S3_0_C12_C8_5
#define ICC_AP0R2_EL1 S3_0_C12_C8_6
#define ICC_AP0R3_EL1 S3_0_C12_C8_7
#define ICC_AP1R0_EL1 S3_0_C12_C9_0
#define ICC_AP1R1_EL1 S3_0_C12_C9_1
#define ICC_AP1R2_EL1 S3_0_C12_C9_2
#define ICC_AP1R3_EL1 S3_0_C12_C9_3
#define ICC_ASGI1R_EL1 S3_0_C12_C11_6
#define ICC_BPR0_EL1 S3_0_C12_C8_3
#define ICC_BPR1_EL1 S3_0_C12_C12_3
#define ICC_CTLR_EL1 S3_0_C12_C12_4
#define ICC_CTLR_EL3 S3_6_C12_C12_4
#define ICC_DIR_EL1 S3_0_C12_C11_1
#define ICC_EOIR0_EL1 S3_0_C12_C8_1
#define ICC_EOIR1_EL1 S3_0_C12_C12_1
#define ICC_HPPIR0_EL1 S3_0_C12_C8_2
#define ICC_HPPIR1_EL1 S3_0_C12_C12_2
#define ICC_IAR0_EL1 S3_0_C12_C8_0
#define ICC_IAR1_EL1 S3_0_C12_C12_0
#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6
#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7
#define ICC_PMR_EL1 S3_0_C4_C6_0
#define ICC_RPR_EL1 S3_0_C12_C11_3
#define ICC_SGI0R_EL1 S3_0_C12_C11_7
#define ICC_SGI1R_EL1 S3_0_C12_C11_5
#define ICC_SRE_EL1 S3_0_C12_C12_5
#define ICC_SRE_EL2 S3_4_C12_C9_5
#define ICC_SRE_EL3 S3_6_C12_C12_5
/*
* Mapping of MSR and MRS to virtual interface control registers
*
* Arm Generic Interrupt Controller Architecture Specification
* GIC architecture version 3.0 and version 4.0
* Table 8-6
*/
#define ICH_AP0R0_EL2 S3_4_C12_C8_0
#define ICH_AP0R1_EL2 S3_4_C12_C8_1
#define ICH_AP0R2_EL2 S3_4_C12_C8_2
#define ICH_AP0R3_EL2 S3_4_C12_C8_3
#define ICH_AP1R0_EL2 S3_4_C12_C9_0
#define ICH_AP1R1_EL2 S3_4_C12_C9_1
#define ICH_AP1R2_EL2 S3_4_C12_C9_2
#define ICH_AP1R3_EL2 S3_4_C12_C9_3
#define ICH_HCR_EL2 S3_4_C12_C11_0
#define ICH_VTR_EL2 S3_4_C12_C11_1
#define ICH_MISR_EL2 S3_4_C12_C11_2
#define ICH_EISR_EL2 S3_4_C12_C11_3
#define ICH_ELRSR_EL2 S3_4_C12_C11_5
#define ICH_VMCR_EL2 S3_4_C12_C11_7
#define ICH_LR0_EL2 S3_4_C12_C12_0
#define ICH_LR1_EL2 S3_4_C12_C12_1
#define ICH_LR2_EL2 S3_4_C12_C12_2
#define ICH_LR3_EL2 S3_4_C12_C12_3
#define ICH_LR4_EL2 S3_4_C12_C12_4
#define ICH_LR5_EL2 S3_4_C12_C12_5
#define ICH_LR6_EL2 S3_4_C12_C12_6
#define ICH_LR7_EL2 S3_4_C12_C12_7
#define ICH_LR8_EL2 S3_4_C12_C13_0
#define ICH_LR9_EL2 S3_4_C12_C13_1
#define ICH_LR10_EL2 S3_4_C12_C13_2
#define ICH_LR11_EL2 S3_4_C12_C13_3
#define ICH_LR12_EL2 S3_4_C12_C13_4
#define ICH_LR13_EL2 S3_4_C12_C13_5
#define ICH_LR14_EL2 S3_4_C12_C13_6
#define ICH_LR15_EL2 S3_4_C12_C13_7
#endif /* not __clang__ */
#endif /* GICV3_ALIASES */

65
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicc.h
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@@ -2,13 +2,18 @@
* GICv3_gicc.h - prototypes and inline functions for GICC system register operations
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your
* possession of a valid DS-5 end user licence agreement and your compliance
* with all applicable terms and conditions of such licence agreement.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef GICV3_gicc_h
#define GICV3_gicc_h
#include "GICv3_aliases.h"
#define stringify_no_expansion(x) #x
#define stringify(x) stringify_no_expansion(x)
/**********************************************************************/
typedef enum
@@ -21,42 +26,42 @@ typedef enum
static inline void setICC_SRE_EL1(ICC_SREBits_t mode)
{
asm("msr ICC_SRE_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
asm("msr "stringify(ICC_SRE_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
}
static inline uint64_t getICC_SRE_EL1(void)
{
uint64_t retc;
asm("mrs %0, ICC_SRE_EL1\n" : "=r" (retc));
asm("mrs %0, "stringify(ICC_SRE_EL1)"\n" : "=r" (retc));
return retc;
}
static inline void setICC_SRE_EL2(ICC_SREBits_t mode)
{
asm("msr ICC_SRE_EL2, %0\n; isb" :: "r" ((uint64_t)mode));
asm("msr "stringify(ICC_SRE_EL2)", %0\n; isb" :: "r" ((uint64_t)mode));
}
static inline uint64_t getICC_SRE_EL2(void)
{
uint64_t retc;
asm("mrs %0, ICC_SRE_EL2\n" : "=r" (retc));
asm("mrs %0, "stringify(ICC_SRE_EL2)"\n" : "=r" (retc));
return retc;
}
static inline void setICC_SRE_EL3(ICC_SREBits_t mode)
{
asm("msr ICC_SRE_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
asm("msr "stringify(ICC_SRE_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
}
static inline uint64_t getICC_SRE_EL3(void)
{
uint64_t retc;
asm("mrs %0, ICC_SRE_EL3\n" : "=r" (retc));
asm("mrs %0, "stringify(ICC_SRE_EL3)"\n" : "=r" (retc));
return retc;
}
@@ -72,17 +77,17 @@ typedef enum
static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode)
{
asm("msr ICC_IGRPEN0_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
asm("msr "stringify(ICC_IGRPEN0_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
}
static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode)
{
asm("msr ICC_IGRPEN1_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
asm("msr "stringify(ICC_IGRPEN1_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
}
static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode)
{
asm("msr ICC_IGRPEN1_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
asm("msr "stringify(ICC_IGRPEN1_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
}
/**********************************************************************/
@@ -102,28 +107,28 @@ typedef enum
static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode)
{
asm("msr ICC_CTLR_EL1, %0\n; isb" :: "r" ((uint64_t)mode));
asm("msr "stringify(ICC_CTLR_EL1)", %0\n; isb" :: "r" ((uint64_t)mode));
}
static inline uint64_t getICC_CTLR_EL1(void)
{
uint64_t retc;
asm("mrs %0, ICC_CTLR_EL1\n" : "=r" (retc));
asm("mrs %0, "stringify(ICC_CTLR_EL1)"\n" : "=r" (retc));
return retc;
}
static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode)
{
asm("msr ICC_CTLR_EL3, %0\n; isb" :: "r" ((uint64_t)mode));
asm("msr "stringify(ICC_CTLR_EL3)", %0\n; isb" :: "r" ((uint64_t)mode));
}
static inline uint64_t getICC_CTLR_EL3(void)
{
uint64_t retc;
asm("mrs %0, ICC_CTLR_EL3\n" : "=r" (retc));
asm("mrs %0, "stringify(ICC_CTLR_EL3)"\n" : "=r" (retc));
return retc;
}
@@ -134,7 +139,7 @@ static inline uint64_t getICC_IAR0(void)
{
uint64_t retc;
asm("mrs %0, ICC_IAR0_EL1\n" : "=r" (retc));
asm("mrs %0, "stringify(ICC_IAR0_EL1)"\n" : "=r" (retc));
return retc;
}
@@ -143,46 +148,46 @@ static inline uint64_t getICC_IAR1(void)
{
uint64_t retc;
asm("mrs %0, ICC_IAR1_EL1\n" : "=r" (retc));
asm("mrs %0, "stringify(ICC_IAR1_EL1)"\n" : "=r" (retc));
return retc;
}
static inline void setICC_EOIR0(uint32_t interrupt)
{
asm("msr ICC_EOIR0_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
asm("msr "stringify(ICC_EOIR0_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
}
static inline void setICC_EOIR1(uint32_t interrupt)
{
asm("msr ICC_EOIR1_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
asm("msr "stringify(ICC_EOIR1_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
}
static inline void setICC_DIR(uint32_t interrupt)
{
asm("msr ICC_DIR_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt));
asm("msr "stringify(ICC_DIR_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt));
}
static inline void setICC_PMR(uint32_t priority)
{
asm("msr ICC_PMR_EL1, %0\n; isb" :: "r" ((uint64_t)priority));
asm("msr "stringify(ICC_PMR_EL1)", %0\n; isb" :: "r" ((uint64_t)priority));
}
static inline void setICC_BPR0(uint32_t binarypoint)
{
asm("msr ICC_BPR0_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint));
asm("msr "stringify(ICC_BPR0_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint));
}
static inline void setICC_BPR1(uint32_t binarypoint)
{
asm("msr ICC_BPR1_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint));
asm("msr "stringify(ICC_BPR1_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint));
}
static inline uint64_t getICC_BPR0(void)
{
uint64_t retc;
asm("mrs %0, ICC_BPR0_EL1\n" : "=r" (retc));
asm("mrs %0, "stringify(ICC_BPR0_EL1)"\n" : "=r" (retc));
return retc;
}
@@ -191,7 +196,7 @@ static inline uint64_t getICC_BPR1(void)
{
uint64_t retc;
asm("mrs %0, ICC_BPR1_EL1\n" : "=r" (retc));
asm("mrs %0, "stringify(ICC_BPR1_EL1)"\n" : "=r" (retc));
return retc;
}
@@ -200,7 +205,7 @@ static inline uint64_t getICC_RPR(void)
{
uint64_t retc;
asm("mrs %0, ICC_RPR_EL1\n" : "=r" (retc));
asm("mrs %0, "stringify(ICC_RPR_EL1)"\n" : "=r" (retc));
return retc;
}
@@ -221,7 +226,7 @@ static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2,
((uint64_t)aff1 << 16) | irm | targetlist | \
((uint64_t)(intid & 0x0f) << 24));
asm("msr ICC_SGI0R_EL1, %0\n; isb" :: "r" (packedbits));
asm("msr "stringify(ICC_SGI0R_EL1)", %0\n; isb" :: "r" (packedbits));
}
static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2,
@@ -232,7 +237,7 @@ static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2,
((uint64_t)aff1 << 16) | irm | targetlist | \
((uint64_t)(intid & 0x0f) << 24));
asm("msr ICC_SGI1R_EL1, %0\n; isb" :: "r" (packedbits));
asm("msr "stringify(ICC_SGI1R_EL1)", %0\n; isb" :: "r" (packedbits));
}
static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2,
@@ -243,7 +248,7 @@ static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2,
((uint64_t)aff1 << 16) | irm | targetlist | \
((uint64_t)(intid & 0x0f) << 24));
asm("msr ICC_ASGI1R_EL1, %0\n; isb" :: "r" (packedbits));
asm("msr "stringify(ICC_ASGI1R_EL1)", %0\n; isb" :: "r" (packedbits));
}
#endif /* ndef GICV3_gicc_h */

6
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicd.c
View File

@@ -2,9 +2,9 @@
* GICv3_gicd.c - generic driver code for GICv3 distributor
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your
* possession of a valid DS-5 end user licence agreement and your compliance
* with all applicable terms and conditions of such licence agreement.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#include <stdint.h>

44
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicr.c
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@@ -1,10 +1,10 @@
/*
* GICv3_gicr.c - generic driver code for GICv3 redistributor
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your
* possession of a valid DS-5 end user licence agreement and your compliance
* with all applicable terms and conditions of such licence agreement.
* Copyright (c) 2014-2018 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#include "GICv3.h"
@@ -19,8 +19,14 @@ typedef struct
volatile uint32_t GICR_STATUSR; // +0x0010 - RW - Error Reporting Status Register, optional
volatile uint32_t GICR_WAKER; // +0x0014 - RW - Redistributor Wake Register
const volatile uint32_t padding1[2]; // +0x0018 - RESERVED
volatile uint32_t IMPDEF1 ; // +0x0020 - ?? - IMPLEMENTATION DEFINED
const volatile uint32_t padding2[7]; // +0x0024 - RESERVED
#ifndef USE_GIC600
volatile uint32_t IMPDEF1[8]; // +0x0020 - ?? - IMPLEMENTATION DEFINED
#else
volatile uint32_t GICR_FCTLR; // +0x0020 - RW - Function Control Register
volatile uint32_t GICR_PWRR; // +0x0024 - RW - Power Management Control Register
volatile uint32_t GICR_CLASS; // +0x0028 - RW - Class Register
const volatile uint32_t padding2[5]; // +0x002C - RESERVED
#endif
volatile uint64_t GICR_SETLPIR; // +0x0040 - WO - Set LPI Pending Register
volatile uint64_t GICR_CLRLPIR; // +0x0048 - WO - Clear LPI Pending Register
const volatile uint32_t padding3[8]; // +0x0050 - RESERVED
@@ -63,9 +69,9 @@ typedef struct
volatile uint8_t GICR_IPRIORITYR[32]; // +0x0400 - RW - Interrupt Priority Registers
const volatile uint32_t padding9[504]; // +0x0420 - RESERVED
volatile uint32_t GICR_ICnoFGR[2]; // +0x0C00 - RW - Interrupt Configuration Registers
const volatile uint32_t padding10[62]; // +0x0C08 - RESERVED
const volatile uint32_t padding10[62]; // +0x0C08 - RESERVED
volatile uint32_t GICR_IGRPMODR0; // +0x0D00 - RW - ????
const volatile uint32_t padding11[63]; // +0x0D04 - RESERVED
const volatile uint32_t padding11[63]; // +0x0D04 - RESERVED
volatile uint32_t GICR_NSACR; // +0x0E00 - RW - Non-Secure Access Control Register
} GICv3_redistributor_SGI;
@@ -79,14 +85,14 @@ typedef struct
{
union
{
GICv3_redistributor_RD RD_base;
uint8_t padding[64 * 1024];
GICv3_redistributor_RD RD_base;
uint8_t padding[64 * 1024];
} RDblock;
union
{
GICv3_redistributor_SGI SGI_base;
uint8_t padding[64 * 1024];
GICv3_redistributor_SGI SGI_base;
uint8_t padding[64 * 1024];
} SGIblock;
} GICv3_GICR;
@@ -126,6 +132,10 @@ static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr)
void WakeupGICR(uint32_t gicr)
{
GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr);
#ifdef USE_GIC600
//Power up Re-distributor for GIC-600
gicrRD->GICR_PWRR = 0x2;
#endif
/*
* step 1 - ensure GICR_WAKER.ProcessorSleep is off
@@ -136,7 +146,7 @@ void WakeupGICR(uint32_t gicr)
* step 2 - wait for children asleep to be cleared
*/
while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0)
continue;
continue;
/*
* OK, GICR is go
@@ -244,17 +254,17 @@ void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group)
* either set or clear the Group bit for the interrupt as appropriate
*/
if (group)
gicrSGI->GICR_IGROUPR0 |= 1 << id;
gicrSGI->GICR_IGROUPR0 |= 1 << id;
else
gicrSGI->GICR_IGROUPR0 &= ~(1 << id);
gicrSGI->GICR_IGROUPR0 &= ~(1 << id);
/*
* now deal with groupmod
*/
if (groupmod)
gicrSGI->GICR_IGRPMODR0 |= 1 << id;
gicrSGI->GICR_IGRPMODR0 |= 1 << id;
else
gicrSGI->GICR_IGRPMODR0 &= ~(1 << id);
gicrSGI->GICR_IGRPMODR0 &= ~(1 << id);
}
void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group)

6
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.S
View File

@@ -2,9 +2,9 @@
// Armv8-A AArch64 - Basic Mutex Example
//
// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your
// possession of a valid DS-5 end user licence agreement and your compliance
// with all applicable terms and conditions of such licence agreement.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

6
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/PPM_AEM.h
View File

@@ -2,9 +2,9 @@
// Private Peripheral Map for the v8 Architecture Envelope Model
//
// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your
// possession of a valid DS-5 end user licence agreement and your compliance
// with all applicable terms and conditions of such licence agreement.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//
#ifndef PPM_AEM_H

46
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c
View File

@@ -1,5 +1,5 @@
/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
byte pool, and block pool. */
#include "tx_api.h"
@@ -101,41 +101,41 @@ CHAR *pointer = TX_NULL;
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the main thread. */
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 1. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 1 and 2. These threads pass information through a ThreadX
/* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 2. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 3. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 4. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 5. */
@@ -143,23 +143,23 @@ CHAR *pointer = TX_NULL;
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 6. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 7. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the message queue. */
@@ -261,11 +261,11 @@ UINT status;
/* Retrieve a message from the queue. */
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
/* Check completion status and make sure the message is what we
/* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
@@ -324,7 +324,7 @@ ULONG actual_flags;
thread_5_counter++;
/* Wait for event flag 0. */
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
@@ -377,7 +377,7 @@ UINT status;
if (status != TX_SUCCESS)
break;
/* Release the mutex again. This will actually
/* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(&mutex_0);

90
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.launch
View File

@@ -6,17 +6,17 @@
<stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
<mapAttribute key="AverageDurationTracker">
<mapEntry key="*Fetching Data" value="34126331"/>
<mapEntry key="*Fetching Data Model" value="440446"/>
<mapEntry key="*Fetching Data Model" value="1439173"/>
<mapEntry key="*FunctionLoader" value="137168653"/>
<mapEntry key="*list global low level symbols" value="1646899"/>
<mapEntry key="*list global low level symbols" value="2707112"/>
<mapEntry key="*loading memory from target" value="2367919"/>
<mapEntry key="*loading values from target" value="10254159"/>
<mapEntry key="*loading values from target" value="8477514"/>
<mapEntry key="*trace" value="1527238"/>
<mapEntry key="*updating expressions" value="120397628"/>
<mapEntry key="*updating expressions" value="101886453"/>
<mapEntry key="*updating local_variables" value="836905"/>
<mapEntry key="*updating registers" value="97090462"/>
<mapEntry key="*updating variables" value="877039"/>
<mapEntry key="AddEventObserver" value="8093286"/>
<mapEntry key="AddEventObserver" value="6587743"/>
<mapEntry key="Evaluate" value="1689813"/>
<mapEntry key="ResumeToHere" value="20159012"/>
<mapEntry key="Retrieving globals list" value="21298708"/>
@@ -24,11 +24,11 @@
<mapEntry key="backtrace" value="21505977"/>
<mapEntry key="break" value="9764564"/>
<mapEntry key="checking tracepoints" value="372731"/>
<mapEntry key="compute execution mode" value="656960"/>
<mapEntry key="compute execution mode" value="557345"/>
<mapEntry key="console" value="11946310"/>
<mapEntry key="continue" value="30605812"/>
<mapEntry key="continue" value="12697403"/>
<mapEntry key="core" value="5451456"/>
<mapEntry key="directory" value="5756324"/>
<mapEntry key="directory" value="4737162"/>
<mapEntry key="disable" value="2444670"/>
<mapEntry key="disassemble" value="64135505"/>
<mapEntry key="enable" value="5445745"/>
@@ -36,38 +36,38 @@
<mapEntry key="evaluate address" value="1056014"/>
<mapEntry key="finish" value="20115248"/>
<mapEntry key="get byte order" value="633302"/>
<mapEntry key="get capabilities" value="487813"/>
<mapEntry key="get execution addresss" value="489635"/>
<mapEntry key="get source lines" value="643716"/>
<mapEntry key="get substitute paths" value="476043"/>
<mapEntry key="get capabilities" value="548556"/>
<mapEntry key="get execution addresss" value="438164"/>
<mapEntry key="get source lines" value="3151194"/>
<mapEntry key="get substitute paths" value="293110"/>
<mapEntry key="getValidEncodings" value="1202320"/>
<mapEntry key="initialize command help" value="73033741"/>
<mapEntry key="interrupt" value="17605741"/>
<mapEntry key="list breakpoint options" value="248517"/>
<mapEntry key="list breakpoints" value="592398"/>
<mapEntry key="list instruction sets" value="1120702"/>
<mapEntry key="list signals" value="652481"/>
<mapEntry key="initialize command help" value="68196070"/>
<mapEntry key="interrupt" value="11210435"/>
<mapEntry key="list breakpoint options" value="1264804"/>
<mapEntry key="list breakpoints" value="1473749"/>
<mapEntry key="list instruction sets" value="1512051"/>
<mapEntry key="list signals" value="1314040"/>
<mapEntry key="list source files" value="573423"/>
<mapEntry key="list watchpoint options" value="865975"/>
<mapEntry key="list watchpoints" value="469237"/>
<mapEntry key="loadfile" value="125129738"/>
<mapEntry key="list watchpoint options" value="4130737"/>
<mapEntry key="list watchpoints" value="739118"/>
<mapEntry key="loadfile" value="308178719"/>
<mapEntry key="next" value="24266800"/>
<mapEntry key="query supports threads" value="215433"/>
<mapEntry key="remove" value="3597385"/>
<mapEntry key="run script" value="28627145"/>
<mapEntry key="set CWD" value="2965984"/>
<mapEntry key="run script" value="37326822"/>
<mapEntry key="set CWD" value="4366642"/>
<mapEntry key="set breakpoint properties" value="10666013"/>
<mapEntry key="set debug-from" value="917651"/>
<mapEntry key="set substitute-path" value="8468055"/>
<mapEntry key="source use_model_semihosting.ds" value="5545625"/>
<mapEntry key="start" value="24235608"/>
<mapEntry key="set debug-from" value="1215725"/>
<mapEntry key="set substitute-path" value="23083827"/>
<mapEntry key="source use_model_semihosting.ds" value="7540462"/>
<mapEntry key="start" value="36728254"/>
<mapEntry key="step" value="26461127"/>
<mapEntry key="stepi" value="29574773"/>
<mapEntry key="synchronizing trace ranges" value="21582"/>
<mapEntry key="target reset" value="32992642"/>
<mapEntry key="toggleBreakpoint" value="7875634"/>
<mapEntry key="updateBreakpointLocation" value="1868000"/>
<mapEntry key="waitForTargetToStop" value="38251299"/>
<mapEntry key="waitForTargetToStop" value="47515299"/>
<mapEntry key="write expression" value="21220700"/>
</mapAttribute>
<listAttribute key="DEBUG_TAB."/>
@@ -89,37 +89,37 @@
<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.VALUE" value=""/>
<intAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.COUNT" value="1"/>
<listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="APPLICATION_ON_TARGET"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.VALUE" value=""/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="APPLICATION_ON_TARGET"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
<intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
<listAttribute key="FILES.DOWNLOAD_AND_DEBUG"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_DOWNLOAD_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
<intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
<listAttribute key="FILES.DOWNLOAD_DEBUG"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_DOWNLOAD_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
<intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
<intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
@@ -223,8 +223,8 @@
<stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
<stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#10;&lt;/breakpoints&gt;&#10;"/>
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.addresses">
<listEntry value="&lt;Next Instruction&gt;"/>
<listEntry value=""/>
<listEntry value="&lt;Next Instruction&gt;"/>
<listEntry value="$pc"/>
<listEntry value="0x8000986c"/>
<listEntry value="$pc"/>
@@ -245,10 +245,10 @@
<listEntry value="EL1N:thread_2_entry"/>
</listAttribute>
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.ranges">
<listEntry value="100"/>
<listEntry value=""/>
<listEntry value="100"/>
<listEntry value="100"/>
<listEntry value="100"/>
<listEntry value="1000"/>
<listEntry value="1000"/>
<listEntry value="100"/>
@@ -313,15 +313,16 @@
<listAttribute key="com.arm.debugger.views.common.AddressTracker.debugger.view.DisassemblyView.ranges">
<listEntry value="100"/>
</listAttribute>
<stringAttribute key="config_db_activity_name" value="Debug Cortex-A35x4 SMP"/>
<stringAttribute key="config_db_connection_keys" value="dtsl_config dtsl_tracecapture_option dtsl_config_script model_params config_file setup TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
<stringAttribute key="config_db_activity_name" value="Cortex-A35x4 SMP"/>
<stringAttribute key="config_db_connection_keys" value="dtsl_config dtsl_tracecapture_option connect_existing_model dtsl_config_script model_params model_iris config_file model_connection_address setup TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
<stringAttribute key="config_db_connection_type" value="Bare Metal Debug"/>
<stringAttribute key="config_db_platform_name" value="Arm FVP - Base_A35x4"/>
<stringAttribute key="config_db_project_type" value="Bare Metal Debug"/>
<stringAttribute key="config_db_project_type_id" value="BARE_METAL"/>
<stringAttribute key="config_db_taxonomy_id" value="/platform/armfvp/base_a35x4"/>
<stringAttribute key="config_file" value="CDB://cadi_config.xml"/>
<stringAttribute key="config_file" value="CDB://iris_config.xml"/>
<booleanAttribute key="connectOnly" value="false"/>
<stringAttribute key="connect_existing_model" value="false"/>
<stringAttribute key="debugger.view.DataView.os:DataView" value="rO0ABXNyACtjb20uYXJtLmRlYnVnLnZpZXdzLmRhdGEuRGF0YVZpZXdQcm9wZXJ0aWVzAAAAAAAAAAECAAB4cgAlY29tLmFybS5kZWJ1Zy52aWV3cy5kYXRhLlByb3BlcnR5VHJlZQAAAAAAAAABAwABTAAFbURhdGF0ABNMamF2YS91dGlsL0hhc2hNYXA7eHB3BAAAAAJ0ABJkYXRhYmFzZVByb3BlcnRpZXNzcQB+AAF3BAAAAAF0AAd0aHJlYWR4c3IAK2NvbS5hcm0uZGVidWcudmlld3MuZGF0YS5EYXRhYmFzZVByb3BlcnRpZXMAAAAAAAAAAQIAAHhxAH4AAXcEAAAAAnQAAmlkcQB+AAZ0AAxjdXJyZW50VGFibGV0AAd0aHJlYWRzeHh0AA9jdXJyZW50RGF0YWJhc2V0AAd0aHJlYWR4eA=="/>
<listAttribute key="debugger.view.DisassemblyView:current">
<listEntry value=""/>
@@ -383,8 +384,10 @@
<stringAttribute key="dtsl_config" value="DtslScript"/>
<stringAttribute key="dtsl_config_script" value="CDB://dtsl_config_script.py"/>
<stringAttribute key="dtsl_options_file" value="default"/>
<stringAttribute key="dtsl_tracecapture_option" value="options.traceBuffer.traceCaptureDevice"/>
<stringAttribute key="dtsl_tracecapture_option" value="options.trace.traceCapture"/>
<booleanAttribute key="linuxOS" value="false"/>
<stringAttribute key="model_connection_address" value=""/>
<stringAttribute key="model_iris" value="1"/>
<stringAttribute key="model_params" value="-C bp.secure_memory=false -C cache_state_modelled=0"/>
<stringAttribute key="os_extension_id" value="com.arm.debug.os.threadx"/>
<booleanAttribute key="runAfterConnect" value="false"/>
@@ -392,12 +395,13 @@
<mapAttribute key="scripts_view_script_links">
<mapEntry key="B:\support\broadcom\a53smp_el1_clean_mar25\sample_threadx\use_model_semihosting.ds" value=""/>
<mapEntry key="B:\support\broadcom\tx58cortexa53arm\release\threadx\sample_threadx\use_model_semihosting.ds" value=""/>
<mapEntry key="C:\Users\andrejm\work\git\AzureRTOS\threadx_other\ports_smp\cortex_a35_smp\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/>
<mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_smp\cortex_a35_smp\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/>
<mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x_smp\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/>
</mapAttribute>
<listAttribute key="setup">
<listEntry value="CDB://Scripts/rtsm_launcher.py"/>
<listEntry value="FVP_Base_Cortex-A35x4"/>
<listEntry value="&quot;FVP_Base_Cortex-A35x4&quot;"/>
</listAttribute>
<stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/>
<stringAttribute key="substitutePath" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;tuplelist&gt;&#10;&#9;&lt;tuple&gt;&#10;&#9;&#9;&lt;ta&gt;C:/release/threadx/sample_threadx&lt;/ta&gt;&#10;&#9;&#9;&lt;tb&gt;C:\release\threadx\sample_threadx\&lt;/tb&gt;&#10;&#9;&lt;/tuple&gt;&#10;&#9;&lt;tuple&gt;&#10;&#9;&#9;&lt;ta&gt;C:/release/threadx/tx&lt;/ta&gt;&#10;&#9;&#9;&lt;tb&gt;C:\release\threadx\sample_threadx\&lt;/tb&gt;&#10;&#9;&lt;/tuple&gt;&#10;&lt;/tuplelist&gt;&#10;"/>

6
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sp804_timer.c
View File

@@ -2,9 +2,9 @@
// SP804 Dual Timer
//
// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your
// possession of a valid DS-5 end user licence agreement and your compliance
// with all applicable terms and conditions of such licence agreement.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------
#include "sp804_timer.h"

6
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sp804_timer.h
View File

@@ -3,9 +3,9 @@
// Header Filer
//
// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your
// possession of a valid DS-5 end user licence agreement and your compliance
// with all applicable terms and conditions of such licence agreement.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------
#ifndef _SP804_TIMER_

14
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/startup.S
View File

@@ -6,14 +6,14 @@
// Exits in EL1 AArch64
//
// Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your
// possession of a valid DS-5 end user licence agreement and your compliance
// with all applicable terms and conditions of such licence agreement.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------
#include "v8_mmu.h"
#include "v8_system.h"
#include "GICv3_aliases.h"
.section StartUp, "ax"
.balign 4
@@ -328,7 +328,7 @@ el1_entry_aarch64:
//
// Cortex-A processors automatically invalidate their caches on reset
// (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
// It is therefore not necessary for software to invalidate the caches
// It is therefore not necessary for software to invalidate the caches
// on startup, however, this is done here in case of a warm reset.
bl InvalidateUDCaches
tlbi VMALLE1
@@ -761,7 +761,7 @@ wait_for_mmu_ready:
msr SCTLR_EL1, x1
isb
/* EL: Secondary core entrance. */
/* EL: Secondary core entrance. */
B _tx_thread_smp_initialize_wait
loop_wfi:
@@ -800,4 +800,4 @@ __user_setup_stackheap:
ADRP X0, Image$$ARM_LIB_HEAP$$ZI$$Base
ADRP X2, Image$$ARM_LIB_HEAP$$ZI$$Limit
RET

10
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_aarch64.S
View File

@@ -1,10 +1,10 @@
// ------------------------------------------------------------
// Armv8-A AArch64 - Common helper functions
//
// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your
// possession of a valid DS-5 end user licence agreement and your compliance
// with all applicable terms and conditions of such licence agreement.
// Copyright (c) 2012-2018 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------
#include "v8_system.h"
@@ -144,6 +144,8 @@ GetCPUID:
mrs x0, MIDR_EL1
ubfx x0, x0, #4, #12 // extract PartNum
cmp x0, #0xD0B // Cortex-A76
b.eq DynamIQ
cmp x0, #0xD0A // Cortex-A75
b.eq DynamIQ
cmp x0, #0xD05 // Cortex-A55

6
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_mmu.h
View File

@@ -2,9 +2,9 @@
// Defines for v8 Memory Model
//
// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your
// possession of a valid DS-5 end user licence agreement and your compliance
// with all applicable terms and conditions of such licence agreement.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//
#ifndef V8_MMU_H

6
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_system.h
View File

@@ -2,9 +2,9 @@
// Defines for v8 System Registers
//
// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your
// possession of a valid DS-5 end user licence agreement and your compliance
// with all applicable terms and conditions of such licence agreement.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//
#ifndef V8_SYSTEM_H

6
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_utils.S
View File

@@ -2,9 +2,9 @@
// Simple utility routines for baremetal v8 code
//
// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your
// possession of a valid DS-5 end user licence agreement and your compliance
// with all applicable terms and conditions of such licence agreement.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//
#include "v8_system.h"

6
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/vectors.S
View File

@@ -2,9 +2,9 @@
// Armv8-A Vector tables
//
// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your
// possession of a valid DS-5 end user licence agreement and your compliance
// with all applicable terms and conditions of such licence agreement.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------

72
ports_smp/cortex_a35_smp/ac6/example_build/tx/.cproject
View File

@@ -118,78 +118,6 @@
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
<cconfiguration id="com.arm.eclipse.build.config.v6.lib.release.base.597173224">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.release.base.597173224" moduleId="org.eclipse.cdt.core.settings" name="Release">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.arm.eclipse.builder.armcc.error" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="a" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.staticLib" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.staticLib,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="clean" description="" id="com.arm.eclipse.build.config.v6.lib.release.base.597173224" name="Release" parent="com.arm.eclipse.build.config.v6.lib.release.base">
<folderInfo id="com.arm.eclipse.build.config.v6.lib.release.base.597173224." name="/" resourcePath="">
<toolChain id="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6.1176479246" name="Arm Compiler 6" superClass="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6">
<targetPlatform id="com.arm.toolchain.v6.lib.release.base.var.arm_compiler_6-6.1176479246.1337532818" name=""/>
<builder autoBuildTarget="all" buildPath="${workspace_loc:/tx}/Release" cleanBuildTarget="clean" enableAutoBuild="false" enableCleanBuild="true" enabledIncrementalBuild="true" id="com.arm.toolchain.v6.builder.1329350735" incrementalBuildTarget="all" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="false" superClass="com.arm.toolchain.v6.builder"/>
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.599090274" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6">
<option id="com.arm.tool.c.compiler.v6.base.option.optlevel.1379419239" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/>
<inputType id="com.arm.tool.c.compiler.v6.base.input.1827794426" superClass="com.arm.tool.c.compiler.v6.base.input"/>
</tool>
<tool id="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6.681809063" name="Arm C++ Compiler 6" superClass="com.arm.tool.cpp.compiler.v6.base.var.arm_compiler_6-6">
<option id="com.arm.tool.c.compiler.v6.base.option.optlevel.1575069010" name="Optimization level" superClass="com.arm.tool.c.compiler.v6.base.option.optlevel" useByScannerDiscovery="true" value="com.arm.tool.c.compiler.v6.base.option.optlevel.high" valueType="enumerated"/>
</tool>
<tool id="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6.541732194" name="Arm Assembler 6" superClass="com.arm.tool.assembler.v6.base.var.arm_compiler_6-6">
<inputType id="com.arm.tool.assembler.v6.base.input.1308655066" superClass="com.arm.tool.assembler.v6.base.input"/>
</tool>
<tool id="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6.1174783096" name="Arm Linker 6" superClass="com.arm.tool.c.linker.v6.base.var.arm_compiler_6-6"/>
<tool id="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6.121864210" name="Arm Librarian 6" superClass="com.arm.tool.librarian.v6.base.var.arm_compiler_6-6"/>
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding="src_generic/tx_misra.c|src_generic/tx_thread_timeout.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>

102
ports_smp/cortex_a35_smp/ac6/inc/tx_port.h
View File

@@ -12,7 +12,7 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** */
/** ThreadX Component */
/** */
/** Port Specific */
@@ -21,36 +21,39 @@
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-A35-SMP/AC6 */
/* 6.1.6 */
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */
/* macro definition, */
/* resulting in version 6.1.6 */
/* 10-15-2021 William E. Lamie Modified comment(s), added */
/* symbol ULONG64_DEFINED, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
@@ -81,12 +84,12 @@
/* Define ThreadX SMP initialization macro. */
#define TX_PORT_SPECIFIC_PRE_INITIALIZATION
#define TX_PORT_SPECIFIC_PRE_INITIALIZATION
/* Define ThreadX SMP pre-scheduler initialization. */
#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION
#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION
/* Enable the inter-core interrupt logic. */
@@ -127,7 +130,7 @@
#ifdef TX_INCLUDE_USER_DEFINE_FILE
/* Yes, include the user defines in tx_user.h. The defines in this file may
/* Yes, include the user defines in tx_user.h. The defines in this file may
alternately be defined on the command line. */
#include "tx_user.h"
@@ -140,7 +143,7 @@
#include <string.h>
/* Define ThreadX basic types for this port. */
/* Define ThreadX basic types for this port. */
#define VOID void
typedef char CHAR;
@@ -152,7 +155,7 @@ typedef unsigned int ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Override the alignment type to use 64-bit alignment and storage for pointers. */
@@ -188,19 +191,19 @@ typedef unsigned long long ALIGN_TYPE;
#define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */
#endif
#ifndef TX_TIMER_THREAD_PRIORITY
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#ifndef TX_TIMER_THREAD_PRIORITY
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
/* Define various constants for the ThreadX ARM port. */
/* Define various constants for the ThreadX ARM port. */
#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */
#define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
@@ -258,7 +261,7 @@ ULONG _tx_misra_time_stamp_get(VOID);
#endif
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
define is negated, thereby forcing the stack fill which is necessary for the stack checking
@@ -272,11 +275,11 @@ ULONG _tx_misra_time_stamp_get(VOID);
/* Define the TX_THREAD control block extensions for this port. The main reason
for the multiple macros is so that backward compatibility can be maintained with
for the multiple macros is so that backward compatibility can be maintained with
existing ThreadX kernel awareness modules. */
#define TX_THREAD_EXTENSION_0
#define TX_THREAD_EXTENSION_1
#define TX_THREAD_EXTENSION_0
#define TX_THREAD_EXTENSION_1
#define TX_THREAD_EXTENSION_2 ULONG tx_thread_fp_enable;
#define TX_THREAD_EXTENSION_3 VOID *tx_thread_extension_ptr;
@@ -292,11 +295,11 @@ ULONG _tx_misra_time_stamp_get(VOID);
#define TX_TIMER_EXTENSION
/* Define the user extension field of the thread control block. Nothing
/* Define the user extension field of the thread control block. Nothing
additional is needed for this port so it is defined as white space. */
#ifndef TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#endif
@@ -304,8 +307,8 @@ ULONG _tx_misra_time_stamp_get(VOID);
tx_thread_shell_entry, and tx_thread_terminate. */
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
@@ -332,8 +335,8 @@ ULONG _tx_misra_time_stamp_get(VOID);
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
/* Determine if the ARM architecture has the CLZ instruction. This is available on
architectures v5 and above. If available, redefine the macro for calculating the
/* Determine if the ARM architecture has the CLZ instruction. This is available on
architectures v5 and above. If available, redefine the macro for calculating the
lowest bit set. */
#ifndef TX_DISABLE_INLINE
@@ -345,7 +348,7 @@ ULONG _tx_misra_time_stamp_get(VOID);
/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout
can figure out what thread timeout to process. */
#define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_extension_ptr;
@@ -375,14 +378,14 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT
ULONG tx_thread_smp_protect_count;
ULONG tx_thread_smp_protect_pad_0;
ULONG tx_thread_smp_protect_pad_1;
ULONG tx_thread_smp_protect_pad_2;
ULONG tx_thread_smp_protect_pad_3;
ULONG tx_thread_smp_protect_pad_2;
ULONG tx_thread_smp_protect_pad_3;
} TX_THREAD_SMP_PROTECT;
/* Define ThreadX interrupt lockout and restore macros for protection on
access of critical kernel information. The restore interrupt macro must
restore the interrupt posture of the running thread prior to the value
/* Define ThreadX interrupt lockout and restore macros for protection on
access of critical kernel information. The restore interrupt macro must
restore the interrupt posture of the running thread prior to the value
present prior to the disable macro. In most cases, the save area macro
is used to define a local function save area for the disable and restore
macros. */
@@ -420,16 +423,11 @@ VOID tx_thread_fp_disable(VOID);
/* Define the version ID of ThreadX. This may be utilized by the application. */
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35-SMP/AC6 Version 6.1.6 *";
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35-SMP/AC6 Version 6.1.9 *";
#else
extern CHAR _tx_version_id[];
#endif
#endif

90
ports_smp/cortex_a35_smp/ac6/src/tx_initialize_low_level.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Initialize */
/** */
@@ -21,63 +21,53 @@
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_initialize.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for any low-level processor */
/* initialization, including setting up interrupt vectors, setting */
/* up a periodic timer interrupt source, saving the system stack */
/* pointer for use in ISR processing later, and finding the first */
/* available RAM memory address for tx_application_define. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This function is responsible for any low-level processor */
/* initialization, including setting up interrupt vectors, setting */
/* up a periodic timer interrupt source, saving the system stack */
/* pointer for use in ISR processing later, and finding the first */
/* available RAM memory address for tx_application_define. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* VOID _tx_initialize_low_level(VOID)
{ */
// VOID _tx_initialize_low_level(VOID)
// {
.global _tx_initialize_low_level
.type _tx_initialize_low_level, @function
_tx_initialize_low_level:
@@ -86,7 +76,7 @@ _tx_initialize_low_level:
/* Save the system stack pointer. */
/* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */
// _tx_thread_system_stack_ptr = (VOID_PTR) (sp);
LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr
MOV x1, sp // Pickup SP
@@ -95,7 +85,7 @@ _tx_initialize_low_level:
STR x1, [x0] // Store system stack
/* Save the first available memory address. */
/* _tx_initialize_unused_memory = (VOID_PTR) Image$$HEAP$$ZI$$Limit; */
// _tx_initialize_unused_memory = (VOID_PTR) Image$$HEAP$$ZI$$Limit;
LDR x0, =_tx_initialize_unused_memory // Pickup address of unused memory ptr
LDR x1, =heap_limit // Pickup unused memory address - A free
@@ -106,7 +96,7 @@ _tx_initialize_low_level:
/* Done, return to caller. */
RET // Return to caller
/* } */
// }
.align 3
heap_limit:

163
ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_restore.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -21,64 +21,56 @@
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function restores the interrupt context if it is processing a */
/* nested interrupt. If not, it returns to the interrupt thread if no */
/* preemption is necessary. Otherwise, if preemption is necessary or */
/* if no thread was running, the function returns to the scheduler. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling routine */
/* */
/* CALLED BY */
/* */
/* ISRs Interrupt Service Routines */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This function restores the interrupt context if it is processing a */
/* nested interrupt. If not, it returns to the interrupt thread if no */
/* preemption is necessary. Otherwise, if preemption is necessary or */
/* if no thread was running, the function returns to the scheduler. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling routine */
/* */
/* CALLED BY */
/* */
/* ISRs Interrupt Service Routines */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* VOID _tx_thread_context_restore(VOID)
{ */
// VOID _tx_thread_context_restore(VOID)
// {
.global _tx_thread_context_restore
.type _tx_thread_context_restore, @function
_tx_thread_context_restore:
@@ -97,28 +89,35 @@ _tx_thread_context_restore:
/* Pickup the CPU ID. */
MRS x8, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x8, #16, #8 // Isolate cluster ID
#endif
UBFX x8, x8, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x8, #8, #8 // Isolate cluster ID
#endif
UBFX x8, x8, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x8, x8, x2, LSL #2 // Calculate CPU ID
#endif
/* Determine if interrupts are nested. */
/* if (--_tx_thread_system_state)
{ */
// if (--_tx_thread_system_state)
// {
LDR x3, =_tx_thread_system_state // Pickup address of system state var
LDR w2, [x3, x8, LSL #2] // Pickup system state
SUB w2, w2, #1 // Decrement the counter
STR w2, [x3, x8, LSL #2] // Store the counter
STR w2, [x3, x8, LSL #2] // Store the counter
CMP w2, #0 // Was this the first interrupt?
BEQ __tx_thread_not_nested_restore // If so, not a nested restore
/* Interrupts are nested. */
/* Just recover the saved registers and return to the point of
/* Just recover the saved registers and return to the point of
interrupt. */
LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL
@@ -147,13 +146,13 @@ _tx_thread_context_restore:
LDP x29, x30, [sp], #16 // Recover x29, x30
ERET // Return to point of interrupt
/* } */
// }
__tx_thread_not_nested_restore:
/* Determine if a thread was interrupted and no preemption is required. */
/* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
|| (_tx_thread_preempt_disable))
{ */
// else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
// || (_tx_thread_preempt_disable))
// {
LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr
LDR x0, [x1, x8, LSL #3] // Pickup actual current thread pointer
@@ -162,7 +161,7 @@ __tx_thread_not_nested_restore:
LDR x3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr
LDR x2, [x3, x8, LSL #3] // Pickup actual execute thread pointer
CMP x0, x2 // Is the same thread highest priority?
BEQ __tx_thread_no_preempt_restore // Same thread in the execute list,
BEQ __tx_thread_no_preempt_restore // Same thread in the execute list,
// no preemption needs to happen
LDR x3, =_tx_thread_smp_protection // Build address to protection structure
LDR w3, [x3, #4] // Pickup the owning core
@@ -179,7 +178,7 @@ __tx_thread_no_preempt_restore:
/* Restore interrupted thread or ISR. */
/* Pickup the saved stack pointer. */
/* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */
// sp = _tx_thread_current_ptr -> tx_thread_stack_ptr;
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
@@ -212,14 +211,14 @@ __tx_thread_no_preempt_restore:
LDP x29, x30, [sp], #16 // Recover x29, x30
ERET // Return to point of interrupt
/* }
else
{ */
// }
// else
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
/* if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
{ */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
@@ -227,8 +226,8 @@ __tx_thread_preempt_restore:
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
/* if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
{ */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
@@ -236,14 +235,14 @@ __tx_thread_preempt_restore:
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
/* _tx_thread_smp_protect_wait_list_remove(this_core); */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
/* }
else
{ */
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
@@ -251,7 +250,7 @@ __tx_thread_preempt_restore:
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
/* _tx_thread_smp_protect_wait_counts[core]--; */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
@@ -261,7 +260,7 @@ _this_core_has_lock:
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF; */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
@@ -269,7 +268,7 @@ _this_core_has_lock:
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0; */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
@@ -281,8 +280,8 @@ _this_core_has_lock:
SEV // Send event to other CPUs
#endif
/* }
} */
// }
// }
_nobody_waiting_for_lock:
@@ -331,27 +330,27 @@ _skip_fp_save:
/* Save the remaining time-slice and disable it. */
/* if (_tx_timer_time_slice)
{ */
// if (_tx_timer_time_slice)
// {
LDR x3, =_tx_timer_time_slice // Pickup time-slice variable address
LDR w2, [x3, x8, LSL #2] // Pickup time-slice
CMP w2, #0 // Is it active?
BEQ __tx_thread_dont_save_ts // No, don't save it
/* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
_tx_timer_time_slice = 0; */
// _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
// _tx_timer_time_slice = 0;
STR w2, [x0, #36] // Save thread's time-slice
MOV w2, #0 // Clear value
STR w2, [x3, x8, LSL #2] // Disable global time-slice flag
/* } */
// }
__tx_thread_dont_save_ts:
/* Clear the current task pointer. */
/* _tx_thread_current_ptr = TX_NULL; */
// _tx_thread_current_ptr = TX_NULL;
MOV x2, #0 // NULL value
STR x2, [x1, x8, LSL #3] // Clear current thread pointer
@@ -359,13 +358,13 @@ __tx_thread_dont_save_ts:
/* Set bit indicating this thread is ready for execution. */
MOV x2, #1 // Build ready flag
STR w2, [x0, #260] // Set thread's ready flag
DMB ISH // Ensure that accesses to shared resource have completed
STR w2, [x0, #260] // Set thread's ready flag
/* Return to the scheduler. */
/* _tx_thread_schedule(); */
// _tx_thread_schedule();
/* } */
// }
__tx_thread_idle_system_restore:
@@ -388,6 +387,4 @@ __tx_thread_idle_system_restore:
#endif
#endif
ERET // Return to scheduler
/* } */
// }

129
ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_save.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -21,70 +21,63 @@
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function saves the context of an executing thread in the */
/* beginning of interrupt processing. The function also ensures that */
/* the system stack is used upon return to the calling ISR. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ISRs */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This function saves the context of an executing thread in the */
/* beginning of interrupt processing. The function also ensures that */
/* the system stack is used upon return to the calling ISR. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ISRs */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* VOID _tx_thread_context_save(VOID)
{ */
// VOID _tx_thread_context_save(VOID)
// {
.global _tx_thread_context_save
.type _tx_thread_context_save, @function
_tx_thread_context_save:
/* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked
out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL,
out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL,
and all other registers are intact. */
/* Check for a nested interrupt condition. */
/* if (_tx_thread_system_state++)
{ */
// if (_tx_thread_system_state++)
// {
STP x0, x1, [sp, #-16]! // Save x0, x1
STP x2, x3, [sp, #-16]! // Save x2, x3
@@ -92,10 +85,17 @@ _tx_thread_context_save:
/* Pickup the CPU ID. */
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x2, LSL #2 // Calculate CPU ID
#endif
@@ -149,18 +149,18 @@ _tx_thread_context_save:
RET // Return to ISR
__tx_thread_not_nested_save:
/* } */
// }
/* Otherwise, not nested, check to see if a thread was running. */
/* else if (_tx_thread_current_ptr)
{ */
// else if (_tx_thread_current_ptr)
// {
ADD w2, w2, #1 // Increment the interrupt counter
STR w2, [x3, x1, LSL #2] // Store it back in the variable
LDR x2, =_tx_thread_current_ptr // Pickup address of current thread ptr
LDR x0, [x2, x1, LSL #3] // Pickup current thread pointer
CMP x0, #0 // Is it NULL?
BEQ __tx_thread_idle_system_save // If so, interrupt occurred in
BEQ __tx_thread_idle_system_save // If so, interrupt occurred in
// scheduling loop - nothing needs saving!
/* Save minimal context of interrupted thread. */
@@ -188,20 +188,27 @@ __tx_thread_not_nested_save:
STP x4, x5, [sp, #-16]! // Save SPSR, ELR
/* Save the current stack pointer in the thread's control block. */
/* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */
// _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
MOV x4, sp //
STR x4, [x0, #8] // Save thread stack pointer
/* Switch to the system stack. */
/* sp = _tx_thread_system_stack_ptr; */
// sp = _tx_thread_system_stack_ptr;
LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x2, LSL #2 // Calculate CPU ID
#endif
@@ -218,17 +225,17 @@ __tx_thread_not_nested_save:
LDP x29, x30, [sp], #16 // Recover x29, x30
#endif
RET // Return to caller
RET // Return to caller
/* }
else
{ */
// }
// else
// {
__tx_thread_idle_system_save:
/* Interrupt occurred in the scheduling loop. */
/* Not much to do here, just adjust the stack pointer, and return to IRQ
/* Not much to do here, just adjust the stack pointer, and return to IRQ
processing. */
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@@ -241,9 +248,7 @@ __tx_thread_idle_system_save:
#endif
ADD sp, sp, #48 // Recover saved registers
RET // Continue IRQ processing
/* }
} */
RET // Continue IRQ processing
// }
// }

66
ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_disable.c
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -29,41 +29,43 @@
#include "tx_thread.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fp_disable Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fp_disable Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function disables the FP for the currently executing thread. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This function disables the FP for the currently executing thread. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
VOID _tx_thread_fp_disable(VOID)
@@ -82,14 +84,14 @@ ULONG system_state;
/* Make sure it is not NULL. */
if (thread_ptr != TX_NULL)
{
/* Thread is running... make sure the call is from the thread context. */
if (system_state == 0)
{
/* Yes, now set the FP enable flag to false in the TX_THREAD structure. */
thread_ptr -> tx_thread_fp_enable = TX_FALSE;
}
}
}
}

67
ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_enable.c
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -28,42 +28,43 @@
#include "tx_api.h"
#include "tx_thread.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fp_enable Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fp_enable Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function enabled the FP for the currently executing thread. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This function enabled the FP for the currently executing thread. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
VOID _tx_thread_fp_enable(VOID)
@@ -82,14 +83,14 @@ ULONG system_state;
/* Make sure it is not NULL. */
if (thread_ptr != TX_NULL)
{
/* Thread is running... make sure the call is from the thread context. */
if (system_state == 0)
{
/* Yes, now setup the FP enable flag in the TX_THREAD structure. */
thread_ptr -> tx_thread_fp_enable = TX_TRUE;
}
}
}
}

77
ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_control.S
View File

@@ -12,66 +12,59 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
/*#define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for changing the interrupt lockout */
/* posture of the system. */
/* */
/* INPUT */
/* */
/* new_posture New interrupt lockout posture */
/* */
/* OUTPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This function is responsible for changing the interrupt lockout */
/* posture of the system. */
/* */
/* INPUT */
/* */
/* new_posture New interrupt lockout posture */
/* */
/* OUTPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* UINT _tx_thread_interrupt_control(UINT new_posture)
{ */
// UINT _tx_thread_interrupt_control(UINT new_posture)
// {
.global _tx_thread_interrupt_control
.type _tx_thread_interrupt_control, @function
_tx_thread_interrupt_control:
@@ -85,5 +78,5 @@ _tx_thread_interrupt_control:
MSR DAIF, x0 // Set new interrupt posture
MOV x0, x1 // Setup return value
RET // Return to caller
/* } */
// }

76
ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_disable.S
View File

@@ -12,65 +12,58 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for disabling interrupts */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This function is responsible for disabling interrupts */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* UINT _tx_thread_interrupt_disable(void)
{ */
// UINT _tx_thread_interrupt_disable(void)
// {
.global _tx_thread_interrupt_disable
.type _tx_thread_interrupt_disable, @function
_tx_thread_interrupt_disable:
@@ -83,5 +76,4 @@ _tx_thread_interrupt_disable:
MSR DAIFSet, 0x3 // Lockout interrupts
RET // Return to caller
/* } */
// }

74
ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_restore.S
View File

@@ -12,66 +12,59 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* */
/* This function is responsible for restoring interrupts to the state */
/* returned by a previous _tx_thread_interrupt_disable call. */
/* */
/* INPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* INPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* UINT _tx_thread_interrupt_restore(UINT old_posture)
{ */
// UINT _tx_thread_interrupt_restore(UINT old_posture)
// {
.global _tx_thread_interrupt_restore
.type _tx_thread_interrupt_restore, @function
_tx_thread_interrupt_restore:
@@ -81,5 +74,4 @@ _tx_thread_interrupt_restore:
MSR DAIF, x0 // Setup the old posture
RET // Return to caller
/* } */
// }

47
ports_smp/cortex_a35_smp/ac6/src/tx_thread_schedule.S
View File

@@ -21,17 +21,6 @@
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
@@ -39,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-A35-SMP/AC6 */
/* 6.1 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -73,10 +62,13 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* VOID _tx_thread_schedule(VOID)
{ */
// VOID _tx_thread_schedule(VOID)
// {
.global _tx_thread_schedule
.type _tx_thread_schedule, @function
_tx_thread_schedule:
@@ -88,17 +80,24 @@ _tx_thread_schedule:
/* Pickup the CPU ID. */
MRS x20, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x1, x20, #16, #8 // Isolate cluster ID
#endif
UBFX x20, x20, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x1, x20, #8, #8 // Isolate cluster ID
#endif
UBFX x20, x20, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x20, x20, x1, LSL #2 // Calculate CPU ID
#endif
/* Wait for a thread to execute. */
/* do
{ */
// do
// {
LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr
@@ -119,8 +118,8 @@ _tx_thread_schedule_thread:
BEQ _tx_thread_schedule // Keep looking for a thread
#endif
/* }
while(_tx_thread_execute_ptr == TX_NULL); */
// }
// while(_tx_thread_execute_ptr == TX_NULL);
/* Get the lock for accessing the thread's ready bit. */
@@ -162,7 +161,7 @@ _tx_thread_ready_for_execution:
DMB ISH
/* Setup the current thread pointer. */
/* _tx_thread_current_ptr = _tx_thread_execute_ptr; */
// _tx_thread_current_ptr = _tx_thread_execute_ptr;
LDR x2, =_tx_thread_current_ptr // Pickup address of current thread
STR x0, [x2, x20, LSL #3] // Setup current thread pointer
@@ -190,7 +189,7 @@ _tx_thread_ready_for_execution:
_execute_pointer_did_not_change:
/* Increment the run count for this thread. */
/* _tx_thread_current_ptr -> tx_thread_run_count++; */
// _tx_thread_current_ptr -> tx_thread_run_count++;
LDR w2, [x0, #4] // Pickup run counter
LDR w3, [x0, #36] // Pickup time-slice for this thread
@@ -198,7 +197,7 @@ _execute_pointer_did_not_change:
STR w2, [x0, #4] // Store the new run counter
/* Setup time-slice, if present. */
/* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */
// _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice;
LDR x2, =_tx_timer_time_slice // Pickup address of time slice
// variable
@@ -216,7 +215,7 @@ _execute_pointer_did_not_change:
#endif
/* Switch to the thread's stack. */
/* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */
// sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr;
/* Determine if an interrupt frame or a synchronous task suspension frame
is present. */
@@ -302,6 +301,4 @@ _skip_solicited_fp_restore:
LDP x29, x30, [sp], #16 // Recover x29, x30
MSR DAIF, x4 // Recover DAIF
RET // Return to caller
/* } */
// }

78
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_get.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
@@ -21,69 +21,65 @@
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_get Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_get Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function gets the currently running core number and returns it.*/
/* */
/* INPUT */
/* */
/* */
/* This function gets the currently running core number and returns it.*/
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* Core ID */
/* */
/* CALLS */
/* */
/* */
/* OUTPUT */
/* */
/* Core ID */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_core_get
.type _tx_thread_smp_core_get, @function
_tx_thread_smp_core_get:
MRS x0, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x1, x0, #16, #8 // Isolate cluster ID
#endif
UBFX x0, x0, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x1, x0, #8, #8 // Isolate cluster ID
#endif
UBFX x0, x0, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x0, x0, x1, LSL #2 // Calculate CPU ID
#endif
RET

82
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_preempt.S
View File

@@ -12,76 +12,72 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_preempt Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_preempt Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function preempts the specified core in situations where the */
/* thread corresponding to this core is no longer ready or when the */
/* core must be used for a higher-priority thread. If the specified is */
/* the current core, this processing is skipped since the will give up */
/* control subsequently on its own. */
/* */
/* INPUT */
/* */
/* core The core to preempt */
/* */
/* OUTPUT */
/* */
/* */
/* This function preempts the specified core in situations where the */
/* thread corresponding to this core is no longer ready or when the */
/* core must be used for a higher-priority thread. If the specified is */
/* the current core, this processing is skipped since the will give up */
/* control subsequently on its own. */
/* */
/* INPUT */
/* */
/* core The core to preempt */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_core_preempt
.type _tx_thread_smp_core_preempt, @function
_tx_thread_smp_core_preempt:
DSB ISH
#ifdef TX_ARMV8_2
MOV x2, #0x1 // Build the target list field
LSL x3, x0, #16 // Build the affinity1 field
ORR x2, x2, x3 // Combine the fields
#else
MOV x2, #0x1 //
LSL x2, x2, x0 // Shift by the core ID
#endif
MSR ICC_SGI1R_EL1, x2 // Issue inter-core interrupt
RET

77
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_state_get.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
@@ -21,56 +21,46 @@
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_state_get Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_state_get Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is gets the current state of the calling core. */
/* */
/* INPUT */
/* */
/* */
/* This function is gets the current state of the calling core. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Components */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* CALLED BY */
/* */
/* ThreadX Components */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_current_state_get
@@ -80,10 +70,17 @@ _tx_thread_smp_current_state_get:
MRS x1, DAIF // Pickup current interrupt posture
MSR DAIFSet, 0x3 // Lockout interrupts
MRS x2, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #16, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #8, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x2, x2, x3, LSL #2 // Calculate CPU ID
#endif
@@ -91,5 +88,3 @@ _tx_thread_smp_current_state_get:
LDR w0, [x3, x2, LSL #2] // Pickup the current system state for this core
MSR DAIF, x1 // Restore interrupt posture
RET

76
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_thread_get.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
@@ -21,56 +21,46 @@
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_thread_get Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_thread_get Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is gets the current thread of the calling core. */
/* */
/* INPUT */
/* */
/* */
/* This function is gets the current thread of the calling core. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Components */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* CALLED BY */
/* */
/* ThreadX Components */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_current_thread_get
@@ -80,10 +70,17 @@ _tx_thread_smp_current_thread_get:
MRS x1, DAIF // Pickup current interrupt posture
MSR DAIFSet, 0x3 // Lockout interrupts
MRS x2, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #16, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #8, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x2, x2, x3, LSL #2 // Calculate CPU ID
#endif
@@ -91,4 +88,3 @@ _tx_thread_smp_current_thread_get:
LDR x0, [x3, x2, LSL #3] // Pickup the current thread pointer for this core
MSR DAIF, x1 // Restore interrupt posture
RET

106
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_initialize_wait.S
View File

@@ -12,67 +12,57 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_initialize_wait Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_initialize_wait Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is the place where additional cores wait until */
/* initialization is complete before they enter the thread scheduling */
/* loop. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* */
/* This function is the place where additional cores wait until */
/* initialization is complete before they enter the thread scheduling */
/* loop. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling loop */
/* */
/* CALLED BY */
/* */
/* Hardware */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* CALLED BY */
/* */
/* Hardware */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_initialize_wait
@@ -86,15 +76,22 @@ _tx_thread_smp_initialize_wait:
/* Pickup the Core ID. */
MRS x2, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #16, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #8, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x2, x2, x3, LSL #2 // Calculate CPU ID
#endif
/* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release
/* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release
flag. */
LDR w1, =0xF0F0F0F0 // Build TX_INITIALIZE_IN_PROGRESS flag
@@ -105,7 +102,7 @@ wait_for_initialize:
BNE wait_for_initialize // Not equal, just spin here
/* Save the system stack pointer for this core. */
LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr
MOV x1, sp // Pickup SP
SUB x1, x1, #15 //
@@ -114,30 +111,29 @@ wait_for_initialize:
/* Pickup the release cores flag. */
LDR x4, =_tx_thread_smp_release_cores_flag // Build address of release cores flag
wait_for_release:
wait_for_release:
LDR w0, [x4, #0] // Pickup the flag
CMP w0, #0 // Is it set?
BEQ wait_for_release // Wait for the flag to be set
/* Core 0 has released this core. */
/* Clear this core's system state variable. */
MOV x0, #0 // Build clear value
STR w0, [x3, x2, LSL #2] // Set the current system state for this core to zero
/* Now wait for core 0 to finish it's initialization. */
core_0_wait_loop:
LDR w0, [x3, #0] // Pickup the current system state for core 0
CMP w0, #0 // Is it 0?
BNE core_0_wait_loop // No, keep waiting for core 0 to finish its initialization
/* Initialization is complete, enter the scheduling loop! */
B _tx_thread_schedule // Enter the scheduling loop for this core
B _tx_thread_schedule // Enter the scheduling loop for this core
RET

70
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_low_level_initialize.S
View File

@@ -12,65 +12,55 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_low_level_initialize Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_low_level_initialize Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function performs low-level initialization of the booting */
/* core. */
/* */
/* INPUT */
/* */
/* number_of_cores Number of cores */
/* */
/* OUTPUT */
/* */
/* */
/* This function performs low-level initialization of the booting */
/* core. */
/* */
/* INPUT */
/* */
/* number_of_cores Number of cores */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_high_level ThreadX high-level init */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_high_level ThreadX high-level init */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_low_level_initialize

183
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protect.S
View File

@@ -12,26 +12,14 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
@@ -39,43 +27,47 @@
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_protect Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_protect Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function gets protection for running inside the ThreadX */
/* source. This is acomplished by a combination of a test-and-set */
/* flag and periodically disabling interrupts. */
/* */
/* INPUT */
/* */
/* */
/* This function gets protection for running inside the ThreadX */
/* source. This is acomplished by a combination of a test-and-set */
/* flag and periodically disabling interrupts. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* Previous Status Register */
/* */
/* CALLS */
/* */
/* */
/* OUTPUT */
/* */
/* Previous Status Register */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* improved SMP code, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_protect
@@ -90,17 +82,24 @@ _tx_thread_smp_protect:
/* Pickup the CPU ID. */
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x7, LSL #2 // Calculate CPU ID
#endif
/* Do we already have protection? */
/* if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core)
{ */
// if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core)
// {
LDR x2, =_tx_thread_smp_protection // Build address to protection structure
LDR w3, [x2, #4] // Pickup the owning core
@@ -110,7 +109,7 @@ _tx_thread_smp_protect:
/* We already have protection. */
/* Increment the protection count. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */
// _tx_thread_smp_protection.tx_thread_smp_protect_count++;
LDR w3, [x2, #8] // Pickup ownership count
ADD w3, w3, #1 // Increment ownership count
@@ -122,16 +121,16 @@ _tx_thread_smp_protect:
_protection_not_owned:
/* Is the lock available? */
/* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
{ */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
// {
LDAXR w3, [x2, #0] // Pickup the protection flag
CMP w3, #0
BNE _start_waiting // No, protection not available
/* Is the list empty? */
/* if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail)
{ */
// if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail)
// {
LDR x3, =_tx_thread_smp_protect_wait_list_head
LDR w3, [x3]
@@ -141,8 +140,8 @@ _protection_not_owned:
BNE _list_not_empty
/* Try to get the lock. */
/* if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS)
{ */
// if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS)
// {
MOV w3, #1 // Build lock value
STXR w4, w3, [x2, #0] // Attempt to get the protection
@@ -150,7 +149,7 @@ _protection_not_owned:
BNE _start_waiting // Did it fail?
/* We got the lock! */
/* _tx_thread_smp_protect_lock_got(); */
// _tx_thread_smp_protect_lock_got();
DMB ISH // Ensure write to protection finishes
_tx_thread_smp_protect_lock_got // Call the lock got function
@@ -160,8 +159,8 @@ _protection_not_owned:
_list_not_empty:
/* Are we at the front of the list? */
/* if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head])
{ */
// if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head])
// {
LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
LDR w3, [x3] // Get the value of the head
@@ -172,27 +171,29 @@ _list_not_empty:
BNE _start_waiting
/* Is the lock still available? */
/* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
{ */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
// {
LDR w3, [x2, #0] // Pickup the protection flag
LDAXR w3, [x2, #0] // Pickup the protection flag
CMP w3, #0
BNE _start_waiting // No, protection not available
/* Get the lock. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1;
MOV w3, #1 // Build lock value
STR w3, [x2, #0] // Store lock value
STXR w4, w3, [x2, #0] // Attempt to get the protection
CMP w4, #0
BNE _start_waiting // Did it fail?
DMB ISH //
/* Got the lock. */
/* _tx_thread_smp_protect_lock_got(); */
// _tx_thread_smp_protect_lock_got();
_tx_thread_smp_protect_lock_got
/* Remove this core from the wait list. */
/* _tx_thread_smp_protect_remove_from_front_of_list(); */
// _tx_thread_smp_protect_remove_from_front_of_list();
_tx_thread_smp_protect_remove_from_front_of_list
@@ -203,7 +204,7 @@ _start_waiting:
/* For one reason or another, we didn't get the lock. */
/* Increment wait count. */
/* _tx_thread_smp_protect_wait_counts[this_core]++; */
// _tx_thread_smp_protect_wait_counts[this_core]++;
LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts
LDR w4, [x3, x1, LSL #2] // Load waiting value for this core
@@ -211,32 +212,32 @@ _start_waiting:
STR w4, [x3, x1, LSL #2] // Store new wait value
/* Have we not added ourselves to the list yet? */
/* if (_tx_thread_smp_protect_wait_counts[this_core] == 1)
{ */
// if (_tx_thread_smp_protect_wait_counts[this_core] == 1)
// {
CMP w4, #1
BNE _already_in_list0 // Is this core already waiting?
/* Add ourselves to the list. */
/* _tx_thread_smp_protect_wait_list_add(this_core); */
// _tx_thread_smp_protect_wait_list_add(this_core);
_tx_thread_smp_protect_wait_list_add // Call macro to add ourselves to the list
/* } */
// }
_already_in_list0:
/* Restore interrupts. */
MSR DAIF, x0 // Restore interrupts
ISB //
ISB //
#ifdef TX_ENABLE_WFE
WFE // Go into standby
#endif
/* We do this until we have the lock. */
/* while (1)
{ */
// while (1)
// {
_try_to_get_lock:
@@ -248,28 +249,35 @@ _try_to_get_lock:
/* Pickup the CPU ID. */
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x7, LSL #2 // Calculate CPU ID
#endif
/* Do we already have protection? */
/* if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core)
{ */
// if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core)
// {
LDR w3, [x2, #4] // Pickup the owning core
CMP w3, w1 // Is it this core?
BEQ _got_lock_after_waiting // Yes, the protection is already owned. This means
// an ISR preempted us and got protection
/* } */
// }
/* Are we at the front of the list? */
/* if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head])
{ */
// if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head])
// {
LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
LDR w3, [x3] // Get the value of the head
@@ -280,27 +288,29 @@ _try_to_get_lock:
BNE _did_not_get_lock
/* Is the lock still available? */
/* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
{ */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
// {
LDR w3, [x2, #0] // Pickup the protection flag
LDAXR w3, [x2, #0] // Pickup the protection flag
CMP w3, #0
BNE _did_not_get_lock // No, protection not available
/* Get the lock. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1;
MOV w3, #1 // Build lock value
STR w3, [x2, #0] // Store lock value
STXR w4, w3, [x2, #0] // Attempt to get the protection
CMP w4, #0
BNE _did_not_get_lock // Did it fail?
DMB ISH //
/* Got the lock. */
/* _tx_thread_smp_protect_lock_got(); */
// _tx_thread_smp_protect_lock_got();
_tx_thread_smp_protect_lock_got
/* Remove this core from the wait list. */
/* _tx_thread_smp_protect_remove_from_front_of_list(); */
// _tx_thread_smp_protect_remove_from_front_of_list();
_tx_thread_smp_protect_remove_from_front_of_list
@@ -312,8 +322,8 @@ _did_not_get_lock:
/* Were we removed from the list? This can happen if we're a thread
and we got preempted. */
/* if (_tx_thread_smp_protect_wait_counts[this_core] == 0)
{ */
// if (_tx_thread_smp_protect_wait_counts[this_core] == 0)
// {
LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts
LDR w4, [x3, x1, LSL #2] // Load waiting value for this core
@@ -321,26 +331,26 @@ _did_not_get_lock:
BNE _already_in_list1 // Is this core already in the list?
/* Add ourselves to the list. */
/* _tx_thread_smp_protect_wait_list_add(this_core); */
// _tx_thread_smp_protect_wait_list_add(this_core);
_tx_thread_smp_protect_wait_list_add // Call macro to add ourselves to the list
/* Our waiting count was also reset when we were preempted. Increment it again. */
/* _tx_thread_smp_protect_wait_counts[this_core]++; */
// _tx_thread_smp_protect_wait_counts[this_core]++;
LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts
LDR w4, [x3, x1, LSL #2] // Load waiting value for this core
ADD w4, w4, #1 // Increment wait value
STR w4, [x3, x1, LSL #2] // Store new wait value value
/* } */
// }
_already_in_list1:
/* Restore interrupts and try again. */
MSR DAIF, x0 // Restore interrupts
ISB //
ISB //
#ifdef TX_ENABLE_WFE
WFE // Go into standby
#endif
@@ -349,7 +359,7 @@ _already_in_list1:
_got_lock_after_waiting:
/* We're no longer waiting. */
/* _tx_thread_smp_protect_wait_counts[this_core]--; */
// _tx_thread_smp_protect_wait_counts[this_core]--;
LDR x3, =_tx_thread_smp_protect_wait_counts // Load waiting list
LDR w4, [x3, x1, LSL #2] // Load current wait value
@@ -361,4 +371,3 @@ _got_lock_after_waiting:
_return:
RET

116
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h
View File

@@ -23,12 +23,12 @@
.macro _tx_thread_smp_protect_lock_got
/* Set the currently owned core. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core;
STR w1, [x2, #4] // Store this core
/* Increment the protection count. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */
// _tx_thread_smp_protection.tx_thread_smp_protect_count++;
LDR w3, [x2, #8] // Pickup ownership count
ADD w3, w3, #1 // Increment ownership count
@@ -40,7 +40,7 @@
.macro _tx_thread_smp_protect_remove_from_front_of_list
/* Remove ourselves from the list. */
/* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; */
// _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF;
MOV w3, #0xFFFFFFFF // Build the invalid core value
LDR x4, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
@@ -50,53 +50,55 @@
ADD w5, w5, #1 // Increment the head
/* Did we wrap? */
/* if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1)
{ */
// if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1)
// {
LDR x3, =_tx_thread_smp_protect_wait_list_size // Load address of core list size
LDR w3, [x3] // Load the max cores value
CMP w5, w3 // Compare the head to it
BNE _store_new_head\@ // Are we at the max?
/* _tx_thread_smp_protect_wait_list_head = 0; */
// _tx_thread_smp_protect_wait_list_head = 0;
EOR w5, w5, w5 // We're at the max. Set it to zero
/* } */
// }
_store_new_head\@:
STR w5, [x4] // Store the new head
/* We have the lock! */
/* return; */
DMB ISH // Ensure write to protection finishes
// return;
.endm
.macro _tx_thread_smp_protect_wait_list_lock_get
/* VOID _tx_thread_smp_protect_wait_list_lock_get()
{ */
// VOID _tx_thread_smp_protect_wait_list_lock_get()
// {
/* We do this until we have the lock. */
/* while (1)
{ */
// while (1)
// {
_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
/* Is the list lock available? */
/* _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); */
// Is the list lock available? */
// _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force);
LDR x1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force
LDAXR w2, [x1] // Pickup the protection flag
/* if (protect_in_force == 0)
{ */
// if (protect_in_force == 0)
// {
CMP w2, #0
BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // No, protection not available
/* Try to get the list. */
/* int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); */
// int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1);
MOV w2, #1 // Build lock value
STXR w3, w2, [x1] // Attempt to get the protection
@@ -107,17 +109,17 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // Did it fail? If so, try again.
/* We have the lock! */
/* return; */
// return;
.endm
.macro _tx_thread_smp_protect_wait_list_add
/* VOID _tx_thread_smp_protect_wait_list_add(UINT new_core)
{ */
// VOID _tx_thread_smp_protect_wait_list_add(UINT new_core)
// {
/* We're about to modify the list, so get the list lock. */
/* _tx_thread_smp_protect_wait_list_lock_get(); */
// _tx_thread_smp_protect_wait_list_lock_get();
STP x1, x2, [sp, #-16]! // Save registers we'll be using
@@ -126,7 +128,7 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
LDP x1, x2, [sp], #16
/* Add this core. */
/* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; */
// _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core;
LDR x3, =_tx_thread_smp_protect_wait_list_tail // Get the address of the tail
LDR w4, [x3] // Get the value of tail
@@ -135,64 +137,66 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
ADD w4, w4, #1 // Increment the tail
/* Did we wrap? */
/* if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size)
{ */
// if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size)
// {
LDR x5, =_tx_thread_smp_protect_wait_list_size // Load max cores address
LDR w5, [x5] // Load max cores value
CMP w4, w5 // Compare max cores to tail
BNE _tx_thread_smp_protect_wait_list_add__no_wrap\@ // Did we wrap?
/* _tx_thread_smp_protect_wait_list_tail = 0; */
// _tx_thread_smp_protect_wait_list_tail = 0;
MOV w4, #0
/* } */
// }
_tx_thread_smp_protect_wait_list_add__no_wrap\@:
STR w4, [x3] // Store the new tail value.
DMB ISH // Ensure that accesses to shared resource have completed
/* Release the list lock. */
/* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */
// _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0;
MOV w3, #0 // Build lock value
LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force
STR w3, [x4] // Store the new value
DMB ISH // Ensure write to protection finishes
.endm
.macro _tx_thread_smp_protect_wait_list_remove
/* VOID _tx_thread_smp_protect_wait_list_remove(UINT core)
{ */
// VOID _tx_thread_smp_protect_wait_list_remove(UINT core)
// {
/* Get the core index. */
/* UINT core_index;
for (core_index = 0;; core_index++) */
// UINT core_index;
// for (core_index = 0;; core_index++)
EOR w4, w4, w4 // Clear for 'core_index'
LDR x2, =_tx_thread_smp_protect_wait_list // Get the address of the list
/* { */
// {
_tx_thread_smp_protect_wait_list_remove__check_cur_core\@:
/* Is this the core? */
/* if (_tx_thread_smp_protect_wait_list[core_index] == core)
{
break; */
// if (_tx_thread_smp_protect_wait_list[core_index] == core)
// {
// break;
LDR w3, [x2, x4, LSL #2] // Get the value at the current index
CMP w3, w8 // Did we find the core?
BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@
/* } */
// }
ADD w4, w4, #1 // Increment cur index
B _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ // Restart the loop
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__found_core\@:
@@ -200,15 +204,15 @@ _tx_thread_smp_protect_wait_list_remove__found_core\@:
core could be simultaneously adding (a core is simultaneously trying to get
the inter-core lock) or removing (a core is simultaneously being preempted,
like what is currently happening). */
/* _tx_thread_smp_protect_wait_list_lock_get(); */
// _tx_thread_smp_protect_wait_list_lock_get();
MOV x6, x1
_tx_thread_smp_protect_wait_list_lock_get
MOV x1, x6
/* We remove by shifting. */
/* while (core_index != _tx_thread_smp_protect_wait_list_tail)
{ */
// while (core_index != _tx_thread_smp_protect_wait_list_tail)
// {
_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@:
@@ -217,76 +221,78 @@ _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@:
CMP w4, w2 // Compare cur index and tail
BEQ _tx_thread_smp_protect_wait_list_remove__removed\@
/* UINT next_index = core_index + 1; */
// UINT next_index = core_index + 1;
MOV w2, w4 // Move current index to next index register
ADD w2, w2, #1 // Add 1
/* if (next_index == _tx_thread_smp_protect_wait_list_size)
{ */
// if (next_index == _tx_thread_smp_protect_wait_list_size)
// {
LDR x3, =_tx_thread_smp_protect_wait_list_size
LDR w3, [x3]
CMP w2, w3
BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@
/* next_index = 0; */
// next_index = 0;
MOV w2, #0
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@:
/* list_cores[core_index] = list_cores[next_index]; */
// list_cores[core_index] = list_cores[next_index];
LDR x5, =_tx_thread_smp_protect_wait_list // Get the address of the list
LDR w3, [x5, x2, LSL #2] // Get the value at the next index
STR w3, [x5, x4, LSL #2] // Store the value at the current index
/* core_index = next_index; */
// core_index = next_index;
MOV w4, w2
B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__removed\@:
/* Now update the tail. */
/* if (_tx_thread_smp_protect_wait_list_tail == 0)
{ */
// if (_tx_thread_smp_protect_wait_list_tail == 0)
// {
LDR x5, =_tx_thread_smp_protect_wait_list_tail // Load tail address
LDR w4, [x5] // Load tail value
CMP w4, #0
BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@
/* _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; */
// _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size;
LDR x2, =_tx_thread_smp_protect_wait_list_size
LDR w4, [x2]
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@:
/* _tx_thread_smp_protect_wait_list_tail--; */
// _tx_thread_smp_protect_wait_list_tail--;
SUB w4, w4, #1
STR w4, [x5] // Store new tail value
DMB ISH // Ensure that accesses to shared resource have completed
/* Release the list lock. */
/* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */
// _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0;
MOV w2, #0 // Build lock value
LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force // Load lock address
STR w2, [x4] // Store the new value
DMB ISH // Ensure write to protection finishes
/* We're no longer waiting. Note that this should be zero since, again,
this function is only called when a thread preemption is occurring. */
/* _tx_thread_smp_protect_wait_counts[core]--; */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x4, =_tx_thread_smp_protect_wait_counts // Load wait list counts
LDR w2, [x4, x8, LSL #2] // Load waiting value
SUB w2, w2, #1 // Subtract 1

73
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_time_get.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
@@ -21,57 +21,46 @@
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_time_get Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_time_get Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function gets the global time value that is used for debug */
/* information and event tracing. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* 32-bit time stamp */
/* */
/* CALLS */
/* */
/* */
/* This function gets the global time value that is used for debug */
/* information and event tracing. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* */
/* OUTPUT */
/* */
/* 32-bit time stamp */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_time_get
@@ -79,5 +68,3 @@
_tx_thread_smp_time_get:
MOV x0, #0 // FIXME: Get timer
RET

26
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_unprotect.S
View File

@@ -21,19 +21,6 @@
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
@@ -41,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_unprotect Cortex-A35-SMP/AC6 */
/* 6.1 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -74,6 +61,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -82,10 +72,17 @@ _tx_thread_smp_unprotect:
MSR DAIFSet, 0x3 // Lockout interrupts
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x2, LSL #2 // Calculate CPU ID
#endif
@@ -127,4 +124,3 @@ _still_protected:
#endif
MSR DAIF, x0 // Restore interrupt posture
RET

88
ports_smp/cortex_a35_smp/ac6/src/tx_thread_stack_build.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -21,69 +21,59 @@
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* */
/* This function builds a stack frame on the supplied thread's stack. */
/* The stack frame results in a fake interrupt return to the supplied */
/* function pointer. */
/* */
/* INPUT */
/* */
/* thread_ptr Pointer to thread control blk */
/* function_ptr Pointer to return function */
/* */
/* OUTPUT */
/* */
/* function pointer. */
/* */
/* INPUT */
/* */
/* thread_ptr Pointer to thread */
/* function_ptr Pointer to entry function */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* */
/* CALLED BY */
/* */
/* _tx_thread_create Create thread service */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
{ */
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
// {
.global _tx_thread_stack_build
.type _tx_thread_stack_build, @function
_tx_thread_stack_build:
/* Build a fake interrupt frame. The form of the fake interrupt stack
on the Cortex-A35 should look like the following after it is built:
/* Build an interrupt frame. On Cortex-A35 it should look like this:
Stack Top: SSPR Initial SSPR
ELR Point of interrupt
x28 Initial value for x28
@@ -129,7 +119,7 @@ _tx_thread_stack_build:
MOV x2, #0 // Build clear value
MOV x3, #0 //
STP x2, x3, [x4, #-16]! // Set backtrace to 0
STP x2, x3, [x4, #-16]! // Set initial x29, x30
STP x2, x3, [x4, #-16]! // Set initial x0, x1
@@ -160,13 +150,11 @@ _tx_thread_stack_build:
STP x2, x3, [x4, #-16]! // Set initial SPSR & ELR
/* Setup stack pointer. */
/* thread_ptr -> tx_thread_stack_ptr = x2; */
// thread_ptr -> tx_thread_stack_ptr = x2;
STR x4, [x0, #8] // Save stack pointer in thread's
MOV x3, #1 // Build ready flag
STR w3, [x0, #260] // Set ready flag
STR w3, [x0, #260] // Set ready flag
RET // Return to caller
/* } */
// }

124
ports_smp/cortex_a35_smp/ac6/src/tx_thread_system_return.S
View File

@@ -12,75 +12,68 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is target processor specific. It is used to transfer */
/* control from a thread back to the ThreadX system. Only a */
/* minimal context is saved since the compiler assumes temp registers */
/* are going to get slicked by a function call anyway. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling loop */
/* */
/* CALLED BY */
/* */
/* ThreadX components */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This function is target processor specific. It is used to transfer */
/* control from a thread back to the ThreadX system. Only a */
/* minimal context is saved since the compiler assumes temp registers */
/* are going to get slicked by a function call anyway. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling loop */
/* */
/* CALLED BY */
/* */
/* ThreadX components */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* VOID _tx_thread_system_return(VOID)
{ */
// VOID _tx_thread_system_return(VOID)
// {
.global _tx_thread_system_return
.type _tx_thread_system_return, @function
_tx_thread_system_return:
;
; /* Save minimal context on the stack. */
;
/* Save minimal context on the stack. */
MRS x0, DAIF // Pickup DAIF
MSR DAIFSet, 0x3 // Lockout interrupts
STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register)
@@ -90,10 +83,17 @@ _tx_thread_system_return:
STP x25, x26, [sp, #-16]! // Save x25, x26
STP x27, x28, [sp, #-16]! // Save x27, x28
MRS x8, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x8, #16, #8 // Isolate cluster ID
#endif
UBFX x8, x8, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x8, #8, #8 // Isolate cluster ID
#endif
UBFX x8, x8, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x8, x8, x3, LSL #2 // Calculate CPU ID
#endif
@@ -134,8 +134,8 @@ _skip_fp_save:
LDR w1, [x2, x8, LSL #2] // Pickup current time slice
/* Save current stack and switch to system stack. */
/* _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; */
/* sp = _tx_thread_system_stack_ptr[core]; */
// _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp;
// sp = _tx_thread_system_stack_ptr[core];
MOV x4, sp //
STR x4, [x6, #8] // Save thread stack pointer
@@ -144,36 +144,36 @@ _skip_fp_save:
MOV sp, x4 // Setup system stack pointer
/* Determine if the time-slice is active. */
/* if (_tx_timer_time_slice[core])
{ */
// if (_tx_timer_time_slice[core])
// {
MOV x4, #0 // Build clear value
CMP w1, #0 // Is a time-slice active?
BEQ __tx_thread_dont_save_ts // No, don't save the time-slice
/* Save the current remaining time-slice. */
/* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
_tx_timer_time_slice = 0; */
// _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
// _tx_timer_time_slice = 0;
STR w4, [x2, x8, LSL #2] // Clear time-slice
STR w1, [x6, #36] // Store current time-slice
/* } */
// }
__tx_thread_dont_save_ts:
/* Clear the current thread pointer. */
/* _tx_thread_current_ptr = TX_NULL; */
// _tx_thread_current_ptr = TX_NULL;
STR x4, [x5, x8, LSL #3] // Clear current thread pointer
/* Set ready bit in thread control block. */
MOV x3, #1 // Build ready value
STR w3, [x6, #260] // Make the thread ready
DMB ISH //
STR w3, [x6, #260] // Make the thread ready
DMB ISH //
/* Now clear protection. It is assumed that protection is in force whenever this routine is called. */
LDR x3, =_tx_thread_smp_protection // Pickup address of protection structure
LDR x1, =_tx_thread_preempt_disable // Build address to preempt disable flag
STR w4, [x1, #0] // Clear preempt disable flag
@@ -186,6 +186,4 @@ __tx_thread_dont_save_ts:
SEV // Send event to other CPUs, wakes anyone waiting on a mutex (using WFE)
B _tx_thread_schedule // Jump to scheduler!
/* } */
// }

79
ports_smp/cortex_a35_smp/ac6/src/tx_thread_timeout.c
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -30,48 +30,50 @@
#include "tx_timer.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_timeout Cortex-A35-SMP */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_timeout Cortex-A35-SMP */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function handles thread timeout processing. Timeouts occur in */
/* two flavors, namely the thread sleep timeout and all other service */
/* call timeouts. Thread sleep timeouts are processed locally, while */
/* the others are processed by the appropriate suspension clean-up */
/* service. */
/* */
/* INPUT */
/* */
/* timeout_input Contains the thread pointer */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* Suspension Cleanup Functions */
/* _tx_thread_system_resume Resume thread */
/* _tx_thread_system_ni_resume Non-interruptable resume thread */
/* */
/* CALLED BY */
/* */
/* _tx_timer_expiration_process Timer expiration function */
/* _tx_timer_thread_entry Timer thread function */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This function handles thread timeout processing. Timeouts occur in */
/* two flavors, namely the thread sleep timeout and all other service */
/* call timeouts. Thread sleep timeouts are processed locally, while */
/* the others are processed by the appropriate suspension clean-up */
/* service. */
/* */
/* INPUT */
/* */
/* timeout_input Contains the thread pointer */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* Suspension Cleanup Functions */
/* _tx_thread_system_resume Resume thread */
/* _tx_thread_system_ni_resume Non-interruptable resume thread */
/* */
/* CALLED BY */
/* */
/* _tx_timer_expiration_process Timer expiration function */
/* _tx_timer_thread_entry Timer thread function */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
VOID _tx_thread_timeout(ULONG timeout_input)
@@ -79,7 +81,7 @@ VOID _tx_thread_timeout(ULONG timeout_input)
TX_INTERRUPT_SAVE_AREA
TX_THREAD *thread_ptr;
TX_THREAD *thread_ptr;
VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence);
ULONG suspension_sequence;
@@ -126,7 +128,7 @@ ULONG suspension_sequence;
/* Increment the number of timeouts for this thread. */
thread_ptr -> tx_thread_performance_timeout_count++;
#endif
/* Pickup the cleanup routine address. */
suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup;
@@ -162,4 +164,3 @@ ULONG suspension_sequence;
#endif
}
}

129
ports_smp/cortex_a35_smp/ac6/src/tx_timer_interrupt.S
View File

@@ -12,80 +12,77 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Timer */
/** */
/**************************************************************************/
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_timer.h"
#include "tx_thread.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-A35-SMP/AC6 */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function processes the hardware timer interrupt. This */
/* processing includes incrementing the system clock and checking for */
/* time slice and/or timer expiration. If either is found, the */
/* interrupt context save/restore functions are called along with the */
/* expiration functions. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_timer_expiration_process Timer expiration processing */
/* _tx_thread_time_slice Time slice interrupted thread */
/* */
/* CALLED BY */
/* */
/* interrupt vector */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This function processes the hardware timer interrupt. This */
/* processing includes incrementing the system clock and checking for */
/* time slice and/or timer expiration. If either is found, the */
/* interrupt context save/restore functions are called along with the */
/* expiration functions. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_timer_expiration_process Timer expiration processing */
/* _tx_thread_time_slice Time slice interrupted thread */
/* */
/* CALLED BY */
/* */
/* interrupt vector */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* */
/**************************************************************************/
/* VOID _tx_timer_interrupt(VOID)
{ */
// VOID _tx_timer_interrupt(VOID)
// {
.global _tx_timer_interrupt
.type _tx_timer_interrupt, @function
_tx_timer_interrupt:
MRS x2, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #16, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #8, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x2, x2, x3, LSL #2 // Calculate CPU ID
#endif
@@ -107,7 +104,7 @@ __tx_process_timer:
MOV x28, x0 // Save the return value in preserved register
/* Increment the system clock. */
/* _tx_timer_system_clock++; */
// _tx_timer_system_clock++;
LDR x1, =_tx_timer_system_clock // Pickup address of system clock
LDR w0, [x1, #0] // Pickup system clock
@@ -115,8 +112,8 @@ __tx_process_timer:
STR w0, [x1, #0] // Store new system clock
/* Test for timer expiration. */
/* if (*_tx_timer_current_ptr)
{ */
// if (*_tx_timer_current_ptr)
// {
LDR x1, =_tx_timer_current_ptr // Pickup current timer pointer addr
LDR x0, [x1, #0] // Pickup current timer
@@ -125,25 +122,25 @@ __tx_process_timer:
BEQ __tx_timer_no_timer // No, just increment the timer
/* Set expiration flag. */
/* _tx_timer_expired = TX_TRUE; */
// _tx_timer_expired = TX_TRUE;
LDR x3, =_tx_timer_expired // Pickup expiration flag address
MOV w2, #1 // Build expired value
STR w2, [x3, #0] // Set expired flag
B __tx_timer_done // Finished timer processing
/* }
else
{ */
// }
// else
// {
__tx_timer_no_timer:
/* No timer expired, increment the timer pointer. */
/* _tx_timer_current_ptr++; */
// _tx_timer_current_ptr++;
ADD x0, x0, #8 // Move to next timer
/* Check for wrap-around. */
/* if (_tx_timer_current_ptr == _tx_timer_list_end) */
// if (_tx_timer_current_ptr == _tx_timer_list_end)
LDR x3, =_tx_timer_list_end // Pickup addr of timer list end
LDR x2, [x3, #0] // Pickup list end
@@ -151,7 +148,7 @@ __tx_timer_no_timer:
BNE __tx_timer_skip_wrap // No, skip wrap-around logic
/* Wrap to beginning of list. */
/* _tx_timer_current_ptr = _tx_timer_list_start; */
// _tx_timer_current_ptr = _tx_timer_list_start;
LDR x3, =_tx_timer_list_start // Pickup addr of timer list start
LDR x0, [x3, #0] // Set current pointer to list start
@@ -159,13 +156,13 @@ __tx_timer_no_timer:
__tx_timer_skip_wrap:
STR x0, [x1, #0] // Store new current timer pointer
/* } */
// }
__tx_timer_done:
/* Did a timer expire? */
/* if (_tx_timer_expired)
{ */
// if (_tx_timer_expired)
// {
LDR x1, =_tx_timer_expired // Pickup addr of expired flag
LDR w0, [x1, #0] // Pickup timer expired flag
@@ -173,26 +170,24 @@ __tx_timer_done:
BEQ __tx_timer_dont_activate // If not set, skip timer activation
/* Process timer expiration. */
/* _tx_timer_expiration_process(); */
// _tx_timer_expiration_process();
BL _tx_timer_expiration_process // Call the timer expiration handling routine
/* } */
// }
__tx_timer_dont_activate:
/* Call time-slice processing. */
/* _tx_thread_time_slice(); */
// _tx_thread_time_slice();
BL _tx_thread_time_slice // Call time-slice processing
/* Release inter-core protection. */
MOV x0, x28 // Pass the previous status register back
MOV x0, x28 // Pass the previous status register back
BL _tx_thread_smp_unprotect // Release protection
LDP x29, x30, [sp], #16 // Recover x29, x30
LDP x27, x28, [sp], #16 // Recover x27, x28
RET // Return to caller
/* } */
// }

90
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.cproject
View File

@@ -51,6 +51,8 @@
</option>
<option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.arch.592546526" name="Architecture (-march)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.arch" useByScannerDiscovery="false" value="armv8-a" valueType="string"/>
<inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.1092691037" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input"/>
</tool>
@@ -67,6 +69,8 @@
<option defaultValue="true" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug.427023612" name="Generate debugging information (-g)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.debug" valueType="boolean"/>
<option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.arch.1946877163" name="Architecture (-march)" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.option.arch" useByScannerDiscovery="false" value="armv8-a" valueType="string"/>
<inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input.1130706267" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input"/>
</tool>
@@ -114,92 +118,6 @@
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
<cconfiguration id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.642985025">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.642985025" moduleId="org.eclipse.cdt.core.settings" name="Release">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="clean" description="" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.642985025" name="Release" parent="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf">
<folderInfo id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.642985025." name="/" resourcePath="">
<toolChain id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.exe.release.var.gcc-8.3.0-aarch64-elf.1889558597" name="GCC 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.toolchain.exe.release.var.gcc-8.3.0-aarch64-elf">
<targetPlatform id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.642985025..1708553087" name=""/>
<builder buildPath="${workspace_loc:/sample_threadx}/Release" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder.416280101" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.target.builder"/>
<tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1917850252" name="GCC C Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf">
<option defaultValue="gnu.c.optimization.level.most" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1722348869" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
<option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.1341620364" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
<inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.1015544157" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input"/>
</tool>
<tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf.641068181" name="GCC C++ Compiler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.compiler.var.gcc-8.3.0-aarch64-elf">
<option defaultValue="gnu.c.optimization.level.most" id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt.1891867995" name="Optimization Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.opt" useByScannerDiscovery="false" valueType="enumerated"/>
<option id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug.1839498489" name="Debug Level" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.option.debug" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
</tool>
<tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf.2025441100" name="GCC Assembler 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.var.gcc-8.3.0-aarch64-elf">
<inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input.685695697" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.assembler.input"/>
</tool>
<tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf.205164594" name="GCC C Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.var.gcc-8.3.0-aarch64-elf">
<inputType id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input.1542192122" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.linker.input">
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
</inputType>
</tool>
<tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf.1330330667" name="GCC C++ Linker 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.cpp.linker.var.gcc-8.3.0-aarch64-elf"/>
<tool id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf.1377298461" name="GCC Archiver 8.3.0 [aarch64-elf]" superClass="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.archiver.var.gcc-8.3.0-aarch64-elf"/>
</toolChain>
</folderInfo>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>

48
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/.settings/language.settings.xml
View File

@@ -1,48 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.1006631269" name="Debug">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.arm.managedbuilder.gcc.langsettings.ArmGCCBaremetalLanguageSettingsProvider" console="false" env-hash="-606533458206092714" id="com.arm.managedbuilder.langsettingsprovider.arm.gcc.baremetal" keep-relative-paths="false" name="Arm GCC Built-in Compiler Settings Baremetal" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
</extension>
</configuration>
<configuration id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.642985025" name="Release">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.arm.managedbuilder.gcc.langsettings.ArmGCCBaremetalLanguageSettingsProvider" console="false" env-hash="-606533458206092714" id="com.arm.managedbuilder.langsettingsprovider.arm.gcc.baremetal" keep-relative-paths="false" name="Arm GCC Built-in Compiler Settings Baremetal" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
</extension>
</configuration>
</project>

2
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3.h
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef GICV3_h

2
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_aliases.h
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicc.h
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef GICV3_gicc_h

2
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicd.c
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#include <stdint.h>

4
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicr.c
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2014-2018 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#include "GICv3.h"
@@ -274,7 +274,7 @@ void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group)
uint32_t groupmod;
/*
* get each bit of group config duplicated over all 32 bits
* get each bit of group config duplicated over all 32-bits
*/
groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31);
group = (uint32_t)(((int32_t)group << nbits) >> 31);

2
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/PPM_AEM.h
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

48
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c
View File

@@ -1,5 +1,5 @@
/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
threads of different priorities, using a message queue, semaphore, mutex, event flags group,
byte pool, and block pool. */
#include "tx_api.h"
@@ -86,7 +86,7 @@ int main(void)
void tx_application_define(void *first_unused_memory)
{
CHAR *pointer;
CHAR *pointer = TX_NULL;
#ifdef TX_ENABLE_EVENT_TRACE
@@ -101,41 +101,41 @@ CHAR *pointer;
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create the main thread. */
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0,
pointer, DEMO_STACK_SIZE,
1, 1, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 1. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 1 and 2. These threads pass information through a ThreadX
/* Create threads 1 and 2. These threads pass information through a ThreadX
message queue. It is also interesting to note that these threads have a time
slice. */
tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 2. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2,
pointer, DEMO_STACK_SIZE,
pointer, DEMO_STACK_SIZE,
16, 16, 4, TX_AUTO_START);
/* Allocate the stack for thread 3. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
/* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore.
An interesting thing here is that both threads share the same instruction area. */
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 4. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 5. */
@@ -143,23 +143,23 @@ CHAR *pointer;
/* Create thread 5. This thread simply pends on an event flag which will be set
by thread_0. */
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5,
pointer, DEMO_STACK_SIZE,
4, 4, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 6. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
/* Create threads 6 and 7. These threads compete for a ThreadX mutex. */
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the stack for thread 7. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7,
pointer, DEMO_STACK_SIZE,
8, 8, TX_NO_TIME_SLICE, TX_AUTO_START);
/* Allocate the message queue. */
@@ -261,11 +261,11 @@ UINT status;
/* Retrieve a message from the queue. */
status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER);
/* Check completion status and make sure the message is what we
/* Check completion status and make sure the message is what we
expected. */
if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received))
break;
/* Otherwise, all is okay. Increment the received message count. */
thread_2_messages_received++;
}
@@ -324,7 +324,7 @@ ULONG actual_flags;
thread_5_counter++;
/* Wait for event flag 0. */
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR,
&actual_flags, TX_WAIT_FOREVER);
/* Check status. */
@@ -377,7 +377,7 @@ UINT status;
if (status != TX_SUCCESS)
break;
/* Release the mutex again. This will actually
/* Release the mutex again. This will actually
release ownership since it was obtained twice. */
status = tx_mutex_put(&mutex_0);

110
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.launch
View File

@@ -5,69 +5,69 @@
<stringAttribute key="ANDROID_APP_DIR" value=""/>
<stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
<mapAttribute key="AverageDurationTracker">
<mapEntry key="*Fetching Data" value="89578513"/>
<mapEntry key="*Fetching Data Model" value="2590988"/>
<mapEntry key="*Fetching Data" value="121247103"/>
<mapEntry key="*Fetching Data Model" value="3376098"/>
<mapEntry key="*FunctionLoader" value="137168653"/>
<mapEntry key="*list global low level symbols" value="2201767"/>
<mapEntry key="*list global low level symbols" value="1899166"/>
<mapEntry key="*loading memory from target" value="2367919"/>
<mapEntry key="*loading values from target" value="15477096"/>
<mapEntry key="*loading values from target" value="13078793"/>
<mapEntry key="*trace" value="334742630"/>
<mapEntry key="*updating expressions" value="900994463"/>
<mapEntry key="*updating expressions" value="375472141"/>
<mapEntry key="*updating local_variables" value="461891"/>
<mapEntry key="*updating registers" value="47308607"/>
<mapEntry key="*updating variables" value="877039"/>
<mapEntry key="AddEventObserver" value="11937441"/>
<mapEntry key="Evaluate" value="2985778"/>
<mapEntry key="AddEventObserver" value="5805417"/>
<mapEntry key="Evaluate" value="12827993"/>
<mapEntry key="ResumeToHere" value="20159012"/>
<mapEntry key="Retrieving globals list" value="21298708"/>
<mapEntry key="areCachesAvailable" value="790123"/>
<mapEntry key="backtrace" value="2055607"/>
<mapEntry key="break" value="5253493"/>
<mapEntry key="checking tracepoints" value="356506"/>
<mapEntry key="compute execution mode" value="663718"/>
<mapEntry key="checking tracepoints" value="92412"/>
<mapEntry key="compute execution mode" value="899838"/>
<mapEntry key="console" value="11946310"/>
<mapEntry key="continue" value="15520207"/>
<mapEntry key="continue" value="11209568"/>
<mapEntry key="core" value="3342238"/>
<mapEntry key="directory" value="16230007"/>
<mapEntry key="directory" value="6811550"/>
<mapEntry key="disable" value="2444670"/>
<mapEntry key="disassemble" value="269175113"/>
<mapEntry key="disassemble" value="90761388"/>
<mapEntry key="enable" value="5445745"/>
<mapEntry key="evaluate" value="5333036"/>
<mapEntry key="evaluate address" value="1056014"/>
<mapEntry key="finish" value="20115248"/>
<mapEntry key="get byte order" value="633302"/>
<mapEntry key="get capabilities" value="310592"/>
<mapEntry key="get execution addresss" value="752111"/>
<mapEntry key="get source lines" value="3119541"/>
<mapEntry key="get substitute paths" value="384451"/>
<mapEntry key="get capabilities" value="323786"/>
<mapEntry key="get execution addresss" value="3339733"/>
<mapEntry key="get source lines" value="10489178"/>
<mapEntry key="get substitute paths" value="562096"/>
<mapEntry key="getValidEncodings" value="1253192"/>
<mapEntry key="initialize command help" value="94010230"/>
<mapEntry key="interrupt" value="32230330"/>
<mapEntry key="list breakpoint options" value="2649765"/>
<mapEntry key="list breakpoints" value="1792136"/>
<mapEntry key="list instruction sets" value="1951102"/>
<mapEntry key="list signals" value="2642566"/>
<mapEntry key="initialize command help" value="87603528"/>
<mapEntry key="interrupt" value="12378383"/>
<mapEntry key="list breakpoint options" value="1935354"/>
<mapEntry key="list breakpoints" value="1803667"/>
<mapEntry key="list instruction sets" value="2659862"/>
<mapEntry key="list signals" value="2562245"/>
<mapEntry key="list source files" value="1035061"/>
<mapEntry key="list watchpoint options" value="5584867"/>
<mapEntry key="list watchpoints" value="1750606"/>
<mapEntry key="loadfile" value="836785942"/>
<mapEntry key="list watchpoint options" value="5544195"/>
<mapEntry key="list watchpoints" value="1677850"/>
<mapEntry key="loadfile" value="842545730"/>
<mapEntry key="next" value="35850257"/>
<mapEntry key="query supports threads" value="215433"/>
<mapEntry key="remove" value="5206014"/>
<mapEntry key="run script" value="227735417"/>
<mapEntry key="run script" value="86204027"/>
<mapEntry key="set $pc" value="7542800"/>
<mapEntry key="set CWD" value="8076653"/>
<mapEntry key="set CWD" value="9332544"/>
<mapEntry key="set breakpoint properties" value="3230756"/>
<mapEntry key="set debug-from" value="1737474"/>
<mapEntry key="set substitute-path" value="48794824"/>
<mapEntry key="source use_model_semihosting.ds" value="12517151"/>
<mapEntry key="start" value="87931800"/>
<mapEntry key="set debug-from" value="1463434"/>
<mapEntry key="set substitute-path" value="68584340"/>
<mapEntry key="source use_model_semihosting.ds" value="9119318"/>
<mapEntry key="start" value="94073900"/>
<mapEntry key="step" value="37429909"/>
<mapEntry key="stepi" value="29574773"/>
<mapEntry key="synchronizing trace ranges" value="68477"/>
<mapEntry key="target reset" value="32992642"/>
<mapEntry key="toggleBreakpoint" value="16594048"/>
<mapEntry key="waitForTargetToStop" value="77378589"/>
<mapEntry key="waitForTargetToStop" value="61355123"/>
<mapEntry key="write expression" value="21220700"/>
</mapAttribute>
<listAttribute key="DEBUG_TAB."/>
@@ -94,32 +94,38 @@
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
<intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
<listAttribute key="FILES.DOWNLOAD_AND_DEBUG"/>
<listAttribute key="FILES.DOWNLOAD_AND_DEBUG">
<listEntry value="ON_DEMAND_LOAD"/>
<listEntry value="ALSO_LOAD_SYMBOLS"/>
</listAttribute>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="TARGET_DOWNLOAD_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_DOWNLOAD_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
<intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
<listAttribute key="FILES.DOWNLOAD_DEBUG"/>
<listAttribute key="FILES.DOWNLOAD_DEBUG">
<listEntry value="ON_DEMAND_LOAD"/>
<listEntry value="ALSO_LOAD_SYMBOLS"/>
</listAttribute>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="TARGET_DOWNLOAD_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_DOWNLOAD_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="APP_ON_HOST_TO_DOWNLOAD"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
<intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
<intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
@@ -160,8 +166,16 @@
<intAttribute key="Messages.POST_TRIGGER_CAPTURE_SIZE.getLocalisedValue().FMTrace" value="50"/>
<booleanAttribute key="Messages.STOP_ON_TRIGGER.getLocalisedValue().FMTrace" value="false"/>
<intAttribute key="POST_TRIGGER_CAPTURE_SIZE" value="50"/>
<intAttribute key="POST_TRIGGER_CAPTURE_SIZE.model_streaming_capture_0" value="50"/>
<intAttribute key="POST_TRIGGER_CAPTURE_SIZE.model_streaming_capture_1" value="50"/>
<intAttribute key="POST_TRIGGER_CAPTURE_SIZE.model_streaming_capture_2" value="50"/>
<intAttribute key="POST_TRIGGER_CAPTURE_SIZE.model_streaming_capture_3" value="50"/>
<booleanAttribute key="RSE_USE_HOSTNAME" value="true"/>
<booleanAttribute key="STOP_ON_TRIGGER" value="false"/>
<booleanAttribute key="STOP_ON_TRIGGER.model_streaming_capture_0" value="false"/>
<booleanAttribute key="STOP_ON_TRIGGER.model_streaming_capture_1" value="false"/>
<booleanAttribute key="STOP_ON_TRIGGER.model_streaming_capture_2" value="false"/>
<booleanAttribute key="STOP_ON_TRIGGER.model_streaming_capture_3" value="false"/>
<stringAttribute key="TCP_DISABLE_EXTENDED_MODE" value="true"/>
<booleanAttribute key="TCP_KILL_ON_EXIT" value="false"/>
<listAttribute key="TREE_NODE_PROPERTIES:debugger.view.ExpressionsView">
@@ -331,15 +345,16 @@
<listAttribute key="com.arm.debugger.views.common.AddressTracker.debugger.view.DisassemblyView.ranges">
<listEntry value="100"/>
</listAttribute>
<stringAttribute key="config_db_activity_name" value="Debug Cortex-A35x4 SMP"/>
<stringAttribute key="config_db_connection_keys" value="dtsl_config dtsl_tracecapture_option dtsl_config_script model_params config_file setup TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
<stringAttribute key="config_db_activity_name" value="Cortex-A35x4 SMP"/>
<stringAttribute key="config_db_connection_keys" value="dtsl_config dtsl_tracecapture_option connect_existing_model dtsl_config_script model_params model_iris config_file model_connection_address setup TCP_KILL_ON_EXIT TCP_DISABLE_EXTENDED_MODE"/>
<stringAttribute key="config_db_connection_type" value="Bare Metal Debug"/>
<stringAttribute key="config_db_platform_name" value="Arm FVP - Base_A35x4"/>
<stringAttribute key="config_db_project_type" value="Bare Metal Debug"/>
<stringAttribute key="config_db_project_type_id" value="BARE_METAL"/>
<stringAttribute key="config_db_taxonomy_id" value="/platform/armfvp/base_a35x4"/>
<stringAttribute key="config_file" value="CDB://cadi_config.xml"/>
<stringAttribute key="config_file" value="CDB://iris_config.xml"/>
<booleanAttribute key="connectOnly" value="false"/>
<stringAttribute key="connect_existing_model" value="false"/>
<stringAttribute key="debugger.view.DataView.os:DataView" value="rO0ABXNyACtjb20uYXJtLmRlYnVnLnZpZXdzLmRhdGEuRGF0YVZpZXdQcm9wZXJ0aWVzAAAAAAAAAAECAAB4cgAlY29tLmFybS5kZWJ1Zy52aWV3cy5kYXRhLlByb3BlcnR5VHJlZQAAAAAAAAABAwABTAAFbURhdGF0ABNMamF2YS91dGlsL0hhc2hNYXA7eHB3BAAAAAJ0ABJkYXRhYmFzZVByb3BlcnRpZXNzcQB+AAF3BAAAAAF0AAd0aHJlYWR4c3IAK2NvbS5hcm0uZGVidWcudmlld3MuZGF0YS5EYXRhYmFzZVByb3BlcnRpZXMAAAAAAAAAAQIAAHhxAH4AAXcEAAAAAnQAAmlkcQB+AAZ0AAxjdXJyZW50VGFibGV0AAd0aHJlYWRzeHh0AA9jdXJyZW50RGF0YWJhc2V0AAd0aHJlYWR4eA=="/>
<listAttribute key="debugger.view.DisassemblyView:current">
<listEntry value="&lt;Next Instruction&gt;"/>
@@ -380,7 +395,7 @@
<mapEntry key="6" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
<mapEntry key="7" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
</mapAttribute>
<stringAttribute key="debugger.view.ExpressionsView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;187&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;108&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;57&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;50&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;37&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;150&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;53&#9;-1&#9;true"/>
<stringAttribute key="debugger.view.ExpressionsView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;187&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;108&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;57&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;50&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;37&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;151&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;53&#9;-1&#9;true"/>
<stringAttribute key="debugger.view.MemoryView" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;page&gt;&#10;&#9;&lt;memoryView/&gt;&#10;&lt;/page&gt;&#10;"/>
<listAttribute key="debugger.view.MemoryView:current">
<listEntry value=""/>
@@ -401,8 +416,10 @@
<stringAttribute key="dtsl_config" value="DtslScript"/>
<stringAttribute key="dtsl_config_script" value="CDB://dtsl_config_script.py"/>
<stringAttribute key="dtsl_options_file" value="default"/>
<stringAttribute key="dtsl_tracecapture_option" value="options.traceBuffer.traceCaptureDevice"/>
<stringAttribute key="dtsl_tracecapture_option" value="options.trace.traceCapture"/>
<booleanAttribute key="linuxOS" value="false"/>
<stringAttribute key="model_connection_address" value=""/>
<stringAttribute key="model_iris" value="1"/>
<stringAttribute key="model_params" value="-C bp.secure_memory=false -C cache_state_modelled=0"/>
<stringAttribute key="os_extension_id" value="com.arm.debug.os.threadx"/>
<booleanAttribute key="runAfterConnect" value="false"/>
@@ -410,6 +427,7 @@
<mapAttribute key="scripts_view_script_links">
<mapEntry key="B:\support\broadcom\a53smp_el1_clean_mar25\sample_threadx\use_model_semihosting.ds" value=""/>
<mapEntry key="B:\support\broadcom\tx58cortexa53arm\release\threadx\sample_threadx\use_model_semihosting.ds" value=""/>
<mapEntry key="C:\Users\andrejm\work\git\AzureRTOS\threadx_other\ports_smp\cortex_a35_smp\gnu\example_build\sample_threadx\use_model_semihosting.ds" value=""/>
<mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_smp\cortex_a35_smp\gnu\example_build\sample_threadx\use_model_semihosting.ds" value=""/>
<mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x_smp\gnu\example_build\common\use_model_semihosting.ds" value=""/>
<mapEntry key="D:\Documents\work\get_threadx-smp_cortex-a53_gnu_working\threadx_arm\threadx\common\use_model_semihosting.ds" value=""/>
@@ -419,7 +437,7 @@
</mapAttribute>
<listAttribute key="setup">
<listEntry value="CDB://Scripts/rtsm_launcher.py"/>
<listEntry value="FVP_Base_Cortex-A35x4"/>
<listEntry value="&quot;FVP_Base_Cortex-A35x4&quot;"/>
</listAttribute>
<stringAttribute key="stopAtExpression" value="*$ENTRYPOINT"/>
<stringAttribute key="substitutePath" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;tuplelist&gt;&#10;&#9;&lt;tuple&gt;&#10;&#9;&#9;&lt;ta&gt;/tmp/dgboter/bbs/dsggnu-vm-1-x86_64--mingw32-i686/buildbot/mingw32-i686--aarch64-elf/build/src/newlib-cygwin/libgloss/aarch64/&lt;/ta&gt;&#10;&#9;&#9;&lt;tb&gt;D:\Documents\work\toolchains\newlib-cygwin\libgloss\aarch64\&lt;/tb&gt;&#10;&#9;&lt;/tuple&gt;&#10;&#9;&lt;tuple&gt;&#10;&#9;&#9;&lt;ta&gt;C:/release/threadx/sample_threadx&lt;/ta&gt;&#10;&#9;&#9;&lt;tb&gt;C:\release\threadx\sample_threadx\&lt;/tb&gt;&#10;&#9;&lt;/tuple&gt;&#10;&#9;&lt;tuple&gt;&#10;&#9;&#9;&lt;ta&gt;C:/release/threadx/tx&lt;/ta&gt;&#10;&#9;&#9;&lt;tb&gt;C:\release\threadx\sample_threadx\&lt;/tb&gt;&#10;&#9;&lt;/tuple&gt;&#10;&lt;/tuplelist&gt;&#10;"/>

2
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.c
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------

2
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sp804_timer.h
View File

@@ -4,7 +4,7 @@
//
// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------

10
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/startup.S
View File

@@ -7,7 +7,7 @@
//
// Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------
@@ -326,7 +326,7 @@ el1_entry_aarch64:
//
// Cortex-A processors automatically invalidate their caches on reset
// (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins).
// It is therefore not necessary for software to invalidate the caches
// It is therefore not necessary for software to invalidate the caches
// on startup, however, this is done here in case of a warm reset.
bl InvalidateUDCaches
tlbi VMALLE1
@@ -685,7 +685,7 @@ nol2setup:
bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr
msr SCTLR_EL1, x1
isb
//
// The Arm Architecture Reference Manual for Armv8-A states:
//
@@ -740,7 +740,7 @@ arg0:
bl main
b exit // Will not return
// ------------------------------------------------------------
// EL1 - secondary CPU init code
//
@@ -795,4 +795,4 @@ loop_wfi:
// Branch to thread start
//
//B MainApp

2
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.S
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2018 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------

2
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_system.h
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_utils.S
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
//

2
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/vectors.S
View File

@@ -3,7 +3,7 @@
//
// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
// ------------------------------------------------------------

126
ports_smp/cortex_a35_smp/gnu/example_build/tx/.cproject
View File

@@ -75,6 +75,8 @@
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</tool>
@@ -97,6 +99,8 @@
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@@ -138,98 +142,6 @@
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<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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@@ -239,18 +151,6 @@
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<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.413724976;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.413724976.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1738885767;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.1019453589">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="com.arm.projectSettings" version="6.0.0"/>
@@ -272,5 +172,23 @@
</storageModule>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.413724976;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.413724976.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1738885767;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.1019453589">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674.;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.var.gcc-8.3.0-aarch64-elf.1247168701;com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.tool.c.compiler.input.1073576394">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
</cproject>

48
ports_smp/cortex_a35_smp/gnu/example_build/tx/.settings/language.settings.xml
View File

@@ -1,48 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
<configuration id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.debug.var.gcc-8.3.0-aarch64-elf.794347674" name="Debug">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.arm.managedbuilder.gcc.langsettings.ArmGCCBaremetalLanguageSettingsProvider" console="false" env-hash="-606533458206092714" id="com.arm.managedbuilder.langsettingsprovider.arm.gcc.baremetal" keep-relative-paths="false" name="Arm GCC Built-in Compiler Settings Baremetal" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
</extension>
</configuration>
<configuration id="com.arm.eclipse.cdt.managedbuild.ds5.gcc.baremetal.config.exe.release.var.gcc-8.3.0-aarch64-elf.413724976" name="Release">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.arm.managedbuilder.gcc.langsettings.ArmGCCBaremetalLanguageSettingsProvider" console="false" env-hash="-606533458206092714" id="com.arm.managedbuilder.langsettingsprovider.arm.gcc.baremetal" keep-relative-paths="false" name="Arm GCC Built-in Compiler Settings Baremetal" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
</extension>
</configuration>
</project>

97
ports_smp/cortex_a35_smp/gnu/inc/tx_port.h
View File

@@ -12,7 +12,7 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** */
/** ThreadX Component */
/** */
/** Port Specific */
@@ -21,30 +21,30 @@
/**************************************************************************/
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-A35-SMP/GNU */
/**************************************************************************/
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-A35-SMP/GNU */
/* 6.1.6 */
/* */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This file contains data type definitions that make the ThreadX */
/* real-time kernel function identically on a variety of different */
/* processor architectures. For example, the size or number of bits */
/* in an "int" data type vary between microprocessor architectures and */
/* even C compilers for the same microprocessor. ThreadX does not */
/* directly use native C data types. Instead, ThreadX creates its */
/* own special types that can be mapped to actual data types by this */
/* file to guarantee consistency in the interface and functionality. */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@@ -81,12 +81,12 @@
/* Define ThreadX SMP initialization macro. */
#define TX_PORT_SPECIFIC_PRE_INITIALIZATION
#define TX_PORT_SPECIFIC_PRE_INITIALIZATION
/* Define ThreadX SMP pre-scheduler initialization. */
#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION
#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION
/* Enable the inter-core interrupt logic. */
@@ -127,7 +127,7 @@
#ifdef TX_INCLUDE_USER_DEFINE_FILE
/* Yes, include the user defines in tx_user.h. The defines in this file may
/* Yes, include the user defines in tx_user.h. The defines in this file may
alternately be defined on the command line. */
#include "tx_user.h"
@@ -140,7 +140,7 @@
#include <string.h>
/* Define ThreadX basic types for this port. */
/* Define ThreadX basic types for this port. */
#define VOID void
typedef char CHAR;
@@ -152,7 +152,7 @@ typedef unsigned int ULONG;
typedef unsigned long long ULONG64;
typedef short SHORT;
typedef unsigned short USHORT;
#define ULONG64_DEFINED
/* Override the alignment type to use 64-bit alignment and storage for pointers. */
@@ -188,19 +188,19 @@ typedef unsigned long long ALIGN_TYPE;
#define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */
#endif
#ifndef TX_TIMER_THREAD_PRIORITY
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#ifndef TX_TIMER_THREAD_PRIORITY
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
/* Define various constants for the ThreadX ARM port. */
/* Define various constants for the ThreadX ARM port. */
#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */
#define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
@@ -258,7 +258,7 @@ ULONG _tx_misra_time_stamp_get(VOID);
#endif
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
define is negated, thereby forcing the stack fill which is necessary for the stack checking
@@ -272,11 +272,11 @@ ULONG _tx_misra_time_stamp_get(VOID);
/* Define the TX_THREAD control block extensions for this port. The main reason
for the multiple macros is so that backward compatibility can be maintained with
for the multiple macros is so that backward compatibility can be maintained with
existing ThreadX kernel awareness modules. */
#define TX_THREAD_EXTENSION_0
#define TX_THREAD_EXTENSION_1
#define TX_THREAD_EXTENSION_0
#define TX_THREAD_EXTENSION_1
#define TX_THREAD_EXTENSION_2 ULONG tx_thread_fp_enable;
#define TX_THREAD_EXTENSION_3 VOID *tx_thread_extension_ptr;
@@ -292,11 +292,11 @@ ULONG _tx_misra_time_stamp_get(VOID);
#define TX_TIMER_EXTENSION
/* Define the user extension field of the thread control block. Nothing
/* Define the user extension field of the thread control block. Nothing
additional is needed for this port so it is defined as white space. */
#ifndef TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#endif
@@ -304,8 +304,8 @@ ULONG _tx_misra_time_stamp_get(VOID);
tx_thread_shell_entry, and tx_thread_terminate. */
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_THREAD_CREATE_EXTENSION(thread_ptr)
#define TX_THREAD_DELETE_EXTENSION(thread_ptr)
#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr)
#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr)
@@ -332,8 +332,8 @@ ULONG _tx_misra_time_stamp_get(VOID);
#define TX_TIMER_DELETE_EXTENSION(timer_ptr)
/* Determine if the ARM architecture has the CLZ instruction. This is available on
architectures v5 and above. If available, redefine the macro for calculating the
/* Determine if the ARM architecture has the CLZ instruction. This is available on
architectures v5 and above. If available, redefine the macro for calculating the
lowest bit set. */
#ifndef TX_DISABLE_INLINE
@@ -345,7 +345,7 @@ ULONG _tx_misra_time_stamp_get(VOID);
/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout
can figure out what thread timeout to process. */
#define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_extension_ptr;
@@ -375,14 +375,14 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT
ULONG tx_thread_smp_protect_count;
ULONG tx_thread_smp_protect_pad_0;
ULONG tx_thread_smp_protect_pad_1;
ULONG tx_thread_smp_protect_pad_2;
ULONG tx_thread_smp_protect_pad_3;
ULONG tx_thread_smp_protect_pad_2;
ULONG tx_thread_smp_protect_pad_3;
} TX_THREAD_SMP_PROTECT;
/* Define ThreadX interrupt lockout and restore macros for protection on
access of critical kernel information. The restore interrupt macro must
restore the interrupt posture of the running thread prior to the value
/* Define ThreadX interrupt lockout and restore macros for protection on
access of critical kernel information. The restore interrupt macro must
restore the interrupt posture of the running thread prior to the value
present prior to the disable macro. In most cases, the save area macro
is used to define a local function save area for the disable and restore
macros. */
@@ -420,14 +420,11 @@ VOID tx_thread_fp_disable(VOID);
/* Define the version ID of ThreadX. This may be utilized by the application. */
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35-SMP/GNU Version 6.1.6 *";
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35-SMP/GNU Version 6.1.9 *";
#else
extern CHAR _tx_version_id[];
#endif
#endif

92
ports_smp/cortex_a35_smp/gnu/src/tx_initialize_low_level.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Initialize */
/** */
@@ -21,63 +21,53 @@
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_initialize.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for any low-level processor */
/* initialization, including setting up interrupt vectors, setting */
/* up a periodic timer interrupt source, saving the system stack */
/* pointer for use in ISR processing later, and finding the first */
/* available RAM memory address for tx_application_define. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for any low-level processor */
/* initialization, including setting up interrupt vectors, setting */
/* up a periodic timer interrupt source, saving the system stack */
/* pointer for use in ISR processing later, and finding the first */
/* available RAM memory address for tx_application_define. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* VOID _tx_initialize_low_level(VOID)
{ */
// VOID _tx_initialize_low_level(VOID)
// {
.global _tx_initialize_low_level
.type _tx_initialize_low_level, @function
_tx_initialize_low_level:
@@ -86,7 +76,7 @@ _tx_initialize_low_level:
/* Save the system stack pointer. */
/* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */
// _tx_thread_system_stack_ptr = (VOID_PTR) (sp);
LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr
MOV x1, sp // Pickup SP
@@ -95,7 +85,7 @@ _tx_initialize_low_level:
STR x1, [x0] // Store system stack
/* Save the first available memory address. */
/* _tx_initialize_unused_memory = (VOID_PTR) __top_of_ram; */
// _tx_initialize_unused_memory = (VOID_PTR) __top_of_ram;
LDR x0, =_tx_initialize_unused_memory // Pickup address of unused memory ptr
LDR x1, =__top_of_ram // Pickup unused memory address - A free
@@ -106,7 +96,7 @@ _tx_initialize_low_level:
/* Done, return to caller. */
RET // Return to caller
/* } */
// }
.align 3

163
ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_restore.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -21,64 +21,56 @@
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function restores the interrupt context if it is processing a */
/* nested interrupt. If not, it returns to the interrupt thread if no */
/* preemption is necessary. Otherwise, if preemption is necessary or */
/* if no thread was running, the function returns to the scheduler. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling routine */
/* */
/* CALLED BY */
/* */
/* ISRs Interrupt Service Routines */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function restores the interrupt context if it is processing a */
/* nested interrupt. If not, it returns to the interrupt thread if no */
/* preemption is necessary. Otherwise, if preemption is necessary or */
/* if no thread was running, the function returns to the scheduler. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling routine */
/* */
/* CALLED BY */
/* */
/* ISRs Interrupt Service Routines */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* VOID _tx_thread_context_restore(VOID)
{ */
// VOID _tx_thread_context_restore(VOID)
// {
.global _tx_thread_context_restore
.type _tx_thread_context_restore, @function
_tx_thread_context_restore:
@@ -97,28 +89,35 @@ _tx_thread_context_restore:
/* Pickup the CPU ID. */
MRS x8, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x8, #16, #8 // Isolate cluster ID
#endif
UBFX x8, x8, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x8, #8, #8 // Isolate cluster ID
#endif
UBFX x8, x8, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x8, x8, x2, LSL #2 // Calculate CPU ID
#endif
/* Determine if interrupts are nested. */
/* if (--_tx_thread_system_state)
{ */
// if (--_tx_thread_system_state)
// {
LDR x3, =_tx_thread_system_state // Pickup address of system state var
LDR w2, [x3, x8, LSL #2] // Pickup system state
SUB w2, w2, #1 // Decrement the counter
STR w2, [x3, x8, LSL #2] // Store the counter
STR w2, [x3, x8, LSL #2] // Store the counter
CMP w2, #0 // Was this the first interrupt?
BEQ __tx_thread_not_nested_restore // If so, not a nested restore
/* Interrupts are nested. */
/* Just recover the saved registers and return to the point of
/* Just recover the saved registers and return to the point of
interrupt. */
LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL
@@ -147,13 +146,13 @@ _tx_thread_context_restore:
LDP x29, x30, [sp], #16 // Recover x29, x30
ERET // Return to point of interrupt
/* } */
// }
__tx_thread_not_nested_restore:
/* Determine if a thread was interrupted and no preemption is required. */
/* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
|| (_tx_thread_preempt_disable))
{ */
// else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr)
// || (_tx_thread_preempt_disable))
// {
LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr
LDR x0, [x1, x8, LSL #3] // Pickup actual current thread pointer
@@ -162,7 +161,7 @@ __tx_thread_not_nested_restore:
LDR x3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr
LDR x2, [x3, x8, LSL #3] // Pickup actual execute thread pointer
CMP x0, x2 // Is the same thread highest priority?
BEQ __tx_thread_no_preempt_restore // Same thread in the execute list,
BEQ __tx_thread_no_preempt_restore // Same thread in the execute list,
// no preemption needs to happen
LDR x3, =_tx_thread_smp_protection // Build address to protection structure
LDR w3, [x3, #4] // Pickup the owning core
@@ -179,7 +178,7 @@ __tx_thread_no_preempt_restore:
/* Restore interrupted thread or ISR. */
/* Pickup the saved stack pointer. */
/* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */
// sp = _tx_thread_current_ptr -> tx_thread_stack_ptr;
LDR x4, [x0, #8] // Switch to thread stack pointer
MOV sp, x4 //
@@ -212,14 +211,14 @@ __tx_thread_no_preempt_restore:
LDP x29, x30, [sp], #16 // Recover x29, x30
ERET // Return to point of interrupt
/* }
else
{ */
// }
// else
// {
__tx_thread_preempt_restore:
/* Was the thread being preempted waiting for the lock? */
/* if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
{ */
// if (_tx_thread_smp_protect_wait_counts[this_core] != 0)
// {
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
@@ -227,8 +226,8 @@ __tx_thread_preempt_restore:
BEQ _nobody_waiting_for_lock // Is the core waiting for the lock?
/* Do we not have the lock? This means the ISR never got the inter-core lock. */
/* if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
{ */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core)
// {
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
LDR w3, [x2, #4] // Pickup the owning core
@@ -236,14 +235,14 @@ __tx_thread_preempt_restore:
BEQ _this_core_has_lock // Do we have the lock?
/* We don't have the lock. This core should be in the list. Remove it. */
/* _tx_thread_smp_protect_wait_list_remove(this_core); */
// _tx_thread_smp_protect_wait_list_remove(this_core);
_tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list
B _nobody_waiting_for_lock // Leave
/* }
else
{ */
// }
// else
// {
/* We have the lock. This means the ISR got the inter-core lock, but
never released it because it saw that there was someone waiting.
Note this core is not in the list. */
@@ -251,7 +250,7 @@ __tx_thread_preempt_restore:
_this_core_has_lock:
/* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */
/* _tx_thread_smp_protect_wait_counts[core]--; */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list
LDR w3, [x2, x8, LSL #2] // Load waiting value for this core
@@ -261,7 +260,7 @@ _this_core_has_lock:
/* Now release the inter-core lock. */
/* Set protected core as invalid. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF; */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF;
LDR x2, =_tx_thread_smp_protection // Load address of protection structure
MOV w3, #0xFFFFFFFF // Build invalid value
@@ -269,7 +268,7 @@ _this_core_has_lock:
DMB ISH // Ensure that accesses to shared resource have completed
/* Release protection. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0; */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0;
MOV w3, #0 // Build release protection value
STR w3, [x2, #0] // Release the protection
@@ -281,8 +280,8 @@ _this_core_has_lock:
SEV // Send event to other CPUs
#endif
/* }
} */
// }
// }
_nobody_waiting_for_lock:
@@ -331,27 +330,27 @@ _skip_fp_save:
/* Save the remaining time-slice and disable it. */
/* if (_tx_timer_time_slice)
{ */
// if (_tx_timer_time_slice)
// {
LDR x3, =_tx_timer_time_slice // Pickup time-slice variable address
LDR w2, [x3, x8, LSL #2] // Pickup time-slice
CMP w2, #0 // Is it active?
BEQ __tx_thread_dont_save_ts // No, don't save it
/* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
_tx_timer_time_slice = 0; */
// _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
// _tx_timer_time_slice = 0;
STR w2, [x0, #36] // Save thread's time-slice
MOV w2, #0 // Clear value
STR w2, [x3, x8, LSL #2] // Disable global time-slice flag
/* } */
// }
__tx_thread_dont_save_ts:
/* Clear the current task pointer. */
/* _tx_thread_current_ptr = TX_NULL; */
// _tx_thread_current_ptr = TX_NULL;
MOV x2, #0 // NULL value
STR x2, [x1, x8, LSL #3] // Clear current thread pointer
@@ -363,9 +362,9 @@ __tx_thread_dont_save_ts:
DMB ISH // Ensure that accesses to shared resource have completed
/* Return to the scheduler. */
/* _tx_thread_schedule(); */
// _tx_thread_schedule();
/* } */
// }
__tx_thread_idle_system_restore:
@@ -388,6 +387,4 @@ __tx_thread_idle_system_restore:
#endif
#endif
ERET // Return to scheduler
/* } */
// }

131
ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_save.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -21,70 +21,63 @@
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function saves the context of an executing thread in the */
/* beginning of interrupt processing. The function also ensures that */
/* the system stack is used upon return to the calling ISR. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ISRs */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function saves the context of an executing thread in the */
/* beginning of interrupt processing. The function also ensures that */
/* the system stack is used upon return to the calling ISR. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ISRs */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* VOID _tx_thread_context_save(VOID)
{ */
// VOID _tx_thread_context_save(VOID)
// {
.global _tx_thread_context_save
.type _tx_thread_context_save, @function
_tx_thread_context_save:
/* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked
out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL,
out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL,
and all other registers are intact. */
/* Check for a nested interrupt condition. */
/* if (_tx_thread_system_state++)
{ */
// if (_tx_thread_system_state++)
// {
STP x0, x1, [sp, #-16]! // Save x0, x1
STP x2, x3, [sp, #-16]! // Save x2, x3
@@ -92,10 +85,17 @@ _tx_thread_context_save:
/* Pickup the CPU ID. */
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x2, LSL #2 // Calculate CPU ID
#endif
@@ -149,18 +149,18 @@ _tx_thread_context_save:
RET // Return to ISR
__tx_thread_not_nested_save:
/* } */
// }
/* Otherwise, not nested, check to see if a thread was running. */
/* else if (_tx_thread_current_ptr)
{ */
// else if (_tx_thread_current_ptr)
// {
ADD w2, w2, #1 // Increment the interrupt counter
STR w2, [x3, x1, LSL #2] // Store it back in the variable
LDR x2, =_tx_thread_current_ptr // Pickup address of current thread ptr
LDR x0, [x2, x1, LSL #3] // Pickup current thread pointer
CMP x0, #0 // Is it NULL?
BEQ __tx_thread_idle_system_save // If so, interrupt occurred in
BEQ __tx_thread_idle_system_save // If so, interrupt occurred in
// scheduling loop - nothing needs saving!
/* Save minimal context of interrupted thread. */
@@ -188,20 +188,27 @@ __tx_thread_not_nested_save:
STP x4, x5, [sp, #-16]! // Save SPSR, ELR
/* Save the current stack pointer in the thread's control block. */
/* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */
// _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
MOV x4, sp //
STR x4, [x0, #8] // Save thread stack pointer
/* Switch to the system stack. */
/* sp = _tx_thread_system_stack_ptr; */
// sp = _tx_thread_system_stack_ptr;
LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x2, LSL #2 // Calculate CPU ID
#endif
@@ -218,17 +225,17 @@ __tx_thread_not_nested_save:
LDP x29, x30, [sp], #16 // Recover x29, x30
#endif
RET // Return to caller
RET // Return to caller
/* }
else
{ */
// }
// else
// {
__tx_thread_idle_system_save:
/* Interrupt occurred in the scheduling loop. */
/* Not much to do here, just adjust the stack pointer, and return to IRQ
/* Not much to do here, just adjust the stack pointer, and return to IRQ
processing. */
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
@@ -241,9 +248,7 @@ __tx_thread_idle_system_save:
#endif
ADD sp, sp, #48 // Recover saved registers
RET // Continue IRQ processing
/* }
} */
RET // Continue IRQ processing
// }
// }

68
ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_disable.c
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -29,41 +29,43 @@
#include "tx_thread.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fp_disable Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fp_disable Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function disables the FP for the currently executing thread. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function disables the FP for the currently executing thread. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
VOID _tx_thread_fp_disable(VOID)
@@ -82,14 +84,14 @@ ULONG system_state;
/* Make sure it is not NULL. */
if (thread_ptr != TX_NULL)
{
/* Thread is running... make sure the call is from the thread context. */
if (system_state == 0)
{
/* Yes, now set the FP enable flag to false in the TX_THREAD structure. */
thread_ptr -> tx_thread_fp_enable = TX_FALSE;
}
}
}
}

68
ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_enable.c
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -28,41 +28,43 @@
#include "tx_api.h"
#include "tx_thread.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fp_enable Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fp_enable Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function enabled the FP for the currently executing thread. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function enabled the FP for the currently executing thread. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
VOID _tx_thread_fp_enable(VOID)
@@ -81,14 +83,14 @@ ULONG system_state;
/* Make sure it is not NULL. */
if (thread_ptr != TX_NULL)
{
/* Thread is running... make sure the call is from the thread context. */
if (system_state == 0)
{
/* Yes, now setup the FP enable flag in the TX_THREAD structure. */
thread_ptr -> tx_thread_fp_enable = TX_TRUE;
}
}
}
}

79
ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_control.S
View File

@@ -12,66 +12,59 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
/*#define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for changing the interrupt lockout */
/* posture of the system. */
/* */
/* INPUT */
/* */
/* new_posture New interrupt lockout posture */
/* */
/* OUTPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for changing the interrupt lockout */
/* posture of the system. */
/* */
/* INPUT */
/* */
/* new_posture New interrupt lockout posture */
/* */
/* OUTPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* UINT _tx_thread_interrupt_control(UINT new_posture)
{ */
// UINT _tx_thread_interrupt_control(UINT new_posture)
// {
.global _tx_thread_interrupt_control
.type _tx_thread_interrupt_control, @function
_tx_thread_interrupt_control:
@@ -85,5 +78,5 @@ _tx_thread_interrupt_control:
MSR DAIF, x0 // Set new interrupt posture
MOV x0, x1 // Setup return value
RET // Return to caller
/* } */
// }

78
ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_disable.S
View File

@@ -12,65 +12,58 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for disabling interrupts */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for disabling interrupts */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* UINT _tx_thread_interrupt_disable(void)
{ */
// UINT _tx_thread_interrupt_disable(void)
// {
.global _tx_thread_interrupt_disable
.type _tx_thread_interrupt_disable, @function
_tx_thread_interrupt_disable:
@@ -83,5 +76,4 @@ _tx_thread_interrupt_disable:
MSR DAIFSet, 0x3 // Lockout interrupts
RET // Return to caller
/* } */
// }

76
ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_restore.S
View File

@@ -12,66 +12,59 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for restoring interrupts to the state */
/* returned by a previous _tx_thread_interrupt_disable call. */
/* */
/* INPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* INPUT */
/* */
/* old_posture Old interrupt lockout posture */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* Application Code */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* UINT _tx_thread_interrupt_restore(UINT old_posture)
{ */
// UINT _tx_thread_interrupt_restore(UINT old_posture)
// {
.global _tx_thread_interrupt_restore
.type _tx_thread_interrupt_restore, @function
_tx_thread_interrupt_restore:
@@ -81,5 +74,4 @@ _tx_thread_interrupt_restore:
MSR DAIF, x0 // Setup the old posture
RET // Return to caller
/* } */
// }

49
ports_smp/cortex_a35_smp/gnu/src/tx_thread_schedule.S
View File

@@ -21,25 +21,14 @@
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-A35-SMP/GNU */
/* 6.1 */
/* _tx_thread_schedule Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -73,10 +62,13 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* VOID _tx_thread_schedule(VOID)
{ */
// VOID _tx_thread_schedule(VOID)
// {
.global _tx_thread_schedule
.type _tx_thread_schedule, @function
_tx_thread_schedule:
@@ -88,17 +80,24 @@ _tx_thread_schedule:
/* Pickup the CPU ID. */
MRS x20, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x1, x20, #16, #8 // Isolate cluster ID
#endif
UBFX x20, x20, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x1, x20, #8, #8 // Isolate cluster ID
#endif
UBFX x20, x20, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x20, x20, x1, LSL #2 // Calculate CPU ID
#endif
/* Wait for a thread to execute. */
/* do
{ */
// do
// {
LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr
@@ -119,8 +118,8 @@ _tx_thread_schedule_thread:
BEQ _tx_thread_schedule // Keep looking for a thread
#endif
/* }
while(_tx_thread_execute_ptr == TX_NULL); */
// }
// while(_tx_thread_execute_ptr == TX_NULL);
/* Get the lock for accessing the thread's ready bit. */
@@ -162,7 +161,7 @@ _tx_thread_ready_for_execution:
DMB ISH
/* Setup the current thread pointer. */
/* _tx_thread_current_ptr = _tx_thread_execute_ptr; */
// _tx_thread_current_ptr = _tx_thread_execute_ptr;
LDR x2, =_tx_thread_current_ptr // Pickup address of current thread
STR x0, [x2, x20, LSL #3] // Setup current thread pointer
@@ -190,7 +189,7 @@ _tx_thread_ready_for_execution:
_execute_pointer_did_not_change:
/* Increment the run count for this thread. */
/* _tx_thread_current_ptr -> tx_thread_run_count++; */
// _tx_thread_current_ptr -> tx_thread_run_count++;
LDR w2, [x0, #4] // Pickup run counter
LDR w3, [x0, #36] // Pickup time-slice for this thread
@@ -198,7 +197,7 @@ _execute_pointer_did_not_change:
STR w2, [x0, #4] // Store the new run counter
/* Setup time-slice, if present. */
/* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */
// _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice;
LDR x2, =_tx_timer_time_slice // Pickup address of time slice
// variable
@@ -216,7 +215,7 @@ _execute_pointer_did_not_change:
#endif
/* Switch to the thread's stack. */
/* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */
// sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr;
/* Determine if an interrupt frame or a synchronous task suspension frame
is present. */
@@ -302,6 +301,4 @@ _skip_solicited_fp_restore:
LDP x29, x30, [sp], #16 // Recover x29, x30
MSR DAIF, x4 // Recover DAIF
RET // Return to caller
/* } */
// }

80
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_get.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
@@ -21,69 +21,65 @@
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_get Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_get Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function gets the currently running core number and returns it.*/
/* */
/* INPUT */
/* */
/* DESCRIPTION */
/* */
/* This function gets the currently running core number and returns it.*/
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* Core ID */
/* */
/* CALLS */
/* */
/* */
/* OUTPUT */
/* */
/* Core ID */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_core_get
.type _tx_thread_smp_core_get, @function
_tx_thread_smp_core_get:
MRS x0, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x1, x0, #16, #8 // Isolate cluster ID
#endif
UBFX x0, x0, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x1, x0, #8, #8 // Isolate cluster ID
#endif
UBFX x0, x0, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x0, x0, x1, LSL #2 // Calculate CPU ID
#endif
RET

84
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_preempt.S
View File

@@ -12,78 +12,74 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
#define ICC_SGI1R_EL1 S3_0_C12_C11_5
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_preempt Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_preempt Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function preempts the specified core in situations where the */
/* thread corresponding to this core is no longer ready or when the */
/* core must be used for a higher-priority thread. If the specified is */
/* the current core, this processing is skipped since the will give up */
/* control subsequently on its own. */
/* */
/* INPUT */
/* */
/* core The core to preempt */
/* */
/* OUTPUT */
/* */
/* DESCRIPTION */
/* */
/* This function preempts the specified core in situations where the */
/* thread corresponding to this core is no longer ready or when the */
/* core must be used for a higher-priority thread. If the specified is */
/* the current core, this processing is skipped since the will give up */
/* control subsequently on its own. */
/* */
/* INPUT */
/* */
/* core The core to preempt */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_core_preempt
.type _tx_thread_smp_core_preempt, @function
_tx_thread_smp_core_preempt:
DSB ISH
#ifdef TX_ARMV8_2
MOV x2, #0x1 // Build the target list field
LSL x3, x0, #16 // Build the affinity1 field
ORR x2, x2, x3 // Combine the fields
#else
MOV x2, #0x1 //
LSL x2, x2, x0 // Shift by the core ID
#endif
MSR ICC_SGI1R_EL1, x2 // Issue inter-core interrupt
RET

79
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_state_get.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
@@ -21,56 +21,46 @@
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_state_get Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_state_get Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is gets the current state of the calling core. */
/* */
/* INPUT */
/* */
/* DESCRIPTION */
/* */
/* This function is gets the current state of the calling core. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Components */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* CALLED BY */
/* */
/* ThreadX Components */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_current_state_get
@@ -80,10 +70,17 @@ _tx_thread_smp_current_state_get:
MRS x1, DAIF // Pickup current interrupt posture
MSR DAIFSet, 0x3 // Lockout interrupts
MRS x2, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #16, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #8, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x2, x2, x3, LSL #2 // Calculate CPU ID
#endif
@@ -91,5 +88,3 @@ _tx_thread_smp_current_state_get:
LDR w0, [x3, x2, LSL #2] // Pickup the current system state for this core
MSR DAIF, x1 // Restore interrupt posture
RET

78
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_thread_get.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
@@ -21,56 +21,46 @@
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_thread_get Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_thread_get Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is gets the current thread of the calling core. */
/* */
/* INPUT */
/* */
/* DESCRIPTION */
/* */
/* This function is gets the current thread of the calling core. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Components */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* CALLED BY */
/* */
/* ThreadX Components */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_current_thread_get
@@ -80,10 +70,17 @@ _tx_thread_smp_current_thread_get:
MRS x1, DAIF // Pickup current interrupt posture
MSR DAIFSet, 0x3 // Lockout interrupts
MRS x2, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #16, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #8, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x2, x2, x3, LSL #2 // Calculate CPU ID
#endif
@@ -91,4 +88,3 @@ _tx_thread_smp_current_thread_get:
LDR x0, [x3, x2, LSL #3] // Pickup the current thread pointer for this core
MSR DAIF, x1 // Restore interrupt posture
RET

108
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_initialize_wait.S
View File

@@ -12,67 +12,57 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_initialize_wait Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_initialize_wait Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is the place where additional cores wait until */
/* initialization is complete before they enter the thread scheduling */
/* loop. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* DESCRIPTION */
/* */
/* This function is the place where additional cores wait until */
/* initialization is complete before they enter the thread scheduling */
/* loop. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling loop */
/* */
/* CALLED BY */
/* */
/* Hardware */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* CALLED BY */
/* */
/* Hardware */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_initialize_wait
@@ -86,15 +76,22 @@ _tx_thread_smp_initialize_wait:
/* Pickup the Core ID. */
MRS x2, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #16, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #8, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x2, x2, x3, LSL #2 // Calculate CPU ID
#endif
/* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release
/* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release
flag. */
LDR w1, =0xF0F0F0F0 // Build TX_INITIALIZE_IN_PROGRESS flag
@@ -105,7 +102,7 @@ wait_for_initialize:
BNE wait_for_initialize // Not equal, just spin here
/* Save the system stack pointer for this core. */
LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr
MOV x1, sp // Pickup SP
SUB x1, x1, #15 //
@@ -114,30 +111,29 @@ wait_for_initialize:
/* Pickup the release cores flag. */
LDR x4, =_tx_thread_smp_release_cores_flag // Build address of release cores flag
wait_for_release:
wait_for_release:
LDR w0, [x4, #0] // Pickup the flag
CMP w0, #0 // Is it set?
BEQ wait_for_release // Wait for the flag to be set
/* Core 0 has released this core. */
/* Clear this core's system state variable. */
MOV x0, #0 // Build clear value
STR w0, [x3, x2, LSL #2] // Set the current system state for this core to zero
/* Now wait for core 0 to finish it's initialization. */
core_0_wait_loop:
LDR w0, [x3, #0] // Pickup the current system state for core 0
CMP w0, #0 // Is it 0?
BNE core_0_wait_loop // No, keep waiting for core 0 to finish its initialization
/* Initialization is complete, enter the scheduling loop! */
B _tx_thread_schedule // Enter the scheduling loop for this core
B _tx_thread_schedule // Enter the scheduling loop for this core
RET

72
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_low_level_initialize.S
View File

@@ -12,65 +12,55 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_low_level_initialize Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_low_level_initialize Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function performs low-level initialization of the booting */
/* core. */
/* */
/* INPUT */
/* */
/* number_of_cores Number of cores */
/* */
/* OUTPUT */
/* */
/* DESCRIPTION */
/* */
/* This function performs low-level initialization of the booting */
/* core. */
/* */
/* INPUT */
/* */
/* number_of_cores Number of cores */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_high_level ThreadX high-level init */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_high_level ThreadX high-level init */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_low_level_initialize

185
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protect.S
View File

@@ -12,26 +12,14 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
/**************************************************************************/
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
/* Include macros for modifying the wait list. */
#include "tx_thread_smp_protection_wait_list_macros.h"
@@ -39,43 +27,47 @@
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_protect Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_protect Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function gets protection for running inside the ThreadX */
/* source. This is acomplished by a combination of a test-and-set */
/* flag and periodically disabling interrupts. */
/* */
/* INPUT */
/* */
/* DESCRIPTION */
/* */
/* This function gets protection for running inside the ThreadX */
/* source. This is acomplished by a combination of a test-and-set */
/* flag and periodically disabling interrupts. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* Previous Status Register */
/* */
/* CALLS */
/* */
/* */
/* OUTPUT */
/* */
/* Previous Status Register */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* improved SMP code, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_protect
@@ -90,17 +82,24 @@ _tx_thread_smp_protect:
/* Pickup the CPU ID. */
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x7, LSL #2 // Calculate CPU ID
#endif
/* Do we already have protection? */
/* if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core)
{ */
// if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core)
// {
LDR x2, =_tx_thread_smp_protection // Build address to protection structure
LDR w3, [x2, #4] // Pickup the owning core
@@ -110,7 +109,7 @@ _tx_thread_smp_protect:
/* We already have protection. */
/* Increment the protection count. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */
// _tx_thread_smp_protection.tx_thread_smp_protect_count++;
LDR w3, [x2, #8] // Pickup ownership count
ADD w3, w3, #1 // Increment ownership count
@@ -122,16 +121,16 @@ _tx_thread_smp_protect:
_protection_not_owned:
/* Is the lock available? */
/* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
{ */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
// {
LDAXR w3, [x2, #0] // Pickup the protection flag
CMP w3, #0
BNE _start_waiting // No, protection not available
/* Is the list empty? */
/* if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail)
{ */
// if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail)
// {
LDR x3, =_tx_thread_smp_protect_wait_list_head
LDR w3, [x3]
@@ -141,8 +140,8 @@ _protection_not_owned:
BNE _list_not_empty
/* Try to get the lock. */
/* if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS)
{ */
// if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS)
// {
MOV w3, #1 // Build lock value
STXR w4, w3, [x2, #0] // Attempt to get the protection
@@ -150,7 +149,7 @@ _protection_not_owned:
BNE _start_waiting // Did it fail?
/* We got the lock! */
/* _tx_thread_smp_protect_lock_got(); */
// _tx_thread_smp_protect_lock_got();
DMB ISH // Ensure write to protection finishes
_tx_thread_smp_protect_lock_got // Call the lock got function
@@ -160,8 +159,8 @@ _protection_not_owned:
_list_not_empty:
/* Are we at the front of the list? */
/* if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head])
{ */
// if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head])
// {
LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
LDR w3, [x3] // Get the value of the head
@@ -172,27 +171,29 @@ _list_not_empty:
BNE _start_waiting
/* Is the lock still available? */
/* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
{ */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
// {
LDR w3, [x2, #0] // Pickup the protection flag
LDAXR w3, [x2, #0] // Pickup the protection flag
CMP w3, #0
BNE _start_waiting // No, protection not available
/* Get the lock. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1;
MOV w3, #1 // Build lock value
STR w3, [x2, #0] // Store lock value
STXR w4, w3, [x2, #0] // Attempt to get the protection
CMP w4, #0
BNE _start_waiting // Did it fail?
DMB ISH //
/* Got the lock. */
/* _tx_thread_smp_protect_lock_got(); */
// _tx_thread_smp_protect_lock_got();
_tx_thread_smp_protect_lock_got
/* Remove this core from the wait list. */
/* _tx_thread_smp_protect_remove_from_front_of_list(); */
// _tx_thread_smp_protect_remove_from_front_of_list();
_tx_thread_smp_protect_remove_from_front_of_list
@@ -203,7 +204,7 @@ _start_waiting:
/* For one reason or another, we didn't get the lock. */
/* Increment wait count. */
/* _tx_thread_smp_protect_wait_counts[this_core]++; */
// _tx_thread_smp_protect_wait_counts[this_core]++;
LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts
LDR w4, [x3, x1, LSL #2] // Load waiting value for this core
@@ -211,32 +212,32 @@ _start_waiting:
STR w4, [x3, x1, LSL #2] // Store new wait value
/* Have we not added ourselves to the list yet? */
/* if (_tx_thread_smp_protect_wait_counts[this_core] == 1)
{ */
// if (_tx_thread_smp_protect_wait_counts[this_core] == 1)
// {
CMP w4, #1
BNE _already_in_list0 // Is this core already waiting?
/* Add ourselves to the list. */
/* _tx_thread_smp_protect_wait_list_add(this_core); */
// _tx_thread_smp_protect_wait_list_add(this_core);
_tx_thread_smp_protect_wait_list_add // Call macro to add ourselves to the list
/* } */
// }
_already_in_list0:
/* Restore interrupts. */
MSR DAIF, x0 // Restore interrupts
ISB //
ISB //
#ifdef TX_ENABLE_WFE
WFE // Go into standby
#endif
/* We do this until we have the lock. */
/* while (1)
{ */
// while (1)
// {
_try_to_get_lock:
@@ -248,28 +249,35 @@ _try_to_get_lock:
/* Pickup the CPU ID. */
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x7, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x7, LSL #2 // Calculate CPU ID
#endif
/* Do we already have protection? */
/* if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core)
{ */
// if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core)
// {
LDR w3, [x2, #4] // Pickup the owning core
CMP w3, w1 // Is it this core?
BEQ _got_lock_after_waiting // Yes, the protection is already owned. This means
// an ISR preempted us and got protection
/* } */
// }
/* Are we at the front of the list? */
/* if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head])
{ */
// if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head])
// {
LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
LDR w3, [x3] // Get the value of the head
@@ -280,27 +288,29 @@ _try_to_get_lock:
BNE _did_not_get_lock
/* Is the lock still available? */
/* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
{ */
// if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0)
// {
LDR w3, [x2, #0] // Pickup the protection flag
LDAXR w3, [x2, #0] // Pickup the protection flag
CMP w3, #0
BNE _did_not_get_lock // No, protection not available
/* Get the lock. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; */
// _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1;
MOV w3, #1 // Build lock value
STR w3, [x2, #0] // Store lock value
STXR w4, w3, [x2, #0] // Attempt to get the protection
CMP w4, #0
BNE _did_not_get_lock // Did it fail?
DMB ISH //
/* Got the lock. */
/* _tx_thread_smp_protect_lock_got(); */
// _tx_thread_smp_protect_lock_got();
_tx_thread_smp_protect_lock_got
/* Remove this core from the wait list. */
/* _tx_thread_smp_protect_remove_from_front_of_list(); */
// _tx_thread_smp_protect_remove_from_front_of_list();
_tx_thread_smp_protect_remove_from_front_of_list
@@ -312,8 +322,8 @@ _did_not_get_lock:
/* Were we removed from the list? This can happen if we're a thread
and we got preempted. */
/* if (_tx_thread_smp_protect_wait_counts[this_core] == 0)
{ */
// if (_tx_thread_smp_protect_wait_counts[this_core] == 0)
// {
LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts
LDR w4, [x3, x1, LSL #2] // Load waiting value for this core
@@ -321,26 +331,26 @@ _did_not_get_lock:
BNE _already_in_list1 // Is this core already in the list?
/* Add ourselves to the list. */
/* _tx_thread_smp_protect_wait_list_add(this_core); */
// _tx_thread_smp_protect_wait_list_add(this_core);
_tx_thread_smp_protect_wait_list_add // Call macro to add ourselves to the list
/* Our waiting count was also reset when we were preempted. Increment it again. */
/* _tx_thread_smp_protect_wait_counts[this_core]++; */
// _tx_thread_smp_protect_wait_counts[this_core]++;
LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts
LDR w4, [x3, x1, LSL #2] // Load waiting value for this core
ADD w4, w4, #1 // Increment wait value
STR w4, [x3, x1, LSL #2] // Store new wait value value
/* } */
// }
_already_in_list1:
/* Restore interrupts and try again. */
MSR DAIF, x0 // Restore interrupts
ISB //
ISB //
#ifdef TX_ENABLE_WFE
WFE // Go into standby
#endif
@@ -349,7 +359,7 @@ _already_in_list1:
_got_lock_after_waiting:
/* We're no longer waiting. */
/* _tx_thread_smp_protect_wait_counts[this_core]--; */
// _tx_thread_smp_protect_wait_counts[this_core]--;
LDR x3, =_tx_thread_smp_protect_wait_counts // Load waiting list
LDR w4, [x3, x1, LSL #2] // Load current wait value
@@ -361,4 +371,3 @@ _got_lock_after_waiting:
_return:
RET

116
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h
View File

@@ -23,12 +23,12 @@
.macro _tx_thread_smp_protect_lock_got
/* Set the currently owned core. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; */
// _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core;
STR w1, [x2, #4] // Store this core
/* Increment the protection count. */
/* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */
// _tx_thread_smp_protection.tx_thread_smp_protect_count++;
LDR w3, [x2, #8] // Pickup ownership count
ADD w3, w3, #1 // Increment ownership count
@@ -40,7 +40,7 @@
.macro _tx_thread_smp_protect_remove_from_front_of_list
/* Remove ourselves from the list. */
/* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; */
// _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF;
MOV w3, #0xFFFFFFFF // Build the invalid core value
LDR x4, =_tx_thread_smp_protect_wait_list_head // Get the address of the head
@@ -50,53 +50,55 @@
ADD w5, w5, #1 // Increment the head
/* Did we wrap? */
/* if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1)
{ */
// if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1)
// {
LDR x3, =_tx_thread_smp_protect_wait_list_size // Load address of core list size
LDR w3, [x3] // Load the max cores value
CMP w5, w3 // Compare the head to it
BNE _store_new_head\@ // Are we at the max?
/* _tx_thread_smp_protect_wait_list_head = 0; */
// _tx_thread_smp_protect_wait_list_head = 0;
EOR w5, w5, w5 // We're at the max. Set it to zero
/* } */
// }
_store_new_head\@:
STR w5, [x4] // Store the new head
/* We have the lock! */
/* return; */
DMB ISH // Ensure write to protection finishes
// return;
.endm
.macro _tx_thread_smp_protect_wait_list_lock_get
/* VOID _tx_thread_smp_protect_wait_list_lock_get()
{ */
// VOID _tx_thread_smp_protect_wait_list_lock_get()
// {
/* We do this until we have the lock. */
/* while (1)
{ */
// while (1)
// {
_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
/* Is the list lock available? */
/* _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); */
// Is the list lock available? */
// _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force);
LDR x1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force
LDAXR w2, [x1] // Pickup the protection flag
/* if (protect_in_force == 0)
{ */
// if (protect_in_force == 0)
// {
CMP w2, #0
BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // No, protection not available
/* Try to get the list. */
/* int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); */
// int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1);
MOV w2, #1 // Build lock value
STXR w3, w2, [x1] // Attempt to get the protection
@@ -107,17 +109,17 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // Did it fail? If so, try again.
/* We have the lock! */
/* return; */
// return;
.endm
.macro _tx_thread_smp_protect_wait_list_add
/* VOID _tx_thread_smp_protect_wait_list_add(UINT new_core)
{ */
// VOID _tx_thread_smp_protect_wait_list_add(UINT new_core)
// {
/* We're about to modify the list, so get the list lock. */
/* _tx_thread_smp_protect_wait_list_lock_get(); */
// _tx_thread_smp_protect_wait_list_lock_get();
STP x1, x2, [sp, #-16]! // Save registers we'll be using
@@ -126,7 +128,7 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
LDP x1, x2, [sp], #16
/* Add this core. */
/* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; */
// _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core;
LDR x3, =_tx_thread_smp_protect_wait_list_tail // Get the address of the tail
LDR w4, [x3] // Get the value of tail
@@ -135,64 +137,66 @@ _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@:
ADD w4, w4, #1 // Increment the tail
/* Did we wrap? */
/* if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size)
{ */
// if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size)
// {
LDR x5, =_tx_thread_smp_protect_wait_list_size // Load max cores address
LDR w5, [x5] // Load max cores value
CMP w4, w5 // Compare max cores to tail
BNE _tx_thread_smp_protect_wait_list_add__no_wrap\@ // Did we wrap?
/* _tx_thread_smp_protect_wait_list_tail = 0; */
// _tx_thread_smp_protect_wait_list_tail = 0;
MOV w4, #0
/* } */
// }
_tx_thread_smp_protect_wait_list_add__no_wrap\@:
STR w4, [x3] // Store the new tail value.
DMB ISH // Ensure that accesses to shared resource have completed
/* Release the list lock. */
/* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */
// _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0;
MOV w3, #0 // Build lock value
LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force
STR w3, [x4] // Store the new value
DMB ISH // Ensure write to protection finishes
.endm
.macro _tx_thread_smp_protect_wait_list_remove
/* VOID _tx_thread_smp_protect_wait_list_remove(UINT core)
{ */
// VOID _tx_thread_smp_protect_wait_list_remove(UINT core)
// {
/* Get the core index. */
/* UINT core_index;
for (core_index = 0;; core_index++) */
// UINT core_index;
// for (core_index = 0;; core_index++)
EOR w4, w4, w4 // Clear for 'core_index'
LDR x2, =_tx_thread_smp_protect_wait_list // Get the address of the list
/* { */
// {
_tx_thread_smp_protect_wait_list_remove__check_cur_core\@:
/* Is this the core? */
/* if (_tx_thread_smp_protect_wait_list[core_index] == core)
{
break; */
// if (_tx_thread_smp_protect_wait_list[core_index] == core)
// {
// break;
LDR w3, [x2, x4, LSL #2] // Get the value at the current index
CMP w3, w8 // Did we find the core?
BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@
/* } */
// }
ADD w4, w4, #1 // Increment cur index
B _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ // Restart the loop
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__found_core\@:
@@ -200,15 +204,15 @@ _tx_thread_smp_protect_wait_list_remove__found_core\@:
core could be simultaneously adding (a core is simultaneously trying to get
the inter-core lock) or removing (a core is simultaneously being preempted,
like what is currently happening). */
/* _tx_thread_smp_protect_wait_list_lock_get(); */
// _tx_thread_smp_protect_wait_list_lock_get();
MOV x6, x1
_tx_thread_smp_protect_wait_list_lock_get
MOV x1, x6
/* We remove by shifting. */
/* while (core_index != _tx_thread_smp_protect_wait_list_tail)
{ */
// while (core_index != _tx_thread_smp_protect_wait_list_tail)
// {
_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@:
@@ -217,76 +221,78 @@ _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@:
CMP w4, w2 // Compare cur index and tail
BEQ _tx_thread_smp_protect_wait_list_remove__removed\@
/* UINT next_index = core_index + 1; */
// UINT next_index = core_index + 1;
MOV w2, w4 // Move current index to next index register
ADD w2, w2, #1 // Add 1
/* if (next_index == _tx_thread_smp_protect_wait_list_size)
{ */
// if (next_index == _tx_thread_smp_protect_wait_list_size)
// {
LDR x3, =_tx_thread_smp_protect_wait_list_size
LDR w3, [x3]
CMP w2, w3
BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@
/* next_index = 0; */
// next_index = 0;
MOV w2, #0
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@:
/* list_cores[core_index] = list_cores[next_index]; */
// list_cores[core_index] = list_cores[next_index];
LDR x5, =_tx_thread_smp_protect_wait_list // Get the address of the list
LDR w3, [x5, x2, LSL #2] // Get the value at the next index
STR w3, [x5, x4, LSL #2] // Store the value at the current index
/* core_index = next_index; */
// core_index = next_index;
MOV w4, w2
B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__removed\@:
/* Now update the tail. */
/* if (_tx_thread_smp_protect_wait_list_tail == 0)
{ */
// if (_tx_thread_smp_protect_wait_list_tail == 0)
// {
LDR x5, =_tx_thread_smp_protect_wait_list_tail // Load tail address
LDR w4, [x5] // Load tail value
CMP w4, #0
BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@
/* _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; */
// _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size;
LDR x2, =_tx_thread_smp_protect_wait_list_size
LDR w4, [x2]
/* } */
// }
_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@:
/* _tx_thread_smp_protect_wait_list_tail--; */
// _tx_thread_smp_protect_wait_list_tail--;
SUB w4, w4, #1
STR w4, [x5] // Store new tail value
DMB ISH // Ensure that accesses to shared resource have completed
/* Release the list lock. */
/* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */
// _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0;
MOV w2, #0 // Build lock value
LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force // Load lock address
STR w2, [x4] // Store the new value
DMB ISH // Ensure write to protection finishes
/* We're no longer waiting. Note that this should be zero since, again,
this function is only called when a thread preemption is occurring. */
/* _tx_thread_smp_protect_wait_counts[core]--; */
// _tx_thread_smp_protect_wait_counts[core]--;
LDR x4, =_tx_thread_smp_protect_wait_counts // Load wait list counts
LDR w2, [x4, x8, LSL #2] // Load waiting value
SUB w2, w2, #1 // Subtract 1

75
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_time_get.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
@@ -21,57 +21,46 @@
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_time_get Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_time_get Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function gets the global time value that is used for debug */
/* information and event tracing. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* 32-bit time stamp */
/* */
/* CALLS */
/* */
/* DESCRIPTION */
/* */
/* This function gets the global time value that is used for debug */
/* information and event tracing. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* */
/* OUTPUT */
/* */
/* 32-bit time stamp */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_time_get
@@ -79,5 +68,3 @@
_tx_thread_smp_time_get:
MOV x0, #0 // FIXME: Get timer
RET

84
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_unprotect.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread - Low Level SMP Support */
/** */
@@ -21,59 +21,49 @@
/**************************************************************************/
/*
#define TX_SOURCE_CODE
#define TX_THREAD_SMP_SOURCE_CODE
*/
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_unprotect Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_unprotect Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function releases previously obtained protection. The supplied */
/* previous SR is restored. If the value of _tx_thread_system_state */
/* and _tx_thread_preempt_disable are both zero, then multithreading */
/* is enabled as well. */
/* */
/* INPUT */
/* */
/* Previous Status Register */
/* */
/* OUTPUT */
/* */
/* DESCRIPTION */
/* */
/* This function releases previously obtained protection. The supplied */
/* previous SR is restored. If the value of _tx_thread_system_state */
/* and _tx_thread_preempt_disable are both zero, then multithreading */
/* is enabled as well. */
/* */
/* INPUT */
/* */
/* Previous Status Register */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* */
/* CALLED BY */
/* */
/* ThreadX Source */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect
@@ -82,10 +72,17 @@ _tx_thread_smp_unprotect:
MSR DAIFSet, 0x3 // Lockout interrupts
MRS x1, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #16, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x2, x1, #8, #8 // Isolate cluster ID
#endif
UBFX x1, x1, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x1, x1, x2, LSL #2 // Calculate CPU ID
#endif
@@ -127,4 +124,3 @@ _still_protected:
#endif
MSR DAIF, x0 // Restore interrupt posture
RET

90
ports_smp/cortex_a35_smp/gnu/src/tx_thread_stack_build.S
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -21,69 +21,59 @@
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* DESCRIPTION */
/* */
/* This function builds a stack frame on the supplied thread's stack. */
/* The stack frame results in a fake interrupt return to the supplied */
/* function pointer. */
/* */
/* INPUT */
/* */
/* thread_ptr Pointer to thread control blk */
/* function_ptr Pointer to return function */
/* */
/* OUTPUT */
/* */
/* function pointer. */
/* */
/* INPUT */
/* */
/* thread_ptr Pointer to thread */
/* function_ptr Pointer to entry function */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* */
/* CALLED BY */
/* */
/* _tx_thread_create Create thread service */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
{ */
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
// {
.global _tx_thread_stack_build
.type _tx_thread_stack_build, @function
_tx_thread_stack_build:
/* Build a fake interrupt frame. The form of the fake interrupt stack
on the Cortex-A35 should look like the following after it is built:
/* Build an interrupt frame. On Cortex-A35 it should look like this:
Stack Top: SSPR Initial SSPR
ELR Point of interrupt
x28 Initial value for x28
@@ -129,7 +119,7 @@ _tx_thread_stack_build:
MOV x2, #0 // Build clear value
MOV x3, #0 //
STP x2, x3, [x4, #-16]! // Set backtrace to 0
STP x2, x3, [x4, #-16]! // Set initial x29, x30
STP x2, x3, [x4, #-16]! // Set initial x0, x1
@@ -160,13 +150,11 @@ _tx_thread_stack_build:
STP x2, x3, [x4, #-16]! // Set initial SPSR & ELR
/* Setup stack pointer. */
/* thread_ptr -> tx_thread_stack_ptr = x2; */
// thread_ptr -> tx_thread_stack_ptr = x2;
STR x4, [x0, #8] // Save stack pointer in thread's
MOV x3, #1 // Build ready flag
STR w3, [x0, #260] // Set ready flag
STR w3, [x0, #260] // Set ready flag
RET // Return to caller
/* } */
// }

126
ports_smp/cortex_a35_smp/gnu/src/tx_thread_system_return.S
View File

@@ -12,75 +12,68 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-A35-SMP/ARM */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is target processor specific. It is used to transfer */
/* control from a thread back to the ThreadX system. Only a */
/* minimal context is saved since the compiler assumes temp registers */
/* are going to get slicked by a function call anyway. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling loop */
/* */
/* CALLED BY */
/* */
/* ThreadX components */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function is target processor specific. It is used to transfer */
/* control from a thread back to the ThreadX system. Only a */
/* minimal context is saved since the compiler assumes temp registers */
/* are going to get slicked by a function call anyway. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_thread_schedule Thread scheduling loop */
/* */
/* CALLED BY */
/* */
/* ThreadX components */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* VOID _tx_thread_system_return(VOID)
{ */
// VOID _tx_thread_system_return(VOID)
// {
.global _tx_thread_system_return
.type _tx_thread_system_return, @function
_tx_thread_system_return:
;
; /* Save minimal context on the stack. */
;
/* Save minimal context on the stack. */
MRS x0, DAIF // Pickup DAIF
MSR DAIFSet, 0x3 // Lockout interrupts
STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register)
@@ -90,10 +83,17 @@ _tx_thread_system_return:
STP x25, x26, [sp, #-16]! // Save x25, x26
STP x27, x28, [sp, #-16]! // Save x27, x28
MRS x8, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x8, #16, #8 // Isolate cluster ID
#endif
UBFX x8, x8, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x8, #8, #8 // Isolate cluster ID
#endif
UBFX x8, x8, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x8, x8, x3, LSL #2 // Calculate CPU ID
#endif
@@ -134,8 +134,8 @@ _skip_fp_save:
LDR w1, [x2, x8, LSL #2] // Pickup current time slice
/* Save current stack and switch to system stack. */
/* _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; */
/* sp = _tx_thread_system_stack_ptr[core]; */
// _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp;
// sp = _tx_thread_system_stack_ptr[core];
MOV x4, sp //
STR x4, [x6, #8] // Save thread stack pointer
@@ -144,36 +144,36 @@ _skip_fp_save:
MOV sp, x4 // Setup system stack pointer
/* Determine if the time-slice is active. */
/* if (_tx_timer_time_slice[core])
{ */
// if (_tx_timer_time_slice[core])
// {
MOV x4, #0 // Build clear value
CMP w1, #0 // Is a time-slice active?
BEQ __tx_thread_dont_save_ts // No, don't save the time-slice
/* Save the current remaining time-slice. */
/* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
_tx_timer_time_slice = 0; */
// _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
// _tx_timer_time_slice = 0;
STR w4, [x2, x8, LSL #2] // Clear time-slice
STR w1, [x6, #36] // Store current time-slice
/* } */
// }
__tx_thread_dont_save_ts:
/* Clear the current thread pointer. */
/* _tx_thread_current_ptr = TX_NULL; */
// _tx_thread_current_ptr = TX_NULL;
STR x4, [x5, x8, LSL #3] // Clear current thread pointer
/* Set ready bit in thread control block. */
MOV x3, #1 // Build ready value
STR w3, [x6, #260] // Make the thread ready
DMB ISH //
STR w3, [x6, #260] // Make the thread ready
DMB ISH //
/* Now clear protection. It is assumed that protection is in force whenever this routine is called. */
LDR x3, =_tx_thread_smp_protection // Pickup address of protection structure
LDR x1, =_tx_thread_preempt_disable // Build address to preempt disable flag
STR w4, [x1, #0] // Clear preempt disable flag
@@ -186,6 +186,4 @@ __tx_thread_dont_save_ts:
SEV // Send event to other CPUs, wakes anyone waiting on a mutex (using WFE)
B _tx_thread_schedule // Jump to scheduler!
/* } */
// }

81
ports_smp/cortex_a35_smp/gnu/src/tx_thread_timeout.c
View File

@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
@@ -30,48 +30,50 @@
#include "tx_timer.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_timeout Cortex-A35-SMP */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_timeout Cortex-A35-SMP */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function handles thread timeout processing. Timeouts occur in */
/* two flavors, namely the thread sleep timeout and all other service */
/* call timeouts. Thread sleep timeouts are processed locally, while */
/* the others are processed by the appropriate suspension clean-up */
/* service. */
/* */
/* INPUT */
/* */
/* timeout_input Contains the thread pointer */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* Suspension Cleanup Functions */
/* _tx_thread_system_resume Resume thread */
/* _tx_thread_system_ni_resume Non-interruptable resume thread */
/* */
/* CALLED BY */
/* */
/* _tx_timer_expiration_process Timer expiration function */
/* _tx_timer_thread_entry Timer thread function */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function handles thread timeout processing. Timeouts occur in */
/* two flavors, namely the thread sleep timeout and all other service */
/* call timeouts. Thread sleep timeouts are processed locally, while */
/* the others are processed by the appropriate suspension clean-up */
/* service. */
/* */
/* INPUT */
/* */
/* timeout_input Contains the thread pointer */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* Suspension Cleanup Functions */
/* _tx_thread_system_resume Resume thread */
/* _tx_thread_system_ni_resume Non-interruptable resume thread */
/* */
/* CALLED BY */
/* */
/* _tx_timer_expiration_process Timer expiration function */
/* _tx_timer_thread_entry Timer thread function */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
VOID _tx_thread_timeout(ULONG timeout_input)
@@ -79,7 +81,7 @@ VOID _tx_thread_timeout(ULONG timeout_input)
TX_INTERRUPT_SAVE_AREA
TX_THREAD *thread_ptr;
TX_THREAD *thread_ptr;
VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence);
ULONG suspension_sequence;
@@ -126,7 +128,7 @@ ULONG suspension_sequence;
/* Increment the number of timeouts for this thread. */
thread_ptr -> tx_thread_performance_timeout_count++;
#endif
/* Pickup the cleanup routine address. */
suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup;
@@ -162,4 +164,3 @@ ULONG suspension_sequence;
#endif
}
}

133
ports_smp/cortex_a35_smp/gnu/src/tx_timer_interrupt.S
View File

@@ -12,80 +12,79 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Timer */
/** */
/**************************************************************************/
/**************************************************************************/
/* #define TX_SOURCE_CODE */
/* Include necessary system files. */
/*
#include "tx_api.h"
#include "tx_timer.h"
#include "tx_thread.h"
*/
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-A35-SMP/GNU */
/* 6.1 */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function processes the hardware timer interrupt. This */
/* processing includes incrementing the system clock and checking for */
/* time slice and/or timer expiration. If either is found, the */
/* interrupt context save/restore functions are called along with the */
/* expiration functions. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_timer_expiration_process Timer expiration processing */
/* _tx_thread_time_slice Time slice interrupted thread */
/* */
/* CALLED BY */
/* */
/* interrupt vector */
/* */
/* RELEASE HISTORY */
/* */
/* DESCRIPTION */
/* */
/* This function processes the hardware timer interrupt. This */
/* processing includes incrementing the system clock and checking for */
/* time slice and/or timer expiration. If either is found, the */
/* interrupt context save/restore functions are called along with the */
/* expiration functions. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_timer_expiration_process Timer expiration processing */
/* _tx_thread_time_slice Time slice interrupted thread */
/* */
/* CALLED BY */
/* */
/* interrupt vector */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Yuxin Zhou Modified comment(s), */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
/* VOID _tx_timer_interrupt(VOID)
{ */
// VOID _tx_timer_interrupt(VOID)
// {
.global _tx_timer_interrupt
.type _tx_timer_interrupt, @function
_tx_timer_interrupt:
MRS x2, MPIDR_EL1 // Pickup the core ID
#ifdef TX_ARMV8_2
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #16, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #8, #8 // Isolate core ID
#else
#if TX_THREAD_SMP_CLUSTERS > 1
UBFX x3, x2, #8, #8 // Isolate cluster ID
#endif
UBFX x2, x2, #0, #8 // Isolate core ID
#endif
#if TX_THREAD_SMP_CLUSTERS > 1
ADDS x2, x2, x3, LSL #2 // Calculate CPU ID
#endif
@@ -107,7 +106,7 @@ __tx_process_timer:
MOV x28, x0 // Save the return value in preserved register
/* Increment the system clock. */
/* _tx_timer_system_clock++; */
// _tx_timer_system_clock++;
LDR x1, =_tx_timer_system_clock // Pickup address of system clock
LDR w0, [x1, #0] // Pickup system clock
@@ -115,8 +114,8 @@ __tx_process_timer:
STR w0, [x1, #0] // Store new system clock
/* Test for timer expiration. */
/* if (*_tx_timer_current_ptr)
{ */
// if (*_tx_timer_current_ptr)
// {
LDR x1, =_tx_timer_current_ptr // Pickup current timer pointer addr
LDR x0, [x1, #0] // Pickup current timer
@@ -125,25 +124,25 @@ __tx_process_timer:
BEQ __tx_timer_no_timer // No, just increment the timer
/* Set expiration flag. */
/* _tx_timer_expired = TX_TRUE; */
// _tx_timer_expired = TX_TRUE;
LDR x3, =_tx_timer_expired // Pickup expiration flag address
MOV w2, #1 // Build expired value
STR w2, [x3, #0] // Set expired flag
B __tx_timer_done // Finished timer processing
/* }
else
{ */
// }
// else
// {
__tx_timer_no_timer:
/* No timer expired, increment the timer pointer. */
/* _tx_timer_current_ptr++; */
// _tx_timer_current_ptr++;
ADD x0, x0, #8 // Move to next timer
/* Check for wrap-around. */
/* if (_tx_timer_current_ptr == _tx_timer_list_end) */
// if (_tx_timer_current_ptr == _tx_timer_list_end)
LDR x3, =_tx_timer_list_end // Pickup addr of timer list end
LDR x2, [x3, #0] // Pickup list end
@@ -151,7 +150,7 @@ __tx_timer_no_timer:
BNE __tx_timer_skip_wrap // No, skip wrap-around logic
/* Wrap to beginning of list. */
/* _tx_timer_current_ptr = _tx_timer_list_start; */
// _tx_timer_current_ptr = _tx_timer_list_start;
LDR x3, =_tx_timer_list_start // Pickup addr of timer list start
LDR x0, [x3, #0] // Set current pointer to list start
@@ -159,13 +158,13 @@ __tx_timer_no_timer:
__tx_timer_skip_wrap:
STR x0, [x1, #0] // Store new current timer pointer
/* } */
// }
__tx_timer_done:
/* Did a timer expire? */
/* if (_tx_timer_expired)
{ */
// if (_tx_timer_expired)
// {
LDR x1, =_tx_timer_expired // Pickup addr of expired flag
LDR w0, [x1, #0] // Pickup timer expired flag
@@ -173,26 +172,24 @@ __tx_timer_done:
BEQ __tx_timer_dont_activate // If not set, skip timer activation
/* Process timer expiration. */
/* _tx_timer_expiration_process(); */
// _tx_timer_expiration_process();
BL _tx_timer_expiration_process // Call the timer expiration handling routine
/* } */
// }
__tx_timer_dont_activate:
/* Call time-slice processing. */
/* _tx_thread_time_slice(); */
// _tx_thread_time_slice();
BL _tx_thread_time_slice // Call time-slice processing
/* Release inter-core protection. */
MOV x0, x28 // Pass the previous status register back
MOV x0, x28 // Pass the previous status register back
BL _tx_thread_smp_unprotect // Release protection
LDP x29, x30, [sp], #16 // Recover x29, x30
LDP x27, x28, [sp], #16 // Recover x27, x28
RET // Return to caller
/* } */
// }