Release 6.1.5

common/inc/tx_api.h

@@ -26,7 +26,7 @@
 /*  APPLICATION INTERFACE DEFINITION                       RELEASE        */
 /*                                                                        */
 /*    tx_api.h                                            PORTABLE C      */
-/*                                                           6.1.3        */
+/*                                                           6.1.5        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    William E. Lamie, Microsoft Corporation                             */
@@ -61,6 +61,11 @@
 /*  12-31-2020      William E. Lamie        Modified comment(s), and      */
 /*                                            increased patch version,    */
 /*                                            resulting in version 6.1.3  */
+/*  03-02-2021      Scott Larson            Modified comment(s), and      */
+/*                                            order defines numerically,  */
+/*                                            add option to remove FileX  */
+/*                                            pointer,                    */
+/*                                            resulting in version 6.1.5  */
 /*                                                                        */
 /**************************************************************************/
 
@@ -93,7 +98,7 @@ extern   "C" {
 #define AZURE_RTOS_THREADX
 #define THREADX_MAJOR_VERSION           6
 #define THREADX_MINOR_VERSION           1
-#define THREADX_PATCH_VERSION           3
+#define THREADX_PATCH_VERSION           5
 
 /* Define the following symbol for backward compatibility */
 #define EL_PRODUCT_THREADX
@@ -154,7 +159,6 @@ extern   "C" {
 
 #define TX_SUCCESS                      ((UINT) 0x00)
 #define TX_DELETED                      ((UINT) 0x01)
-#define TX_NO_MEMORY                    ((UINT) 0x10)
 #define TX_POOL_ERROR                   ((UINT) 0x02)
 #define TX_PTR_ERROR                    ((UINT) 0x03)
 #define TX_WAIT_ERROR                   ((UINT) 0x04)
@@ -169,6 +173,7 @@ extern   "C" {
 #define TX_NO_INSTANCE                  ((UINT) 0x0D)
 #define TX_THREAD_ERROR                 ((UINT) 0x0E)
 #define TX_PRIORITY_ERROR               ((UINT) 0x0F)
+#define TX_NO_MEMORY                    ((UINT) 0x10)
 #define TX_START_ERROR                  ((UINT) 0x10)
 #define TX_DELETE_ERROR                 ((UINT) 0x11)
 #define TX_RESUME_ERROR                 ((UINT) 0x12)
@@ -422,7 +427,9 @@ typedef struct TX_THREAD_STRUCT
     TX_THREAD_EXTENSION_2
 
     /* Define a pointer type for FileX extensions.  */
+#ifndef TX_NO_FILEX_POINTER
     VOID                *tx_thread_filex_ptr;
+#endif
     
     /* Define the priority inheritance variables. These will be used
        to manage priority inheritance changes applied to this thread 
@@ -1092,7 +1099,6 @@ UINT    _tx_trace_interrupt_control(UINT new_posture);
 
 #ifdef TX_ENABLE_MULTI_ERROR_CHECKING
 
-
 /* Services with MULTI runtime error checking ThreadX.  */
 
 #define tx_block_allocate                           _txr_block_allocate
@@ -1790,7 +1796,6 @@ VOID                    _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL *inte
 VOID                    _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, VOID **highest_stack);
 VOID                    _tx_misra_trace_event_insert(ULONG event_id, VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4, ULONG filter, ULONG time_stamp);
 UINT                    _tx_misra_always_true(void);
-
 UCHAR                   **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **pointer);
 UCHAR                   **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer);
 UCHAR                   *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool);
@@ -1823,7 +1828,6 @@ VOID                    _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore
 VOID                    _tx_misra_thread_not_used(TX_THREAD *thread_ptr);
 VOID                    _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id));
 
-
 #define TX_MEMSET(a,b,c)                                _tx_misra_memset((a), (UINT) (b), (UINT) (c))
 #define TX_UCHAR_POINTER_ADD(a,b)                       _tx_misra_uchar_pointer_add((UCHAR *) (a), (ULONG) (b))
 #define TX_UCHAR_POINTER_SUB(a,b)                       _tx_misra_uchar_pointer_sub((UCHAR *) (a), (ULONG) (b))
@@ -1842,8 +1846,6 @@ VOID                    _tx_misra_thread_entry_exit_notify_not_used(VOID (*threa
 #define TX_TRACE_IN_LINE_INSERT(i,a,b,c,d,e)            _tx_misra_trace_event_insert((ULONG) (i), (VOID *) (a), (ULONG) (b), (ULONG) (c), (ULONG) (d), (ULONG) (e), ((ULONG) TX_TRACE_TIME_SOURCE));
 #endif
 #define TX_LOOP_FOREVER                                 (_tx_misra_always_true() == TX_TRUE)
-
-
 #define TX_INDIRECT_VOID_TO_UCHAR_POINTER_CONVERT(a)    _tx_misra_indirect_void_to_uchar_pointer_convert((a))
 #define TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(a)   _tx_misra_uchar_to_indirect_uchar_pointer_convert((a))
 #define TX_BLOCK_POOL_TO_UCHAR_POINTER_CONVERT(a)       _tx_misra_block_pool_to_uchar_pointer_convert((a))
@@ -1879,7 +1881,6 @@ VOID                    _tx_misra_thread_entry_exit_notify_not_used(VOID (*threa
 #define TX_THREAD_NOT_USED(a)                           _tx_misra_thread_not_used((a))
 #define TX_THREAD_ENTRY_EXIT_NOTIFY_NOT_USED(a)         _tx_misra_thread_entry_exit_notify_not_used((a))
 
-
 #else
 
 /* Define the TX_MEMSET macro to the standard library function, if not already defined.  */
@@ -1908,8 +1909,6 @@ VOID                    _tx_misra_thread_entry_exit_notify_not_used(VOID (*threa
                                                             (b) =  (TX_TIMER *) working_ptr; \
                                                         }
 #define TX_LOOP_FOREVER                                 ((UINT) 1)
-
-
 #define TX_INDIRECT_VOID_TO_UCHAR_POINTER_CONVERT(a)    ((UCHAR **) ((VOID *) (a)))
 #define TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(a)   ((UCHAR **) ((VOID *) (a)))
 #define TX_BLOCK_POOL_TO_UCHAR_POINTER_CONVERT(a)       ((UCHAR *) ((VOID *) (a)))

common/inc/tx_user_sample.h

@@ -26,7 +26,7 @@
 /*  PORT SPECIFIC C INFORMATION                            RELEASE        */
 /*                                                                        */
 /*    tx_user.h                                           PORTABLE C      */
-/*                                                           6.1          */
+/*                                                           6.1.5        */
 /*                                                                        */
 /*  AUTHOR                                                                */
 /*                                                                        */
@@ -47,6 +47,10 @@
 /*  05-19-2020      William E. Lamie        Initial Version 6.0           */
 /*  09-30-2020      Yuxin Zhou              Modified comment(s),          */
 /*                                            resulting in version 6.1    */
+/*  03-02-2021      Scott Larson            Modified comment(s),          */
+/*                                            added option to remove      */
+/*                                            FileX pointer,              */
+/*                                            resulting in version 6.1.5  */
 /*                                                                        */
 /**************************************************************************/
 
@@ -76,6 +80,7 @@
         TX_DISABLE_PREEMPTION_THRESHOLD
         TX_DISABLE_REDUNDANT_CLEARING
         TX_DISABLE_NOTIFY_CALLBACKS
+        TX_NO_FILEX_POINTER
         TX_NOT_INTERRUPTABLE
         TX_TIMER_PROCESS_IN_ISR
    
@@ -98,6 +103,16 @@
 #define TX_TIMER_THREAD_PRIORITY                ????
 */
 
+/* Determine if there is a FileX pointer in the thread control block.
+   By default, the pointer is there for legacy/backwards compatibility. 
+   The pointer must also be there for applications using FileX.
+   Define this to save space in the thread control block. 
+*/
+
+/*
+#define TX_NO_FILEX_POINTER
+*/
+
 /* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls 
    should be processed within the a system timer thread or directly in the timer ISR. 
    By default, the timer thread is used. When the following is defined, the timer expiration 

common_modules/module_manager/src/txm_module_manager_stop.c

@@ -60,7 +60,7 @@ extern UINT  _txm_module_manager_usbx_stop(TXM_MODULE_INSTANCE *module_instance)
 /*  FUNCTION                                               RELEASE        */
 /*                                                                        */
 /*    _txm_module_manager_stop                            PORTABLE C      */
-/*                                                           6.1          */
+/*                                                           6.1.5        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    Scott Larson, Microsoft Corporation                                 */
@@ -109,6 +109,9 @@ extern UINT  _txm_module_manager_usbx_stop(TXM_MODULE_INSTANCE *module_instance)
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
 /*  09-30-2020      Scott Larson            Initial Version 6.1           */
+/*  03-02-2021      Scott Larson            Modified comments, fix        */
+/*                                            object delete underflow,    */
+/*                                            resulting in version 6.1.5  */
 /*                                                                        */
 /**************************************************************************/
 UINT  _txm_module_manager_stop(TXM_MODULE_INSTANCE *module_instance)
@@ -531,9 +534,8 @@ TXM_MODULE_ALLOCATED_OBJECT     *object_ptr;
 #endif
 
     /* Delete the allocated objects for this module.  */
-    while (module_instance -> txm_module_instance_object_list_count--)
+    while (module_instance -> txm_module_instance_object_list_count != 0)
     {
-
         /* Pickup the current object pointer.  */
         object_ptr =  module_instance -> txm_module_instance_object_list_head;
 
@@ -542,6 +544,9 @@ TXM_MODULE_ALLOCATED_OBJECT     *object_ptr;
 
         /* Release the object.  */
         _tx_byte_release((VOID *) object_ptr);
+
+        /* Decrement count.  */
+        module_instance -> txm_module_instance_object_list_count--;
     }
 
     /* Set the allocated list head pointer to NULL.  */

common_smp/inc/tx_api.h

@@ -26,7 +26,7 @@
 /*  APPLICATION INTERFACE DEFINITION                       RELEASE        */
 /*                                                                        */
 /*    tx_api.h                                            PORTABLE SMP    */
-/*                                                           6.1.3        */
+/*                                                           6.1.5        */
 /*  AUTHOR                                                                */
 /*                                                                        */
 /*    William E. Lamie, Microsoft Corporation                             */
@@ -50,6 +50,11 @@
 /*  12-31-2020      William E. Lamie        Modified comment(s), and      */
 /*                                            increased patch version,    */
 /*                                            resulting in version 6.1.3  */
+/*  03-02-2021      Scott Larson            Modified comment(s), and      */
+/*                                            order defines numerically,  */
+/*                                            add option to remove FileX  */
+/*                                            pointer, fix whitespace,    */
+/*                                            resulting in version 6.1.5  */
 /*                                                                        */
 /**************************************************************************/
 
@@ -89,7 +94,7 @@ extern   "C" {
 #define AZURE_RTOS_THREADX
 #define THREADX_MAJOR_VERSION           6
 #define THREADX_MINOR_VERSION           1
-#define THREADX_PATCH_VERSION           3
+#define THREADX_PATCH_VERSION           5
 
 /* Define the following symbol for backward compatibility */
 #define EL_PRODUCT_THREADX
@@ -150,7 +155,6 @@ extern   "C" {
 
 #define TX_SUCCESS                      ((UINT) 0x00)
 #define TX_DELETED                      ((UINT) 0x01)
-#define TX_NO_MEMORY                    ((UINT) 0x10)
 #define TX_POOL_ERROR                   ((UINT) 0x02)
 #define TX_PTR_ERROR                    ((UINT) 0x03)
 #define TX_WAIT_ERROR                   ((UINT) 0x04)
@@ -165,6 +169,7 @@ extern   "C" {
 #define TX_NO_INSTANCE                  ((UINT) 0x0D)
 #define TX_THREAD_ERROR                 ((UINT) 0x0E)
 #define TX_PRIORITY_ERROR               ((UINT) 0x0F)
+#define TX_NO_MEMORY                    ((UINT) 0x10)
 #define TX_START_ERROR                  ((UINT) 0x10)
 #define TX_DELETE_ERROR                 ((UINT) 0x11)
 #define TX_RESUME_ERROR                 ((UINT) 0x12)
@@ -449,7 +454,9 @@ typedef struct TX_THREAD_STRUCT
     /************* End of ThreadX SMP thread control block extensions.  *************/
 
     /* Define a pointer type for FileX extensions.  */
+#ifndef TX_NO_FILEX_POINTER
     VOID                *tx_thread_filex_ptr;
+#endif
     
     /* Define the priority inheritance variables. These will be used
        to manage priority inheritance changes applied to this thread 
@@ -1184,7 +1191,6 @@ UINT    _tx_el_interrupt_control(UINT new_posture);
 
 #ifdef TX_ENABLE_MULTI_ERROR_CHECKING
 
-
 /* Services with MULTI runtime error checking ThreadX.  */
 
 #define tx_block_allocate                           _txr_block_allocate
@@ -1742,7 +1748,6 @@ UINT        _tx_trace_user_event_insert(ULONG event_id, ULONG info_field_1, ULON
 UINT        _tx_trace_interrupt_control(UINT new_posture);
 
 
-
 /* Add a default macro that can be re-defined in tx_port.h to add default processing when a thread starts. Common usage
    would be for enabling floating point for a thread by default, however, the additional processing could be anything
    defined in tx_port.h.  */

common_smp/inc/tx_user_sample.h

@@ -26,7 +26,7 @@
 /*  PORT SPECIFIC C INFORMATION                            RELEASE        */
 /*                                                                        */
 /*    tx_user.h                                           PORTABLE C      */
-/*                                                           6.1          */
+/*                                                           6.1.5        */
 /*                                                                        */
 /*  AUTHOR                                                                */
 /*                                                                        */
@@ -45,6 +45,10 @@
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
 /*  09-30-2020      William E. Lamie        Initial Version 6.1           */
+/*  03-02-2021      Scott Larson            Modified comment(s),          */
+/*                                            added option to remove      */
+/*                                            FileX pointer,              */
+/*                                            resulting in version 6.1.5  */
 /*                                                                        */
 /**************************************************************************/
 
@@ -74,6 +78,7 @@
         TX_DISABLE_PREEMPTION_THRESHOLD
         TX_DISABLE_REDUNDANT_CLEARING
         TX_DISABLE_NOTIFY_CALLBACKS
+        TX_NO_FILEX_POINTER
         TX_NOT_INTERRUPTABLE
         TX_TIMER_PROCESS_IN_ISR
    
@@ -96,6 +101,16 @@
 #define TX_TIMER_THREAD_PRIORITY                ????
 */
 
+/* Determine if there is a FileX pointer in the thread control block.
+   By default, the pointer is there for legacy/backwards compatibility. 
+   The pointer must also be there for applications using FileX.
+   Define this to save space in the thread control block. 
+*/
+
+/*
+#define TX_NO_FILEX_POINTER
+*/
+
 /* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls 
    should be processed within the a system timer thread or directly in the timer ISR. 
    By default, the timer thread is used. When the following is defined, the timer expiration 
@@ -153,7 +168,7 @@
    processing when not needed. The user will also have to comment out the call to 
    tx_timer_interrupt, which is typically made from assembly language in 
    tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR
-   must also be used.  */
+   must also be used and tx_timer_initialize must be removed from ThreadX library.  */
 
 /*
 #define TX_NO_TIMER

ports/c667x/ccs/example_build/tx/Release/makefile

@@ -0,0 +1,351 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+SHELL = cmd.exe
+
+CG_TOOL_ROOT := C:/ti/ccsv8/tools/compiler/ti-cgt-c6000_8.2.4
+
+GEN_OPTS__FLAG := 
+GEN_CMDS__FLAG := 
+
+ORDERED_OBJS += \
+"./tx_block_allocate.obj" \
+"./tx_block_pool_cleanup.obj" \
+"./tx_block_pool_create.obj" \
+"./tx_block_pool_delete.obj" \
+"./tx_block_pool_info_get.obj" \
+"./tx_block_pool_initialize.obj" \
+"./tx_block_pool_performance_info_get.obj" \
+"./tx_block_pool_performance_system_info_get.obj" \
+"./tx_block_pool_prioritize.obj" \
+"./tx_block_release.obj" \
+"./tx_byte_allocate.obj" \
+"./tx_byte_pool_cleanup.obj" \
+"./tx_byte_pool_create.obj" \
+"./tx_byte_pool_delete.obj" \
+"./tx_byte_pool_info_get.obj" \
+"./tx_byte_pool_initialize.obj" \
+"./tx_byte_pool_performance_info_get.obj" \
+"./tx_byte_pool_performance_system_info_get.obj" \
+"./tx_byte_pool_prioritize.obj" \
+"./tx_byte_pool_search.obj" \
+"./tx_byte_release.obj" \
+"./tx_event_flags_cleanup.obj" \
+"./tx_event_flags_create.obj" \
+"./tx_event_flags_delete.obj" \
+"./tx_event_flags_get.obj" \
+"./tx_event_flags_info_get.obj" \
+"./tx_event_flags_initialize.obj" \
+"./tx_event_flags_performance_info_get.obj" \
+"./tx_event_flags_performance_system_info_get.obj" \
+"./tx_event_flags_set.obj" \
+"./tx_event_flags_set_notify.obj" \
+"./tx_initialize_high_level.obj" \
+"./tx_initialize_kernel_enter.obj" \
+"./tx_initialize_kernel_setup.obj" \
+"./tx_mutex_cleanup.obj" \
+"./tx_mutex_create.obj" \
+"./tx_mutex_delete.obj" \
+"./tx_mutex_get.obj" \
+"./tx_mutex_info_get.obj" \
+"./tx_mutex_initialize.obj" \
+"./tx_mutex_performance_info_get.obj" \
+"./tx_mutex_performance_system_info_get.obj" \
+"./tx_mutex_prioritize.obj" \
+"./tx_mutex_priority_change.obj" \
+"./tx_mutex_put.obj" \
+"./tx_queue_cleanup.obj" \
+"./tx_queue_create.obj" \
+"./tx_queue_delete.obj" \
+"./tx_queue_flush.obj" \
+"./tx_queue_front_send.obj" \
+"./tx_queue_info_get.obj" \
+"./tx_queue_initialize.obj" \
+"./tx_queue_performance_info_get.obj" \
+"./tx_queue_performance_system_info_get.obj" \
+"./tx_queue_prioritize.obj" \
+"./tx_queue_receive.obj" \
+"./tx_queue_send.obj" \
+"./tx_queue_send_notify.obj" \
+"./tx_semaphore_ceiling_put.obj" \
+"./tx_semaphore_cleanup.obj" \
+"./tx_semaphore_create.obj" \
+"./tx_semaphore_delete.obj" \
+"./tx_semaphore_get.obj" \
+"./tx_semaphore_info_get.obj" \
+"./tx_semaphore_initialize.obj" \
+"./tx_semaphore_performance_info_get.obj" \
+"./tx_semaphore_performance_system_info_get.obj" \
+"./tx_semaphore_prioritize.obj" \
+"./tx_semaphore_put.obj" \
+"./tx_semaphore_put_notify.obj" \
+"./tx_thread_context_restore.obj" \
+"./tx_thread_context_save.obj" \
+"./tx_thread_create.obj" \
+"./tx_thread_delete.obj" \
+"./tx_thread_entry_exit_notify.obj" \
+"./tx_thread_identify.obj" \
+"./tx_thread_info_get.obj" \
+"./tx_thread_initialize.obj" \
+"./tx_thread_interrupt_control.obj" \
+"./tx_thread_performance_info_get.obj" \
+"./tx_thread_performance_system_info_get.obj" \
+"./tx_thread_preemption_change.obj" \
+"./tx_thread_priority_change.obj" \
+"./tx_thread_relinquish.obj" \
+"./tx_thread_reset.obj" \
+"./tx_thread_resume.obj" \
+"./tx_thread_schedule.obj" \
+"./tx_thread_shell_entry.obj" \
+"./tx_thread_sleep.obj" \
+"./tx_thread_stack_analyze.obj" \
+"./tx_thread_stack_build.obj" \
+"./tx_thread_stack_error_handler.obj" \
+"./tx_thread_stack_error_notify.obj" \
+"./tx_thread_suspend.obj" \
+"./tx_thread_system_preempt_check.obj" \
+"./tx_thread_system_resume.obj" \
+"./tx_thread_system_return.obj" \
+"./tx_thread_system_suspend.obj" \
+"./tx_thread_terminate.obj" \
+"./tx_thread_time_slice.obj" \
+"./tx_thread_time_slice_change.obj" \
+"./tx_thread_timeout.obj" \
+"./tx_thread_wait_abort.obj" \
+"./tx_time_get.obj" \
+"./tx_time_set.obj" \
+"./tx_timer_activate.obj" \
+"./tx_timer_change.obj" \
+"./tx_timer_create.obj" \
+"./tx_timer_deactivate.obj" \
+"./tx_timer_delete.obj" \
+"./tx_timer_expiration_process.obj" \
+"./tx_timer_info_get.obj" \
+"./tx_timer_initialize.obj" \
+"./tx_timer_interrupt.obj" \
+"./tx_timer_performance_info_get.obj" \
+"./tx_timer_performance_system_info_get.obj" \
+"./tx_timer_system_activate.obj" \
+"./tx_timer_system_deactivate.obj" \
+"./tx_timer_thread_entry.obj" \
+"./tx_trace_buffer_full_notify.obj" \
+"./tx_trace_disable.obj" \
+"./tx_trace_enable.obj" \
+"./tx_trace_event_filter.obj" \
+"./tx_trace_event_unfilter.obj" \
+"./tx_trace_initialize.obj" \
+"./tx_trace_interrupt_control.obj" \
+"./tx_trace_isr_enter_insert.obj" \
+"./tx_trace_isr_exit_insert.obj" \
+"./tx_trace_object_register.obj" \
+"./tx_trace_object_unregister.obj" \
+"./tx_trace_user_event_insert.obj" \
+"./txe_block_allocate.obj" \
+"./txe_block_pool_create.obj" \
+"./txe_block_pool_delete.obj" \
+"./txe_block_pool_info_get.obj" \
+"./txe_block_pool_prioritize.obj" \
+"./txe_block_release.obj" \
+"./txe_byte_allocate.obj" \
+"./txe_byte_pool_create.obj" \
+"./txe_byte_pool_delete.obj" \
+"./txe_byte_pool_info_get.obj" \
+"./txe_byte_pool_prioritize.obj" \
+"./txe_byte_release.obj" \
+"./txe_event_flags_create.obj" \
+"./txe_event_flags_delete.obj" \
+"./txe_event_flags_get.obj" \
+"./txe_event_flags_info_get.obj" \
+"./txe_event_flags_set.obj" \
+"./txe_event_flags_set_notify.obj" \
+"./txe_mutex_create.obj" \
+"./txe_mutex_delete.obj" \
+"./txe_mutex_get.obj" \
+"./txe_mutex_info_get.obj" \
+"./txe_mutex_prioritize.obj" \
+"./txe_mutex_put.obj" \
+"./txe_queue_create.obj" \
+"./txe_queue_delete.obj" \
+"./txe_queue_flush.obj" \
+"./txe_queue_front_send.obj" \
+"./txe_queue_info_get.obj" \
+"./txe_queue_prioritize.obj" \
+"./txe_queue_receive.obj" \
+"./txe_queue_send.obj" \
+"./txe_queue_send_notify.obj" \
+"./txe_semaphore_ceiling_put.obj" \
+"./txe_semaphore_create.obj" \
+"./txe_semaphore_delete.obj" \
+"./txe_semaphore_get.obj" \
+"./txe_semaphore_info_get.obj" \
+"./txe_semaphore_prioritize.obj" \
+"./txe_semaphore_put.obj" \
+"./txe_semaphore_put_notify.obj" \
+"./txe_thread_create.obj" \
+"./txe_thread_delete.obj" \
+"./txe_thread_entry_exit_notify.obj" \
+"./txe_thread_info_get.obj" \
+"./txe_thread_preemption_change.obj" \
+"./txe_thread_priority_change.obj" \
+"./txe_thread_relinquish.obj" \
+"./txe_thread_reset.obj" \
+"./txe_thread_resume.obj" \
+"./txe_thread_suspend.obj" \
+"./txe_thread_terminate.obj" \
+"./txe_thread_time_slice_change.obj" \
+"./txe_thread_wait_abort.obj" \
+"./txe_timer_activate.obj" \
+"./txe_timer_change.obj" \
+"./txe_timer_create.obj" \
+"./txe_timer_deactivate.obj" \
+"./txe_timer_delete.obj" \
+"./txe_timer_info_get.obj" \
+
+-include ../makefile.init
+
+RM := DEL /F
+RMDIR := RMDIR /S/Q
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include subdir_vars.mk
+-include subdir_rules.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(C55_DEPS)),)
+-include $(C55_DEPS)
+endif
+ifneq ($(strip $(C_UPPER_DEPS)),)
+-include $(C_UPPER_DEPS)
+endif
+ifneq ($(strip $(S67_DEPS)),)
+-include $(S67_DEPS)
+endif
+ifneq ($(strip $(S62_DEPS)),)
+-include $(S62_DEPS)
+endif
+ifneq ($(strip $(S_DEPS)),)
+-include $(S_DEPS)
+endif
+ifneq ($(strip $(OPT_DEPS)),)
+-include $(OPT_DEPS)
+endif
+ifneq ($(strip $(C??_DEPS)),)
+-include $(C??_DEPS)
+endif
+ifneq ($(strip $(ASM_UPPER_DEPS)),)
+-include $(ASM_UPPER_DEPS)
+endif
+ifneq ($(strip $(S??_DEPS)),)
+-include $(S??_DEPS)
+endif
+ifneq ($(strip $(C64_DEPS)),)
+-include $(C64_DEPS)
+endif
+ifneq ($(strip $(CXX_DEPS)),)
+-include $(CXX_DEPS)
+endif
+ifneq ($(strip $(S64_DEPS)),)
+-include $(S64_DEPS)
+endif
+ifneq ($(strip $(INO_DEPS)),)
+-include $(INO_DEPS)
+endif
+ifneq ($(strip $(CLA_DEPS)),)
+-include $(CLA_DEPS)
+endif
+ifneq ($(strip $(S55_DEPS)),)
+-include $(S55_DEPS)
+endif
+ifneq ($(strip $(SV7A_DEPS)),)
+-include $(SV7A_DEPS)
+endif
+ifneq ($(strip $(C62_DEPS)),)
+-include $(C62_DEPS)
+endif
+ifneq ($(strip $(C67_DEPS)),)
+-include $(C67_DEPS)
+endif
+ifneq ($(strip $(PDE_DEPS)),)
+-include $(PDE_DEPS)
+endif
+ifneq ($(strip $(K_DEPS)),)
+-include $(K_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+ifneq ($(strip $(CC_DEPS)),)
+-include $(CC_DEPS)
+endif
+ifneq ($(strip $(C++_DEPS)),)
+-include $(C++_DEPS)
+endif
+ifneq ($(strip $(C43_DEPS)),)
+-include $(C43_DEPS)
+endif
+ifneq ($(strip $(S43_DEPS)),)
+-include $(S43_DEPS)
+endif
+ifneq ($(strip $(ASM_DEPS)),)
+-include $(ASM_DEPS)
+endif
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+ifneq ($(strip $(CPP_DEPS)),)
+-include $(CPP_DEPS)
+endif
+ifneq ($(strip $(SA_DEPS)),)
+-include $(SA_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables 
+LIB_OUTPUTS += \
+tx.lib \
+
+LIB_OUTPUTS__QUOTED += \
+"tx.lib" \
+
+
+# All Target
+all: tx.lib
+
+# Tool invocations
+tx.lib: $(OBJS) $(OBJ_SRCS) $(LIB_SRCS)
+ifneq ($(strip $(ORDERED_OBJS)),)
+	@echo 'Building target: "$@"'
+	@echo 'Invoking: C6000 Archiver'
+	"C:/ti/ccsv8/tools/compiler/ti-cgt-c6000_8.2.4/bin/ar6x" r "tx.lib" $(ORDERED_OBJS)
+	@echo 'Finished building target: "$@"'
+	@echo ' '
+endif
+
+# Other Targets
+clean:
+	-$(RM) $(LIB_OUTPUTS__QUOTED)
+	-$(RM) "tx_block_allocate.obj" "tx_block_pool_cleanup.obj" "tx_block_pool_create.obj" "tx_block_pool_delete.obj" "tx_block_pool_info_get.obj" "tx_block_pool_initialize.obj" "tx_block_pool_performance_info_get.obj" "tx_block_pool_performance_system_info_get.obj" "tx_block_pool_prioritize.obj" "tx_block_release.obj" "tx_byte_allocate.obj" "tx_byte_pool_cleanup.obj" "tx_byte_pool_create.obj" "tx_byte_pool_delete.obj" "tx_byte_pool_info_get.obj" "tx_byte_pool_initialize.obj" "tx_byte_pool_performance_info_get.obj" "tx_byte_pool_performance_system_info_get.obj" "tx_byte_pool_prioritize.obj" "tx_byte_pool_search.obj" "tx_byte_release.obj" "tx_event_flags_cleanup.obj" "tx_event_flags_create.obj" "tx_event_flags_delete.obj" "tx_event_flags_get.obj" "tx_event_flags_info_get.obj" "tx_event_flags_initialize.obj" "tx_event_flags_performance_info_get.obj" "tx_event_flags_performance_system_info_get.obj" "tx_event_flags_set.obj" "tx_event_flags_set_notify.obj" "tx_initialize_high_level.obj" "tx_initialize_kernel_enter.obj" 
+	-$(RM) "tx_initialize_kernel_setup.obj" "tx_mutex_cleanup.obj" "tx_mutex_create.obj" "tx_mutex_delete.obj" "tx_mutex_get.obj" "tx_mutex_info_get.obj" "tx_mutex_initialize.obj" "tx_mutex_performance_info_get.obj" "tx_mutex_performance_system_info_get.obj" "tx_mutex_prioritize.obj" "tx_mutex_priority_change.obj" "tx_mutex_put.obj" "tx_queue_cleanup.obj" "tx_queue_create.obj" "tx_queue_delete.obj" "tx_queue_flush.obj" "tx_queue_front_send.obj" "tx_queue_info_get.obj" "tx_queue_initialize.obj" "tx_queue_performance_info_get.obj" "tx_queue_performance_system_info_get.obj" "tx_queue_prioritize.obj" "tx_queue_receive.obj" "tx_queue_send.obj" "tx_queue_send_notify.obj" "tx_semaphore_ceiling_put.obj" "tx_semaphore_cleanup.obj" "tx_semaphore_create.obj" "tx_semaphore_delete.obj" "tx_semaphore_get.obj" "tx_semaphore_info_get.obj" "tx_semaphore_initialize.obj" "tx_semaphore_performance_info_get.obj" "tx_semaphore_performance_system_info_get.obj" "tx_semaphore_prioritize.obj" "tx_semaphore_put.obj" "tx_semaphore_put_notify.obj" 
+	-$(RM) "tx_thread_context_restore.obj" "tx_thread_context_save.obj" "tx_thread_create.obj" "tx_thread_delete.obj" "tx_thread_entry_exit_notify.obj" "tx_thread_identify.obj" "tx_thread_info_get.obj" "tx_thread_initialize.obj" "tx_thread_interrupt_control.obj" "tx_thread_performance_info_get.obj" "tx_thread_performance_system_info_get.obj" "tx_thread_preemption_change.obj" "tx_thread_priority_change.obj" "tx_thread_relinquish.obj" "tx_thread_reset.obj" "tx_thread_resume.obj" "tx_thread_schedule.obj" "tx_thread_shell_entry.obj" "tx_thread_sleep.obj" "tx_thread_stack_analyze.obj" "tx_thread_stack_build.obj" "tx_thread_stack_error_handler.obj" "tx_thread_stack_error_notify.obj" "tx_thread_suspend.obj" "tx_thread_system_preempt_check.obj" "tx_thread_system_resume.obj" "tx_thread_system_return.obj" "tx_thread_system_suspend.obj" "tx_thread_terminate.obj" "tx_thread_time_slice.obj" "tx_thread_time_slice_change.obj" "tx_thread_timeout.obj" "tx_thread_wait_abort.obj" "tx_time_get.obj" "tx_time_set.obj" 
+	-$(RM) "tx_timer_activate.obj" "tx_timer_change.obj" "tx_timer_create.obj" "tx_timer_deactivate.obj" "tx_timer_delete.obj" "tx_timer_expiration_process.obj" "tx_timer_info_get.obj" "tx_timer_initialize.obj" "tx_timer_interrupt.obj" "tx_timer_performance_info_get.obj" "tx_timer_performance_system_info_get.obj" "tx_timer_system_activate.obj" "tx_timer_system_deactivate.obj" "tx_timer_thread_entry.obj" "tx_trace_buffer_full_notify.obj" "tx_trace_disable.obj" "tx_trace_enable.obj" "tx_trace_event_filter.obj" "tx_trace_event_unfilter.obj" "tx_trace_initialize.obj" "tx_trace_interrupt_control.obj" "tx_trace_isr_enter_insert.obj" "tx_trace_isr_exit_insert.obj" "tx_trace_object_register.obj" "tx_trace_object_unregister.obj" "tx_trace_user_event_insert.obj" "txe_block_allocate.obj" "txe_block_pool_create.obj" "txe_block_pool_delete.obj" "txe_block_pool_info_get.obj" "txe_block_pool_prioritize.obj" "txe_block_release.obj" "txe_byte_allocate.obj" "txe_byte_pool_create.obj" "txe_byte_pool_delete.obj" "txe_byte_pool_info_get.obj" 
+	-$(RM) "txe_byte_pool_prioritize.obj" "txe_byte_release.obj" "txe_event_flags_create.obj" "txe_event_flags_delete.obj" "txe_event_flags_get.obj" "txe_event_flags_info_get.obj" "txe_event_flags_set.obj" "txe_event_flags_set_notify.obj" "txe_mutex_create.obj" "txe_mutex_delete.obj" "txe_mutex_get.obj" "txe_mutex_info_get.obj" "txe_mutex_prioritize.obj" "txe_mutex_put.obj" "txe_queue_create.obj" "txe_queue_delete.obj" "txe_queue_flush.obj" "txe_queue_front_send.obj" "txe_queue_info_get.obj" "txe_queue_prioritize.obj" "txe_queue_receive.obj" "txe_queue_send.obj" "txe_queue_send_notify.obj" "txe_semaphore_ceiling_put.obj" "txe_semaphore_create.obj" "txe_semaphore_delete.obj" "txe_semaphore_get.obj" "txe_semaphore_info_get.obj" "txe_semaphore_prioritize.obj" "txe_semaphore_put.obj" "txe_semaphore_put_notify.obj" "txe_thread_create.obj" "txe_thread_delete.obj" "txe_thread_entry_exit_notify.obj" "txe_thread_info_get.obj" "txe_thread_preemption_change.obj" "txe_thread_priority_change.obj" "txe_thread_relinquish.obj" 
+	-$(RM) "txe_thread_reset.obj" "txe_thread_resume.obj" "txe_thread_suspend.obj" "txe_thread_terminate.obj" "txe_thread_time_slice_change.obj" "txe_thread_wait_abort.obj" "txe_timer_activate.obj" "txe_timer_change.obj" "txe_timer_create.obj" "txe_timer_deactivate.obj" "txe_timer_delete.obj" "txe_timer_info_get.obj" 
+	-$(RM) "tx_block_allocate.d" "tx_block_pool_cleanup.d" "tx_block_pool_create.d" "tx_block_pool_delete.d" "tx_block_pool_info_get.d" "tx_block_pool_initialize.d" "tx_block_pool_performance_info_get.d" "tx_block_pool_performance_system_info_get.d" "tx_block_pool_prioritize.d" "tx_block_release.d" "tx_byte_allocate.d" "tx_byte_pool_cleanup.d" "tx_byte_pool_create.d" "tx_byte_pool_delete.d" "tx_byte_pool_info_get.d" "tx_byte_pool_initialize.d" "tx_byte_pool_performance_info_get.d" "tx_byte_pool_performance_system_info_get.d" "tx_byte_pool_prioritize.d" "tx_byte_pool_search.d" "tx_byte_release.d" "tx_event_flags_cleanup.d" "tx_event_flags_create.d" "tx_event_flags_delete.d" "tx_event_flags_get.d" "tx_event_flags_info_get.d" "tx_event_flags_initialize.d" "tx_event_flags_performance_info_get.d" "tx_event_flags_performance_system_info_get.d" "tx_event_flags_set.d" "tx_event_flags_set_notify.d" "tx_initialize_high_level.d" "tx_initialize_kernel_enter.d" "tx_initialize_kernel_setup.d" "tx_mutex_cleanup.d" 
+	-$(RM) "tx_mutex_create.d" "tx_mutex_delete.d" "tx_mutex_get.d" "tx_mutex_info_get.d" "tx_mutex_initialize.d" "tx_mutex_performance_info_get.d" "tx_mutex_performance_system_info_get.d" "tx_mutex_prioritize.d" "tx_mutex_priority_change.d" "tx_mutex_put.d" "tx_queue_cleanup.d" "tx_queue_create.d" "tx_queue_delete.d" "tx_queue_flush.d" "tx_queue_front_send.d" "tx_queue_info_get.d" "tx_queue_initialize.d" "tx_queue_performance_info_get.d" "tx_queue_performance_system_info_get.d" "tx_queue_prioritize.d" "tx_queue_receive.d" "tx_queue_send.d" "tx_queue_send_notify.d" "tx_semaphore_ceiling_put.d" "tx_semaphore_cleanup.d" "tx_semaphore_create.d" "tx_semaphore_delete.d" "tx_semaphore_get.d" "tx_semaphore_info_get.d" "tx_semaphore_initialize.d" "tx_semaphore_performance_info_get.d" "tx_semaphore_performance_system_info_get.d" "tx_semaphore_prioritize.d" "tx_semaphore_put.d" "tx_semaphore_put_notify.d" "tx_thread_create.d" "tx_thread_delete.d" "tx_thread_entry_exit_notify.d" "tx_thread_identify.d" "tx_thread_info_get.d" 
+	-$(RM) "tx_thread_initialize.d" "tx_thread_performance_info_get.d" "tx_thread_performance_system_info_get.d" "tx_thread_preemption_change.d" "tx_thread_priority_change.d" "tx_thread_relinquish.d" "tx_thread_reset.d" "tx_thread_resume.d" "tx_thread_shell_entry.d" "tx_thread_sleep.d" "tx_thread_stack_analyze.d" "tx_thread_stack_error_handler.d" "tx_thread_stack_error_notify.d" "tx_thread_suspend.d" "tx_thread_system_preempt_check.d" "tx_thread_system_resume.d" "tx_thread_system_suspend.d" "tx_thread_terminate.d" "tx_thread_time_slice.d" "tx_thread_time_slice_change.d" "tx_thread_timeout.d" "tx_thread_wait_abort.d" "tx_time_get.d" "tx_time_set.d" "tx_timer_activate.d" "tx_timer_change.d" "tx_timer_create.d" "tx_timer_deactivate.d" "tx_timer_delete.d" "tx_timer_expiration_process.d" "tx_timer_info_get.d" "tx_timer_initialize.d" "tx_timer_performance_info_get.d" "tx_timer_performance_system_info_get.d" "tx_timer_system_activate.d" "tx_timer_system_deactivate.d" "tx_timer_thread_entry.d" "tx_trace_buffer_full_notify.d" 
+	-$(RM) "tx_trace_disable.d" "tx_trace_enable.d" "tx_trace_event_filter.d" "tx_trace_event_unfilter.d" "tx_trace_initialize.d" "tx_trace_interrupt_control.d" "tx_trace_isr_enter_insert.d" "tx_trace_isr_exit_insert.d" "tx_trace_object_register.d" "tx_trace_object_unregister.d" "tx_trace_user_event_insert.d" "txe_block_allocate.d" "txe_block_pool_create.d" "txe_block_pool_delete.d" "txe_block_pool_info_get.d" "txe_block_pool_prioritize.d" "txe_block_release.d" "txe_byte_allocate.d" "txe_byte_pool_create.d" "txe_byte_pool_delete.d" "txe_byte_pool_info_get.d" "txe_byte_pool_prioritize.d" "txe_byte_release.d" "txe_event_flags_create.d" "txe_event_flags_delete.d" "txe_event_flags_get.d" "txe_event_flags_info_get.d" "txe_event_flags_set.d" "txe_event_flags_set_notify.d" "txe_mutex_create.d" "txe_mutex_delete.d" "txe_mutex_get.d" "txe_mutex_info_get.d" "txe_mutex_prioritize.d" "txe_mutex_put.d" "txe_queue_create.d" "txe_queue_delete.d" "txe_queue_flush.d" "txe_queue_front_send.d" "txe_queue_info_get.d" 
+	-$(RM) "txe_queue_prioritize.d" "txe_queue_receive.d" "txe_queue_send.d" "txe_queue_send_notify.d" "txe_semaphore_ceiling_put.d" "txe_semaphore_create.d" "txe_semaphore_delete.d" "txe_semaphore_get.d" "txe_semaphore_info_get.d" "txe_semaphore_prioritize.d" "txe_semaphore_put.d" "txe_semaphore_put_notify.d" "txe_thread_create.d" "txe_thread_delete.d" "txe_thread_entry_exit_notify.d" "txe_thread_info_get.d" "txe_thread_preemption_change.d" "txe_thread_priority_change.d" "txe_thread_relinquish.d" "txe_thread_reset.d" "txe_thread_resume.d" "txe_thread_suspend.d" "txe_thread_terminate.d" "txe_thread_time_slice_change.d" "txe_thread_wait_abort.d" "txe_timer_activate.d" "txe_timer_change.d" "txe_timer_create.d" "txe_timer_deactivate.d" "txe_timer_delete.d" "txe_timer_info_get.d" 
+	-$(RM) "tx_thread_context_restore.d" "tx_thread_context_save.d" "tx_thread_interrupt_control.d" "tx_thread_schedule.d" "tx_thread_stack_build.d" "tx_thread_system_return.d" "tx_timer_interrupt.d" 
+	-@echo 'Finished clean'
+	-@echo ' '
+
+.PHONY: all clean dependents
+.SECONDARY:
+
+-include ../makefile.targets
+

ports/cortex_m0/ac5/src/tx_thread_schedule.s

@@ -30,6 +30,10 @@
     IMPORT  _tx_execution_thread_enter
     IMPORT  _tx_execution_thread_exit
     ENDIF
+    IF :DEF:TX_LOW_POWER
+    IMPORT  tx_low_power_enter
+    IMPORT  tx_low_power_exit
+    ENDIF
 ;
 ;
     AREA    ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M0/AC5     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -73,6 +77,9 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -240,11 +247,23 @@ __tx_ts_wait
     STR     r1, [r0]                                ; Store it in the current pointer
     CMP     r1, #0                                  ; If non-NULL, a new thread is ready!
     BNE     __tx_ts_ready                           ;
+    IF:DEF:TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+    ENDIF
+
     IF:DEF:TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
     ENDIF
+
+    IF:DEF:TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+    ENDIF
 __tx_ts_ISB
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting

ports/cortex_m0/ac6/src/tx_thread_schedule.S

@@ -25,6 +25,10 @@
     .global  _tx_thread_execute_ptr
     .global  _tx_timer_time_slice
     .global  _tx_thread_system_stack_ptr
+#ifdef TX_LOW_POWER
+    .global tx_low_power_enter
+    .global tx_low_power_exit
+#endif
 @
 @
     .text
@@ -35,7 +39,7 @@
 @/*  FUNCTION                                               RELEASE        */
 @/*                                                                        */
 @/*    _tx_thread_schedule                               Cortex-M0/AC6     */
-@/*                                                           6.1          */
+@/*                                                           6.1.5        */
 @/*  AUTHOR                                                                */
 @/*                                                                        */
 @/*    William E. Lamie, Microsoft Corporation                             */
@@ -69,6 +73,9 @@
 @/*    DATE              NAME                      DESCRIPTION             */
 @/*                                                                        */
 @/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+@/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+@/*                                           low power code,              */
+@/*                                           resulting in version 6.1.5   */
 @/*                                                                        */
 @/**************************************************************************/
 @VOID   _tx_thread_schedule(VOID)
@@ -244,11 +251,25 @@ __tx_ts_wait:
     STR     r1, [r0]                                @ Store it in the current pointer
     CMP     r1, #0                                  @ If non-NULL, a new thread is ready!
     BNE     __tx_ts_ready                           @
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      @ Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             @ Ensure no outstanding memory transactions
     WFI                                             @ Wait for interrupt
     ISB                                             @ Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       @ Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       @ Enable interrupts
     B       __tx_ts_wait                            @ Loop to continue waiting
 @

ports/cortex_m0/gnu/src/tx_thread_schedule.S

@@ -27,6 +27,10 @@
     .global  _tx_thread_system_stack_ptr
     .global  _tx_execution_thread_enter
     .global  _tx_execution_thread_exit
+#ifdef TX_LOW_POWER
+    .global tx_low_power_enter
+    .global tx_low_power_exit
+#endif
 @
 @
     .text
@@ -37,7 +41,7 @@
 @/*  FUNCTION                                               RELEASE        */
 @/*                                                                        */
 @/*    _tx_thread_schedule                               Cortex-M0/GNU     */
-@/*                                                           6.1          */
+@/*                                                           6.1.5        */
 @/*  AUTHOR                                                                */
 @/*                                                                        */
 @/*    William E. Lamie, Microsoft Corporation                             */
@@ -73,6 +77,9 @@
 @/*  05-19-2020     William E. Lamie        Initial Version 6.0            */
 @/*  09-30-2020     William E. Lamie        Modified comment(s),           */
 @/*                                            resulting in version 6.1    */
+@/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+@/*                                           low power code,              */
+@/*                                           resulting in version 6.1.5   */
 @/*                                                                        */
 @/**************************************************************************/
 @VOID   _tx_thread_schedule(VOID)
@@ -248,11 +255,25 @@ __tx_ts_wait:
     STR     r1, [r0]                                @ Store it in the current pointer
     CMP     r1, #0                                  @ If non-NULL, a new thread is ready!
     BNE     __tx_ts_ready                           @
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      @ Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             @ Ensure no outstanding memory transactions
     WFI                                             @ Wait for interrupt
     ISB                                             @ Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       @ Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       @ Enable interrupts
     B       __tx_ts_wait                            @ Loop to continue waiting
 @

ports/cortex_m0/iar/src/tx_thread_schedule.s

@@ -28,6 +28,10 @@
     EXTERN  _tx_thread_preempt_disable
     EXTERN  _tx_execution_thread_enter
     EXTERN  _tx_execution_thread_exit
+#ifdef TX_LOW_POWER
+    EXTERN  tx_low_power_enter
+    EXTERN  tx_low_power_exit
+#endif
 ;
 ;
     SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M0/IAR     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -71,6 +75,9 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -238,11 +245,25 @@ __tx_ts_wait:
     STR     r1, [r0]                                ; Store it in the current pointer
     CMP     r1, #0                                  ; If non-NULL, a new thread is ready!
     BNE     __tx_ts_ready                           ;
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting
 ;

ports/cortex_m0/keil/src/tx_thread_schedule.s

@@ -30,6 +30,10 @@
     IMPORT  _tx_execution_thread_enter
     IMPORT  _tx_execution_thread_exit
     ENDIF
+    IF :DEF:TX_LOW_POWER
+    IMPORT  tx_low_power_enter
+    IMPORT  tx_low_power_exit
+    ENDIF
 ;
 ;
     AREA    ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M0/AC5     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -73,6 +77,9 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -241,11 +248,25 @@ __tx_ts_wait
     STR     r1, [r0]                                ; Store it in the current pointer
     CMP     r1, #0                                  ; If non-NULL, a new thread is ready!
     BNE     __tx_ts_ready                           ;
+
+    IF:DEF:TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+    ENDIF
+
     IF:DEF:TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
     ENDIF
+
+    IF:DEF:TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+    ENDIF
+
 __tx_ts_ISB
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting

ports/cortex_m23/ac6/inc/tx_port.h

@@ -26,7 +26,7 @@
 /*  PORT SPECIFIC C INFORMATION                            RELEASE        */
 /*                                                                        */
 /*    tx_port.h                                         Cortex-M23/AC6    */
-/*                                                           6.1          */
+/*                                                           6.1.5        */
 /*                                                                        */
 /*  AUTHOR                                                                */
 /*                                                                        */
@@ -48,6 +48,9 @@
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
 /*  09-30-2020      Scott Larson            Initial Version 6.1           */
+/*  03-02-2021      Scott Larson            Modified comment(s), added    */
+/*                                            ULONG64_DEFINED,            */
+/*                                            resulting in version 6.1.5  */
 /*                                                                        */
 /**************************************************************************/
 
@@ -82,6 +85,7 @@ typedef unsigned long                           ULONG;
 typedef unsigned long long                      ULONG64;
 typedef short                                   SHORT;
 typedef unsigned short                          USHORT;
+#define ULONG64_DEFINED
 
 /* Function prototypes for this port. */
 struct  TX_THREAD_STRUCT;

ports/cortex_m23/ac6/readme_threadx.txt

@@ -15,6 +15,8 @@ Building the ThreadX library is easy; simply set the ThreadX_Library project
 as active, then then build the library. You should now observe the compilation 
 and assembly of the ThreadX library. This project build produces the ThreadX
 library file ThreadX_Library.lib.
+Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c 
+replace the common files of the same name. 
 
 
 3.  Demonstration System

ports/cortex_m23/gnu/inc/tx_port.h

@@ -48,10 +48,11 @@
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
 /*  09-30-2020      Scott Larson            Initial Version 6.1           */
-/*  12-31-2020     Scott Larson             Modified comment(s),          */
+/*  03-02-2021      Scott Larson            Modified comment(s),          */
 /*                                            remove unneeded headers,    */
-/*                                            use builtins,               */
+/*                                            use builtins, added         */
-/*                                            resulting in version 6.1.3  */
+/*                                            ULONG64_DEFINED,            */
+/*                                            resulting in version 6.1.5  */
 /*                                                                        */
 /**************************************************************************/
 
@@ -84,6 +85,7 @@ typedef unsigned long                           ULONG;
 typedef unsigned long long                      ULONG64;
 typedef short                                   SHORT;
 typedef unsigned short                          USHORT;
+#define ULONG64_DEFINED
 
 /* Function prototypes for this port. */
 struct  TX_THREAD_STRUCT;

ports/cortex_m23/gnu/readme_threadx.txt

@@ -6,7 +6,8 @@
 1.  Building the ThreadX run-time Library
 
 An example .bat file is in the example_build directory.
-
+Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c 
+replace the common files of the same name. 
 
 2.  Demonstration System
 

ports/cortex_m23/iar/inc/tx_port.h

@@ -26,7 +26,7 @@
 /*  PORT SPECIFIC C INFORMATION                            RELEASE        */
 /*                                                                        */
 /*    tx_port.h                                         Cortex-M23/IAR    */
-/*                                                           6.1          */
+/*                                                           6.1.5        */
 /*                                                                        */
 /*  AUTHOR                                                                */
 /*                                                                        */
@@ -48,6 +48,9 @@
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
 /*  09-30-2020      Scott Larson            Initial Version 6.1           */
+/*  03-02-2021      Scott Larson            Modified comment(s), added    */
+/*                                            ULONG64_DEFINED,            */
+/*                                            resulting in version 6.1.5  */
 /*                                                                        */
 /**************************************************************************/
 
@@ -85,6 +88,7 @@ typedef unsigned long                           ULONG;
 typedef unsigned long long                      ULONG64;
 typedef short                                   SHORT;
 typedef unsigned short                          USHORT;
+#define ULONG64_DEFINED
 
 /* Function prototypes for this port. */
 struct  TX_THREAD_STRUCT;

ports/cortex_m23/iar/readme_threadx.txt

@@ -9,7 +9,8 @@ Import all ThreadX common and port-specific source files into an IAR project.
 Configure the project to build a library rather than an executable. This 
 results in the ThreadX run-time library file tx.a, which is needed by 
 the application.
-
+Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c 
+replace the common files of the same name. 
 
 2.  Demonstration System
 

ports/cortex_m3/ac5/src/tx_thread_schedule.s

@@ -30,6 +30,10 @@
     IMPORT  _tx_execution_thread_enter
     IMPORT  _tx_execution_thread_exit
     ENDIF
+    IF :DEF:TX_LOW_POWER
+    IMPORT  tx_low_power_enter
+    IMPORT  tx_low_power_exit
+    ENDIF
 ;
 ;
     AREA    ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M3/AC5     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -73,6 +77,9 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -217,11 +224,25 @@ __tx_ts_wait
     LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
     STR     r1, [r0]                                ; Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+
+    IF:DEF:TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+    ENDIF
+
     IF:DEF:TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
     ENDIF
+
+    IF:DEF:TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+    ENDIF
+
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting
 ;

ports/cortex_m3/ac6/src/tx_thread_schedule.S

@@ -25,6 +25,11 @@
     .global     _tx_thread_execute_ptr
     .global     _tx_timer_time_slice
     .global     _tx_thread_system_stack_ptr
+#ifdef TX_LOW_POWER
+    .global tx_low_power_enter
+    .global tx_low_power_exit
+#endif
+
 @
 @
     .text
@@ -35,7 +40,7 @@
 @/*  FUNCTION                                               RELEASE        */
 @/*                                                                        */
 @/*    _tx_thread_schedule                               Cortex-M3/AC6     */
-@/*                                                           6.1          */
+@/*                                                           6.1.5        */
 @/*  AUTHOR                                                                */
 @/*                                                                        */
 @/*    William E. Lamie, Microsoft Corporation                             */
@@ -69,6 +74,9 @@
 @/*    DATE              NAME                      DESCRIPTION             */
 @/*                                                                        */
 @/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+@/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+@/*                                           low power code,              */
+@/*                                           resulting in version 6.1.5   */
 @/*                                                                        */
 @/**************************************************************************/
 @VOID   _tx_thread_schedule(VOID)
@@ -218,11 +226,25 @@ __tx_ts_wait:
     LDR     r1, [r2]                                @ Pickup the next thread to execute pointer
     STR     r1, [r0]                                @ Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       @ If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      @ Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             @ Ensure no outstanding memory transactions
     WFI                                             @ Wait for interrupt
     ISB                                             @ Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       @ Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       @ Enable interrupts
     B       __tx_ts_wait                            @ Loop to continue waiting
 @

ports/cortex_m3/ghs/src/tx_thread_schedule.arm

@@ -28,7 +28,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M3/GHS     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -62,6 +62,9 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -210,11 +213,25 @@ __tx_ts_wait:
     LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
     STR     r1, [r0]                                ; Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting
 ;

ports/cortex_m3/gnu/src/tx_thread_schedule.S

@@ -27,6 +27,10 @@
     .global     _tx_thread_system_stack_ptr
     .global     _tx_execution_thread_enter
     .global     _tx_execution_thread_exit
+#ifdef TX_LOW_POWER
+    .global tx_low_power_enter
+    .global tx_low_power_exit
+#endif
 @
 @
     .text
@@ -37,7 +41,7 @@
 @/*  FUNCTION                                               RELEASE        */
 @/*                                                                        */
 @/*    _tx_thread_schedule                               Cortex-M3/GNU     */
-@/*                                                           6.1          */
+@/*                                                           6.1.5        */
 @/*  AUTHOR                                                                */
 @/*                                                                        */
 @/*    William E. Lamie, Microsoft Corporation                             */
@@ -73,6 +77,9 @@
 @/*  05-19-2020     William E. Lamie        Initial Version 6.0            */
 @/*  09-30-2020     William E. Lamie        Modified comment(s),           */
 @/*                                            resulting in version 6.1    */
+@/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+@/*                                           low power code,              */
+@/*                                           resulting in version 6.1.5   */
 @/*                                                                        */
 @/**************************************************************************/
 @VOID   _tx_thread_schedule(VOID)
@@ -222,11 +229,25 @@ __tx_ts_wait:
     LDR     r1, [r2]                                @ Pickup the next thread to execute pointer
     STR     r1, [r0]                                @ Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       @ If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      @ Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             @ Ensure no outstanding memory transactions
     WFI                                             @ Wait for interrupt
     ISB                                             @ Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       @ Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       @ Enable interrupts
     B       __tx_ts_wait                            @ Loop to continue waiting
 @

ports/cortex_m3/iar/src/tx_thread_schedule.s

@@ -28,6 +28,10 @@
     EXTERN  _tx_execution_thread_enter
     EXTERN  _tx_execution_thread_exit
     EXTERN  _tx_thread_preempt_disable
+#ifdef TX_LOW_POWER
+    EXTERN  tx_low_power_enter
+    EXTERN  tx_low_power_exit
+#endif
 ;
 ;
     SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M3/IAR     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -71,6 +75,9 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -216,11 +223,25 @@ __tx_ts_wait:
     LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
     STR     r1, [r0]                                ; Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting
 ;

ports/cortex_m3/keil/src/tx_thread_schedule.s

@@ -30,6 +30,10 @@
     IMPORT  _tx_execution_thread_enter
     IMPORT  _tx_execution_thread_exit
     ENDIF
+    IF :DEF:TX_LOW_POWER
+    IMPORT  tx_low_power_enter
+    IMPORT  tx_low_power_exit
+    ENDIF
 ;
 ;
     AREA    ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M3/AC5     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -73,6 +77,9 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -217,11 +224,25 @@ __tx_ts_wait
     LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
     STR     r1, [r0]                                ; Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+
+    IF:DEF:TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+    ENDIF
+
     IF:DEF:TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
     ENDIF
+
+    IF:DEF:TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+    ENDIF
+
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting
 ;

ports/cortex_m33/ac5/readme_threadx.txt

@@ -56,7 +56,7 @@ Non-FPU Stack Frame:
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r4
+    0x04            r4          Software stacked GP registers
     0x08            r5
     0x0C            r6
     0x10            r7
@@ -64,7 +64,7 @@ Non-FPU Stack Frame:
     0x18            r9
     0x1C            r10
     0x20            r11
-     0x24               r0          (Hardware stack starts here!!)
+    0x24            r0          Hardware stacked registers
     0x28            r1
     0x2C            r2
     0x30            r3
@@ -78,55 +78,55 @@ FPU Stack Frame (only interrupted thread with FPU enabled):
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               s0
+    0x04            s16         Software stacked FPU registers
-     0x08               s1
+    0x08            s17
-     0x0C               s2
+    0x0C            s18
-     0x10               s3
+    0x10            s19
-     0x14               s4
+    0x14            s20
-     0x18               s5
+    0x18            s21
-     0x1C               s6
+    0x1C            s22
-     0x20               s7
+    0x20            s23
-     0x24               s8
+    0x24            s24
-     0x28               s9
+    0x28            s25
-     0x2C               s10
+    0x2C            s26
-     0x30               s11
+    0x30            s27
-     0x34               s12
+    0x34            s28
-     0x38               s13
+    0x38            s29
-     0x3C               s14
+    0x3C            s30
-     0x40               s15
+    0x40            s31
-     0x44               s16
+    0x44            r4          Software stacked registers
-     0x48               s17
+    0x48            r5
-     0x4C               s18
+    0x4C            r6
-     0x50               s19
+    0x50            r7
-     0x54               s20
+    0x54            r8
-     0x58               s21
+    0x58            r9
-     0x5C               s22
+    0x5C            r10
-     0x60               s23
+    0x60            r11
-     0x64               s24
+    0x64            r0          Hardware stacked registers
-     0x68               s25
+    0x68            r1
-     0x6C               s26
+    0x6C            r2
-     0x70               s27
+    0x70            r3
-     0x74               s28
+    0x74            r12
-     0x78               s29
+    0x78            lr
-     0x7C               s30
+    0x7C            pc
-     0x80               s31
+    0x80            xPSR
-     0x84               fpscr
+    0x84            s0          Hardware stacked FPU registers
-     0x88               r4
+    0x88            s1
-     0x8C               r5
+    0x8C            s2
-     0x90               r6
+    0x90            s3
-     0x94               r7
+    0x94            s4
-     0x98               r8
+    0x98            s5
-     0x9C               r9
+    0x9C            s6
-     0xA0               r10
+    0xA0            s7
-     0xA4               r11
+    0xA4            s8
-     0xA8               r0          (Hardware stack starts here!!)
+    0xA8            s9
-     0xAC               r1
+    0xAC            s10
-     0xB0               r2
+    0xB0            s11
-     0xB4               r3
+    0xB4            s12
-     0xB8               r12
+    0xB8            s13
-     0xBC               lr
+    0xBC            s14
-     0xC0               pc
+    0xC0            s15
-     0xC4               xPSR
+    0xC4            fpscr
 
 
 6.  Improving Performance

ports/cortex_m33/ac6/inc/tx_port.h

@@ -26,7 +26,7 @@
 /*  PORT SPECIFIC C INFORMATION                            RELEASE        */
 /*                                                                        */
 /*    tx_port.h                                         Cortex-M33/AC6    */
-/*                                                            6.1         */
+/*                                                            6.1.5       */
 /*                                                                        */
 /*  AUTHOR                                                                */
 /*                                                                        */
@@ -48,6 +48,9 @@
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
 /*  09-30-2020      Scott Larson            Initial Version 6.1           */
+/*  03-02-2021      Scott Larson            Modified comment(s), added    */
+/*                                            ULONG64_DEFINED,            */
+/*                                            resulting in version 6.1.5  */
 /*                                                                        */
 /**************************************************************************/
 
@@ -82,6 +85,7 @@ typedef unsigned long                           ULONG;
 typedef unsigned long long                      ULONG64;
 typedef short                                   SHORT;
 typedef unsigned short                          USHORT;
+#define ULONG64_DEFINED
 
 /* Function prototypes for this port. */
 struct  TX_THREAD_STRUCT;

ports/cortex_m33/ac6/readme_threadx.txt

@@ -15,7 +15,8 @@ Building the ThreadX library is easy; simply set the ThreadX_Library project
 as active, then then build the library. You should now observe the compilation 
 and assembly of the ThreadX library. This project build produces the ThreadX
 library file ThreadX_Library.lib.
-
+Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c 
+replace the common files of the same name. 
 
 3.  Demonstration System
 
@@ -56,7 +57,7 @@ Non-FPU Stack Frame:
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r4
+    0x04            r4          Software stacked GP registers
     0x08            r5
     0x0C            r6
     0x10            r7
@@ -64,7 +65,7 @@ Non-FPU Stack Frame:
     0x18            r9
     0x1C            r10
     0x20            r11
-     0x24               r0          (Hardware stack starts here!!)
+    0x24            r0          Hardware stacked registers
     0x28            r1
     0x2C            r2
     0x30            r3
@@ -78,55 +79,55 @@ FPU Stack Frame (only interrupted thread with FPU enabled):
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               s0
+    0x04            s16         Software stacked FPU registers
-     0x08               s1
+    0x08            s17
-     0x0C               s2
+    0x0C            s18
-     0x10               s3
+    0x10            s19
-     0x14               s4
+    0x14            s20
-     0x18               s5
+    0x18            s21
-     0x1C               s6
+    0x1C            s22
-     0x20               s7
+    0x20            s23
-     0x24               s8
+    0x24            s24
-     0x28               s9
+    0x28            s25
-     0x2C               s10
+    0x2C            s26
-     0x30               s11
+    0x30            s27
-     0x34               s12
+    0x34            s28
-     0x38               s13
+    0x38            s29
-     0x3C               s14
+    0x3C            s30
-     0x40               s15
+    0x40            s31
-     0x44               s16
+    0x44            r4          Software stacked registers
-     0x48               s17
+    0x48            r5
-     0x4C               s18
+    0x4C            r6
-     0x50               s19
+    0x50            r7
-     0x54               s20
+    0x54            r8
-     0x58               s21
+    0x58            r9
-     0x5C               s22
+    0x5C            r10
-     0x60               s23
+    0x60            r11
-     0x64               s24
+    0x64            r0          Hardware stacked registers
-     0x68               s25
+    0x68            r1
-     0x6C               s26
+    0x6C            r2
-     0x70               s27
+    0x70            r3
-     0x74               s28
+    0x74            r12
-     0x78               s29
+    0x78            lr
-     0x7C               s30
+    0x7C            pc
-     0x80               s31
+    0x80            xPSR
-     0x84               fpscr
+    0x84            s0          Hardware stacked FPU registers
-     0x88               r4
+    0x88            s1
-     0x8C               r5
+    0x8C            s2
-     0x90               r6
+    0x90            s3
-     0x94               r7
+    0x94            s4
-     0x98               r8
+    0x98            s5
-     0x9C               r9
+    0x9C            s6
-     0xA0               r10
+    0xA0            s7
-     0xA4               r11
+    0xA4            s8
-     0xA8               r0          (Hardware stack starts here!!)
+    0xA8            s9
-     0xAC               r1
+    0xAC            s10
-     0xB0               r2
+    0xB0            s11
-     0xB4               r3
+    0xB4            s12
-     0xB8               r12
+    0xB8            s13
-     0xBC               lr
+    0xBC            s14
-     0xC0               pc
+    0xC0            s15
-     0xC4               xPSR
+    0xC4            fpscr
 
 
 6.  Improving Performance

ports/cortex_m33/gnu/inc/tx_port.h

@@ -26,7 +26,7 @@
 /*  PORT SPECIFIC C INFORMATION                            RELEASE        */
 /*                                                                        */
 /*    tx_port.h                                         Cortex-M33/GNU    */
-/*                                                           6.1          */
+/*                                                           6.1.5        */
 /*                                                                        */
 /*  AUTHOR                                                                */
 /*                                                                        */
@@ -48,6 +48,9 @@
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
 /*  09-30-2020      Scott Larson            Initial Version 6.1           */
+/*  03-02-2021      Scott Larson            Modified comment(s), added    */
+/*                                            ULONG64_DEFINED,            */
+/*                                            resulting in version 6.1.5  */
 /*                                                                        */
 /**************************************************************************/
 
@@ -80,6 +83,7 @@ typedef unsigned long                           ULONG;
 typedef unsigned long long                      ULONG64;
 typedef short                                   SHORT;
 typedef unsigned short                          USHORT;
+#define ULONG64_DEFINED
 
 /* Function prototypes for this port. */
 struct  TX_THREAD_STRUCT;

ports/cortex_m33/gnu/readme_threadx.txt

@@ -8,7 +8,8 @@ Import all ThreadX common and port-specific source files into a GNU project.
 Configure the project to build a library rather than an executable. This 
 results in the ThreadX run-time library file tx.a, which is needed by 
 the application.
-
+Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c 
+replace the common files of the same name. 
 
 2.  Demonstration System
 
@@ -42,7 +43,7 @@ Non-FPU Stack Frame:
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r4
+    0x04            r4          Software stacked GP registers
     0x08            r5
     0x0C            r6
     0x10            r7
@@ -50,7 +51,7 @@ Non-FPU Stack Frame:
     0x18            r9
     0x1C            r10
     0x20            r11
-     0x24               r0          (Hardware stack starts here!!)
+    0x24            r0          Hardware stacked registers
     0x28            r1
     0x2C            r2
     0x30            r3
@@ -64,55 +65,55 @@ FPU Stack Frame (only interrupted thread with FPU enabled):
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               s0
+    0x04            s16         Software stacked FPU registers
-     0x08               s1
+    0x08            s17
-     0x0C               s2
+    0x0C            s18
-     0x10               s3
+    0x10            s19
-     0x14               s4
+    0x14            s20
-     0x18               s5
+    0x18            s21
-     0x1C               s6
+    0x1C            s22
-     0x20               s7
+    0x20            s23
-     0x24               s8
+    0x24            s24
-     0x28               s9
+    0x28            s25
-     0x2C               s10
+    0x2C            s26
-     0x30               s11
+    0x30            s27
-     0x34               s12
+    0x34            s28
-     0x38               s13
+    0x38            s29
-     0x3C               s14
+    0x3C            s30
-     0x40               s15
+    0x40            s31
-     0x44               s16
+    0x44            r4          Software stacked registers
-     0x48               s17
+    0x48            r5
-     0x4C               s18
+    0x4C            r6
-     0x50               s19
+    0x50            r7
-     0x54               s20
+    0x54            r8
-     0x58               s21
+    0x58            r9
-     0x5C               s22
+    0x5C            r10
-     0x60               s23
+    0x60            r11
-     0x64               s24
+    0x64            r0          Hardware stacked registers
-     0x68               s25
+    0x68            r1
-     0x6C               s26
+    0x6C            r2
-     0x70               s27
+    0x70            r3
-     0x74               s28
+    0x74            r12
-     0x78               s29
+    0x78            lr
-     0x7C               s30
+    0x7C            pc
-     0x80               s31
+    0x80            xPSR
-     0x84               fpscr
+    0x84            s0          Hardware stacked FPU registers
-     0x88               r4
+    0x88            s1
-     0x8C               r5
+    0x8C            s2
-     0x90               r6
+    0x90            s3
-     0x94               r7
+    0x94            s4
-     0x98               r8
+    0x98            s5
-     0x9C               r9
+    0x9C            s6
-     0xA0               r10
+    0xA0            s7
-     0xA4               r11
+    0xA4            s8
-     0xA8               r0          (Hardware stack starts here!!)
+    0xA8            s9
-     0xAC               r1
+    0xAC            s10
-     0xB0               r2
+    0xB0            s11
-     0xB4               r3
+    0xB4            s12
-     0xB8               r12
+    0xB8            s13
-     0xBC               lr
+    0xBC            s14
-     0xC0               pc
+    0xC0            s15
-     0xC4               xPSR
+    0xC4            fpscr
 
 
 5.  Improving Performance

ports/cortex_m33/iar/inc/tx_port.h

@@ -26,7 +26,7 @@
 /*  PORT SPECIFIC C INFORMATION                            RELEASE        */
 /*                                                                        */
 /*    tx_port.h                                         Cortex-M33/IAR    */
-/*                                                            6.1         */
+/*                                                            6.1.5       */
 /*                                                                        */
 /*  AUTHOR                                                                */
 /*                                                                        */
@@ -48,6 +48,9 @@
 /*    DATE              NAME                      DESCRIPTION             */
 /*                                                                        */
 /*  09-30-2020      Scott Larson            Initial Version 6.1           */
+/*  03-02-2021      Scott Larson            Modified comment(s), added    */
+/*                                            ULONG64_DEFINED,            */
+/*                                            resulting in version 6.1.5  */
 /*                                                                        */
 /**************************************************************************/
 
@@ -85,6 +88,7 @@ typedef unsigned long                           ULONG;
 typedef unsigned long long                      ULONG64;
 typedef short                                   SHORT;
 typedef unsigned short                          USHORT;
+#define ULONG64_DEFINED
 
 /* Function prototypes for this port. */
 struct  TX_THREAD_STRUCT;

ports/cortex_m33/iar/readme_threadx.txt

@@ -9,7 +9,8 @@ Import all ThreadX common and port-specific source files into an IAR project.
 Configure the project to build a library rather than an executable. This 
 results in the ThreadX run-time library file tx.a, which is needed by 
 the application.
-
+Files tx_thread_stack_error_handler.c and tx_thread_stack_error_notify.c 
+replace the common files of the same name. 
 
 2.  Demonstration System
 
@@ -48,7 +49,7 @@ Non-FPU Stack Frame:
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r4
+    0x04            r4          Software stacked GP registers
     0x08            r5
     0x0C            r6
     0x10            r7
@@ -56,7 +57,7 @@ Non-FPU Stack Frame:
     0x18            r9
     0x1C            r10
     0x20            r11
-     0x24               r0          (Hardware stack starts here!!)
+    0x24            r0          Hardware stacked registers
     0x28            r1
     0x2C            r2
     0x30            r3
@@ -70,55 +71,55 @@ FPU Stack Frame (only interrupted thread with FPU enabled):
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               s0
+    0x04            s16         Software stacked FPU registers
-     0x08               s1
+    0x08            s17
-     0x0C               s2
+    0x0C            s18
-     0x10               s3
+    0x10            s19
-     0x14               s4
+    0x14            s20
-     0x18               s5
+    0x18            s21
-     0x1C               s6
+    0x1C            s22
-     0x20               s7
+    0x20            s23
-     0x24               s8
+    0x24            s24
-     0x28               s9
+    0x28            s25
-     0x2C               s10
+    0x2C            s26
-     0x30               s11
+    0x30            s27
-     0x34               s12
+    0x34            s28
-     0x38               s13
+    0x38            s29
-     0x3C               s14
+    0x3C            s30
-     0x40               s15
+    0x40            s31
-     0x44               s16
+    0x44            r4          Software stacked registers
-     0x48               s17
+    0x48            r5
-     0x4C               s18
+    0x4C            r6
-     0x50               s19
+    0x50            r7
-     0x54               s20
+    0x54            r8
-     0x58               s21
+    0x58            r9
-     0x5C               s22
+    0x5C            r10
-     0x60               s23
+    0x60            r11
-     0x64               s24
+    0x64            r0          Hardware stacked registers
-     0x68               s25
+    0x68            r1
-     0x6C               s26
+    0x6C            r2
-     0x70               s27
+    0x70            r3
-     0x74               s28
+    0x74            r12
-     0x78               s29
+    0x78            lr
-     0x7C               s30
+    0x7C            pc
-     0x80               s31
+    0x80            xPSR
-     0x84               fpscr
+    0x84            s0          Hardware stacked FPU registers
-     0x88               r4
+    0x88            s1
-     0x8C               r5
+    0x8C            s2
-     0x90               r6
+    0x90            s3
-     0x94               r7
+    0x94            s4
-     0x98               r8
+    0x98            s5
-     0x9C               r9
+    0x9C            s6
-     0xA0               r10
+    0xA0            s7
-     0xA4               r11
+    0xA4            s8
-     0xA8               r0          (Hardware stack starts here!!)
+    0xA8            s9
-     0xAC               r1
+    0xAC            s10
-     0xB0               r2
+    0xB0            s11
-     0xB4               r3
+    0xB4            s12
-     0xB8               r12
+    0xB8            s13
-     0xBC               lr
+    0xBC            s14
-     0xC0               pc
+    0xC0            s15
-     0xC4               xPSR
+    0xC4            fpscr
 
 
 5.  Improving Performance

ports/cortex_m4/ac5/readme_threadx.txt

@@ -58,76 +58,78 @@ Non-FPU Stack Frame:
 
     Stack Offset    Stack Contents
 
-     0x00               r4
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r5
+    0x04            r4          Software stacked GP registers
-     0x08               r6
+    0x08            r5
-     0x0C               r7
+    0x0C            r6
-     0x10               r8
+    0x10            r7
-     0x14               r9
+    0x14            r8
-     0x18               r10
+    0x18            r9
-     0x1C               r11
+    0x1C            r10
-     0x20               r0          (Hardware stack starts here!!)
+    0x20            r11
-     0x24               r1
+    0x24            r0          Hardware stacked registers
-     0x28               r2
+    0x28            r1
-     0x2C               r3
+    0x2C            r2
-     0x30               r12
+    0x30            r3
-     0x34               lr
+    0x34            r12
-     0x38               pc
+    0x38            lr
-     0x3C               xPSR
+    0x3C            pc
+    0x40            xPSR
 
 FPU Stack Frame (only interrupted thread with FPU enabled):
 
     Stack Offset    Stack Contents
 
-     0x00               s0
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               s1
+    0x04            s16         Software stacked FPU registers
-     0x08               s2
+    0x08            s17
-     0x0C               s3
+    0x0C            s18
-     0x10               s4
+    0x10            s19
-     0x14               s5
+    0x14            s20
-     0x18               s6
+    0x18            s21
-     0x1C               s7
+    0x1C            s22
-     0x20               s8
+    0x20            s23
-     0x24               s9
+    0x24            s24
-     0x28               s10
+    0x28            s25
-     0x2C               s11
+    0x2C            s26
-     0x30               s12
+    0x30            s27
-     0x34               s13
+    0x34            s28
-     0x38               s14
+    0x38            s29
-     0x3C               s15
+    0x3C            s30
-     0x40               s16
+    0x40            s31
-     0x44               s17
+    0x44            r4          Software stacked registers
-     0x48               s18
+    0x48            r5
-     0x4C               s19
+    0x4C            r6
-     0x50               s20
+    0x50            r7
-     0x54               s21
+    0x54            r8
-     0x58               s22
+    0x58            r9
-     0x5C               s23
+    0x5C            r10
-     0x60               s24
+    0x60            r11
-     0x64               s25
+    0x64            r0          Hardware stacked registers
-     0x68               s26
+    0x68            r1
-     0x6C               s27
+    0x6C            r2
-     0x70               s28
+    0x70            r3
-     0x74               s29
+    0x74            r12
-     0x78               s30
+    0x78            lr
-     0x7C               s31
+    0x7C            pc
-     0x80               fpscr
+    0x80            xPSR
-     0x84               r4
+    0x84            s0          Hardware stacked FPU registers
-     0x88               r5
+    0x88            s1
-     0x8C               r6
+    0x8C            s2
-     0x90               r7
+    0x90            s3
-     0x94               r8
+    0x94            s4
-     0x98               r9
+    0x98            s5
-     0x9C               r10
+    0x9C            s6
-     0xA0               r11
+    0xA0            s7
-     0xA4               r0          (Hardware stack starts here!!)
+    0xA4            s8
-     0xA8               r1
+    0xA8            s9
-     0xAC               r2
+    0xAC            s10
-     0xB0               r3
+    0xB0            s11
-     0xB4               r12
+    0xB4            s12
-     0xB8               lr
+    0xB8            s13
-     0xBC               pc
+    0xBC            s14
-     0xC0               xPSR
+    0xC0            s15
+    0xC4            fpscr
 
 
 5.  Improving Performance

ports/cortex_m4/ac5/src/tx_thread_schedule.s

@@ -30,6 +30,10 @@
     IMPORT  _tx_execution_thread_enter
     IMPORT  _tx_execution_thread_exit
     ENDIF
+    IF :DEF:TX_LOW_POWER
+    IMPORT  tx_low_power_enter
+    IMPORT  tx_low_power_exit
+    ENDIF
 ;
 ;
     AREA    ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M4/AC5     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -73,6 +77,9 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -237,11 +244,25 @@ __tx_ts_wait
     LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
     STR     r1, [r0]                                ; Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+
+    IF:DEF:TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+    ENDIF
+
     IF:DEF:TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
     ENDIF
+
+    IF:DEF:TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+    ENDIF
+
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting
 ;

ports/cortex_m4/ac6/readme_threadx.txt

@@ -59,7 +59,7 @@ Non-FPU Stack Frame:
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r4
+    0x04            r4          Software stacked GP registers
     0x08            r5
     0x0C            r6
     0x10            r7
@@ -67,7 +67,7 @@ Non-FPU Stack Frame:
     0x18            r9
     0x1C            r10
     0x20            r11
-     0x24               r0          (Hardware stack starts here!!)
+    0x24            r0          Hardware stacked registers
     0x28            r1
     0x2C            r2
     0x30            r3
@@ -81,55 +81,55 @@ FPU Stack Frame (only interrupted thread with FPU enabled):
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               s0
+    0x04            s16         Software stacked FPU registers
-     0x08               s1
+    0x08            s17
-     0x0C               s2
+    0x0C            s18
-     0x10               s3
+    0x10            s19
-     0x14               s4
+    0x14            s20
-     0x18               s5
+    0x18            s21
-     0x1C               s6
+    0x1C            s22
-     0x20               s7
+    0x20            s23
-     0x24               s8
+    0x24            s24
-     0x28               s9
+    0x28            s25
-     0x2C               s10
+    0x2C            s26
-     0x30               s11
+    0x30            s27
-     0x34               s12
+    0x34            s28
-     0x38               s13
+    0x38            s29
-     0x3C               s14
+    0x3C            s30
-     0x40               s15
+    0x40            s31
-     0x44               s16
+    0x44            r4          Software stacked registers
-     0x48               s17
+    0x48            r5
-     0x4C               s18
+    0x4C            r6
-     0x50               s19
+    0x50            r7
-     0x54               s20
+    0x54            r8
-     0x58               s21
+    0x58            r9
-     0x5C               s22
+    0x5C            r10
-     0x60               s23
+    0x60            r11
-     0x64               s24
+    0x64            r0          Hardware stacked registers
-     0x68               s25
+    0x68            r1
-     0x6C               s26
+    0x6C            r2
-     0x70               s27
+    0x70            r3
-     0x74               s28
+    0x74            r12
-     0x78               s29
+    0x78            lr
-     0x7C               s30
+    0x7C            pc
-     0x80               s31
+    0x80            xPSR
-     0x84               fpscr
+    0x84            s0          Hardware stacked FPU registers
-     0x88               r4          
+    0x88            s1
-     0x8C               r5          
+    0x8C            s2
-     0x90               r6          
+    0x90            s3
-     0x94               r7          
+    0x94            s4
-     0x98               r8          
+    0x98            s5
-     0x9C               r9          
+    0x9C            s6
-     0xA0               r10 (sl)    
+    0xA0            s7
-     0xA4               r11         
+    0xA4            s8
-     0xA8               r0          (Hardware stack starts here!!)
+    0xA8            s9
-     0xAC               r1          
+    0xAC            s10
-     0xB0               r2          
+    0xB0            s11
-     0xB4               r3          
+    0xB4            s12
-     0xB8               r12         
+    0xB8            s13
-     0xBC               lr          
+    0xBC            s14
-     0xC0               pc          
+    0xC0            s15
-     0xC4               xPSR        
+    0xC4            fpscr
 
 
 6.  Improving Performance

ports/cortex_m4/ac6/src/tx_thread_schedule.S

@@ -25,6 +25,11 @@
     .global     _tx_thread_execute_ptr
     .global     _tx_timer_time_slice
     .global     _tx_thread_system_stack_ptr
+#ifdef TX_LOW_POWER
+    .global tx_low_power_enter
+    .global tx_low_power_exit
+#endif
+
 @
 @
     .text
@@ -35,7 +40,7 @@
 @/*  FUNCTION                                               RELEASE        */
 @/*                                                                        */
 @/*    _tx_thread_schedule                               Cortex-M4/AC6     */
-@/*                                                           6.1          */
+@/*                                                           6.1.5        */
 @/*  AUTHOR                                                                */
 @/*                                                                        */
 @/*    William E. Lamie, Microsoft Corporation                             */
@@ -69,6 +74,9 @@
 @/*    DATE              NAME                      DESCRIPTION             */
 @/*                                                                        */
 @/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+@/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+@/*                                           low power code,              */
+@/*                                           resulting in version 6.1.5   */
 @/*                                                                        */
 @/**************************************************************************/
 @VOID   _tx_thread_schedule(VOID)
@@ -238,11 +246,25 @@ __tx_ts_wait:
     LDR     r1, [r2]                                @ Pickup the next thread to execute pointer
     STR     r1, [r0]                                @ Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       @ If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      @ Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             @ Ensure no outstanding memory transactions
     WFI                                             @ Wait for interrupt
     ISB                                             @ Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       @ Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       @ Enable interrupts
     B       __tx_ts_wait                            @ Loop to continue waiting
 @

ports/cortex_m4/ghs/readme_threadx.txt

@@ -83,76 +83,78 @@ Non-FPU Stack Frame:
 
     Stack Offset    Stack Contents
 
-     0x00               r4
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r5
+    0x04            r4          Software stacked GP registers
-     0x08               r6
+    0x08            r5
-     0x0C               r7
+    0x0C            r6
-     0x10               r8
+    0x10            r7
-     0x14               r9
+    0x14            r8
-     0x18               r10
+    0x18            r9
-     0x1C               r11
+    0x1C            r10
-     0x20               r0          (Hardware stack starts here!!)
+    0x20            r11
-     0x24               r1
+    0x24            r0          Hardware stacked registers
-     0x28               r2
+    0x28            r1
-     0x2C               r3
+    0x2C            r2
-     0x30               r12
+    0x30            r3
-     0x34               lr
+    0x34            r12
-     0x38               pc
+    0x38            lr
-     0x3C               xPSR
+    0x3C            pc
+    0x40            xPSR
 
 FPU Stack Frame (only interrupted thread with FPU enabled):
 
     Stack Offset    Stack Contents
 
-     0x00               s0
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               s1
+    0x04            s16         Software stacked FPU registers
-     0x08               s2
+    0x08            s17
-     0x0C               s3
+    0x0C            s18
-     0x10               s4
+    0x10            s19
-     0x14               s5
+    0x14            s20
-     0x18               s6
+    0x18            s21
-     0x1C               s7
+    0x1C            s22
-     0x20               s8
+    0x20            s23
-     0x24               s9
+    0x24            s24
-     0x28               s10
+    0x28            s25
-     0x2C               s11
+    0x2C            s26
-     0x30               s12
+    0x30            s27
-     0x34               s13
+    0x34            s28
-     0x38               s14
+    0x38            s29
-     0x3C               s15
+    0x3C            s30
-     0x40               s16
+    0x40            s31
-     0x44               s17
+    0x44            r4          Software stacked registers
-     0x48               s18
+    0x48            r5
-     0x4C               s19
+    0x4C            r6
-     0x50               s20
+    0x50            r7
-     0x54               s21
+    0x54            r8
-     0x58               s22
+    0x58            r9
-     0x5C               s23
+    0x5C            r10
-     0x60               s24
+    0x60            r11
-     0x64               s25
+    0x64            r0          Hardware stacked registers
-     0x68               s26
+    0x68            r1
-     0x6C               s27
+    0x6C            r2
-     0x70               s28
+    0x70            r3
-     0x74               s29
+    0x74            r12
-     0x78               s30
+    0x78            lr
-     0x7C               s31
+    0x7C            pc
-     0x80               fpscr
+    0x80            xPSR
-     0x84               r4          
+    0x84            s0          Hardware stacked FPU registers
-     0x88               r5          
+    0x88            s1
-     0x8C               r6          
+    0x8C            s2
-     0x90               r7          
+    0x90            s3
-     0x94               r8          
+    0x94            s4
-     0x98               r9          
+    0x98            s5
-     0x9C               r10 (sl)    
+    0x9C            s6
-     0xA0               r11         
+    0xA0            s7
-     0xA4               r0          (Hardware stack starts here!!)
+    0xA4            s8
-     0xA8               r1          
+    0xA8            s9
-     0xAC               r2          
+    0xAC            s10
-     0xB0               r3          
+    0xB0            s11
-     0xB4               r12         
+    0xB4            s12
-     0xB8               lr          
+    0xB8            s13
-     0xBC               pc          
+    0xBC            s14
-     0xC0               xPSR        
+    0xC0            s15
+    0xC4            fpscr
 
 
 7. Improving Performance

ports/cortex_m4/ghs/src/tx_thread_schedule.arm

@@ -28,7 +28,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M4/GHS     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -62,6 +62,9 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -230,11 +233,25 @@ __tx_ts_wait:
     LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
     STR     r1, [r0]                                ; Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting
 ;

ports/cortex_m4/gnu/readme_threadx.txt

@@ -56,7 +56,7 @@ Non-FPU Stack Frame:
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r4
+    0x04            r4          Software stacked GP registers
     0x08            r5
     0x0C            r6
     0x10            r7
@@ -64,7 +64,7 @@ Non-FPU Stack Frame:
     0x18            r9
     0x1C            r10
     0x20            r11
-     0x24               r0          (Hardware stack starts here!!)
+    0x24            r0          Hardware stacked registers
     0x28            r1
     0x2C            r2
     0x30            r3
@@ -78,55 +78,55 @@ FPU Stack Frame (only interrupted thread with FPU enabled):
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               s0
+    0x04            s16         Software stacked FPU registers
-     0x08               s1
+    0x08            s17
-     0x0C               s2
+    0x0C            s18
-     0x10               s3
+    0x10            s19
-     0x14               s4
+    0x14            s20
-     0x18               s5
+    0x18            s21
-     0x1C               s6
+    0x1C            s22
-     0x20               s7
+    0x20            s23
-     0x24               s8
+    0x24            s24
-     0x28               s9
+    0x28            s25
-     0x2C               s10
+    0x2C            s26
-     0x30               s11
+    0x30            s27
-     0x34               s12
+    0x34            s28
-     0x38               s13
+    0x38            s29
-     0x3C               s14
+    0x3C            s30
-     0x40               s15
+    0x40            s31
-     0x44               s16
+    0x44            r4          Software stacked registers
-     0x48               s17
+    0x48            r5
-     0x4C               s18
+    0x4C            r6
-     0x50               s19
+    0x50            r7
-     0x54               s20
+    0x54            r8
-     0x58               s21
+    0x58            r9
-     0x5C               s22
+    0x5C            r10
-     0x60               s23
+    0x60            r11
-     0x64               s24
+    0x64            r0          Hardware stacked registers
-     0x68               s25
+    0x68            r1
-     0x6C               s26
+    0x6C            r2
-     0x70               s27
+    0x70            r3
-     0x74               s28
+    0x74            r12
-     0x78               s29
+    0x78            lr
-     0x7C               s30
+    0x7C            pc
-     0x80               s31
+    0x80            xPSR
-     0x84               fpscr
+    0x84            s0          Hardware stacked FPU registers
-     0x88               r4          
+    0x88            s1
-     0x8C               r5          
+    0x8C            s2
-     0x90               r6          
+    0x90            s3
-     0x94               r7          
+    0x94            s4
-     0x98               r8          
+    0x98            s5
-     0x9C               r9          
+    0x9C            s6
-     0xA0               r10 (sl)    
+    0xA0            s7
-     0xA4               r11         
+    0xA4            s8
-     0xA8               r0          (Hardware stack starts here!!)
+    0xA8            s9
-     0xAC               r1          
+    0xAC            s10
-     0xB0               r2          
+    0xB0            s11
-     0xB4               r3          
+    0xB4            s12
-     0xB8               r12         
+    0xB8            s13
-     0xBC               lr          
+    0xBC            s14
-     0xC0               pc          
+    0xC0            s15
-     0xC4               xPSR        
+    0xC4            fpscr
 
 
 5.  Improving Performance

ports/cortex_m4/gnu/src/tx_thread_schedule.S

@@ -27,6 +27,10 @@
     .global     _tx_thread_system_stack_ptr
     .global     _tx_execution_thread_enter
     .global     _tx_execution_thread_exit
+#ifdef TX_LOW_POWER
+    .global tx_low_power_enter
+    .global tx_low_power_exit
+#endif
 @
 @
     .text
@@ -37,7 +41,7 @@
 @/*  FUNCTION                                               RELEASE        */
 @/*                                                                        */
 @/*    _tx_thread_schedule                               Cortex-M4/GNU     */
-@/*                                                           6.1          */
+@/*                                                           6.1.5        */
 @/*  AUTHOR                                                                */
 @/*                                                                        */
 @/*    William E. Lamie, Microsoft Corporation                             */
@@ -73,6 +77,9 @@
 @/*  05-19-2020     William E. Lamie        Initial Version 6.0            */
 @/*  09-30-2020     William E. Lamie        Modified comment(s),           */
 @/*                                            resulting in version 6.1    */
+@/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+@/*                                           low power code,              */
+@/*                                           resulting in version 6.1.5   */
 @/*                                                                        */
 @/**************************************************************************/
 @VOID   _tx_thread_schedule(VOID)
@@ -242,11 +249,25 @@ __tx_ts_wait:
     LDR     r1, [r2]                                @ Pickup the next thread to execute pointer
     STR     r1, [r0]                                @ Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       @ If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      @ Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             @ Ensure no outstanding memory transactions
     WFI                                             @ Wait for interrupt
     ISB                                             @ Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       @ Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       @ Enable interrupts
     B       __tx_ts_wait                            @ Loop to continue waiting
 @

ports/cortex_m4/iar/readme_threadx.txt

@@ -61,15 +61,15 @@ Non-FPU Stack Frame:
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r4          
+    0x04            r4          Software stacked GP registers
     0x08            r5
     0x0C            r6
     0x10            r7
     0x14            r8
     0x18            r9
-     0x1C               r10 (sl)    
+    0x1C            r10
     0x20            r11
-     0x24               r0          (Hardware stack starts here!!)
+    0x24            r0          Hardware stacked registers
     0x28            r1
     0x2C            r2
     0x30            r3
@@ -83,55 +83,55 @@ FPU Stack Frame (only interrupted thread with FPU enabled):
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               s0
+    0x04            s16         Software stacked FPU registers
-     0x08               s1
+    0x08            s17
-     0x0C               s2
+    0x0C            s18
-     0x10               s3
+    0x10            s19
-     0x14               s4
+    0x14            s20
-     0x18               s5
+    0x18            s21
-     0x1C               s6
+    0x1C            s22
-     0x20               s7
+    0x20            s23
-     0x24               s8
+    0x24            s24
-     0x28               s9
+    0x28            s25
-     0x2C               s10
+    0x2C            s26
-     0x30               s11
+    0x30            s27
-     0x34               s12
+    0x34            s28
-     0x38               s13
+    0x38            s29
-     0x3C               s14
+    0x3C            s30
-     0x40               s15
+    0x40            s31
-     0x44               s16
+    0x44            r4          Software stacked registers
-     0x48               s17
+    0x48            r5
-     0x4C               s18
+    0x4C            r6
-     0x50               s19
+    0x50            r7
-     0x54               s20
+    0x54            r8
-     0x58               s21
+    0x58            r9
-     0x5C               s22
+    0x5C            r10
-     0x60               s23
+    0x60            r11
-     0x64               s24
+    0x64            r0          Hardware stacked registers
-     0x68               s25
+    0x68            r1
-     0x6C               s26
+    0x6C            r2
-     0x70               s27
+    0x70            r3
-     0x74               s28
+    0x74            r12
-     0x78               s29
+    0x78            lr
-     0x7C               s30
+    0x7C            pc
-     0x80               s31
+    0x80            xPSR
-     0x84               fpscr
+    0x84            s0          Hardware stacked FPU registers
-     0x88               r4          
+    0x88            s1
-     0x8C               r5          
+    0x8C            s2
-     0x90               r6          
+    0x90            s3
-     0x94               r7          
+    0x94            s4
-     0x98               r8          
+    0x98            s5
-     0x9C               r9          
+    0x9C            s6
-     0xA0               r10 (sl)    
+    0xA0            s7
-     0xA4               r11         
+    0xA4            s8
-     0xA8               r0          (Hardware stack starts here!!)
+    0xA8            s9
-     0xAC               r1          
+    0xAC            s10
-     0xB0               r2          
+    0xB0            s11
-     0xB4               r3          
+    0xB4            s12
-     0xB8               r12         
+    0xB8            s13
-     0xBC               lr          
+    0xBC            s14
-     0xC0               pc          
+    0xC0            s15
-     0xC4               xPSR        
+    0xC4            fpscr
 
 
 5.  Improving Performance

ports/cortex_m4/iar/src/tx_thread_schedule.s

@@ -28,6 +28,10 @@
     EXTERN  _tx_execution_thread_enter
     EXTERN  _tx_execution_thread_exit
     EXTERN  _tx_thread_preempt_disable
+#ifdef TX_LOW_POWER
+    EXTERN  tx_low_power_enter
+    EXTERN  tx_low_power_exit
+#endif
 ;
 ;
     SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M4/IAR     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -71,6 +75,9 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -236,11 +243,25 @@ __tx_ts_wait:
     LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
     STR     r1, [r0]                                ; Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting
 ;

ports/cortex_m4/keil/readme_threadx.txt

@@ -59,76 +59,78 @@ Non-FPU Stack Frame:
 
     Stack Offset    Stack Contents
 
-     0x00               r4
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r5
+    0x04            r4          Software stacked GP registers
-     0x08               r6
+    0x08            r5
-     0x0C               r7
+    0x0C            r6
-     0x10               r8
+    0x10            r7
-     0x14               r9
+    0x14            r8
-     0x18               r10
+    0x18            r9
-     0x1C               r11
+    0x1C            r10
-     0x20               r0          (Hardware stack starts here!!)
+    0x20            r11
-     0x24               r1
+    0x24            r0          Hardware stacked registers
-     0x28               r2
+    0x28            r1
-     0x2C               r3
+    0x2C            r2
-     0x30               r12
+    0x30            r3
-     0x34               lr
+    0x34            r12
-     0x38               pc
+    0x38            lr
-     0x3C               xPSR
+    0x3C            pc
+    0x40            xPSR
 
 FPU Stack Frame (only interrupted thread with FPU enabled):
 
     Stack Offset    Stack Contents
 
-     0x00               s0
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               s1
+    0x04            s16         Software stacked FPU registers
-     0x08               s2
+    0x08            s17
-     0x0C               s3
+    0x0C            s18
-     0x10               s4
+    0x10            s19
-     0x14               s5
+    0x14            s20
-     0x18               s6
+    0x18            s21
-     0x1C               s7
+    0x1C            s22
-     0x20               s8
+    0x20            s23
-     0x24               s9
+    0x24            s24
-     0x28               s10
+    0x28            s25
-     0x2C               s11
+    0x2C            s26
-     0x30               s12
+    0x30            s27
-     0x34               s13
+    0x34            s28
-     0x38               s14
+    0x38            s29
-     0x3C               s15
+    0x3C            s30
-     0x40               s16
+    0x40            s31
-     0x44               s17
+    0x44            r4          Software stacked registers
-     0x48               s18
+    0x48            r5
-     0x4C               s19
+    0x4C            r6
-     0x50               s20
+    0x50            r7
-     0x54               s21
+    0x54            r8
-     0x58               s22
+    0x58            r9
-     0x5C               s23
+    0x5C            r10
-     0x60               s24
+    0x60            r11
-     0x64               s25
+    0x64            r0          Hardware stacked registers
-     0x68               s26
+    0x68            r1
-     0x6C               s27
+    0x6C            r2
-     0x70               s28
+    0x70            r3
-     0x74               s29
+    0x74            r12
-     0x78               s30
+    0x78            lr
-     0x7C               s31
+    0x7C            pc
-     0x80               fpscr
+    0x80            xPSR
-     0x84               r4          
+    0x84            s0          Hardware stacked FPU registers
-     0x88               r5          
+    0x88            s1
-     0x8C               r6          
+    0x8C            s2
-     0x90               r7          
+    0x90            s3
-     0x94               r8          
+    0x94            s4
-     0x98               r9          
+    0x98            s5
-     0x9C               r10 (sl)    
+    0x9C            s6
-     0xA0               r11         
+    0xA0            s7
-     0xA4               r0          (Hardware stack starts here!!)
+    0xA4            s8
-     0xA8               r1          
+    0xA8            s9
-     0xAC               r2          
+    0xAC            s10
-     0xB0               r3          
+    0xB0            s11
-     0xB4               r12         
+    0xB4            s12
-     0xB8               lr          
+    0xB8            s13
-     0xBC               pc          
+    0xBC            s14
-     0xC0               xPSR        
+    0xC0            s15
+    0xC4            fpscr
 
 
 5.  Improving Performance

ports/cortex_m4/keil/src/tx_thread_schedule.s

@@ -30,6 +30,10 @@
     IMPORT  _tx_execution_thread_enter
     IMPORT  _tx_execution_thread_exit
     ENDIF
+    IF :DEF:TX_LOW_POWER
+    IMPORT  tx_low_power_enter
+    IMPORT  tx_low_power_exit
+    ENDIF
 ;
 ;
     AREA    ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M4/AC5     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -73,6 +77,9 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -237,11 +244,25 @@ __tx_ts_wait
     LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
     STR     r1, [r0]                                ; Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+
+    IF:DEF:TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+    ENDIF
+
     IF:DEF:TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
     ENDIF
+
+    IF:DEF:TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+    ENDIF
+
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting
 ;

ports/cortex_m7/ac5/readme_threadx.txt

@@ -59,76 +59,78 @@ Non-FPU Stack Frame:
 
     Stack Offset    Stack Contents
 
-     0x00               r4
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r5
+    0x04            r4          Software stacked GP registers
-     0x08               r6
+    0x08            r5
-     0x0C               r7
+    0x0C            r6
-     0x10               r8
+    0x10            r7
-     0x14               r9
+    0x14            r8
-     0x18               r10
+    0x18            r9
-     0x1C               r11
+    0x1C            r10
-     0x20               r0          (Hardware stack starts here!!)
+    0x20            r11
-     0x24               r1
+    0x24            r0          Hardware stacked registers
-     0x28               r2
+    0x28            r1
-     0x2C               r3
+    0x2C            r2
-     0x30               r12
+    0x30            r3
-     0x34               lr
+    0x34            r12
-     0x38               pc
+    0x38            lr
-     0x3C               xPSR
+    0x3C            pc
+    0x40            xPSR
 
 FPU Stack Frame (only interrupted thread with FPU enabled):
 
     Stack Offset    Stack Contents
 
-     0x00               s0
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               s1
+    0x04            s16         Software stacked FPU registers
-     0x08               s2
+    0x08            s17
-     0x0C               s3
+    0x0C            s18
-     0x10               s4
+    0x10            s19
-     0x14               s5
+    0x14            s20
-     0x18               s6
+    0x18            s21
-     0x1C               s7
+    0x1C            s22
-     0x20               s8
+    0x20            s23
-     0x24               s9
+    0x24            s24
-     0x28               s10
+    0x28            s25
-     0x2C               s11
+    0x2C            s26
-     0x30               s12
+    0x30            s27
-     0x34               s13
+    0x34            s28
-     0x38               s14
+    0x38            s29
-     0x3C               s15
+    0x3C            s30
-     0x40               s16
+    0x40            s31
-     0x44               s17
+    0x44            r4          Software stacked registers
-     0x48               s18
+    0x48            r5
-     0x4C               s19
+    0x4C            r6
-     0x50               s20
+    0x50            r7
-     0x54               s21
+    0x54            r8
-     0x58               s22
+    0x58            r9
-     0x5C               s23
+    0x5C            r10
-     0x60               s24
+    0x60            r11
-     0x64               s25
+    0x64            r0          Hardware stacked registers
-     0x68               s26
+    0x68            r1
-     0x6C               s27
+    0x6C            r2
-     0x70               s28
+    0x70            r3
-     0x74               s29
+    0x74            r12
-     0x78               s30
+    0x78            lr
-     0x7C               s31
+    0x7C            pc
-     0x80               fpscr
+    0x80            xPSR
-     0x84               r4          
+    0x84            s0          Hardware stacked FPU registers
-     0x88               r5          
+    0x88            s1
-     0x8C               r6          
+    0x8C            s2
-     0x90               r7          
+    0x90            s3
-     0x94               r8          
+    0x94            s4
-     0x98               r9          
+    0x98            s5
-     0x9C               r10 (sl)    
+    0x9C            s6
-     0xA0               r11         
+    0xA0            s7
-     0xA4               r0          (Hardware stack starts here!!)
+    0xA4            s8
-     0xA8               r1          
+    0xA8            s9
-     0xAC               r2          
+    0xAC            s10
-     0xB0               r3          
+    0xB0            s11
-     0xB4               r12         
+    0xB4            s12
-     0xB8               lr          
+    0xB8            s13
-     0xBC               pc          
+    0xBC            s14
-     0xC0               xPSR        
+    0xC0            s15
+    0xC4            fpscr
 
 
 5.  Improving Performance

ports/cortex_m7/ac5/src/tx_thread_schedule.s

@@ -30,6 +30,10 @@
     IMPORT  _tx_execution_thread_enter
     IMPORT  _tx_execution_thread_exit
     ENDIF
+    IF :DEF:TX_LOW_POWER
+    IMPORT  tx_low_power_enter
+    IMPORT  tx_low_power_exit
+    ENDIF
 ;
 ;
     AREA    ||.text||, CODE, READONLY
@@ -39,7 +43,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M7/AC5     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -73,6 +77,9 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -237,11 +244,25 @@ __tx_ts_wait
     LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
     STR     r1, [r0]                                ; Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+
+    IF:DEF:TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+    ENDIF
+
     IF:DEF:TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
     ENDIF
+
+    IF:DEF:TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+    ENDIF
+
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting
 ;

ports/cortex_m7/ac6/readme_threadx.txt

@@ -55,24 +55,82 @@ ThreadX. The top of the suspended thread's stack is pointed to by
 tx_thread_stack_ptr in the associated thread control block TX_THREAD.
 
 
+Non-FPU Stack Frame:
+
     Stack Offset    Stack Contents
 
-     0x00               r4
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r5
+    0x04            r4          Software stacked GP registers
-     0x08               r6
+    0x08            r5
-     0x0C               r7
+    0x0C            r6
-     0x10               r8
+    0x10            r7
-     0x14               r9
+    0x14            r8
-     0x18               r10
+    0x18            r9
-     0x1C               r11
+    0x1C            r10
-     0x20               r0          (Hardware stack starts here!!)
+    0x20            r11
-     0x24               r1
+    0x24            r0          Hardware stacked registers
-     0x28               r2
+    0x28            r1
-     0x2C               r3
+    0x2C            r2
-     0x30               r12
+    0x30            r3
-     0x34               lr
+    0x34            r12
-     0x38               pc
+    0x38            lr
-     0x3C               xPSR
+    0x3C            pc
+    0x40            xPSR
+
+FPU Stack Frame (only interrupted thread with FPU enabled):
+
+    Stack Offset    Stack Contents
+
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
+    0x04            s16         Software stacked FPU registers
+    0x08            s17
+    0x0C            s18
+    0x10            s19
+    0x14            s20
+    0x18            s21
+    0x1C            s22
+    0x20            s23
+    0x24            s24
+    0x28            s25
+    0x2C            s26
+    0x30            s27
+    0x34            s28
+    0x38            s29
+    0x3C            s30
+    0x40            s31
+    0x44            r4          Software stacked registers
+    0x48            r5
+    0x4C            r6
+    0x50            r7
+    0x54            r8
+    0x58            r9
+    0x5C            r10
+    0x60            r11
+    0x64            r0          Hardware stacked registers
+    0x68            r1
+    0x6C            r2
+    0x70            r3
+    0x74            r12
+    0x78            lr
+    0x7C            pc
+    0x80            xPSR
+    0x84            s0          Hardware stacked FPU registers
+    0x88            s1
+    0x8C            s2
+    0x90            s3
+    0x94            s4
+    0x98            s5
+    0x9C            s6
+    0xA0            s7
+    0xA4            s8
+    0xA8            s9
+    0xAC            s10
+    0xB0            s11
+    0xB4            s12
+    0xB8            s13
+    0xBC            s14
+    0xC0            s15
+    0xC4            fpscr
 
 
 6.  Improving Performance

ports/cortex_m7/ac6/src/tx_thread_schedule.S

@@ -25,6 +25,11 @@
     .global     _tx_thread_execute_ptr
     .global     _tx_timer_time_slice
     .global     _tx_thread_system_stack_ptr
+#ifdef TX_LOW_POWER
+    .global tx_low_power_enter
+    .global tx_low_power_exit
+#endif
+
 @
 @
     .text
@@ -35,7 +40,7 @@
 @/*  FUNCTION                                               RELEASE        */
 @/*                                                                        */
 @/*    _tx_thread_schedule                               Cortex-M7/AC6     */
-@/*                                                           6.1          */
+@/*                                                           6.1.5        */
 @/*  AUTHOR                                                                */
 @/*                                                                        */
 @/*    William E. Lamie, Microsoft Corporation                             */
@@ -69,6 +74,9 @@
 @/*    DATE              NAME                      DESCRIPTION             */
 @/*                                                                        */
 @/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+@/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+@/*                                           low power code,              */
+@/*                                           resulting in version 6.1.5   */
 @/*                                                                        */
 @/**************************************************************************/
 @VOID   _tx_thread_schedule(VOID)
@@ -237,11 +245,25 @@ __tx_ts_wait:
     LDR     r1, [r2]                                @ Pickup the next thread to execute pointer
     STR     r1, [r0]                                @ Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       @ If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      @ Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             @ Ensure no outstanding memory transactions
     WFI                                             @ Wait for interrupt
     ISB                                             @ Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       @ Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       @ Enable interrupts
     B       __tx_ts_wait                            @ Loop to continue waiting
 @

ports/cortex_m7/ghs/readme_threadx.txt

@@ -83,76 +83,78 @@ Non-FPU Stack Frame:
 
     Stack Offset    Stack Contents
 
-     0x00               r4
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r5
+    0x04            r4          Software stacked GP registers
-     0x08               r6
+    0x08            r5
-     0x0C               r7
+    0x0C            r6
-     0x10               r8
+    0x10            r7
-     0x14               r9
+    0x14            r8
-     0x18               r10
+    0x18            r9
-     0x1C               r11
+    0x1C            r10
-     0x20               r0          (Hardware stack starts here!!)
+    0x20            r11
-     0x24               r1
+    0x24            r0          Hardware stacked registers
-     0x28               r2
+    0x28            r1
-     0x2C               r3
+    0x2C            r2
-     0x30               r12
+    0x30            r3
-     0x34               lr
+    0x34            r12
-     0x38               pc
+    0x38            lr
-     0x3C               xPSR
+    0x3C            pc
+    0x40            xPSR
 
 FPU Stack Frame (only interrupted thread with FPU enabled):
 
     Stack Offset    Stack Contents
 
-     0x00               s0
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               s1
+    0x04            s16         Software stacked FPU registers
-     0x08               s2
+    0x08            s17
-     0x0C               s3
+    0x0C            s18
-     0x10               s4
+    0x10            s19
-     0x14               s5
+    0x14            s20
-     0x18               s6
+    0x18            s21
-     0x1C               s7
+    0x1C            s22
-     0x20               s8
+    0x20            s23
-     0x24               s9
+    0x24            s24
-     0x28               s10
+    0x28            s25
-     0x2C               s11
+    0x2C            s26
-     0x30               s12
+    0x30            s27
-     0x34               s13
+    0x34            s28
-     0x38               s14
+    0x38            s29
-     0x3C               s15
+    0x3C            s30
-     0x40               s16
+    0x40            s31
-     0x44               s17
+    0x44            r4          Software stacked registers
-     0x48               s18
+    0x48            r5
-     0x4C               s19
+    0x4C            r6
-     0x50               s20
+    0x50            r7
-     0x54               s21
+    0x54            r8
-     0x58               s22
+    0x58            r9
-     0x5C               s23
+    0x5C            r10
-     0x60               s24
+    0x60            r11
-     0x64               s25
+    0x64            r0          Hardware stacked registers
-     0x68               s26
+    0x68            r1
-     0x6C               s27
+    0x6C            r2
-     0x70               s28
+    0x70            r3
-     0x74               s29
+    0x74            r12
-     0x78               s30
+    0x78            lr
-     0x7C               s31
+    0x7C            pc
-     0x80               fpscr
+    0x80            xPSR
-     0x84               r4          
+    0x84            s0          Hardware stacked FPU registers
-     0x88               r5          
+    0x88            s1
-     0x8C               r6          
+    0x8C            s2
-     0x90               r7          
+    0x90            s3
-     0x94               r8          
+    0x94            s4
-     0x98               r9          
+    0x98            s5
-     0x9C               r10 (sl)    
+    0x9C            s6
-     0xA0               r11         
+    0xA0            s7
-     0xA4               r0          (Hardware stack starts here!!)
+    0xA4            s8
-     0xA8               r1          
+    0xA8            s9
-     0xAC               r2          
+    0xAC            s10
-     0xB0               r3          
+    0xB0            s11
-     0xB4               r12         
+    0xB4            s12
-     0xB8               lr          
+    0xB8            s13
-     0xBC               pc          
+    0xBC            s14
-     0xC0               xPSR        
+    0xC0            s15
+    0xC4            fpscr
 
 
 7. Improving Performance

ports/cortex_m7/ghs/src/tx_thread_schedule.arm

@@ -28,7 +28,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M7/GHS     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -62,6 +62,9 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -230,11 +233,25 @@ __tx_ts_wait:
     LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
     STR     r1, [r0]                                ; Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting
 ;

ports/cortex_m7/gnu/readme_threadx.txt

@@ -52,24 +52,82 @@ ThreadX. The top of the suspended thread's stack is pointed to by
 tx_thread_stack_ptr in the associated thread control block TX_THREAD.
 
 
+Non-FPU Stack Frame:
+
     Stack Offset    Stack Contents
 
-     0x00               r4
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r5
+    0x04            r4          Software stacked GP registers
-     0x08               r6
+    0x08            r5
-     0x0C               r7
+    0x0C            r6
-     0x10               r8
+    0x10            r7
-     0x14               r9
+    0x14            r8
-     0x18               r10
+    0x18            r9
-     0x1C               r11
+    0x1C            r10
-     0x20               r0          (Hardware stack starts here!!)
+    0x20            r11
-     0x24               r1
+    0x24            r0          Hardware stacked registers
-     0x28               r2
+    0x28            r1
-     0x2C               r3
+    0x2C            r2
-     0x30               r12
+    0x30            r3
-     0x34               lr
+    0x34            r12
-     0x38               pc
+    0x38            lr
-     0x3C               xPSR
+    0x3C            pc
+    0x40            xPSR
+
+FPU Stack Frame (only interrupted thread with FPU enabled):
+
+    Stack Offset    Stack Contents
+
+    0x00            LR          Interrupted LR (LR at time of PENDSV)
+    0x04            s16         Software stacked FPU registers
+    0x08            s17
+    0x0C            s18
+    0x10            s19
+    0x14            s20
+    0x18            s21
+    0x1C            s22
+    0x20            s23
+    0x24            s24
+    0x28            s25
+    0x2C            s26
+    0x30            s27
+    0x34            s28
+    0x38            s29
+    0x3C            s30
+    0x40            s31
+    0x44            r4          Software stacked registers
+    0x48            r5
+    0x4C            r6
+    0x50            r7
+    0x54            r8
+    0x58            r9
+    0x5C            r10
+    0x60            r11
+    0x64            r0          Hardware stacked registers
+    0x68            r1
+    0x6C            r2
+    0x70            r3
+    0x74            r12
+    0x78            lr
+    0x7C            pc
+    0x80            xPSR
+    0x84            s0          Hardware stacked FPU registers
+    0x88            s1
+    0x8C            s2
+    0x90            s3
+    0x94            s4
+    0x98            s5
+    0x9C            s6
+    0xA0            s7
+    0xA4            s8
+    0xA8            s9
+    0xAC            s10
+    0xB0            s11
+    0xB4            s12
+    0xB8            s13
+    0xBC            s14
+    0xC0            s15
+    0xC4            fpscr
 
 
 5.  Improving Performance

ports/cortex_m7/gnu/src/tx_thread_schedule.S

@@ -27,6 +27,10 @@
     .global     _tx_thread_system_stack_ptr
     .global     _tx_execution_thread_enter
     .global     _tx_execution_thread_exit
+#ifdef TX_LOW_POWER
+    .global tx_low_power_enter
+    .global tx_low_power_exit
+#endif
 @
 @
     .text
@@ -37,7 +41,7 @@
 @/*  FUNCTION                                               RELEASE        */
 @/*                                                                        */
 @/*    _tx_thread_schedule                               Cortex-M7/GNU     */
-@/*                                                           6.1          */
+@/*                                                           6.1.5        */
 @/*  AUTHOR                                                                */
 @/*                                                                        */
 @/*    William E. Lamie, Microsoft Corporation                             */
@@ -73,6 +77,9 @@
 @/*  05-19-2020     William E. Lamie        Initial Version 6.0            */
 @/*  09-30-2020     William E. Lamie        Modified comment(s),           */
 @/*                                            resulting in version 6.1    */
+@/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+@/*                                           low power code,              */
+@/*                                           resulting in version 6.1.5   */
 @/*                                                                        */
 @/**************************************************************************/
 @VOID   _tx_thread_schedule(VOID)
@@ -241,11 +248,25 @@ __tx_ts_wait:
     LDR     r1, [r2]                                @ Pickup the next thread to execute pointer
     STR     r1, [r0]                                @ Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       @ If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      @ Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             @ Ensure no outstanding memory transactions
     WFI                                             @ Wait for interrupt
     ISB                                             @ Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       @ Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       @ Enable interrupts
     B       __tx_ts_wait                            @ Loop to continue waiting
 @

ports/cortex_m7/iar/readme_threadx.txt

@@ -61,15 +61,15 @@ Non-FPU Stack Frame:
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               r4          
+    0x04            r4          Software stacked GP registers
     0x08            r5
     0x0C            r6
     0x10            r7
     0x14            r8
     0x18            r9
-     0x1C               r10 (sl)    
+    0x1C            r10
     0x20            r11
-     0x24               r0          (Hardware stack starts here!!)
+    0x24            r0          Hardware stacked registers
     0x28            r1
     0x2C            r2
     0x30            r3
@@ -83,55 +83,55 @@ FPU Stack Frame (only interrupted thread with FPU enabled):
     Stack Offset    Stack Contents
 
     0x00            LR          Interrupted LR (LR at time of PENDSV)
-     0x04               s0
+    0x04            s16         Software stacked FPU registers
-     0x08               s1
+    0x08            s17
-     0x0C               s2
+    0x0C            s18
-     0x10               s3
+    0x10            s19
-     0x14               s4
+    0x14            s20
-     0x18               s5
+    0x18            s21
-     0x1C               s6
+    0x1C            s22
-     0x20               s7
+    0x20            s23
-     0x24               s8
+    0x24            s24
-     0x28               s9
+    0x28            s25
-     0x2C               s10
+    0x2C            s26
-     0x30               s11
+    0x30            s27
-     0x34               s12
+    0x34            s28
-     0x38               s13
+    0x38            s29
-     0x3C               s14
+    0x3C            s30
-     0x40               s15
+    0x40            s31
-     0x44               s16
+    0x44            r4          Software stacked registers
-     0x48               s17
+    0x48            r5
-     0x4C               s18
+    0x4C            r6
-     0x50               s19
+    0x50            r7
-     0x54               s20
+    0x54            r8
-     0x58               s21
+    0x58            r9
-     0x5C               s22
+    0x5C            r10
-     0x60               s23
+    0x60            r11
-     0x64               s24
+    0x64            r0          Hardware stacked registers
-     0x68               s25
+    0x68            r1
-     0x6C               s26
+    0x6C            r2
-     0x70               s27
+    0x70            r3
-     0x74               s28
+    0x74            r12
-     0x78               s29
+    0x78            lr
-     0x7C               s30
+    0x7C            pc
-     0x80               s31
+    0x80            xPSR
-     0x84               fpscr
+    0x84            s0          Hardware stacked FPU registers
-     0x88               r4          
+    0x88            s1
-     0x8C               r5          
+    0x8C            s2
-     0x90               r6          
+    0x90            s3
-     0x94               r7          
+    0x94            s4
-     0x98               r8          
+    0x98            s5
-     0x9C               r9          
+    0x9C            s6
-     0xA0               r10 (sl)    
+    0xA0            s7
-     0xA4               r11         
+    0xA4            s8
-     0xA8               r0          (Hardware stack starts here!!)
+    0xA8            s9
-     0xAC               r1          
+    0xAC            s10
-     0xB0               r2          
+    0xB0            s11
-     0xB4               r3          
+    0xB4            s12
-     0xB8               r12         
+    0xB8            s13
-     0xBC               lr          
+    0xBC            s14
-     0xC0               pc          
+    0xC0            s15
-     0xC4               xPSR        
+    0xC4            fpscr
 
 
 5.  Improving Performance

ports/cortex_m7/iar/src/tx_thread_schedule.s

@@ -28,6 +28,10 @@
     EXTERN  _tx_execution_thread_enter
     EXTERN  _tx_execution_thread_exit
     EXTERN  _tx_thread_preempt_disable
+#ifdef TX_LOW_POWER
+    EXTERN  tx_low_power_enter
+    EXTERN  tx_low_power_exit
+#endif
 ;
 ;
     SECTION `.text`:CODE:NOROOT(2)
@@ -37,7 +41,7 @@
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
 ;/*    _tx_thread_schedule                               Cortex-M7/IAR     */
-;/*                                                           6.1          */
+;/*                                                           6.1.5        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */
 ;/*    William E. Lamie, Microsoft Corporation                             */
@@ -71,6 +75,9 @@
 ;/*    DATE              NAME                      DESCRIPTION             */
 ;/*                                                                        */
 ;/*  09-30-2020     William E. Lamie        Initial Version 6.1            */
+;/*  03-02-2021     Scott Larson            Modified comment(s), add       */
+;/*                                           low power code,              */
+;/*                                           resulting in version 6.1.5   */
 ;/*                                                                        */
 ;/**************************************************************************/
 ;VOID   _tx_thread_schedule(VOID)
@@ -236,11 +243,25 @@ __tx_ts_wait:
     LDR     r1, [r2]                                ; Pickup the next thread to execute pointer
     STR     r1, [r0]                                ; Store it in the current pointer
     CBNZ    r1, __tx_ts_ready                       ; If non-NULL, a new thread is ready!
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_enter                      ; Possibly enter low power mode
+    POP     {r0-r3}
+#endif
+
 #ifdef TX_ENABLE_WFI
     DSB                                             ; Ensure no outstanding memory transactions
     WFI                                             ; Wait for interrupt
     ISB                                             ; Ensure pipeline is flushed
 #endif
+
+#ifdef TX_LOW_POWER
+    PUSH    {r0-r3}
+    BL      tx_low_power_exit                       ; Exit low power mode
+    POP     {r0-r3}
+#endif
+
     CPSIE   i                                       ; Enable interrupts
     B       __tx_ts_wait                            ; Loop to continue waiting
 ;

ports/rxv2/ccrx/inc/tx_port.h

@@ -25,7 +25,7 @@
 /*                                                                        */
 /*  PORT SPECIFIC C INFORMATION                            RELEASE        */
 /*                                                                        */
-/*    tx_port.h                                            RX/CCRX        */
+/*    tx_port.h                                            RXv2/CCRX      */
 /*                                                           6.1.3        */
 /*                                                                        */
 /*  AUTHOR                                                                */
@@ -271,7 +271,7 @@ extern volatile ULONG  _tx_thread_system_state;
 
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] = 
-                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX RX/CCRX Version 6.1.3 *";
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX RXv2/CCRX Version 6.1.3 *";
 #else
 extern  CHAR                    _tx_version_id[];
 #endif

ports/rxv2/ccrx/src/tx_initialize_low_level.src

@@ -33,7 +33,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_initialize_low_level                             RX/CCRX        */
+;/*    _tx_initialize_low_level                             RXv2/CCRX      */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/ccrx/src/tx_thread_context_restore.src

@@ -44,7 +44,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_context_restore                           RX/CCRX        */
+;/*    _tx_thread_context_restore                           RXv2/CCRX      */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/ccrx/src/tx_thread_context_save.src

@@ -39,7 +39,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_context_save                              RX/CCRX        */
+;/*    _tx_thread_context_save                              RXv2/CCRX      */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/ccrx/src/tx_thread_interrupt_control.src

@@ -34,7 +34,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_interrupt_control                         RX/CCRX        */
+;/*    _tx_thread_interrupt_control                         RXv2/CCRX      */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/ccrx/src/tx_thread_schedule.src

@@ -41,7 +41,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_schedule                                  RX/CCRX        */
+;/*    _tx_thread_schedule                                  RXv2/CCRX      */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/ccrx/src/tx_thread_stack_build.src

@@ -35,7 +35,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_stack_build                               RX/CCRX        */
+;/*    _tx_thread_stack_build                               RXv2/CCRX      */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/ccrx/src/tx_thread_system_return.src

@@ -39,7 +39,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_system_return                             RX/CCRX        */
+;/*    _tx_thread_system_return                             RXv2/CCRX      */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/ccrx/src/tx_timer_interrupt.src

@@ -49,7 +49,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_timer_interrupt                                  RX/CCRX        */
+;/*    _tx_timer_interrupt                                  RXv2/CCRX      */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/gnu/inc/tx_port.h

@@ -25,7 +25,7 @@
 /*                                                                        */
 /*  PORT SPECIFIC C INFORMATION                            RELEASE        */
 /*                                                                        */
-/*    tx_port.h                                            RX/GNURX       */
+/*    tx_port.h                                            RXv2/GNURX     */
 /*                                                           6.1.3        */
 /*                                                                        */
 /*  AUTHOR                                                                */
@@ -255,7 +255,7 @@ static void _tx_thread_system_return_inline(void)
 
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] = 
-                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX RX/GNURX Version 6.1.3 *";
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX RXv2/GNURX Version 6.1.3 *";
 #else
 extern  CHAR                    _tx_version_id[];
 #endif

ports/rxv2/gnu/src/tx_initialize_low_level.S

@@ -28,7 +28,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_initialize_low_level                             RX/GNURX       */
+;/*    _tx_initialize_low_level                             RXv2/GNURX     */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/gnu/src/tx_thread_context_restore.S

@@ -45,7 +45,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_context_restore                           RX/GNURX       */
+;/*    _tx_thread_context_restore                           RXv2/GNURX     */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/gnu/src/tx_thread_context_save.S

@@ -19,17 +19,7 @@
 ;/**                                                                       */
 ;/**************************************************************************/
 ;/**************************************************************************/
-;
+
-;
-;#define TX_SOURCE_CODE
-;
-;
-;/* Include necessary system files.  */
-;
-;#include "tx_api.h"
-;#include "tx_thread.h"
-;#include "tx_timer.h"
-;
     .global     __tx_thread_system_state
     .global     __tx_thread_current_ptr
     .global     __tx_thread_system_stack_ptr
@@ -39,7 +29,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_context_save                              RX/GNURX       */
+;/*    _tx_thread_context_save                              RXv2/GNURX     */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/gnu/src/tx_thread_interrupt_control.S

@@ -19,22 +19,13 @@
 ;/**                                                                       */
 ;/**************************************************************************/
 ;/**************************************************************************/
-;
+
-;#define TX_SOURCE_CODE
-;
-;
-;/* Include necessary system files.  */
-;
-;#include "tx_api.h"
-;#include "tx_thread.h"
-;
-;
     .text
 ;/**************************************************************************/
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_interrupt_control                         RX/GNURX       */
+;/*    _tx_thread_interrupt_control                         RXv2/GNURX     */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/gnu/src/tx_thread_schedule.S

@@ -19,18 +19,7 @@
 ;/**                                                                       */
 ;/**************************************************************************/
 ;/**************************************************************************/
-;
+
-;
-;#define TX_SOURCE_CODE
-;
-;
-;/* Include necessary system files.  */
-;
-;#include "tx_api.h"
-;#include "tx_thread.h"
-;#include "tx_timer.h"
-;
-;
     .global     __tx_thread_execute_ptr
     .global     __tx_thread_current_ptr
     .global     __tx_timer_time_slice
@@ -41,7 +30,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_schedule                                  RX/GNURX       */
+;/*    _tx_thread_schedule                                  RXv2/GNURX     */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/gnu/src/tx_thread_stack_build.S

@@ -19,23 +19,13 @@
 ;/**                                                                       */
 ;/**************************************************************************/
 ;/**************************************************************************/
-;
+
-;
-;#define TX_SOURCE_CODE
-;
-;
-;/* Include necessary system files.  */
-;
-;#include "tx_api.h"
-;#include "tx_thread.h"
-;
-;
     .text
 ;/**************************************************************************/
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_stack_build                               RX/GNURX       */
+;/*    _tx_thread_stack_build                               RXv2/GNURX     */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/gnu/src/tx_thread_system_return.S

@@ -19,17 +19,7 @@
 ;/**                                                                       */
 ;/**************************************************************************/
 ;/**************************************************************************/
-;
+
-;#define TX_SOURCE_CODE
-;
-;
-;/* Include necessary system files.  */
-;
-;#include "tx_api.h"
-;#include "tx_thread.h"
-;#include "tx_timer.h"
-;
-;
     .global     __tx_thread_current_ptr
     .global     __tx_timer_time_slice
     .global     __tx_thread_schedule
@@ -39,7 +29,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_system_return                             RX/GNURX       */
+;/*    _tx_thread_system_return                             RXv2/GNURX     */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/gnu/src/tx_timer_interrupt.S

@@ -19,19 +19,7 @@
 ;/**                                                                       */
 ;/**************************************************************************/
 ;/**************************************************************************/
-;
+
-;#define TX_SOURCE_CODE
-;
-;
-;/* Include necessary system files.  */
-;
-;#include "tx_api.h"
-;#include "tx_timer.h"
-;#include "tx_thread.h"
-;
-;
-;Define Assembly language external references...
-;
     .global     __tx_timer_time_slice
     .global     __tx_timer_system_clock
     .global     __tx_timer_current_ptr
@@ -43,13 +31,13 @@
     .global     __tx_thread_context_save
     .global     __tx_thread_time_slice
     .global     __tx_thread_context_restore
-;
+
     .SECTION    P,CODE
 ;/**************************************************************************/
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_timer_interrupt                                  RX/GNURX       */
+;/*    _tx_timer_interrupt                                  RXv2/GNURX     */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/iar/inc/tx_port.h

@@ -25,7 +25,7 @@
 /*                                                                        */
 /*  PORT SPECIFIC C INFORMATION                            RELEASE        */
 /*                                                                        */
-/*    tx_port.h                                            RX/IAR         */
+/*    tx_port.h                                            RXv2/IAR       */
 /*                                                           6.1.3        */
 /*                                                                        */
 /*  AUTHOR                                                                */
@@ -263,7 +263,7 @@ extern volatile ULONG  _tx_thread_system_state;
 
 #ifdef TX_THREAD_INIT
 CHAR                            _tx_version_id[] = 
-                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX RX/IAR Version 6.1.3 *";
+                                    "Copyright (c) Microsoft Corporation. All rights reserved.  *  ThreadX RXv2/IAR Version 6.1.3 *";
 #else
 extern  CHAR                    _tx_version_id[];
 #endif

ports/rxv2/iar/src/tx_initialize_low_level.s

@@ -30,7 +30,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_initialize_low_level                             RX/IAR         */
+;/*    _tx_initialize_low_level                             RXv2/IAR       */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/iar/src/tx_thread_context_restore.s

@@ -19,18 +19,7 @@
 ;/**                                                                       */
 ;/**************************************************************************/
 ;/**************************************************************************/
-;
+
-;
-;#define TX_SOURCE_CODE
-;
-;
-;/* Include necessary system files.  */
-;
-;#include "tx_api.h"
-;#include "tx_thread.h"
-;#include "tx_timer.h"
-;
-;
     extern __tx_thread_system_state
     extern __tx_thread_current_ptr
     extern __tx_thread_preempt_disable
@@ -44,7 +33,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_context_restore                           RX/IAR         */
+;/*    _tx_thread_context_restore                           RXv2/IAR       */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/iar/src/tx_thread_context_save.s

@@ -19,17 +19,7 @@
 ;/**                                                                       */
 ;/**************************************************************************/
 ;/**************************************************************************/
-;
+
-;
-;#define TX_SOURCE_CODE
-;
-;
-;/* Include necessary system files.  */
-;
-;#include "tx_api.h"
-;#include "tx_thread.h"
-;#include "tx_timer.h"
-;
     extern __tx_thread_system_state
     extern __tx_thread_current_ptr
 
@@ -38,7 +28,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_context_save                              RX/IAR         */
+;/*    _tx_thread_context_save                              RXv2/IAR       */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/iar/src/tx_thread_interrupt_control.s

@@ -19,21 +19,13 @@
 ;/**                                                                       */
 ;/**************************************************************************/
 ;/**************************************************************************/
-;
+
-;#define TX_SOURCE_CODE
-;
-;
-;/* Include necessary system files.  */
-;
-;#include "tx_api.h"
-;#include "tx_thread.h"
-;
     section .text:CODE:ROOT
 ;/**************************************************************************/
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_interrupt_control                         RX/IAR         */
+;/*    _tx_thread_interrupt_control                         RXv2/IAR       */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/iar/src/tx_thread_schedule.s

@@ -19,18 +19,7 @@
 ;/**                                                                       */
 ;/**************************************************************************/
 ;/**************************************************************************/
-;
+
-;
-;#define TX_SOURCE_CODE
-;
-;
-;/* Include necessary system files.  */
-;
-;#include "tx_api.h"
-;#include "tx_thread.h"
-;#include "tx_timer.h"
-;
-;
     extern __tx_thread_execute_ptr
     extern __tx_thread_current_ptr
     extern __tx_timer_time_slice
@@ -41,7 +30,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_schedule                                  RX/IAR         */
+;/*    _tx_thread_schedule                                  RXv2/IAR       */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/iar/src/tx_thread_stack_build.s

@@ -27,7 +27,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_stack_build                               RX/IAR         */
+;/*    _tx_thread_stack_build                               RXv2/IAR       */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/iar/src/tx_thread_system_return.s

@@ -26,7 +26,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_thread_system_return                             RX/IAR         */
+;/*    _tx_thread_system_return                             RXv2/IAR       */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */

ports/rxv2/iar/src/tx_timer_interrupt.s

@@ -36,7 +36,7 @@
 ;/*                                                                        */
 ;/*  FUNCTION                                               RELEASE        */
 ;/*                                                                        */
-;/*    _tx_timer_interrupt                                  RX/IAR         */
+;/*    _tx_timer_interrupt                                  RXv2/IAR       */
 ;/*                                                           6.1.3        */
 ;/*  AUTHOR                                                                */
 ;/*                                                                        */