                       Microsoft's Azure RTOS ThreadX for Cortex-M7 

                                   Using the IAR Tools


1.  Building the ThreadX run-time Library

Building the ThreadX library is easy. First, open the Azure RTOS workspace
azure_rtos.eww. Next, make the TX project the "active project" in the 
IAR Embedded Workbench and select the "Make" button. You should observe 
assembly and compilation of a series of ThreadX source files. This 
results in the ThreadX run-time library file tx.a, which is needed by 
the application.


2.  Demonstration System

The ThreadX demonstration is designed to execute under the IAR debugger under 
simulation.

Building the demonstration is easy; simply open the threadx.www workspace file,
make the sample_threadx.ewp project the "active project" in the IAR Embedded 
Workbench, and select the "Make" button.

You should observe the compilation of sample_threadx.c (which is the demonstration 
application) and linking with tx.a. The resulting file sample_threadx.out is a 
binary ELF file that can be downloaded and executed on the IAR Windows-based 
Cortex-M7 simulator.


3.  System Initialization

The entry point in ThreadX for the Cortex-M7 using IAR tools is at label 
__iar_program_start. This is defined within the IAR compiler's startup code. 
In addition, this is where all static and global preset C variable 
initialization processing takes place.

The ThreadX tx_initialize_low_level.s file is responsible for setting up 
various system data structures, and a periodic timer interrupt source. 
By default, the vector area is defined at the top of cstartup_M.s, which is
a slightly modified from the base IAR file. 

The _tx_initialize_low_level function inside of tx_initialize_low_level.s
also determines the first available address for use by the application, which 
is supplied as the sole input parameter to your application definition function, 
tx_application_define. To accomplish this, a section is created in 
tx_initialize_low_level.s called FREE_MEM, which must be located after all 
other RAM sections in memory.


4.  Register Usage and Stack Frames

The following defines the saved context stack frames for context switches
that occur as a result of interrupt handling or from thread-level API calls.
All suspended threads have the same stack frame in the Cortex-M7 version of
ThreadX. The top of the suspended thread's stack is pointed to by 
tx_thread_stack_ptr in the associated thread control block TX_THREAD.

Non-FPU Stack Frame:

  Stack Offset     Stack Contents 

     0x00               LR          Interrupted LR (LR at time of PENDSV)
     0x04               r4          
     0x08               r5          
     0x0C               r6          
     0x10               r7          
     0x14               r8          
     0x18               r9          
     0x1C               r10 (sl)    
     0x20               r11         
     0x24               r0          (Hardware stack starts here!!)
     0x28               r1          
     0x2C               r2          
     0x30               r3          
     0x34               r12         
     0x38               lr          
     0x3C               pc          
     0x40               xPSR        

FPU Stack Frame (only interrupted thread with FPU enabled):

  Stack Offset     Stack Contents 

     0x00               LR          Interrupted LR (LR at time of PENDSV)
     0x04               s0
     0x08               s1
     0x0C               s2
     0x10               s3
     0x14               s4
     0x18               s5
     0x1C               s6
     0x20               s7
     0x24               s8
     0x28               s9
     0x2C               s10
     0x30               s11
     0x34               s12
     0x38               s13
     0x3C               s14
     0x40               s15
     0x44               s16
     0x48               s17
     0x4C               s18
     0x50               s19
     0x54               s20
     0x58               s21
     0x5C               s22
     0x60               s23
     0x64               s24
     0x68               s25
     0x6C               s26
     0x70               s27
     0x74               s28
     0x78               s29
     0x7C               s30
     0x80               s31
     0x84               fpscr
     0x88               r4          
     0x8C               r5          
     0x90               r6          
     0x94               r7          
     0x98               r8          
     0x9C               r9          
     0xA0               r10 (sl)    
     0xA4               r11         
     0xA8               r0          (Hardware stack starts here!!)
     0xAC               r1          
     0xB0               r2          
     0xB4               r3          
     0xB8               r12         
     0xBC               lr          
     0xC0               pc          
     0xC4               xPSR        


5.  Improving Performance

The distribution version of ThreadX is built without any compiler 
optimizations. This makes it easy to debug because you can trace or set 
breakpoints inside of ThreadX itself. Of course, this costs some 
performance. To make it run faster, you can change the ThreadX library
project to enable various compiler optimizations. 

In addition, you can eliminate the ThreadX basic API error checking by 
compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 
defined. 


6.  Interrupt Handling

The Cortex-M7 vectors start at the label __vector_table and is defined in cstartup_M.s. 
The application may modify the vector area according to its needs.


6.1 Managed Interrupts

ISRs for Cortex-M using the IAR tools can be written completely in C (or assembly
language) without any calls to _tx_thread_context_save or _tx_thread_context_restore.
These ISRs are allowed access to the ThreadX API that is available to ISRs.

ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table):

void    your_C_isr(void)
{

    /* ISR processing goes here, including any needed function calls.  */
}

ISRs written in assembly language will take the form:

        PUBLIC  your_assembly_isr
your_assembly_isr:

    PUSH    {r0, lr}

    ; ISR processing goes here, including any needed function calls.

    POP     {r0, lr}
    BX      lr


7.  IAR Thread-safe Library Support

Thread-safe support for the IAR tools is easily enabled by building the ThreadX library
and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file
should have the following line added (if not already in place):

initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application

The project options "General Options -> Library Configuration" should also have the 
"Enable thread support in library" box selected.


8. VFP Support

ThreadX for Cortex-M7 supports automatic ("lazy") VFP support, which means that applications threads 
can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread 
context - no additional setup by the application.



9.  Revision History

For generic code revision information, please refer to the readme_threadx_generic.txt
file, which is included in your distribution. The following details the revision
information associated with this specific port of ThreadX:

08-14-2020  ThreadX update of Cortex-M7/IAR port. The following files were 
            changed/added for port specific version 6.0.2:

            *.s                             Modified comments and whitespace.

06/30/2020  Initial ThreadX version 6.0.1 for Cortex-M7 using IAR's ARM tools.


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