;********************************************************
; Scatter file for Armv8-A Startup code on FVP Base model
; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
; Use, modification and redistribution of this file is subject to your
; possession of a valid DS-5 end user licence agreement and your compliance
; with all applicable terms and conditions of such licence agreement.
;********************************************************

LOAD 0x80000000
{
    EXEC +0
    {
        startup.o (StartUp, +FIRST)
        * (+RO, +RW, +ZI)
        
    }
    ;XTABLES +0 ALIGN 0x1000
    ;{
    ;   xtables.o (*) 
    ;}
    
    SYS_STACK +0 ALIGN 8 EMPTY 0x1000
    {
    }

    ;
    ; Separate heap - import symbol __use_two_region_memory
    ; in source code for this to work correctly
    ;
    ARM_LIB_HEAP     +0 ALIGN 64 EMPTY 0xA0000 {}

    ;
    ; App stacks for all CPUs
    ; All stacks and heap are aligned to a cache-line boundary
    ;
    ARM_LIB_STACK    +0 ALIGN 64 EMPTY 4 * 0x4000 {}
    
    ;
    ; Handler stacks for all CPUs
    ; All stacks and heap are aligned to a cache-line boundary
    ;
    HANDLER_STACK    +0 ALIGN 64 EMPTY 4 * 0x4000 {}
    
    ;
    ; Stacks for EL3
    ;
    EL3_STACKS       +0 ALIGN 64 EMPTY 4 * 0x1000 {}
    ;
    ; Strictly speaking, the L1 tables don't need to
    ; be so strongly aligned, but no matter
    ;
    TTB0_L1          +0 ALIGN 4096 EMPTY 0x1000 {}

    ;
    ; Various sets of L2 tables
    ;
    ; Alignment is 4KB, since the code uses a 4K page
    ; granularity - larger granularities would require
    ; correspondingly stricter alignment
    ;
    TTB0_L2_RAM      +0 ALIGN 4096 EMPTY 0x1000 {}

    TTB0_L2_PRIVATE  +0 ALIGN 4096 EMPTY 0x1000 {}

    TTB0_L2_PERIPH   +0 ALIGN 4096 EMPTY 0x1000 {}

    ;
    ; The startup code uses the end of this region to calculate
    ; the top of memory - don't place any RAM regions after it
    ;
    TOP_OF_RAM  +0 EMPTY 4 {}

    ;
    ; CS3 Peripherals is a 64MB region from 0x1c000000
    ; that includes the following:
    ; System Registers             at 0x1C010000
    ; UART0 (PL011)                at 0x1C090000
    ; Color LCD Controller (PL111) at 0x1C1F0000
    ; plus a number of others.
    ; CS3_PERIPHERALS is used by the startup code for page-table generation
    ; This region is not truly empty, but we have no
    ; predefined objects that live within it
    ;
    CS3_PERIPHERALS  0x1c000000 EMPTY 0x90000 {}

    ;
    ; Place the UART peripheral registers data structure
    ; This is only really needed if USE_SERIAL_PORT is defined, but
    ; the linker will remove unused sections if not needed
;    PL011  0x1c090000 UNINIT 0x1000
;    {
;        uart.o (+ZI)
;    }
    ; Note that some other CS3_PERIPHERALS follow this

    ;
    ; GICv3 distributor
    ;
    GICD  0x2f000000 UNINIT 0x8000
    {
        GICv3_gicd.o (.bss.distributor)
    }

    ;
    ; GICv3 redistributors
    ; 128KB for each redistributor in the system
    ;
    GICR  0x2f100000 UNINIT 0x80000
    {
        GICv3_gicr.o (.bss.redistributor)
    }
}





; Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
;
; Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without specific
; prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.

;RO AlignExpr(0x80000000, 0x1000)
;{
;    C_SYNCH_SP0 +0 ALIGN 0x80
;    {
;        vectors.o (_c_synch_sp0)
;    }
;    C_IRQ_SP0 +0 ALIGN 0x80
;    {
;        vectors.o (_c_irq_sp0)
;    }
;    C_FIQ_SP0 +0 ALIGN 0x80
;    {
;        vectors.o (_c_fiq_sp0)
;    }
;    C_SERROR_SP0 +0 ALIGN 0x80
;    {
;        vectors.o (_c_serror_sp0)
;    }
;
;    C_SYNCH_SPX +0 ALIGN 0x80
;    {
;        vectors.o (_c_synch_spx)
;    }
;    C_IRQ_SPX +0 ALIGN 0x80
;    {
;        vectors.o (_c_irq_spx)
;    }
;    C_FIQ_SPX +0 ALIGN 0x80
;    {
;        vectors.o (_c_fiq_spx)
;    }
;    C_SERROR_SPX +0 ALIGN 0x80
;    {
;        vectors.o (_c_serror_spx)
;    }
;
;    L64_SYNCH +0 ALIGN 0x80
;    {
;        vectors.o (_l64_synch)
;    }
;    L64_IRQ +0 ALIGN 0x80
;    {
;        vectors.o (_l64_irq)
;    }
;    L64_FIQ +0 ALIGN 0x80
;    {
;        vectors.o (_l64_fiq)
;    }
;    L64_SERROR +0 ALIGN 0x80
;    {
;        vectors.o (_l64_serror)
;    }
;
;    L32_SYNCH +0 ALIGN 0x80
;    {
;        vectors.o (_l32_synch)
;    }
;    L32_IRQ +0 ALIGN 0x80
;    {
;        vectors.o (_l32_irq)
;    }
;    L32_FIQ +0 ALIGN 0x80
;    {
;        vectors.o (_l32_fiq)
;    }
;    L32_SERROR +0 ALIGN 0x80
;    {
;        vectors.o (_l32_serror)
;    }
;
;    ROSEC +0 ALIGN 8
;    {
;        *( +RO )
;    }
;    
;    XTABLES +0 ALIGN 0x1000
;    {
;        xtables.o (*) 
;    }
;}
;
;RW AlignExpr(ImageLimit(XTABLES), 0x1000)
;{   
;    RWSEC +0
;    {
;        *( +RW )
;    }
;    
;    ZISEC +0
;    {
;        *( +ZI )
;    }
;    
;    SYS_STACK +0 ALIGN 8 EMPTY 0x1000
;    {
;    }
;    
;    ; 512 MiB heap
;    HEAP +0 ALIGN 8 EMPTY 0x10000000
;    {
;    }
;    
;    ; Free Memory section
;    FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000
;    {
;    }
;
;    ; Per-CPU 128 MiB task stacks
;    TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000)
;    {
;    }
;    
;    ; Per-CPU 128 MiB handler stacks
;    HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000)
;    {
;    }
;}
