mirror of
https://github.com/seL4/seL4.git
synced 2026-04-04 22:39:54 +00:00
476 lines
13 KiB
Plaintext
476 lines
13 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only or MIT */
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/* Copyright (c) 2019-2020 Microchip Technology Inc. */
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "SiFive,FU540G-dev", "fu540-dev", "sifive-dev";
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model = "SiFive,FU540G";
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L45: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <1000000>;
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L8: cpu@0 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <16384>;
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next-level-cache = <&L0 &L26>;
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reg = <0>;
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riscv,isa = "rv64imac";
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sifive,dtim = <&L6>;
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sifive,itim = <&L5>;
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status = "okay";
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L4: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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L12: cpu@1 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&L0 &L26>;
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reg = <1>;
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riscv,isa = "rv64imafdc";
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sifive,itim = <&L10>;
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status = "okay";
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tlb-split;
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L9: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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L16: cpu@2 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&L0 &L26>;
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reg = <2>;
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riscv,isa = "rv64imafdc";
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sifive,itim = <&L14>;
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status = "okay";
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tlb-split;
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L13: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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L20: cpu@3 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&L0 &L26>;
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reg = <3>;
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riscv,isa = "rv64imafdc";
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sifive,itim = <&L18>;
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status = "okay";
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tlb-split;
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L17: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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L24: cpu@4 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&L0 &L26>;
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reg = <4>;
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riscv,isa = "rv64imafdc";
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sifive,itim = <&L22>;
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status = "okay";
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tlb-split;
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L21: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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L40: memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x40000000>;
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clocks = <&clkcfg 26>;
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};
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L44: soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus";
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ranges;
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L7: bus-error-unit@1700000 {
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compatible = "sifive,buserror0";
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interrupt-parent = <&L1>;
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interrupts = <182>;
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reg = <0x0 0x1700000 0x0 0x1000>;
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reg-names = "control";
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};
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L11: bus-error-unit@1701000 {
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compatible = "sifive,buserror0";
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interrupt-parent = <&L1>;
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interrupts = <183>;
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reg = <0x0 0x1701000 0x0 0x1000>;
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reg-names = "control";
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};
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L15: bus-error-unit@1702000 {
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compatible = "sifive,buserror0";
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interrupt-parent = <&L1>;
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interrupts = <184>;
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reg = <0x0 0x1702000 0x0 0x1000>;
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reg-names = "control";
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};
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L19: bus-error-unit@1703000 {
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compatible = "sifive,buserror0";
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interrupt-parent = <&L1>;
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interrupts = <185>;
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reg = <0x0 0x1703000 0x0 0x1000>;
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reg-names = "control";
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};
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L23: bus-error-unit@1704000 {
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compatible = "sifive,buserror0";
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interrupt-parent = <&L1>;
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interrupts = <186>;
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reg = <0x0 0x1704000 0x0 0x1000>;
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reg-names = "control";
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};
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L0: cache-controller@2010000 {
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <2048>;
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cache-size = <2097152>;
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cache-unified;
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compatible = "sifive,ccache0", "cache";
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interrupt-parent = <&L1>;
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interrupts = <1 2 3 4>;
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next-level-cache = <&L40 &L42>;
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reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x200000>;
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reg-names = "control", "sideband";
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};
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L2: clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&L4 3 &L4 7 &L9 3 &L9 7 &L13 3 &L13 7 &L17 3 &L17 7 &L21 3 &L21 7>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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reg-names = "control";
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};
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L35: cplex_d0@20000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x20000000 0x0 0x20000000 0x8000000 0x30000000 0x0 0x30000000 0x30000000>;
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};
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L36: cplex_d1@28000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x28000000 0x0 0x28000000 0x8000000>;
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};
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L37: cplex_f0@60000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges = <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000 0x20 0x0 0x20 0x0 0x10 0x0>;
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};
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L38: cplex_f1@e0000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges = <0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000 0x30 0x0 0x30 0x0 0x10 0x0>;
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};
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L39: cplex_ncache@c0000000 {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges = <0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000 0x14 0x0 0x14 0x0 0x8 0x0>;
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};
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L3: debug-controller@0 {
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compatible = "sifive,debug-013", "riscv,debug-013";
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interrupts-extended = <&L4 65535 &L9 65535 &L13 65535 &L17 65535 &L21 65535>;
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reg = <0x0 0x0 0x0 0x1000>;
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reg-names = "control";
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};
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L27: dma@3000000 {
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#dma-cells = <1>;
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compatible = "riscv,dma0";
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dma-channels = <4>;
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dma-requests = <0>;
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interrupt-parent = <&L1>;
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interrupts = <5 6 7 8 9 10 11 12>;
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reg = <0x0 0x3000000 0x0 0x100000>;
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reg-names = "control";
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riscv,dma-pools = <1>;
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};
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L6: dtim@1000000 {
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compatible = "sifive,dtim0";
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reg = <0x0 0x1000000 0x0 0x2000>;
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reg-names = "mem";
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};
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L26: error-device@18000000 {
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compatible = "sifive,error0";
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reg = <0x0 0x18000000 0x0 0x8000000>;
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reg-names = "mem";
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};
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L28: global-external-interrupts {
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interrupt-parent = <&L1>;
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interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181>;
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};
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L1: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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compatible = "riscv,plic0";
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interrupt-controller;
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interrupts-extended = <&L4 11 &L9 11 &L9 9 &L13 11 &L13 9 &L17 11 &L17 9 &L21 11 &L21 9>;
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reg = <0x0 0xc000000 0x0 0x4000000>;
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reg-names = "control";
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riscv,max-priority = <7>;
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riscv,ndev = <186>;
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};
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L5: itim@1800000 {
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compatible = "sifive,itim0";
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reg = <0x0 0x1800000 0x0 0x4000>;
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reg-names = "mem";
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};
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L10: itim@1808000 {
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compatible = "sifive,itim0";
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reg = <0x0 0x1808000 0x0 0x8000>;
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reg-names = "mem";
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};
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L14: itim@1810000 {
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compatible = "sifive,itim0";
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reg = <0x0 0x1810000 0x0 0x8000>;
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reg-names = "mem";
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};
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L18: itim@1818000 {
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compatible = "sifive,itim0";
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reg = <0x0 0x1818000 0x0 0x8000>;
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reg-names = "mem";
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};
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L22: itim@1820000 {
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compatible = "sifive,itim0";
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reg = <0x0 0x1820000 0x0 0x8000>;
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reg-names = "mem";
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};
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L29: local-external-interrupts-0 {
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interrupt-parent = <&L4>;
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interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63>;
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};
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L30: local-external-interrupts-1 {
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interrupt-parent = <&L9>;
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interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63>;
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};
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L31: local-external-interrupts-2 {
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interrupt-parent = <&L13>;
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interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63>;
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};
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L32: local-external-interrupts-3 {
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interrupt-parent = <&L17>;
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interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63>;
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};
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L33: local-external-interrupts-4 {
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interrupt-parent = <&L21>;
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interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63>;
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};
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L42: rom@a000000 {
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compatible = "ucbbar,cacheable-zero0";
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reg = <0x0 0xa000000 0x0 0x2000000>;
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reg-names = "mem";
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};
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L25: teststatus@4000 {
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compatible = "sifive,test0";
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reg = <0x0 0x4000 0x0 0x1000>;
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reg-names = "control";
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};
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L41: wcb@2020000 {
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compatible = "sifive,wcb0";
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reg = <0x0 0x2020000 0x0 0x1000>;
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reg-names = "control";
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};
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};
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chosen {
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stdout-path = "/serial@20000000:115200n8";
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bootargs = "console=ttyS0,115200n8 ";
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};
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refclk: refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <600000000>;
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clock-output-names = "msspllclk";
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};
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clkcfg: clkcfg@20002000 {
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compatible = "microchip,pfsoc-clkcfg";
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reg = <0x0 0x20002000 0x0 0x1000>;
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reg-names = "mss_sysreg";
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clocks = <&refclk>;
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#clock-cells = <1>;
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clock-output-names = "cpuclk", "axiclk", "ahbclk", "ENVMclk", "MAC0clk", "MAC1clk", "MMCclk", "TIMERclk", "MMUART0clk", "MMUART1clk", "MMUART2clk", "MMUART3clk", "MMUART4clk", "SPI0clk", "SPI1clk", "I2C0clk", "I2C1clk", "CAN0clk", "CAN1clk", "USBclk", "RESERVED", "RTCclk", "QSPIclk", "GPIO0clk", "GPIO1clk", "GPIO2clk", "DDRCclk", "FIC0clk", "FIC1clk", "FIC2clk", "FIC3clk", "ATHENAclk", "CFMclk";
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};
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serial0: serial@20000000 {
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compatible = "ns16550a";
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reg = <0x0 0x20000000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&L1>;
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interrupts = <90>;
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current-speed = <115200>;
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clock-frequency = <150000000>;
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clocks = <&clkcfg 8>;
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status = "okay";
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};
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serial1: serial@20100000 {
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compatible = "ns16550a";
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reg = <0x0 0x20100000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&L1>;
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interrupts = <91>;
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current-speed = <115200>;
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clocks = <&clkcfg 9>;
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status = "okay";
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};
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serial2: serial@20102000 {
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compatible = "ns16550a";
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reg = <0x0 0x20102000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&L1>;
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interrupts = <92>;
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current-speed = <115200>;
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clocks = <&clkcfg 10>;
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status = "okay";
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};
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serial3: serial@20104000 {
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compatible = "ns16550a";
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reg = <0x0 0x20104000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&L1>;
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interrupts = <93>;
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current-speed = <115200>;
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clocks = <&clkcfg 11>;
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status = "okay";
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};
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/* emmc: sdhc@20008000 {
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compatible = "cdns,sd4hc";
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reg = <0x0 0x20008000 0x0 0x1000>;
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interrupt-parent = <&L1>;
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interrupts = <88>;
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pinctrl-names = "default";
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clocks = <&clkcfg 6>;
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bus-width = <4>;
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cap-mmc-highspeed;
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max-frequency = <200000000>;
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};*/
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/*
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sdcard: sdhc@20008000 {
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compatible = "cdns,sd4hc";
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reg = <0x0 0x20008000 0x0 0x1000>;
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interrupt-parent = <&L1>;
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interrupts = <88>;
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pinctrl-names = "default";
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clocks = <&clkcfg 6>;
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bus-width = <4>;
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cap-sd-highspeed;
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max-frequency = <200000000>;
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};
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*/
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/* emac0: ethernet@20110000 {
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compatible = "cdns,macb";
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reg = <0x0 0x20110000 0x0 0x2000>;
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interrupt-parent = <&L1>;
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interrupts = <64 65 66 67>;
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mac-address = [56 34 12 00 FC 00];
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phy-mode = "sgmii";
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clocks = <&clkcfg 4>, <&clkcfg 1>;
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clock-names = "pclk", "hclk";
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@8 {
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reg = <8>;
|
|
ti,fifo-depth = <0x01>;
|
|
};
|
|
};
|
|
*/
|
|
emac1: ethernet@20112000 {
|
|
compatible = "cdns,macb";
|
|
reg = <0x0 0x20112000 0x0 0x2000>;
|
|
interrupt-parent = <&L1>;
|
|
interrupts = <70 71 72 73>;
|
|
mac-address = [56 34 12 00 FC 00];
|
|
phy-mode = "sgmii";
|
|
clocks = <&clkcfg 5>, <&clkcfg 2>;
|
|
clock-names = "pclk", "hclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
phy1: ethernet-phy@9 {
|
|
reg = <9>;
|
|
ti,fifo-depth = <0x01>;
|
|
};
|
|
};
|
|
|
|
timer0: timer@20125000 {
|
|
compatible = "timer";
|
|
status = "okay";
|
|
reg = <0x0 0x20125000 0x0 0x1000>;
|
|
interrupt-parent = <&L1>;
|
|
interrupts = <82 83>;
|
|
timer-width = < 0x20 >;
|
|
};
|
|
|
|
};
|