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API-master
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54
CONTRIBUTORS.md
Normal file
54
CONTRIBUTORS.md
Normal file
@@ -0,0 +1,54 @@
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Contributors
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------------
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People who contributed to the seL4 code, design, or documentation in this
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repository (in alphabetical order).
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* June Andronick, NICTA & UNSW
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* Ali Akguel, NICTA
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* Joel Beeren, NICTA
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* Bernard Blackham, NICTA & UNSW
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* Timothy Bourke, NICTA
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* Andrew Boyton, NICTA & UNSW
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* Matthew Brassil, NICTA
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* Aleksander Budzynowski, NICTA & UNSW
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* Manuel Chakravarty, NICTA & UNSW
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* Xi Ma Chen, NICTA
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* Nahida Chowdhury, NICTA
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* Peter Chubb, NICTA
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* David Cock, NICTA & UNSW
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* Adrian Danis, NICTA
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* Matthias Daum, NICTA & UNSW
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* Philip Derrin, NICTA
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* Dhammika Elkaduwe, NICTA & UNSW
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* Kevin Elphinstone, NICTA & UNSW
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* Matthew Fernandez, NICTA & UNSW
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* Peter Gammie, NICTA
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* Xin Gao, NICTA
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* David Greenaway, NICTA & UNSW
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* Matthew Grosvenor, NICTA
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* Lukas Haenel, NICTA
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* Gernot Heiser, NICTA & UNSW
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* Benjamin Kalman, NICTA
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* Justin King-Lacroix, NICTA
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* Gerwin Klein, NICTA & UNSW
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* Rafal Kolanski, NICTA & UNSW
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* Alexander Kroh, NICTA
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* Etienne Le Sueur, NICTA & UNSW
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* Corey Lewis, NICTA
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* Japheth Lim, NICTA
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* Anna Lyons, NICTA & UNSW
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* Stephanie McArthur, NICTA
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* Sam McNally, NICTA
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* Toby Murray, NICTA & UNSW
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* Ameya Palande, NICTA
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* Max R.D. Parmer
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* Sean Peters, NICTA
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* Simon Rodgers, NICTA
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* Sean Seefried, NICTA
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* Thomas Sewell, NICTA & UNSW
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* Michael von Tessin, NICTA & UNSW
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* Adam Walker, NICTA
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* James Wilmot, NICTA
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* Simon Winwood, NICTA
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* Jiawei Xie, NICTA
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14
Kconfig
14
Kconfig
@@ -55,13 +55,6 @@ config ARCH_IA32
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help
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Support for ARM1136JF-S
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config ARM926EJ_S
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bool "ARM926EJ-S"
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depends on ARCH_ARM
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select ARCH_ARM_V5
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help
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Support for ARM926EJ_S
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config ARM_CORTEX_A8
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bool "Cortex A8"
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depends on ARCH_ARM
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@@ -97,13 +90,6 @@ config ARCH_IA32
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help
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Support for the KZM platform
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config PLAT_INTEGRATORCP
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bool "IntegratorCP Platform"
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depends on ARCH_ARM
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depends on ARM926EJ_S
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help
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Support for the IntegratorCP platform
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config PLAT_OMAP3
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bool "OMAP3 (BeagleBoard)"
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depends on ARCH_ARM
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4
Makefile
4
Makefile
@@ -17,7 +17,7 @@
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ARCH_LIST:=arm ia32
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CPU_LIST:=arm1136jf-s ixp420 cortex-a8 cortex-a9 cortex-a15
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PLAT_LIST:=imx31 pc99 integratorcp ixp420 omap3 am335x exynos4 exynos5 imx6 apq8064
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PLAT_LIST:=imx31 pc99 ixp420 omap3 am335x exynos4 exynos5 imx6 apq8064
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ARMV_LIST:=armv6 armv7-a
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ifndef SOURCE_ROOT
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@@ -147,7 +147,7 @@ default: all
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### Paths
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############################################################
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PYTHONPATH = ${SOURCE_ROOT}/tools
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PYTHONPATH := ${PYTHONPATH}:${SOURCE_ROOT}/tools
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export PYTHONPATH
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vpath %.c ${SOURCE_ROOT}
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33
README.md
33
README.md
@@ -1,10 +1,10 @@
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<!--
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<!--
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Copyright 2014, General Dynamics C4 Systems
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This software may be distributed and modified according to the terms of
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the GNU General Public License version 2. Note that NO WARRANTY is provided.
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See "LICENSE_GPLv2.txt" for details.
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@TAG(GD_GPL)
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-->
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@@ -13,25 +13,36 @@ The seL4 Repository
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This repository contains the source code of seL4 microkernel.
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For details about the seL4 microkernel, including details about its formal
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correctness proof, please see the [`sel4.systems`][1] website and associated
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[FAQ][2].
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We welcome contributions to seL4. Please see the website for information
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on [how to contribute][3].
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This repository is usually not used in isolation, but as part of the build
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system in a larger project.
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[1]: http://sel4.systems/
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[2]: http://sel4.systems/FAQ/
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[3]: http://sel4.systems/Contributing/
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Repository Overview
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-------------------
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* `include` and `src`: C and ASM source code of seL4
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* `tools`: build tools
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* `haskell`: Haskell model of the seL4 kernel,
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* `haskell`: Haskell model of the seL4 kernel,
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kept in sync with the C version.
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* `libsel4`: C bindings for the seL4 ABI
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* `manual`: LaTeX sourced of the seL4 reference manual
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* `manual`: LaTeX sources of the seL4 reference manual
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Build Instructions
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------------------
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tl;dr:
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tl;dr:
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TOOLPREFIX=arm-none-eabi- ARCH=arm PLAT=imx31 ARMV=armv6 CPU=arm1136jf-s \
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make
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@@ -39,10 +50,10 @@ tl;dr:
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The kernel source requires a cross-compiler for the target architecture. To
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build using `make`, follow these instructions:
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* Ensure that the appropriate cross-compiler for your target
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* Ensure that the appropriate cross-compiler for your target
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architecture is installed.
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* Set the `TOOLPREFIX` environment variable to your cross-compiler's
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* Set the `TOOLPREFIX` environment variable to your cross-compiler's
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prefix. E.g. `arm-none-eabi-`.
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* Set the `ARCH`, `PLAT`, `ARMV` and `CPU` variables for the intended target
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@@ -54,9 +65,13 @@ build using `make`, follow these instructions:
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arm | omap3 | armv7-a | cortex-a8
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arm | am335x | armv7-a | cortex-a8
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ia32 | pc99 | |
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* For a debug build, append `DEBUG=y`.
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See the seL4 website for more [comprehensive build instructions][4].
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[4]: http://sel4.systems/Download/
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License
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=======
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@@ -1,4 +1,4 @@
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#!/usr/bin/python
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#!/usr/bin/env python
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#
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# Copyright 2014, NICTA
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#
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@@ -1,4 +1,4 @@
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#!/usr/bin/python
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#!/usr/bin/env python
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#
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# Copyright 2014, NICTA
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#
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@@ -440,6 +440,12 @@ try_init_kernel(
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return false;
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}
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/* Before creating the initial thread (which also switches to it)
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* we clean the cache so that any page table information written
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* as a result of calling create_frames_of_region will be correctly
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* read by the hardware page table walker */
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cleanInvalidateL1Caches();
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/* create the initial thread */
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if (!create_initial_thread(
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root_cnode_cap,
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@@ -22,6 +22,7 @@
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/* Available physical memory regions on platform (RAM) */
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/* NOTE: Regions are not allowed to be adjacent! */
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/* and must be page-aligned */
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const p_region_t BOOT_RODATA avail_p_regs[] = {
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/* 2 GiB -1 page to prevent uin32_t overflow */
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{ /* .start = */ 0x80000000, /* .end = */ 0xfffff000 }
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@@ -38,7 +39,10 @@ get_avail_p_reg(unsigned int i)
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{
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return avail_p_regs[i];
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}
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/*
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* We're limited to one page of boot data.
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* Exclude some devices.
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*/
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const p_region_t BOOT_RODATA dev_p_regs[] = {
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{ /* .start */ RPM_PADDR , /* .end */ RPM_PADDR + (1 << PAGE_BITS) },
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{ /* .start */ RPM_TIMERS_PADDR , /* .end */ RPM_TIMERS_PADDR + (1 << PAGE_BITS) },
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@@ -145,27 +149,49 @@ const p_region_t BOOT_RODATA dev_p_regs[] = {
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{ /* .start */ SIC_APU_PADDR , /* .end */ SIC_APU_PADDR + (1 << PAGE_BITS) },
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{ /* .start */ SIC_NON_SECURE_PADDR , /* .end */ SIC_NON_SECURE_PADDR + (1 << PAGE_BITS) },
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{ /* .start */ INTCTL0_PADDR , /* .end */ INTCTL0_PADDR + (1 << PAGE_BITS) },
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#if (INTCTL1_PADDR & 0xfff) == 0
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{ /* .start */ INTCTL1_PADDR , /* .end */ INTCTL1_PADDR + (1 << PAGE_BITS) },
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#endif
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#if (INTCTL2_PADDR & 0xfff) == 0
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{ /* .start */ INTCTL2_PADDR , /* .end */ INTCTL2_PADDR + (1 << PAGE_BITS) },
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#endif
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#if (INTCTL3_PADDR & 0xfff) == 0
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{ /* .start */ INTCTL3_PADDR , /* .end */ INTCTL3_PADDR + (1 << PAGE_BITS) },
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#endif
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#if (INTCTL4_PADDR & 0xfff) == 0
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{ /* .start */ INTCTL4_PADDR , /* .end */ INTCTL4_PADDR + (1 << PAGE_BITS) },
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#endif
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#if (INTCTL5_PADDR & 0xfff) == 0
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{ /* .start */ INTCTL5_PADDR , /* .end */ INTCTL5_PADDR + (1 << PAGE_BITS) },
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#endif
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#if (INTCTL6_PADDR & 0xfff) == 0
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{ /* .start */ INTCTL6_PADDR , /* .end */ INTCTL6_PADDR + (1 << PAGE_BITS) },
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#endif
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#if (INTCTL7_PADDR & 0xfff) == 0
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{ /* .start */ INTCTL7_PADDR , /* .end */ INTCTL7_PADDR + (1 << PAGE_BITS) },
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#endif
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{ /* .start */ SDC2_PADDR , /* .end */ SDC2_PADDR + (1 << PAGE_BITS) },
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#if (SDC2_DML_PADDR & 0xfff) == 0
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{ /* .start */ SDC2_DML_PADDR , /* .end */ SDC2_DML_PADDR + (1 << PAGE_BITS) },
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#endif
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{ /* .start */ SDC2_BAM_PADDR , /* .end */ SDC2_BAM_PADDR + (1 << PAGE_BITS) },
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{ /* .start */ SDC3_PADDR , /* .end */ SDC3_PADDR + (1 << PAGE_BITS) },
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#if (SDC3_DML_PADDR & 0xfff) == 0
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{ /* .start */ SDC3_DML_PADDR , /* .end */ SDC3_DML_PADDR + (1 << PAGE_BITS) },
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#endif
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{ /* .start */ SDC3_BAM_PADDR , /* .end */ SDC3_BAM_PADDR + (1 << PAGE_BITS) },
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{ /* .start */ SDC4_PADDR , /* .end */ SDC4_PADDR + (1 << PAGE_BITS) },
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#if (SDC4_DML_PADDR & 0xfff) == 0
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{ /* .start */ SDC4_DML_PADDR , /* .end */ SDC4_DML_PADDR + (1 << PAGE_BITS) },
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#endif
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{ /* .start */ SDC4_BAM_PADDR , /* .end */ SDC4_BAM_PADDR + (1 << PAGE_BITS) },
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{ /* .start */ BAM_DMA_PADDR , /* .end */ BAM_DMA_PADDR + (1 << PAGE_BITS) },
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{ /* .start */ BAM_DMA_BAM_PADDR , /* .end */ BAM_DMA_BAM_PADDR + (1 << PAGE_BITS) },
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{ /* .start */ BAM_DMA_BAM_XPU_PADDR , /* .end */ BAM_DMA_BAM_XPU_PADDR + (1 << PAGE_BITS) },
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{ /* .start */ SDC1_PADDR , /* .end */ SDC1_PADDR + (1 << PAGE_BITS) },
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#if (SDC1_DML_PADDR & 0xfff) == 0
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{ /* .start */ SDC1_DML_PADDR , /* .end */ SDC1_DML_PADDR + (1 << PAGE_BITS) },
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#endif
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{ /* .start */ SDC1_BAM_PADDR , /* .end */ SDC1_BAM_PADDR + (1 << PAGE_BITS) },
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{ /* .start */ SPS_GSBI1_PADDR , /* .end */ SPS_GSBI1_PADDR + (1 << PAGE_BITS) },
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{ /* .start */ SPS_UART1_DM_PADDR , /* .end */ SPS_UART1_DM_PADDR + (1 << PAGE_BITS) },
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@@ -1,4 +1,4 @@
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#!/usr/bin/python
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#!/usr/bin/env python
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#
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# Copyright 2014, NICTA
|
||||
#
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||||
|
||||
@@ -1,4 +1,4 @@
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#!/usr/bin/python
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#!/usr/bin/env python
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#
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# Copyright 2014, NICTA
|
||||
#
|
||||
|
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Reference in New Issue
Block a user