Added initial support for Cheshire platform

Signed-off-by: Matt Rossouw <matthew.rossouw@unsw.edu.au>

tools/dts/cheshire.dts

@@ -0,0 +1,118 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Nicole Narr <narrn@student.ethz.ch>
+// Christopher Reinwardt <creinwar@student.ethz.ch>
+// Axel Vanoni <axvanoni@student.ethz.ch>
+
+/dts-v1/;
+/ {
+  #address-cells = <2>;
+  #size-cells = <2>;
+  compatible = "eth,cheshire-dev";
+  model = "eth,cheshire";
+  chosen {
+    console = "/soc/serial@3002000";
+    stdout-path = "/soc/serial@3002000:115200";
+    linux,initrd-start = <0x84000000>;
+    linux,initrd-end = <0x85600000>;
+  };
+  memory@80000000 {
+    device_type = "memory";
+    reg = <0x0 0x80000000 0x0 0x40000000>;
+  };
+  cpus {
+    #address-cells = <1>;
+    #size-cells = <0>;
+    timebase-frequency = <1000000>; // 1 MHz
+    CPU0: cpu@0 {
+      device_type = "cpu";
+      status = "okay";
+      compatible = "eth,cheshire", "riscv";
+      clock-frequency = <50000000>; // 50 MHz
+      riscv,isa = "rv64imafdch";
+      mmu-type = "riscv,sv39";
+      tlb-split;
+      reg = <0>;
+      CPU0_intc: interrupt-controller {
+        #address-cells = <0>;
+        #interrupt-cells = <1>;
+        interrupt-controller;
+        compatible = "riscv,cpu-intc";
+      };
+    };
+  };
+  soc: soc {
+    #address-cells = <2>;
+    #size-cells = <2>;
+    compatible = "eth,cheshire-bare-soc", "simple-bus";
+    ranges;
+    debug@0 {
+      compatible = "riscv,debug-013";
+      reg-names = "control";
+      reg = <0x0 0x0 0x0 0x1000>;
+    };
+    axi_llc@3001000 {
+      compatible = "eth,axi-llc";
+      reg = <0x0 0x3001000 0x0 0x5000>;
+    };
+    ddr_link: memory-controller@3006000 {
+      compatible = "eth,ddr-link";
+      reg = <0x0 0x3006000 0x0 0x1000>;
+    };
+    serial@3002000 {
+      compatible = "ns16550a";
+      clock-frequency = <50000000>; // 50 MHz
+      current-speed = <115200>;
+      interrupt-parent = <&PLIC0>;
+      interrupts = <1>;
+      reg = <0x0 0x3002000 0x0 0x1000>;
+      reg-shift = <2>; // regs are spaced on 32 bit boundary
+      reg-io-width = <4>; // only 32-bit access are supported
+    };
+    i2c@3003000 {
+      compatible = "eth,i2c";
+      interrupt-parent = <&PLIC0>;
+      interrupts = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 16>;
+      reg = <0x0 0x3003000 0x0 0x1000>;
+    };
+    spi@3004000 {
+      compatible = "opentitan,spi-host", "lowrisc,spi";
+      interrupt-parent = <&PLIC0>;
+      interrupts = <17 18>;
+      reg = <0x0 0x3004000 0x0 0x1000>;
+      clock-frequency = <50000000>;
+      max-frequency = <25000000>;
+      #address-cells = <1>;
+      #size-cells = <0>;
+      mmc@0 {
+        compatible = "mmc-spi-slot";
+        reg = <0>;
+        spi-max-frequency = <25000000>;
+        voltage-ranges = <3300 3300>;
+        disable-wp;
+      };
+    };
+    vga@3007000 {
+      compatible = "eth,axi-vga";
+      reg = <0x0 0x3007000 0x0 0x1000>;
+    };
+    clint@2040000 {
+      compatible = "riscv,clint0";
+      interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
+      reg-names = "control";
+      reg = <0x0 0x2040000 0x0 0x040000>;
+    };
+    PLIC0: interrupt-controller@4000000 {
+      compatible = "riscv,plic0";
+      #address-cells = <0>;
+      #interrupt-cells = <1>;
+      interrupt-controller;
+      interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
+      riscv,max-priority = <7>;
+      riscv,ndev = <51>;
+      reg = <0x0 0x4000000 0x0 0x4000000>;
+    };
+  };
+};

tools/hardware.yml

@@ -209,7 +209,7 @@ devices:
         kernel: PLIC_PPTR
         kernel_size: 0x04000000
 
-  # SiFive CLINT (HiFive, Polarfire, Ariane, QEMU RISC-V virt, Spike)
+  # SiFive CLINT (HiFive, Polarfire, Ariane, Cheshire, QEMU RISC-V virt, Spike)
   # Note that not all CLINTs with this compatible string are of the same size.
   # However, omitting the kernel_size field works as each kernel device frame
   # is of size 0x200000, which is currently larger than the CLINT's of all