Add support for the Banana Pi BPI-F3

Based on the SpacemiT K1 SoC

Signed-off-by: Akif Ejaz <akifejaz40@gmail.com>

include/drivers/irq/riscv_plic0.h

@@ -19,7 +19,8 @@
     !defined(CONFIG_PLAT_STAR64) && \
     !defined(CONFIG_PLAT_CHESHIRE) && \
     !defined(CONFIG_PLAT_ARIANE) && \
-    !defined(CONFIG_PLAT_HIFIVE_P550)
+    !defined(CONFIG_PLAT_HIFIVE_P550) && \
+    !defined(CONFIG_PLAT_BANANAPIF3)
 #error "Check if this platform supports a PLIC."
 #endif
 

libsel4/sel4_plat_include/bananapi-f3/sel4/plat/api/constants.h

@@ -0,0 +1,9 @@
+/*
+ * Copyright 2025, 10xEngineers
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#pragma once
+
+#include <sel4/config.h>

src/plat/spacemit-k1/config.cmake

@@ -0,0 +1,29 @@
+#
+# Copyright 2025, 10xEngineers
+#
+# SPDX-License-Identifier: GPL-2.0-only
+#
+
+cmake_minimum_required(VERSION 3.16.0)
+
+declare_platform(bananapi-f3 KernelPlatformBananapiF3 PLAT_BANANAPIF3 KernelArchRiscV)
+
+if(KernelPlatformBananapiF3)
+    declare_seL4_arch(riscv64)
+    config_set(KernelRiscVPlatform RISCV_PLAT ${KernelPlatform})
+    config_set(KernelPlatformFirstHartID FIRST_HART_ID 0)
+    config_set(KernelOpenSBIPlatform OPENSBI_PLATFORM "generic")
+    list(APPEND KernelDTSList "tools/dts/${KernelPlatform}.dts")
+    list(APPEND KernelDTSList "${CMAKE_CURRENT_LIST_DIR}/overlay-${KernelPlatform}.dts")
+    # The value for TIMER_FREQUENCY is from the "timebase-frequency" field on
+    # the "cpus" node in the Banana Pi F3 device tree.
+    # The value for MAX_IRQ comes from the DTS "interrupt-controller" node which says
+    # "riscv,ndev = <0x9f>".
+    declare_default_headers(
+        TIMER_FREQUENCY 24000000
+        MAX_IRQ 159
+        INTERRUPT_CONTROLLER drivers/irq/riscv_plic0.h
+    )
+else()
+    unset(KernelPlatformFirstHartID CACHE)
+endif()

src/plat/spacemit-k1/overlay-bananapi-f3.dts

@@ -0,0 +1,64 @@
+/*
+ * Copyright 2025, 10xEngineers
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+/ {
+    reserved-memory {
+        /delete-node/ linux,cma;
+    };
+
+    chosen {
+        seL4,kernel-devices =
+            &{/soc/clint@e4000000},
+            &{/soc/interrupt-controller@e0000000};
+    };
+
+    /*
+    * Main memory layout
+    *
+    *   - Bank 0: usable DRAM from 0x00080000 (skipping first 512 KiB)
+    *             up to 0x7f000000 (reserving final 16 MiB of the low 2 GiB).
+    *   - Bank 1: usable DRAM from 0x100000000 (4 GiB) for ~14 GiB above.
+    *
+    *   Note: the 2–4 GiB physical window is omitted from use here.
+    */
+    memory@80000 {
+        device_type = "memory";
+        reg = <0x00000000 0x00080000 0x00000000 0x7ef80000>,
+              <0x00000001 0x00000000 0x00000003 0x80000000>;
+    };
+
+    /*
+     * According to the Spacemit K1 memory map the CLINT is mapped from
+     * 0xe4000000 to 0xe4010000 (64 KiB region used for timer and IPIs).
+     */
+    soc {
+        clint@e4000000 {
+            compatible = "riscv,clint0";
+            reg = <0x00000000 0xe4000000 0x00000000 0x00010000>;
+        };
+    };
+
+    /*
+     * Reserve memory regions that must not be used by seL4:
+     * - (512 KiB): M-mode / OpenSBI
+     * - (16 MiB): framebuffer / S-mode runtime
+     */
+    reserved-memory {
+        #address-cells = <0x02>;
+        #size-cells = <0x02>;
+        ranges;
+
+        mmode_resv0@0 {
+            reg = <0x00000000 0x00000000 0x00000000 0x00080000>;
+            no-map;
+        };
+
+        framebuffer@7f000000 {
+            reg = <0x00000000 0x7f000000 0x00000000 0x01000000>;
+            no-map;
+        };
+    };
+};

tools/hardware.yml

@@ -217,6 +217,7 @@ devices:
   # supported platforms.
   - compatible:
       - riscv,cpu-intc
+      - riscv,clint0
     regions:
       - index: 0
         kernel: CLINT_PPTR