diff --git a/CHANGES b/CHANGES index c5c3c0ceb..f0b00360a 100644 --- a/CHANGES +++ b/CHANGES @@ -31,6 +31,7 @@ Upcoming release: BINARY COMPATIBLE * Rename libsel4 config option ENABLE_SMP_SUPPORT to CONFIG_ENABLE_SMP_SUPPORT to be namespace compliant. * Rename libsel4 config option AARCH64_VSPACE_S2_START_L1 to CONFIG_AARCH64_VSPACE_S2_START_L1 to be namespace compliant. +* Remove imx31/kzm platform support. This platform is being removed as it is sufficiently old and unused. ## Upgrade Notes --- diff --git a/include/drivers/irq/imx31.h b/include/drivers/irq/imx31.h deleted file mode 100644 index 68499e44f..000000000 --- a/include/drivers/irq/imx31.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright 2014, General Dynamics C4 Systems - * - * SPDX-License-Identifier: GPL-2.0-only - */ - -#pragma once - -#include -#include -#include - -enum irqNumbers { - irqInvalid = 255 -}; - -/* Memory map for AVIC (Advanced Vectored Interrupt Controller). */ -volatile struct avic_map { - uint32_t intctl; - uint32_t nimask; - uint32_t intennum; - uint32_t intdisnum; - uint32_t intenableh; - uint32_t intenablel; - uint32_t inttypeh; - uint32_t inttypel; - uint32_t nipriority[8]; - uint32_t nivecsr; - uint32_t fivecsr; - uint32_t intsrch; - uint32_t intsrcl; - uint32_t intfrch; - uint32_t intfrcl; - uint32_t nipndh; - uint32_t nipndl; - uint32_t fipndh; - uint32_t fipndl; - uint32_t vector[64]; -} *avic = (volatile void *)AVIC_PPTR; - -/* Reading the IRQ number from the nivecsr register also - * acks the interrupt. To allow the active irq to be read - * multiple times per interrupt received, we store the - * current active IRQ in a global variable. - */ -extern irq_t active_irq; - -/* Get the active IRQ number from the AVIC. Returns 0xff if - * there isn't one. Note this is also known as irqInvalid */ -static inline irq_t getActiveIRQ(void) -{ - if (active_irq == irqInvalid) { - /* Read the IRQ number from the IRQ controller. - * This has the side-effect of acking the interrupt. - * Reading from this register after acking the - * interrupt will yield an invalid IRQ number, so - * we save the IRQ number in a global variable to - * allow multiple successive calls to this function. - */ - active_irq = (avic->nivecsr >> 16) & 0xff; - } - - return active_irq; -} - -/* Check for pending IRQ */ -static inline bool_t isIRQPending(void) -{ - return getActiveIRQ() != irqInvalid; -} - -/* Enable or disable irq according to the 'disable' flag. */ -static inline void maskInterrupt(bool_t disable, irq_t irq) -{ - if (disable) { - avic->intdisnum = irq; - } else { - avic->intennum = irq; - } -} - -static inline void ackInterrupt(irq_t irq) -{ - /* The interrupt was acked when the IRQ number was read from - * the IRQ controller in getActiveIRQ. Here we reset the - * global active IRQ number so the next call to getActiveIRQ - * will read the IRQ number from the IRQ controller. - */ - active_irq = irqInvalid; -} - -static inline void handleSpuriousIRQ(void) -{ - /* do nothing */ -} - diff --git a/include/drivers/timer/imx31-epit.bf b/include/drivers/timer/imx31-epit.bf deleted file mode 100644 index 72bbade58..000000000 --- a/include/drivers/timer/imx31-epit.bf +++ /dev/null @@ -1,24 +0,0 @@ --- --- Copyright 2014, General Dynamics C4 Systems --- --- SPDX-License-Identifier: GPL-2.0-only --- - -base 32 - -block epitcr { - padding 6 - field clksrc 2 - field om 2 - field stopen 1 - field dozen 1 - field waiten 1 - field dbgen 1 - field iovw 1 - field swr 1 - field prescaler 12 - field rld 1 - field ocien 1 - field enmod 1 - field en 1 -} diff --git a/include/drivers/timer/imx31-epit.h b/include/drivers/timer/imx31-epit.h deleted file mode 100644 index 5d35ee621..000000000 --- a/include/drivers/timer/imx31-epit.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: GPL-2.0-only - */ - -#pragma once - -/* Memory map for EPIT (Enhanced Periodic Interrupt Timer). */ -struct timer { - uint32_t epitcr; - uint32_t epitsr; - uint32_t epitlr; - uint32_t epitcmpr; - uint32_t epitcnt; -}; -typedef volatile struct timer timer_t; -extern timer_t *epit1; - -static inline void resetTimer(void) -{ - epit1->epitsr = 1; - /* Timer resets automatically */ -} - - diff --git a/include/drivers/timer/imx31-gpt.h b/include/drivers/timer/imx31-gpt.h deleted file mode 100644 index a8a02aa4a..000000000 --- a/include/drivers/timer/imx31-gpt.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: GPL-2.0-only - */ - -#pragma once - -#include - -#ifndef CONFIG_KERNEL_MCS -#error "This driver should only be selected for MCS kernel" -#endif /* CONFIG_KERNEL_MCS */ - -/* gptir and gptsr bits */ -#define OF1IE 0 /* output compare 1 */ -#define ROV 5 /* roll over */ - -/* Memory map for GPT (General Purpose Timer). */ -struct timer { - uint32_t gptcr; /* control */ - uint32_t gptpr; /* prescaler */ - uint32_t gptsr; /* status register */ - uint32_t gptir; /* interrupt register */ - uint32_t gptcr1; - uint32_t gptcr2; - uint32_t gptcr3; - uint32_t gpticr1; - uint32_t gpticr2; - uint32_t gptcnt; -}; -typedef volatile struct timer timer_t; -extern timer_t *gpt; -extern ticks_t high_bits; - -static inline ticks_t getCurrentTime(void) -{ - return ((high_bits + !!(gpt->gptsr & BIT(ROV))) << 32llu) + gpt->gptcnt; -} - -static inline void setDeadline(ticks_t deadline) -{ - if (((uint32_t) deadline) > gpt->gptcnt) { - /* turn on compare irq */ - gpt->gptir |= BIT(OF1IE); - /* set the deadline */ - do { - gpt->gptcr1 = (uint32_t) deadline; - } while (gpt->gptcr1 != (uint32_t) deadline); - } -} - -static inline void ackDeadlineIRQ(void) -{ - if (gpt->gptsr & BIT(ROV)) { - high_bits++; - } - - /* turn off compare irq */ - gpt->gptir &= ~(BIT(OF1IE)); - /* ack either irq */ - gpt->gptsr |= (BIT(OF1IE) | BIT(ROV)); -} - diff --git a/libsel4/sel4_plat_include/imx31/sel4/plat/api/constants.h b/libsel4/sel4_plat_include/imx31/sel4/plat/api/constants.h deleted file mode 100644 index f4bca63e9..000000000 --- a/libsel4/sel4_plat_include/imx31/sel4/plat/api/constants.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: BSD-2-Clause - */ - -#pragma once - -#include - -/* ARM1136-JF-S manual, table 13-3 */ -#define seL4_NumHWBreakpoints (8) -#define seL4_NumExclusiveBreakpoints (6) -#define seL4_NumExclusiveWatchpoints (2) -#ifdef CONFIG_HARDWARE_DEBUG_API -#define seL4_FirstWatchpoint (6) -#define seL4_NumDualFunctionMonitors (0) -#endif - -/* First address in the virtual address space that is not accessible to user level */ -#define seL4_UserTop 0xf0000000 diff --git a/src/drivers/serial/config.cmake b/src/drivers/serial/config.cmake index 3c127b0df..402aa0d6f 100644 --- a/src/drivers/serial/config.cmake +++ b/src/drivers/serial/config.cmake @@ -19,7 +19,7 @@ register_driver( CFILES "tegra_omap3_dwapb.c" ) register_driver( - compatibility_strings "fsl,imx31-uart;fsl,imx6q-uart;fsl,imx6sx-uart" + compatibility_strings "fsl,imx6q-uart;fsl,imx6sx-uart" PREFIX src/drivers/serial CFILES "imx.c" ) diff --git a/src/drivers/timer/config.cmake b/src/drivers/timer/config.cmake index daf231043..9182065b5 100644 --- a/src/drivers/timer/config.cmake +++ b/src/drivers/timer/config.cmake @@ -26,12 +26,6 @@ register_driver( PREFIX src/drivers/timer CFILES "exynos4412-mct.c" ) -register_driver( - compatibility_strings "fsl,imx31-epit" - PREFIX src/drivers/timer - CFILES "imx31-epit.c" -) -register_driver(compatibility_strings "fsl,imx31-gpt" PREFIX src/drivers/timer CFILES "imx31-gpt.c") register_driver( compatibility_strings "ti,omap3430-timer" PREFIX src/drivers/timer diff --git a/src/drivers/timer/imx31-epit.c b/src/drivers/timer/imx31-epit.c deleted file mode 100644 index c076852b3..000000000 --- a/src/drivers/timer/imx31-epit.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright 2014, General Dynamics C4 Systems - * - * SPDX-License-Identifier: GPL-2.0-only - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define L2_LINE_SIZE_BITS 5 -#define L2_LINE_SIZE BIT(L2_LINE_SIZE_BITS) - -#define L2_LINE_START(a) ROUND_DOWN(a, L2_LINE_SIZE_BITS) -#define L2_LINE_INDEX(a) (L2_LINE_START(a)>>L2_LINE_SIZE_BITS) - -timer_t *epit1 = (timer_t *) EPIT_PPTR; - -enum IPGConstants { - IPG_CLK = 1, - IPG_CLK_HIGHFREQ = 2, - IPG_CLK_32K = 3 -}; - -#define TIMER_CLOCK_SRC IPG_CLK_32K - -/* Configure EPIT1 as kernel preemption timer */ -BOOT_CODE void initTimer(void) -{ - epitcr_t epitcr_kludge; - - /* Stop timer */ - epit1->epitcr = 0; - - /* Configure timer */ - epitcr_kludge.words[0] = 0; /* Zero struct */ - epitcr_kludge = epitcr_set_clksrc(epitcr_kludge, TIMER_CLOCK_SRC); - /* Overwrite counter immediately on write */ - epitcr_kludge = epitcr_set_iovw(epitcr_kludge, 1); - /* Reload from modulus register */ - epitcr_kludge = epitcr_set_rld(epitcr_kludge, 1); - /* Enable interrupt */ - epitcr_kludge = epitcr_set_ocien(epitcr_kludge, 1); - /* Count from modulus value on restart */ - epitcr_kludge = epitcr_set_enmod(epitcr_kludge, 1); - epit1->epitcr = epitcr_kludge.words[0]; - - /* Set counter modulus */ - epit1->epitlr = TIMER_RELOAD; - - /* Interrupt at zero count */ - epit1->epitcmpr = 0; - - /* Clear pending interrupt */ - epit1->epitsr = 1; - - /* Enable timer */ - epitcr_kludge = epitcr_set_en(epitcr_kludge, 1); - epit1->epitcr = epitcr_kludge.words[0]; -} - diff --git a/src/drivers/timer/imx31-gpt.c b/src/drivers/timer/imx31-gpt.c deleted file mode 100644 index 6586feb14..000000000 --- a/src/drivers/timer/imx31-gpt.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: GPL-2.0-only - */ - -#include -#include -#include -#include -#include -#include -#include - -/* gptcr bits */ -#define EN 0 -#define ENMOD 1 -#define FRR 9 -#define CLKSRC 6 -#define SWR 15 - -timer_t *gpt = (timer_t *) TIMER_PPTR; -ticks_t high_bits = 0; - -enum IPGConstants { - IPG_CLK = 1, - IPG_CLK_HIGHFREQ = 2, - IPG_CLK_32K = 3 -}; - -BOOT_CODE void initTimer(void) -{ - /* reset the gpt */ - gpt->gptcr = 0; - /* clear the status register */ - gpt->gptcr = 0x3F; - /* software reset */ - gpt->gptcr = BIT(SWR); - /* configure the gpt */ - gpt->gptcr = BIT(ENMOD) | BIT(FRR) | (IPG_CLK_HIGHFREQ << CLKSRC); - /* enable overflow irq */ - gpt->gptir = BIT(ROV); - /* turn it on */ - gpt->gptcr |= BIT(EN); -} diff --git a/src/plat/imx31/config.cmake b/src/plat/imx31/config.cmake deleted file mode 100644 index 16c8a9057..000000000 --- a/src/plat/imx31/config.cmake +++ /dev/null @@ -1,40 +0,0 @@ -# -# Copyright 2020, Data61, CSIRO (ABN 41 687 119 230) -# -# SPDX-License-Identifier: GPL-2.0-only -# - -cmake_minimum_required(VERSION 3.7.2) - -declare_platform(imx31 KernelPlatformKZM PLAT_KZM KernelSel4ArchAarch32) - -if(KernelPlatformKZM) - declare_seL4_arch(aarch32) - set(KernelArm1136JF_S ON) - set(KernelArchArmV6 ON) - set(KernelHardwareDebugAPIUnsupported ON CACHE INTERNAL "") - config_set(KernelARMPlatform ARM_PLAT kzm) - set(KernelArmMach "imx" CACHE INTERNAL "") - list(APPEND KernelDTSList "tools/dts/kzm.dts") - list(APPEND KernelDTSList "src/plat/imx31/overlay-kzm.dts") - if(KernelIsMCS) - list(APPEND KernelDTSList "src/plat/imx31/mcs-overlay-kzm.dts") - set(TimerFrequency 35000000) # 35MHz -- calculated by trial and error, roughly precise - set(TimerDriver drivers/timer/imx31-gpt.h) - else() - set(TimerFrequency 32768) - set(TimerDriver drivers/timer/imx31-epit.h) - add_bf_source_old("KernelPlatformKZM" "imx31-epit.bf" "include" "drivers/timer") - endif() - declare_default_headers( - TIMER_FREQUENCY ${TimerFrequency} - MAX_IRQ 63 - INTERRUPT_CONTROLLER drivers/irq/imx31.h - TIMER ${TimerDriver} - KERNEL_WCET 10u - CLK_SHIFT 38u - CLK_MAGIC 7853654485llu - ) -endif() - -add_sources(DEP "KernelPlatformKZM" CFILES src/plat/imx31/machine/hardware.c) diff --git a/src/plat/imx31/machine/hardware.c b/src/plat/imx31/machine/hardware.c deleted file mode 100644 index 4c3329f40..000000000 --- a/src/plat/imx31/machine/hardware.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright 2014, General Dynamics C4 Systems - * - * SPDX-License-Identifier: GPL-2.0-only - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define L2_LINE_SIZE_BITS 5 -#define L2_LINE_SIZE BIT(L2_LINE_SIZE_BITS) - -#define L2_LINE_START(a) ROUND_DOWN(a, L2_LINE_SIZE_BITS) -#define L2_LINE_INDEX(a) (L2_LINE_START(a)>>L2_LINE_SIZE_BITS) - -/* kernel devices */ -struct imx31_l2cc_id { - uint32_t id; /* 000 */ - uint32_t type; /* 004 */ -}; -#define imx31_l2cc_id_regs \ - ((volatile struct imx31_l2cc_id *)L2CC_PPTR) - -struct imx31_l2cc_ctrl { - uint32_t control; /* 100 */ - uint32_t aux_control; /* 104 */ -}; -#define imx31_l2cc_ctrl_regs \ - ((volatile struct imx31_l2cc_ctrl *)(L2CC_PPTR + 0x100)) - -struct imx31_l2cc_flush { - uint32_t pad_0[12]; - uint32_t sync; /* 730 */ - uint32_t pad_1[15]; - uint32_t inv_by_pa; /* 770 */ - uint32_t pad_2[2]; - uint32_t inv_by_way; /* 77c */ - uint32_t pad_3[12]; - uint32_t clean_by_pa; /* 7b0 */ - uint32_t pad_4[1]; - uint32_t clean_by_ix; /* 7b8 */ - uint32_t clean_by_way; /* 7bc */ - uint32_t pad_5[12]; - uint32_t clinv_by_pa; /* 7f0 */ - uint32_t pad_6[1]; - uint32_t clinv_by_ix; /* 7f8 */ - uint32_t clinv_by_way; /* 7fc */ -}; -#define imx31_l2cc_flush_regs \ - ((volatile struct imx31_l2cc_flush *)(L2CC_PPTR + 0x700)) - -struct imx31_l2cc_lockdown { - uint32_t lock_way_D; /* 900 */ - uint32_t lock_way_I; /* 904 */ -}; -#define imx32_l2cc_lockdown_regs \ - ((volatile struct imx31_l2cc_lockdown *)(L2CC_PPTR + 0x900)) - -static void cleanL2(void) -{ - /* clean all ways */ - imx31_l2cc_flush_regs->clean_by_way = 0xff; - /* Busy-wait for completion */ - while (imx31_l2cc_flush_regs->clean_by_way); -} - -static void invalidateL2(void) -{ - /* Invalidate all ways. */ - imx31_l2cc_flush_regs->inv_by_way = 0xff; - /* Busy-wait for completion. */ - while (imx31_l2cc_flush_regs->inv_by_way); -} - -static void finaliseL2Op(void) -{ - /* We sync the l2 cache, which drains the write and eviction - buffers, to ensure that everything is consistent with RAM. */ - imx31_l2cc_flush_regs->sync = 1; -} - -void plat_cleanL2Range(paddr_t start, paddr_t end) -{ - paddr_t line; - word_t index; - - for (index = L2_LINE_INDEX(start); - index < L2_LINE_INDEX(end) + 1; - index++) { - line = index << L2_LINE_SIZE_BITS; - imx31_l2cc_flush_regs->clean_by_pa = line; - } - finaliseL2Op(); -} - -void plat_invalidateL2Range(paddr_t start, paddr_t end) -{ - paddr_t line; - word_t index; - - for (index = L2_LINE_INDEX(start); - index < L2_LINE_INDEX(end) + 1; - index++) { - line = index << L2_LINE_SIZE_BITS; - imx31_l2cc_flush_regs->inv_by_pa = line; - } - - finaliseL2Op(); -} - -void plat_cleanInvalidateL2Range(paddr_t start, paddr_t end) -{ - paddr_t line; - word_t index; - - for (index = L2_LINE_INDEX(start); - index < L2_LINE_INDEX(end) + 1; - index++) { - line = index << L2_LINE_SIZE_BITS; - imx31_l2cc_flush_regs->clinv_by_pa = line; - } - finaliseL2Op(); -} - -void plat_cleanInvalidateL2Cache(void) -{ - cleanL2(); - invalidateL2(); -} - -BOOT_CODE void initL2Cache(void) -{ -#ifndef CONFIG_DEBUG_DISABLE_L2_CACHE - /* Configure L2 cache */ - imx31_l2cc_ctrl_regs->aux_control = 0x0003001b; - - /* Invalidate the L2 cache */ - invalidateL2(); - - /* Enable the L2 cache */ - imx31_l2cc_ctrl_regs->control = 1; -#endif -} - -irq_t active_irq = irqInvalid; - -BOOT_CODE void initIRQController(void) -{ - /* Do nothing */ -} - -BOOT_CODE void cpu_initLocalIRQController(void) -{ - /* Do nothing */ -} diff --git a/src/plat/imx31/mcs-overlay-kzm.dts b/src/plat/imx31/mcs-overlay-kzm.dts deleted file mode 100644 index d91412ed2..000000000 --- a/src/plat/imx31/mcs-overlay-kzm.dts +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: GPL-2.0-only - */ - -/ { - chosen { - seL4,kernel-devices = - "serial0", - &{/interrupt-controller@68000000}, - &{/l2cc@30000000}, - &{/soc/aips@53f00000/timer@53f90000}; - }; -}; diff --git a/src/plat/imx31/overlay-kzm.dts b/src/plat/imx31/overlay-kzm.dts deleted file mode 100644 index bf00f3eed..000000000 --- a/src/plat/imx31/overlay-kzm.dts +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230) - * - * SPDX-License-Identifier: GPL-2.0-only - */ - -/ { - /* Pick serial console */ - chosen { - stdout-path = "serial0"; - seL4,elfloader-devices = - "serial0"; - seL4,kernel-devices = - "serial0", - &{/interrupt-controller@68000000}, - &{/l2cc@30000000}, - &{/soc/aips@53f00000/timer@53f94000}; - }; - - /* Upstream bug: the memory node doesn't have a device_type, - * but there is an empty memory node with a device_type. */ - /delete-node/ memory; - memory@80000000 { - device_type = "memory"; - }; - - l2cc@30000000 { - compatible = "fsl,imx31-l2cc"; - reg = <0x30000000 0x1000>; - }; - - soc { - aips@43f00000 { - /* Incomplete PMU binding, but enough to generate headers. */ - evtmon@43f08000 { - compatible = "fsl,imx31-evtmon"; - reg = <0x43f08000 0x4000>; - interrupts = <0x17>; - }; - }; - - aips@53f00000 { - /* Incomplete timer binding, but enough to generate headers. */ - timer@53f94000 { - compatible = "fsl,imx31-epit"; - reg = <0x53f94000 0x4000>; - interrupts = <0x1c>; - }; - - timer@53f98000 { - compatible = "fsl,imx31-epit"; - reg = <0x53f98000 0x4000>; - interrupts = <0x1b>; - }; - }; - }; -}; diff --git a/tools/dts/kzm.dts b/tools/dts/kzm.dts deleted file mode 100644 index 0cf994421..000000000 --- a/tools/dts/kzm.dts +++ /dev/null @@ -1,383 +0,0 @@ -/* - * Copyright Linux Kernel Team - * - * SPDX-License-Identifier: GPL-2.0-only - * - * This file is derived from an intermediate build stage of the - * Linux kernel. The licenses of all input files to this process - * are compatible with GPL-2.0-only. - */ - -/dts-v1/; - -/ { - #address-cells = < 0x01 >; - #size-cells = < 0x01 >; - model = "Buglabs i.MX31 Bug 1.x"; - compatible = "buglabs,imx31-bug\0fsl,imx31"; - - chosen { - }; - - memory { - device_type = "memory"; - }; - - aliases { - gpio0 = "/soc/aips@53f00000/gpio@53fcc000"; - gpio1 = "/soc/aips@53f00000/gpio@53fd0000"; - gpio2 = "/soc/aips@53f00000/gpio@53fa4000"; - i2c0 = "/soc/aips@43f00000/i2c@43f80000"; - i2c1 = "/soc/aips@43f00000/i2c@43f98000"; - i2c2 = "/soc/aips@43f00000/i2c@43f84000"; - serial0 = "/soc/aips@43f00000/serial@43f90000"; - serial1 = "/soc/aips@43f00000/serial@43f94000"; - serial2 = "/soc/spba@50000000/serial@5000c000"; - serial3 = "/soc/aips@43f00000/serial@43fb0000"; - serial4 = "/soc/aips@43f00000/serial@43fb4000"; - spi0 = "/soc/aips@43f00000/spi@43fa4000"; - spi1 = "/soc/spba@50000000/spi@50010000"; - spi2 = "/soc/aips@53f00000/spi@53f84000"; - }; - - cpus { - #address-cells = < 0x01 >; - #size-cells = < 0x00 >; - - cpu@0 { - compatible = "arm,arm1136jf-s"; - device_type = "cpu"; - reg = < 0x00 >; - }; - }; - - interrupt-controller@68000000 { - compatible = "fsl,imx31-avic\0fsl,avic"; - interrupt-controller; - #interrupt-cells = < 0x01 >; - reg = < 0x68000000 0x100000 >; - phandle = < 0x01 >; - }; - - soc { - #address-cells = < 0x01 >; - #size-cells = < 0x01 >; - compatible = "simple-bus"; - interrupt-parent = < 0x01 >; - ranges; - - iram@1fffc000 { - compatible = "mmio-sram"; - reg = < 0x1fffc000 0x4000 >; - #address-cells = < 0x01 >; - #size-cells = < 0x01 >; - ranges = < 0x00 0x1fffc000 0x4000 >; - }; - - aips@43f00000 { - compatible = "fsl,aips-bus\0simple-bus"; - #address-cells = < 0x01 >; - #size-cells = < 0x01 >; - reg = < 0x43f00000 0x100000 >; - ranges; - - i2c@43f80000 { - compatible = "fsl,imx31-i2c\0fsl,imx21-i2c"; - reg = < 0x43f80000 0x4000 >; - interrupts = < 0x0a >; - clocks = < 0x02 0x21 >; - #address-cells = < 0x01 >; - #size-cells = < 0x00 >; - status = "disabled"; - }; - - i2c@43f84000 { - compatible = "fsl,imx31-i2c\0fsl,imx21-i2c"; - reg = < 0x43f84000 0x4000 >; - interrupts = < 0x03 >; - clocks = < 0x02 0x23 >; - #address-cells = < 0x01 >; - #size-cells = < 0x00 >; - status = "disabled"; - }; - - ata@43f8c000 { - compatible = "fsl,imx31-pata\0fsl,imx27-pata"; - reg = < 0x43f8c000 0x4000 >; - interrupts = < 0x0f >; - clocks = < 0x02 0x1a >; - status = "disabled"; - }; - - serial@43f90000 { - compatible = "fsl,imx31-uart\0fsl,imx21-uart"; - reg = < 0x43f90000 0x4000 >; - interrupts = < 0x2d >; - clocks = < 0x02 0x0a 0x02 0x1e >; - clock-names = "ipg\0per"; - status = "disabled"; - }; - - serial@43f94000 { - compatible = "fsl,imx31-uart\0fsl,imx21-uart"; - reg = < 0x43f94000 0x4000 >; - interrupts = < 0x20 >; - clocks = < 0x02 0x0a 0x02 0x1f >; - clock-names = "ipg\0per"; - status = "disabled"; - }; - - i2c@43f98000 { - compatible = "fsl,imx31-i2c\0fsl,imx21-i2c"; - reg = < 0x43f98000 0x4000 >; - interrupts = < 0x04 >; - clocks = < 0x02 0x22 >; - #address-cells = < 0x01 >; - #size-cells = < 0x00 >; - status = "disabled"; - }; - - spi@43fa4000 { - compatible = "fsl,imx31-cspi"; - reg = < 0x43fa4000 0x4000 >; - interrupts = < 0x0e >; - clocks = < 0x02 0x0a 0x02 0x35 >; - clock-names = "ipg\0per"; - dmas = < 0x03 0x08 0x08 0x00 0x03 0x09 0x08 0x00 >; - dma-names = "rx\0tx"; - #address-cells = < 0x01 >; - #size-cells = < 0x00 >; - status = "disabled"; - }; - - kpp@43fa8000 { - compatible = "fsl,imx31-kpp\0fsl,imx21-kpp"; - reg = < 0x43fa8000 0x4000 >; - interrupts = < 0x18 >; - clocks = < 0x02 0x2e >; - status = "disabled"; - }; - - serial@43fb0000 { - compatible = "fsl,imx31-uart\0fsl,imx21-uart"; - reg = < 0x43fb0000 0x4000 >; - clocks = < 0x02 0x0a 0x02 0x31 >; - clock-names = "ipg\0per"; - interrupts = < 0x2e >; - status = "disabled"; - }; - - serial@43fb4000 { - compatible = "fsl,imx31-uart\0fsl,imx21-uart"; - reg = < 0x43fb4000 0x4000 >; - interrupts = < 0x2f >; - clocks = < 0x02 0x0a 0x02 0x32 >; - clock-names = "ipg\0per"; - status = "okay"; - uart-has-rtscts; - }; - }; - - spba@50000000 { - compatible = "fsl,spba-bus\0simple-bus"; - #address-cells = < 0x01 >; - #size-cells = < 0x01 >; - reg = < 0x50000000 0x100000 >; - ranges; - - sdhci@50004000 { - compatible = "fsl,imx31-mmc"; - reg = < 0x50004000 0x4000 >; - interrupts = < 0x09 >; - clocks = < 0x02 0x0a 0x02 0x14 >; - clock-names = "ipg\0per"; - dmas = < 0x03 0x14 0x03 0x00 >; - dma-names = "rx-tx"; - status = "disabled"; - }; - - sdhci@50008000 { - compatible = "fsl,imx31-mmc"; - reg = < 0x50008000 0x4000 >; - interrupts = < 0x08 >; - clocks = < 0x02 0x0a 0x02 0x15 >; - clock-names = "ipg\0per"; - dmas = < 0x03 0x15 0x03 0x00 >; - dma-names = "rx-tx"; - status = "disabled"; - }; - - serial@5000c000 { - compatible = "fsl,imx31-uart\0fsl,imx21-uart"; - reg = < 0x5000c000 0x4000 >; - interrupts = < 0x12 >; - clocks = < 0x02 0x0a 0x02 0x30 >; - clock-names = "ipg\0per"; - status = "disabled"; - }; - - spi@50010000 { - compatible = "fsl,imx31-cspi"; - reg = < 0x50010000 0x4000 >; - interrupts = < 0x0d >; - clocks = < 0x02 0x0a 0x02 0x36 >; - clock-names = "ipg\0per"; - dmas = < 0x03 0x06 0x08 0x00 0x03 0x07 0x08 0x00 >; - dma-names = "rx\0tx"; - #address-cells = < 0x01 >; - #size-cells = < 0x00 >; - status = "disabled"; - }; - - iim@5001c000 { - compatible = "fsl,imx31-iim\0fsl,imx27-iim"; - reg = < 0x5001c000 0x1000 >; - interrupts = < 0x13 >; - clocks = < 0x02 0x19 >; - }; - }; - - aips@53f00000 { - compatible = "fsl,aips-bus\0simple-bus"; - #address-cells = < 0x01 >; - #size-cells = < 0x01 >; - reg = < 0x53f00000 0x100000 >; - ranges; - - ccm@53f80000 { - compatible = "fsl,imx31-ccm"; - reg = < 0x53f80000 0x4000 >; - interrupts = < 0x1f 0x35 >; - #clock-cells = < 0x01 >; - phandle = < 0x02 >; - }; - - spi@53f84000 { - compatible = "fsl,imx31-cspi"; - reg = < 0x53f84000 0x4000 >; - interrupts = < 0x11 >; - clocks = < 0x02 0x0a 0x02 0x1c >; - clock-names = "ipg\0per"; - dmas = < 0x03 0x0a 0x08 0x00 0x03 0x0b 0x08 0x00 >; - dma-names = "rx\0tx"; - #address-cells = < 0x01 >; - #size-cells = < 0x00 >; - status = "disabled"; - }; - - timer@53f90000 { - compatible = "fsl,imx31-gpt"; - reg = < 0x53f90000 0x4000 >; - interrupts = < 0x1d >; - clocks = < 0x02 0x0a 0x02 0x16 >; - clock-names = "ipg\0per"; - }; - - gpio@53fa4000 { - compatible = "fsl,imx31-gpio"; - reg = < 0x53fa4000 0x4000 >; - interrupts = < 0x38 >; - gpio-controller; - #gpio-cells = < 0x02 >; - interrupt-controller; - #interrupt-cells = < 0x02 >; - }; - - rng@53fb0000 { - compatible = "fsl,imx31-rnga"; - reg = < 0x53fb0000 0x4000 >; - interrupts = < 0x16 >; - clocks = < 0x02 0x1d >; - }; - - gpio@53fcc000 { - compatible = "fsl,imx31-gpio"; - reg = < 0x53fcc000 0x4000 >; - interrupts = < 0x34 >; - gpio-controller; - #gpio-cells = < 0x02 >; - interrupt-controller; - #interrupt-cells = < 0x02 >; - }; - - gpio@53fd0000 { - compatible = "fsl,imx31-gpio"; - reg = < 0x53fd0000 0x4000 >; - interrupts = < 0x33 >; - gpio-controller; - #gpio-cells = < 0x02 >; - interrupt-controller; - #interrupt-cells = < 0x02 >; - }; - - sdma@53fd4000 { - compatible = "fsl,imx31-sdma"; - reg = < 0x53fd4000 0x4000 >; - interrupts = < 0x22 >; - clocks = < 0x02 0x0a 0x02 0x1b >; - clock-names = "ipg\0ahb"; - #dma-cells = < 0x03 >; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin"; - phandle = < 0x03 >; - }; - - rtc@53fd8000 { - compatible = "fsl,imx31-rtc\0fsl,imx21-rtc"; - reg = < 0x53fd8000 0x4000 >; - interrupts = < 0x19 >; - clocks = < 0x02 0x02 0x02 0x28 >; - clock-names = "ref\0ipg"; - }; - - wdog@53fdc000 { - compatible = "fsl,imx31-wdt\0fsl,imx21-wdt"; - reg = < 0x53fdc000 0x4000 >; - clocks = < 0x02 0x29 >; - }; - - pwm@53fe0000 { - compatible = "fsl,imx31-pwm\0fsl,imx27-pwm"; - reg = < 0x53fe0000 0x4000 >; - interrupts = < 0x1a >; - clocks = < 0x02 0x0a 0x02 0x2a >; - clock-names = "ipg\0per"; - #pwm-cells = < 0x02 >; - status = "disabled"; - }; - }; - - emi@b8000000 { - compatible = "simple-bus"; - reg = < 0xb8000000 0x5000 >; - ranges; - #address-cells = < 0x01 >; - #size-cells = < 0x01 >; - - nand@b8000000 { - compatible = "fsl,imx31-nand\0fsl,imx27-nand"; - reg = < 0xb8000000 0x1000 >; - interrupts = < 0x21 >; - clocks = < 0x02 0x09 >; - dmas = < 0x03 0x1e 0x11 0x00 >; - dma-names = "rx-tx"; - #address-cells = < 0x01 >; - #size-cells = < 0x01 >; - status = "disabled"; - }; - - weim@b8002000 { - compatible = "fsl,imx31-weim\0fsl,imx27-weim"; - reg = < 0xb8002000 0x1000 >; - clocks = < 0x02 0x38 >; - #address-cells = < 0x02 >; - #size-cells = < 0x01 >; - ranges = < 0x00 0x00 0xa0000000 0x8000000 0x01 0x00 0xa8000000 0x8000000 0x02 0x00 0xb0000000 0x2000000 0x03 0x00 0xb2000000 0x2000000 0x04 0x00 0xb4000000 0x2000000 0x05 0x00 0xb6000000 0x2000000 >; - status = "disabled"; - }; - }; - }; - - memory@80000000 { - reg = < 0x80000000 0x8000000 >; - }; -}; diff --git a/tools/dts/update-dts.sh b/tools/dts/update-dts.sh index 747bc15db..452176165 100755 --- a/tools/dts/update-dts.sh +++ b/tools/dts/update-dts.sh @@ -17,10 +17,6 @@ echo Using DTS from Linux $(make -s kernelversion) make ARCH=arm multi_v7_defconfig make ARCH=arm -j4 dtbs -# for kzm -make ARCH=arm imx_v6_v7_defconfig -make ARCH=arm -j4 dtbs - make ARCH=arm64 defconfig make ARCH=arm64 -j4 dtbs @@ -43,7 +39,6 @@ exynos4412-odroidx=exynos4 exynos5250-arndale=exynos5250 exynos5410-odroidxu=exynos5410 exynos5422-odroidxu4=exynos5422 -imx31-bug=kzm imx6q-sabrelite=sabre imx6q-wandboard-revd1=wandq imx7d-sdb=imx7sabre diff --git a/tools/hardware.yml b/tools/hardware.yml index 6076486b8..7794a0fc0 100644 --- a/tools/hardware.yml +++ b/tools/hardware.yml @@ -72,25 +72,12 @@ devices: regions: - index: 0 kernel: ARM_LOCAL_PPTR - # i.MX AVIC (no Linux docs, used in arch/arm/mach-imx/avic.c) - - compatible: - - fsl,imx31-avic - regions: - - index: 0 - kernel: AVIC_PPTR - kernel_size: 0x1000 # ARM PL310 L2 cache controller (arm/l2c2x0.txt) - compatible: - arm,pl310-cache regions: - index: 0 kernel: L2CC_L2C310_PPTR - # i.MX31 L2CC (seL4 only) - - compatible: - - fsl,imx31-l2cc - regions: - - index: 0 - kernel: L2CC_PPTR # Exynos multi core timer (timer/samsung,exynos4210-mct.txt) # Exynos4412 MCT is separate as we use it for the timer IRQ. # Other Exynos platforms use the ARM architecture timer. @@ -114,11 +101,6 @@ devices: - arm,cortex-a9-pmu interrupts: KERNEL_PMU_IRQ: boot-cpu - # i.MX evtmon (no Linux binding, this one is seL4-specific.) - - compatible: - - fsl,imx31-evtmon - interrupts: - KERNEL_PMU_IRQ: 0 # Tegra SMMU (memory-controllers/nvidia,tegra30-mc.txt) - compatible: - arm,mmu-500 @@ -176,23 +158,6 @@ devices: interrupts: # IMX6 also has the imx31-gpt. KERNEL_TIMER_IRQ: 0 - # i.MX EPIT (no Linux binding, this is seL4-specific.) - - compatible: - - fsl,imx31-epit - regions: - - index: 0 - kernel: EPIT_PPTR - kernel_size: 0x1000 - interrupts: - KERNEL_TIMER_IRQ: 0 - # i.MX GPT - - compatible: - - fsl,imx31-gpt - regions: - - index: 0 - kernel: TIMER_PPTR - interrupts: - KERNEL_TIMER_IRQ: 0 # QCOM Krait timer (timer/qcom,msm-timer.txt) - compatible: - qcom,kpss-timer @@ -230,7 +195,6 @@ devices: - amlogic,meson-gx-uart - arm,pl011 - brcm,bcm2835-aux-uart - - fsl,imx31-uart - fsl,imx6q-uart - fsl,imx8qxp-lpuart - fsl,imx6sx-uart