tools: add risc-v dtb interrupt parsing

Co-authored-by: Oliver Scott <Oliver.Scott@data61.csiro.au>
Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>

tools/hardware/irq.py

@@ -186,6 +186,7 @@ CONTROLLERS = {
     'ti,am33xx-intc': RawIrqController,
     'ti,omap3-intc': RawIrqController,
     'riscv,cpu-intc': RawIrqController,
+    'riscv,plic0': RawIrqController,
 }