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https://gitlab.rtems.org/rtems/rtos/rtems.git
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549 lines
12 KiB
ArmAsm
549 lines
12 KiB
ArmAsm
/**
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* @file
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*
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* @ingroup qoriq
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*
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* @brief BSP start.
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*/
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/*
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* Copyright (c) 2010, 2017 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/score/percpu.h>
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#include <bsp.h>
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#include <libcpu/powerpc-utility.h>
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#include <bsp/vectors.h>
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#if (QORIQ_INITIAL_MSR & MSR_FP) != 0
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#define INITIALIZE_FPU
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#endif
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#define FIRST_TLB 0
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#define SCRATCH_TLB QORIQ_TLB1_ENTRY_COUNT - 1
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#define INITIAL_MSR r14
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#define START_STACK r15
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#define SAVED_LINK_REGISTER r16
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#define FDT_REGISTER r17
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.globl _start
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#ifdef RTEMS_SMP
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#if QORIQ_THREAD_COUNT > 1
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.globl _start_thread
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#endif
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.globl _start_secondary_processor
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#endif
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.globl bsp_exc_vector_base
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.section ".bsp_start_text", "ax"
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_start:
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mr FDT_REGISTER, r3
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bl .Linitearly
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/* Get start stack */
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LA START_STACK, start_stack_end
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bl .Linitmore
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/* Copy fast text */
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LA r3, bsp_section_fast_text_begin
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LA r4, bsp_section_fast_text_load_begin
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LA r5, bsp_section_fast_text_size
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bl .Lcopy
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LA r3, bsp_section_fast_text_begin
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LA r4, bsp_section_fast_text_size
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bl rtems_cache_flush_multiple_data_lines
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Copy read-only data */
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LA r3, bsp_section_rodata_begin
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LA r4, bsp_section_rodata_load_begin
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LA r5, bsp_section_rodata_size
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bl .Lcopy
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/* Copy FDT into read-only data */
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mr r3, FDT_REGISTER
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bl bsp_fdt_copy
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Flush read-only data */
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LA r3, bsp_section_rodata_begin
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LA r4, bsp_section_rodata_size
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bl rtems_cache_flush_multiple_data_lines
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Copy fast data */
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LA r3, bsp_section_fast_data_begin
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LA r4, bsp_section_fast_data_load_begin
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LA r5, bsp_section_fast_data_size
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bl .Lcopy
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/* Copy data */
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LA r3, bsp_section_data_begin
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LA r4, bsp_section_data_load_begin
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LA r5, bsp_section_data_size
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bl .Lcopy
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/* NULL pointer access protection (only core 0 has to do this) */
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mfspr r3, BOOKE_PIR
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cmpwi r3, 0
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bne .Lnull_area_setup_done
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LA r3, bsp_section_start_begin
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srawi r3, r3, 2
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mtctr r3
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li r3, -4
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LWI r4, 0x44000002
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.Lnull_area_setup_loop:
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stwu r4, 4(r3)
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bdnz .Lnull_area_setup_loop
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.Lnull_area_setup_done:
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li r3, 1
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bl .Linitmmu
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/* Clear SBSS */
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LA r3, bsp_section_sbss_begin
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LA r4, bsp_section_sbss_size
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bl bsp_start_zero
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Clear BSS */
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LA r3, bsp_section_bss_begin
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LA r4, bsp_section_bss_size
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bl bsp_start_zero
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#ifndef __powerpc64__
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/* Set up EABI and SYSV environment */
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bl __eabi
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#endif
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/* Clear command line */
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li r3, 0
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bl boot_card
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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.Lcopy:
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PPC_REG_CMP r3, r4
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beqlr
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b memcpy
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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.Linitearly:
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#ifdef __powerpc64__
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/* Enable 64-bit computation mode for exceptions */
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mfspr r0, BOOKE_EPCR
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oris r0, r0, BOOKE_EPCR_ICM >> 16
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mtspr BOOKE_EPCR, r0
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/* Enable 64-bit computation mode */
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mfmsr r0
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oris r0, r0, MSR_CM >> 16
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mtmsr r0
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isync
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#endif
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/* Disable decrementer */
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mfspr r0, BOOKE_TCR
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LWI r4, BOOKE_TCR_DIE
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andc r0, r0, r4
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mtspr BOOKE_TCR, r0
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#ifdef QORIQ_INITIAL_SPEFSCR
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/* SPEFSCR initialization */
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LWI r0, QORIQ_INITIAL_SPEFSCR
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mtspr FSL_EIS_SPEFSCR, r0
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#endif
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#ifdef QORIQ_INITIAL_BUCSR
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/* BUCSR initialization */
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LWI r0, QORIQ_INITIAL_BUCSR
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mtspr FSL_EIS_BUCSR, r0
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isync
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#endif
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#if defined(QORIQ_INITIAL_HID0) && !defined(QORIQ_IS_HYPERVISOR_GUEST)
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/* HID0 initialization */
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LWI r0, QORIQ_INITIAL_HID0
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mtspr HID0, r0
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#endif
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#ifdef __powerpc64__
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LA32 r2, .TOC.
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#else
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/* Invalidate TLS anchor */
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li r2, 0
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/* Set small-data anchor */
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LA r13, _SDA_BASE_
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#endif
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SET_SELF_CPU_CONTROL r4, r5
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blr
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.Linitmore:
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mflr SAVED_LINK_REGISTER
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/* Invalidate all TS1 MMU entries */
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li r3, 1
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bl qoriq_tlb1_invalidate_all_by_ts
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Add TS1 entry for the first 4GiB of RAM */
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li r3, SCRATCH_TLB
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li r4, FSL_EIS_MAS1_TS
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li r5, FSL_EIS_MAS2_M
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li r6, FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SW | FSL_EIS_MAS3_SX
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li r7, 0
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li r8, 0
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li r9, 11
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bl qoriq_tlb1_write
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* MSR initialization and use TS1 for address translation */
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LWI INITIAL_MSR, QORIQ_INITIAL_MSR
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ori r0, INITIAL_MSR, MSR_IS | MSR_DS
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#ifdef QORIQ_IS_HYPERVISOR_GUEST
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oris r0, r0, MSR_GS >> 16
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#endif
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mtmsr r0
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isync
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/*
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* Initialize start stack. Make sure that we do not share a cache line
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* with the heap block management, since initial stacks for the
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* secondary processors are allocated from the workspace.
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*/
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subi r1, START_STACK, 2 * PPC_DEFAULT_CACHE_LINE_SIZE
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clrrwi r1, r1, PPC_DEFAULT_CACHE_LINE_POWER
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li r0, 0
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PPC_REG_STORE r0, 0(r1)
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#ifdef INITIALIZE_FPU
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bl .Linitfpu
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#endif
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mtlr SAVED_LINK_REGISTER
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blr
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.Linitmmu:
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mflr SAVED_LINK_REGISTER
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/* Configure MMU */
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li r4, FIRST_TLB
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li r5, SCRATCH_TLB
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bl qoriq_mmu_config
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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mtmsr INITIAL_MSR
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isync
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li r3, SCRATCH_TLB
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bl qoriq_tlb1_invalidate
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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mtlr SAVED_LINK_REGISTER
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blr
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#ifdef INITIALIZE_FPU
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/*
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* Write a value to the FPRs to initialize the hidden tag bits. See
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* also "Core Software Initialization Requirements" of the e500mc
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* reference manual for example.
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*/
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.Linitfpu:
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li r0, 0
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stw r0, 0(r1)
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stw r0, 4(r1)
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lfd f0, 0(r1)
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fmr f1, f0
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fmr f2, f0
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fmr f3, f0
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fmr f4, f0
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fmr f5, f0
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fmr f6, f0
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fmr f7, f0
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fmr f8, f0
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fmr f9, f0
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fmr f10, f0
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fmr f11, f0
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fmr f12, f0
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fmr f13, f0
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fmr f14, f0
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fmr f15, f0
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fmr f16, f0
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fmr f17, f0
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fmr f18, f0
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fmr f19, f0
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fmr f20, f0
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fmr f21, f0
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fmr f22, f0
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fmr f23, f0
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fmr f24, f0
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fmr f25, f0
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fmr f26, f0
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fmr f27, f0
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fmr f28, f0
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fmr f29, f0
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fmr f30, f0
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fmr f31, f0
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blr
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#endif
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#ifdef RTEMS_SMP
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#if QORIQ_THREAD_COUNT > 1
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_start_thread:
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/* Adjust PIR */
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mfspr r0, BOOKE_PIR
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srawi r0, r0, 2
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ori r0, r0, 1
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mtspr BOOKE_PIR, r0
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bl .Linitearly
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/* Initialize start stack */
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GET_SELF_CPU_CONTROL r3
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PPC_REG_LOAD r3, PER_CPU_INTERRUPT_STACK_HIGH(r3)
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subi r1, r3, PPC_MINIMUM_STACK_FRAME_SIZE
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clrrwi r1, r1, PPC_STACK_ALIGN_POWER
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li r0, 0
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PPC_REG_STORE r0, 0(r1)
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#ifdef INITIALIZE_FPU
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bl .Linitfpu
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#endif
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b qoriq_start_thread
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#endif
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_start_secondary_processor:
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bl .Linitearly
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/* Get start stack */
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mr START_STACK, r3
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bl .Linitmore
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li r3, 0
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bl .Linitmmu
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b bsp_start_on_secondary_processor
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PPC64_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#endif /* RTEMS_SMP */
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#ifdef __powerpc64__
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#define START_NOP_FOR_LINKER_TOC_POINTER_RESTORE nop; nop; nop; nop
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#else
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#define START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#endif
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/* Exception vector prologues area */
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.section ".bsp_start_text", "ax"
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.align 4
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bsp_exc_vector_base:
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/* Critical input */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 0
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b ppc_exc_fatal_critical
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Machine check */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 1
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b ppc_exc_fatal_machine_check
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Data storage */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 2
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Instruction storage */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 3
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* External input */
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PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
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PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
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li r3, 4
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b ppc_exc_interrupt
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Alignment */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 5
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Program */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 6
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#ifdef __PPC_CPU_E6500__
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/* Floating-point unavailable */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 7
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#endif
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/* System call */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 8
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#ifdef __PPC_CPU_E6500__
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/* APU unavailable */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 9
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#endif
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/* Decrementer */
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#ifdef QORIQ_IS_HYPERVISOR_GUEST
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PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
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PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
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li r3, 10
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b ppc_exc_interrupt
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#else
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 10
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b ppc_exc_fatal_normal
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#endif
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Fixed-interval timer interrupt */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 11
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Watchdog timer interrupt */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 12
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b ppc_exc_fatal_critical
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Data TLB error */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 13
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Instruction TLB error */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 14
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* Debug */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 15
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b ppc_exc_fatal_debug
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* SPE APU unavailable or AltiVec unavailable */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 32
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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/* SPE floating-point data exception or AltiVec assist */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 33
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b ppc_exc_fatal_normal
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START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
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#ifndef __PPC_CPU_E6500__
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/* SPE floating-point round exception */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 34
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b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
#endif
|
|
/* Performance monitor */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 35
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
#ifdef __PPC_CPU_E6500__
|
|
/* Processor doorbell interrupt */
|
|
#if defined(QORIQ_IS_HYPERVISOR_GUEST) && defined(RTEMS_SMP)
|
|
PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
|
|
PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
|
|
li r3, 36
|
|
b ppc_exc_interrupt
|
|
#else
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 36
|
|
b ppc_exc_fatal_normal
|
|
#endif
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* Processor doorbell critical interrupt */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 37
|
|
b ppc_exc_fatal_critical
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* Guest processor doorbell */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 38
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* Guest processor doorbell critical and machine check */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 39
|
|
b ppc_exc_fatal_critical
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* Hypervisor system call */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 40
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* Hypervisor privilege */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 41
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
/* LRAT error */
|
|
PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
|
|
PPC_REG_STORE r3, GPR3_OFFSET(r1)
|
|
li r3, 42
|
|
b ppc_exc_fatal_normal
|
|
START_NOP_FOR_LINKER_TOC_POINTER_RESTORE
|
|
#endif
|
|
|
|
/* Symbol provided for debugging and tracing */
|
|
bsp_exc_vector_end:
|
|
|
|
/* Start stack area */
|
|
.section ".bsp_rwextra", "aw", @nobits
|
|
.align 4
|
|
.space 4096
|
|
start_stack_end:
|