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https://gitlab.rtems.org/rtems/rtos/rtems.git
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160 lines
2.9 KiB
C
160 lines
2.9 KiB
C
/**
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* @file
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*
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* @ingroup lpc_timer
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*
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* @brief Timer API.
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*/
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/*
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* Copyright (c) 2009
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* D-82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef LIBBSP_ARM_SHARED_LPC_TIMER_H
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#define LIBBSP_ARM_SHARED_LPC_TIMER_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @defgroup lpc_timer Timer Support
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*
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* @ingroup RTEMSBSPsARMLPC24XX
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* @ingroup RTEMSBSPsARMLPC32XX
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*
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* @brief Timer support.
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*
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* @{
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*/
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/**
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* @name Interrupt Register Defines
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*
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* @{
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*/
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#define LPC_TIMER_IR_MR0 0x1U
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#define LPC_TIMER_IR_MR1 0x2U
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#define LPC_TIMER_IR_MR2 0x4U
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#define LPC_TIMER_IR_MR3 0x8U
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#define LPC_TIMER_IR_CR0 0x10U
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#define LPC_TIMER_IR_CR1 0x20U
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#define LPC_TIMER_IR_CR2 0x40U
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#define LPC_TIMER_IR_CR3 0x80U
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#define LPC_TIMER_IR_ALL 0xffU
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/** @} */
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/**
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* @name Timer Control Register Defines
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*
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* @{
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*/
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#define LPC_TIMER_TCR_EN 0x1U
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#define LPC_TIMER_TCR_RST 0x2U
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/** @} */
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/**
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* @name Match Control Register Defines
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*
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* @{
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*/
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#define LPC_TIMER_MCR_MR0_INTR 0x1U
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#define LPC_TIMER_MCR_MR0_RST 0x2U
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#define LPC_TIMER_MCR_MR0_STOP 0x4U
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#define LPC_TIMER_MCR_MR1_INTR 0x8U
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#define LPC_TIMER_MCR_MR1_RST 0x10U
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#define LPC_TIMER_MCR_MR1_STOP 0x20U
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#define LPC_TIMER_MCR_MR2_INTR 0x40U
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#define LPC_TIMER_MCR_MR2_RST 0x80U
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#define LPC_TIMER_MCR_MR2_STOP 0x100U
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#define LPC_TIMER_MCR_MR3_INTR 0x200U
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#define LPC_TIMER_MCR_MR3_RST 0x400U
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#define LPC_TIMER_MCR_MR3_STOP 0x800U
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/** @} */
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/**
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* @name Capture Control Register Defines
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*
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* @{
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*/
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#define LPC_TIMER_CCR_CAP0_RE 0x1U
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#define LPC_TIMER_CCR_CAP0_FE 0x2U
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#define LPC_TIMER_CCR_CAP0_INTR 0x4U
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#define LPC_TIMER_CCR_CAP1_RE 0x8U
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#define LPC_TIMER_CCR_CAP1_FE 0x10U
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#define LPC_TIMER_CCR_CAP1_INTR 0x20U
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#define LPC_TIMER_CCR_CAP2_RE 0x40U
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#define LPC_TIMER_CCR_CAP2_FE 0x80U
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#define LPC_TIMER_CCR_CAP2_INTR 0x100U
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#define LPC_TIMER_CCR_CAP3_RE 0x200U
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#define LPC_TIMER_CCR_CAP3_FE 0x400U
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#define LPC_TIMER_CCR_CAP3_INTR 0x800U
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/** @} */
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/**
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* @name External Match Register Defines
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*
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* @{
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*/
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#define LPC_TIMER_EMR_EM0_RE 0x1U
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#define LPC_TIMER_EMR_EM1_FE 0x2U
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#define LPC_TIMER_EMR_EM2_INTR 0x4U
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#define LPC_TIMER_EMR_EM3_RE 0x8U
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#define LPC_TIMER_EMR_EMC0_FE 0x10U
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#define LPC_TIMER_EMR_EMC1_INTR 0x20U
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#define LPC_TIMER_EMR_EMC2_RE 0x40U
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#define LPC_TIMER_EMR_EMC3_FE 0x80U
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/** @} */
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/**
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* @brief Timer control block.
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*/
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typedef struct {
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uint32_t ir;
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uint32_t tcr;
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uint32_t tc;
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uint32_t pr;
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uint32_t pc;
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uint32_t mcr;
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uint32_t mr0;
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uint32_t mr1;
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uint32_t mr2;
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uint32_t mr3;
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uint32_t ccr;
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uint32_t cr0;
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uint32_t cr1;
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uint32_t cr2;
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uint32_t cr3;
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uint32_t emr;
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uint32_t ctcr;
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} lpc_timer;
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/** @} */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_ARM_SHARED_LPC_TIMER_H */
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