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https://gitlab.rtems.org/rtems/rtos/rtems.git
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2020 lines
77 KiB
C
2020 lines
77 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RtemsTaskReqMode
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*/
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/*
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* Copyright (C) 2021 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file is part of the RTEMS quality process and was automatically
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* generated. If you find something that needs to be fixed or
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* worded better please post a report or patch to an RTEMS mailing list
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* or raise a bug report:
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*
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* https://www.rtems.org/bugs.html
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*
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* For information on updating and regenerating please refer to the How-To
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* section in the Software Requirements Engineering chapter of the
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* RTEMS Software Engineering manual. The manual is provided as a part of
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* a release. For development sources please refer to the online
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* documentation at:
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*
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* https://docs.rtems.org
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems.h>
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#include <string.h>
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#include "tx-support.h"
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#include <rtems/test.h>
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/**
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* @defgroup RtemsTaskReqMode spec:/rtems/task/req/mode
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*
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* @ingroup TestsuitesValidationNoClock0
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* @ingroup TestsuitesValidationOneCpu0
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*
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* @{
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*/
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typedef enum {
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RtemsTaskReqMode_Pre_PrevMode_Valid,
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RtemsTaskReqMode_Pre_PrevMode_Null,
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RtemsTaskReqMode_Pre_PrevMode_NA
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} RtemsTaskReqMode_Pre_PrevMode;
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typedef enum {
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RtemsTaskReqMode_Pre_PreemptCur_Yes,
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RtemsTaskReqMode_Pre_PreemptCur_No,
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RtemsTaskReqMode_Pre_PreemptCur_NA
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} RtemsTaskReqMode_Pre_PreemptCur;
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typedef enum {
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RtemsTaskReqMode_Pre_TimesliceCur_Yes,
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RtemsTaskReqMode_Pre_TimesliceCur_No,
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RtemsTaskReqMode_Pre_TimesliceCur_NA
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} RtemsTaskReqMode_Pre_TimesliceCur;
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typedef enum {
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RtemsTaskReqMode_Pre_ASRCur_Yes,
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RtemsTaskReqMode_Pre_ASRCur_No,
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RtemsTaskReqMode_Pre_ASRCur_NA
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} RtemsTaskReqMode_Pre_ASRCur;
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typedef enum {
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RtemsTaskReqMode_Pre_IntLvlCur_Zero,
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RtemsTaskReqMode_Pre_IntLvlCur_Positive,
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RtemsTaskReqMode_Pre_IntLvlCur_NA
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} RtemsTaskReqMode_Pre_IntLvlCur;
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typedef enum {
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RtemsTaskReqMode_Pre_Preempt_Yes,
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RtemsTaskReqMode_Pre_Preempt_No,
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RtemsTaskReqMode_Pre_Preempt_NA
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} RtemsTaskReqMode_Pre_Preempt;
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typedef enum {
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RtemsTaskReqMode_Pre_Timeslice_Yes,
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RtemsTaskReqMode_Pre_Timeslice_No,
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RtemsTaskReqMode_Pre_Timeslice_NA
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} RtemsTaskReqMode_Pre_Timeslice;
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typedef enum {
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RtemsTaskReqMode_Pre_ASR_Yes,
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RtemsTaskReqMode_Pre_ASR_No,
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RtemsTaskReqMode_Pre_ASR_NA
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} RtemsTaskReqMode_Pre_ASR;
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typedef enum {
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RtemsTaskReqMode_Pre_IntLvl_Zero,
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RtemsTaskReqMode_Pre_IntLvl_Positive,
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RtemsTaskReqMode_Pre_IntLvl_NA
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} RtemsTaskReqMode_Pre_IntLvl;
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typedef enum {
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RtemsTaskReqMode_Pre_PreemptMsk_Yes,
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RtemsTaskReqMode_Pre_PreemptMsk_No,
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RtemsTaskReqMode_Pre_PreemptMsk_NA
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} RtemsTaskReqMode_Pre_PreemptMsk;
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typedef enum {
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RtemsTaskReqMode_Pre_TimesliceMsk_Yes,
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RtemsTaskReqMode_Pre_TimesliceMsk_No,
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RtemsTaskReqMode_Pre_TimesliceMsk_NA
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} RtemsTaskReqMode_Pre_TimesliceMsk;
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typedef enum {
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RtemsTaskReqMode_Pre_ASRMsk_Yes,
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RtemsTaskReqMode_Pre_ASRMsk_No,
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RtemsTaskReqMode_Pre_ASRMsk_NA
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} RtemsTaskReqMode_Pre_ASRMsk;
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typedef enum {
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RtemsTaskReqMode_Pre_IntLvlMsk_Yes,
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RtemsTaskReqMode_Pre_IntLvlMsk_No,
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RtemsTaskReqMode_Pre_IntLvlMsk_NA
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} RtemsTaskReqMode_Pre_IntLvlMsk;
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typedef enum {
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RtemsTaskReqMode_Post_Status_Ok,
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RtemsTaskReqMode_Post_Status_InvAddr,
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RtemsTaskReqMode_Post_Status_NotImplIntLvl,
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RtemsTaskReqMode_Post_Status_NotImplIntLvlSMP,
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RtemsTaskReqMode_Post_Status_NotImplNoPreempt,
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RtemsTaskReqMode_Post_Status_NA
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} RtemsTaskReqMode_Post_Status;
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typedef enum {
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RtemsTaskReqMode_Post_Preempt_Yes,
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RtemsTaskReqMode_Post_Preempt_No,
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RtemsTaskReqMode_Post_Preempt_Maybe,
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RtemsTaskReqMode_Post_Preempt_NA
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} RtemsTaskReqMode_Post_Preempt;
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typedef enum {
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RtemsTaskReqMode_Post_ASR_Yes,
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RtemsTaskReqMode_Post_ASR_No,
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RtemsTaskReqMode_Post_ASR_Maybe,
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RtemsTaskReqMode_Post_ASR_NA
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} RtemsTaskReqMode_Post_ASR;
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typedef enum {
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RtemsTaskReqMode_Post_PMVar_Set,
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RtemsTaskReqMode_Post_PMVar_Nop,
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RtemsTaskReqMode_Post_PMVar_Maybe,
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RtemsTaskReqMode_Post_PMVar_NA
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} RtemsTaskReqMode_Post_PMVar;
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typedef enum {
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RtemsTaskReqMode_Post_Mode_Set,
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RtemsTaskReqMode_Post_Mode_Nop,
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RtemsTaskReqMode_Post_Mode_Maybe,
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RtemsTaskReqMode_Post_Mode_NA
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} RtemsTaskReqMode_Post_Mode;
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typedef struct {
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uint32_t Skip : 1;
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uint32_t Pre_PrevMode_NA : 1;
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uint32_t Pre_PreemptCur_NA : 1;
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uint32_t Pre_TimesliceCur_NA : 1;
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uint32_t Pre_ASRCur_NA : 1;
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uint32_t Pre_IntLvlCur_NA : 1;
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uint32_t Pre_Preempt_NA : 1;
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uint32_t Pre_Timeslice_NA : 1;
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uint32_t Pre_ASR_NA : 1;
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uint32_t Pre_IntLvl_NA : 1;
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uint32_t Pre_PreemptMsk_NA : 1;
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uint32_t Pre_TimesliceMsk_NA : 1;
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uint32_t Pre_ASRMsk_NA : 1;
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uint32_t Pre_IntLvlMsk_NA : 1;
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uint32_t Post_Status : 3;
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uint32_t Post_Preempt : 2;
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uint32_t Post_ASR : 2;
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uint32_t Post_PMVar : 2;
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uint32_t Post_Mode : 2;
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} RtemsTaskReqMode_Entry;
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/**
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* @brief Test context for spec:/rtems/task/req/mode test case.
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*/
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typedef struct {
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/**
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* @brief This member contains the object identifier of the worker task.
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*/
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rtems_id worker_id;
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/**
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* @brief null If this member is contains the initial mode of the runner.
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*/
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rtems_mode runner_mode;
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/**
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* @brief This member provides a value for the previous mode set.
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*/
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rtems_mode previous_mode_set_value;
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/**
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* @brief This member specifies the task mode in which rtems_task_mode() is
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* called.
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*/
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rtems_mode current_mode;
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/**
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* @brief This member counts worker activity.
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*/
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uint32_t worker_counter;
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/**
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* @brief This member contains worker counter before the rtems_task_mode()
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* call.
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*/
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uint32_t worker_counter_before;
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/**
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* @brief This member contains worker counter after the rtems_task_mode()
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* call.
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*/
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uint32_t worker_counter_after;
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/**
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* @brief This member counts signal handler activity.
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*/
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uint32_t signal_counter;
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/**
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* @brief This member contains signal counter before the rtems_task_mode()
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* call.
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*/
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uint32_t signal_counter_before;
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/**
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* @brief This member contains signal counter after the rtems_task_mode()
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* call.
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*/
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uint32_t signal_counter_after;
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/**
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* @brief This member specifies the ``mode_set`` parameter for
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* rtems_task_mode().
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*/
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rtems_mode mode_set;
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/**
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* @brief This member specifies the mode mask ``mask`` parameter for
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* rtems_task_mode() for the action.
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*/
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rtems_mode mode_mask;
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/**
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* @brief This member specifies the previous mode set ``previous_mode_set``
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* parameter for rtems_task_mode().
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*/
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rtems_mode *previous_mode_set;
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/**
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* @brief This member contains the return status of the rtems_task_mode()
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* call.
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*/
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rtems_status_code status;
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struct {
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/**
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* @brief This member defines the pre-condition states for the next action.
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*/
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size_t pcs[ 13 ];
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/**
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* @brief If this member is true, then the test action loop is executed.
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*/
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bool in_action_loop;
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/**
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* @brief This member contains the next transition map index.
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*/
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size_t index;
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/**
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* @brief This member contains the current transition map entry.
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*/
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RtemsTaskReqMode_Entry entry;
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/**
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* @brief If this member is true, then the current transition variant
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* should be skipped.
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*/
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bool skip;
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} Map;
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} RtemsTaskReqMode_Context;
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static RtemsTaskReqMode_Context
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RtemsTaskReqMode_Instance;
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static const char * const RtemsTaskReqMode_PreDesc_PrevMode[] = {
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"Valid",
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"Null",
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"NA"
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};
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static const char * const RtemsTaskReqMode_PreDesc_PreemptCur[] = {
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"Yes",
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"No",
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"NA"
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};
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static const char * const RtemsTaskReqMode_PreDesc_TimesliceCur[] = {
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"Yes",
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"No",
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"NA"
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};
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static const char * const RtemsTaskReqMode_PreDesc_ASRCur[] = {
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"Yes",
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"No",
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"NA"
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};
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static const char * const RtemsTaskReqMode_PreDesc_IntLvlCur[] = {
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"Zero",
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"Positive",
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"NA"
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};
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static const char * const RtemsTaskReqMode_PreDesc_Preempt[] = {
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"Yes",
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"No",
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"NA"
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};
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static const char * const RtemsTaskReqMode_PreDesc_Timeslice[] = {
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"Yes",
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"No",
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"NA"
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};
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static const char * const RtemsTaskReqMode_PreDesc_ASR[] = {
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"Yes",
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"No",
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"NA"
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};
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static const char * const RtemsTaskReqMode_PreDesc_IntLvl[] = {
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"Zero",
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"Positive",
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"NA"
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};
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static const char * const RtemsTaskReqMode_PreDesc_PreemptMsk[] = {
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"Yes",
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"No",
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"NA"
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};
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static const char * const RtemsTaskReqMode_PreDesc_TimesliceMsk[] = {
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"Yes",
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"No",
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"NA"
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};
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static const char * const RtemsTaskReqMode_PreDesc_ASRMsk[] = {
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"Yes",
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"No",
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"NA"
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};
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static const char * const RtemsTaskReqMode_PreDesc_IntLvlMsk[] = {
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"Yes",
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"No",
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"NA"
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};
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static const char * const * const RtemsTaskReqMode_PreDesc[] = {
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RtemsTaskReqMode_PreDesc_PrevMode,
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RtemsTaskReqMode_PreDesc_PreemptCur,
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RtemsTaskReqMode_PreDesc_TimesliceCur,
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RtemsTaskReqMode_PreDesc_ASRCur,
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RtemsTaskReqMode_PreDesc_IntLvlCur,
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RtemsTaskReqMode_PreDesc_Preempt,
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RtemsTaskReqMode_PreDesc_Timeslice,
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RtemsTaskReqMode_PreDesc_ASR,
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RtemsTaskReqMode_PreDesc_IntLvl,
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RtemsTaskReqMode_PreDesc_PreemptMsk,
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RtemsTaskReqMode_PreDesc_TimesliceMsk,
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RtemsTaskReqMode_PreDesc_ASRMsk,
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RtemsTaskReqMode_PreDesc_IntLvlMsk,
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NULL
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};
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#define INVALID_MODE 0xffffffff
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#define EVENT_MAKE_READY RTEMS_EVENT_0
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#define EVENT_TIMESLICE RTEMS_EVENT_1
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typedef RtemsTaskReqMode_Context Context;
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static void Worker( rtems_task_argument arg )
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{
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Context *ctx;
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ctx = (Context *) arg;
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while ( true ) {
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rtems_event_set events;
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events = ReceiveAnyEvents();
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if ( ( events & EVENT_TIMESLICE ) != 0 ) {
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SetSelfPriority( PRIO_NORMAL );
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SetSelfPriority( PRIO_HIGH );
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}
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++ctx->worker_counter;
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}
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}
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static void SignalHandler( rtems_signal_set signal_set )
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{
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Context *ctx;
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ctx = T_fixture_context();
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++ctx->signal_counter;
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T_eq_u32( signal_set, 0xdeadbeef );
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}
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static void ExhaustTimeslice( void )
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{
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uint32_t ticks;
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for (
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ticks = 0;
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ticks < rtems_configuration_get_ticks_per_timeslice();
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++ticks
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) {
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ClockTick();
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}
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}
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static void CheckMode(
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Context *ctx,
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rtems_mode mode,
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rtems_mode mask,
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rtems_mode set
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)
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{
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rtems_status_code sc;
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uint32_t counter;
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mode &= ~mask;
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mode |= set & mask;
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counter = ctx->worker_counter;
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SendEvents( ctx->worker_id, EVENT_MAKE_READY );
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if ( ( mode & RTEMS_PREEMPT_MASK ) == RTEMS_PREEMPT ) {
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T_eq_u32( ctx->worker_counter, counter + 1 );
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} else {
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T_eq_u32( ctx->worker_counter, counter );
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}
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counter = ctx->worker_counter;
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SendEvents( ctx->worker_id, EVENT_TIMESLICE );
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ExhaustTimeslice();
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if ( ( mode & RTEMS_PREEMPT_MASK ) == RTEMS_PREEMPT ) {
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if ( ( mode & RTEMS_TIMESLICE_MASK ) == RTEMS_TIMESLICE ) {
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T_eq_u32( ctx->worker_counter, counter + 1 );
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} else {
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T_eq_u32( ctx->worker_counter, counter );
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}
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} else {
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T_eq_u32( ctx->worker_counter, counter );
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}
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counter = ctx->signal_counter;
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sc = rtems_signal_send( RTEMS_SELF, 0xdeadbeef );
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T_rsc_success( sc );
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if ( ( mode & RTEMS_ASR_MASK ) == RTEMS_ASR ) {
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T_eq_u32( ctx->signal_counter, counter + 1 );
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} else {
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T_eq_u32( ctx->signal_counter, counter );
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}
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T_eq_u32( mode & RTEMS_INTERRUPT_MASK, _ISR_Get_level() );
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}
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static void RtemsTaskReqMode_Pre_PrevMode_Prepare(
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RtemsTaskReqMode_Context *ctx,
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RtemsTaskReqMode_Pre_PrevMode state
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)
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{
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switch ( state ) {
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case RtemsTaskReqMode_Pre_PrevMode_Valid: {
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/*
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* While the ``previous_mode_set`` parameter references an object of type
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* rtems_mode.
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*/
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ctx->previous_mode_set = &ctx->previous_mode_set_value;
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break;
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}
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case RtemsTaskReqMode_Pre_PrevMode_Null: {
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/*
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* While the ``previous_mode_set`` parameter is NULL.
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*/
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ctx->previous_mode_set = NULL;
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|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_PrevMode_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Pre_PreemptCur_Prepare(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Pre_PreemptCur state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Pre_PreemptCur_Yes: {
|
|
/*
|
|
* While the calling task has preemption enabled.
|
|
*/
|
|
ctx->current_mode |= RTEMS_PREEMPT;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_PreemptCur_No: {
|
|
/*
|
|
* Where the scheduler does not support the no-preempt mode, while the
|
|
* calling task has preemption enabled.
|
|
*
|
|
* Where the scheduler does support the no-preempt mode, while the
|
|
* calling task has preemption disabled.
|
|
*/
|
|
if ( rtems_configuration_get_maximum_processors() > 1 ) {
|
|
ctx->current_mode |= RTEMS_PREEMPT;
|
|
} else {
|
|
ctx->current_mode |= RTEMS_NO_PREEMPT;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_PreemptCur_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Pre_TimesliceCur_Prepare(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Pre_TimesliceCur state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Pre_TimesliceCur_Yes: {
|
|
/*
|
|
* While the calling task has timeslicing enabled.
|
|
*/
|
|
ctx->current_mode |= RTEMS_TIMESLICE;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_TimesliceCur_No: {
|
|
/*
|
|
* While the calling task has timeslicing disabled.
|
|
*/
|
|
ctx->current_mode |= RTEMS_NO_TIMESLICE;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_TimesliceCur_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Pre_ASRCur_Prepare(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Pre_ASRCur state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Pre_ASRCur_Yes: {
|
|
/*
|
|
* While the calling task has ASR processing enabled.
|
|
*/
|
|
ctx->current_mode |= RTEMS_ASR;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_ASRCur_No: {
|
|
/*
|
|
* While the calling task has ASR processing disabled.
|
|
*/
|
|
ctx->current_mode |= RTEMS_NO_ASR;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_ASRCur_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Pre_IntLvlCur_Prepare(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Pre_IntLvlCur state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Pre_IntLvlCur_Zero: {
|
|
/*
|
|
* While the calling task executes with an interrupt level of zero.
|
|
*/
|
|
ctx->current_mode |= RTEMS_INTERRUPT_LEVEL( 0 );
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_IntLvlCur_Positive: {
|
|
/*
|
|
* Where the system needs inter-processor interrupts, while the calling
|
|
* task executes with an interrupt level of zero.
|
|
*
|
|
* Where the system does not need inter-processor interrupts, while the
|
|
* calling task executes with an an interrupt level greater than zero and
|
|
* less than or equal to CPU_MODES_INTERRUPT_MASK.
|
|
*/
|
|
if ( rtems_configuration_get_maximum_processors() > 1 ) {
|
|
ctx->current_mode |= RTEMS_INTERRUPT_LEVEL( 0 );
|
|
} else {
|
|
ctx->current_mode |= RTEMS_INTERRUPT_LEVEL( 1 );
|
|
}
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_IntLvlCur_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Pre_Preempt_Prepare(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Pre_Preempt state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Pre_Preempt_Yes: {
|
|
/*
|
|
* While the ``mode_set`` parameter specifies that preemption is enabled.
|
|
*/
|
|
ctx->mode_set |= RTEMS_PREEMPT;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_Preempt_No: {
|
|
/*
|
|
* While the ``mode_set`` parameter specifies that preemption is
|
|
* disabled.
|
|
*/
|
|
ctx->mode_set |= RTEMS_NO_PREEMPT;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_Preempt_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Pre_Timeslice_Prepare(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Pre_Timeslice state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Pre_Timeslice_Yes: {
|
|
/*
|
|
* While the ``mode_set`` parameter specifies that timeslicing is
|
|
* enabled.
|
|
*/
|
|
ctx->mode_set |= RTEMS_TIMESLICE;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_Timeslice_No: {
|
|
/*
|
|
* While the ``mode_set`` parameter specifies that timeslicing is
|
|
* disabled.
|
|
*/
|
|
ctx->mode_set |= RTEMS_NO_TIMESLICE;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_Timeslice_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Pre_ASR_Prepare(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Pre_ASR state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Pre_ASR_Yes: {
|
|
/*
|
|
* While the ``mode_set`` parameter specifies that ASR processing is
|
|
* enabled.
|
|
*/
|
|
ctx->mode_set |= RTEMS_ASR;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_ASR_No: {
|
|
/*
|
|
* While the ``mode_set`` parameter specifies that ASR processing is
|
|
* disabled.
|
|
*/
|
|
ctx->mode_set |= RTEMS_NO_ASR;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_ASR_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Pre_IntLvl_Prepare(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Pre_IntLvl state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Pre_IntLvl_Zero: {
|
|
/*
|
|
* While the ``mode_set`` parameter specifies an interrupt level of zero.
|
|
*/
|
|
ctx->mode_set |= RTEMS_INTERRUPT_LEVEL( 0 );
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_IntLvl_Positive: {
|
|
/*
|
|
* While the ``mode_set`` parameter specifies an interrupt level greater
|
|
* than zero and less than or equal to CPU_MODES_INTERRUPT_MASK.
|
|
*/
|
|
ctx->mode_set |= RTEMS_INTERRUPT_LEVEL( 1 );
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_IntLvl_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Pre_PreemptMsk_Prepare(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Pre_PreemptMsk state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Pre_PreemptMsk_Yes: {
|
|
/*
|
|
* While the ``mask`` parameter specifies that the preemption mode shall
|
|
* be set.
|
|
*/
|
|
ctx->mode_mask |= RTEMS_PREEMPT_MASK;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_PreemptMsk_No: {
|
|
/*
|
|
* While the ``mask`` parameter specifies that the preemption mode shall
|
|
* not be set.
|
|
*/
|
|
/* This is the default mode mask */
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_PreemptMsk_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Pre_TimesliceMsk_Prepare(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Pre_TimesliceMsk state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Pre_TimesliceMsk_Yes: {
|
|
/*
|
|
* While the ``mask`` parameter specifies that the timeslicing mode shall
|
|
* be set.
|
|
*/
|
|
ctx->mode_mask |= RTEMS_TIMESLICE_MASK;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_TimesliceMsk_No: {
|
|
/*
|
|
* While the ``mask`` parameter specifies that the timeslicing mode shall
|
|
* not be set.
|
|
*/
|
|
/* This is the default mode mask */
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_TimesliceMsk_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Pre_ASRMsk_Prepare(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Pre_ASRMsk state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Pre_ASRMsk_Yes: {
|
|
/*
|
|
* While the ``mask`` parameter specifies that the ASR processing mode
|
|
* shall be set.
|
|
*/
|
|
ctx->mode_mask |= RTEMS_ASR_MASK;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_ASRMsk_No: {
|
|
/*
|
|
* While the ``mask`` parameter specifies that the ASR processing mode
|
|
* shall not be set.
|
|
*/
|
|
/* This is the default mode mask */
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_ASRMsk_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Pre_IntLvlMsk_Prepare(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Pre_IntLvlMsk state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Pre_IntLvlMsk_Yes: {
|
|
/*
|
|
* While the ``mask`` parameter specifies that the interrupt level shall
|
|
* be set.
|
|
*/
|
|
ctx->mode_mask |= RTEMS_INTERRUPT_MASK;
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_IntLvlMsk_No: {
|
|
/*
|
|
* While the ``mask`` parameter specifies that the interrupt level shall
|
|
* not be set.
|
|
*/
|
|
/* This is the default mode mask */
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Pre_IntLvlMsk_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Post_Status_Check(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Post_Status state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Post_Status_Ok: {
|
|
/*
|
|
* The return status of rtems_task_mode() shall be RTEMS_SUCCESSFUL.
|
|
*/
|
|
T_rsc_success( ctx->status );
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_Status_InvAddr: {
|
|
/*
|
|
* The return status of rtems_task_mode() shall be RTEMS_INVALID_ADDRESS.
|
|
*/
|
|
T_rsc( ctx->status, RTEMS_INVALID_ADDRESS );
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_Status_NotImplIntLvl: {
|
|
/*
|
|
* The return status of rtems_task_mode() shall be RTEMS_NOT_IMPLEMENTED.
|
|
*/
|
|
T_rsc( ctx->status, RTEMS_NOT_IMPLEMENTED );
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_Status_NotImplIntLvlSMP: {
|
|
/*
|
|
* Where the system needs inter-processor interrupts, the return status
|
|
* of rtems_task_mode() shall be RTEMS_NOT_IMPLEMENTED.
|
|
*
|
|
* Where the system does not need inter-processor interrupts, the return
|
|
* status of rtems_task_mode() shall be RTEMS_SUCCESSFUL.
|
|
*/
|
|
if ( rtems_configuration_get_maximum_processors() > 1 ) {
|
|
T_rsc( ctx->status, RTEMS_NOT_IMPLEMENTED );
|
|
} else {
|
|
T_rsc_success( ctx->status );
|
|
}
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_Status_NotImplNoPreempt: {
|
|
/*
|
|
* Where the scheduler does not support the no-preempt mode, the return
|
|
* status of rtems_task_mode() shall be RTEMS_NOT_IMPLEMENTED.
|
|
*
|
|
* Where the scheduler does support the no-preempt mode, the return
|
|
* status of rtems_task_mode() shall be RTEMS_SUCCESSFUL.
|
|
*/
|
|
if ( rtems_configuration_get_maximum_processors() > 1 ) {
|
|
T_rsc( ctx->status, RTEMS_NOT_IMPLEMENTED );
|
|
} else {
|
|
T_rsc_success( ctx->status );
|
|
}
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_Status_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Post_Preempt_Check(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Post_Preempt state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Post_Preempt_Yes: {
|
|
/*
|
|
* The calling task shall be preempted by a higher priority ready task
|
|
* during the rtems_task_mode() call.
|
|
*/
|
|
T_eq_u32( ctx->worker_counter_after, ctx->worker_counter_before + 1 );
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_Preempt_No: {
|
|
/*
|
|
* The calling task shall not be preempted during the rtems_task_mode()
|
|
* call.
|
|
*/
|
|
T_eq_u32( ctx->worker_counter_after, ctx->worker_counter_before );
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_Preempt_Maybe: {
|
|
/*
|
|
* Where the scheduler does not support the no-preempt mode, the calling
|
|
* task shall not be preempted during the rtems_task_mode() call.
|
|
*
|
|
* Where the scheduler does support the no-preempt mode, the calling task
|
|
* shall be preempted by a higher priority ready task during the
|
|
* rtems_task_mode() call.
|
|
*/
|
|
if ( rtems_configuration_get_maximum_processors() > 1 ) {
|
|
T_eq_u32( ctx->worker_counter_after, ctx->worker_counter_before );
|
|
} else {
|
|
T_eq_u32( ctx->worker_counter_after, ctx->worker_counter_before + 1 );
|
|
}
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_Preempt_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Post_ASR_Check(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Post_ASR state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Post_ASR_Yes: {
|
|
/*
|
|
* The calling task shall process pending signals during the
|
|
* rtems_task_mode() call.
|
|
*/
|
|
T_eq_u32( ctx->signal_counter_after, ctx->signal_counter_before + 1 );
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_ASR_No: {
|
|
/*
|
|
* The calling task shall not process signals during the
|
|
* rtems_task_mode() call.
|
|
*/
|
|
T_eq_u32( ctx->signal_counter_after, ctx->signal_counter_before );
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_ASR_Maybe: {
|
|
/*
|
|
* Where the scheduler does not support the no-preempt mode, the calling
|
|
* task shall not process signals during the rtems_task_mode() call.
|
|
*
|
|
* Where the scheduler does support the no-preempt mode, the calling task
|
|
* shall process pending signals during the rtems_task_mode() call.
|
|
*/
|
|
if ( rtems_configuration_get_maximum_processors() > 1 ) {
|
|
T_eq_u32( ctx->signal_counter_after, ctx->signal_counter_before );
|
|
} else {
|
|
T_eq_u32( ctx->signal_counter_after, ctx->signal_counter_before + 1 );
|
|
}
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_ASR_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Post_PMVar_Check(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Post_PMVar state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Post_PMVar_Set: {
|
|
/*
|
|
* The value of the object referenced by the ``previous_mode_set``
|
|
* parameter shall be set to the task modes of the calling task on entry
|
|
* of the call to rtems_task_mode().
|
|
*/
|
|
T_eq_ptr( ctx->previous_mode_set, &ctx->previous_mode_set_value );
|
|
T_eq_u32( ctx->previous_mode_set_value, ctx->current_mode );
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_PMVar_Nop: {
|
|
/*
|
|
* Objects referenced by the ``stack_size`` parameter in past calls to
|
|
* rtems_task_mode() shall not be accessed by the rtems_task_mode() call.
|
|
*/
|
|
T_eq_u32( ctx->previous_mode_set_value, INVALID_MODE );
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_PMVar_Maybe: {
|
|
/*
|
|
* Where the scheduler does not support the no-preempt mode, objects
|
|
* referenced by the ``stack_size`` parameter in past calls to
|
|
* rtems_task_mode() shall not be accessed by the rtems_task_mode() call.
|
|
*
|
|
* Where the scheduler does support the no-preempt mode, the value of the
|
|
* object referenced by the ``previous_mode_set`` parameter shall be set
|
|
* to the task modes of the calling task on entry of the call to
|
|
* rtems_task_mode().
|
|
*/
|
|
T_eq_ptr( ctx->previous_mode_set, &ctx->previous_mode_set_value );
|
|
|
|
if ( rtems_configuration_get_maximum_processors() > 1 ) {
|
|
T_eq_u32( ctx->previous_mode_set_value, INVALID_MODE );
|
|
} else {
|
|
T_eq_u32( ctx->previous_mode_set_value, ctx->current_mode );
|
|
}
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_PMVar_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Post_Mode_Check(
|
|
RtemsTaskReqMode_Context *ctx,
|
|
RtemsTaskReqMode_Post_Mode state
|
|
)
|
|
{
|
|
switch ( state ) {
|
|
case RtemsTaskReqMode_Post_Mode_Set: {
|
|
/*
|
|
* The task modes of the calling task indicated by the ``mask`` parameter
|
|
* shall be set to the corrsponding modes specified by the ``mode_set``
|
|
* parameter.
|
|
*/
|
|
CheckMode( ctx, ctx->current_mode, ctx->mode_mask, ctx->mode_set );
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_Mode_Nop: {
|
|
/*
|
|
* The task modes of the calling task shall not be modified by the
|
|
* rtems_task_mode() call.
|
|
*/
|
|
CheckMode( ctx, ctx->current_mode, 0, 0 );
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_Mode_Maybe: {
|
|
/*
|
|
* Where the scheduler does not support the no-preempt mode, the task
|
|
* modes of the calling task shall not be modified by the
|
|
* rtems_task_mode() call.
|
|
*
|
|
* Where the scheduler does support the no-preempt mode, the task modes
|
|
* of the calling task indicated by the ``mask`` parameter shall be set
|
|
* to the corrsponding modes specified by the ``mode_set`` parameter.
|
|
*/
|
|
if ( rtems_configuration_get_maximum_processors() > 1 ) {
|
|
CheckMode( ctx, ctx->current_mode, 0, 0 );
|
|
} else {
|
|
CheckMode( ctx, ctx->current_mode, ctx->mode_mask, ctx->mode_set );
|
|
}
|
|
break;
|
|
}
|
|
|
|
case RtemsTaskReqMode_Post_Mode_NA:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Setup( RtemsTaskReqMode_Context *ctx )
|
|
{
|
|
rtems_status_code sc;
|
|
|
|
memset( ctx, 0, sizeof( *ctx ) );
|
|
|
|
sc = rtems_task_mode(
|
|
RTEMS_DEFAULT_MODES,
|
|
RTEMS_CURRENT_MODE,
|
|
&ctx->runner_mode
|
|
);
|
|
T_rsc_success( sc );
|
|
|
|
SetSelfPriority( PRIO_NORMAL );
|
|
ctx->worker_id = CreateTask( "WORK", PRIO_HIGH );
|
|
StartTask( ctx->worker_id, Worker, ctx );
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Setup_Wrap( void *arg )
|
|
{
|
|
RtemsTaskReqMode_Context *ctx;
|
|
|
|
ctx = arg;
|
|
ctx->Map.in_action_loop = false;
|
|
RtemsTaskReqMode_Setup( ctx );
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Teardown( RtemsTaskReqMode_Context *ctx )
|
|
{
|
|
DeleteTask( ctx->worker_id );
|
|
RestoreRunnerMode();
|
|
RestoreRunnerPriority();
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Teardown_Wrap( void *arg )
|
|
{
|
|
RtemsTaskReqMode_Context *ctx;
|
|
|
|
ctx = arg;
|
|
ctx->Map.in_action_loop = false;
|
|
RtemsTaskReqMode_Teardown( ctx );
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Prepare( RtemsTaskReqMode_Context *ctx )
|
|
{
|
|
ctx->current_mode = RTEMS_DEFAULT_MODES;
|
|
ctx->mode_set = RTEMS_DEFAULT_MODES;
|
|
ctx->mode_mask = RTEMS_CURRENT_MODE;
|
|
ctx->previous_mode_set_value = INVALID_MODE;
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Action( RtemsTaskReqMode_Context *ctx )
|
|
{
|
|
rtems_status_code sc;
|
|
rtems_mode mode;
|
|
|
|
sc = rtems_task_mode( ctx->current_mode, RTEMS_ALL_MODE_MASKS, &mode );
|
|
T_rsc_success( sc );
|
|
|
|
SendEvents( ctx->worker_id, EVENT_MAKE_READY );
|
|
|
|
sc = rtems_signal_catch( SignalHandler, ctx->current_mode | RTEMS_NO_ASR );
|
|
T_rsc_success( sc );
|
|
|
|
sc = rtems_signal_send( RTEMS_SELF, 0xdeadbeef );
|
|
T_rsc_success( sc );
|
|
|
|
ctx->worker_counter_before = ctx->worker_counter;
|
|
ctx->signal_counter_before = ctx->signal_counter;
|
|
ctx->status = rtems_task_mode(
|
|
ctx->mode_set,
|
|
ctx->mode_mask,
|
|
ctx->previous_mode_set
|
|
);
|
|
ctx->worker_counter_after = ctx->worker_counter;
|
|
ctx->signal_counter_after = ctx->signal_counter;
|
|
}
|
|
|
|
static void RtemsTaskReqMode_Cleanup( RtemsTaskReqMode_Context *ctx )
|
|
{
|
|
rtems_status_code sc;
|
|
rtems_mode mode;
|
|
|
|
sc = rtems_task_mode( RTEMS_DEFAULT_MODES, RTEMS_ALL_MODE_MASKS, &mode );
|
|
T_rsc_success( sc );
|
|
|
|
sc = rtems_task_wake_after( RTEMS_YIELD_PROCESSOR );
|
|
T_rsc_success( sc );
|
|
|
|
sc = rtems_signal_catch( NULL, RTEMS_DEFAULT_MODES );
|
|
T_rsc_success( sc );
|
|
}
|
|
|
|
static const RtemsTaskReqMode_Entry
|
|
RtemsTaskReqMode_Entries[] = {
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_InvAddr, RtemsTaskReqMode_Post_Preempt_No,
|
|
RtemsTaskReqMode_Post_ASR_No, RtemsTaskReqMode_Post_PMVar_Nop,
|
|
RtemsTaskReqMode_Post_Mode_Nop },
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_NA,
|
|
RtemsTaskReqMode_Post_Preempt_NA, RtemsTaskReqMode_Post_ASR_NA,
|
|
RtemsTaskReqMode_Post_PMVar_NA, RtemsTaskReqMode_Post_Mode_NA },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_InvAddr, RtemsTaskReqMode_Post_Preempt_No,
|
|
RtemsTaskReqMode_Post_ASR_No, RtemsTaskReqMode_Post_PMVar_Nop,
|
|
RtemsTaskReqMode_Post_Mode_Nop },
|
|
#endif
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_NA,
|
|
RtemsTaskReqMode_Post_Preempt_NA, RtemsTaskReqMode_Post_ASR_NA,
|
|
RtemsTaskReqMode_Post_PMVar_NA, RtemsTaskReqMode_Post_Mode_NA },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_NA,
|
|
RtemsTaskReqMode_Post_Preempt_NA, RtemsTaskReqMode_Post_ASR_NA,
|
|
RtemsTaskReqMode_Post_PMVar_NA, RtemsTaskReqMode_Post_Mode_NA },
|
|
#elif defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplNoPreempt,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Maybe, RtemsTaskReqMode_Post_Mode_Maybe },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplNoPreempt,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Maybe, RtemsTaskReqMode_Post_Mode_Maybe },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplIntLvl,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Nop, RtemsTaskReqMode_Post_Mode_Nop },
|
|
#elif defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplIntLvlSMP,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Maybe, RtemsTaskReqMode_Post_Mode_Maybe },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_NA,
|
|
RtemsTaskReqMode_Post_Preempt_NA, RtemsTaskReqMode_Post_ASR_NA,
|
|
RtemsTaskReqMode_Post_PMVar_NA, RtemsTaskReqMode_Post_Mode_NA },
|
|
#elif defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplIntLvlSMP,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Maybe, RtemsTaskReqMode_Post_Mode_Maybe },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_Maybe, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_Yes, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_NA,
|
|
RtemsTaskReqMode_Post_Preempt_NA, RtemsTaskReqMode_Post_ASR_NA,
|
|
RtemsTaskReqMode_Post_PMVar_NA, RtemsTaskReqMode_Post_Mode_NA },
|
|
#elif defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_Maybe, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_Yes, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_Yes,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_NA,
|
|
RtemsTaskReqMode_Post_Preempt_NA, RtemsTaskReqMode_Post_ASR_NA,
|
|
RtemsTaskReqMode_Post_PMVar_NA, RtemsTaskReqMode_Post_Mode_NA },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_Yes,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplIntLvl,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Nop, RtemsTaskReqMode_Post_Mode_Nop },
|
|
#elif defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplNoPreempt,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Maybe, RtemsTaskReqMode_Post_Mode_Maybe },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_NA,
|
|
RtemsTaskReqMode_Post_Preempt_NA, RtemsTaskReqMode_Post_ASR_NA,
|
|
RtemsTaskReqMode_Post_PMVar_NA, RtemsTaskReqMode_Post_Mode_NA },
|
|
#elif defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplNoPreempt,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_Maybe,
|
|
RtemsTaskReqMode_Post_PMVar_Maybe, RtemsTaskReqMode_Post_Mode_Maybe },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_Yes,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplIntLvl,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Nop, RtemsTaskReqMode_Post_Mode_Nop },
|
|
#elif defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplIntLvlSMP,
|
|
RtemsTaskReqMode_Post_Preempt_Maybe, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Maybe, RtemsTaskReqMode_Post_Mode_Maybe },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_Yes, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_NA,
|
|
RtemsTaskReqMode_Post_Preempt_NA, RtemsTaskReqMode_Post_ASR_NA,
|
|
RtemsTaskReqMode_Post_PMVar_NA, RtemsTaskReqMode_Post_Mode_NA },
|
|
#elif defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplIntLvlSMP,
|
|
RtemsTaskReqMode_Post_Preempt_Maybe, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Maybe, RtemsTaskReqMode_Post_Mode_Maybe },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_Yes, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplNoPreempt,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_Maybe,
|
|
RtemsTaskReqMode_Post_PMVar_Maybe, RtemsTaskReqMode_Post_Mode_Maybe },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_Yes,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplIntLvl,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Nop, RtemsTaskReqMode_Post_Mode_Nop },
|
|
#elif defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplIntLvlSMP,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_Maybe,
|
|
RtemsTaskReqMode_Post_PMVar_Maybe, RtemsTaskReqMode_Post_Mode_Maybe },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_Yes,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_NA,
|
|
RtemsTaskReqMode_Post_Preempt_NA, RtemsTaskReqMode_Post_ASR_NA,
|
|
RtemsTaskReqMode_Post_PMVar_NA, RtemsTaskReqMode_Post_Mode_NA },
|
|
#elif defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplIntLvlSMP,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_Maybe,
|
|
RtemsTaskReqMode_Post_PMVar_Maybe, RtemsTaskReqMode_Post_Mode_Maybe },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_Yes,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_Maybe, RtemsTaskReqMode_Post_ASR_Yes,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_Yes, RtemsTaskReqMode_Post_ASR_Yes,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_NA,
|
|
RtemsTaskReqMode_Post_Preempt_NA, RtemsTaskReqMode_Post_ASR_NA,
|
|
RtemsTaskReqMode_Post_PMVar_NA, RtemsTaskReqMode_Post_Mode_NA },
|
|
#elif defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_Maybe, RtemsTaskReqMode_Post_ASR_Yes,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_Yes, RtemsTaskReqMode_Post_ASR_Yes,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplIntLvl,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Nop, RtemsTaskReqMode_Post_Mode_Nop },
|
|
#elif defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplNoPreempt,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_Maybe,
|
|
RtemsTaskReqMode_Post_PMVar_Maybe, RtemsTaskReqMode_Post_Mode_Maybe },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_Yes,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplIntLvl,
|
|
RtemsTaskReqMode_Post_Preempt_No, RtemsTaskReqMode_Post_ASR_No,
|
|
RtemsTaskReqMode_Post_PMVar_Nop, RtemsTaskReqMode_Post_Mode_Nop },
|
|
#elif defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplIntLvlSMP,
|
|
RtemsTaskReqMode_Post_Preempt_Maybe, RtemsTaskReqMode_Post_ASR_Maybe,
|
|
RtemsTaskReqMode_Post_PMVar_Maybe, RtemsTaskReqMode_Post_Mode_Maybe },
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_Yes, RtemsTaskReqMode_Post_ASR_Yes,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set },
|
|
#endif
|
|
#if CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE
|
|
{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_NA,
|
|
RtemsTaskReqMode_Post_Preempt_NA, RtemsTaskReqMode_Post_ASR_NA,
|
|
RtemsTaskReqMode_Post_PMVar_NA, RtemsTaskReqMode_Post_Mode_NA }
|
|
#elif defined(RTEMS_SMP)
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
RtemsTaskReqMode_Post_Status_NotImplIntLvlSMP,
|
|
RtemsTaskReqMode_Post_Preempt_Maybe, RtemsTaskReqMode_Post_ASR_Maybe,
|
|
RtemsTaskReqMode_Post_PMVar_Maybe, RtemsTaskReqMode_Post_Mode_Maybe }
|
|
#else
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RtemsTaskReqMode_Post_Status_Ok,
|
|
RtemsTaskReqMode_Post_Preempt_Yes, RtemsTaskReqMode_Post_ASR_Yes,
|
|
RtemsTaskReqMode_Post_PMVar_Set, RtemsTaskReqMode_Post_Mode_Set }
|
|
#endif
|
|
};
|
|
|
|
static const uint8_t
|
|
RtemsTaskReqMode_Map[] = {
|
|
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2,
|
|
6, 2, 6, 2, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 6, 2, 6, 2,
|
|
6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
|
2, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
|
2, 2, 2, 2, 2, 2, 2, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 5, 5,
|
|
5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2,
|
|
6, 2, 6, 2, 6, 2, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12,
|
|
5, 12, 5, 12, 5, 6, 2, 6, 2, 6, 2, 6, 2, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2, 2, 2,
|
|
2, 2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6, 2, 6, 2, 6, 2, 5, 5, 5, 5,
|
|
5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6, 2,
|
|
6, 2, 6, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 7, 3, 7, 3, 7, 3,
|
|
7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3,
|
|
7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4,
|
|
7, 3, 7, 3, 7, 3, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4,
|
|
4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 4, 4, 4, 4, 4, 4,
|
|
4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3,
|
|
10, 10, 2, 2, 10, 10, 2, 2, 10, 10, 2, 2, 10, 10, 2, 2, 17, 10, 6, 2, 17, 10,
|
|
6, 2, 17, 10, 6, 2, 17, 10, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
|
2, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 10, 10, 2, 2, 10, 10,
|
|
2, 2, 10, 10, 2, 2, 10, 10, 2, 2, 17, 10, 6, 2, 17, 10, 6, 2, 17, 10, 6, 2,
|
|
17, 10, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 6, 2, 6, 2, 6,
|
|
2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 16, 16, 5, 5, 16, 16, 5, 5, 10, 10, 2, 2,
|
|
10, 10, 2, 2, 21, 16, 12, 5, 21, 16, 12, 5, 17, 10, 6, 2, 17, 10, 6, 2, 5, 5,
|
|
5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2,
|
|
6, 2, 6, 2, 6, 2, 16, 16, 5, 5, 16, 16, 5, 5, 10, 10, 2, 2, 10, 10, 2, 2, 21,
|
|
16, 12, 5, 21, 16, 12, 5, 17, 10, 6, 2, 17, 10, 6, 2, 5, 5, 5, 5, 5, 5, 5, 5,
|
|
2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6, 2, 6, 2, 6, 2,
|
|
11, 11, 3, 3, 11, 11, 3, 3, 11, 11, 3, 3, 11, 11, 3, 3, 18, 11, 7, 3, 18, 11,
|
|
7, 3, 18, 11, 7, 3, 18, 11, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 11, 11, 3, 3, 11, 11,
|
|
3, 3, 11, 11, 3, 3, 11, 11, 3, 3, 18, 11, 7, 3, 18, 11, 7, 3, 18, 11, 7, 3,
|
|
18, 11, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 7, 3, 7, 3, 7,
|
|
3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 13, 13, 4, 4, 13, 13, 4, 4, 11, 11, 3, 3,
|
|
11, 11, 3, 3, 13, 13, 4, 4, 13, 13, 4, 4, 18, 11, 7, 3, 18, 11, 7, 3, 4, 4,
|
|
4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3,
|
|
7, 3, 7, 3, 13, 13, 4, 4, 13, 13, 4, 4, 11, 11, 3, 3, 11, 11, 3, 3, 13, 13,
|
|
4, 4, 13, 13, 4, 4, 18, 11, 7, 3, 18, 11, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 2, 2, 2, 2,
|
|
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2,
|
|
6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 6, 2, 6, 2, 6, 2, 6, 2,
|
|
6, 2, 6, 2, 6, 2, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 6, 2,
|
|
6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
|
2, 2, 2, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 5, 5, 5, 5, 5, 5,
|
|
5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6, 2, 6, 2,
|
|
6, 2, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12, 5, 12, 5,
|
|
12, 5, 6, 2, 6, 2, 6, 2, 6, 2, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2,
|
|
2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6, 2, 6, 2, 6, 2, 5, 5, 5, 5, 5, 5, 5,
|
|
5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6, 2, 6, 2, 6,
|
|
2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7,
|
|
3, 7, 3, 7, 3, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 7, 3, 7,
|
|
3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 4,
|
|
4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7,
|
|
3, 7, 3, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4,
|
|
4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 10, 10,
|
|
2, 2, 10, 10, 2, 2, 10, 10, 2, 2, 10, 10, 2, 2, 17, 10, 6, 2, 17, 10, 6, 2,
|
|
17, 10, 6, 2, 17, 10, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
|
|
6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 6, 2, 10, 10, 2, 2, 10, 10, 2, 2,
|
|
10, 10, 2, 2, 10, 10, 2, 2, 17, 10, 6, 2, 17, 10, 6, 2, 17, 10, 6, 2, 17, 10,
|
|
6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 6, 2, 6, 2, 6, 2, 6, 2,
|
|
6, 2, 6, 2, 6, 2, 6, 2, 16, 16, 5, 5, 16, 16, 5, 5, 10, 10, 2, 2, 10, 10, 2,
|
|
2, 21, 16, 12, 5, 21, 16, 12, 5, 17, 10, 6, 2, 17, 10, 6, 2, 5, 5, 5, 5, 5,
|
|
5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6, 2, 6,
|
|
2, 6, 2, 16, 16, 5, 5, 16, 16, 5, 5, 10, 10, 2, 2, 10, 10, 2, 2, 21, 16, 12,
|
|
5, 21, 16, 12, 5, 17, 10, 6, 2, 17, 10, 6, 2, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2,
|
|
2, 2, 2, 2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6, 2, 6, 2, 6, 2, 11, 11,
|
|
3, 3, 11, 11, 3, 3, 11, 11, 3, 3, 11, 11, 3, 3, 18, 11, 7, 3, 18, 11, 7, 3,
|
|
18, 11, 7, 3, 18, 11, 7, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
|
|
7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 11, 11, 3, 3, 11, 11, 3, 3,
|
|
11, 11, 3, 3, 11, 11, 3, 3, 18, 11, 7, 3, 18, 11, 7, 3, 18, 11, 7, 3, 18, 11,
|
|
7, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 7, 3, 7, 3, 7, 3, 7, 3,
|
|
7, 3, 7, 3, 7, 3, 7, 3, 13, 13, 4, 4, 13, 13, 4, 4, 11, 11, 3, 3, 11, 11, 3,
|
|
3, 13, 13, 4, 4, 13, 13, 4, 4, 18, 11, 7, 3, 18, 11, 7, 3, 4, 4, 4, 4, 4, 4,
|
|
4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3,
|
|
13, 13, 4, 4, 13, 13, 4, 4, 11, 11, 3, 3, 11, 11, 3, 3, 13, 13, 4, 4, 13, 13,
|
|
4, 4, 18, 11, 7, 3, 18, 11, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 8, 8, 8, 8, 8, 8, 8, 8,
|
|
2, 2, 2, 2, 2, 2, 2, 2, 14, 8, 14, 8, 14, 8, 14, 8, 6, 2, 6, 2, 6, 2, 6, 2,
|
|
8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 14, 8, 14, 8, 14, 8, 14, 8,
|
|
6, 2, 6, 2, 6, 2, 6, 2, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 14,
|
|
8, 14, 8, 14, 8, 14, 8, 6, 2, 6, 2, 6, 2, 6, 2, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2,
|
|
2, 2, 2, 2, 2, 2, 14, 8, 14, 8, 14, 8, 14, 8, 6, 2, 6, 2, 6, 2, 6, 2, 5, 5,
|
|
5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2,
|
|
6, 2, 6, 2, 6, 2, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12,
|
|
5, 12, 5, 12, 5, 6, 2, 6, 2, 6, 2, 6, 2, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2, 2, 2,
|
|
2, 2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6, 2, 6, 2, 6, 2, 5, 5, 5, 5,
|
|
5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6, 2,
|
|
6, 2, 6, 2, 9, 9, 9, 9, 9, 9, 9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 15, 9, 15, 9, 15,
|
|
9, 15, 9, 7, 3, 7, 3, 7, 3, 7, 3, 9, 9, 9, 9, 9, 9, 9, 9, 3, 3, 3, 3, 3, 3,
|
|
3, 3, 15, 9, 15, 9, 15, 9, 15, 9, 7, 3, 7, 3, 7, 3, 7, 3, 9, 9, 9, 9, 9, 9,
|
|
9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 15, 9, 15, 9, 15, 9, 15, 9, 7, 3, 7, 3, 7, 3,
|
|
7, 3, 9, 9, 9, 9, 9, 9, 9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 15, 9, 15, 9, 15, 9,
|
|
15, 9, 7, 3, 7, 3, 7, 3, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3,
|
|
3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 4, 4, 4,
|
|
4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7,
|
|
3, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4,
|
|
4, 7, 3, 7, 3, 7, 3, 7, 3, 19, 19, 8, 8, 19, 19, 8, 8, 10, 10, 2, 2, 10, 10,
|
|
2, 2, 22, 19, 14, 8, 22, 19, 14, 8, 17, 10, 6, 2, 17, 10, 6, 2, 8, 8, 8, 8,
|
|
8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 14, 8, 14, 8, 14, 8, 14, 8, 6, 2, 6, 2,
|
|
6, 2, 6, 2, 19, 19, 8, 8, 19, 19, 8, 8, 10, 10, 2, 2, 10, 10, 2, 2, 22, 19,
|
|
14, 8, 22, 19, 14, 8, 17, 10, 6, 2, 17, 10, 6, 2, 8, 8, 8, 8, 8, 8, 8, 8, 2,
|
|
2, 2, 2, 2, 2, 2, 2, 14, 8, 14, 8, 14, 8, 14, 8, 6, 2, 6, 2, 6, 2, 6, 2, 16,
|
|
16, 5, 5, 16, 16, 5, 5, 10, 10, 2, 2, 10, 10, 2, 2, 21, 16, 12, 5, 21, 16,
|
|
12, 5, 17, 10, 6, 2, 17, 10, 6, 2, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2,
|
|
2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6, 2, 6, 2, 6, 2, 16, 16, 5, 5, 16,
|
|
16, 5, 5, 10, 10, 2, 2, 10, 10, 2, 2, 21, 16, 12, 5, 21, 16, 12, 5, 17, 10,
|
|
6, 2, 17, 10, 6, 2, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5,
|
|
12, 5, 12, 5, 12, 5, 6, 2, 6, 2, 6, 2, 6, 2, 20, 20, 9, 9, 20, 20, 9, 9, 11,
|
|
11, 3, 3, 11, 11, 3, 3, 23, 20, 15, 9, 23, 20, 15, 9, 18, 11, 7, 3, 18, 11,
|
|
7, 3, 9, 9, 9, 9, 9, 9, 9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 15, 9, 15, 9, 15, 9,
|
|
15, 9, 7, 3, 7, 3, 7, 3, 7, 3, 20, 20, 9, 9, 20, 20, 9, 9, 11, 11, 3, 3, 11,
|
|
11, 3, 3, 23, 20, 15, 9, 23, 20, 15, 9, 18, 11, 7, 3, 18, 11, 7, 3, 9, 9, 9,
|
|
9, 9, 9, 9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 15, 9, 15, 9, 15, 9, 15, 9, 7, 3, 7,
|
|
3, 7, 3, 7, 3, 13, 13, 4, 4, 13, 13, 4, 4, 11, 11, 3, 3, 11, 11, 3, 3, 13,
|
|
13, 4, 4, 13, 13, 4, 4, 18, 11, 7, 3, 18, 11, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4,
|
|
3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 13,
|
|
13, 4, 4, 13, 13, 4, 4, 11, 11, 3, 3, 11, 11, 3, 3, 13, 13, 4, 4, 13, 13, 4,
|
|
4, 18, 11, 7, 3, 18, 11, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 8, 8, 8, 8, 8, 8, 8, 8, 2,
|
|
2, 2, 2, 2, 2, 2, 2, 14, 8, 14, 8, 14, 8, 14, 8, 6, 2, 6, 2, 6, 2, 6, 2, 8,
|
|
8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 14, 8, 14, 8, 14, 8, 14, 8, 6,
|
|
2, 6, 2, 6, 2, 6, 2, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 14, 8,
|
|
14, 8, 14, 8, 14, 8, 6, 2, 6, 2, 6, 2, 6, 2, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2,
|
|
2, 2, 2, 2, 2, 14, 8, 14, 8, 14, 8, 14, 8, 6, 2, 6, 2, 6, 2, 6, 2, 5, 5, 5,
|
|
5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6,
|
|
2, 6, 2, 6, 2, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12, 5,
|
|
12, 5, 12, 5, 6, 2, 6, 2, 6, 2, 6, 2, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2,
|
|
2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6, 2, 6, 2, 6, 2, 5, 5, 5, 5, 5,
|
|
5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6, 2, 6,
|
|
2, 6, 2, 9, 9, 9, 9, 9, 9, 9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 15, 9, 15, 9, 15, 9,
|
|
15, 9, 7, 3, 7, 3, 7, 3, 7, 3, 9, 9, 9, 9, 9, 9, 9, 9, 3, 3, 3, 3, 3, 3, 3,
|
|
3, 15, 9, 15, 9, 15, 9, 15, 9, 7, 3, 7, 3, 7, 3, 7, 3, 9, 9, 9, 9, 9, 9, 9,
|
|
9, 3, 3, 3, 3, 3, 3, 3, 3, 15, 9, 15, 9, 15, 9, 15, 9, 7, 3, 7, 3, 7, 3, 7,
|
|
3, 9, 9, 9, 9, 9, 9, 9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 15, 9, 15, 9, 15, 9, 15,
|
|
9, 7, 3, 7, 3, 7, 3, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4,
|
|
4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3,
|
|
3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 4, 4, 4, 4, 4,
|
|
4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7,
|
|
3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7,
|
|
3, 7, 3, 7, 3, 7, 3, 19, 19, 8, 8, 19, 19, 8, 8, 10, 10, 2, 2, 10, 10, 2, 2,
|
|
22, 19, 14, 8, 22, 19, 14, 8, 17, 10, 6, 2, 17, 10, 6, 2, 8, 8, 8, 8, 8, 8,
|
|
8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 14, 8, 14, 8, 14, 8, 14, 8, 6, 2, 6, 2, 6, 2,
|
|
6, 2, 19, 19, 8, 8, 19, 19, 8, 8, 10, 10, 2, 2, 10, 10, 2, 2, 22, 19, 14, 8,
|
|
22, 19, 14, 8, 17, 10, 6, 2, 17, 10, 6, 2, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2,
|
|
2, 2, 2, 2, 2, 14, 8, 14, 8, 14, 8, 14, 8, 6, 2, 6, 2, 6, 2, 6, 2, 16, 16, 5,
|
|
5, 16, 16, 5, 5, 10, 10, 2, 2, 10, 10, 2, 2, 21, 16, 12, 5, 21, 16, 12, 5,
|
|
17, 10, 6, 2, 17, 10, 6, 2, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2,
|
|
12, 5, 12, 5, 12, 5, 12, 5, 6, 2, 6, 2, 6, 2, 6, 2, 16, 16, 5, 5, 16, 16, 5,
|
|
5, 10, 10, 2, 2, 10, 10, 2, 2, 21, 16, 12, 5, 21, 16, 12, 5, 17, 10, 6, 2,
|
|
17, 10, 6, 2, 5, 5, 5, 5, 5, 5, 5, 5, 2, 2, 2, 2, 2, 2, 2, 2, 12, 5, 12, 5,
|
|
12, 5, 12, 5, 6, 2, 6, 2, 6, 2, 6, 2, 20, 20, 9, 9, 20, 20, 9, 9, 11, 11, 3,
|
|
3, 11, 11, 3, 3, 23, 20, 15, 9, 23, 20, 15, 9, 18, 11, 7, 3, 18, 11, 7, 3, 9,
|
|
9, 9, 9, 9, 9, 9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 15, 9, 15, 9, 15, 9, 15, 9, 7,
|
|
3, 7, 3, 7, 3, 7, 3, 20, 20, 9, 9, 20, 20, 9, 9, 11, 11, 3, 3, 11, 11, 3, 3,
|
|
23, 20, 15, 9, 23, 20, 15, 9, 18, 11, 7, 3, 18, 11, 7, 3, 9, 9, 9, 9, 9, 9,
|
|
9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 15, 9, 15, 9, 15, 9, 15, 9, 7, 3, 7, 3, 7, 3,
|
|
7, 3, 13, 13, 4, 4, 13, 13, 4, 4, 11, 11, 3, 3, 11, 11, 3, 3, 13, 13, 4, 4,
|
|
13, 13, 4, 4, 18, 11, 7, 3, 18, 11, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3,
|
|
3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 13, 13, 4, 4, 13,
|
|
13, 4, 4, 11, 11, 3, 3, 11, 11, 3, 3, 13, 13, 4, 4, 13, 13, 4, 4, 18, 11, 7,
|
|
3, 18, 11, 7, 3, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4,
|
|
4, 4, 4, 4, 7, 3, 7, 3, 7, 3, 7, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
|
|
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
|
|
};
|
|
|
|
static size_t RtemsTaskReqMode_Scope( void *arg, char *buf, size_t n )
|
|
{
|
|
RtemsTaskReqMode_Context *ctx;
|
|
|
|
ctx = arg;
|
|
|
|
if ( ctx->Map.in_action_loop ) {
|
|
return T_get_scope( RtemsTaskReqMode_PreDesc, buf, n, ctx->Map.pcs );
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static T_fixture RtemsTaskReqMode_Fixture = {
|
|
.setup = RtemsTaskReqMode_Setup_Wrap,
|
|
.stop = NULL,
|
|
.teardown = RtemsTaskReqMode_Teardown_Wrap,
|
|
.scope = RtemsTaskReqMode_Scope,
|
|
.initial_context = &RtemsTaskReqMode_Instance
|
|
};
|
|
|
|
static inline RtemsTaskReqMode_Entry RtemsTaskReqMode_PopEntry(
|
|
RtemsTaskReqMode_Context *ctx
|
|
)
|
|
{
|
|
size_t index;
|
|
|
|
index = ctx->Map.index;
|
|
ctx->Map.index = index + 1;
|
|
return RtemsTaskReqMode_Entries[
|
|
RtemsTaskReqMode_Map[ index ]
|
|
];
|
|
}
|
|
|
|
static void RtemsTaskReqMode_TestVariant( RtemsTaskReqMode_Context *ctx )
|
|
{
|
|
RtemsTaskReqMode_Pre_PrevMode_Prepare( ctx, ctx->Map.pcs[ 0 ] );
|
|
RtemsTaskReqMode_Pre_PreemptCur_Prepare( ctx, ctx->Map.pcs[ 1 ] );
|
|
RtemsTaskReqMode_Pre_TimesliceCur_Prepare( ctx, ctx->Map.pcs[ 2 ] );
|
|
RtemsTaskReqMode_Pre_ASRCur_Prepare( ctx, ctx->Map.pcs[ 3 ] );
|
|
RtemsTaskReqMode_Pre_IntLvlCur_Prepare( ctx, ctx->Map.pcs[ 4 ] );
|
|
RtemsTaskReqMode_Pre_Preempt_Prepare( ctx, ctx->Map.pcs[ 5 ] );
|
|
RtemsTaskReqMode_Pre_Timeslice_Prepare( ctx, ctx->Map.pcs[ 6 ] );
|
|
RtemsTaskReqMode_Pre_ASR_Prepare( ctx, ctx->Map.pcs[ 7 ] );
|
|
RtemsTaskReqMode_Pre_IntLvl_Prepare( ctx, ctx->Map.pcs[ 8 ] );
|
|
RtemsTaskReqMode_Pre_PreemptMsk_Prepare( ctx, ctx->Map.pcs[ 9 ] );
|
|
RtemsTaskReqMode_Pre_TimesliceMsk_Prepare( ctx, ctx->Map.pcs[ 10 ] );
|
|
RtemsTaskReqMode_Pre_ASRMsk_Prepare( ctx, ctx->Map.pcs[ 11 ] );
|
|
RtemsTaskReqMode_Pre_IntLvlMsk_Prepare( ctx, ctx->Map.pcs[ 12 ] );
|
|
RtemsTaskReqMode_Action( ctx );
|
|
RtemsTaskReqMode_Post_Status_Check( ctx, ctx->Map.entry.Post_Status );
|
|
RtemsTaskReqMode_Post_Preempt_Check( ctx, ctx->Map.entry.Post_Preempt );
|
|
RtemsTaskReqMode_Post_ASR_Check( ctx, ctx->Map.entry.Post_ASR );
|
|
RtemsTaskReqMode_Post_PMVar_Check( ctx, ctx->Map.entry.Post_PMVar );
|
|
RtemsTaskReqMode_Post_Mode_Check( ctx, ctx->Map.entry.Post_Mode );
|
|
}
|
|
|
|
/**
|
|
* @fn void T_case_body_RtemsTaskReqMode( void )
|
|
*/
|
|
T_TEST_CASE_FIXTURE( RtemsTaskReqMode, &RtemsTaskReqMode_Fixture )
|
|
{
|
|
RtemsTaskReqMode_Context *ctx;
|
|
|
|
ctx = T_fixture_context();
|
|
ctx->Map.in_action_loop = true;
|
|
ctx->Map.index = 0;
|
|
|
|
for (
|
|
ctx->Map.pcs[ 0 ] = RtemsTaskReqMode_Pre_PrevMode_Valid;
|
|
ctx->Map.pcs[ 0 ] < RtemsTaskReqMode_Pre_PrevMode_NA;
|
|
++ctx->Map.pcs[ 0 ]
|
|
) {
|
|
for (
|
|
ctx->Map.pcs[ 1 ] = RtemsTaskReqMode_Pre_PreemptCur_Yes;
|
|
ctx->Map.pcs[ 1 ] < RtemsTaskReqMode_Pre_PreemptCur_NA;
|
|
++ctx->Map.pcs[ 1 ]
|
|
) {
|
|
for (
|
|
ctx->Map.pcs[ 2 ] = RtemsTaskReqMode_Pre_TimesliceCur_Yes;
|
|
ctx->Map.pcs[ 2 ] < RtemsTaskReqMode_Pre_TimesliceCur_NA;
|
|
++ctx->Map.pcs[ 2 ]
|
|
) {
|
|
for (
|
|
ctx->Map.pcs[ 3 ] = RtemsTaskReqMode_Pre_ASRCur_Yes;
|
|
ctx->Map.pcs[ 3 ] < RtemsTaskReqMode_Pre_ASRCur_NA;
|
|
++ctx->Map.pcs[ 3 ]
|
|
) {
|
|
for (
|
|
ctx->Map.pcs[ 4 ] = RtemsTaskReqMode_Pre_IntLvlCur_Zero;
|
|
ctx->Map.pcs[ 4 ] < RtemsTaskReqMode_Pre_IntLvlCur_NA;
|
|
++ctx->Map.pcs[ 4 ]
|
|
) {
|
|
for (
|
|
ctx->Map.pcs[ 5 ] = RtemsTaskReqMode_Pre_Preempt_Yes;
|
|
ctx->Map.pcs[ 5 ] < RtemsTaskReqMode_Pre_Preempt_NA;
|
|
++ctx->Map.pcs[ 5 ]
|
|
) {
|
|
for (
|
|
ctx->Map.pcs[ 6 ] = RtemsTaskReqMode_Pre_Timeslice_Yes;
|
|
ctx->Map.pcs[ 6 ] < RtemsTaskReqMode_Pre_Timeslice_NA;
|
|
++ctx->Map.pcs[ 6 ]
|
|
) {
|
|
for (
|
|
ctx->Map.pcs[ 7 ] = RtemsTaskReqMode_Pre_ASR_Yes;
|
|
ctx->Map.pcs[ 7 ] < RtemsTaskReqMode_Pre_ASR_NA;
|
|
++ctx->Map.pcs[ 7 ]
|
|
) {
|
|
for (
|
|
ctx->Map.pcs[ 8 ] = RtemsTaskReqMode_Pre_IntLvl_Zero;
|
|
ctx->Map.pcs[ 8 ] < RtemsTaskReqMode_Pre_IntLvl_NA;
|
|
++ctx->Map.pcs[ 8 ]
|
|
) {
|
|
for (
|
|
ctx->Map.pcs[ 9 ] = RtemsTaskReqMode_Pre_PreemptMsk_Yes;
|
|
ctx->Map.pcs[ 9 ] < RtemsTaskReqMode_Pre_PreemptMsk_NA;
|
|
++ctx->Map.pcs[ 9 ]
|
|
) {
|
|
for (
|
|
ctx->Map.pcs[ 10 ] = RtemsTaskReqMode_Pre_TimesliceMsk_Yes;
|
|
ctx->Map.pcs[ 10 ] < RtemsTaskReqMode_Pre_TimesliceMsk_NA;
|
|
++ctx->Map.pcs[ 10 ]
|
|
) {
|
|
for (
|
|
ctx->Map.pcs[ 11 ] = RtemsTaskReqMode_Pre_ASRMsk_Yes;
|
|
ctx->Map.pcs[ 11 ] < RtemsTaskReqMode_Pre_ASRMsk_NA;
|
|
++ctx->Map.pcs[ 11 ]
|
|
) {
|
|
for (
|
|
ctx->Map.pcs[ 12 ] = RtemsTaskReqMode_Pre_IntLvlMsk_Yes;
|
|
ctx->Map.pcs[ 12 ] < RtemsTaskReqMode_Pre_IntLvlMsk_NA;
|
|
++ctx->Map.pcs[ 12 ]
|
|
) {
|
|
ctx->Map.entry = RtemsTaskReqMode_PopEntry( ctx );
|
|
|
|
if ( ctx->Map.entry.Skip ) {
|
|
continue;
|
|
}
|
|
|
|
RtemsTaskReqMode_Prepare( ctx );
|
|
RtemsTaskReqMode_TestVariant( ctx );
|
|
RtemsTaskReqMode_Cleanup( ctx );
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/** @} */
|