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94 lines
2.9 KiB
C
94 lines
2.9 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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* @ingroup zynq_slcr
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* @brief SLCR support.
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*/
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/*
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*
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* Copyright (c) 2017
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* NSF Center for High-Performance Reconfigurable Computing (CHREC),
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* University of Pittsburgh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation
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* are those of the authors and should not be interpreted as representing
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* official policies, either expressed or implied, of CHREC.
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*
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* Author: Patrick Gauvin <gauvin@hcs.ufl.edu>
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*/
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/**
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* @defgroup zynq_slcr SLCR Support
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* @ingroup arm_zynq
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* @brief SLCR Support
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*/
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#ifndef LIBBSP_ARM_XILINX_ZYNQ_SLCR_H
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#define LIBBSP_ARM_XILINX_ZYNQ_SLCR_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/**
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* @brief Set the mask that allows the FPGA resets to be modified.
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*
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* Bit 0 corresponds to FPGA0_OUT_RST, and bit 3 to FPGA3_OUT_RST. Setting a
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* bit in the mask to 1 allows calls to zynq_slcr_fpga_clk_rst to modify that
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* reset. The default mask is 0xf.
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*/
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void zynq_slcr_fpga_clk_rst_mask_set(
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uint32_t mask
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);
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/**
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* @brief Control the FPGA reset values.
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*
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* @param val Bits 0 through 3 correspond to FPGA RST 0 through 3. A bit value
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* of 1 asserts the reset.
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*/
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void zynq_slcr_fpga_clk_rst(
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uint32_t val
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);
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/**
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* @brief Control the level shifters between the PS and PL.
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*
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* @param val Acceptable values are ZYNQ_SLCR_LVL_SHFTR_EN_DISABLE,
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* ZYNQ_SLCR_LVL_SHFTR_EN_PS_TO_PL, and ZYNQ_SLCR_LVL_SHFTR_EN_ALL.
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*/
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void zynq_slcr_level_shifter_enable(
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uint32_t val
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);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_ARM_XILINX_ZYNQ_SLCR_H */
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