Sebastian Huber c4c3e68790 bsps/arm: Use fatal error for data cache disable ...

On the Cortex-A cores, at least the L1 data cache is required to provide
support for atomic operations.

Close #5050.

2024-06-25 03:58:34 +00:00

..

bsps

bsps/aarch64/zynqmp: Add memory error reporting

2024-06-21 05:57:21 +00:00

cpukit

build: Install <rtems/score/processormaskimpl.h>

2024-04-30 01:39:05 -04:00

testsuites

bsps/arm: Use fatal error for data cache disable

2024-06-25 03:58:34 +00:00

grp.yml

Update company name

2023-05-20 11:05:26 +02:00