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90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSBSPsARMCycV
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*/
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/*
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* Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H
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#define LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H
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/**
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* @defgroup RTEMSBSPsARMCycV Intel Cyclone V
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*
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* @ingroup RTEMSBSPsARM
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*
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* @brief Intel Cyclone V Board Support Package.
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*
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* @{
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*/
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#include <bspopts.h>
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#define BSP_FEATURE_IRQ_EXTENSION
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#ifndef ASM
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#include <rtems.h>
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#include <bsp/default-initial-extension.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000
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#define BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
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#define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 )
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#define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 )
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#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 )
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#ifndef BSP_ARM_A9MPCORE_PERIPHCLK
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extern uint32_t altera_cyclone_v_a9mpcore_periphclk;
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#define BSP_ARM_A9MPCORE_PERIPHCLK altera_cyclone_v_a9mpcore_periphclk
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#define ALTERA_CYCLONE_V_NEED_A9MPCORE_PERIPHCLK
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#endif
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#define BSP_ARM_L2C_310_BASE 0xfffef000
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#define BSP_ARM_L2C_310_ID 0x410000c9
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* ASM */
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/* @} */
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#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H */
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