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bc8ffae115
The devfg driver loads the PL with a bitfile image. The driver can also support scrubbing. These drivers are from Patrick Gauvin <pggauvin at gmail.com> and a thread on the devel list: https://lists.rtems.org/pipermail/devel/2017-May/017705.html
102 lines
3.4 KiB
C
102 lines
3.4 KiB
C
/*
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* SLCR Support Implementation
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*
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* At this point, only a few operations related to programming the FPGA are
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* supported.
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*
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* Copyright (c) 2017
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* NSF Center for High-Performance Reconfigurable Computing (CHREC),
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* University of Pittsburgh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation
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* are those of the authors and should not be interpreted as representing
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* official policies, either expressed or implied, of CHREC.
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*
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* Author: Patrick Gauvin <gauvin@hcs.ufl.edu>
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*/
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#include <stdint.h>
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#include <rtems.h>
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#include <dev/slcr/zynq-slcr.h>
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#include <dev/slcr/zynq-slcr-regs.h>
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static uint32_t rst_mask = 0xf;
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static rtems_interrupt_lock zynq_slcr_lock =
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RTEMS_INTERRUPT_LOCK_INITIALIZER( "zynq_slcr" );
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static inline void slcr_unlock( void )
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{
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zynq_slcr_write32( ZYNQ_SLCR_UNLOCK_OFF, ZYNQ_SLCR_UNLOCK_KEY );
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}
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static inline void slcr_lock( void )
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{
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zynq_slcr_write32( ZYNQ_SLCR_LOCK_OFF, ZYNQ_SLCR_LOCK_KEY );
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}
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void zynq_slcr_fpga_clk_rst_mask_set(
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uint32_t mask
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)
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{
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rtems_interrupt_lock_context lcontext;
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rtems_interrupt_lock_acquire( &zynq_slcr_lock, &lcontext );
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rst_mask = 0xf & mask;
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rtems_interrupt_lock_release( &zynq_slcr_lock, &lcontext );
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}
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void zynq_slcr_fpga_clk_rst(
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uint32_t val
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)
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{
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uint32_t rst_ctrl;
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rtems_interrupt_lock_context lcontext;
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rtems_interrupt_lock_acquire( &zynq_slcr_lock, &lcontext );
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slcr_unlock();
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rst_ctrl = ZYNQ_SLCR_FPGA_RST_CTRL_FPGA_OUT_RST_GET(
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zynq_slcr_read32( ZYNQ_SLCR_FPGA_RST_CTRL_OFF )
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);
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/* Only modify resets that are set in the mask */
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zynq_slcr_write32( ZYNQ_SLCR_FPGA_RST_CTRL_OFF,
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ZYNQ_SLCR_FPGA_RST_CTRL_FPGA_OUT_RST(
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( ~rst_mask & rst_ctrl ) | ( rst_mask & val )
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)
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);
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slcr_lock();
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rtems_interrupt_lock_release( &zynq_slcr_lock, &lcontext );
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}
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void zynq_slcr_level_shifter_enable(
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uint32_t val
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)
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{
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rtems_interrupt_lock_context lcontext;
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rtems_interrupt_lock_acquire( &zynq_slcr_lock, &lcontext );
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slcr_unlock();
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zynq_slcr_write32( ZYNQ_SLCR_LVL_SHFTR_EN_OFF, val );
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slcr_lock();
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rtems_interrupt_lock_release( &zynq_slcr_lock, &lcontext );
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}
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