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0067feb693
PR 1385/cpukit * cpu_asm.S: When the type rtems_boolean was switched to the C99 bool, the size changed from 4 bytes to 1 byte. The interrupt dispatching code accesses two boolean variables for scheduling purposes and the assembly implementations of this code did not get updated.
599 lines
11 KiB
ArmAsm
599 lines
11 KiB
ArmAsm
/* cpu_asm.S
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*
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* This file contains the basic algorithms for all assembly code used
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* in the Blackfin port of RTEMS. These algorithms must be implemented
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* in assembly language
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*
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* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
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* written by Allan Hessenflow <allanh@kallisti.com>
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*
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* Based on earlier version:
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*
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* Copyright (c) 2006 by Atos Automacao Industrial Ltda.
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* written by Alain Schaefer <alain.schaefer@easc.ch>
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* and Antonio Giovanini <antonio@atos.com.br>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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#include <rtems/asm.h>
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#include <rtems/score/cpu_asm.h>
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#include <rtems/score/bfin.h>
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#include <rtems/bfin/bfin.h>
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#define LO(con32) ((con32) & 0xFFFF)
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#define HI(con32) (((con32) >> 16) & 0xFFFF)
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#if 0
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/* some debug routines */
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.globl __CPU_write_char;
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__CPU_write_char:
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p0.h = 0xffc0;
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p0.l = 0x0400;
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txWaitLoop:
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r1 = w[p0 + 0x14];
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cc = bittst(r1, 5);
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if !cc jump txWaitLoop;
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w[p0 + 0x00] = r0;
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rts;
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.globl __CPU_write_crlf;
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__CPU_write_crlf:
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r0 = '\r';
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[--sp] = rets;
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call __CPU_write_char;
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rets = [sp++];
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r0 = '\n';
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jump __CPU_write_char;
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__CPU_write_space:
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r0 = ' ';
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jump __CPU_write_char;
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.globl __CPU_write_nybble;
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__CPU_write_nybble:
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r1 = 0x0f;
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r0 = r0 & r1;
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r0 += '0';
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r1 = '9';
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cc = r0 <= r1;
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if cc jump __CPU_write_char;
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r0 += 'a' - '0' - 10;
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jump __CPU_write_char;
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.globl __CPU_write_byte;
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__CPU_write_byte:
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[--sp] = r0;
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[--sp] = rets;
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r0 >>= 4;
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call __CPU_write_nybble;
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rets = [sp++];
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r0 = [sp++];
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jump __CPU_write_nybble;
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__CPU_write_chawmp:
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[--sp] = r0;
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[--sp] = rets;
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r0 >>= 8;
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call __CPU_write_byte;
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rets = [sp++];
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r0 = [sp++];
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jump __CPU_write_byte;
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__CPU_write_gawble:
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[--sp] = r0;
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[--sp] = rets;
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r0 >>= 16;
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call __CPU_write_chawmp;
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rets = [sp++];
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r0 = [sp++];
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jump __CPU_write_chawmp;
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__CPU_dump_registers:
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[--sp] = rets;
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[--sp] = r0;
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[--sp] = r1;
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[--sp] = p0;
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r0 = [sp + 8];
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call __CPU_write_gawble;
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call __CPU_write_space;
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r0 = [sp + 4];
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call __CPU_write_gawble;
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call __CPU_write_space;
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r0 = r2;
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call __CPU_write_gawble;
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call __CPU_write_space;
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r0 = r3;
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call __CPU_write_gawble;
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call __CPU_write_space;
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r0 = r4;
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call __CPU_write_gawble;
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call __CPU_write_space;
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r0 = r5;
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call __CPU_write_gawble;
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call __CPU_write_space;
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r0 = r6;
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call __CPU_write_gawble;
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call __CPU_write_space;
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r0 = r7;
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call __CPU_write_gawble;
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call __CPU_write_crlf;
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r0 = [sp];
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call __CPU_write_gawble;
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call __CPU_write_space;
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r0 = p1;
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call __CPU_write_gawble;
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call __CPU_write_space;
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r0 = p2;
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call __CPU_write_gawble;
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call __CPU_write_space;
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r0 = p3;
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call __CPU_write_gawble;
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call __CPU_write_space;
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r0 = p4;
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call __CPU_write_gawble;
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call __CPU_write_space;
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r0 = p5;
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call __CPU_write_gawble;
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call __CPU_write_space;
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r0 = fp;
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call __CPU_write_gawble;
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call __CPU_write_space;
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r0 = sp;
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r0 += 16;
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call __CPU_write_gawble;
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call __CPU_write_crlf;
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p0 = [sp++];
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r1 = [sp++];
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r0 = [sp++];
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rets = [sp++];
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rts;
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.globl __CPU_Exception_handler;
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__CPU_Exception_handler:
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usp = sp;
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sp.h = 0xffb0;
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sp.l = 0x1000;
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[--sp] = (r7:0,p5:0);
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r0 = 'x';
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call __CPU_write_char;
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jump hcf;
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.globl __CPU_Emulation_handler;
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__CPU_Emulation_handler:
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usp = sp;
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sp.h = 0xffb0;
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sp.l = 0x1000;
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[--sp] = (r7:0,p5:0);
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r0 = 'e';
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call __CPU_write_char;
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jump hcf;
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.globl __CPU_Reset_handler;
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__CPU_Reset_handler:
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usp = sp;
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sp.h = 0xffb0;
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sp.l = 0x1000;
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[--sp] = (r7:0,p5:0);
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r0 = 'r';
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call __CPU_write_char;
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jump hcf;
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.globl __CPU_NMI_handler;
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__CPU_NMI_handler:
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usp = sp;
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sp.h = 0xffb0;
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sp.l = 0x1000;
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[--sp] = (r7:0,p5:0);
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r0 = 'n';
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call __CPU_write_char;
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jump hcf;
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.globl __CPU_Unhandled_Interrupt_handler;
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__CPU_Unhandled_Interrupt_handler:
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usp = sp;
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sp.h = 0xffb0;
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sp.l = 0x1000;
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[--sp] = (r7:0,p5:0);
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call __CPU_write_crlf;
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r0 = 'i';
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call __CPU_write_char;
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p0.h = HI(IPEND);
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p0.l = LO(IPEND);
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r0 = [p0];
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call __CPU_write_chawmp;
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jump hcf;
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hcf:
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idle;
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jump hcf;
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#endif
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/* _CPU_Context_switch
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*
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* This routine performs a normal non-FP context switch.
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*
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* bfin Specific Information:
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*
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* For now we simply save all registers.
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*
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*/
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/* make sure this sequence stays in sync with the definition for
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Context_Control in rtems/score/cpu.h */
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.globl __CPU_Context_switch
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__CPU_Context_switch:
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/* Start saving context R0 = current, R1=heir */
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p0 = r0;
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[p0++] = r4;
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[p0++] = r5;
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[p0++] = r6;
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[p0++] = r7;
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/* save pointer registers */
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[p0++] = p3;
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[p0++] = p4;
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[p0++] = p5;
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[p0++] = fp;
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[p0++] = sp;
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/* save length registers */
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r0 = l0;
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[p0++] = r0;
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r0 = l1;
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[p0++] = r0;
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r0 = l2;
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[p0++] = r0;
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r0 = l3;
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[p0++] = r0;
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/* save rets */
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r0 = rets;
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[p0++] = r0;
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/* save IMASK */
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p1.h = HI(IMASK);
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p1.l = LO(IMASK);
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r0 = [p1];
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[p0++] = r0;
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p0 = r1;
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restore:
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/* restore data registers */
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r4 = [p0++];
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r5 = [p0++];
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r6 = [p0++];
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r7 = [p0++];
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/* restore pointer registers */
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p3 = [p0++];
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p4 = [p0++];
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p5 = [p0++];
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fp = [p0++];
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sp = [p0++];
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/* restore length registers */
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r0 = [p0++];
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l0 = r0;
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r0 = [p0++];
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l1 = r0;
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r0 = [p0++];
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l2 = r0;
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r0 = [p0++];
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l3 = r0;
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/* restore rets */
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r0 = [p0++];
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rets = r0;
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/* restore IMASK */
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r0 = [p0++];
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p1.h = HI(IMASK);
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p1.l = LO(IMASK);
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[p1] = r0;
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rts;
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/*
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* _CPU_Context_restore
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*
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* This routine is generally used only to restart self in an
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* efficient manner. It may simply be a label in _CPU_Context_switch.
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*
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* NOTE: May be unnecessary to reload some registers.
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*
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* Blackfin Specific Information:
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*
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* none
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*
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*/
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.globl __CPU_Context_restore
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__CPU_Context_restore:
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p0 = r0;
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jump restore;
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.globl __ISR_Handler
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.extern __CPU_Interrupt_stack_high;
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.extern __ISR_Nest_level
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.extern __Thread_Dispatch_disable_level
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.extern __Context_Switch_necessary
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.extern __ISR_Signals_to_thread_executing
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__ISR_Handler:
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/* all interrupts are disabled at this point */
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/* the following few items are pushed onto the task stack for at
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most one interrupt; nested interrupts will be using the interrupt
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stack for everything. */
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[--sp] = astat;
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[--sp] = p1;
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[--sp] = p0;
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[--sp] = r1;
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[--sp] = r0;
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p0.h = __ISR_Nest_level;
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p0.l = __ISR_Nest_level;
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r0 = [p0];
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r0 += 1;
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[p0] = r0;
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cc = r0 <= 1 (iu);
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if !cc jump noStackSwitch;
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/* setup interrupt stack */
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r0 = sp;
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p0.h = __CPU_Interrupt_stack_high;
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p0.l = __CPU_Interrupt_stack_high;
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sp = [p0];
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[--sp] = r0;
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noStackSwitch:
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/* disable thread dispatch */
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p0.h = __Thread_Dispatch_disable_level;
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p0.l = __Thread_Dispatch_disable_level;
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r0 = [p0];
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r0 += 1;
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[p0] = r0;
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[--sp] = reti; /* interrupts are now enabled */
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/* figure out what vector we are */
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p0.h = HI(IPEND);
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p0.l = LO(IPEND);
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r1 = [p0];
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/* we should only get here for events that require RTI to return */
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r1 = r1 >> 5;
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r0 = 4;
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/* at least one bit must be set, so this loop will exit */
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vectorIDLoop:
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r0 += 1;
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r1 = rot r1 by -1;
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if !cc jump vectorIDLoop;
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[--sp] = r2;
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p0.h = __ISR_Vector_table;
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p0.l = __ISR_Vector_table;
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r2 = [p0];
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r1 = r0 << 2;
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r1 = r1 + r2;
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p0 = r1;
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p0 = [p0];
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cc = p0 == 0;
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if cc jump noHandler;
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/* r2, r0, r1, p0, p1, astat are already saved */
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[--sp] = a1.x;
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[--sp] = a1.w;
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[--sp] = a0.x;
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[--sp] = a0.w;
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[--sp] = r3;
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[--sp] = p3;
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[--sp] = p2;
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[--sp] = lt1;
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[--sp] = lt0;
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[--sp] = lc1;
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[--sp] = lc0;
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[--sp] = lb1;
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[--sp] = lb0;
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[--sp] = i3;
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[--sp] = i2;
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[--sp] = i1;
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[--sp] = i0;
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[--sp] = m3;
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[--sp] = m2;
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[--sp] = m1;
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[--sp] = m0;
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[--sp] = l3;
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[--sp] = l2;
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[--sp] = l1;
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[--sp] = l0;
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[--sp] = b3;
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[--sp] = b2;
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[--sp] = b1;
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[--sp] = b0;
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[--sp] = rets;
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r1 = fp; /* is this really what should be passed here? */
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/* call user isr; r0 = vector number, r1 = frame pointer */
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sp += -12; /* bizarre abi... */
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call (p0);
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sp += 12;
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rets = [sp++];
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b0 = [sp++];
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b1 = [sp++];
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b2 = [sp++];
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b3 = [sp++];
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l0 = [sp++];
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l1 = [sp++];
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l2 = [sp++];
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l3 = [sp++];
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m0 = [sp++];
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m1 = [sp++];
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m2 = [sp++];
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m3 = [sp++];
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i0 = [sp++];
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i1 = [sp++];
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i2 = [sp++];
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i3 = [sp++];
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lb0 = [sp++];
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lb1 = [sp++];
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lc0 = [sp++];
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lc1 = [sp++];
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lt0 = [sp++];
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lt1 = [sp++];
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p2 = [sp++];
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p3 = [sp++];
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r3 = [sp++];
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a0.w = [sp++];
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a0.x = [sp++];
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a1.w = [sp++];
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a1.x = [sp++];
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noHandler:
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r2 = [sp++];
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/* this disables interrupts again */
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reti = [sp++];
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p0.h = __ISR_Nest_level;
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p0.l = __ISR_Nest_level;
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r0 = [p0];
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r0 += -1;
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[p0] = r0;
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cc = r0 == 0;
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if !cc jump noStackRestore;
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sp = [sp];
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noStackRestore:
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/* check this stuff to ensure context_switch_necessary and
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isr_signals_to_thread_executing are being handled appropriately. */
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p0.h = __Thread_Dispatch_disable_level;
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p0.l = __Thread_Dispatch_disable_level;
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r0 = [p0];
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r0 += -1;
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[p0] = r0;
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cc = r0 == 0;
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if !cc jump noDispatch
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/* do thread dispatch if necessary */
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p0.h = __Context_Switch_necessary;
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p0.l = __Context_Switch_necessary;
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r0 = B[p0] (Z);
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cc = r0 == 0;
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p0.h = __ISR_Signals_to_thread_executing;
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p0.l = __ISR_Signals_to_thread_executing;
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if !cc jump doDispatch
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r0 = B[p0] (Z);
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cc = r0 == 0;
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if cc jump noDispatch
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doDispatch:
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r0 = 0;
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B[p0] = r0;
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raise 15;
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noDispatch:
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r0 = [sp++];
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r1 = [sp++];
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p0 = [sp++];
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p1 = [sp++];
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astat = [sp++];
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rti
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/* the approach here is for the main interrupt handler, when a dispatch is
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wanted, to do a "raise 15". when the main interrupt handler does its
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"rti", the "raise 15" takes effect and we end up here. we can now
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safely call _Thread_Dispatch, and do an "rti" to get back to the
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original interrupted function. this does require self-nesting to be
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enabled; the maximum nest depth is the number of tasks. */
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.global __ISR15_Handler
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.extern __Thread_Dispatch
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__ISR15_Handler:
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[--sp] = reti;
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[--sp] = rets;
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[--sp] = astat;
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[--sp] = a1.x;
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[--sp] = a1.w;
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[--sp] = a0.x;
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[--sp] = a0.w;
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[--sp] = r3;
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[--sp] = r2;
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[--sp] = r1;
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[--sp] = r0;
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[--sp] = p3;
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[--sp] = p2;
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[--sp] = p1;
|
|
[--sp] = p0;
|
|
[--sp] = lt1;
|
|
[--sp] = lt0;
|
|
[--sp] = lc1;
|
|
[--sp] = lc0;
|
|
[--sp] = lb1;
|
|
[--sp] = lb0;
|
|
[--sp] = i3;
|
|
[--sp] = i2;
|
|
[--sp] = i1;
|
|
[--sp] = i0;
|
|
[--sp] = m3;
|
|
[--sp] = m2;
|
|
[--sp] = m1;
|
|
[--sp] = m0;
|
|
[--sp] = l3;
|
|
[--sp] = l2;
|
|
[--sp] = l1;
|
|
[--sp] = l0;
|
|
[--sp] = b3;
|
|
[--sp] = b2;
|
|
[--sp] = b1;
|
|
[--sp] = b0;
|
|
sp += -12; /* bizarre abi... */
|
|
call __Thread_Dispatch;
|
|
sp += 12;
|
|
b0 = [sp++];
|
|
b1 = [sp++];
|
|
b2 = [sp++];
|
|
b3 = [sp++];
|
|
l0 = [sp++];
|
|
l1 = [sp++];
|
|
l2 = [sp++];
|
|
l3 = [sp++];
|
|
m0 = [sp++];
|
|
m1 = [sp++];
|
|
m2 = [sp++];
|
|
m3 = [sp++];
|
|
i0 = [sp++];
|
|
i1 = [sp++];
|
|
i2 = [sp++];
|
|
i3 = [sp++];
|
|
lb0 = [sp++];
|
|
lb1 = [sp++];
|
|
lc0 = [sp++];
|
|
lc1 = [sp++];
|
|
lt0 = [sp++];
|
|
lt1 = [sp++];
|
|
p0 = [sp++];
|
|
p1 = [sp++];
|
|
p2 = [sp++];
|
|
p3 = [sp++];
|
|
r0 = [sp++];
|
|
r1 = [sp++];
|
|
r2 = [sp++];
|
|
r3 = [sp++];
|
|
a0.w = [sp++];
|
|
a0.x = [sp++];
|
|
a1.w = [sp++];
|
|
a1.x = [sp++];
|
|
astat = [sp++];
|
|
rets = [sp++];
|
|
reti = [sp++];
|
|
rti;
|
|
|