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https://gitlab.rtems.org/rtems/rtos/rtems.git
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396 lines
8.8 KiB
ArmAsm
396 lines
8.8 KiB
ArmAsm
/* start.S
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*
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* This file contains the entry veneer for RTEMS programs
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* on the MBX8xx board.
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* It jumps to the BSP which is responsible for performing
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* all remaining initialization.
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*
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* This file is based on several others:
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*
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* (1) start360.s from the gen68360 BSP by
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* W. Eric Norum (eric@skatter.usask.ca)
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* with the following copyright and license:
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*
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* COPYRIGHT (c) 1989-1998.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may in
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* the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* (2) start.s for the eth_comm port by
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* Jay Monkman (jmonkman@fracsa.com),
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* which itself is based on the
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*
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* (3) dlentry.s for the Papyrus BSP, written by:
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* Andrew Bray <andy@i-cubed.co.uk>
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* with the following copyright and license:
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*
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* COPYRIGHT (c) 1995 by i-cubed ltd.
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*
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* (4) start860.S for the MBX821/MBX860, written by:
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* Darlene A. Stewart <darlene.stewart@iit.nrc.ca>
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* Copyright (c) 1999, National Research Council of Canada
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*
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* To anyone who acknowledges that this file is provided "AS IS"
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* without any express or implied warranty:
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* permission to use, copy, modify, and distribute this file
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* for any purpose is hereby granted without fee, provided that
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* the above copyright notice and this notice appears in all
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* copies, and that the name of i-cubed limited not be used in
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* advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission.
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* i-cubed limited makes no representations about the suitability
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* of this software for any purpose.
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*
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* Modifications (for MBX8xx) of respective RTEMS files:
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* Copyright (c) 1999, National Research Council of Canada
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*/
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#include <rtems/asm.h>
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/*
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* The initial stack is set to run BELOW the code base address.
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* (between the vectors and text sections)
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*
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* All the entry veneer has to do is to clear the BSS.
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*/
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/*
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* GDB likes to have debugging information for the entry veneer.
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* Play compiler and provide some DWARF information.
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*
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* CHANGE TO SUIT YOUR SETUP!
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*/
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.section .entry,"ax",@progbits
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.L_text_b:
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.L_LC1:
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.previous
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.section .debug_sfnames
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.L_sfnames_b:
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.byte "rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/"
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.byte 0
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.L_F0:
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.byte "start.S"
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.byte 0
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.previous
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.section .line
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.L_line_b:
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.4byte .L_line_e-.L_line_b
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.4byte .L_text_b
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.L_LE1:
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.L_line_last:
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.4byte 0x0
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.2byte 0xffff
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.4byte .L_text_e-.L_text_b
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.L_line_e:
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.previous
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.section .debug_srcinfo
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.L_srcinfo_b:
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.4byte .L_line_b
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.4byte .L_sfnames_b
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.4byte .L_text_b
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.4byte .L_text_e
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.4byte 0xffffffff
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.4byte .L_LE1-.L_line_b
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.4byte .L_F0-.L_sfnames_b
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.4byte .L_line_last-.L_line_b
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.4byte 0xffffffff
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.previous
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.section .debug_pubnames
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.4byte .L_debug_b
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.4byte .L_P0
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.byte "start"
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.byte 0
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.4byte 0x0
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.byte 0
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.previous
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.section .debug_aranges
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.4byte .L_debug_b
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.4byte .L_text_b
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.4byte .L_text_e-.L_text_b
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.4byte 0
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.4byte 0
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.4byte 0
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.4byte 0
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.4byte 0
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.4byte 0
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.4byte 0x0
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.4byte 0x0
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.previous
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.section .debug
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.L_debug_b:
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.L_D1:
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.4byte .L_D1_e-.L_D1
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.2byte 0x11 /* TAG_compile_unit */
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.2byte 0x12 /* AT_sibling */
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.4byte .L_D2
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.2byte 0x38 /* AT_name */
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.byte "start.S"
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.byte 0
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.2byte 0x258 /* AT_producer */
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.byte "GAS 2.5.2"
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.byte 0
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.2byte 0x111 /* AT_low_pc */
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.4byte .L_text_b
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.2byte 0x121 /* AT_high_pc */
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.4byte .L_text_e
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.2byte 0x106 /* AT_stmt_list */
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.4byte .L_line_b
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.2byte 0x1b8 /* AT_comp_dir */
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.byte "rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/"
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.byte 0
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.2byte 0x8006 /* AT_sf_names */
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.4byte .L_sfnames_b
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.2byte 0x8016 /* AT_src_info */
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.4byte .L_srcinfo_b
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.L_D1_e:
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.L_P0:
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.L_D3:
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.4byte .L_D3_e-.L_D3
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.2byte 0x6 /* TAG_global_subroutine */
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.2byte 0x12 /* AT_sibling */
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.4byte .L_D4
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.2byte 0x38 /* AT_name */
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.byte "start"
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.byte 0
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.2byte 0x278 /* AT_prototyped */
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.byte 0
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.2byte 0x111 /* AT_low_pc */
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.4byte .L_text_b
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.2byte 0x121 /* AT_high_pc */
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.4byte .L_text_e
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.2byte 0x8041 /* AT_body_begin */
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.4byte .L_text_b
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.2byte 0x8051 /* AT_body_end */
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.4byte .L_text_e
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.L_D3_e:
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.L_D4:
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.4byte .L_D4_e-.L_D4
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.align 2
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.L_D4_e:
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.L_D2:
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.previous
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/*
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* Tell C's eabi-ctor's that we have an atexit function,
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* and that it is to register __do_global_dtors.
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*/
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EXTERN_PROC(atexit)
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PUBLIC_VAR(__atexit)
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.section ".sdata","aw"
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.align 2
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SYM(__atexit):
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EXT_PROC_REF(atexit)@fixup
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.previous
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.section ".fixup","aw"
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.align 2
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EXT_SYM_REF(__atexit)
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.previous
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/* That should do it */
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/*
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* Put the entry point in its own section. That way, we can guarantee
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* to put it first in the .text section in the linker script.
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*/
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.section .entry
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PUBLIC_VAR (start)
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SYM(start):
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bl .startup /* or bl .spin */
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base_addr:
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/*
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* Parameters from linker
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*/
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toc_pointer:
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.long __GOT_START__
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bss_length:
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.long bss.size
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bss_addr:
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.long bss.start
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PUBLIC_VAR (text_addr)
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text_addr:
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.long text.start
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PUBLIC_VAR (text_length)
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text_length:
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.long text.size
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/*
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* Spin, if necessary, to acquire control from debugger (CodeWarrior).
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*/
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spin:
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.long 0x0001
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.spin:
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lis r3, spin@ha
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lwz r3, spin@l(r3)
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cmpwi r3, 0x1
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beq .spin
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/*
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* #define LOADED_BY_EPPCBUG
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*/
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#define LOADED_BY_EPPCBUG
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#define EARLY_CONSOLE
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/*
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* Initialization code
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*/
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.startup:
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/* Get the start address. */
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mflr r1
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#ifdef LOADED_BY_EPPCBUG
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/* Save pointer to residual/board data */
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lis r9,eppcbugInfo@ha
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stw r3,eppcbugInfo@l(r9)
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#endif
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/* Initialize essential registers. */
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bl initregs
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nop
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/*
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* C_setup.
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*/
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/* set toc */
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lwz r2, toc_pointer-base_addr(r1)
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/* Set up stack pointer = beginning of text section - 56 */
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addi r1, r1, -56-4
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/* Initialize the memory mapped MPC821 registers (done in C). */
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EXTERN_PROC (_InitMBX8xx)
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bl PROC (_InitMBX8xx)
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nop
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/* Clear the bss section. */
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bl bssclr
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nop
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#if defined(EARLY_CONSOLE) && defined(LOADED_BY_EPPCBUG)
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EXTERN_PROC (serial_init)
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bl PROC (serial_init)
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#endif
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lis r5,environ@ha
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la r5,environ@l(r5) /* environp */
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/* clear argc and argv */
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xor r3, r3, r3
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xor r4, r4, r4
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EXTERN_PROC (boot_card)
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bl PROC (boot_card) /* call the first C routine */
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nop
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/* we should never return from boot_card, but in case we do ... */
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/* The next instructions are dependent on your runtime environment */
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/* Return to EPPCBug */
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lis r10, 0x0400 /* Data cache disable */
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mtspr 568, r10
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isync
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mtspr 560, r10 /* Instruction cache disable */
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isync
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stop_here:
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li r10, 0x0F00 /* .RETURN */
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sc
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b stop_here
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nop
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/*
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* bssclr - zero out bss
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*/
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bssclr:
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lis r3, base_addr@ha
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addi r3, r3, base_addr@l
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lwz r4, bss_addr-base_addr(r3) /* Start of bss */
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lwz r5, bss_length-base_addr(r3) /* Length of bss */
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rlwinm. r5,r5,30,0x3FFFFFFF /* form length/4 */
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beqlr /* no bss - return */
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mtctr r5 /* set ctr reg */
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li r5,0x0000 /* r5 = 0 */
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clear_bss:
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stw r5,0(r4) /* store r6 */
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addi r4,r4,0x4 /* update r4 */
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bdnz clear_bss /* dec counter and loop */
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blr /* return */
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/*
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* initregs
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* Initialize the MSR and basic core PowerPC registers
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*
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* Register usage:
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* r0 - scratch
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*/
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initregs:
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/*
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* Disable address translation. We should already be running in real space,
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* so this should be a no-op, i.e. no need to switch instruction stream
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* addresses from virtual space to real space. Other bits set the processor
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* for big-endian mode, exceptions vectored to 0x000n_nnnn (vectors are
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* already in low memory!), no execution tracing, machine check exceptions
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* enabled, floating-point not available (MPC8xx has none), supervisor
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* priviledge level, external interrupts disabled, power management
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* disabled (normal operation mode).
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*/
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li r0, 0x1000 /* MSR_ME */
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mtmsr r0 /* Context-synchronizing */
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isync
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/*
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* Clear the exception handling registers.
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* Note SPRG3 is reserved for use by EPPCBug on the MBX8xx.
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*/
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li r0, 0x0000
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mtdar r0
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mtspr sprg0, r0
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mtspr sprg1, r0
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mtspr sprg2, r0
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mtspr srr0, r0
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mtspr srr1, r0
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mr r6, r0
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mr r7, r0
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mr r8, r0
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mr r9, r0
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mr r10, r0
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mr r11, r0
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mr r12, r0
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mr r13, r0
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mr r14, r0
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mr r15, r0
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mr r16, r0
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mr r17, r0
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mr r18, r0
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mr r19, r0
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mr r20, r0
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mr r21, r0
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mr r22, r0
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mr r23, r0
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mr r24, r0
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mr r25, r0
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mr r26, r0
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mr r27, r0
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mr r28, r0
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mr r29, r0
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mr r30, r0
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mr r31, r0
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blr /* return */
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.L_text_e:
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