mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
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2f56b7375a
- Add support to the BSP to enable irq-generic management - Update the powerpc shared irq code to support irq-generic. This is an opt in option for existing powerpc bsps. This change should be simpler now - Fix a number of issues in ISA IRQ controller handling by porting fixes from the i386 (PC) BSP Closes #4247 Closes #4248
331 lines
7.8 KiB
C
331 lines
7.8 KiB
C
/*
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*
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* This file contains the i8259/openpic-specific implementation of
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* the function described in irq.h
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*
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* Copyright (C) 1998, 1999 valette@crf.canon.fr
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <stdlib.h>
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#include <bsp.h>
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#include <bsp/irq.h>
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#include <bsp/irq_supp.h>
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#include <bsp/irq-generic.h>
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#ifndef BSP_HAS_NO_VME
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#include <bsp/VMEConfig.h>
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#endif
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#if BSP_PCI_IRQ_NUMBER > 0
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#include <bsp/openpic.h>
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#endif
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#include <libcpu/io.h>
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#include <bsp/vectors.h>
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#include <stdlib.h>
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#include <rtems/bspIo.h> /* for printk */
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#ifndef qemu
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#define RAVEN_INTR_ACK_REG 0xfeff0030
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#else
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#define RAVEN_INTR_ACK_REG 0xbffffff0
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#endif
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#if BSP_ISA_IRQ_NUMBER > 0
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/*
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* pointer to the mask representing the additionnal irq vectors
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* that must be disabled when a particular entry is activated.
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* They will be dynamically computed from the priority table given
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* in BSP_rtems_irq_mngt_set();
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* CAUTION : this table is accessed directly by interrupt routine
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* prologue.
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*/
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rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_NUMBER];
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#endif
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/*
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* default handler connected on each irq after bsp initialization
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*/
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static rtems_irq_connect_data default_rtems_entry;
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static rtems_irq_connect_data* rtems_hdl_tbl;
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#if BSP_ISA_IRQ_NUMBER > 0
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/*
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* Check if IRQ is an ISA IRQ
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*/
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static inline int is_isa_irq(const rtems_irq_number irqLine)
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{
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return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &&
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((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
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);
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}
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#endif
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#if BSP_PCI_IRQ_NUMBER > 0
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/*
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* Check if IRQ is an OPENPIC IRQ
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*/
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static inline int is_pci_irq(const rtems_irq_number irqLine)
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{
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return OpenPIC && (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &&
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((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
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);
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}
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#endif
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/*
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* ------------------------ RTEMS Irq helper functions ----------------
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*/
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#if BSP_ISA_IRQ_NUMBER > 0
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/*
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* Caution : this function assumes the variable "*config"
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* is already set and that the tables it contains are still valid
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* and accessible.
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*/
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static void compute_i8259_masks_from_prio (rtems_irq_global_settings* config)
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{
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int i;
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int j;
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/*
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* Always mask at least current interrupt to prevent re-entrance
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*/
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for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
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* ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
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for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) {
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/*
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* Mask interrupts at i8259 level that have a lower priority
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*/
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if (config->irqPrioTbl [i] > config->irqPrioTbl [j]) {
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* ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j);
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}
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}
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}
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}
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#endif
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void
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BSP_enable_irq_at_pic(const rtems_irq_number name)
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{
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#if BSP_ISA_IRQ_NUMBER > 0
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if (is_isa_irq(name)) {
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/*
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* Enable interrupt at PIC level
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*/
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BSP_irq_enable_at_i8259s ((int) name - BSP_ISA_IRQ_LOWEST_OFFSET);
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}
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#endif
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#if BSP_PCI_IRQ_NUMBER > 0
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if (is_pci_irq(name)) {
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/*
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* Enable interrupt at OPENPIC level
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*/
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openpic_enable_irq ((int) name - BSP_PCI_IRQ_LOWEST_OFFSET);
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}
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#endif
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}
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int
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BSP_disable_irq_at_pic(const rtems_irq_number name)
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{
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#if BSP_ISA_IRQ_NUMBER > 0
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if (is_isa_irq(name)) {
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/*
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* disable interrupt at PIC level
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*/
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return BSP_irq_disable_at_i8259s ((int) name - BSP_ISA_IRQ_LOWEST_OFFSET);
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}
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#endif
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#if BSP_PCI_IRQ_NUMBER > 0
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if (is_pci_irq(name)) {
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/*
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* disable interrupt at OPENPIC level
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*/
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return openpic_disable_irq ((int) name - BSP_PCI_IRQ_LOWEST_OFFSET);
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}
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#endif
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return -1;
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}
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/*
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* RTEMS Global Interrupt Handler Management Routines
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*/
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int BSP_setup_the_pic(rtems_irq_global_settings* config)
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{
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int i;
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/*
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* Store various code accelerators
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*/
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default_rtems_entry = config->defaultEntry;
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rtems_hdl_tbl = config->irqHdlTbl;
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/*
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* set up internal tables used by rtems interrupt prologue
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*/
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#if BSP_ISA_IRQ_NUMBER > 0
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/*
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* start with ISA IRQ
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*/
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compute_i8259_masks_from_prio (config);
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for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
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if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
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BSP_irq_enable_at_i8259s (i);
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}
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else {
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BSP_irq_disable_at_i8259s (i);
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}
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}
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if ( BSP_ISA_IRQ_NUMBER > 0 ) {
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/*
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* must enable slave pic anyway
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*/
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BSP_irq_enable_at_i8259s (2);
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}
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#endif
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#if BSP_PCI_IRQ_NUMBER > 0
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if ( ! OpenPIC )
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return 1;
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/*
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* continue with PCI IRQ
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*/
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for (i=BSP_PCI_IRQ_LOWEST_OFFSET; i < BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER ; i++) {
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/*
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* Note that openpic_set_priority() sets the TASK priority of the PIC
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*/
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openpic_set_source_priority(i - BSP_PCI_IRQ_LOWEST_OFFSET,
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config->irqPrioTbl[i]);
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if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
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openpic_enable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET);
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}
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else {
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openpic_disable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET);
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}
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}
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#ifdef BSP_PCI_ISA_BRIDGE_IRQ
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/*
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* Must enable PCI/ISA bridge IRQ
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*/
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openpic_enable_irq (BSP_PCI_ISA_BRIDGE_IRQ - BSP_PCI_IRQ_LOWEST_OFFSET);
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#endif
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#endif
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return 1;
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}
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int _BSP_vme_bridge_irq = -1;
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unsigned BSP_spuriousIntr = 0;
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/*
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* High level IRQ handler called from shared_raw_irq_code_entry
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*/
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int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
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{
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register unsigned int irq;
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#if BSP_ISA_IRQ_NUMBER > 0
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register unsigned isaIntr; /* boolean */
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register unsigned oldMask = 0; /* old isa pic masks */
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#endif
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if (excNum == ASM_DEC_VECTOR) {
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#ifdef BSP_POWERPC_IRQ_GENERIC_SUPPORT
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bsp_interrupt_handler_dispatch(BSP_DECREMENTER);
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#else
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bsp_irq_dispatch_list(rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_entry.hdl);
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#endif
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return 0;
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}
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#if BSP_PCI_IRQ_NUMBER > 0
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if ( OpenPIC ) {
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irq = openpic_irq(0);
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if (irq == OPENPIC_VEC_SPURIOUS) {
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++BSP_spuriousIntr;
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return 0;
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}
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/* some BSPs might want to use a different numbering... */
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irq = irq - OPENPIC_VEC_SOURCE + BSP_PCI_IRQ_LOWEST_OFFSET;
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} else {
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#if BSP_ISA_IRQ_NUMBER > 0
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#ifdef BSP_PCI_ISA_BRIDGE_IRQ
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irq = BSP_PCI_ISA_BRIDGE_IRQ;
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#else
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#error "Configuration Error -- BSP with ISA + PCI IRQs MUST define BSP_PCI_ISA_BRIDGE_IRQ"
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#endif
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#else
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rtems_panic("MUST have an OpenPIC if BSP has PCI IRQs but no ISA IRQs");
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/* rtems_panic() never returns but the 'return' statement silences
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* a compiler warning about 'irq' possibly being used w/o initialization.
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*/
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return -1;
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#endif
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}
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#endif
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#if BSP_ISA_IRQ_NUMBER > 0
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#ifdef BSP_PCI_ISA_BRIDGE_IRQ
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#if 0 == BSP_PCI_IRQ_NUMBER
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#error "Configuration Error -- BSP w/o PCI IRQs MUST NOT define BSP_PCI_ISA_BRIDGE_IRQ"
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#endif
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isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ);
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#else
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isaIntr = 1;
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#endif
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if (isaIntr) {
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/*
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* Acknowledge and read 8259 vector
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*/
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irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG);
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/*
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* store current PIC mask
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*/
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oldMask = BSP_irq_suspend_i8259s(irq_mask_or_tbl [irq]);
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BSP_irq_ack_at_i8259s (irq);
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#if BSP_PCI_IRQ_NUMBER > 0
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if ( OpenPIC )
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openpic_eoi(0);
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#endif
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}
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#endif
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/* dispatch handlers */
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#ifdef BSP_POWERPC_IRQ_GENERIC_SUPPORT
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bsp_interrupt_handler_dispatch(irq);
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#else
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bsp_irq_dispatch_list(rtems_hdl_tbl, irq, default_rtems_entry.hdl);
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#endif
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#if BSP_ISA_IRQ_NUMBER > 0
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if (isaIntr) {
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BSP_irq_resume_i8259s(oldMask);
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}
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else
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#endif
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{
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#if BSP_PCI_IRQ_NUMBER > 0
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#ifdef BSP_PCI_VME_DRIVER_DOES_EOI
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/* leave it to the VME bridge driver to do EOI, so
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* it can re-enable the openpic while handling
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* VME interrupts (-> VME priorities in software)
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*/
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if (_BSP_vme_bridge_irq != irq && OpenPIC)
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#endif
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openpic_eoi(0);
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#else
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do {} while (0);
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#endif
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}
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return 0;
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}
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