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152 lines
3.3 KiB
Perl
152 lines
3.3 KiB
Perl
@c
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@c COPYRIGHT (c) 1988-2002.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@ifinfo
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@end ifinfo
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@chapter MIPS Specific Information
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This chapter discusses the MIPS architecture dependencies
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in this port of RTEMS. The MIPS family has a wide variety
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of implementations by a wide range of vendors. Consequently,
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there are many, many CPU models within it.
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@subheading Architecture Documents
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IDT docs are online at http://www.idt.com/products/risc/Welcome.html
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For information on the XXX architecture, refer to the following documents
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available from VENDOR (@file{http//www.XXX.com/}):
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@itemize @bullet
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@item @cite{XXX Family Reference, VENDOR, PART NUMBER}.
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@end itemize
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@c
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@c
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@c
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@section CPU Model Dependent Features
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This section presents the set of features which vary
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across MIPS implementations and are of importance to RTEMS.
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The set of CPU model feature macros are defined in the file
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@code{cpukit/score/cpu/mips/mips.h} based upon the particular CPU
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model specified on the compilation command line.
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@subsection Another Optional Feature
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The macro XXX
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@c
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@c
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@c
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@section Calling Conventions
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@subsection Processor Background
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TBD
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@subsection Calling Mechanism
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TBD
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@subsection Register Usage
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TBD
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@subsection Parameter Passing
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TBD
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@c
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@c
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@c
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@section Memory Model
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@subsection Flat Memory Model
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The MIPS family supports a flat 32-bit address
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space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
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gigabytes). Each address is represented by a 32-bit value and
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is byte addressable. The address may be used to reference a
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single byte, word (2-bytes), or long word (4 bytes). Memory
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accesses within this address space are performed in big endian
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fashion by the processors in this family.
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Some of the MIPS family members such as the support virtual memory and
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segmentation. RTEMS does not support virtual memory or
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segmentation on any of these family members.
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@c
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@c
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@c
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@section Interrupt Processing
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Although RTEMS hides many of the processor dependent
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details of interrupt processing, it is important to understand
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how the RTEMS interrupt manager is mapped onto the processor's
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unique architecture. Discussed in this chapter are the MIPS's
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interrupt response and control mechanisms as they pertain to
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RTEMS.
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@subsection Vectoring of an Interrupt Handler
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Upon receipt of an interrupt the XXX family
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members with separate interrupt stacks automatically perform the
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following actions:
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@itemize @bullet
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@item TBD
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@end itemize
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A nested interrupt is processed similarly by these
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CPU models with the exception that only a single ISF is placed
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on the interrupt stack and the current stack need not be
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switched.
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@subsection Interrupt Levels
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TBD
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@c
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@c
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@c
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@section Default Fatal Error Processing
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The default fatal error handler for this target architecture disables
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processor interrupts, places the error code in @b{XXX}, and executes a
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@code{XXX} instruction to simulate a halt processor instruction.
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@section Symmetric Multiprocessing
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SMP is not supported.
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@section Thread-Local Storage
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Thread-local storage is not implemented.
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@c
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@c
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@c
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@section Board Support Packages
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@subsection System Reset
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An RTEMS based application is initiated or
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re-initiated when the processor is reset. When the
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processor is reset, it performs the following actions:
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@itemize @bullet
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@item TBD
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@end itemize
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@subsection Processor Initialization
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TBD
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