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80 lines
2.1 KiB
Perl
80 lines
2.1 KiB
Perl
@c
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@c Copyright (c) 2015 University of York.
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@c Hesham ALMatary <hmka501@york.ac.uk>
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@ifinfo
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@end ifinfo
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@chapter Epiphany Specific Information
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This chapter discusses the
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@uref{http://adapteva.com/docs/epiphany_sdk_ref.pdf, Epiphany Architecture}
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dependencies in this port of RTEMS. Epiphany is a chip that can come with 16 and
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64 cores, each of which can run RTEMS separately or they can work together to
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run a SMP RTEMS application.
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@subheading Architecture Documents
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For information on the Epiphany architecture refer to the
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@uref{http://adapteva.com/docs/epiphany_arch_ref.pdf,Epiphany Architecture Reference}.
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@section Calling Conventions
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Please refer to the
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@uref{http://adapteva.com/docs/epiphany_sdk_ref.pdf, Epiphany SDK}
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Appendix A: Application Binary Interface
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@subsection Floating Point Unit
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A floating point unit is currently not supported.
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@section Memory Model
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A flat 32-bit memory model is supported, no caches. Each core has its own 32 KiB
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strictly ordered local memory along with an access to a shared 32 MiB external
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DRAM.
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@section Interrupt Processing
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Every Epiphany core has 10 exception types:
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@itemize @bullet
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@item Reset
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@item Software Exception
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@item Data Page Fault
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@item Timer 0
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@item Timer 1
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@item Message Interrupt
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@item DMA0 Interrupt
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@item DMA1 Interrupt
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@item WANT Interrupt
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@item User Interrupt
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@end itemize
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@subsection Interrupt Levels
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There are only two levels: interrupts enabled and interrupts disabled.
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@subsection Interrupt Stack
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The Epiphany RTEMS port uses a dedicated software interrupt stack.
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The stack for interrupts is allocated during interrupt driver initialization.
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When an interrupt is entered, the _ISR_Handler routine is responsible for
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switching from the interrupted task stack to RTEMS software interrupt stack.
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@section Default Fatal Error Processing
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The default fatal error handler for this architecture performs the
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following actions:
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@itemize @bullet
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@item disables operating system supported interrupts (IRQ),
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@item places the error code in @code{r0}, and
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@item executes an infinite loop to simulate a halt processor instruction.
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@end itemize
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@section Symmetric Multiprocessing
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SMP is not supported.
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