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134 lines
4.0 KiB
Perl
134 lines
4.0 KiB
Perl
@c
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@c COPYRIGHT (c) 1988-2009.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@ifinfo
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@end ifinfo
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@chapter Atmel AVR Specific Information
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This chapter discusses the AVR architecture dependencies in this
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port of RTEMS.
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@subheading Architecture Documents
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For information on the AVR architecture, refer to the following
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documents available from Atmel.
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TBD
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@itemize @bullet
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@item See other CPUs for documentation reference formatting examples.
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@end itemize
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@section CPU Model Dependent Features
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CPUs of the AVR 53X only differ in the peripherals and thus in the
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device drivers. This port does not yet support the 56X dual core variants.
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@subsection Count Leading Zeroes Instruction
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The AVR CPU has the XXX instruction which could be used to speed
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up the find first bit operation. The use of this instruction should
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significantly speed up the scheduling associated with a thread blocking.
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@section Calling Conventions
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@subsection Processor Background
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The AVR architecture supports a simple call and return mechanism.
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A subroutine is invoked via the call (@code{call}) instruction.
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This instruction saves the return address in the @code{RETS} register
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and transfers the execution to the given address.
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It is the called funcions responsability to use the link instruction
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to reserve space on the stack for the local variables. Returning from
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a subroutine is done by using the RTS (@code{RTS}) instruction which
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loads the PC with the adress stored in RETS.
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It is is important to note that the @code{call} instruction does not
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automatically save or restore any registers. It is the responsibility
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of the high-level language compiler to define the register preservation
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and usage convention.
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@subsection Register Usage
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A called function may clobber all registers, except RETS, R4-R7, P3-P5,
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FP and SP. It may also modify the first 12 bytes in the caller’s stack
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frame which is used as an argument area for the first three arguments
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(which are passed in R0...R3 but may be placed on the stack by the
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called function).
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@subsection Parameter Passing
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RTEMS assumes that the AVR GCC calling convention is followed.
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The first three parameters are stored in registers R0, R1, and R2.
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All other parameters are put pushed on the stack. The result is returned
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through register R0.
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@section Memory Model
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The AVR family architecutre support a single unified 4 GB byte
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address space using 32-bit addresses. It maps all resources like internal
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and external memory and IO registers into separate sections of this
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common address space.
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The AVR architcture supports some form of memory
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protection via its Memory Management Unit. Since the
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AVR port runs in supervisior mode this memory
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protection mechanisms are not used.
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@section Interrupt Processing
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Discussed in this chapter are the AVR's interrupt response and
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control mechanisms as they pertain to RTEMS.
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@subsection Vectoring of an Interrupt Handler
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TBD
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@subsection Disabling of Interrupts by RTEMS
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During interrupt disable critical sections, RTEMS disables interrupts to
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level N (N) before the execution of this section and restores them
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to the previous level upon completion of the section. RTEMS uses the
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instructions CLI and STI to enable and disable Interrupts. Emulation,
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Reset, NMI and Exception Interrupts are never disabled.
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@subsection Interrupt Stack
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The AVR Architecture works with two different kind of stacks,
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User and Supervisor Stack. Since RTEMS and its Application run
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in supervisor mode, all interrupts will use the interrupted
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tasks stack for execution.
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@section Default Fatal Error Processing
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The default fatal error handler for the AVR performs the following
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actions:
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@itemize @bullet
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@item disables processor interrupts,
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@item places the error code in @b{r0}, and
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@item executes an infinite loop (@code{while(0);} to
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simulate a halt processor instruction.
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@end itemize
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@section Symmetric Multiprocessing
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SMP is not supported.
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@section Thread-Local Storage
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Thread-local storage is not supported due to a broken tool chain.
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@section Board Support Packages
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@subsection System Reset
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TBD
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