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* comm/i386-stub-glue.c, comm/tty_drv.c, comm/uart.c, comm/uart.h: Add the ability to set parity, number of data bits and number of stop bits to the existing i386 serial drivers.
170 lines
5.6 KiB
C
170 lines
5.6 KiB
C
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/*
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* This software is Copyright (C) 1998 by T.sqware - all rights limited
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* It is provided in to the public domain "as is", can be freely modified
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* as far as this copyight notice is kept unchanged, but does not imply
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* an endorsement by T.sqware of the product in which it is included.
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*/
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#ifndef _BSPUART_H
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#define _BSPUART_H
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void BSP_uart_init(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits, int hwFlow);
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void BSP_uart_set_attributes(int uart, unsigned long baud, unsigned long databits, unsigned long parity, unsigned long stopbits);
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void BSP_uart_intr_ctrl(int uart, int cmd);
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void BSP_uart_throttle(int uart);
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void BSP_uart_unthrottle(int uart);
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int BSP_uart_polled_status(int uart);
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void BSP_uart_polled_write(int uart, int val);
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int BSP_uart_polled_read(int uart);
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void BSP_uart_termios_set(int uart, void *ttyp);
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int BSP_uart_termios_write_com1(int minor, const char *buf, int len);
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int BSP_uart_termios_write_com2(int minor, const char *buf, int len);
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void BSP_uart_termios_isr_com1();
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void BSP_uart_termios_isr_com2();
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void BSP_uart_dbgisr_com1(void);
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void BSP_uart_dbgisr_com2(void);
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extern unsigned BSP_poll_char_via_serial(void);
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extern void BSP_output_char_via_serial(int val);
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extern int BSPConsolePort;
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extern int BSPBaseBaud;
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/*
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* Command values for BSP_uart_intr_ctrl(),
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* values are strange in order to catch errors
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* with assert
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*/
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#define BSP_UART_INTR_CTRL_DISABLE (0)
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#define BSP_UART_INTR_CTRL_GDB (0xaa) /* RX only */
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#define BSP_UART_INTR_CTRL_ENABLE (0xbb) /* Normal operations */
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#define BSP_UART_INTR_CTRL_TERMIOS (0xcc) /* RX & line status */
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/* Return values for uart_polled_status() */
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#define BSP_UART_STATUS_ERROR (-1) /* No character */
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#define BSP_UART_STATUS_NOCHAR (0) /* No character */
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#define BSP_UART_STATUS_CHAR (1) /* Character present */
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#define BSP_UART_STATUS_BREAK (2) /* Break point is detected */
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/* PC UART definitions */
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#define BSP_UART_COM1 (0)
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#define BSP_UART_COM2 (1)
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/*
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* Base IO for UART
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*/
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#define COM1_BASE_IO 0x3F8
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#define COM2_BASE_IO 0x2F8
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/*
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* Offsets from base
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*/
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/* DLAB 0 */
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#define RBR (0) /* Rx Buffer Register (read) */
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#define THR (0) /* Tx Buffer Register (write) */
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#define IER (1) /* Interrupt Enable Register */
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/* DLAB X */
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#define IIR (2) /* Interrupt Ident Register (read) */
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#define FCR (2) /* FIFO Control Register (write) */
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#define LCR (3) /* Line Control Register */
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#define MCR (4) /* Modem Control Register */
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#define LSR (5) /* Line Status Register */
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#define MSR (6) /* Modem Status Register */
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#define SCR (7) /* Scratch register */
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/* DLAB 1 */
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#define DLL (0) /* Divisor Latch, LSB */
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#define DLM (1) /* Divisor Latch, MSB */
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#define AFR (2) /* Alternate Function register */
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/*
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* Interrupt source definition via IIR
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*/
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#define MODEM_STATUS 0
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#define NO_MORE_INTR 1
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#define TRANSMITTER_HODING_REGISTER_EMPTY 2
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#define RECEIVER_DATA_AVAIL 4
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#define RECEIVER_ERROR 6
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#define CHARACTER_TIMEOUT_INDICATION 12
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/*
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* Bits definition of IER
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*/
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#define RECEIVE_ENABLE 0x1
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#define TRANSMIT_ENABLE 0x2
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#define RECEIVER_LINE_ST_ENABLE 0x4
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#define MODEM_ENABLE 0x8
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#define INTERRUPT_DISABLE 0x0
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/*
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* Bits definition of the Line Status Register (LSR)
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*/
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#define DR 0x01 /* Data Ready */
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#define OE 0x02 /* Overrun Error */
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#define PE 0x04 /* Parity Error */
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#define FE 0x08 /* Framing Error */
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#define BI 0x10 /* Break Interrupt */
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#define THRE 0x20 /* Transmitter Holding Register Empty */
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#define TEMT 0x40 /* Transmitter Empty */
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#define ERFIFO 0x80 /* Error receive Fifo */
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/*
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* Bits definition of the MODEM Control Register (MCR)
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*/
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#define DTR 0x01 /* Data Terminal Ready */
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#define RTS 0x02 /* Request To Send */
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#define OUT_1 0x04 /* Output 1, (reserved on COMPAQ I/O Board) */
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#define OUT_2 0x08 /* Output 2, Enable Asynchronous Port Interrupts */
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#define LB 0x10 /* Enable Internal Loop Back */
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/*
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* Bits definition of the Line Control Register (LCR)
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*/
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#define CHR_5_BITS 0
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#define CHR_6_BITS 1
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#define CHR_7_BITS 2
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#define CHR_8_BITS 3
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#define WL 0x03 /* Word length mask */
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#define STB 0x04 /* 1 Stop Bit, otherwise 2 Stop Bits */
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#define PEN 0x08 /* Parity Enabled */
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#define EPS 0x10 /* Even Parity Select, otherwise Odd */
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#define SP 0x20 /* Stick Parity */
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#define BCB 0x40 /* Break Control Bit */
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#define DLAB 0x80 /* Enable Divisor Latch Access */
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/*
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* Bits definition of the MODEM Status Register (MSR)
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*/
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#define DCTS 0x01 /* Delta Clear To Send */
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#define DDSR 0x02 /* Delta Data Set Ready */
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#define TERI 0x04 /* Trailing Edge Ring Indicator */
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#define DDCD 0x08 /* Delta Carrier Detect Indicator */
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#define CTS 0x10 /* Clear To Send (when loop back is active) */
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#define DSR 0x20 /* Data Set Ready (when loop back is active) */
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#define RI 0x40 /* Ring Indicator (when loop back is active) */
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#define DCD 0x80 /* Data Carrier Detect (when loop back is active) */
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/*
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* Bits definition of the FIFO Control Register : WD16C552 or NS16550
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*/
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#define FIFO_CTRL 0x01 /* Set to 1 permit access to other bits */
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#define FIFO_EN 0x01 /* Enable the FIFO */
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#define XMIT_RESET 0x02 /* Transmit FIFO Reset */
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#define RCV_RESET 0x04 /* Receive FIFO Reset */
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#define FCR3 0x08 /* do not understand manual! */
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#define RECEIVE_FIFO_TRIGGER1 0x0 /* trigger recieve interrupt after 1 byte */
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#define RECEIVE_FIFO_TRIGGER4 0x40 /* trigger recieve interrupt after 4 byte */
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#define RECEIVE_FIFO_TRIGGER8 0x80 /* trigger recieve interrupt after 8 byte */
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#define RECEIVE_FIFO_TRIGGER12 0xc0 /* trigger recieve interrupt after 12 byte */
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#define TRIG_LEVEL 0xc0 /* Mask for the trigger level */
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#endif /* _BSPUART_H */
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