rtems/testsuites/tmtests/tmtimer01/tmtimer01.scn

 SIS - SPARC/RISCV instruction simulator 2.30,  copyright Jiri Gaisler 2020
 Bug-reports to jiri@gaisler.se

 GR740/LEON4 emulation enabled, 4 cpus online, delta 50 clocks

 Loaded build/sparc/gr740/testsuites/tmtests/tmtimer01.exe, entry 0x00000000


*** BEGIN OF TEST TMTIMER 1 ***
*** TEST VERSION: 6.0.0.76c91ee7793fc70b92e2f87e601c3fdc2d2b7f3f
*** TEST STATE: EXPECTED_PASS
*** TEST BUILD: RTEMS_SMP
*** TEST TOOLS: 13.2.0 20230727 (RTEMS 6, RSB d3d738c35a71ca05f675b188539225099401ac79, Newlib a021448)
*** BEGIN OF JSON DATA ***
{
  "timer-count": 61024,
  "samples": [
    {
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      "middle": 8600,
      "last": 8520
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      "active-timers": 2,
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    }, {
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      "first": 12720,
      "middle": 12980,
      "last": 19500
    }, {
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      "first": 12720,
      "middle": 13400,
      "last": 18160
    }, {
      "active-timers": 3067,
      "first": 13060,
      "middle": 13060,
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    }, {
      "active-timers": 3774,
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    }, {
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      "active-timers": 5714,
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    }, {
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    }, {
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      "first": 14020,
      "middle": 13940,
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    }, {
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    }, {
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      "first": 13900,
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    }, {
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      "first": 13900,
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    }, {
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      "first": 14360,
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    }, {
      "active-timers": 29968,
      "first": 14360,
      "middle": 14540,
      "last": 21300
    }, {
      "active-timers": 36862,
      "first": 14360,
      "middle": 15320,
      "last": 21440
    }, {
      "active-timers": 45342,
      "first": 14580,
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    }, {
      "active-timers": 55772,
      "first": 14700,
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    }, {
      "active-timers": 61023,
      "first": 14780,
      "middle": 15080,
      "last": 22960
    }
  ]
}
*** END OF JSON DATA ***

*** END OF TEST TMTIMER 1 ***

cpu 0 in error mode (tt = 0x80)
 522750200  00009b40:  91d02000   ta  0x0