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* bsp.t, BSP_TIMES, callconv.t, ChangeLog, cpumodel.t, cputable.t, fatalerr.t, intr_NOTIMES.t, Makefile.am, memmodel.t, mips.texi, preface.texi, stamp-vti, timeBSP.t, version.texi: New files.
94 lines
3.1 KiB
Perl
94 lines
3.1 KiB
Perl
@c
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@c COPYRIGHT (c) 1988-2002.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@chapter Board Support Packages
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@section Introduction
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An RTEMS Board Support Package (BSP) must be designed
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to support a particular processor and target board combination.
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This chapter presents a discussion of XXX specific BSP
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issues. For more information on developing a BSP, refer to the
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chapter titled Board Support Packages in the RTEMS
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Applications User's Guide.
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@section System Reset
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An RTEMS based application is initiated or
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re-initiated when the XXX processor is reset. When the
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XXX is reset, the processor performs the following actions:
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@itemize @bullet
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@item The tracing bits of the status register are cleared to
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disable tracing.
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@item The supervisor interrupt state is entered by setting the
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supervisor (S) bit and clearing the master/interrupt (M) bit of
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the status register.
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@item The interrupt mask of the status register is set to
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level 7 to effectively disable all maskable interrupts.
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@item The vector base register (VBR) is set to zero.
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@item The cache control register (CACR) is set to zero to
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disable and freeze the processor cache.
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@item The interrupt stack pointer (ISP) is set to the value
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stored at vector 0 (bytes 0-3) of the exception vector table
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(EVT).
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@item The program counter (PC) is set to the value stored at
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vector 1 (bytes 4-7) of the EVT.
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@item The processor begins execution at the address stored in
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the PC.
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@end itemize
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@section Processor Initialization
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The address of the application's initialization code
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should be stored in the first vector of the EVT which will allow
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the immediate vectoring to the application code. If the
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application requires that the VBR be some value besides zero,
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then it should be set to the required value at this point. All
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tasks share the same XXX's VBR value. Because interrupts
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are enabled automatically by RTEMS as part of the initialize
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executive directive, the VBR MUST be set before this directive
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is invoked to insure correct interrupt vectoring. If processor
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caching is to be utilized, then it should be enabled during the
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reset application initialization code.
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In addition to the requirements described in the
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Board Support Packages chapter of the Applications User's
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Manual for the reset code which is executed before the call to
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initialize executive, the XXX version has the following
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specific requirements:
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@itemize @bullet
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@item Must leave the S bit of the status register set so that
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the XXX remains in the supervisor state.
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@item Must set the M bit of the status register to remove the
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XXX from the interrupt state.
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@item Must set the master stack pointer (MSP) such that a
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minimum stack size of MINIMUM_STACK_SIZE bytes is provided for
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the initialize executive directive.
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@item Must initialize the XXX's vector table.
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@end itemize
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Note that the BSP is not responsible for allocating
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or installing the interrupt stack. RTEMS does this
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automatically as part of initialization. If the BSP does not
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install an interrupt stack and -- for whatever reason -- an
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interrupt occurs before initialize_executive is invoked, then
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the results are unpredictable.
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