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194 lines
6.7 KiB
Perl
194 lines
6.7 KiB
Perl
@c
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@c COPYRIGHT (c) 1988-2002.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@chapter Interrupt Processing
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@section Introduction
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Different types of processors respond to the
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occurrence of an interrupt in its own unique fashion. In
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addition, each processor type provides a control mechanism to
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allow the proper handling of an interrupt. The processor
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dependent response to the interrupt which modifies the execution
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state and results in the modification of the execution stream.
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This modification usually requires that an interrupt handler
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utilize the provided control mechanisms to return to the normal
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processing stream. Although RTEMS hides many of the processor
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dependent details of interrupt processing, it is important to
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understand how the RTEMS interrupt manager is mapped onto the
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processor's unique architecture. Discussed in this chapter are
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the the processor's response and control mechanisms as they
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pertain to RTEMS.
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@section Vectoring of Interrupt Handler
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Upon receipt of an interrupt the i960CA
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automatically performs the following actions:
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@itemize @bullet
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@item saves the local register set,
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@item sets the Frame Pointer (FP) to point to the interrupt
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stack,
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@item increments the FP by sixteen (16) to make room for the
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Interrupt Record,
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@item saves the current values of the arithmetic-controls (AC)
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register, the process-controls (PC) register, and the interrupt
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vector number are saved in the Interrupt Record,
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@item the CPU sets the Instruction Pointer (IP) to the address
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of the first instruction in the interrupt handler,
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@item the return-status field of the Previous Frame Pointer
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(PFP or R0) register is set to interrupt return,
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@item sets the PC state bit to interrupted,
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@item sets the current interrupt disable level in the PC to
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the level of the current interrupt, and
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@item disables tracing.
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@end itemize
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A nested interrupt is processed similarly by the
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i960CA with the exception that the Frame Pointer (FP) already
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points to the interrupt stack. This means that the FP is NOT
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overwritten before space for the Interrupt Record is allocated.
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The state flag bit of the saved PC register in the
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Interrupt Record is examined by RTEMS to determine when an outer
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most interrupt is being exited. Therefore, the user application
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code MUST NOT modify this bit.
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@section Interrupt Record
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The structure of the Interrupt Record for the i960CA
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which is placed on the interrupt stack by the processor in
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response to an interrupt is as follows:
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@ifset use-ascii
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@example
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@group
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+---------------------------+
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| Saved Process Controls | NFP-16
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+---------------------------+
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| Saved Arithmetic Controls | NFP-12
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+---------------------------+
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| UNUSED | NFP-8
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+---------------------------+
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| UNUSED | NFP-4
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+---------------------------+
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@end group
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@end example
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@end ifset
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@ifset use-tex
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@sp 1
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@tex
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\centerline{\vbox{\offinterlineskip\halign{
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\strut\vrule#&
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\hbox to 2.00in{\enskip\hfil#\hfil}&
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\vrule#&
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\hbox to 1.00in{\enskip\hfil#\hfil}
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\cr
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\multispan{3}\hrulefill\cr
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& Saved Process Controls && NFP-16\cr
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\multispan{3}\hrulefill\cr
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& Saved Arithmetic Controls && NFP-12\cr
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\multispan{3}\hrulefill\cr
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& UNUSED && NFP-8\cr
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\multispan{3}\hrulefill\cr
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& UNUSED && NFP-4\cr
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\multispan{3}\hrulefill\cr
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}}\hfil}
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@end tex
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@end ifset
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@ifset use-html
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@html
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<CENTER>
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<TABLE COLS=2 WIDTH="40%" BORDER=2>
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<TR><TD ALIGN=center><STRONG>Saved Process Controls</STRONG></TD>
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<TD ALIGN=center>NFP-16</TD></TR>
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<TR><TD ALIGN=center><STRONG>Saved Arithmetic Controls</STRONG></TD>
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<TD ALIGN=center>NFP-12</TD></TR>
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<TR><TD ALIGN=center><STRONG>UNUSED</STRONG></TD>
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<TD ALIGN=center>NFP-8</TD></TR>
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<TR><TD ALIGN=center><STRONG>UNUSED</STRONG></TD>
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<TD ALIGN=center>NFP-4</TD></TR>
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</TABLE>
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</CENTER>
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@end html
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@end ifset
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@section Interrupt Levels
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Thirty-two levels (0-31) of interrupt priorities are
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supported by the i960CA microprocessor with level thirty-one
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(31) being the highest priority. Level zero (0) indicates that
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interrupts are fully enabled. Interrupt requests for interrupts
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with priorities less than or equal to the current interrupt mask
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level are ignored.
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Although RTEMS supports 256 interrupt levels, the
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i960CA only supports thirty-two. RTEMS interrupt levels 0
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through 31 directly correspond to i960CA interrupt levels. All
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other RTEMS interrupt levels are undefined and their behavior is
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unpredictable.
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@section Disabling of Interrupts by RTEMS
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During the execution of directive calls, critical
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sections of code may be executed. When these sections are
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encountered, RTEMS disables interrupts to level thirty-one (31)
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before the execution of this section and restores them to the
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previous level upon completion of the section. RTEMS has been
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optimized to insure that interrupts are disabled for less than
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RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a
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RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz i960CA with zero wait states.
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These numbers will vary based the number of wait states and
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processor speed present on the target board. [NOTE: This
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calculation was most recently performed for Release
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RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
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Non-maskable interrupts (NMI) cannot be disabled, and
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ISRs which execute at this level MUST NEVER issue RTEMS system
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calls. If a directive is invoked, unpredictable results may
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occur due to the inability of RTEMS to protect its critical
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sections. However, ISRs that make no system calls may safely
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execute as non-maskable interrupts.
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@section Register Cache Flushing
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The i960CA version of the RTEMS interrupt manager is
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optimized to insure that the flushreg instruction is only
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executed when a context switch is necessary. The flushreg
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instruction flushes the i960CA register set cache and takes (14
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+ 23 * number of sets flushed) cycles to execute. As the i960CA
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supports caching of from five to sixteen register sets, this
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instruction takes from 129 to 382 cycles (3.90 to 11.57
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microseconds at 33 Mhz) to execute given no wait state memory.
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RTEMS flushes the register set cache only at the conclusion of
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the outermost ISR when a context switch is necessary. The
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register set cache will not be flushed as part of processing a
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nested interrupt or when a context switch is not necessary.
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This optimization is essential to providing high-performance
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interrupt management on the i960CA.
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@section Interrupt Stack
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On the i960CA, RTEMS allocates the interrupt stack
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from the Workspace Area. The amount of memory allocated for the
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interrupt stack is determined by the interrupt_stack_size field
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in the CPU Configuration Table. During the initialization
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process, RTEMS will install its interrupt stack.
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