mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2025-11-16 12:34:45 +00:00
612 lines
18 KiB
C
612 lines
18 KiB
C
/**
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* @file
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*
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* @ingroup arm_beagle
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*
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* @brief Support for the BeagleBone Black.
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*/
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/**
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* Copyright (c) 2015 Ketul Shah <ketulshah1993 at gmail.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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/* BSP specific function definitions for BeagleBone Black.
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* It is totally beased on Generic GPIO API definition.
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* For more details related to GPIO API please have a
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* look at libbbsp/shared/include/gpio.h
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*/
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#include <bsp/beagleboneblack.h>
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#include <bsp/irq-generic.h>
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#include <bsp/gpio.h>
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#include <bsp/bbb-gpio.h>
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#include <libcpu/am335x.h>
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#include <assert.h>
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#include <stdlib.h>
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#include <stdio.h>
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/* Currently these definitions are for BeagleBone Black board only
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* with modifications from ketul93
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* (https://gist.github.com/ketul93/d717555951174a74c8b4)
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* Later on Beagle-xM board support can be added in this code.
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* After support gets added if condition should be removed
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* HPJ: set almost all I/O to Mode7 to use all for own application
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* This is not yet well structured and good ideas are still needed
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*/
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#if IS_AM335X
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static const uint32_t gpio_bank_addrs[] =
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{ AM335X_GPIO0_BASE,
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AM335X_GPIO1_BASE,
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AM335X_GPIO2_BASE,
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AM335X_GPIO3_BASE };
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static const rtems_vector_number gpio_bank_vector[] =
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{ AM335X_INT_GPIOINT0A,
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AM335X_INT_GPIOINT1A,
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AM335X_INT_GPIOINT2A,
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AM335X_INT_GPIOINT3A };
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/* Macro for the gpio pin not having control module offset mapping */
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#define CONF_NOT_DEFINED 0x00
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/* Mapping of gpio pin number to the Control module mapped register offset */
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// FHI: allmost all, but mmc, used in MUXMODE7 from our applications
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// Macro?
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static const uint32_t gpio_pad_conf [GPIO_BANK_COUNT][BSP_GPIO_PINS_PER_BANK] =
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{
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/* GPIO Module 0 */
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{ CONF_NOT_DEFINED, /* GPIO0[0] */
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CONF_NOT_DEFINED, /* GPIO0[1] */
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AM335X_CONF_SPI0_SCLK, /* GPIO0[2] */
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AM335X_CONF_SPI0_D0, /* GPIO0[3] */
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AM335X_CONF_SPI0_D1, /* GPIO0[4] */
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AM335X_CONF_SPI0_CS0, /* GPIO0[5] */
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CONF_NOT_DEFINED, /* GPIO0[6] */
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AM335X_CONF_ECAP0_IN_PWM0_OUT,/* GPIO0[7] */
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AM335X_CONF_LCD_DATA12, /* GPIO0[8] */
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AM335X_CONF_LCD_DATA13, /* GPIO0[9] */
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AM335X_CONF_LCD_DATA14, /* GPIO0[10] */
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AM335X_CONF_LCD_DATA15, /* GPIO0[11] */
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AM335X_CONF_UART1_CTSN, /* GPIO0[12] */
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AM335X_CONF_UART1_RTSN, /* GPIO0[13] */
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AM335X_CONF_UART1_RXD, /* GPIO0[14] */
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AM335X_CONF_UART1_TXD, /* GPIO0[15] */
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CONF_NOT_DEFINED, /* GPIO0[16] */
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CONF_NOT_DEFINED, /* GPIO0[17] */
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CONF_NOT_DEFINED, /* GPIO0[18] */
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CONF_NOT_DEFINED, /* GPIO0[19] */
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AM335X_CONF_XDMA_EVENT_INTR1, /* GPIO0[20] */
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CONF_NOT_DEFINED, /* GPIO0[21] */
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AM335X_CONF_GPMC_AD8, /* GPIO0[22] */
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AM335X_CONF_GPMC_AD9, /* GPIO0[23] */
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CONF_NOT_DEFINED, /* GPIO0[24] */
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CONF_NOT_DEFINED, /* GPIO0[25] */
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AM335X_CONF_GPMC_AD10, /* GPIO0[26] */
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AM335X_CONF_GPMC_AD11, /* GPIO0[27] */
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CONF_NOT_DEFINED, /* GPIO0[28] */
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CONF_NOT_DEFINED, /* GPIO0[29] */
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AM335X_CONF_GPMC_WAIT0, /* GPIO0[30] */
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AM335X_CONF_GPMC_WPN /* GPIO0[31] */ },
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/* GPIO Module 1 */
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{ AM335X_CONF_GPMC_AD0, /* GPIO1[0] */
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AM335X_CONF_GPMC_AD1, /* GPIO1[1] */
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AM335X_CONF_GPMC_AD2, /* GPIO1[2] */
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AM335X_CONF_GPMC_AD3, /* GPIO1[3] */
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AM335X_CONF_GPMC_AD4, /* GPIO1[4] */
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AM335X_CONF_GPMC_AD5, /* GPIO1[5] */
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AM335X_CONF_GPMC_AD6, /* GPIO1[6] */
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AM335X_CONF_GPMC_AD7, /* GPIO1[7] */
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CONF_NOT_DEFINED, /* GPIO1[8] */
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CONF_NOT_DEFINED, /* GPIO1[9] */
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CONF_NOT_DEFINED, /* GPIO1[10] */
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CONF_NOT_DEFINED, /* GPIO1[11] */
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AM335X_CONF_GPMC_AD12, /* GPIO1[12] */
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AM335X_CONF_GPMC_AD13, /* GPIO1[13] */
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AM335X_CONF_GPMC_AD14, /* GPIO1[14] */
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AM335X_CONF_GPMC_AD15, /* GPIO1[15] */
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AM335X_CONF_GPMC_A0, /* GPIO1[16] */
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AM335X_CONF_GPMC_A1, /* GPIO1[17] */
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AM335X_CONF_GPMC_A2, /* GPIO1[18] */
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AM335X_CONF_GPMC_A3, /* GPIO1[19] */
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CONF_NOT_DEFINED, /* GPIO1[20] */
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AM335X_CONF_GPMC_A5, /* GPIO1[21] */
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AM335X_CONF_GPMC_A6, /* GPIO1[22] */
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AM335X_CONF_GPMC_A7, /* GPIO1[23] */
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AM335X_CONF_GPMC_A8, /* GPIO1[24] */
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CONF_NOT_DEFINED, /* GPIO1[25] */
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CONF_NOT_DEFINED, /* GPIO1[26] */
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CONF_NOT_DEFINED, /* GPIO1[27] */
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AM335X_CONF_GPMC_BEN1, /* GPIO1[28] */
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AM335X_CONF_GPMC_CSN0, /* GPIO1[29] */
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AM335X_CONF_GPMC_CSN1, /* GPIO1[30] */
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AM335X_CONF_GPMC_CSN2 /* GPIO1[31] */ },
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/* GPIO Module 2 */
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{ CONF_NOT_DEFINED, /* GPIO2[0] */
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AM335X_CONF_GPMC_CLK, /* GPIO2[1] */
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AM335X_CONF_GPMC_ADVN_ALE, /* GPIO2[2] */
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AM335X_CONF_GPMC_OEN_REN, /* GPIO2[3] */
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AM335X_CONF_GPMC_WEN, /* GPIO2[4] */
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AM335X_CONF_GPMC_BEN0_CLE, /* GPIO2[5] */
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AM335X_CONF_LCD_DATA0, /* GPIO2[6] */
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AM335X_CONF_LCD_DATA1, /* GPIO2[7] */
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AM335X_CONF_LCD_DATA2, /* GPIO2[8] */
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AM335X_CONF_LCD_DATA3, /* GPIO2[9] */
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AM335X_CONF_LCD_DATA4, /* GPIO2[10] */
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AM335X_CONF_LCD_DATA5, /* GPIO2[11] */
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AM335X_CONF_LCD_DATA6, /* GPIO2[12] */
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AM335X_CONF_LCD_DATA7, /* GPIO2[13] */
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AM335X_CONF_LCD_DATA8, /* GPIO2[14] */
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AM335X_CONF_LCD_DATA9, /* GPIO2[15] */
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AM335X_CONF_LCD_DATA10, /* GPIO2[16] */
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AM335X_CONF_LCD_DATA11, /* GPIO2[17] */
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CONF_NOT_DEFINED, /* GPIO2[18] */
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CONF_NOT_DEFINED, /* GPIO2[19] */
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CONF_NOT_DEFINED, /* GPIO2[20] */
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CONF_NOT_DEFINED, /* GPIO2[21] */
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AM335X_CONF_LCD_VSYNC, /* GPIO2[22] */
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AM335X_CONF_LCD_HSYNC, /* GPIO2[23] */
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AM335X_CONF_LCD_PCLK, /* GPIO2[24] */
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AM335X_CONF_LCD_AC_BIAS_EN /* GPIO2[25] */ },
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/* GPIO Module 3 */
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{ CONF_NOT_DEFINED, /* GPIO3[0] */
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CONF_NOT_DEFINED, /* GPIO3[1] */
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CONF_NOT_DEFINED, /* GPIO3[2] */
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CONF_NOT_DEFINED, /* GPIO3[3] */
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CONF_NOT_DEFINED, /* GPIO3[4] */
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CONF_NOT_DEFINED, /* GPIO3[5] */
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CONF_NOT_DEFINED, /* GPIO3[6] */
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CONF_NOT_DEFINED, /* GPIO3[7] */
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CONF_NOT_DEFINED, /* GPIO3[8] */
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CONF_NOT_DEFINED, /* GPIO3[9] */
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CONF_NOT_DEFINED, /* GPIO3[10] */
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CONF_NOT_DEFINED, /* GPIO3[11] */
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CONF_NOT_DEFINED, /* GPIO3[12] */
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CONF_NOT_DEFINED, /* GPIO3[13] */
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AM335X_CONF_MCASP0_ACLKX, /* GPIO3[14] */
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AM335X_CONF_MCASP0_FSX, /* GPIO3[15] */
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AM335X_CONF_MCASP0_AXR0, /* GPIO3[16] */
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AM335X_CONF_MCASP0_AHCLKR, /* GPIO3[17] */
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CONF_NOT_DEFINED, /* GPIO3[18] */
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AM335X_CONF_MCASP0_FSR, /* GPIO3[19] */
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AM335X_CONF_MCASP0_AXR1, /* GPIO3[20] */
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AM335X_CONF_MCASP0_AHCLKX /* GPIO3[21] */ }
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};
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/* Get the address of Base Register + Offset for pad config */
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uint32_t static inline bbb_conf_reg(uint32_t bank, uint32_t pin)
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{
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/* Asserts if invalid pin is supplied */
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assert(gpio_pad_conf[bank][pin] != CONF_NOT_DEFINED);
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/*
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How to Deal with MUXMODE 7 ?
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*/
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return (AM335X_PADCONF_BASE + gpio_pad_conf[bank][pin]);
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}
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/* Get the value of Base Register + Offset */
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uint32_t static inline bbb_reg(uint32_t bank, uint32_t reg)
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{
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return REG(gpio_bank_addrs[bank] + reg);
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}
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/* Waits a number of CPU cycles. */
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static void arm_delay(uint8_t cycles)
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{
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uint8_t i;
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for ( i = 0; i < cycles; ++i ) {
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asm volatile("nop");
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}
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}
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static rtems_status_code bbb_select_pin_function(
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uint32_t bank,
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uint32_t pin,
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uint32_t type
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) {
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if ( type == BBB_DIGITAL_IN ) {
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mmio_set((gpio_bank_addrs[bank] + AM335X_GPIO_OE), BIT(pin));
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}
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else {
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mmio_clear((gpio_bank_addrs[bank] + AM335X_GPIO_OE), BIT(pin));
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}
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code rtems_gpio_bsp_multi_set(uint32_t bank, uint32_t bitmask)
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{
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mmio_write((gpio_bank_addrs[bank] + AM335X_GPIO_SETDATAOUT), bitmask);
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code rtems_gpio_bsp_multi_clear(uint32_t bank, uint32_t bitmask)
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{
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mmio_write((gpio_bank_addrs[bank] + AM335X_GPIO_CLEARDATAOUT), bitmask);
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return RTEMS_SUCCESSFUL;
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}
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uint32_t rtems_gpio_bsp_multi_read(uint32_t bank, uint32_t bitmask)
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{
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return (mmio_read(gpio_bank_addrs[bank] + AM335X_GPIO_DATAIN) & bitmask);
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}
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rtems_status_code rtems_gpio_bsp_set(uint32_t bank, uint32_t pin)
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{
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mmio_write((gpio_bank_addrs[bank] + AM335X_GPIO_SETDATAOUT), BIT(pin));
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code rtems_gpio_bsp_clear(uint32_t bank, uint32_t pin)
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{
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mmio_write((gpio_bank_addrs[bank] + AM335X_GPIO_CLEARDATAOUT), BIT(pin));
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return RTEMS_SUCCESSFUL;
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}
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uint32_t rtems_gpio_bsp_get_value(uint32_t bank, uint32_t pin)
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{
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return (mmio_read(gpio_bank_addrs[bank] + AM335X_GPIO_DATAIN) & BIT(pin) ? 1:0);
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}
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rtems_status_code rtems_gpio_bsp_select_input(
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uint32_t bank,
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uint32_t pin,
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void *bsp_specific
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) {
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return bbb_select_pin_function(bank, pin, BBB_DIGITAL_IN);
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}
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rtems_status_code rtems_gpio_bsp_select_output(
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uint32_t bank,
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uint32_t pin,
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void *bsp_specific
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) {
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return bbb_select_pin_function(bank, pin, BBB_DIGITAL_OUT);
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}
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rtems_status_code rtems_gpio_bsp_select_specific_io(
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uint32_t bank,
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uint32_t pin,
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uint32_t function,
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void *pin_data
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) {
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return RTEMS_NOT_DEFINED;
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}
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rtems_status_code rtems_bsp_select_specific_io(
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uint32_t bank,
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uint32_t pin,
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uint32_t function,
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void *pin_data
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) {
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return RTEMS_NOT_DEFINED;
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}
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rtems_status_code rtems_gpio_bsp_set_resistor_mode(
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uint32_t bank,
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uint32_t pin,
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rtems_gpio_pull_mode mode
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) {
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uint32_t register_content;
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register_content = BBB_MUXMODE(7);
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/* Set control signal. */
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switch ( mode ) {
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case PULL_UP:
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register_content = register_content | BBB_PU_EN | BBB_RXACTIVE; // assume input
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break;
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case PULL_DOWN:
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break;
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case NO_PULL_RESISTOR:
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register_content = register_content | BBB_PUDDIS;
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break;
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default:
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return RTEMS_UNSATISFIED;
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}
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mmio_write(bbb_conf_reg(bank,pin), register_content);
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return RTEMS_SUCCESSFUL;
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}
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rtems_vector_number rtems_gpio_bsp_get_vector(uint32_t bank)
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{
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return gpio_bank_vector[bank];
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}
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uint32_t rtems_gpio_bsp_interrupt_line(rtems_vector_number vector)
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{
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uint32_t event_status;
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uint8_t bank_nr = 0;
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/* Following loop will get the bank number from vector number */
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while (bank_nr < GPIO_BANK_COUNT && vector != gpio_bank_vector[bank_nr])
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{
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bank_nr++;
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}
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/* Retrieve the interrupt event status. */
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event_status = bbb_reg(bank_nr, AM335X_GPIO_IRQSTATUS_0);
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/* Clear the interrupt line. */
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mmio_write(gpio_bank_addrs[bank_nr] + AM335X_GPIO_IRQSTATUS_0, event_status);
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return event_status;
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}
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rtems_status_code rtems_gpio_bsp_enable_interrupt(
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uint32_t bank,
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uint32_t pin,
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rtems_gpio_interrupt interrupt
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) {
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return rtems_bsp_enable_interrupt(bank, pin, interrupt);
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}
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rtems_status_code rtems_bsp_enable_interrupt(
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uint32_t bank,
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uint32_t pin,
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rtems_gpio_interrupt interrupt
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) {
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switch ( interrupt ) {
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case FALLING_EDGE:
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/* Enables asynchronous falling edge detection. */
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mmio_set(gpio_bank_addrs[bank] + AM335X_GPIO_FALLINGDETECT, BIT(pin));
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break;
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case RISING_EDGE:
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/* Enables asynchronous rising edge detection. */
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mmio_set(gpio_bank_addrs[bank] + AM335X_GPIO_RISINGDETECT, BIT(pin));
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break;
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case BOTH_EDGES:
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/* Enables asynchronous falling edge detection. */
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mmio_set(gpio_bank_addrs[bank] + AM335X_GPIO_FALLINGDETECT, BIT(pin));
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/* Enables asynchronous rising edge detection. */
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mmio_set(gpio_bank_addrs[bank] + AM335X_GPIO_RISINGDETECT, BIT(pin));
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break;
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case LOW_LEVEL:
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/* Enables pin low level detection. */
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mmio_set(gpio_bank_addrs[bank] + AM335X_GPIO_LEVELDETECT0, BIT(pin));
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break;
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case HIGH_LEVEL:
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/* Enables pin high level detection. */
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mmio_set(gpio_bank_addrs[bank] + AM335X_GPIO_LEVELDETECT1, BIT(pin));
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break;
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case BOTH_LEVELS:
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/* Enables pin low level detection. */
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mmio_set(gpio_bank_addrs[bank] + AM335X_GPIO_LEVELDETECT0, BIT(pin));
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/* Enables pin high level detection. */
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mmio_set(gpio_bank_addrs[bank] + AM335X_GPIO_LEVELDETECT1, BIT(pin));
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break;
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case NONE:
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default:
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return RTEMS_UNSATISFIED;
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}
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/*
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printf(" Register for interrupt detection are : \n");
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printf("\t FALLING : 0x%x\n", mmio_read(gpio_bank_addrs[bank] + AM335X_GPIO_FALLINGDETECT));
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printf("\t RISING : 0x%x\n", mmio_read(gpio_bank_addrs[bank] + AM335X_GPIO_RISINGDETECT));
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printf("\t Low Level : 0x%x\n", mmio_read(gpio_bank_addrs[bank] + AM335X_GPIO_LEVELDETECT0));
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printf("\t High Level : 0x%x\n", mmio_read(gpio_bank_addrs[bank] + AM335X_GPIO_LEVELDETECT1));
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*/
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mmio_write(gpio_bank_addrs[bank] + AM335X_GPIO_IRQSTATUS_SET_0, BIT(pin));
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mmio_write(gpio_bank_addrs[bank] + AM335X_GPIO_IRQSTATUS_SET_1, BIT(pin));
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/* The detection starts after 5 clock cycles as per AM335X TRM
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* This period is required to clean the synchronization edge/
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* level detection pipeline
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*/
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arm_delay(5);
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code rtems_gpio_bsp_disable_interrupt(
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uint32_t bank,
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uint32_t pin,
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rtems_gpio_interrupt interrupt
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) {
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return rtems_bsp_disable_interrupt(bank, pin, interrupt);
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}
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rtems_status_code rtems_bsp_disable_interrupt(
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uint32_t bank,
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uint32_t pin,
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rtems_gpio_interrupt interrupt
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) {
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switch ( interrupt ) {
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case FALLING_EDGE:
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/* Disables asynchronous falling edge detection. */
|
|
mmio_clear(gpio_bank_addrs[bank] + AM335X_GPIO_FALLINGDETECT, BIT(pin));
|
|
break;
|
|
case RISING_EDGE:
|
|
/* Disables asynchronous rising edge detection. */
|
|
mmio_clear(gpio_bank_addrs[bank] + AM335X_GPIO_RISINGDETECT, BIT(pin));
|
|
break;
|
|
case BOTH_EDGES:
|
|
/* Disables asynchronous falling edge detection. */
|
|
mmio_clear(gpio_bank_addrs[bank] + AM335X_GPIO_FALLINGDETECT, BIT(pin));
|
|
|
|
/* Disables asynchronous rising edge detection. */
|
|
mmio_clear(gpio_bank_addrs[bank] + AM335X_GPIO_RISINGDETECT, BIT(pin));
|
|
break;
|
|
case LOW_LEVEL:
|
|
/* Disables pin low level detection. */
|
|
mmio_clear(gpio_bank_addrs[bank] + AM335X_GPIO_LEVELDETECT0, BIT(pin));
|
|
break;
|
|
case HIGH_LEVEL:
|
|
/* Disables pin high level detection. */
|
|
mmio_clear(gpio_bank_addrs[bank] + AM335X_GPIO_LEVELDETECT1, BIT(pin));
|
|
break;
|
|
case BOTH_LEVELS:
|
|
/* Disables pin low level detection. */
|
|
mmio_clear(gpio_bank_addrs[bank] + AM335X_GPIO_LEVELDETECT0, BIT(pin));
|
|
|
|
/* Disables pin high level detection. */
|
|
mmio_clear(gpio_bank_addrs[bank] + AM335X_GPIO_LEVELDETECT1, BIT(pin));
|
|
break;
|
|
case NONE:
|
|
default:
|
|
return RTEMS_UNSATISFIED;
|
|
}
|
|
|
|
mmio_write((gpio_bank_addrs[bank] + AM335X_GPIO_IRQSTATUS_CLR_0), BIT(pin));
|
|
mmio_write((gpio_bank_addrs[bank] + AM335X_GPIO_IRQSTATUS_CLR_1), BIT(pin));
|
|
|
|
return RTEMS_SUCCESSFUL;
|
|
}
|
|
|
|
/* I have unfortunately lost the overview a little ....
|
|
*/
|
|
rtems_status_code rtems_gpio_bsp_multi_select(
|
|
rtems_gpio_multiple_pin_select *pins,
|
|
uint32_t pin_count,
|
|
uint32_t select_bank
|
|
) {
|
|
uint8_t i;
|
|
|
|
for ( i = 0; i < pin_count; ++i ) {
|
|
bbb_select_pin_function((pins[i].pin_number)/32, (pins[i].pin_number)%32, pins[i].function);
|
|
}
|
|
return RTEMS_SUCCESSFUL;
|
|
}
|
|
|
|
rtems_status_code rtems_gpio_bsp_specific_group_operation(
|
|
uint32_t bank,
|
|
uint32_t *pins,
|
|
uint32_t pin_count,
|
|
void *arg
|
|
) {
|
|
return RTEMS_NOT_DEFINED;
|
|
}
|
|
#endif /* IS_AM335X */
|
|
|
|
/* For support of BeagleboardxM */
|
|
#if IS_DM3730
|
|
|
|
/* Currently this section is just to satisfy
|
|
* GPIO API and to make the build successful.
|
|
* Later on support can be added here.
|
|
*/
|
|
|
|
rtems_status_code rtems_gpio_bsp_multi_set(uint32_t bank, uint32_t bitmask)
|
|
{
|
|
return RTEMS_NOT_DEFINED;
|
|
}
|
|
|
|
rtems_status_code rtems_gpio_bsp_multi_clear(uint32_t bank, uint32_t bitmask)
|
|
{
|
|
return RTEMS_NOT_DEFINED;
|
|
}
|
|
|
|
uint32_t rtems_gpio_bsp_multi_read(uint32_t bank, uint32_t bitmask)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
rtems_status_code rtems_gpio_bsp_set(uint32_t bank, uint32_t pin)
|
|
{
|
|
return RTEMS_NOT_DEFINED;
|
|
}
|
|
|
|
rtems_status_code rtems_gpio_bsp_clear(uint32_t bank, uint32_t pin)
|
|
{
|
|
return RTEMS_NOT_DEFINED;
|
|
}
|
|
|
|
uint32_t rtems_gpio_bsp_get_value(uint32_t bank, uint32_t pin)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
rtems_status_code rtems_gpio_bsp_select_input(
|
|
uint32_t bank,
|
|
uint32_t pin,
|
|
void *bsp_specific
|
|
) {
|
|
return RTEMS_NOT_DEFINED;
|
|
}
|
|
|
|
rtems_status_code rtems_gpio_bsp_select_output(
|
|
uint32_t bank,
|
|
uint32_t pin,
|
|
void *bsp_specific
|
|
) {
|
|
return RTEMS_NOT_DEFINED;
|
|
}
|
|
|
|
rtems_status_code rtems_gpio_bsp_select_specific_io(
|
|
uint32_t bank,
|
|
uint32_t pin,
|
|
uint32_t function,
|
|
void *pin_data
|
|
) {
|
|
return RTEMS_NOT_DEFINED;
|
|
}
|
|
|
|
rtems_status_code rtems_gpio_bsp_set_resistor_mode(
|
|
uint32_t bank,
|
|
uint32_t pin,
|
|
rtems_gpio_pull_mode mode
|
|
) {
|
|
return RTEMS_NOT_DEFINED;
|
|
}
|
|
|
|
rtems_vector_number rtems_gpio_bsp_get_vector(uint32_t bank)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
uint32_t rtems_gpio_bsp_interrupt_line(rtems_vector_number vector)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
rtems_status_code rtems_gpio_bsp_enable_interrupt(
|
|
uint32_t bank,
|
|
uint32_t pin,
|
|
rtems_gpio_interrupt interrupt
|
|
) {
|
|
return RTEMS_NOT_DEFINED;
|
|
}
|
|
|
|
rtems_status_code rtems_gpio_bsp_disable_interrupt(
|
|
uint32_t bank,
|
|
uint32_t pin,
|
|
rtems_gpio_interrupt interrupt
|
|
) {
|
|
return RTEMS_NOT_DEFINED;
|
|
}
|
|
|
|
rtems_status_code rtems_gpio_bsp_multi_select(
|
|
rtems_gpio_multiple_pin_select *pins,
|
|
uint32_t pin_count,
|
|
uint32_t select_bank
|
|
) {
|
|
return RTEMS_NOT_DEFINED;
|
|
}
|
|
|
|
rtems_status_code rtems_gpio_bsp_specific_group_operation(
|
|
uint32_t bank,
|
|
uint32_t *pins,
|
|
uint32_t pin_count,
|
|
void *arg
|
|
) {
|
|
return RTEMS_NOT_DEFINED;
|
|
}
|
|
|
|
#endif /* IS_DM3730 */
|