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When using QEMU configurations that support SMP for Zynq7000 systems, the second core is started at the same time as the first core instead of waiting for an event to trigger a check for the value at 0xfffffff0 before jumping into RTEMS code. This makes the erroneously started core wait as expected and prevents prefetch and data aborts from occurring before the MMU has been properly configured. This was recently exposed by cleanup done to the ARM GICv2 driver that removed some delays which were allowing this to operate normally.