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4cf93658ef
The previous cache manager support used a single souce file (cache_manager.c) which included an implementation header (cache_.h). This required the use of specialized include paths to find the right header file. Change this to include a generic implementation header (cacheimpl.h) in specialized source files. Use the following directories and files: * bsps/shared/cache * bsps/@RTEMS_CPU@/shared/cache * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c Update #3285.
521 lines
12 KiB
C
521 lines
12 KiB
C
/*
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* Cache Manager
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*
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*
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* The functions in this file implement the API to the RTEMS Cache Manager and
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* are divided into data cache and instruction cache functions. Data cache
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* functions only have bodies if a data cache is supported. Instruction
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* cache functions only have bodies if an instruction cache is supported.
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* Support for a particular cache exists only if CPU_x_CACHE_ALIGNMENT is
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* defined, where x E {DATA, INSTRUCTION}. These definitions are found in
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* the Cache Manager Wrapper header files, often
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*
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* rtems/c/src/lib/libcpu/CPU/cache_.h
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*
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* The cache implementation header file can define
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*
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* #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
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*
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* if it provides cache maintenance functions which operate on multiple lines.
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* Otherwise a generic loop with single line operations will be used. It is
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* strongly recommended to provide the implementation in terms of static
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* inline functions for performance reasons.
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*
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* The functions below are implemented with CPU dependent inline routines
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* found in the cache.c files for each CPU. In the event that a CPU does
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* not support a specific function for a cache it has, the CPU dependent
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* routine does nothing (but does exist).
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*
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* At this point, the Cache Manager makes no considerations, and provides no
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* support for BSP specific issues such as a secondary cache. In such a system,
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* the CPU dependent routines would have to be modified, or a BSP layer added
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* to this Manager.
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*/
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#include <rtems.h>
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#if CPU_DATA_CACHE_ALIGNMENT > CPU_CACHE_LINE_BYTES
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#error "CPU_DATA_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES"
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#endif
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#if CPU_INSTRUCTION_CACHE_ALIGNMENT > CPU_CACHE_LINE_BYTES
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#error "CPU_INSTRUCTION_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES"
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#endif
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#if defined(RTEMS_SMP)
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#include <rtems/score/smpimpl.h>
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typedef struct {
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const void *addr;
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size_t size;
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} smp_cache_area;
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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static void smp_cache_data_flush(void *arg)
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{
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smp_cache_area *area = arg;
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rtems_cache_flush_multiple_data_lines(area->addr, area->size);
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}
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static void smp_cache_data_inv(void *arg)
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{
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smp_cache_area *area = arg;
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rtems_cache_invalidate_multiple_data_lines(area->addr, area->size);
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}
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static void smp_cache_data_flush_all(void *arg)
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{
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rtems_cache_flush_entire_data();
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}
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static void smp_cache_data_inv_all(void *arg)
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{
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rtems_cache_invalidate_entire_data();
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}
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#endif /* defined(CPU_DATA_CACHE_ALIGNMENT) */
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void
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rtems_cache_flush_multiple_data_lines_processor_set(
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const void *addr,
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size_t size,
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const size_t setsize,
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const cpu_set_t *set
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)
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{
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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smp_cache_area area = { addr, size };
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_SMP_Multicast_action( setsize, set, smp_cache_data_flush, &area );
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#endif
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}
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void
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rtems_cache_invalidate_multiple_data_lines_processor_set(
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const void *addr,
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size_t size,
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const size_t setsize,
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const cpu_set_t *set
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)
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{
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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smp_cache_area area = { addr, size };
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_SMP_Multicast_action( setsize, set, smp_cache_data_inv, &area );
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#endif
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}
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void
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rtems_cache_flush_entire_data_processor_set(
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const size_t setsize,
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const cpu_set_t *set
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)
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{
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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_SMP_Multicast_action( setsize, set, smp_cache_data_flush_all, NULL );
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#endif
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}
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void
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rtems_cache_invalidate_entire_data_processor_set(
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const size_t setsize,
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const cpu_set_t *set
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)
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{
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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_SMP_Multicast_action( setsize, set, smp_cache_data_inv_all, NULL );
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#endif
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}
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#endif /* defined(RTEMS_SMP) */
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/*
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* THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE A DATA CACHE
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*/
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/*
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* This function is called to flush the data cache by performing cache
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* copybacks. It must determine how many cache lines need to be copied
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* back and then perform the copybacks.
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*/
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void
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rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes )
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{
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS)
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_CPU_cache_flush_data_range( d_addr, n_bytes );
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#else
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const void * final_address;
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/*
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* Set d_addr to the beginning of the cache line; final_address indicates
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* the last address_t which needs to be pushed. Increment d_addr and push
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* the resulting line until final_address is passed.
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*/
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if( n_bytes == 0 )
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/* Do nothing if number of bytes to flush is zero */
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return;
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final_address = (void *)((size_t)d_addr + n_bytes - 1);
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d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
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while( d_addr <= final_address ) {
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_CPU_cache_flush_1_data_line( d_addr );
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d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
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}
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#endif
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#endif
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}
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/*
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* This function is responsible for performing a data cache invalidate.
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* It must determine how many cache lines need to be invalidated and then
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* perform the invalidations.
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*/
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void
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rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes )
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{
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS)
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_CPU_cache_invalidate_data_range( d_addr, n_bytes );
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#else
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const void * final_address;
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/*
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* Set d_addr to the beginning of the cache line; final_address indicates
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* the last address_t which needs to be invalidated. Increment d_addr and
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* invalidate the resulting line until final_address is passed.
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*/
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if( n_bytes == 0 )
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/* Do nothing if number of bytes to invalidate is zero */
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return;
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final_address = (void *)((size_t)d_addr + n_bytes - 1);
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d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
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while( final_address >= d_addr ) {
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_CPU_cache_invalidate_1_data_line( d_addr );
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d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
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}
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#endif
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#endif
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}
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/*
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* This function is responsible for performing a data cache flush.
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* It flushes the entire cache.
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*/
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void
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rtems_cache_flush_entire_data( void )
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{
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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/*
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* Call the CPU-specific routine
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*/
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_CPU_cache_flush_entire_data();
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#endif
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}
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/*
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* This function is responsible for performing a data cache
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* invalidate. It invalidates the entire cache.
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*/
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void
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rtems_cache_invalidate_entire_data( void )
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{
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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/*
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* Call the CPU-specific routine
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*/
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_CPU_cache_invalidate_entire_data();
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#endif
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}
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/*
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* This function returns the data cache granularity.
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*/
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size_t
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rtems_cache_get_data_line_size( void )
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{
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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return CPU_DATA_CACHE_ALIGNMENT;
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#else
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return 0;
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#endif
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}
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size_t
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rtems_cache_get_data_cache_size( uint32_t level )
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{
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#if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS)
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return _CPU_cache_get_data_cache_size( level );
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#else
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return 0;
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#endif
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}
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/*
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* This function freezes the data cache; cache lines
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* are not replaced.
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*/
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void
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rtems_cache_freeze_data( void )
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{
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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_CPU_cache_freeze_data();
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#endif
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}
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/*
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* This function unfreezes the instruction cache.
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*/
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void rtems_cache_unfreeze_data( void )
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{
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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_CPU_cache_unfreeze_data();
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#endif
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}
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/* Turn on the data cache. */
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void
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rtems_cache_enable_data( void )
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{
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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_CPU_cache_enable_data();
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#endif
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}
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/* Turn off the data cache. */
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void
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rtems_cache_disable_data( void )
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{
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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_CPU_cache_disable_data();
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#endif
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}
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/*
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* THESE FUNCTIONS ONLY HAVE BODIES IF WE HAVE AN INSTRUCTION CACHE
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*/
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#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) \
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&& defined(RTEMS_SMP) \
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&& defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING)
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static void smp_cache_inst_inv(void *arg)
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{
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smp_cache_area *area = arg;
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_CPU_cache_invalidate_instruction_range(area->addr, area->size);
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}
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static void smp_cache_inst_inv_all(void *arg)
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{
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_CPU_cache_invalidate_entire_instruction();
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}
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#endif
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/*
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* This function is responsible for performing an instruction cache
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* invalidate. It must determine how many cache lines need to be invalidated
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* and then perform the invalidations.
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*/
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#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) \
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&& !defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS)
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static void
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_CPU_cache_invalidate_instruction_range(
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const void * i_addr,
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size_t n_bytes
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)
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{
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const void * final_address;
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/*
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* Set i_addr to the beginning of the cache line; final_address indicates
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* the last address_t which needs to be invalidated. Increment i_addr and
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* invalidate the resulting line until final_address is passed.
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*/
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if( n_bytes == 0 )
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/* Do nothing if number of bytes to invalidate is zero */
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return;
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final_address = (void *)((size_t)i_addr + n_bytes - 1);
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i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1));
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while( final_address >= i_addr ) {
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_CPU_cache_invalidate_1_instruction_line( i_addr );
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i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT);
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}
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}
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#endif
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void
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rtems_cache_invalidate_multiple_instruction_lines(
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const void * i_addr,
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size_t n_bytes
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)
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{
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#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
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#if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING)
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smp_cache_area area = { i_addr, n_bytes };
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_SMP_Multicast_action( 0, NULL, smp_cache_inst_inv, &area );
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#else
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_CPU_cache_invalidate_instruction_range( i_addr, n_bytes );
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#endif
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#endif
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}
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/*
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* This function is responsible for performing an instruction cache
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* invalidate. It invalidates the entire cache.
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*/
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void
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rtems_cache_invalidate_entire_instruction( void )
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{
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#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
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#if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING)
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_SMP_Multicast_action( 0, NULL, smp_cache_inst_inv_all, NULL );
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#else
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_CPU_cache_invalidate_entire_instruction();
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#endif
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#endif
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}
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/*
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* This function returns the instruction cache granularity.
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*/
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size_t
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rtems_cache_get_instruction_line_size( void )
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{
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#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
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return CPU_INSTRUCTION_CACHE_ALIGNMENT;
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#else
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return 0;
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#endif
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}
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size_t
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rtems_cache_get_instruction_cache_size( uint32_t level )
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{
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#if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS)
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return _CPU_cache_get_instruction_cache_size( level );
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#else
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return 0;
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#endif
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}
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/*
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* This function freezes the instruction cache; cache lines
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* are not replaced.
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*/
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void
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rtems_cache_freeze_instruction( void )
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{
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#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
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_CPU_cache_freeze_instruction();
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#endif
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}
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/*
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* This function unfreezes the instruction cache.
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*/
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void rtems_cache_unfreeze_instruction( void )
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{
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#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
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_CPU_cache_unfreeze_instruction();
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#endif
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}
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/* Turn on the instruction cache. */
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void
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rtems_cache_enable_instruction( void )
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{
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#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
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_CPU_cache_enable_instruction();
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#endif
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}
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/* Turn off the instruction cache. */
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void
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rtems_cache_disable_instruction( void )
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{
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#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
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_CPU_cache_disable_instruction();
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#endif
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}
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/* Returns the maximal cache line size of all cache kinds in bytes. */
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size_t rtems_cache_get_maximal_line_size( void )
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{
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#if defined(CPU_MAXIMAL_CACHE_ALIGNMENT)
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return CPU_MAXIMAL_CACHE_ALIGNMENT;
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#endif
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size_t max_line_size = 0;
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#if defined(CPU_DATA_CACHE_ALIGNMENT)
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{
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size_t data_line_size = CPU_DATA_CACHE_ALIGNMENT;
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if ( max_line_size < data_line_size )
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max_line_size = data_line_size;
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}
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#endif
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#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
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{
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size_t instruction_line_size = CPU_INSTRUCTION_CACHE_ALIGNMENT;
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if ( max_line_size < instruction_line_size )
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max_line_size = instruction_line_size;
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}
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#endif
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return max_line_size;
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}
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/*
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* Purpose is to synchronize caches after code has been loaded
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* or self modified. Actual implementation is simple only
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* but it can and should be repaced by optimized version
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* which does not need flush and invalidate all cache levels
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* when code is changed.
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*/
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void
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rtems_cache_instruction_sync_after_code_change( const void * code_addr, size_t n_bytes )
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{
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#if defined(CPU_CACHE_SUPPORT_PROVIDES_INSTRUCTION_SYNC_FUNCTION)
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_CPU_cache_instruction_sync_after_code_change( code_addr, n_bytes );
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#else
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rtems_cache_flush_multiple_data_lines( code_addr, n_bytes );
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rtems_cache_invalidate_multiple_instruction_lines( code_addr, n_bytes );
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#endif
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}
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