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2f56b7375a
- Add support to the BSP to enable irq-generic management - Update the powerpc shared irq code to support irq-generic. This is an opt in option for existing powerpc bsps. This change should be simpler now - Fix a number of issues in ISA IRQ controller handling by porting fixes from the i386 (PC) BSP Closes #4247 Closes #4248
219 lines
7.1 KiB
C
219 lines
7.1 KiB
C
/* irq.h
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*
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* This include file describe the data structure and the functions implemented
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* by RTEMS to write interrupt handlers.
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*
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* Copyright (C) 1999 valette@crf.canon.fr
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*
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* This code is heavilly inspired by the public specification of STREAM V2
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* that can be found at :
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*
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* <http://www.chorus.com/Documentation/index.html> by following
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* the STREAM API Specification Document link.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef BSP_POWERPC_IRQ_H
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#define BSP_POWERPC_IRQ_H
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#ifndef BSP_SHARED_HANDLER_SUPPORT
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#define BSP_SHARED_HANDLER_SUPPORT 1
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#endif
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#include <rtems/irq.h>
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/*
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* Switch to using the generic support. Remove this when all BSPs have
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* been converted.
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*/
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#define BSP_POWERPC_IRQ_GENERIC_SUPPORT 1
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/*
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* 8259 edge/level control definitions at VIA
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*/
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#define ISA8259_M_ELCR 0x4d0
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#define ISA8259_S_ELCR 0x4d1
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#define ELCRS_INT15_LVL 0x80
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#define ELCRS_INT14_LVL 0x40
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#define ELCRS_INT13_LVL 0x20
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#define ELCRS_INT12_LVL 0x10
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#define ELCRS_INT11_LVL 0x08
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#define ELCRS_INT10_LVL 0x04
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#define ELCRS_INT9_LVL 0x02
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#define ELCRS_INT8_LVL 0x01
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#define ELCRM_INT7_LVL 0x80
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#define ELCRM_INT6_LVL 0x40
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#define ELCRM_INT5_LVL 0x20
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#define ELCRM_INT4_LVL 0x10
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#define ELCRM_INT3_LVL 0x8
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#define ELCRM_INT2_LVL 0x4
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#define ELCRM_INT1_LVL 0x2
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#define ELCRM_INT0_LVL 0x1
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/* PIC's command and mask registers */
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#define PIC_MASTER_COMMAND_IO_PORT 0x20 /* Master PIC command register */
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#define PIC_SLAVE_COMMAND_IO_PORT 0xa0 /* Slave PIC command register */
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#define PIC_MASTER_IMR_IO_PORT 0x21 /* Master PIC Interrupt Mask Register */
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#define PIC_SLAVE_IMR_IO_PORT 0xa1 /* Slave PIC Interrupt Mask Register */
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/* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
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#define PIC_EOSI 0x60 /* End of Specific Interrupt (EOSI) */
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#define SLAVE_PIC_EOSI 0x62 /* End of Specific Interrupt (EOSI) for cascade */
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#define PIC_EOI 0x20 /* Generic End of Interrupt (EOI) */
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#ifndef ASM
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* rtems_irq_number Definitions
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*/
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/*
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* ISA IRQ handler related definitions
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*/
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#define BSP_ISA_IRQ_NUMBER (16)
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#define BSP_ISA_IRQ_LOWEST_OFFSET (0)
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#define BSP_ISA_IRQ_MAX_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
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/*
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* PCI IRQ handlers related definitions
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* CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
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*/
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#ifndef qemu
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#define BSP_PCI_IRQ_NUMBER (16)
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#else
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#define BSP_PCI_IRQ_NUMBER (0)
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#endif
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#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER)
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#define BSP_PCI_IRQ_MAX_OFFSET (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
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/*
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* PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
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* handler might be connected
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*/
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#define BSP_PROCESSOR_IRQ_NUMBER (1)
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#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
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#define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
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/* Misc vectors for OPENPIC irqs (IPI, timers)
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*/
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#ifndef qemu
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#define BSP_MISC_IRQ_NUMBER (8)
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#else
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#define BSP_MISC_IRQ_NUMBER (0)
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#endif
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#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
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#define BSP_MISC_IRQ_MAX_OFFSET (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
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/*
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* Summary
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*/
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#define BSP_IRQ_NUMBER (BSP_MISC_IRQ_MAX_OFFSET + 1)
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#define BSP_LOWEST_OFFSET (BSP_ISA_IRQ_LOWEST_OFFSET)
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#define BSP_MAX_OFFSET (BSP_MISC_IRQ_MAX_OFFSET)
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#define BSP_INTERRUPT_VECTOR_MIN (BSP_LOWEST_OFFSET)
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#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_OFFSET)
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/*
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* Some ISA IRQ symbolic name definition
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*/
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#define BSP_ISA_PERIODIC_TIMER (0)
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#define BSP_ISA_KEYBOARD (1)
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#define BSP_ISA_UART_COM2_IRQ (3)
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#define BSP_ISA_UART_COM1_IRQ (4)
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#define BSP_ISA_RT_TIMER1 (8)
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#define BSP_ISA_RT_TIMER3 (10)
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/*
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* Some PCI IRQ symbolic name definition
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*/
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#define BSP_PCI_IRQ0 (BSP_PCI_IRQ_LOWEST_OFFSET)
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#if BSP_PCI_IRQ_NUMBER > 0
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#define BSP_PCI_ISA_BRIDGE_IRQ (BSP_PCI_IRQ0)
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#endif
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#if defined(mvme2100)
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#define BSP_DEC21143_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
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#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
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#define BSP_PCMIP_TYPE1_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
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#define BSP_PCMIP_TYPE2_SLOT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
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#define BSP_PCMIP_TYPE2_SLOT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
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#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
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#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
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#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
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#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
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#define BSP_UART_COM1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
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#define BSP_FRONT_PANEL_ABORT_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
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#define BSP_RTC_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
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#else
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#define BSP_UART_COM1_IRQ BSP_ISA_UART_COM1_IRQ
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#define BSP_UART_COM2_IRQ BSP_ISA_UART_COM2_IRQ
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#endif
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/*
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* Some Processor execption handled as RTEMS IRQ symbolic name definition
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*/
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#define BSP_DECREMENTER (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
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/*
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* Type definition for RTEMS managed interrupts
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*/
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typedef unsigned short rtems_i8259_masks;
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extern volatile rtems_i8259_masks i8259s_cache;
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/*-------------------------------------------------------------------------+
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| Function Prototypes.
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+--------------------------------------------------------------------------*/
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/*
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* ------------------------ Intel 8259 (or emulation) Mngt Routines -------
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*/
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void BSP_i8259s_init(void);
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/*
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* function to disable a particular irq at 8259 level. After calling
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* this function, even if the device asserts the interrupt line it will
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* not be propagated further to the processor
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*
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* RETURNS: 1/0 if the interrupt was enabled/disabled originally or
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* a value < 0 on error.
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*/
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int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine);
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/*
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* function to enable a particular irq at 8259 level. After calling
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* this function, if the device asserts the interrupt line it will
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* be propagated further to the processor
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*/
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int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine);
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/*
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* function to acknowledge a particular irq at 8259 level. After calling
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* this function, if a device asserts an enabled interrupt line it will
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* be propagated further to the processor. Mainly usefull for people
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* writing raw handlers as this is automagically done for RTEMS managed
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* handlers.
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*/
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int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine);
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/*
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* function to check if a particular irq is enabled at 8259 level. After calling
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*/
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int BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine);
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unsigned short BSP_irq_suspend_i8259s(unsigned short mask);
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void BSP_irq_resume_i8259s(unsigned short in_progress_save);
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extern void BSP_rtems_irq_mng_init(unsigned cpuId);
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extern void BSP_i8259s_init(void);
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/* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
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#include <bsp/irq_supp.h>
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#ifdef __cplusplus
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};
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#endif
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#endif
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#endif
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