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0ef82c8cfe
PR 1385/cpukit * shared/irq/irq_asm.S: When the type rtems_boolean was switched to the C99 bool, the size changed from 4 bytes to 1 byte. The interrupt dispatching code accesses two boolean variables for scheduling purposes and the assembly implementations of this code did not get updated.
207 lines
6.9 KiB
ArmAsm
207 lines
6.9 KiB
ArmAsm
/* irq_asm.S
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*
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* This file contains the implementation of the IRQ handler
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*
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* Copyright (c) 2002 Advent Networks, Inc.
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* Jay Monkman <jmonkman@adventnetworks.com>
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*
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* CopyRight (C) 2000 Canon Research France SA.
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* Emmanuel Raguet, mailto:raguet@crf.canon.fr
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*
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* Modified Andy Dachs <a.dachs@sstl.co.uk>
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* Copyright (c) 2001 Surrey Satellite Technolgy Limited
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*
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* The license and distribution terms for this file may be
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* found in found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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#include <rtems/asm.h>
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#define __asm__
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/*MUST be ARM code*/
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/* assume that before interrupt we are in svc mode */
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/* fix me: No priority support, interrupt disabled too long in the ISR */
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.arm
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.globl _ISR_Handler
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_ISR_Handler:
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.code 32
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stmdb sp!, {r0, r1, r2, r3, r12} /* save regs on INT stack */
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stmdb sp!, {lr} /* now safe to call C funcs */
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/* one nest level deeper */
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ldr r0, =_ISR_Nest_level
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ldr r1, [r0]
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add r1, r1,#1
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str r1, [r0]
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/* disable multitasking */
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ldr r0, =_Thread_Dispatch_disable_level
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ldr r1, [r0]
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add r1, r1,#1
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str r1, [r0]
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/* BSP specific function to INT handler */
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/* FIXME: I'm not sure why I can't save just r12. I'm also */
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/* not sure which of r1-r3 are important. */
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#ifdef __thumb__
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ldr r0, =ExecuteITHandler +1
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mov lr, pc
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bx r0
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#else
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bl ExecuteITHandler
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#endif
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/* one less nest level */
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ldr r0, =_ISR_Nest_level
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ldr r1, [r0]
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sub r1, r1,#1
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str r1, [r0]
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/* unnest multitasking */
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ldr r0, =_Thread_Dispatch_disable_level
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ldr r1, [r0]
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sub r1, r1,#1
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str r1, [r0]
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/* check to see if we interrupted nd INT (with FIQ?) */
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mrs r0, spsr
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and r0, r0, #0x1f
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cmp r0, #0x12 /* is it INT mode? */
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beq exitit
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/* If thread dispatching is disabled, exit */
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cmp r1, #0
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bne exitit
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/* If a task switch is necessary, call scheduler */
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ldr r0, =_Context_Switch_necessary
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ldrb r1, [r0]
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cmp r1, #0
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/* since bframe is going to clear _ISR_Signals_to_thread_executing, */
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/* we need to load it here */
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ldr r0, =_ISR_Signals_to_thread_executing
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ldrb r1, [r0]
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bne bframe
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/* If a signals to be sent (_ISR_Signals_to_thread_executing != 0), */
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/* call scheduler */
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cmp r1, #0
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beq exitit
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/* _ISR_Signals_to_thread_executing = FALSE */
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mov r1, #0
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strb r1, [r0]
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bframe:
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/* Now we need to set up the return from this ISR to be _ISR_Dispatch */
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/* To do that, we need to save the current lr_int and spsr_int on the */
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/* SVC stack */
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mrs r0, spsr
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ldmia sp!, {r1} /* get lr off stack */
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stmdb sp!, {r1}
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mrs r2, cpsr
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orr r3, r2, #0x1 /* change to SVC mode */
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msr cpsr_c, r3
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/* now in SVC mode */
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stmdb sp!, {r0, r1} /* put spsr_int and lr_int on SVC stack */
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msr cpsr_c, r2 /* change back to INT mode */
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/* now in INT mode */
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/* replace lr with address of _ISR_Dispatch */
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ldr lr, =_ISR_Dispatch_p_4 /* On entry to an ISR, the lr is */
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/* the return address + 4, so */
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/* we have to emulate that */
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#ifdef __thumb__
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sub lr, #0x1
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#endif
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ldmia sp!, {r1} /* out with the old */
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stmdb sp!, {lr} /* in with the new (lr) */
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#ifndef __thumb__
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orr r0, r0, #0xc0
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msr spsr_cf, r0 /* mask interrupt */
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#endif
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exitit:
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ldmia sp!, {lr} /* restore regs from INT stack */
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ldmia sp!, {r0, r1, r2, r3, r12} /* restore regs from INT stack */
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subs pc, lr, #4 /* return */
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/* on entry to _ISR_Dispatch, we're in SVC mode */
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.globl _ISR_Dispatch
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_ISR_Dispatch:
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#ifdef __thumb__
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/* will be called from ISR, with SPSR in T mode */
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/* ISR will enter from here */
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.code 16
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.thumb_func
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push {r0-r3,lr} /* save regs on SVC stack */
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/* (now safe to call C funcs) */
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/* we don't save lr, since */
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/* it's just going to get */
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/* overwritten */
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nop /* made _ISR_Dispatch_p_4 4-word align */
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#else
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.code 32
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stmdb sp!, {r0-r3, r12,lr} /* save regs on SVC stack */
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/* (now safe to call C funcs) */
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/* we don't save lr, since */
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/* it's just going to get */
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/* overwritten */
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#endif
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_ISR_Dispatch_p_4:
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bl _Thread_Dispatch
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#ifdef __thumb__
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ldr r0, = .Thread_Disp_T
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bx r0
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.pool
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.code 32
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.Thread_Disp_T:
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#endif
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#ifdef __thumb__
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ldmia sp!, {r0-r3, lr} /*r12 not saved in thumb mode*/
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#else
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ldmia sp!, {r0-r3, r12, lr}
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#endif
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stmdb sp!, {r0-r2}
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/* Now we have to screw with the stack */
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mov r0, sp /* copy the SVC stack pointer */
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mrs r1, cpsr
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bic r2, r1, #0x1 /* change to INT mode */
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orr r2, r2, #0xc0 /* disable interrupts */
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msr cpsr_c, r2
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/* now in INT mode */
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stmdb sp!, {r4, r5, r6} /* save temp vars on INT stack */
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ldmia r0!, {r4, r5, r6} /* Get r0-r3 from SVC stack */
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stmdb sp!, {r4, r5, r6} /* and save them on INT stack */
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ldmia r0!, {r4, r5} /* get saved values from SVC stack */
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/* r4=spsr, r5=lr */
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mov lr, r5 /* restore lr_int */
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msr spsr, r4 /* restore spsr_int */
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/* switch to SVC mode, update sp, then return to INT mode */
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msr cpsr_c, r1 /* switch to SVC mode */
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mov sp, r0 /* update sp_svc */
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msr cpsr_c, r2 /* switch back to INT mode */
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/* pop all the registers from the stack */
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ldmia sp!, {r0, r1, r2}
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ldmia sp!, {r4, r5, r6}
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/* Finally, we can return to the interrupted task */
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subs pc, lr, #4
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