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147 lines
6.0 KiB
C
147 lines
6.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+-with-RTEMS-exception */
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/*
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* pgtable.h
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*
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* PowerPC memory management structures
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*
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* It is a stripped down version of linux ppc file...
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*
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* Copyright (C) 1999 Eric Valette (eric.valette@free.fr)
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* Canon Centre Recherche France.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef _LIBCPU_PGTABLE_H
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#define _LIBCPU_PGTABLE_H
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/*
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* The PowerPC MMU uses a hash table containing PTEs, together with
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* a set of 16 segment registers (on 32-bit implementations), to define
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* the virtual to physical address mapping.
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*
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* We use the hash table as an extended TLB, i.e. a cache of currently
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* active mappings. We maintain a two-level page table tree, much like
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* that used by the i386, for the sake of the Linux memory management code.
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* Low-level assembler code in head.S (procedure hash_page) is responsible
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* for extracting ptes from the tree and putting them into the hash table
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* when necessary, and updating the accessed and modified bits in the
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* page table tree.
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*
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* The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
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* We also use the two level tables, but we can put the real bits in them
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* needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
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* Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
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* additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
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* based upon user/super access. The TLB does not have accessed nor write
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* protect. We assume that if the TLB get loaded with an entry it is
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* accessed, and overload the changed bit for write protect. We use
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* two bits in the software pte that are supposed to be set to zero in
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* the TLB entry (24 and 25) for these indicators. Although the level 1
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* descriptor contains the guarded and writethrough/copyback bits, we can
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* set these at the page level since they get copied from the Mx_TWC
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* register when the TLB entry is loaded. We will use bit 27 for guard, since
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* that is where it exists in the MD_TWC, and bit 26 for writethrough.
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* These will get masked from the level 2 descriptor at TLB load time, and
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* copied to the MD_TWC before it gets loaded.
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*/
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/* PMD_SHIFT determines the size of the area mapped by the second-level page tables */
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#define PMD_SHIFT 22
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#define PGDIR_SHIFT 22
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* entries per page directory level: our page-table tree is two-level, so
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* we don't really have any PMD directory.
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*/
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#define PTRS_PER_PTE 1024
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#define PTRS_PER_PMD 1
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#define PTRS_PER_PGD 1024
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#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
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/* Just any arbitrary offset to the start of the vmalloc VM area: the
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* current 64MB value just means that there will be a 64MB "hole" after the
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* physical memory until the kernel virtual memory starts. That means that
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* any out-of-bounds memory accesses will hopefully be caught.
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* The vmalloc() routines leaves a hole of 4kB between each vmalloced
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* area for the same reason. ;)
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*
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* We no longer map larger than phys RAM with the BATs so we don't have
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* to worry about the VMALLOC_OFFSET causing problems. We do have to worry
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* about clashes between our early calls to ioremap() that start growing down
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* from ioremap_base being run into the VM area allocations (growing upwards
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* from VMALLOC_START). For this reason we have ioremap_bot to check when
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* we actually run into our mappings setup in the early boot with the VM
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* system. This really does become a problem for machines with good amounts
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* of RAM. -- Cort
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*/
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#define VMALLOC_OFFSET (0x4000000) /* 64M */
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#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
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#define VMALLOC_VMADDR(x) ((unsigned long)(x))
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#define VMALLOC_END ioremap_bot
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/*
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* Bits in a linux-style PTE. These match the bits in the
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* (hardware-defined) PowerPC PTE as closely as possible.
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*/
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#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
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#define _PAGE_USER 0x002 /* matches one of the PP bits */
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#define _PAGE_RW 0x004 /* software: user write access allowed */
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#define _PAGE_GUARDED 0x008
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#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
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#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
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#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
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#define _PAGE_DIRTY 0x080 /* C: page changed */
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#define _PAGE_ACCESSED 0x100 /* R: page referenced */
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#define _PAGE_HWWRITE 0x200 /* software: _PAGE_RW & _PAGE_DIRTY */
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#define _PAGE_SHARED 0
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#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
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#define _PAGE_BASE _PAGE_PRESENT | _PAGE_ACCESSED
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#define _PAGE_WRENABLE _PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE
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#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
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#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | \
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_PAGE_SHARED)
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#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
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#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
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#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED)
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#define PAGE_KERNEL_CI __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | \
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_PAGE_NO_CACHE )
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/*
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* The PowerPC can only do execute protection on a segment (256MB) basis,
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* not on a page basis. So we consider execute permission the same as read.
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* Also, write permissions imply read permissions.
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* This is the closest we can get..
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*/
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#define __P000 PAGE_NONE
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#define __P001 PAGE_READONLY
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#define __P010 PAGE_COPY
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#define __P011 PAGE_COPY
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#define __P100 PAGE_READONLY
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#define __P101 PAGE_READONLY
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#define __P110 PAGE_COPY
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#define __P111 PAGE_COPY
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#define __S000 PAGE_NONE
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#define __S001 PAGE_READONLY
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#define __S010 PAGE_SHARED
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#define __S011 PAGE_SHARED
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#define __S100 PAGE_READONLY
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#define __S101 PAGE_READONLY
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#define __S110 PAGE_SHARED
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#define __S111 PAGE_SHARED
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#endif /* _LIBCPU_PGTABLE_H */
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