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202 lines
7.1 KiB
C
202 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+-with-RTEMS-exception */
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/*
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* irq.h
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*
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* This include file describe the data structure and the functions implemented
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* by rtems to write interrupt handlers.
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*
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*
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* MPC5xx port sponsored by Defence Research and Development Canada - Suffield
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* Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
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*
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* Derived from libbsp/powerpc/mbx8xx/irq/irq.h:
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*
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* CopyRight (C) 1999 eric.valette@free.fr
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*
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* This code is heavilly inspired by the public specification of STREAM V2
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* that can be found at :
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*
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* <http://www.chorus.com/Documentation/index.html> by following
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* the STREAM API Specification Document link.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef _LIBCPU_IRQ_H
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#define _LIBCPU_IRQ_H
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#include <rtems/irq.h>
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#define CPU_ASM_IRQ_VECTOR_BASE 0x0
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#ifndef ASM
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extern volatile unsigned int ppc_cached_irq_mask;
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/*
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* Symblolic IRQ names and related definitions.
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*/
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/*
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* Base vector for our USIU IRQ handlers.
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*/
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#define CPU_USIU_VECTOR_BASE (CPU_ASM_IRQ_VECTOR_BASE)
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/*
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* USIU IRQ handler related definitions
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*/
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#define CPU_USIU_IRQ_COUNT (16) /* 16 reserved but in the future... */
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#define CPU_USIU_IRQ_MIN_OFFSET (0)
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#define CPU_USIU_IRQ_MAX_OFFSET (CPU_USIU_IRQ_MIN_OFFSET + CPU_USIU_IRQ_COUNT - 1)
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/*
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* UIMB IRQ handlers related definitions
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*/
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#define CPU_UIMB_IRQ_COUNT (32 - 8) /* first 8 overlap USIU */
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#define CPU_UIMB_IRQ_MIN_OFFSET (CPU_USIU_IRQ_COUNT + CPU_USIU_VECTOR_BASE)
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#define CPU_UIMB_IRQ_MAX_OFFSET (CPU_UIMB_IRQ_MIN_OFFSET + CPU_UIMB_IRQ_COUNT - 1)
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/*
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* PowerPc exceptions handled as interrupt where a rtems managed interrupt
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* handler might be connected
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*/
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#define CPU_PROC_IRQ_COUNT (1)
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#define CPU_PROC_IRQ_MIN_OFFSET (CPU_UIMB_IRQ_MAX_OFFSET + 1)
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#define CPU_PROC_IRQ_MAX_OFFSET (CPU_PROC_IRQ_MIN_OFFSET + CPU_PROC_IRQ_COUNT - 1)
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/*
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* Summary
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*/
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#define CPU_IRQ_COUNT (CPU_PROC_IRQ_MAX_OFFSET + 1)
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#define CPU_MIN_OFFSET (CPU_USIU_IRQ_MIN_OFFSET)
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#define CPU_MAX_OFFSET (CPU_PROC_IRQ_MAX_OFFSET)
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/*
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* USIU IRQ symbolic name definitions.
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*/
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#define CPU_USIU_EXT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 0)
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#define CPU_USIU_INT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 1)
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#define CPU_USIU_EXT_IRQ_1 (CPU_USIU_IRQ_MIN_OFFSET + 2)
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#define CPU_USIU_INT_IRQ_1 (CPU_USIU_IRQ_MIN_OFFSET + 3)
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#define CPU_USIU_EXT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 4)
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#define CPU_USIU_INT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 5)
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#define CPU_USIU_EXT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 6)
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#define CPU_USIU_INT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 7)
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#define CPU_USIU_EXT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 8)
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#define CPU_USIU_INT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 9)
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#define CPU_USIU_EXT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 10)
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#define CPU_USIU_INT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 11)
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#define CPU_USIU_EXT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 12)
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#define CPU_USIU_INT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 13)
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#define CPU_USIU_EXT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 14)
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#define CPU_USIU_INT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 15)
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/*
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* Symbolic names for UISU interrupt sources.
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*/
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#define CPU_PERIODIC_TIMER (CPU_USIU_INT_IRQ_6)
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#define CPU_UIMB_INTERRUPT (CPU_USIU_INT_IRQ_7)
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/*
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* UIMB IRQ symbolic name definitions. The first 8 sources are aliases to
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* the USIU interrupts of the same number, because they are detected in
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* the USIU pending register rather than the UIMB pending register.
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*/
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#define CPU_UIMB_IRQ_0 (CPU_USIU_INT_IRQ_0)
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#define CPU_UIMB_IRQ_1 (CPU_USIU_INT_IRQ_1)
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#define CPU_UIMB_IRQ_2 (CPU_USIU_INT_IRQ_2)
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#define CPU_UIMB_IRQ_3 (CPU_USIU_INT_IRQ_3)
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#define CPU_UIMB_IRQ_4 (CPU_USIU_INT_IRQ_4)
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#define CPU_UIMB_IRQ_5 (CPU_USIU_INT_IRQ_5)
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#define CPU_UIMB_IRQ_6 (CPU_USIU_INT_IRQ_6)
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#define CPU_UIMB_IRQ_7 (CPU_USIU_INT_IRQ_7)
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#define CPU_UIMB_IRQ_8 (CPU_UIMB_IRQ_MIN_OFFSET+ 0)
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#define CPU_UIMB_IRQ_9 (CPU_UIMB_IRQ_MIN_OFFSET+ 1)
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#define CPU_UIMB_IRQ_10 (CPU_UIMB_IRQ_MIN_OFFSET+ 2)
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#define CPU_UIMB_IRQ_11 (CPU_UIMB_IRQ_MIN_OFFSET+ 3)
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#define CPU_UIMB_IRQ_12 (CPU_UIMB_IRQ_MIN_OFFSET+ 4)
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#define CPU_UIMB_IRQ_13 (CPU_UIMB_IRQ_MIN_OFFSET+ 5)
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#define CPU_UIMB_IRQ_14 (CPU_UIMB_IRQ_MIN_OFFSET+ 6)
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#define CPU_UIMB_IRQ_15 (CPU_UIMB_IRQ_MIN_OFFSET+ 7)
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#define CPU_UIMB_IRQ_16 (CPU_UIMB_IRQ_MIN_OFFSET+ 8)
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#define CPU_UIMB_IRQ_17 (CPU_UIMB_IRQ_MIN_OFFSET+ 9)
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#define CPU_UIMB_IRQ_18 (CPU_UIMB_IRQ_MIN_OFFSET+ 0)
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#define CPU_UIMB_IRQ_19 (CPU_UIMB_IRQ_MIN_OFFSET+11)
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#define CPU_UIMB_IRQ_20 (CPU_UIMB_IRQ_MIN_OFFSET+12)
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#define CPU_UIMB_IRQ_21 (CPU_UIMB_IRQ_MIN_OFFSET+13)
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#define CPU_UIMB_IRQ_22 (CPU_UIMB_IRQ_MIN_OFFSET+14)
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#define CPU_UIMB_IRQ_23 (CPU_UIMB_IRQ_MIN_OFFSET+15)
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#define CPU_UIMB_IRQ_24 (CPU_UIMB_IRQ_MIN_OFFSET+16)
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#define CPU_UIMB_IRQ_25 (CPU_UIMB_IRQ_MIN_OFFSET+17)
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#define CPU_UIMB_IRQ_26 (CPU_UIMB_IRQ_MIN_OFFSET+18)
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#define CPU_UIMB_IRQ_27 (CPU_UIMB_IRQ_MIN_OFFSET+19)
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#define CPU_UIMB_IRQ_28 (CPU_UIMB_IRQ_MIN_OFFSET+20)
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#define CPU_UIMB_IRQ_29 (CPU_UIMB_IRQ_MIN_OFFSET+21)
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#define CPU_UIMB_IRQ_30 (CPU_UIMB_IRQ_MIN_OFFSET+22)
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#define CPU_UIMB_IRQ_31 (CPU_UIMB_IRQ_MIN_OFFSET+23)
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/*
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* Symbolic names for UIMB interrupt sources.
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*/
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#define CPU_IRQ_SCI (CPU_UIMB_IRQ_5)
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/*
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* Processor exceptions handled as rtems IRQ symbolic name definitions.
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*/
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#define CPU_DECREMENTER (CPU_PROC_IRQ_MIN_OFFSET)
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/*
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* Convert an rtems_irq_number constant to an interrupt level
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* suitable for programming into an I/O device's interrupt level field.
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*/
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int CPU_irq_level_from_symbolic_name(const rtems_irq_number name);
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/*-------------------------------------------------------------------------+
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| Function Prototypes.
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+--------------------------------------------------------------------------*/
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extern void CPU_rtems_irq_mng_init(unsigned cpuId);
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typedef struct MPC5XX_Interrupt_frame {
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uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */
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uint32_t calleeLr; /* link register used by callees: SVR4/EABI */
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/* This is what is left out of the primary contexts */
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uint32_t gpr0;
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uint32_t gpr2; /* play safe */
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uint32_t gpr3;
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uint32_t gpr4;
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uint32_t gpr5;
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uint32_t gpr6;
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uint32_t gpr7;
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uint32_t gpr8;
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uint32_t gpr9;
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uint32_t gpr10;
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uint32_t gpr11;
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uint32_t gpr12;
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uint32_t gpr13; /* Play safe */
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uint32_t gpr28; /* For internal use by the IRQ handler */
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uint32_t gpr29; /* For internal use by the IRQ handler */
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uint32_t gpr30; /* For internal use by the IRQ handler */
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uint32_t gpr31; /* For internal use by the IRQ handler */
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uint32_t cr; /* Bits of this are volatile, so no-one may save */
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uint32_t ctr;
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uint32_t xer;
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uint32_t lr;
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uint32_t pc;
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uint32_t msr;
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uint32_t pad[3];
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} MPC5XX_Interrupt_frame;
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void C_dispatch_irq_handler(MPC5XX_Interrupt_frame *frame, unsigned int excNum);
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#endif
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#endif
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