This adds a backend for flashdev that simulates a flash device with
adjustable delays to simulate real flash devices and offers
configurable flash parameters. This also migrates the JFFS2
filesystem tests to the flashdev framework and eliminates the
purpose-built simulated flash in the testsuite in favor of a more
generic and widely usable solution.
Closes#5403
Return the actual out of bounds size per page instead of the ioctl
return status. JFFS2 will happily operate with an OOB size of 0 and
instead put cleanmarkers in the normal page space of the flash.
Closes#5379
Previously this RTC was using the file system-based i2c interface in
/dev. Since the RTC is initialized pretty early on during system init,
we call open() before stdin/stdout/stderr have been opened. RTEMS
assumes that stdin == 0, stdout == 1, etc., and fails when that isn't
the case. In particular, when stdin != 0, RTEMS assumes that it wasn't
configured with a console driver and skips opening stdout/stderr,
leading to confusing issues with the standard I/O streams.
Closes#5284
The maximum size of JFFS2 is 4GB minus the block size of the flash.
Enforce this limitation when setting up a filesystem on a flashdev
region that is larger than the maximum.
This also resolves some off-nominal memory leaks.
Closes#5347
This adds an API call allowing for unregistration to include destruction
of private data that is not managed by the flashdev framework. This also
updates the existing consumers of flashdev to use the new private data
destructor callback.
Closes#5346
This adds generic JFFS2 interworking code that allows JFFS2 to be used
on top of any flashdev backend. It currently only supports NOR flashdev
backends.
The two RTCs supported by that driver (MCP7940M and EOZ9) use slightly
different register order. Add support for a different order to the
i2c-rtc driver.
This removes the headers imported from the embeddedsw repository in
favor of a much thinner shim. This also removes the complicated build
system configuration necessary to support use of these headers. The
primary reason for removal is that certain external Xilinx libraries
also require use of these headers and this causes version mismatches and
header conflicts that can be avoided.
There is no need to wait on secondary processors for the GIC distributor
enable since the BSPs for real targets start the secondary processors
in _CPU_SMP_Start_processor().
Rename xilinx_zynqmp_rpu BSP variant to zynqmp_rpu_lock_step to
emphasize that this BSP is for the lock-step mode RPU configuration.
Add BSP variants zynqmp_rpu_split_0 and zynqmp_rpu_split_1 for the split
mode RPU configuration for core 0 and 1 respectively.
Add support for the BSP_ARM_GIC_MULTI_PROCESSOR_SECONDARY build option
for the GICv2 support. This option is useful for multiprocessor systems
without SMP support.
- Refactor the pl011 driver to be extensible.
- Add IRQ support and baudrate configuration support for pl011 driver.
- Modify related BSP.
- Add doxygen comments for arm-pl011.
Close#5026
Co-authored-by: Ning Yang <yangn0@qq.com>
It is not clear why this is necessary. For example, the
zynq_uart_initialize() does not issue the '\r' before waiting for an
inactive transmission state.
Similar to the recent commit in tms570-sci.c, the assumption that a UART will
only see printable ASCII characters, instead of any value in the range
0x00-0xFF, is wrong.
A non forgiving binary protocol will be thrown off by this driver sending
"\r\r\r\r" when initializing.
If a user wants to flush the interface, they should explicitely use the
dedicated function `tcflush(fd, TCIOFLUSH);`.
Add BSP option BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 to customize the ARM
GIC support. Enable this option for arm/altera-cyclone-v and
arm/xilinx-zynq BSPs by default.
The EOZ9 RTC has a similar register interface like the MCP7940M (and
quite some other I2C RTCs). This commit:
* Extracts the generic parts from MCP7940M and moves it into a generic
i2c-rtc driver.
* Uses the new i2c-rtc for the MCP7940M.
* Uses the new i2c-rtc for the new Abracom EOZ9.
This switches the XQspiPsu NOR driver layer to use the RTEMS event
system so that waits for interrupt-based data transfers can time out
instead of waiting indefinitely. It is sometimes possible for either the
controller or the NOR chip to fail to issue a transfer completion event
and recovery is preferable to a hang.
Add directives to get and set the priority of an interrupt vector.
Implement the directives for the following BSP families:
* arm/lpc24xx
* arm/lpc32xx
* powerpc/mpc55xxevb
* powerpc/qoriq
Implement the directives for the following interrupt controllers:
* GICv2 and GICv3 (arm and aarch64)
* NVIC (arm)
* PLIC (riscv)
Update #5002.
In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.
Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.
