doc: Add SMP section to CPU Arch Supplement

doc/cpu_supplement/arm.t

@@ -172,6 +172,11 @@ following actions:
 @item executes an infinite loop to simulate a halt processor instruction.
 @end itemize
 
+@section Symmetric Multiprocessing
+
+SMP is supported on ARMv7-A.  Available platforms are the Altera Cyclone V and
+the Xilinx Zynq.
+
 @section Thread-Local Storage
 
 Thread-local storage is supported.

doc/cpu_supplement/avr.t

@@ -117,6 +117,10 @@ actions:
 simulate a halt processor instruction.
 @end itemize
 
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
 @section Thread-Local Storage
 
 Thread-local storage is not supported due to a broken tool chain.

doc/cpu_supplement/bfin.t

@@ -130,6 +130,10 @@ actions:
 simulate a halt processor instruction.
 @end itemize
 
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
 @section Thread-Local Storage
 
 Thread-local storage is not implemented.

doc/cpu_supplement/epiphany.t

@@ -73,3 +73,7 @@ following actions:
 @item places the error code in @code{r0}, and
 @item executes an infinite loop to simulate a halt processor instruction.
 @end itemize
+
+@section Symmetric Multiprocessing
+
+SMP is not supported.

doc/cpu_supplement/general.t

@@ -344,6 +344,11 @@ interrupts and halts the processor.
 In each of the architecture specific chapters, this describes the precise
 operations of the default CPU specific fatal error handler.
 
+@section Symmetric Multiprocessing
+
+This section contains information about the Symmetric Multiprocessing (SMP)
+status of a particular architecture.
+
 @section Thread-Local Storage
 
 In order to support thread-local storage (TLS) the CPU port must implement the

doc/cpu_supplement/h8300.t

@@ -2,6 +2,10 @@
 
 @chapter Renesas H8/300 Specific Information
 
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
 @section Thread-Local Storage
 
 Thread-local storage is not implemented.

doc/cpu_supplement/i386.t

@@ -266,6 +266,10 @@ The default fatal error handler for this architecture disables processor
 interrupts, places the error code in EAX, and executes a HLT instruction
 to halt the processor.
 
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
 @section Thread-Local Storage
 
 Thread-local storage is not implemented.

doc/cpu_supplement/lm32.t

@@ -163,6 +163,10 @@ interrupts and halts the processor.
 In each of the architecture specific chapters, this describes the precise
 operations of the default CPU specific fatal error handler.
 
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
 @section Thread-Local Storage
 
 Thread-local storage is not implemented.

doc/cpu_supplement/m32c.t

@@ -2,6 +2,10 @@
 
 @chapter Renesas M32C Specific Information
 
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
 @section Thread-Local Storage
 
 Thread-local storage is not implemented.

doc/cpu_supplement/m32r.t

@@ -2,6 +2,10 @@
 
 @chapter Renesas M32R Specific Information
 
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
 @section Thread-Local Storage
 
 Thread-local storage is not implemented.

doc/cpu_supplement/m68k.t

@@ -357,6 +357,10 @@ The default fatal error handler for this architecture disables processor
 interrupts to level 7, places the error code in D0, and executes a
 @code{stop} instruction to simulate a halt processor instruction.
 
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
 @section Thread-Local Storage
 
 Thread-local storage is supported.

doc/cpu_supplement/microblaze.t

@@ -2,6 +2,10 @@
 
 @chapter Xilinx MicroBlaze Specific Information
 
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
 @section Thread-Local Storage
 
 Thread-local storage is not implemented.

doc/cpu_supplement/mips.t

@@ -122,6 +122,10 @@ The default fatal error handler for this target architecture disables
 processor interrupts, places the error code in @b{XXX}, and executes a
 @code{XXX} instruction to simulate a halt processor instruction.
 
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
 @section Thread-Local Storage
 
 Thread-local storage is not implemented.

doc/cpu_supplement/nios2.t

@@ -2,6 +2,10 @@
 
 @chapter Altera Nios II Specific Information
 
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
 @section Thread-Local Storage
 
 Thread-local storage is not implemented.

doc/cpu_supplement/or1k.t

@@ -74,3 +74,7 @@ following actions:
 @item places the error code in @code{r0}, and
 @item executes an infinite loop to simulate a halt processor instruction.
 @end itemize
+
+@section Symmetric Multiprocessing
+
+SMP is not supported.

doc/cpu_supplement/powerpc.t

@@ -657,6 +657,11 @@ If the Program Exception returns, then the following actions are performed:
 
 @end itemize
 
+@section Symmetric Multiprocessing
+
+SMP is supported.  Available platforms are the Freescale QorIQ P series (e.g.
+P1020) and T series (e.g. T2080, T4240).
+
 @section Thread-Local Storage
 
 Thread-local storage is supported.

doc/cpu_supplement/sh.t

@@ -139,6 +139,10 @@ The default fatal error handler for this architecture disables processor
 interrupts, places the error code in @b{XXX}, and executes a @code{XXX}
 instruction to simulate a halt processor instruction.
 
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
 @section Thread-Local Storage
 
 Thread-local storage is not implemented.

doc/cpu_supplement/sparc.t

@@ -969,6 +969,11 @@ error source in register @code{g2}, and the error code in register
 @code{g3}. It will then generate a system error which will
 hand over control to the debugger, simulator, etc.
 
+@section Symmetric Multiprocessing
+
+SMP is supported.  Available platforms are the Cobham Gaisler GR712RC and
+GR740.
+
 @section Thread-Local Storage
 
 Thread-local storage is supported.

doc/cpu_supplement/sparc64.t

@@ -773,6 +773,10 @@ default fatal error handler disables processor interrupts to
 level 15, places the error code in g1, and goes into an infinite
 loop to simulate a halt processor instruction.
 
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
 @section Thread-Local Storage
 
 Thread-local storage is supported.

doc/cpu_supplement/v850.t

@@ -103,6 +103,10 @@ following actions:
 @item executes a halt processor instruction.
 @end itemize
 
+@section Symmetric Multiprocessing
+
+SMP is not supported.
+
 @section Thread-Local Storage
 
 Thread-local storage is not implemented.