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2003-02-20 Till Straumann <strauman@slac.stanford.edu>

Browse Source 
PR 349/bsps
	* console/polled_io.c, console/reboot.c, irq/irq.c, irq/irq_asm.S,
	irq/irq_init.c, openpic/Makefile.am, startup/linkcmds,
	vectors/vectors.S, vectors/vectors_init.c:
	  - install the 'openpic.h' and 'pci.h' headers
	  - avoid a name clash by renaming 'vsprintf' & friends
	    to 'k_vsprintf' etc.
	  - let 'rtemsReboot' print a stack trace (in case an 'assert' failed)
	  - irq.c:
	     * fix: remove implicit assumption that ISA interrupt vectors start
	            at 0
	     * add BSP hook to let a VME interrupt acknowledge the PCI/openpic
	       IRQ. (SEE ALSO THE ppc-sharedbsp-vme.diff patch)
	  - fix: EABI compliance; isr/exception lowlevel handlers must not
	         clobber R2 or R13
	  - fix: openpic_init was called with the polarity/senses tables
	         swapped (fixed wrong order of arguments)
	  - cosmetics: use new _read_SPRXX() _write_SPRXX() macros
This commit is contained in:
Joel Sherrill
2003-02-20 21:48:25 +00:00
parent 837a1323e3
commit e7625fc6c9
8 changed files with 96 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
c/src/lib/libbsp/powerpc/shared/ChangeLog
View File

@@ -1,3 +1,24 @@
2003-02-20 Till Straumann <strauman@slac.stanford.edu>
PR 349/bsps
* console/polled_io.c, console/reboot.c, irq/irq.c, irq/irq_asm.S,
irq/irq_init.c, openpic/Makefile.am, startup/linkcmds,
vectors/vectors.S, vectors/vectors_init.c:
- install the 'openpic.h' and 'pci.h' headers
- avoid a name clash by renaming 'vsprintf' & friends
to 'k_vsprintf' etc.
- let 'rtemsReboot' print a stack trace (in case an 'assert' failed)
- irq.c:
* fix: remove implicit assumption that ISA interrupt vectors start
at 0
* add BSP hook to let a VME interrupt acknowledge the PCI/openpic
IRQ. (SEE ALSO THE ppc-sharedbsp-vme.diff patch)
- fix: EABI compliance; isr/exception lowlevel handlers must not
clobber R2 or R13
- fix: openpic_init was called with the polarity/senses tables
swapped (fixed wrong order of arguments)
- cosmetics: use new _read_SPRXX() _write_SPRXX() macros
2003-02-20 Till Straumann <strauman@slac.stanford.edu>
PR 349/bsps

2
c/src/lib/libbsp/powerpc/shared/Makefile.am
View File

@@ -5,7 +5,7 @@
if need_shared
SUBDIRS = clock console include pci residual openpic irq vectors start \
startup motorola bootloader
startup motorola bootloader vme
endif
include $(top_srcdir)/../../../../../automake/subdirs.am

15
c/src/lib/libbsp/powerpc/shared/irq/irq.c
View File

@@ -14,6 +14,7 @@
#include <rtems/system.h>
#include <bsp.h>
#include <bsp/irq.h>
#include <bsp/VME.h>
#include <bsp/openpic.h>
#include <rtems/score/thread.h>
#include <rtems/score/apiext.h>
@@ -86,14 +87,14 @@ static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
*/
static void compute_i8259_masks_from_prio ()
{
unsigned int i;
unsigned int j;
int i;
int j;
/*
* Always mask at least current interrupt to prevent re-entrance
*/
for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_NUMBER; i++) {
for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
* ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_NUMBER; j++) {
for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) {
/*
* Mask interrupts at i8259 level that have a lower priority
*/
@@ -261,7 +262,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
*/
compute_i8259_masks_from_prio ();
for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_NUMBER; i++) {
for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
BSP_irq_enable_at_i8259s (i);
rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
@@ -375,8 +376,8 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
}
else {
#ifdef BSP_PCI_VME_BRIDGE_DOES_EOI
/* leave it to the VME bridge to do EOI, so
#ifdef BSP_PCI_VME_DRIVER_DOES_EOI
/* leave it to the VME bridge driver to do EOI, so
* it can re-enable the openpic while handling
* VME interrupts (-> VME priorities in software)
*/

40
c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
View File

@@ -73,15 +73,19 @@ SYM (shared_raw_irq_code_entry):
* to reenable exception processing
*/
stw r0, GPR0_OFFSET(r1)
/* PPC EABI: R2 is reserved (pointer to short data .sdata2) - we won't touch it
* but we still save/restore it, just in case...
*/
stw r2, GPR2_OFFSET(r1)
stw r3, GPR3_OFFSET(r1)
mfsrr0 r0
mfsrr1 r2
mfmsr r3
mfsrr1 r3
stw r0, SRR0_FRAME_OFFSET(r1)
stw r2, SRR1_FRAME_OFFSET(r1)
stw r3, SRR1_FRAME_OFFSET(r1)
mfmsr r3
/*
* Enable data and instruction address translation, exception recovery
*
@@ -137,21 +141,21 @@ SYM (shared_raw_irq_code_entry):
*/
addis r15,0, _Thread_Dispatch_disable_level@ha
/*
* Get current nesting level in R2
* Get current nesting level in R3
*/
mfspr r2, SPRG0
mfspr r3, SPRG0
/*
* Check if stack switch is necessary
*/
cmpwi r2,0
cmpwi r3,0
bne nested
mfspr r1, SPRG1
nested:
/*
* Start Incrementing nesting level in R2
* Start Incrementing nesting level in R3
*/
addi r2,r2,1
addi r3,r3,1
/*
* Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level
*/
@@ -159,7 +163,7 @@ nested:
/*
* store new nesting level in SPRG0
*/
mtspr SPRG0, r2
mtspr SPRG0, r3
addi r6, r6, 1
mfmsr r5
@@ -183,14 +187,14 @@ nested:
* value as an easy exit condition because if interrupt nesting level > 1
* then _Thread_Dispatch_disable_level > 1
*/
mfspr r2, SPRG0
mfspr r4, SPRG0
/*
* start decrementing _Thread_Dispatch_disable_level
*/
lwz r3,_Thread_Dispatch_disable_level@l(r15)
addi r2, r2, -1 /* Continue decrementing nesting level */
addi r4, r4, -1 /* Continue decrementing nesting level */
addi r3, r3, -1 /* Continue decrementing _Thread_Dispatch_disable_level */
mtspr SPRG0, r2 /* End decrementing nesting level */
mtspr SPRG0, r4 /* End decrementing nesting level */
stw r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
cmpwi r3, 0
/*
@@ -225,11 +229,11 @@ nested:
/*
* compute SP at exception entry
*/
addi r2, r1, EXCEPTION_FRAME_END
addi r4, r1, EXCEPTION_FRAME_END
/*
* store it at the right place
*/
stw r2, GPR1_OFFSET(r1)
stw r4, GPR1_OFFSET(r1)
/*
* Call High Level signal handling code
*/
@@ -314,14 +318,14 @@ easy_exit:
*/
lwz r4, SRR1_FRAME_OFFSET(r1)
lwz r2, SRR0_FRAME_OFFSET(r1)
lwz r3, GPR3_OFFSET(r1)
lwz r3, SRR0_FRAME_OFFSET(r1)
lwz r2, GPR2_OFFSET(r1)
lwz r0, GPR0_OFFSET(r1)
mtsrr1 r4
mtsrr0 r2
mtsrr0 r3
lwz r4, GPR4_OFFSET(r1)
lwz r2, GPR2_OFFSET(r1)
lwz r3, GPR3_OFFSET(r1)
addi r1,r1, EXCEPTION_FRAME_END
SYNC
rfi

2
c/src/lib/libbsp/powerpc/shared/irq/irq_init.c
View File

@@ -237,7 +237,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
#ifdef TRACE_IRQ_INIT
printk("Going to initialize raven interrupt controller (openpic compliant)\n");
#endif
openpic_init(1, mcp750_openpic_initsenses, mcp750_openpic_initpolarities);
openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses);
#ifdef TRACE_IRQ_INIT
printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
#endif

3
c/src/lib/libbsp/powerpc/shared/openpic/Makefile.am
View File

@@ -5,8 +5,7 @@
C_FILES = openpic.c
include_bspdir = $(includedir)/bsp
include_bsp_HEADERS = openpic.h
H_FILES = openpic.h
$(PROJECT_INCLUDE)/bsp:
$(mkinstalldirs) $@

15
c/src/lib/libbsp/powerpc/shared/vectors/vectors.S
View File

@@ -40,9 +40,12 @@ SYM (default_exception_vector_code_prolog):
*/
stwu r1, - (EXCEPTION_FRAME_END)(r1)
stw r3, GPR3_OFFSET(r1)
/* R2 should never change (EABI: pointer to .sdata2) - we
* save it nevertheless..
*/
stw r2, GPR2_OFFSET(r1)
mflr r2
stw r2, EXC_LR_OFFSET(r1)
mflr r3
stw r3, EXC_LR_OFFSET(r1)
bl 0f
0: /*
* r3 = exception vector entry point
@@ -64,8 +67,8 @@ PUBLIC_VAR (push_normalized_frame)
SYM (push_normalized_frame):
stw r3, EXCEPTION_NUMBER_OFFSET(r1)
stw r0, GPR0_OFFSET(r1)
mfsrr0 r2
stw r2, SRR0_FRAME_OFFSET(r1)
mfsrr0 r3
stw r3, SRR0_FRAME_OFFSET(r1)
mfsrr1 r3
stw r3, SRR1_FRAME_OFFSET(r1)
/*
@@ -92,11 +95,11 @@ SYM (push_normalized_frame):
/*
* compute SP at exception entry
*/
addi r2, r1, EXCEPTION_FRAME_END
addi r3, r1, EXCEPTION_FRAME_END
/*
* store it at the right place
*/
stw r2, GPR1_OFFSET(r1)
stw r3, GPR1_OFFSET(r1)
/*
* Enable data and instruction address translation, exception nesting
*/

21
c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c
View File

@@ -16,6 +16,7 @@
#include <bsp/vectors.h>
#include <libcpu/raw_exception.h>
#include <libcpu/spr.h>
#include <bsp.h>
static rtems_raw_except_global_settings exception_config;
@@ -33,16 +34,28 @@ typedef struct LRFrameRec_ {
#define STACK_CLAMP 50 /* in case we have a corrupted bottom */
SPR_RO(LR)
void
BSP_printStackTrace(BSP_Exception_frame* excPtr)
{
LRFrame f;
int i;
LRFrame sp;
void *lr;
printk("Stack Trace: ");
printk(" IP: 0x%08x, LR: 0x%08x\n",
excPtr->EXC_SRR0, excPtr->EXC_LR);
for (f=(LRFrame)excPtr->GPR1, i=0; f->frameLink && i<STACK_CLAMP; f=f->frameLink) {
printk("Stack Trace: \n ");
if (excPtr) {
printk("IP: 0x%08x, ",excPtr->EXC_SRR0);
sp=(LRFrame)excPtr->GPR1;
lr=(void*)excPtr->EXC_LR;
} else {
/* there's no macro for this */
__asm__ __volatile__("mr %0, 1":"=r"(sp));
lr=(LRFrame)_read_LR();
}
printk("LR: 0x%08x\n",lr);
for (f=(LRFrame)sp, i=0; f->frameLink && i<STACK_CLAMP; f=f->frameLink) {
printk("--^ 0x%08x", (long)(f->frameLink->lr));
if (!(++i%5))
printk("\n");