Imagelibrary/rtems
1
0
Fork 1
mirror of https://gitlab.rtems.org/rtems/rtos/rtems.git synced 2025-12-05 23:23:13 +00:00
Code Issues Packages Projects Releases Wiki Activity

Added comments and corrected spacing.

Browse Source
This commit is contained in:
Joel Sherrill
1998-06-22 09:59:22 +00:00
parent aa0da6b2c2
commit e4acf68ace
6 changed files with 426 additions and 394 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
c/src/lib/libchip/serial/z85c30.c
View File

@@ -1,6 +1,11 @@
/* /*
* This file contains the console driver chip level routines for the * This file contains the console driver chip level routines for the
* z85c30 chip. * Zilog z85c30 chip.
*
* The Zilog Z8530 is also available as:
*
* + Intel 82530
* + AMD ???
* *
* COPYRIGHT (c) 1998 by Radstone Technology * COPYRIGHT (c) 1998 by Radstone Technology
* *
@@ -36,6 +41,7 @@
/* /*
* Flow control is only supported when using interrupts * Flow control is only supported when using interrupts
*/ */
console_flow z85c30_flow_RTSCTS = console_flow z85c30_flow_RTSCTS =
{ {
z85c30_negate_RTS, /* deviceStopRemoteTx */ z85c30_negate_RTS, /* deviceStopRemoteTx */
@@ -51,6 +57,7 @@ console_flow z85c30_flow_DTRCTS =
/* /*
* Exported driver function table * Exported driver function table
*/ */
console_fns z85c30_fns = console_fns z85c30_fns =
{ {
z85c30_probe, /* deviceProbe */ z85c30_probe, /* deviceProbe */
@@ -346,9 +353,11 @@ static void z85c30_init(int minor)
/* /*
* These routines provide control of the RTS and DTR lines * These routines provide control of the RTS and DTR lines
*/ */
/* /*
* z85c30_assert_RTS * z85c30_assert_RTS
*/ */
static int z85c30_assert_RTS(int minor) static int z85c30_assert_RTS(int minor)
{ {
rtems_interrupt_level Irql; rtems_interrupt_level Irql;
@@ -377,6 +386,7 @@ static int z85c30_assert_RTS(int minor)
/* /*
* z85c30_negate_RTS * z85c30_negate_RTS
*/ */
static int z85c30_negate_RTS(int minor) static int z85c30_negate_RTS(int minor)
{ {
rtems_interrupt_level Irql; rtems_interrupt_level Irql;
@@ -406,9 +416,11 @@ static int z85c30_negate_RTS(int minor)
* These flow control routines utilise a connection from the local DTR * These flow control routines utilise a connection from the local DTR
* line to the remote CTS line * line to the remote CTS line
*/ */
/* /*
* z85c30_assert_DTR * z85c30_assert_DTR
*/ */
static int z85c30_assert_DTR(int minor) static int z85c30_assert_DTR(int minor)
{ {
rtems_interrupt_level Irql; rtems_interrupt_level Irql;
@@ -437,6 +449,7 @@ static int z85c30_assert_DTR(int minor)
/* /*
* z85c30_negate_DTR * z85c30_negate_DTR
*/ */
static int z85c30_negate_DTR(int minor) static int z85c30_negate_DTR(int minor)
{ {
rtems_interrupt_level Irql; rtems_interrupt_level Irql;
@@ -712,6 +725,7 @@ static void z85c30_initialize_interrupts(
* Console Termios output entry point. * Console Termios output entry point.
* *
*/ */
static int z85c30_write_support_int( static int z85c30_write_support_int(
int minor, int minor,
const char *buf, const char *buf,
@@ -774,6 +788,7 @@ static int z85c30_write_support_int(
* *
* This routine polls for a character. * This routine polls for a character.
*/ */
static int z85c30_inbyte_nonblocking_polled( static int z85c30_inbyte_nonblocking_polled(
int minor int minor
) )

6
c/src/lib/libchip/serial/z85c30.h
View File

@@ -1,6 +1,6 @@
/* z85c30.h /*
* * This include file contains all console driver definitions for the
* This include file contains all console driver definations for the z85c30 * Zilog z85c30.
* *
* COPYRIGHT (c) 1998 by Radstone Technology * COPYRIGHT (c) 1998 by Radstone Technology
* *

387
c/src/lib/libchip/serial/z85c30_p.h
View File

@@ -1,6 +1,6 @@
/* z85c30_p.h /*
* * This include file contains all private driver definitions for the
* This include file contains all private driver definations for the z85c30 * Zilog z85c30.
* *
* COPYRIGHT (c) 1998 by Radstone Technology * COPYRIGHT (c) 1998 by Radstone Technology
* *
@@ -23,7 +23,7 @@
* the file LICENSE in this distribution or at * the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html. * http://www.OARcorp.com/rtems/license.html.
* *
* $Id: * $Id$
*/ */
#ifndef __Z85C30_P_H #ifndef __Z85C30_P_H
@@ -36,48 +36,48 @@ extern "C" {
/* bit values for write register 0 */ /* bit values for write register 0 */
/* command register */ /* command register */
#define SCC_WR0_SEL_WR0 0x00 #define SCC_WR0_SEL_WR0 0x00
#define SCC_WR0_SEL_WR1 0x01 #define SCC_WR0_SEL_WR1 0x01
#define SCC_WR0_SEL_WR2 0x02 #define SCC_WR0_SEL_WR2 0x02
#define SCC_WR0_SEL_WR3 0x03 #define SCC_WR0_SEL_WR3 0x03
#define SCC_WR0_SEL_WR4 0x04 #define SCC_WR0_SEL_WR4 0x04
#define SCC_WR0_SEL_WR5 0x05 #define SCC_WR0_SEL_WR5 0x05
#define SCC_WR0_SEL_WR6 0x06 #define SCC_WR0_SEL_WR6 0x06
#define SCC_WR0_SEL_WR7 0x07 #define SCC_WR0_SEL_WR7 0x07
#define SCC_WR0_SEL_WR8 0x08 #define SCC_WR0_SEL_WR8 0x08
#define SCC_WR0_SEL_WR9 0x09 #define SCC_WR0_SEL_WR9 0x09
#define SCC_WR0_SEL_WR10 0x0a #define SCC_WR0_SEL_WR10 0x0a
#define SCC_WR0_SEL_WR11 0x0b #define SCC_WR0_SEL_WR11 0x0b
#define SCC_WR0_SEL_WR12 0x0c #define SCC_WR0_SEL_WR12 0x0c
#define SCC_WR0_SEL_WR13 0x0d #define SCC_WR0_SEL_WR13 0x0d
#define SCC_WR0_SEL_WR14 0x0e #define SCC_WR0_SEL_WR14 0x0e
#define SCC_WR0_SEL_WR15 0x0f #define SCC_WR0_SEL_WR15 0x0f
#define SCC_WR0_SEL_RD0 0x00 #define SCC_WR0_SEL_RD0 0x00
#define SCC_WR0_SEL_RD1 0x01 #define SCC_WR0_SEL_RD1 0x01
#define SCC_WR0_SEL_RD2 0x02 #define SCC_WR0_SEL_RD2 0x02
#define SCC_WR0_SEL_RD3 0x03 #define SCC_WR0_SEL_RD3 0x03
#define SCC_WR0_SEL_RD4 0x04 #define SCC_WR0_SEL_RD4 0x04
#define SCC_WR0_SEL_RD5 0x05 #define SCC_WR0_SEL_RD5 0x05
#define SCC_WR0_SEL_RD6 0x06 #define SCC_WR0_SEL_RD6 0x06
#define SCC_WR0_SEL_RD7 0x07 #define SCC_WR0_SEL_RD7 0x07
#define SCC_WR0_SEL_RD8 0x08 #define SCC_WR0_SEL_RD8 0x08
#define SCC_WR0_SEL_RD9 0x09 #define SCC_WR0_SEL_RD9 0x09
#define SCC_WR0_SEL_RD10 0x0a #define SCC_WR0_SEL_RD10 0x0a
#define SCC_WR0_SEL_RD11 0x0b #define SCC_WR0_SEL_RD11 0x0b
#define SCC_WR0_SEL_RD12 0x0c #define SCC_WR0_SEL_RD12 0x0c
#define SCC_WR0_SEL_RD13 0x0d #define SCC_WR0_SEL_RD13 0x0d
#define SCC_WR0_SEL_RD14 0x0e #define SCC_WR0_SEL_RD14 0x0e
#define SCC_WR0_SEL_RD15 0x0f #define SCC_WR0_SEL_RD15 0x0f
#define SCC_WR0_NULL_CODE 0x00 #define SCC_WR0_NULL_CODE 0x00
#define SCC_WR0_RST_INT 0x10 #define SCC_WR0_RST_INT 0x10
#define SCC_WR0_SEND_ABORT 0x18 #define SCC_WR0_SEND_ABORT 0x18
#define SCC_WR0_EN_INT_RX 0x20 #define SCC_WR0_EN_INT_RX 0x20
#define SCC_WR0_RST_TX_INT 0x28 #define SCC_WR0_RST_TX_INT 0x28
#define SCC_WR0_ERR_RST 0x30 #define SCC_WR0_ERR_RST 0x30
#define SCC_WR0_RST_HI_IUS 0x38 #define SCC_WR0_RST_HI_IUS 0x38
#define SCC_WR0_RST_RX_CRC 0x40 #define SCC_WR0_RST_RX_CRC 0x40
#define SCC_WR0_RST_TX_CRC 0x80 #define SCC_WR0_RST_TX_CRC 0x80
#define SCC_WR0_RST_TX_UND 0xc0 #define SCC_WR0_RST_TX_UND 0xc0
/* write register 2 */ /* write register 2 */
/* interrupt vector */ /* interrupt vector */
@@ -85,62 +85,62 @@ extern "C" {
/* bit values for write register 1 */ /* bit values for write register 1 */
/* tx/rx interrupt and data transfer mode definition */ /* tx/rx interrupt and data transfer mode definition */
#define SCC_WR1_EXT_INT_EN 0x01 #define SCC_WR1_EXT_INT_EN 0x01
#define SCC_WR1_TX_INT_EN 0x02 #define SCC_WR1_TX_INT_EN 0x02
#define SCC_WR1_PARITY 0x04 #define SCC_WR1_PARITY 0x04
#define SCC_WR1_RX_INT_DIS 0x00 #define SCC_WR1_RX_INT_DIS 0x00
#define SCC_WR1_RX_INT_FIR 0x08 #define SCC_WR1_RX_INT_FIR 0x08
#define SCC_WR1_INT_ALL_RX 0x10 #define SCC_WR1_INT_ALL_RX 0x10
#define SCC_WR1_RX_INT_SPE 0x18 #define SCC_WR1_RX_INT_SPE 0x18
#define SCC_WR1_RDMA_RECTR 0x20 #define SCC_WR1_RDMA_RECTR 0x20
#define SCC_WR1_RDMA_FUNC 0x40 #define SCC_WR1_RDMA_FUNC 0x40
#define SCC_WR1_RDMA_EN 0x80 #define SCC_WR1_RDMA_EN 0x80
/* bit values for write register 3 */ /* bit values for write register 3 */
/* receive parameters and control */ /* receive parameters and control */
#define SCC_WR3_RX_EN 0x01 #define SCC_WR3_RX_EN 0x01
#define SCC_WR3_SYNC_CHAR 0x02 #define SCC_WR3_SYNC_CHAR 0x02
#define SCC_WR3_ADR_SEARCH 0x04 #define SCC_WR3_ADR_SEARCH 0x04
#define SCC_WR3_RX_CRC_EN 0x08 #define SCC_WR3_RX_CRC_EN 0x08
#define SCC_WR3_ENTER_HUNT 0x10 #define SCC_WR3_ENTER_HUNT 0x10
#define SCC_WR3_AUTO_EN 0x20 #define SCC_WR3_AUTO_EN 0x20
#define SCC_WR3_RX_5_BITS 0x00 #define SCC_WR3_RX_5_BITS 0x00
#define SCC_WR3_RX_7_BITS 0x40 #define SCC_WR3_RX_7_BITS 0x40
#define SCC_WR3_RX_6_BITS 0x80 #define SCC_WR3_RX_6_BITS 0x80
#define SCC_WR3_RX_8_BITS 0xc0 #define SCC_WR3_RX_8_BITS 0xc0
/* bit values for write register 4 */ /* bit values for write register 4 */
/* tx/rx misc parameters and modes */ /* tx/rx misc parameters and modes */
#define SCC_WR4_PAR_EN 0x01 #define SCC_WR4_PAR_EN 0x01
#define SCC_WR4_PAR_EVEN 0x02 #define SCC_WR4_PAR_EVEN 0x02
#define SCC_WR4_SYNC_EN 0x00 #define SCC_WR4_SYNC_EN 0x00
#define SCC_WR4_1_STOP 0x04 #define SCC_WR4_1_STOP 0x04
#define SCC_WR4_2_STOP 0x0c #define SCC_WR4_2_STOP 0x0c
#define SCC_WR4_8_SYNC 0x00 #define SCC_WR4_8_SYNC 0x00
#define SCC_WR4_16_SYNC 0x10 #define SCC_WR4_16_SYNC 0x10
#define SCC_WR4_SDLC 0x20 #define SCC_WR4_SDLC 0x20
#define SCC_WR4_EXT_SYNC 0x30 #define SCC_WR4_EXT_SYNC 0x30
#define SCC_WR4_1_CLOCK 0x00 #define SCC_WR4_1_CLOCK 0x00
#define SCC_WR4_16_CLOCK 0x40 #define SCC_WR4_16_CLOCK 0x40
#define SCC_WR4_32_CLOCK 0x80 #define SCC_WR4_32_CLOCK 0x80
#define SCC_WR4_64_CLOCK 0xc0 #define SCC_WR4_64_CLOCK 0xc0
/* bit values for write register 5 */ /* bit values for write register 5 */
/* transmit parameter and controls */ /* transmit parameter and controls */
#define SCC_WR5_TX_CRC_EN 0x01 #define SCC_WR5_TX_CRC_EN 0x01
#define SCC_WR5_RTS 0x02 #define SCC_WR5_RTS 0x02
#define SCC_WR5_SDLC 0x04 #define SCC_WR5_SDLC 0x04
#define SCC_WR5_TX_EN 0x08 #define SCC_WR5_TX_EN 0x08
#define SCC_WR5_SEND_BRK 0x10 #define SCC_WR5_SEND_BRK 0x10
#define SCC_WR5_TX_5_BITS 0x00 #define SCC_WR5_TX_5_BITS 0x00
#define SCC_WR5_TX_7_BITS 0x20 #define SCC_WR5_TX_7_BITS 0x20
#define SCC_WR5_TX_6_BITS 0x40 #define SCC_WR5_TX_6_BITS 0x40
#define SCC_WR5_TX_8_BITS 0x60 #define SCC_WR5_TX_8_BITS 0x60
#define SCC_WR5_DTR 0x80 #define SCC_WR5_DTR 0x80
/* write register 6 */ /* write register 6 */
/* sync chars or sdlc address field */ /* sync chars or sdlc address field */
@@ -154,47 +154,47 @@ extern "C" {
/* bit values for write register 9 */ /* bit values for write register 9 */
/* master interrupt control */ /* master interrupt control */
#define SCC_WR9_VIS 0x01 #define SCC_WR9_VIS 0x01
#define SCC_WR9_NV 0x02 #define SCC_WR9_NV 0x02
#define SCC_WR9_DLC 0x04 #define SCC_WR9_DLC 0x04
#define SCC_WR9_MIE 0x08 #define SCC_WR9_MIE 0x08
#define SCC_WR9_STATUS_HI 0x10 #define SCC_WR9_STATUS_HI 0x10
#define SCC_WR9_NO_RST 0x00 #define SCC_WR9_NO_RST 0x00
#define SCC_WR9_CH_B_RST 0x40 #define SCC_WR9_CH_B_RST 0x40
#define SCC_WR9_CH_A_RST 0x80 #define SCC_WR9_CH_A_RST 0x80
#define SCC_WR9_HDWR_RST 0xc0 #define SCC_WR9_HDWR_RST 0xc0
/* bit values for write register 10 */ /* bit values for write register 10 */
/* misc tx/rx control bits */ /* misc tx/rx control bits */
#define SCC_WR10_6_BIT_SYNC 0x01 #define SCC_WR10_6_BIT_SYNC 0x01
#define SCC_WR10_LOOP_MODE 0x02 #define SCC_WR10_LOOP_MODE 0x02
#define SCC_WR10_ABORT_UND 0x04 #define SCC_WR10_ABORT_UND 0x04
#define SCC_WR10_MARK_IDLE 0x08 #define SCC_WR10_MARK_IDLE 0x08
#define SCC_WR10_ACT_POLL 0x10 #define SCC_WR10_ACT_POLL 0x10
#define SCC_WR10_NRZ 0x00 #define SCC_WR10_NRZ 0x00
#define SCC_WR10_NRZI 0x20 #define SCC_WR10_NRZI 0x20
#define SCC_WR10_FM1 0x40 #define SCC_WR10_FM1 0x40
#define SCC_WR10_FM0 0x60 #define SCC_WR10_FM0 0x60
#define SCC_WR10_CRC_PRESET 0x80 #define SCC_WR10_CRC_PRESET 0x80
/* bit values for write register 11 */ /* bit values for write register 11 */
/* clock mode control */ /* clock mode control */
#define SCC_WR11_OUT_XTAL 0x00 #define SCC_WR11_OUT_XTAL 0x00
#define SCC_WR11_OUT_TX_CLK 0x01 #define SCC_WR11_OUT_TX_CLK 0x01
#define SCC_WR11_OUT_BR_GEN 0x02 #define SCC_WR11_OUT_BR_GEN 0x02
#define SCC_WR11_OUT_DPLL 0x03 #define SCC_WR11_OUT_DPLL 0x03
#define SCC_WR11_TRXC_OI 0x04 #define SCC_WR11_TRXC_OI 0x04
#define SCC_WR11_TX_RTXC 0x00 #define SCC_WR11_TX_RTXC 0x00
#define SCC_WR11_TX_TRXC 0x08 #define SCC_WR11_TX_TRXC 0x08
#define SCC_WR11_TX_BR_GEN 0x10 #define SCC_WR11_TX_BR_GEN 0x10
#define SCC_WR11_TX_DPLL 0x18 #define SCC_WR11_TX_DPLL 0x18
#define SCC_WR11_RX_RTXC 0x00 #define SCC_WR11_RX_RTXC 0x00
#define SCC_WR11_RX_TRXC 0x20 #define SCC_WR11_RX_TRXC 0x20
#define SCC_WR11_RX_BR_GEN 0x40 #define SCC_WR11_RX_BR_GEN 0x40
#define SCC_WR11_RX_DPLL 0x60 #define SCC_WR11_RX_DPLL 0x60
#define SCC_WR11_RTXC_XTAL 0x80 #define SCC_WR11_RTXC_XTAL 0x80
/* write register 12 */ /* write register 12 */
/* lower byte of baud rate generator time constant */ /* lower byte of baud rate generator time constant */
@@ -205,52 +205,52 @@ extern "C" {
/* bit values for write register 14 */ /* bit values for write register 14 */
/* misc control bits */ /* misc control bits */
#define SCC_WR14_BR_EN 0x01 #define SCC_WR14_BR_EN 0x01
#define SCC_WR14_BR_SRC 0x02 #define SCC_WR14_BR_SRC 0x02
#define SCC_WR14_DTR_FUNC 0x04 #define SCC_WR14_DTR_FUNC 0x04
#define SCC_WR14_AUTO_ECHO 0x08 #define SCC_WR14_AUTO_ECHO 0x08
#define SCC_WR14_LCL_LOOP 0x10 #define SCC_WR14_LCL_LOOP 0x10
#define SCC_WR14_NULL 0x00 #define SCC_WR14_NULL 0x00
#define SCC_WR14_SEARCH 0x20 #define SCC_WR14_SEARCH 0x20
#define SCC_WR14_RST_CLK 0x40 #define SCC_WR14_RST_CLK 0x40
#define SCC_WR14_DIS_DPLL 0x60 #define SCC_WR14_DIS_DPLL 0x60
#define SCC_WR14_SRC_BR 0x80 #define SCC_WR14_SRC_BR 0x80
#define SCC_WR14_SRC_RTXC 0xa0 #define SCC_WR14_SRC_RTXC 0xa0
#define SCC_WR14_FM_MODE 0xc0 #define SCC_WR14_FM_MODE 0xc0
#define SCC_WR14_NRZI 0xe0 #define SCC_WR14_NRZI 0xe0
/* bit values for write register 15 */ /* bit values for write register 15 */
/* external/status interrupt control */ /* external/status interrupt control */
#define SCC_WR15_ZERO_CNT 0x02 #define SCC_WR15_ZERO_CNT 0x02
#define SCC_WR15_CD_IE 0x08 #define SCC_WR15_CD_IE 0x08
#define SCC_WR15_SYNC_IE 0x10 #define SCC_WR15_SYNC_IE 0x10
#define SCC_WR15_CTS_IE 0x20 #define SCC_WR15_CTS_IE 0x20
#define SCC_WR15_TX_UND_IE 0x40 #define SCC_WR15_TX_UND_IE 0x40
#define SCC_WR15_BREAK_IE 0x80 #define SCC_WR15_BREAK_IE 0x80
/* bit values for read register 0 */ /* bit values for read register 0 */
/* tx/rx buffer status and external status */ /* tx/rx buffer status and external status */
#define SCC_RR0_RX_AVAIL 0x01 #define SCC_RR0_RX_AVAIL 0x01
#define SCC_RR0_ZERO_CNT 0x02 #define SCC_RR0_ZERO_CNT 0x02
#define SCC_RR0_TX_EMPTY 0x04 #define SCC_RR0_TX_EMPTY 0x04
#define SCC_RR0_CD 0x08 #define SCC_RR0_CD 0x08
#define SCC_RR0_SYNC 0x10 #define SCC_RR0_SYNC 0x10
#define SCC_RR0_CTS 0x20 #define SCC_RR0_CTS 0x20
#define SCC_RR0_TX_UND 0x40 #define SCC_RR0_TX_UND 0x40
#define SCC_RR0_BREAK 0x80 #define SCC_RR0_BREAK 0x80
/* bit values for read register 1 */ /* bit values for read register 1 */
#define SCC_RR1_ALL_SENT 0x01 #define SCC_RR1_ALL_SENT 0x01
#define SCC_RR1_RES_CD_2 0x02 #define SCC_RR1_RES_CD_2 0x02
#define SCC_RR1_RES_CD_1 0x01 #define SCC_RR1_RES_CD_1 0x01
#define SCC_RR1_RES_CD_0 0x08 #define SCC_RR1_RES_CD_0 0x08
#define SCC_RR1_PAR_ERR 0x10 #define SCC_RR1_PAR_ERR 0x10
#define SCC_RR1_RX_OV_ERR 0x20 #define SCC_RR1_RX_OV_ERR 0x20
#define SCC_RR1_CRC_ERR 0x40 #define SCC_RR1_CRC_ERR 0x40
#define SCC_RR1_END_FRAME 0x80 #define SCC_RR1_END_FRAME 0x80
/* read register 2 */ /* read register 2 */
/* interrupt vector */ /* interrupt vector */
@@ -258,12 +258,12 @@ extern "C" {
/* bit values for read register 3 */ /* bit values for read register 3 */
/* interrupt pending register */ /* interrupt pending register */
#define SCC_RR3_B_EXT_IP 0x01 #define SCC_RR3_B_EXT_IP 0x01
#define SCC_RR3_B_TX_IP 0x02 #define SCC_RR3_B_TX_IP 0x02
#define SCC_RR3_B_RX_IP 0x04 #define SCC_RR3_B_RX_IP 0x04
#define SCC_RR3_A_EXT_IP 0x08 #define SCC_RR3_A_EXT_IP 0x08
#define SCC_RR3_A_TX_IP 0x10 #define SCC_RR3_A_TX_IP 0x10
#define SCC_RR3_A_RX_IP 0x20 #define SCC_RR3_A_RX_IP 0x20
/* read register 8 */ /* read register 8 */
/* receive data register */ /* receive data register */
@@ -271,10 +271,10 @@ extern "C" {
/* bit values for read register 10 */ /* bit values for read register 10 */
/* misc status bits */ /* misc status bits */
#define SCC_RR10_ON_LOOP 0x02 #define SCC_RR10_ON_LOOP 0x02
#define SCC_RR10_LOOP_SEND 0x10 #define SCC_RR10_LOOP_SEND 0x10
#define SCC_RR10_2_CLK_MIS 0x40 #define SCC_RR10_2_CLK_MIS 0x40
#define SCC_RR10_1_CLK_MIS 0x80 #define SCC_RR10_1_CLK_MIS 0x80
/* read register 12 */ /* read register 12 */
/* lower byte of time constant */ /* lower byte of time constant */
@@ -285,16 +285,16 @@ extern "C" {
/* bit values for read register 15 */ /* bit values for read register 15 */
/* external/status ie bits */ /* external/status ie bits */
#define SCC_RR15_ZERO_CNT 0x02 #define SCC_RR15_ZERO_CNT 0x02
#define SCC_RR15_CD_IE 0x08 #define SCC_RR15_CD_IE 0x08
#define SCC_RR15_SYNC_IE 0x10 #define SCC_RR15_SYNC_IE 0x10
#define SCC_RR15_CTS_IE 0x20 #define SCC_RR15_CTS_IE 0x20
#define SCC_RR15_TX_UND_IE 0x40 #define SCC_RR15_TX_UND_IE 0x40
#define SCC_RR15_BREAK_IE 0x80 #define SCC_RR15_BREAK_IE 0x80
typedef struct _z85c30_context typedef struct _z85c30_context
{ {
unsigned8 ucModemCtrl; unsigned8 ucModemCtrl;
} z85c30_context; } z85c30_context;
/* /*
@@ -303,6 +303,7 @@ typedef struct _z85c30_context
* Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2 * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2
* eg ((10,000,000 / 16) / (2 * Baud Rate)) - 2 * eg ((10,000,000 / 16) / (2 * Baud Rate)) - 2
*/ */
#define Z85C30_Baud( _clock, _baud_rate ) \ #define Z85C30_Baud( _clock, _baud_rate ) \
( ((_clock) /( 16 * 2 * _baud_rate)) - 2) ( ((_clock) /( 16 * 2 * _baud_rate)) - 2)
@@ -326,36 +327,36 @@ static boolean z85c30_probe(int minor);
static void z85c30_init(int minor); static void z85c30_init(int minor);
static int z85c30_open( static int z85c30_open(
int major, int major,
int minor, int minor,
void * arg void * arg
); );
static int z85c30_close( static int z85c30_close(
int major, int major,
int minor, int minor,
void * arg void * arg
); );
static void z85c30_write_polled( static void z85c30_write_polled(
int minor, int minor,
char cChar char cChar
); );
static int z85c30_assert_RTS( static int z85c30_assert_RTS(
int minor int minor
); );
static int z85c30_negate_RTS( static int z85c30_negate_RTS(
int minor int minor
); );
static int z85c30_assert_DTR( static int z85c30_assert_DTR(
int minor int minor
); );
static int z85c30_negate_DTR( static int z85c30_negate_DTR(
int minor int minor
); );
static void z85c30_initialize_interrupts(int minor); static void z85c30_initialize_interrupts(int minor);
@@ -363,19 +364,19 @@ static void z85c30_initialize_interrupts(int minor);
static int z85c30_flush(int major, int minor, void *arg); static int z85c30_flush(int major, int minor, void *arg);
static int z85c30_write_support_int( static int z85c30_write_support_int(
int minor, int minor,
const char *buf, const char *buf,
int len int len
); );
static int z85c30_write_support_polled( static int z85c30_write_support_polled(
int minor, int minor,
const char *buf, const char *buf,
int len int len
); );
static int z85c30_inbyte_nonblocking_polled( static int z85c30_inbyte_nonblocking_polled(
int minor int minor
); );
#ifdef __cplusplus #ifdef __cplusplus

17
c/src/libchip/serial/z85c30.c
View File

@@ -1,6 +1,11 @@
/* /*
* This file contains the console driver chip level routines for the * This file contains the console driver chip level routines for the
* z85c30 chip. * Zilog z85c30 chip.
*
* The Zilog Z8530 is also available as:
*
* + Intel 82530
* + AMD ???
* *
* COPYRIGHT (c) 1998 by Radstone Technology * COPYRIGHT (c) 1998 by Radstone Technology
* *
@@ -36,6 +41,7 @@
/* /*
* Flow control is only supported when using interrupts * Flow control is only supported when using interrupts
*/ */
console_flow z85c30_flow_RTSCTS = console_flow z85c30_flow_RTSCTS =
{ {
z85c30_negate_RTS, /* deviceStopRemoteTx */ z85c30_negate_RTS, /* deviceStopRemoteTx */
@@ -51,6 +57,7 @@ console_flow z85c30_flow_DTRCTS =
/* /*
* Exported driver function table * Exported driver function table
*/ */
console_fns z85c30_fns = console_fns z85c30_fns =
{ {
z85c30_probe, /* deviceProbe */ z85c30_probe, /* deviceProbe */
@@ -346,9 +353,11 @@ static void z85c30_init(int minor)
/* /*
* These routines provide control of the RTS and DTR lines * These routines provide control of the RTS and DTR lines
*/ */
/* /*
* z85c30_assert_RTS * z85c30_assert_RTS
*/ */
static int z85c30_assert_RTS(int minor) static int z85c30_assert_RTS(int minor)
{ {
rtems_interrupt_level Irql; rtems_interrupt_level Irql;
@@ -377,6 +386,7 @@ static int z85c30_assert_RTS(int minor)
/* /*
* z85c30_negate_RTS * z85c30_negate_RTS
*/ */
static int z85c30_negate_RTS(int minor) static int z85c30_negate_RTS(int minor)
{ {
rtems_interrupt_level Irql; rtems_interrupt_level Irql;
@@ -406,9 +416,11 @@ static int z85c30_negate_RTS(int minor)
* These flow control routines utilise a connection from the local DTR * These flow control routines utilise a connection from the local DTR
* line to the remote CTS line * line to the remote CTS line
*/ */
/* /*
* z85c30_assert_DTR * z85c30_assert_DTR
*/ */
static int z85c30_assert_DTR(int minor) static int z85c30_assert_DTR(int minor)
{ {
rtems_interrupt_level Irql; rtems_interrupt_level Irql;
@@ -437,6 +449,7 @@ static int z85c30_assert_DTR(int minor)
/* /*
* z85c30_negate_DTR * z85c30_negate_DTR
*/ */
static int z85c30_negate_DTR(int minor) static int z85c30_negate_DTR(int minor)
{ {
rtems_interrupt_level Irql; rtems_interrupt_level Irql;
@@ -712,6 +725,7 @@ static void z85c30_initialize_interrupts(
* Console Termios output entry point. * Console Termios output entry point.
* *
*/ */
static int z85c30_write_support_int( static int z85c30_write_support_int(
int minor, int minor,
const char *buf, const char *buf,
@@ -774,6 +788,7 @@ static int z85c30_write_support_int(
* *
* This routine polls for a character. * This routine polls for a character.
*/ */
static int z85c30_inbyte_nonblocking_polled( static int z85c30_inbyte_nonblocking_polled(
int minor int minor
) )

6
c/src/libchip/serial/z85c30.h
View File

@@ -1,6 +1,6 @@
/* z85c30.h /*
* * This include file contains all console driver definitions for the
* This include file contains all console driver definations for the z85c30 * Zilog z85c30.
* *
* COPYRIGHT (c) 1998 by Radstone Technology * COPYRIGHT (c) 1998 by Radstone Technology
* *

387
c/src/libchip/serial/z85c30_p.h
View File

@@ -1,6 +1,6 @@
/* z85c30_p.h /*
* * This include file contains all private driver definitions for the
* This include file contains all private driver definations for the z85c30 * Zilog z85c30.
* *
* COPYRIGHT (c) 1998 by Radstone Technology * COPYRIGHT (c) 1998 by Radstone Technology
* *
@@ -23,7 +23,7 @@
* the file LICENSE in this distribution or at * the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html. * http://www.OARcorp.com/rtems/license.html.
* *
* $Id: * $Id$
*/ */
#ifndef __Z85C30_P_H #ifndef __Z85C30_P_H
@@ -36,48 +36,48 @@ extern "C" {
/* bit values for write register 0 */ /* bit values for write register 0 */
/* command register */ /* command register */
#define SCC_WR0_SEL_WR0 0x00 #define SCC_WR0_SEL_WR0 0x00
#define SCC_WR0_SEL_WR1 0x01 #define SCC_WR0_SEL_WR1 0x01
#define SCC_WR0_SEL_WR2 0x02 #define SCC_WR0_SEL_WR2 0x02
#define SCC_WR0_SEL_WR3 0x03 #define SCC_WR0_SEL_WR3 0x03
#define SCC_WR0_SEL_WR4 0x04 #define SCC_WR0_SEL_WR4 0x04
#define SCC_WR0_SEL_WR5 0x05 #define SCC_WR0_SEL_WR5 0x05
#define SCC_WR0_SEL_WR6 0x06 #define SCC_WR0_SEL_WR6 0x06
#define SCC_WR0_SEL_WR7 0x07 #define SCC_WR0_SEL_WR7 0x07
#define SCC_WR0_SEL_WR8 0x08 #define SCC_WR0_SEL_WR8 0x08
#define SCC_WR0_SEL_WR9 0x09 #define SCC_WR0_SEL_WR9 0x09
#define SCC_WR0_SEL_WR10 0x0a #define SCC_WR0_SEL_WR10 0x0a
#define SCC_WR0_SEL_WR11 0x0b #define SCC_WR0_SEL_WR11 0x0b
#define SCC_WR0_SEL_WR12 0x0c #define SCC_WR0_SEL_WR12 0x0c
#define SCC_WR0_SEL_WR13 0x0d #define SCC_WR0_SEL_WR13 0x0d
#define SCC_WR0_SEL_WR14 0x0e #define SCC_WR0_SEL_WR14 0x0e
#define SCC_WR0_SEL_WR15 0x0f #define SCC_WR0_SEL_WR15 0x0f
#define SCC_WR0_SEL_RD0 0x00 #define SCC_WR0_SEL_RD0 0x00
#define SCC_WR0_SEL_RD1 0x01 #define SCC_WR0_SEL_RD1 0x01
#define SCC_WR0_SEL_RD2 0x02 #define SCC_WR0_SEL_RD2 0x02
#define SCC_WR0_SEL_RD3 0x03 #define SCC_WR0_SEL_RD3 0x03
#define SCC_WR0_SEL_RD4 0x04 #define SCC_WR0_SEL_RD4 0x04
#define SCC_WR0_SEL_RD5 0x05 #define SCC_WR0_SEL_RD5 0x05
#define SCC_WR0_SEL_RD6 0x06 #define SCC_WR0_SEL_RD6 0x06
#define SCC_WR0_SEL_RD7 0x07 #define SCC_WR0_SEL_RD7 0x07
#define SCC_WR0_SEL_RD8 0x08 #define SCC_WR0_SEL_RD8 0x08
#define SCC_WR0_SEL_RD9 0x09 #define SCC_WR0_SEL_RD9 0x09
#define SCC_WR0_SEL_RD10 0x0a #define SCC_WR0_SEL_RD10 0x0a
#define SCC_WR0_SEL_RD11 0x0b #define SCC_WR0_SEL_RD11 0x0b
#define SCC_WR0_SEL_RD12 0x0c #define SCC_WR0_SEL_RD12 0x0c
#define SCC_WR0_SEL_RD13 0x0d #define SCC_WR0_SEL_RD13 0x0d
#define SCC_WR0_SEL_RD14 0x0e #define SCC_WR0_SEL_RD14 0x0e
#define SCC_WR0_SEL_RD15 0x0f #define SCC_WR0_SEL_RD15 0x0f
#define SCC_WR0_NULL_CODE 0x00 #define SCC_WR0_NULL_CODE 0x00
#define SCC_WR0_RST_INT 0x10 #define SCC_WR0_RST_INT 0x10
#define SCC_WR0_SEND_ABORT 0x18 #define SCC_WR0_SEND_ABORT 0x18
#define SCC_WR0_EN_INT_RX 0x20 #define SCC_WR0_EN_INT_RX 0x20
#define SCC_WR0_RST_TX_INT 0x28 #define SCC_WR0_RST_TX_INT 0x28
#define SCC_WR0_ERR_RST 0x30 #define SCC_WR0_ERR_RST 0x30
#define SCC_WR0_RST_HI_IUS 0x38 #define SCC_WR0_RST_HI_IUS 0x38
#define SCC_WR0_RST_RX_CRC 0x40 #define SCC_WR0_RST_RX_CRC 0x40
#define SCC_WR0_RST_TX_CRC 0x80 #define SCC_WR0_RST_TX_CRC 0x80
#define SCC_WR0_RST_TX_UND 0xc0 #define SCC_WR0_RST_TX_UND 0xc0
/* write register 2 */ /* write register 2 */
/* interrupt vector */ /* interrupt vector */
@@ -85,62 +85,62 @@ extern "C" {
/* bit values for write register 1 */ /* bit values for write register 1 */
/* tx/rx interrupt and data transfer mode definition */ /* tx/rx interrupt and data transfer mode definition */
#define SCC_WR1_EXT_INT_EN 0x01 #define SCC_WR1_EXT_INT_EN 0x01
#define SCC_WR1_TX_INT_EN 0x02 #define SCC_WR1_TX_INT_EN 0x02
#define SCC_WR1_PARITY 0x04 #define SCC_WR1_PARITY 0x04
#define SCC_WR1_RX_INT_DIS 0x00 #define SCC_WR1_RX_INT_DIS 0x00
#define SCC_WR1_RX_INT_FIR 0x08 #define SCC_WR1_RX_INT_FIR 0x08
#define SCC_WR1_INT_ALL_RX 0x10 #define SCC_WR1_INT_ALL_RX 0x10
#define SCC_WR1_RX_INT_SPE 0x18 #define SCC_WR1_RX_INT_SPE 0x18
#define SCC_WR1_RDMA_RECTR 0x20 #define SCC_WR1_RDMA_RECTR 0x20
#define SCC_WR1_RDMA_FUNC 0x40 #define SCC_WR1_RDMA_FUNC 0x40
#define SCC_WR1_RDMA_EN 0x80 #define SCC_WR1_RDMA_EN 0x80
/* bit values for write register 3 */ /* bit values for write register 3 */
/* receive parameters and control */ /* receive parameters and control */
#define SCC_WR3_RX_EN 0x01 #define SCC_WR3_RX_EN 0x01
#define SCC_WR3_SYNC_CHAR 0x02 #define SCC_WR3_SYNC_CHAR 0x02
#define SCC_WR3_ADR_SEARCH 0x04 #define SCC_WR3_ADR_SEARCH 0x04
#define SCC_WR3_RX_CRC_EN 0x08 #define SCC_WR3_RX_CRC_EN 0x08
#define SCC_WR3_ENTER_HUNT 0x10 #define SCC_WR3_ENTER_HUNT 0x10
#define SCC_WR3_AUTO_EN 0x20 #define SCC_WR3_AUTO_EN 0x20
#define SCC_WR3_RX_5_BITS 0x00 #define SCC_WR3_RX_5_BITS 0x00
#define SCC_WR3_RX_7_BITS 0x40 #define SCC_WR3_RX_7_BITS 0x40
#define SCC_WR3_RX_6_BITS 0x80 #define SCC_WR3_RX_6_BITS 0x80
#define SCC_WR3_RX_8_BITS 0xc0 #define SCC_WR3_RX_8_BITS 0xc0
/* bit values for write register 4 */ /* bit values for write register 4 */
/* tx/rx misc parameters and modes */ /* tx/rx misc parameters and modes */
#define SCC_WR4_PAR_EN 0x01 #define SCC_WR4_PAR_EN 0x01
#define SCC_WR4_PAR_EVEN 0x02 #define SCC_WR4_PAR_EVEN 0x02
#define SCC_WR4_SYNC_EN 0x00 #define SCC_WR4_SYNC_EN 0x00
#define SCC_WR4_1_STOP 0x04 #define SCC_WR4_1_STOP 0x04
#define SCC_WR4_2_STOP 0x0c #define SCC_WR4_2_STOP 0x0c
#define SCC_WR4_8_SYNC 0x00 #define SCC_WR4_8_SYNC 0x00
#define SCC_WR4_16_SYNC 0x10 #define SCC_WR4_16_SYNC 0x10
#define SCC_WR4_SDLC 0x20 #define SCC_WR4_SDLC 0x20
#define SCC_WR4_EXT_SYNC 0x30 #define SCC_WR4_EXT_SYNC 0x30
#define SCC_WR4_1_CLOCK 0x00 #define SCC_WR4_1_CLOCK 0x00
#define SCC_WR4_16_CLOCK 0x40 #define SCC_WR4_16_CLOCK 0x40
#define SCC_WR4_32_CLOCK 0x80 #define SCC_WR4_32_CLOCK 0x80
#define SCC_WR4_64_CLOCK 0xc0 #define SCC_WR4_64_CLOCK 0xc0
/* bit values for write register 5 */ /* bit values for write register 5 */
/* transmit parameter and controls */ /* transmit parameter and controls */
#define SCC_WR5_TX_CRC_EN 0x01 #define SCC_WR5_TX_CRC_EN 0x01
#define SCC_WR5_RTS 0x02 #define SCC_WR5_RTS 0x02
#define SCC_WR5_SDLC 0x04 #define SCC_WR5_SDLC 0x04
#define SCC_WR5_TX_EN 0x08 #define SCC_WR5_TX_EN 0x08
#define SCC_WR5_SEND_BRK 0x10 #define SCC_WR5_SEND_BRK 0x10
#define SCC_WR5_TX_5_BITS 0x00 #define SCC_WR5_TX_5_BITS 0x00
#define SCC_WR5_TX_7_BITS 0x20 #define SCC_WR5_TX_7_BITS 0x20
#define SCC_WR5_TX_6_BITS 0x40 #define SCC_WR5_TX_6_BITS 0x40
#define SCC_WR5_TX_8_BITS 0x60 #define SCC_WR5_TX_8_BITS 0x60
#define SCC_WR5_DTR 0x80 #define SCC_WR5_DTR 0x80
/* write register 6 */ /* write register 6 */
/* sync chars or sdlc address field */ /* sync chars or sdlc address field */
@@ -154,47 +154,47 @@ extern "C" {
/* bit values for write register 9 */ /* bit values for write register 9 */
/* master interrupt control */ /* master interrupt control */
#define SCC_WR9_VIS 0x01 #define SCC_WR9_VIS 0x01
#define SCC_WR9_NV 0x02 #define SCC_WR9_NV 0x02
#define SCC_WR9_DLC 0x04 #define SCC_WR9_DLC 0x04
#define SCC_WR9_MIE 0x08 #define SCC_WR9_MIE 0x08
#define SCC_WR9_STATUS_HI 0x10 #define SCC_WR9_STATUS_HI 0x10
#define SCC_WR9_NO_RST 0x00 #define SCC_WR9_NO_RST 0x00
#define SCC_WR9_CH_B_RST 0x40 #define SCC_WR9_CH_B_RST 0x40
#define SCC_WR9_CH_A_RST 0x80 #define SCC_WR9_CH_A_RST 0x80
#define SCC_WR9_HDWR_RST 0xc0 #define SCC_WR9_HDWR_RST 0xc0
/* bit values for write register 10 */ /* bit values for write register 10 */
/* misc tx/rx control bits */ /* misc tx/rx control bits */
#define SCC_WR10_6_BIT_SYNC 0x01 #define SCC_WR10_6_BIT_SYNC 0x01
#define SCC_WR10_LOOP_MODE 0x02 #define SCC_WR10_LOOP_MODE 0x02
#define SCC_WR10_ABORT_UND 0x04 #define SCC_WR10_ABORT_UND 0x04
#define SCC_WR10_MARK_IDLE 0x08 #define SCC_WR10_MARK_IDLE 0x08
#define SCC_WR10_ACT_POLL 0x10 #define SCC_WR10_ACT_POLL 0x10
#define SCC_WR10_NRZ 0x00 #define SCC_WR10_NRZ 0x00
#define SCC_WR10_NRZI 0x20 #define SCC_WR10_NRZI 0x20
#define SCC_WR10_FM1 0x40 #define SCC_WR10_FM1 0x40
#define SCC_WR10_FM0 0x60 #define SCC_WR10_FM0 0x60
#define SCC_WR10_CRC_PRESET 0x80 #define SCC_WR10_CRC_PRESET 0x80
/* bit values for write register 11 */ /* bit values for write register 11 */
/* clock mode control */ /* clock mode control */
#define SCC_WR11_OUT_XTAL 0x00 #define SCC_WR11_OUT_XTAL 0x00
#define SCC_WR11_OUT_TX_CLK 0x01 #define SCC_WR11_OUT_TX_CLK 0x01
#define SCC_WR11_OUT_BR_GEN 0x02 #define SCC_WR11_OUT_BR_GEN 0x02
#define SCC_WR11_OUT_DPLL 0x03 #define SCC_WR11_OUT_DPLL 0x03
#define SCC_WR11_TRXC_OI 0x04 #define SCC_WR11_TRXC_OI 0x04
#define SCC_WR11_TX_RTXC 0x00 #define SCC_WR11_TX_RTXC 0x00
#define SCC_WR11_TX_TRXC 0x08 #define SCC_WR11_TX_TRXC 0x08
#define SCC_WR11_TX_BR_GEN 0x10 #define SCC_WR11_TX_BR_GEN 0x10
#define SCC_WR11_TX_DPLL 0x18 #define SCC_WR11_TX_DPLL 0x18
#define SCC_WR11_RX_RTXC 0x00 #define SCC_WR11_RX_RTXC 0x00
#define SCC_WR11_RX_TRXC 0x20 #define SCC_WR11_RX_TRXC 0x20
#define SCC_WR11_RX_BR_GEN 0x40 #define SCC_WR11_RX_BR_GEN 0x40
#define SCC_WR11_RX_DPLL 0x60 #define SCC_WR11_RX_DPLL 0x60
#define SCC_WR11_RTXC_XTAL 0x80 #define SCC_WR11_RTXC_XTAL 0x80
/* write register 12 */ /* write register 12 */
/* lower byte of baud rate generator time constant */ /* lower byte of baud rate generator time constant */
@@ -205,52 +205,52 @@ extern "C" {
/* bit values for write register 14 */ /* bit values for write register 14 */
/* misc control bits */ /* misc control bits */
#define SCC_WR14_BR_EN 0x01 #define SCC_WR14_BR_EN 0x01
#define SCC_WR14_BR_SRC 0x02 #define SCC_WR14_BR_SRC 0x02
#define SCC_WR14_DTR_FUNC 0x04 #define SCC_WR14_DTR_FUNC 0x04
#define SCC_WR14_AUTO_ECHO 0x08 #define SCC_WR14_AUTO_ECHO 0x08
#define SCC_WR14_LCL_LOOP 0x10 #define SCC_WR14_LCL_LOOP 0x10
#define SCC_WR14_NULL 0x00 #define SCC_WR14_NULL 0x00
#define SCC_WR14_SEARCH 0x20 #define SCC_WR14_SEARCH 0x20
#define SCC_WR14_RST_CLK 0x40 #define SCC_WR14_RST_CLK 0x40
#define SCC_WR14_DIS_DPLL 0x60 #define SCC_WR14_DIS_DPLL 0x60
#define SCC_WR14_SRC_BR 0x80 #define SCC_WR14_SRC_BR 0x80
#define SCC_WR14_SRC_RTXC 0xa0 #define SCC_WR14_SRC_RTXC 0xa0
#define SCC_WR14_FM_MODE 0xc0 #define SCC_WR14_FM_MODE 0xc0
#define SCC_WR14_NRZI 0xe0 #define SCC_WR14_NRZI 0xe0
/* bit values for write register 15 */ /* bit values for write register 15 */
/* external/status interrupt control */ /* external/status interrupt control */
#define SCC_WR15_ZERO_CNT 0x02 #define SCC_WR15_ZERO_CNT 0x02
#define SCC_WR15_CD_IE 0x08 #define SCC_WR15_CD_IE 0x08
#define SCC_WR15_SYNC_IE 0x10 #define SCC_WR15_SYNC_IE 0x10
#define SCC_WR15_CTS_IE 0x20 #define SCC_WR15_CTS_IE 0x20
#define SCC_WR15_TX_UND_IE 0x40 #define SCC_WR15_TX_UND_IE 0x40
#define SCC_WR15_BREAK_IE 0x80 #define SCC_WR15_BREAK_IE 0x80
/* bit values for read register 0 */ /* bit values for read register 0 */
/* tx/rx buffer status and external status */ /* tx/rx buffer status and external status */
#define SCC_RR0_RX_AVAIL 0x01 #define SCC_RR0_RX_AVAIL 0x01
#define SCC_RR0_ZERO_CNT 0x02 #define SCC_RR0_ZERO_CNT 0x02
#define SCC_RR0_TX_EMPTY 0x04 #define SCC_RR0_TX_EMPTY 0x04
#define SCC_RR0_CD 0x08 #define SCC_RR0_CD 0x08
#define SCC_RR0_SYNC 0x10 #define SCC_RR0_SYNC 0x10
#define SCC_RR0_CTS 0x20 #define SCC_RR0_CTS 0x20
#define SCC_RR0_TX_UND 0x40 #define SCC_RR0_TX_UND 0x40
#define SCC_RR0_BREAK 0x80 #define SCC_RR0_BREAK 0x80
/* bit values for read register 1 */ /* bit values for read register 1 */
#define SCC_RR1_ALL_SENT 0x01 #define SCC_RR1_ALL_SENT 0x01
#define SCC_RR1_RES_CD_2 0x02 #define SCC_RR1_RES_CD_2 0x02
#define SCC_RR1_RES_CD_1 0x01 #define SCC_RR1_RES_CD_1 0x01
#define SCC_RR1_RES_CD_0 0x08 #define SCC_RR1_RES_CD_0 0x08
#define SCC_RR1_PAR_ERR 0x10 #define SCC_RR1_PAR_ERR 0x10
#define SCC_RR1_RX_OV_ERR 0x20 #define SCC_RR1_RX_OV_ERR 0x20
#define SCC_RR1_CRC_ERR 0x40 #define SCC_RR1_CRC_ERR 0x40
#define SCC_RR1_END_FRAME 0x80 #define SCC_RR1_END_FRAME 0x80
/* read register 2 */ /* read register 2 */
/* interrupt vector */ /* interrupt vector */
@@ -258,12 +258,12 @@ extern "C" {
/* bit values for read register 3 */ /* bit values for read register 3 */
/* interrupt pending register */ /* interrupt pending register */
#define SCC_RR3_B_EXT_IP 0x01 #define SCC_RR3_B_EXT_IP 0x01
#define SCC_RR3_B_TX_IP 0x02 #define SCC_RR3_B_TX_IP 0x02
#define SCC_RR3_B_RX_IP 0x04 #define SCC_RR3_B_RX_IP 0x04
#define SCC_RR3_A_EXT_IP 0x08 #define SCC_RR3_A_EXT_IP 0x08
#define SCC_RR3_A_TX_IP 0x10 #define SCC_RR3_A_TX_IP 0x10
#define SCC_RR3_A_RX_IP 0x20 #define SCC_RR3_A_RX_IP 0x20
/* read register 8 */ /* read register 8 */
/* receive data register */ /* receive data register */
@@ -271,10 +271,10 @@ extern "C" {
/* bit values for read register 10 */ /* bit values for read register 10 */
/* misc status bits */ /* misc status bits */
#define SCC_RR10_ON_LOOP 0x02 #define SCC_RR10_ON_LOOP 0x02
#define SCC_RR10_LOOP_SEND 0x10 #define SCC_RR10_LOOP_SEND 0x10
#define SCC_RR10_2_CLK_MIS 0x40 #define SCC_RR10_2_CLK_MIS 0x40
#define SCC_RR10_1_CLK_MIS 0x80 #define SCC_RR10_1_CLK_MIS 0x80
/* read register 12 */ /* read register 12 */
/* lower byte of time constant */ /* lower byte of time constant */
@@ -285,16 +285,16 @@ extern "C" {
/* bit values for read register 15 */ /* bit values for read register 15 */
/* external/status ie bits */ /* external/status ie bits */
#define SCC_RR15_ZERO_CNT 0x02 #define SCC_RR15_ZERO_CNT 0x02
#define SCC_RR15_CD_IE 0x08 #define SCC_RR15_CD_IE 0x08
#define SCC_RR15_SYNC_IE 0x10 #define SCC_RR15_SYNC_IE 0x10
#define SCC_RR15_CTS_IE 0x20 #define SCC_RR15_CTS_IE 0x20
#define SCC_RR15_TX_UND_IE 0x40 #define SCC_RR15_TX_UND_IE 0x40
#define SCC_RR15_BREAK_IE 0x80 #define SCC_RR15_BREAK_IE 0x80
typedef struct _z85c30_context typedef struct _z85c30_context
{ {
unsigned8 ucModemCtrl; unsigned8 ucModemCtrl;
} z85c30_context; } z85c30_context;
/* /*
@@ -303,6 +303,7 @@ typedef struct _z85c30_context
* Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2 * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2
* eg ((10,000,000 / 16) / (2 * Baud Rate)) - 2 * eg ((10,000,000 / 16) / (2 * Baud Rate)) - 2
*/ */
#define Z85C30_Baud( _clock, _baud_rate ) \ #define Z85C30_Baud( _clock, _baud_rate ) \
( ((_clock) /( 16 * 2 * _baud_rate)) - 2) ( ((_clock) /( 16 * 2 * _baud_rate)) - 2)
@@ -326,36 +327,36 @@ static boolean z85c30_probe(int minor);
static void z85c30_init(int minor); static void z85c30_init(int minor);
static int z85c30_open( static int z85c30_open(
int major, int major,
int minor, int minor,
void * arg void * arg
); );
static int z85c30_close( static int z85c30_close(
int major, int major,
int minor, int minor,
void * arg void * arg
); );
static void z85c30_write_polled( static void z85c30_write_polled(
int minor, int minor,
char cChar char cChar
); );
static int z85c30_assert_RTS( static int z85c30_assert_RTS(
int minor int minor
); );
static int z85c30_negate_RTS( static int z85c30_negate_RTS(
int minor int minor
); );
static int z85c30_assert_DTR( static int z85c30_assert_DTR(
int minor int minor
); );
static int z85c30_negate_DTR( static int z85c30_negate_DTR(
int minor int minor
); );
static void z85c30_initialize_interrupts(int minor); static void z85c30_initialize_interrupts(int minor);
@@ -363,19 +364,19 @@ static void z85c30_initialize_interrupts(int minor);
static int z85c30_flush(int major, int minor, void *arg); static int z85c30_flush(int major, int minor, void *arg);
static int z85c30_write_support_int( static int z85c30_write_support_int(
int minor, int minor,
const char *buf, const char *buf,
int len int len
); );
static int z85c30_write_support_polled( static int z85c30_write_support_polled(
int minor, int minor,
const char *buf, const char *buf,
int len int len
); );
static int z85c30_inbyte_nonblocking_polled( static int z85c30_inbyte_nonblocking_polled(
int minor int minor
); );
#ifdef __cplusplus #ifdef __cplusplus