mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
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2007-04-17 Joel Sherrill <joel@OARcorp.com>
* rtems/bfin/bf533.h: Fix warnings about constants being too large.
This commit is contained in:
Joel Sherrill
@@ -1,3 +1,7 @@
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2007-04-17 Joel Sherrill <joel@OARcorp.com>
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* rtems/bfin/bf533.h: Fix warnings about constants being too large.
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2007-04-17 Ralf Corsépius <ralf.corsepius@rtems.org>
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2007-04-17 Ralf Corsépius <ralf.corsepius@rtems.org>
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* rtems/score/cpu.h:
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* rtems/score/cpu.h:
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@@ -33,54 +33,54 @@ extern "C" {
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/* Clock and System Control Chapter 8 */
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/* Clock and System Control Chapter 8 */
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#define PLL_CTL 0xFFC00000
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#define PLL_CTL 0xFFC00000L
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#define PLL_DIV 0xFFC00004
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#define PLL_DIV 0xFFC00004L
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#define VR_CTL 0xFFC00008
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#define VR_CTL 0xFFC00008L
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#define PLL_STAT 0xFFC0000C
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#define PLL_STAT 0xFFC0000CL
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#define PLL_LOCKCNT 0xFFC00010
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#define PLL_LOCKCNT 0xFFC00010L
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#define SWRST 0xFFC00100
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#define SWRST 0xFFC00100L
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#define SYSCR 0xFFC00104
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#define SYSCR 0xFFC00104L
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/* SPI Controller Chapter 10 */
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/* SPI Controller Chapter 10 */
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#define SPI_CTL 0xFFC00500
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#define SPI_CTL 0xFFC00500L
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#define SPI_FLG 0xFFC00504
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#define SPI_FLG 0xFFC00504L
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#define SPI_STAT 0xFFC00508
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#define SPI_STAT 0xFFC00508L
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#define SPI_TDBR 0xFFC0050C
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#define SPI_TDBR 0xFFC0050CL
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#define SPI_RDBR 0xFFC00510
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#define SPI_RDBR 0xFFC00510L
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#define SPI_BAUD 0xFFC00514
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#define SPI_BAUD 0xFFC00514L
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#define SPI_SHADOW 0xFFC00518
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#define SPI_SHADOW 0xFFC00518L
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/* SPORT0 Controller */
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/* SPORT0 Controller */
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#define SPORT0_TCR1 0xFFC00800
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#define SPORT0_TCR1 0xFFC00800L
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#define SPORT0_TCR2 0xFFC00804
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#define SPORT0_TCR2 0xFFC00804L
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#define SPORT0_TCLKDIV 0xFFC00808
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#define SPORT0_TCLKDIV 0xFFC00808L
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#define SPORT0_TFSDIV 0xFFC0080C
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#define SPORT0_TFSDIV 0xFFC0080CL
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#define SPORT0_TX 0xFFC00810
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#define SPORT0_TX 0xFFC00810L
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#define SPORT0_RX 0xFFC00818
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#define SPORT0_RX 0xFFC00818L
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#define SPORT0_RCR1 0xFFC00820
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#define SPORT0_RCR1 0xFFC00820L
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#define SPORT0_RCR2 0xFFC00824
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#define SPORT0_RCR2 0xFFC00824L
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#define SPORT0_RCLKDIV 0xFFC00828
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#define SPORT0_RCLKDIV 0xFFC00828L
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#define SPORT0_RFSDIV 0xFFC0082C
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#define SPORT0_RFSDIV 0xFFC0082CL
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#define SPORT0_STAT 0xFFC00830
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#define SPORT0_STAT 0xFFC00830L
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#define SPORT0_CHNL 0xFFC00834
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#define SPORT0_CHNL 0xFFC00834L
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#define SPORT0_MCMC1 0xFFC00838
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#define SPORT0_MCMC1 0xFFC00838L
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#define SPORT0_MCMC2 0xFFC0083C
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#define SPORT0_MCMC2 0xFFC0083CL
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#define SPORT0_MTCS0 0xFFC00840
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#define SPORT0_MTCS0 0xFFC00840L
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#define SPORT0_MTCS1 0xFFC00844
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#define SPORT0_MTCS1 0xFFC00844L
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#define SPORT0_MTCS2 0xFFC00848
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#define SPORT0_MTCS2 0xFFC00848L
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#define SPORT0_MTCS3 0xFFC0084C
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#define SPORT0_MTCS3 0xFFC0084CL
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#define SPORT0_MRCS0 0xFFC00850
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#define SPORT0_MRCS0 0xFFC00850L
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#define SPORT0_MRCS1 0xFFC00854
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#define SPORT0_MRCS1 0xFFC00854L
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#define SPORT0_MRCS2 0xFFC00858
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#define SPORT0_MRCS2 0xFFC00858L
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#define SPORT0_MRCS3 0xFFC0085C
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#define SPORT0_MRCS3 0xFFC0085CL
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/* Parallel Peripheral Interface (PPI) Chapter 11 */
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/* Parallel Peripheral Interface (PPI) Chapter 11 */
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#define PPI_CONTROL 0xFFC01000
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#define PPI_CONTROL 0xFFC01000L
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#define PPI_STATUS 0xFFC01004
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#define PPI_STATUS 0xFFC01004L
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#define PPI_COUNT 0xFFC01008
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#define PPI_COUNT 0xFFC01008L
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#define PPI_DELAY 0xFFC0100C
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#define PPI_DELAY 0xFFC0100CL
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#define PPI_FRAME 0xFFC01010
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#define PPI_FRAME 0xFFC01010L
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/********* PPI MASKS ***********/
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/********* PPI MASKS ***********/
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/* PPI_CONTROL Masks */
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/* PPI_CONTROL Masks */
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@@ -107,28 +107,28 @@ extern "C" {
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#define ERR_NCOR 0x00008000
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#define ERR_NCOR 0x00008000
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/* SPORT1 Controller Chapter 12 */
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/* SPORT1 Controller Chapter 12 */
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#define SPORT1_TCR1 0xFFC00900
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#define SPORT1_TCR1 0xFFC00900L
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#define SPORT1_TCR2 0xFFC00904
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#define SPORT1_TCR2 0xFFC00904L
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#define SPORT1_TCLKDIV 0xFFC00908
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#define SPORT1_TCLKDIV 0xFFC00908L
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#define SPORT1_TFSDIV 0xFFC0090C
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#define SPORT1_TFSDIV 0xFFC0090CL
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#define SPORT1_TX 0xFFC00910
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#define SPORT1_TX 0xFFC00910L
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#define SPORT1_RX 0xFFC00918
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#define SPORT1_RX 0xFFC00918L
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#define SPORT1_RCR1 0xFFC00920
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#define SPORT1_RCR1 0xFFC00920L
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#define SPORT1_RCR2 0xFFC00924
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#define SPORT1_RCR2 0xFFC00924L
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#define SPORT1_RCLKDIV 0xFFC00928
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#define SPORT1_RCLKDIV 0xFFC00928L
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#define SPORT1_RFSDIV 0xFFC0092C
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#define SPORT1_RFSDIV 0xFFC0092CL
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#define SPORT1_STAT 0xFFC00930
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#define SPORT1_STAT 0xFFC00930L
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#define SPORT1_CHNL 0xFFC00934
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#define SPORT1_CHNL 0xFFC00934L
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#define SPORT1_MCMC1 0xFFC00938
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#define SPORT1_MCMC1 0xFFC00938L
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#define SPORT1_MCMC2 0xFFC0093C
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#define SPORT1_MCMC2 0xFFC0093CL
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#define SPORT1_MTCS0 0xFFC00940
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#define SPORT1_MTCS0 0xFFC00940L
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#define SPORT1_MTCS1 0xFFC00944
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#define SPORT1_MTCS1 0xFFC00944L
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#define SPORT1_MTCS2 0xFFC00948
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#define SPORT1_MTCS2 0xFFC00948L
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#define SPORT1_MTCS3 0xFFC0094C
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#define SPORT1_MTCS3 0xFFC0094CL
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#define SPORT1_MRCS0 0xFFC00950
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#define SPORT1_MRCS0 0xFFC00950L
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#define SPORT1_MRCS1 0xFFC00954
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#define SPORT1_MRCS1 0xFFC00954L
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#define SPORT1_MRCS2 0xFFC00958
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#define SPORT1_MRCS2 0xFFC00958L
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#define SPORT1_MRCS3 0xFFC0095C
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#define SPORT1_MRCS3 0xFFC0095CL
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/* SPORTx_TCR1 Masks */
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/* SPORTx_TCR1 Masks */
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#define TSPEN 0x0001
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#define TSPEN 0x0001
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@@ -189,18 +189,17 @@ extern "C" {
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#define MFD 0x0000F000
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#define MFD 0x0000F000
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/* UART Controller Chapter 13 */
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/* UART Controller Chapter 13 */
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#define UART_THR 0xFFC00400
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#define UART_THR 0xFFC00400L
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#define UART_RBR 0xFFC00400
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#define UART_RBR 0xFFC00400L
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#define UART_DLL 0xFFC00400
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#define UART_DLL 0xFFC00400L
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#define UART_IER 0xFFC00404
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#define UART_IER 0xFFC00404L
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#define UART_DLH 0xFFC00404
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#define UART_DLH 0xFFC00404L
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#define UART_IIR 0xFFC00408
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#define UART_IIR 0xFFC00408L
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#define UART_LCR 0xFFC0040C
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#define UART_LCR 0xFFC0040CL
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#define UART_MCR 0xFFC00410
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#define UART_MCR 0xFFC00410L
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#define UART_LSR 0xFFC00414
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#define UART_LSR 0xFFC00414L
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#define UART_SCR 0xFFC0041CL
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#define UART_SCR 0xFFC0041C
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#define UART_GCTL 0xFFC00424L
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#define UART_GCTL 0xFFC00424
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/*
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/*
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* UART CONTROLLER MASKS
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* UART CONTROLLER MASKS
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@@ -277,23 +276,23 @@ extern "C" {
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#define UCEN_P 0x00
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#define UCEN_P 0x00
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/* General Purpose IO Chapter 14*/
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/* General Purpose IO Chapter 14*/
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#define FIO_FLAG_D 0xFFC00700
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#define FIO_FLAG_D 0xFFC00700L
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#define FIO_FLAG_C 0xFFC00704
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#define FIO_FLAG_C 0xFFC00704L
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#define FIO_FLAG_S 0xFFC00708
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#define FIO_FLAG_S 0xFFC00708L
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#define FIO_FLAG_T 0xFFC0070C
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#define FIO_FLAG_T 0xFFC0070CL
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#define FIO_MASKA_D 0xFFC00710
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#define FIO_MASKA_D 0xFFC00710L
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#define FIO_MASKA_C 0xFFC00714
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#define FIO_MASKA_C 0xFFC00714L
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#define FIO_MASKA_S 0xFFC00718
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#define FIO_MASKA_S 0xFFC00718L
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#define FIO_MASKA_T 0xFFC0071C
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#define FIO_MASKA_T 0xFFC0071CL
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#define FIO_MASKB_D 0xFFC00720
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#define FIO_MASKB_D 0xFFC00720L
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#define FIO_MASKB_C 0xFFC00724
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#define FIO_MASKB_C 0xFFC00724L
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#define FIO_MASKB_S 0xFFC00728
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#define FIO_MASKB_S 0xFFC00728L
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#define FIO_MASKB_T 0xFFC0072C
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#define FIO_MASKB_T 0xFFC0072CL
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#define FIO_DIR 0xFFC00730
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#define FIO_DIR 0xFFC00730L
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#define FIO_POLAR 0xFFC00734
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#define FIO_POLAR 0xFFC00734L
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#define FIO_EDGE 0xFFC00738
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#define FIO_EDGE 0xFFC00738L
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#define FIO_BOTH 0xFFC0073C
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#define FIO_BOTH 0xFFC0073CL
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#define FIO_INEN 0xFFC00740
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#define FIO_INEN 0xFFC00740L
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/* General Purpose IO Masks */
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/* General Purpose IO Masks */
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#define PF0 0x0001
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#define PF0 0x0001
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@@ -315,49 +314,49 @@ extern "C" {
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/* TIMER 0, 1, 2 Chapter 15 */
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/* TIMER 0, 1, 2 Chapter 15 */
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#define TIMER0_CONFIG 0xFFC00600
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#define TIMER0_CONFIG 0xFFC00600L
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#define TIMER0_COUNTER 0xFFC00604
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#define TIMER0_COUNTER 0xFFC00604L
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#define TIMER0_PERIOD 0xFFC00608
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#define TIMER0_PERIOD 0xFFC00608L
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#define TIMER0_WIDTH 0xFFC0060C
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#define TIMER0_WIDTH 0xFFC0060CL
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#define TIMER1_CONFIG 0xFFC00610
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#define TIMER1_CONFIG 0xFFC00610L
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#define TIMER1_COUNTER 0xFFC00614
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#define TIMER1_COUNTER 0xFFC00614L
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#define TIMER1_PERIOD 0xFFC00618
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#define TIMER1_PERIOD 0xFFC00618L
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#define TIMER1_WIDTH 0xFFC0061C
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#define TIMER1_WIDTH 0xFFC0061CL
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#define TIMER2_CONFIG 0xFFC00620
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#define TIMER2_CONFIG 0xFFC00620L
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#define TIMER2_COUNTER 0xFFC00624
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#define TIMER2_COUNTER 0xFFC00624L
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#define TIMER2_PERIOD 0xFFC00628
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#define TIMER2_PERIOD 0xFFC00628L
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#define TIMER2_WIDTH 0xFFC0062C
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#define TIMER2_WIDTH 0xFFC0062CL
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#define TIMER_ENABLE 0xFFC00640
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#define TIMER_ENABLE 0xFFC00640L
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#define TIMER_DISABLE 0xFFC00644
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#define TIMER_DISABLE 0xFFC00644L
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#define TIMER_STATUS 0xFFC00648
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#define TIMER_STATUS 0xFFC00648L
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/* Real Time Clock Chapter 16 */
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/* Real Time Clock Chapter 16 */
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#define RTC_STAT 0xFFC00300
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#define RTC_STAT 0xFFC00300L
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#define RTC_ICTL 0xFFC00304
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#define RTC_ICTL 0xFFC00304L
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#define RTC_ISTAT 0xFFC00308
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#define RTC_ISTAT 0xFFC00308L
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#define RTC_SWCNT 0xFFC0030C
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#define RTC_SWCNT 0xFFC0030CL
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#define RTC_ALARM 0xFFC00310
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#define RTC_ALARM 0xFFC00310L
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#define RTC_FAST 0xFFC00314
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#define RTC_FAST 0xFFC00314L
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#define RTC_PREN 0xFFC00314
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#define RTC_PREN 0xFFC00314L
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/* RTC_FAST Mask (RTC_PREN Mask) */
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/* RTC_FAST Mask (RTC_PREN Mask) */
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#define ENABLE_PRESCALE 0x00000001
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#define ENABLE_PRESCALE 0x00000001
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#define PREN 0x00000001
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#define PREN 0x00000001
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/* Asynchronous Memory Controller EBUI, Chapter 17*/
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/* Asynchronous Memory Controller EBUI, Chapter 17*/
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#define EBIU_AMGCTL 0xFFC00A00
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#define EBIU_AMGCTL 0xFFC00A00L
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#define EBIU_AMBCTL0 0xFFC00A04
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#define EBIU_AMBCTL0 0xFFC00A04L
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#define EBIU_AMBCTL1 0xFFC00A08
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#define EBIU_AMBCTL1 0xFFC00A08L
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/* SDRAM Controller External Bus Interface Unit */
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/* SDRAM Controller External Bus Interface Unit */
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#define EBIU_SDGCTL 0xFFC00A10
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#define EBIU_SDGCTL 0xFFC00A10L
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#define EBIU_SDBCTL 0xFFC00A14
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#define EBIU_SDBCTL 0xFFC00A14L
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#define EBIU_SDRRC 0xFFC00A18
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#define EBIU_SDRRC 0xFFC00A18L
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#define EBIU_SDSTAT 0xFFC00A1C
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#define EBIU_SDSTAT 0xFFC00A1CL
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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