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bsp/atsam: Enable configuration of SDRAMC_LPR

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This commit is contained in:
Sebastian Huber
2019-06-21 06:58:19 +02:00
parent d9fcb22a61
commit dc581f29ab
3 changed files with 13 additions and 7 deletions
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1
bsps/arm/atsam/contrib/libraries/libboard/source/board_memories.c
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@@ -288,6 +288,7 @@ void BOARD_ConfigureSdram(void)
#else /* __rtems__ */ #else /* __rtems__ */
SDRAMC->SDRAMC_TR = BOARD_Sdram_Config.sdramc_tr; SDRAMC->SDRAMC_TR = BOARD_Sdram_Config.sdramc_tr;
SDRAMC->SDRAMC_CFR1 = BOARD_Sdram_Config.sdramc_cfr1; SDRAMC->SDRAMC_CFR1 = BOARD_Sdram_Config.sdramc_cfr1;
SDRAMC->SDRAMC_LPR = BOARD_Sdram_Config.sdramc_lpr;
#endif /* __rtems__ */ #endif /* __rtems__ */
/* After initialization, the SDRAM devices are fully functional. */ /* After initialization, the SDRAM devices are fully functional. */
} }

7
bsps/arm/atsam/include/bsp/atsam-clock-config.h
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@@ -45,15 +45,16 @@ extern const struct atsam_clock_config atsam_clock_config;
#define BOARD_MCK (atsam_clock_config.mck_freq) #define BOARD_MCK (atsam_clock_config.mck_freq)
struct BOARD_Sdram_Config { typedef struct BOARD_Sdram_Config {
uint32_t sdramc_tr; uint32_t sdramc_tr;
uint32_t sdramc_cr; uint32_t sdramc_cr;
uint32_t sdramc_mdr; uint32_t sdramc_mdr;
uint32_t sdramc_cfr1; uint32_t sdramc_cfr1;
}; uint32_t sdramc_lpr;
} atsam_sdram_config;
ATSAM_START_SRAM_SECTION ATSAM_START_SRAM_SECTION
extern const struct BOARD_Sdram_Config BOARD_Sdram_Config; extern const atsam_sdram_config BOARD_Sdram_Config;
#ifdef __cplusplus #ifdef __cplusplus
} }

12
bsps/arm/atsam/start/sdram-config.c
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@@ -38,7 +38,8 @@ const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
| SDRAMC_CR_TRAS(9) /* Command period (ACT to PRE) 42ns min */ | SDRAMC_CR_TRAS(9) /* Command period (ACT to PRE) 42ns min */
| SDRAMC_CR_TXSR(15U), /* Exit self-refresh to active time 70ns Min */ | SDRAMC_CR_TXSR(15U), /* Exit self-refresh to active time 70ns Min */
.sdramc_mdr = SDRAMC_MDR_MD_SDRAM, .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
.sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | SDRAMC_CFR1_TMRD(2) .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | SDRAMC_CFR1_TMRD(2),
.sdramc_lpr = 0
}; };
#elif defined ATSAM_SDRAM_IS42S16320F_7BL #elif defined ATSAM_SDRAM_IS42S16320F_7BL
@@ -71,7 +72,8 @@ const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
| SDRAMC_CR_TXSR(CLOCK_CYCLES_FROM_NS_MIN(67)), | SDRAMC_CR_TXSR(CLOCK_CYCLES_FROM_NS_MIN(67)),
.sdramc_mdr = SDRAMC_MDR_MD_SDRAM, .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
.sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
SDRAMC_CFR1_TMRD(CLOCK_CYCLES_FROM_NS_MIN(14)) SDRAMC_CFR1_TMRD(CLOCK_CYCLES_FROM_NS_MIN(14)),
.sdramc_lpr = 0
}; };
#elif defined ATSAM_SDRAM_MT48LC16M16A2P_6A #elif defined ATSAM_SDRAM_MT48LC16M16A2P_6A
@@ -104,7 +106,8 @@ const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
| SDRAMC_CR_TXSR(9), | SDRAMC_CR_TXSR(9),
.sdramc_mdr = SDRAMC_MDR_MD_SDRAM, .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
.sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
SDRAMC_CFR1_TMRD(2) SDRAMC_CFR1_TMRD(2),
.sdramc_lpr = 0
}; };
#elif ATSAM_MCK == 123000000 #elif ATSAM_MCK == 123000000
@@ -124,7 +127,8 @@ const struct BOARD_Sdram_Config BOARD_Sdram_Config = {
| SDRAMC_CR_TXSR(9), | SDRAMC_CR_TXSR(9),
.sdramc_mdr = SDRAMC_MDR_MD_SDRAM, .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
.sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
SDRAMC_CFR1_TMRD(2) SDRAMC_CFR1_TMRD(2),
.sdramc_lpr = 0
}; };
#else /* ATSAM_MCK unknown */ #else /* ATSAM_MCK unknown */