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2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>

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* cpu.c, m68302.h, rtems/score/cpu.h, rtems/score/m68k.h: Convert to
	using c99 fixed size types.
This commit is contained in:
Ralf Corsepius
2004-03-30 11:47:03 +00:00
parent 9a26317f87
commit d86bae84e6
6 changed files with 308 additions and 303 deletions
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5
cpukit/score/cpu/m68k/ChangeLog
View File

@@ -1,3 +1,8 @@
2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org>
* cpu.c, m68302.h, rtems/score/cpu.h, rtems/score/m68k.h: Convert to
using c99 fixed size types.
2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> 2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org>
* configure.ac: RTEMS_TOP([../../../..]). * configure.ac: RTEMS_TOP([../../../..]).

16
cpukit/score/cpu/m68k/cpu.c
View File

@@ -34,14 +34,14 @@ void _CPU_Initialize(
/* fill the isr redirect table with the code to place the format/id /* fill the isr redirect table with the code to place the format/id
onto the stack */ onto the stack */
unsigned32 slot; uint32_t slot;
for (slot = 0; slot < CPU_INTERRUPT_NUMBER_OF_VECTORS; slot++) for (slot = 0; slot < CPU_INTERRUPT_NUMBER_OF_VECTORS; slot++)
{ {
_CPU_ISR_jump_table[slot].move_a7 = M68K_MOVE_A7; _CPU_ISR_jump_table[slot].move_a7 = M68K_MOVE_A7;
_CPU_ISR_jump_table[slot].format_id = slot << 2; _CPU_ISR_jump_table[slot].format_id = slot << 2;
_CPU_ISR_jump_table[slot].jmp = M68K_JMP; _CPU_ISR_jump_table[slot].jmp = M68K_JMP;
_CPU_ISR_jump_table[slot].isr_handler = (unsigned32) 0xDEADDEAD; _CPU_ISR_jump_table[slot].isr_handler = (uint32_t ) 0xDEADDEAD;
} }
#endif /* M68K_HAS_VBR */ #endif /* M68K_HAS_VBR */
@@ -53,9 +53,9 @@ void _CPU_Initialize(
* _CPU_ISR_Get_level * _CPU_ISR_Get_level
*/ */
unsigned32 _CPU_ISR_Get_level( void ) uint32_t _CPU_ISR_Get_level( void )
{ {
unsigned32 level; uint32_t level;
m68k_get_interrupt_level( level ); m68k_get_interrupt_level( level );
@@ -68,7 +68,7 @@ unsigned32 _CPU_ISR_Get_level( void )
*/ */
void _CPU_ISR_install_raw_handler( void _CPU_ISR_install_raw_handler(
unsigned32 vector, uint32_t vector,
proc_ptr new_handler, proc_ptr new_handler,
proc_ptr *old_handler proc_ptr *old_handler
) )
@@ -108,8 +108,8 @@ void _CPU_ISR_install_raw_handler(
*/ */
*old_handler = (proc_ptr) _CPU_ISR_jump_table[vector].isr_handler; *old_handler = (proc_ptr) _CPU_ISR_jump_table[vector].isr_handler;
_CPU_ISR_jump_table[vector].isr_handler = (unsigned32) new_handler; _CPU_ISR_jump_table[vector].isr_handler = (uint32_t ) new_handler;
if ( (unsigned32) interrupt_table != 0xFFFFFFFF ) if ( (uint32_t ) interrupt_table != 0xFFFFFFFF )
interrupt_table[ vector ] = (proc_ptr) &_CPU_ISR_jump_table[vector]; interrupt_table[ vector ] = (proc_ptr) &_CPU_ISR_jump_table[vector];
#endif /* M68K_HAS_VBR */ #endif /* M68K_HAS_VBR */
} }
@@ -130,7 +130,7 @@ void _CPU_ISR_install_raw_handler(
*/ */
void _CPU_ISR_install_vector( void _CPU_ISR_install_vector(
unsigned32 vector, uint32_t vector,
proc_ptr new_handler, proc_ptr new_handler,
proc_ptr *old_handler proc_ptr *old_handler
) )

254
cpukit/score/cpu/m68k/m68302.h
View File

@@ -39,13 +39,13 @@
* BAR - Base Address Register * BAR - Base Address Register
* Section 2.7 * Section 2.7
*/ */
#define M302_BAR (*((volatile rtems_unsigned16 *) 0xf2)) #define M302_BAR (*((volatile uint16_t *) 0xf2))
/* /*
* SCR - System Control Register * SCR - System Control Register
* Section 3.8.1 * Section 3.8.1
*/ */
#define M302_SCR (*((volatile rtems_unsigned32 *) 0xf4)) #define M302_SCR (*((volatile uint32_t *) 0xf4))
/* /*
* SCR bits * SCR bits
*/ */
@@ -236,14 +236,14 @@ enum m68302_ivec_e {
* Then simply use pointer references (e.g. dram->count = 3). * Then simply use pointer references (e.g. dram->count = 3).
*/ */
typedef struct { typedef struct {
rtems_unsigned16 dram_high; /* DRAM high address and FC */ uint16_t dram_high; /* DRAM high address and FC */
rtems_unsigned16 dram_low; /* DRAM low address */ uint16_t dram_low; /* DRAM low address */
rtems_unsigned16 increment; /* increment step (bytes/row) */ uint16_t increment; /* increment step (bytes/row) */
rtems_unsigned16 count; /* RAM refresh cycle count (#rows) */ uint16_t count; /* RAM refresh cycle count (#rows) */
rtems_unsigned16 t_ptr_h; /* temporary refresh high addr & FC */ uint16_t t_ptr_h; /* temporary refresh high addr & FC */
rtems_unsigned16 t_ptr_l; /* temporary refresh low address */ uint16_t t_ptr_l; /* temporary refresh low address */
rtems_unsigned16 t_count; /* temporary refresh cycles count */ uint16_t t_count; /* temporary refresh cycles count */
rtems_unsigned16 res; /* reserved */ uint16_t res; /* reserved */
} m302_DRAM_refresh_t; } m302_DRAM_refresh_t;
@@ -275,9 +275,9 @@ typedef struct {
* Section 4.5.5 * Section 4.5.5
*/ */
typedef struct m302_SCC_bd { typedef struct m302_SCC_bd {
rtems_unsigned16 status; /* status and control */ uint16_t status; /* status and control */
rtems_unsigned16 length; /* data length */ uint16_t length; /* data length */
volatile rtems_unsigned8 *buffer; /* data buffer pointer */ volatile uint8_t *buffer; /* data buffer pointer */
} m302_SCC_bd_t; } m302_SCC_bd_t;
typedef struct { typedef struct {
@@ -297,21 +297,21 @@ typedef struct {
* portion of the SCC parameter RAM. * portion of the SCC parameter RAM.
*/ */
typedef struct { typedef struct {
rtems_unsigned8 rfcr; /* Rx Function Code */ uint8_t rfcr; /* Rx Function Code */
rtems_unsigned8 tfcr; /* Tx Function Code */ uint8_t tfcr; /* Tx Function Code */
rtems_unsigned16 mrblr; /* Maximum Rx Buffer Length */ uint16_t mrblr; /* Maximum Rx Buffer Length */
rtems_unsigned16 _rstate; /* Rx Internal State */ uint16_t _rstate; /* Rx Internal State */
rtems_unsigned8 res2; uint8_t res2;
rtems_unsigned8 rbd; /* Rx Internal Buffer Number */ uint8_t rbd; /* Rx Internal Buffer Number */
rtems_unsigned32 _rdptr; /* Rx Internal Data Pointer */ uint32_t _rdptr; /* Rx Internal Data Pointer */
rtems_unsigned16 _rcount; /* Rx Internal Byte Count */ uint16_t _rcount; /* Rx Internal Byte Count */
rtems_unsigned16 _rtmp; /* Rx Temp */ uint16_t _rtmp; /* Rx Temp */
rtems_unsigned16 _tstate; /* Tx Internal State */ uint16_t _tstate; /* Tx Internal State */
rtems_unsigned8 res7; uint8_t res7;
rtems_unsigned8 tbd; /* Tx Internal Buffer Number */ uint8_t tbd; /* Tx Internal Buffer Number */
rtems_unsigned32 _tdptr; /* Tx Internal Data Pointer */ uint32_t _tdptr; /* Tx Internal Data Pointer */
rtems_unsigned16 _tcount; /* Tx Internal Byte Count */ uint16_t _tcount; /* Tx Internal Byte Count */
rtems_unsigned16 _ttmp; /* Tx Temp */ uint16_t _ttmp; /* Tx Temp */
} m302_SCC_parameters_t; } m302_SCC_parameters_t;
/* /*
@@ -319,17 +319,17 @@ typedef struct {
* Section 4.5.11.3 * Section 4.5.11.3
*/ */
typedef struct { typedef struct {
rtems_unsigned16 max_idl; /* Maximum IDLE Characters (rx) */ uint16_t max_idl; /* Maximum IDLE Characters (rx) */
rtems_unsigned16 idlc; /* Temporary rx IDLE counter */ uint16_t idlc; /* Temporary rx IDLE counter */
rtems_unsigned16 brkcr; /* Break Count Register (tx) */ uint16_t brkcr; /* Break Count Register (tx) */
rtems_unsigned16 parec; /* Receive Parity Error Counter */ uint16_t parec; /* Receive Parity Error Counter */
rtems_unsigned16 frmec; /* Receive Framing Error Counter */ uint16_t frmec; /* Receive Framing Error Counter */
rtems_unsigned16 nosec; /* Receive Noise Counter */ uint16_t nosec; /* Receive Noise Counter */
rtems_unsigned16 brkec; /* Receive Break Condition Counter */ uint16_t brkec; /* Receive Break Condition Counter */
rtems_unsigned16 uaddr1; /* UART ADDRESS Character 1 */ uint16_t uaddr1; /* UART ADDRESS Character 1 */
rtems_unsigned16 uaddr2; /* UART ADDRESS Character 2 */ uint16_t uaddr2; /* UART ADDRESS Character 2 */
rtems_unsigned16 rccr; /* Receive Control Character Register */ uint16_t rccr; /* Receive Control Character Register */
rtems_unsigned16 character[8]; /* Control Characters 1 through 8*/ uint16_t character[8]; /* Control Characters 1 through 8*/
} m302_SCC_UartSpecific_t; } m302_SCC_UartSpecific_t;
/* /*
* This definition allows for the checking of receive buffers * This definition allows for the checking of receive buffers
@@ -388,27 +388,27 @@ typedef struct {
* c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC * c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC
*/ */
typedef struct { typedef struct {
rtems_unsigned16 rcrc_l; /* Temp Receive CRC Low */ uint16_t rcrc_l; /* Temp Receive CRC Low */
rtems_unsigned16 rcrc_h; /* Temp Receive CRC High */ uint16_t rcrc_h; /* Temp Receive CRC High */
rtems_unsigned16 c_mask_l; /* CRC Mask Low */ uint16_t c_mask_l; /* CRC Mask Low */
rtems_unsigned16 c_mask_h; /* CRC Mask High */ uint16_t c_mask_h; /* CRC Mask High */
rtems_unsigned16 tcrc_l; /* Temp Transmit CRC Low */ uint16_t tcrc_l; /* Temp Transmit CRC Low */
rtems_unsigned16 tcrc_h; /* Temp Transmit CRC High */ uint16_t tcrc_h; /* Temp Transmit CRC High */
rtems_unsigned16 disfc; /* Discard Frame Counter */ uint16_t disfc; /* Discard Frame Counter */
rtems_unsigned16 crcec; /* CRC Error Counter */ uint16_t crcec; /* CRC Error Counter */
rtems_unsigned16 abtsc; /* Abort Sequence Counter */ uint16_t abtsc; /* Abort Sequence Counter */
rtems_unsigned16 nmarc; /* Nonmatching Address Received Cntr */ uint16_t nmarc; /* Nonmatching Address Received Cntr */
rtems_unsigned16 retrc; /* Frame Retransmission Counter */ uint16_t retrc; /* Frame Retransmission Counter */
rtems_unsigned16 mflr; /* Maximum Frame Length Register */ uint16_t mflr; /* Maximum Frame Length Register */
rtems_unsigned16 max_cnt; /* Maximum_Length Counter */ uint16_t max_cnt; /* Maximum_Length Counter */
rtems_unsigned16 hmask; /* User Defined Frame Address Mask */ uint16_t hmask; /* User Defined Frame Address Mask */
rtems_unsigned16 haddr1; /* User Defined Frame Address */ uint16_t haddr1; /* User Defined Frame Address */
rtems_unsigned16 haddr2; /* " */ uint16_t haddr2; /* " */
rtems_unsigned16 haddr3; /* " */ uint16_t haddr3; /* " */
rtems_unsigned16 haddr4; /* " */ uint16_t haddr4; /* " */
} m302_SCC_HdlcSpecific_t; } m302_SCC_HdlcSpecific_t;
/* /*
* HDLC receiver buffer descriptor bit definitions * HDLC receiver buffer descriptor bit definitions
@@ -461,7 +461,7 @@ typedef struct {
m302_SCC_UartSpecific_t uart; m302_SCC_UartSpecific_t uart;
m302_SCC_HdlcSpecific_t hdlc; m302_SCC_HdlcSpecific_t hdlc;
} prot; } prot;
rtems_unsigned8 res[0x040]; /* +0C0 reserved, (not implemented) */ uint8_t res[0x040]; /* +0C0 reserved, (not implemented) */
} m302_SCC_t; } m302_SCC_t;
@@ -469,17 +469,17 @@ typedef struct {
* Common SCC Registers * Common SCC Registers
*/ */
typedef struct { typedef struct {
rtems_unsigned16 res1; uint16_t res1;
rtems_unsigned16 scon; /* SCC Configuration Register 4.5.2 */ uint16_t scon; /* SCC Configuration Register 4.5.2 */
rtems_unsigned16 scm; /* SCC Mode Register 4.5.3 */ uint16_t scm; /* SCC Mode Register 4.5.3 */
rtems_unsigned16 dsr; /* SCC Data Synchronization Register 4.5.4 */ uint16_t dsr; /* SCC Data Synchronization Register 4.5.4 */
rtems_unsigned8 scce; /* SCC Event Register 4.5.8.1 */ uint8_t scce; /* SCC Event Register 4.5.8.1 */
rtems_unsigned8 res2; uint8_t res2;
rtems_unsigned8 sccm; /* SCC Mask Register 4.5.8.2 */ uint8_t sccm; /* SCC Mask Register 4.5.8.2 */
rtems_unsigned8 res3; uint8_t res3;
rtems_unsigned8 sccs; /* SCC Status Register 4.5.8.3 */ uint8_t sccs; /* SCC Status Register 4.5.8.3 */
rtems_unsigned8 res4; uint8_t res4;
rtems_unsigned16 res5; uint16_t res5;
} m302_SCC_Registers_t; } m302_SCC_Registers_t;
/* /*
@@ -509,77 +509,77 @@ typedef struct {
*/ */
typedef struct { typedef struct {
/* offset +800 */ /* offset +800 */
rtems_unsigned16 res0; uint16_t res0;
rtems_unsigned16 cmr; /* IDMA Channel Mode Register */ uint16_t cmr; /* IDMA Channel Mode Register */
rtems_unsigned32 sapr; /* IDMA Source Address Pointer */ uint32_t sapr; /* IDMA Source Address Pointer */
rtems_unsigned32 dapr; /* IDMA Destination Address Pointer */ uint32_t dapr; /* IDMA Destination Address Pointer */
rtems_unsigned16 bcr; /* IDMA Byte Count Register */ uint16_t bcr; /* IDMA Byte Count Register */
rtems_unsigned8 csr; /* IDMA Channel Status Register */ uint8_t csr; /* IDMA Channel Status Register */
rtems_unsigned8 res1; uint8_t res1;
rtems_unsigned8 fcr; /* IDMA Function Code Register */ uint8_t fcr; /* IDMA Function Code Register */
rtems_unsigned8 res2; uint8_t res2;
/* offset +812 */ /* offset +812 */
rtems_unsigned16 gimr; /* Global Interrupt Mode Register */ uint16_t gimr; /* Global Interrupt Mode Register */
rtems_unsigned16 ipr; /* Interrupt Pending Register */ uint16_t ipr; /* Interrupt Pending Register */
rtems_unsigned16 imr; /* Interrupt Mask Register */ uint16_t imr; /* Interrupt Mask Register */
rtems_unsigned16 isr; /* Interrupt In-Service Register */ uint16_t isr; /* Interrupt In-Service Register */
rtems_unsigned16 res3; uint16_t res3;
rtems_unsigned16 res4; uint16_t res4;
/* offset +81e */ /* offset +81e */
rtems_unsigned16 pacnt; /* Port A Control Register */ uint16_t pacnt; /* Port A Control Register */
rtems_unsigned16 paddr; /* Port A Data Direction Register */ uint16_t paddr; /* Port A Data Direction Register */
rtems_unsigned16 padat; /* Port A Data Register */ uint16_t padat; /* Port A Data Register */
rtems_unsigned16 pbcnt; /* Port B Control Register */ uint16_t pbcnt; /* Port B Control Register */
rtems_unsigned16 pbddr; /* Port B Data Direction Register */ uint16_t pbddr; /* Port B Data Direction Register */
rtems_unsigned16 pbdat; /* Port B Data Register */ uint16_t pbdat; /* Port B Data Register */
rtems_unsigned16 res5; uint16_t res5;
/* offset +82c */ /* offset +82c */
rtems_unsigned16 res6; uint16_t res6;
rtems_unsigned16 res7; uint16_t res7;
rtems_unsigned16 br0; /* Base Register (CS0) */ uint16_t br0; /* Base Register (CS0) */
rtems_unsigned16 or0; /* Option Register (CS0) */ uint16_t or0; /* Option Register (CS0) */
rtems_unsigned16 br1; /* Base Register (CS1) */ uint16_t br1; /* Base Register (CS1) */
rtems_unsigned16 or1; /* Option Register (CS1) */ uint16_t or1; /* Option Register (CS1) */
rtems_unsigned16 br2; /* Base Register (CS2) */ uint16_t br2; /* Base Register (CS2) */
rtems_unsigned16 or2; /* Option Register (CS2) */ uint16_t or2; /* Option Register (CS2) */
rtems_unsigned16 br3; /* Base Register (CS3) */ uint16_t br3; /* Base Register (CS3) */
rtems_unsigned16 or3; /* Option Register (CS3) */ uint16_t or3; /* Option Register (CS3) */
/* offset +840 */ /* offset +840 */
rtems_unsigned16 tmr1; /* Timer Unit 1 Mode Register */ uint16_t tmr1; /* Timer Unit 1 Mode Register */
rtems_unsigned16 trr1; /* Timer Unit 1 Reference Register */ uint16_t trr1; /* Timer Unit 1 Reference Register */
rtems_unsigned16 tcr1; /* Timer Unit 1 Capture Register */ uint16_t tcr1; /* Timer Unit 1 Capture Register */
rtems_unsigned16 tcn1; /* Timer Unit 1 Counter */ uint16_t tcn1; /* Timer Unit 1 Counter */
rtems_unsigned8 res8; uint8_t res8;
rtems_unsigned8 ter1; /* Timer Unit 1 Event Register */ uint8_t ter1; /* Timer Unit 1 Event Register */
rtems_unsigned16 wrr; /* Watchdog Reference Register */ uint16_t wrr; /* Watchdog Reference Register */
rtems_unsigned16 wcn; /* Watchdog Counter */ uint16_t wcn; /* Watchdog Counter */
rtems_unsigned16 res9; uint16_t res9;
rtems_unsigned16 tmr2; /* Timer Unit 2 Mode Register */ uint16_t tmr2; /* Timer Unit 2 Mode Register */
rtems_unsigned16 trr2; /* Timer Unit 2 Reference Register */ uint16_t trr2; /* Timer Unit 2 Reference Register */
rtems_unsigned16 tcr2; /* Timer Unit 2 Capture Register */ uint16_t tcr2; /* Timer Unit 2 Capture Register */
rtems_unsigned16 tcn2; /* Timer Unit 2 Counter */ uint16_t tcn2; /* Timer Unit 2 Counter */
rtems_unsigned8 resa; uint8_t resa;
rtems_unsigned8 ter2; /* Timer Unit 2 Event Register */ uint8_t ter2; /* Timer Unit 2 Event Register */
rtems_unsigned16 resb; uint16_t resb;
rtems_unsigned16 resc; uint16_t resc;
rtems_unsigned16 resd; uint16_t resd;
/* offset +860 */ /* offset +860 */
rtems_unsigned8 cr; /* Command Register */ uint8_t cr; /* Command Register */
rtems_unsigned8 rese[0x1f]; uint8_t rese[0x1f];
/* offset +880, +890, +8a0 */ /* offset +880, +890, +8a0 */
m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */ m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */
/* offset +8b0 */ /* offset +8b0 */
rtems_unsigned16 spmode; /* SCP,SMC Mode and Clock Cntrl Reg */ uint16_t spmode; /* SCP,SMC Mode and Clock Cntrl Reg */
rtems_unsigned16 simask; /* Serial Interface Mask Register */ uint16_t simask; /* Serial Interface Mask Register */
rtems_unsigned16 simode; /* Serial Interface Mode Register */ uint16_t simode; /* Serial Interface Mode Register */
} m302_internalReg_t ; } m302_internalReg_t ;
@@ -589,12 +589,12 @@ typedef struct {
* Section 2.8 * Section 2.8
*/ */
typedef struct { typedef struct {
rtems_unsigned8 mem[0x240]; /* +000 User Data Memory */ uint8_t mem[0x240]; /* +000 User Data Memory */
rtems_unsigned8 res1[0x1c0]; /* +240 reserved, (not implemented) */ uint8_t res1[0x1c0]; /* +240 reserved, (not implemented) */
m302_SCC_t scc1; /* +400 SCC1 */ m302_SCC_t scc1; /* +400 SCC1 */
m302_SCC_t scc2; /* +500 SCC2 */ m302_SCC_t scc2; /* +500 SCC2 */
m302_SCC_t scc3; /* +600 SCC3 */ m302_SCC_t scc3; /* +600 SCC3 */
rtems_unsigned8 res2[0x100]; /* +700 reserved, (not implemented) */ uint8_t res2[0x100]; /* +700 reserved, (not implemented) */
m302_internalReg_t reg; /* +800 68302 Internal Registers */ m302_internalReg_t reg; /* +800 68302 Internal Registers */
} m302_dualPortRAM_t; } m302_dualPortRAM_t;

254
cpukit/score/cpu/m68k/rtems/m68k/m68302.h
View File

@@ -39,13 +39,13 @@
* BAR - Base Address Register * BAR - Base Address Register
* Section 2.7 * Section 2.7
*/ */
#define M302_BAR (*((volatile rtems_unsigned16 *) 0xf2)) #define M302_BAR (*((volatile uint16_t *) 0xf2))
/* /*
* SCR - System Control Register * SCR - System Control Register
* Section 3.8.1 * Section 3.8.1
*/ */
#define M302_SCR (*((volatile rtems_unsigned32 *) 0xf4)) #define M302_SCR (*((volatile uint32_t *) 0xf4))
/* /*
* SCR bits * SCR bits
*/ */
@@ -236,14 +236,14 @@ enum m68302_ivec_e {
* Then simply use pointer references (e.g. dram->count = 3). * Then simply use pointer references (e.g. dram->count = 3).
*/ */
typedef struct { typedef struct {
rtems_unsigned16 dram_high; /* DRAM high address and FC */ uint16_t dram_high; /* DRAM high address and FC */
rtems_unsigned16 dram_low; /* DRAM low address */ uint16_t dram_low; /* DRAM low address */
rtems_unsigned16 increment; /* increment step (bytes/row) */ uint16_t increment; /* increment step (bytes/row) */
rtems_unsigned16 count; /* RAM refresh cycle count (#rows) */ uint16_t count; /* RAM refresh cycle count (#rows) */
rtems_unsigned16 t_ptr_h; /* temporary refresh high addr & FC */ uint16_t t_ptr_h; /* temporary refresh high addr & FC */
rtems_unsigned16 t_ptr_l; /* temporary refresh low address */ uint16_t t_ptr_l; /* temporary refresh low address */
rtems_unsigned16 t_count; /* temporary refresh cycles count */ uint16_t t_count; /* temporary refresh cycles count */
rtems_unsigned16 res; /* reserved */ uint16_t res; /* reserved */
} m302_DRAM_refresh_t; } m302_DRAM_refresh_t;
@@ -275,9 +275,9 @@ typedef struct {
* Section 4.5.5 * Section 4.5.5
*/ */
typedef struct m302_SCC_bd { typedef struct m302_SCC_bd {
rtems_unsigned16 status; /* status and control */ uint16_t status; /* status and control */
rtems_unsigned16 length; /* data length */ uint16_t length; /* data length */
volatile rtems_unsigned8 *buffer; /* data buffer pointer */ volatile uint8_t *buffer; /* data buffer pointer */
} m302_SCC_bd_t; } m302_SCC_bd_t;
typedef struct { typedef struct {
@@ -297,21 +297,21 @@ typedef struct {
* portion of the SCC parameter RAM. * portion of the SCC parameter RAM.
*/ */
typedef struct { typedef struct {
rtems_unsigned8 rfcr; /* Rx Function Code */ uint8_t rfcr; /* Rx Function Code */
rtems_unsigned8 tfcr; /* Tx Function Code */ uint8_t tfcr; /* Tx Function Code */
rtems_unsigned16 mrblr; /* Maximum Rx Buffer Length */ uint16_t mrblr; /* Maximum Rx Buffer Length */
rtems_unsigned16 _rstate; /* Rx Internal State */ uint16_t _rstate; /* Rx Internal State */
rtems_unsigned8 res2; uint8_t res2;
rtems_unsigned8 rbd; /* Rx Internal Buffer Number */ uint8_t rbd; /* Rx Internal Buffer Number */
rtems_unsigned32 _rdptr; /* Rx Internal Data Pointer */ uint32_t _rdptr; /* Rx Internal Data Pointer */
rtems_unsigned16 _rcount; /* Rx Internal Byte Count */ uint16_t _rcount; /* Rx Internal Byte Count */
rtems_unsigned16 _rtmp; /* Rx Temp */ uint16_t _rtmp; /* Rx Temp */
rtems_unsigned16 _tstate; /* Tx Internal State */ uint16_t _tstate; /* Tx Internal State */
rtems_unsigned8 res7; uint8_t res7;
rtems_unsigned8 tbd; /* Tx Internal Buffer Number */ uint8_t tbd; /* Tx Internal Buffer Number */
rtems_unsigned32 _tdptr; /* Tx Internal Data Pointer */ uint32_t _tdptr; /* Tx Internal Data Pointer */
rtems_unsigned16 _tcount; /* Tx Internal Byte Count */ uint16_t _tcount; /* Tx Internal Byte Count */
rtems_unsigned16 _ttmp; /* Tx Temp */ uint16_t _ttmp; /* Tx Temp */
} m302_SCC_parameters_t; } m302_SCC_parameters_t;
/* /*
@@ -319,17 +319,17 @@ typedef struct {
* Section 4.5.11.3 * Section 4.5.11.3
*/ */
typedef struct { typedef struct {
rtems_unsigned16 max_idl; /* Maximum IDLE Characters (rx) */ uint16_t max_idl; /* Maximum IDLE Characters (rx) */
rtems_unsigned16 idlc; /* Temporary rx IDLE counter */ uint16_t idlc; /* Temporary rx IDLE counter */
rtems_unsigned16 brkcr; /* Break Count Register (tx) */ uint16_t brkcr; /* Break Count Register (tx) */
rtems_unsigned16 parec; /* Receive Parity Error Counter */ uint16_t parec; /* Receive Parity Error Counter */
rtems_unsigned16 frmec; /* Receive Framing Error Counter */ uint16_t frmec; /* Receive Framing Error Counter */
rtems_unsigned16 nosec; /* Receive Noise Counter */ uint16_t nosec; /* Receive Noise Counter */
rtems_unsigned16 brkec; /* Receive Break Condition Counter */ uint16_t brkec; /* Receive Break Condition Counter */
rtems_unsigned16 uaddr1; /* UART ADDRESS Character 1 */ uint16_t uaddr1; /* UART ADDRESS Character 1 */
rtems_unsigned16 uaddr2; /* UART ADDRESS Character 2 */ uint16_t uaddr2; /* UART ADDRESS Character 2 */
rtems_unsigned16 rccr; /* Receive Control Character Register */ uint16_t rccr; /* Receive Control Character Register */
rtems_unsigned16 character[8]; /* Control Characters 1 through 8*/ uint16_t character[8]; /* Control Characters 1 through 8*/
} m302_SCC_UartSpecific_t; } m302_SCC_UartSpecific_t;
/* /*
* This definition allows for the checking of receive buffers * This definition allows for the checking of receive buffers
@@ -388,27 +388,27 @@ typedef struct {
* c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC * c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC
*/ */
typedef struct { typedef struct {
rtems_unsigned16 rcrc_l; /* Temp Receive CRC Low */ uint16_t rcrc_l; /* Temp Receive CRC Low */
rtems_unsigned16 rcrc_h; /* Temp Receive CRC High */ uint16_t rcrc_h; /* Temp Receive CRC High */
rtems_unsigned16 c_mask_l; /* CRC Mask Low */ uint16_t c_mask_l; /* CRC Mask Low */
rtems_unsigned16 c_mask_h; /* CRC Mask High */ uint16_t c_mask_h; /* CRC Mask High */
rtems_unsigned16 tcrc_l; /* Temp Transmit CRC Low */ uint16_t tcrc_l; /* Temp Transmit CRC Low */
rtems_unsigned16 tcrc_h; /* Temp Transmit CRC High */ uint16_t tcrc_h; /* Temp Transmit CRC High */
rtems_unsigned16 disfc; /* Discard Frame Counter */ uint16_t disfc; /* Discard Frame Counter */
rtems_unsigned16 crcec; /* CRC Error Counter */ uint16_t crcec; /* CRC Error Counter */
rtems_unsigned16 abtsc; /* Abort Sequence Counter */ uint16_t abtsc; /* Abort Sequence Counter */
rtems_unsigned16 nmarc; /* Nonmatching Address Received Cntr */ uint16_t nmarc; /* Nonmatching Address Received Cntr */
rtems_unsigned16 retrc; /* Frame Retransmission Counter */ uint16_t retrc; /* Frame Retransmission Counter */
rtems_unsigned16 mflr; /* Maximum Frame Length Register */ uint16_t mflr; /* Maximum Frame Length Register */
rtems_unsigned16 max_cnt; /* Maximum_Length Counter */ uint16_t max_cnt; /* Maximum_Length Counter */
rtems_unsigned16 hmask; /* User Defined Frame Address Mask */ uint16_t hmask; /* User Defined Frame Address Mask */
rtems_unsigned16 haddr1; /* User Defined Frame Address */ uint16_t haddr1; /* User Defined Frame Address */
rtems_unsigned16 haddr2; /* " */ uint16_t haddr2; /* " */
rtems_unsigned16 haddr3; /* " */ uint16_t haddr3; /* " */
rtems_unsigned16 haddr4; /* " */ uint16_t haddr4; /* " */
} m302_SCC_HdlcSpecific_t; } m302_SCC_HdlcSpecific_t;
/* /*
* HDLC receiver buffer descriptor bit definitions * HDLC receiver buffer descriptor bit definitions
@@ -461,7 +461,7 @@ typedef struct {
m302_SCC_UartSpecific_t uart; m302_SCC_UartSpecific_t uart;
m302_SCC_HdlcSpecific_t hdlc; m302_SCC_HdlcSpecific_t hdlc;
} prot; } prot;
rtems_unsigned8 res[0x040]; /* +0C0 reserved, (not implemented) */ uint8_t res[0x040]; /* +0C0 reserved, (not implemented) */
} m302_SCC_t; } m302_SCC_t;
@@ -469,17 +469,17 @@ typedef struct {
* Common SCC Registers * Common SCC Registers
*/ */
typedef struct { typedef struct {
rtems_unsigned16 res1; uint16_t res1;
rtems_unsigned16 scon; /* SCC Configuration Register 4.5.2 */ uint16_t scon; /* SCC Configuration Register 4.5.2 */
rtems_unsigned16 scm; /* SCC Mode Register 4.5.3 */ uint16_t scm; /* SCC Mode Register 4.5.3 */
rtems_unsigned16 dsr; /* SCC Data Synchronization Register 4.5.4 */ uint16_t dsr; /* SCC Data Synchronization Register 4.5.4 */
rtems_unsigned8 scce; /* SCC Event Register 4.5.8.1 */ uint8_t scce; /* SCC Event Register 4.5.8.1 */
rtems_unsigned8 res2; uint8_t res2;
rtems_unsigned8 sccm; /* SCC Mask Register 4.5.8.2 */ uint8_t sccm; /* SCC Mask Register 4.5.8.2 */
rtems_unsigned8 res3; uint8_t res3;
rtems_unsigned8 sccs; /* SCC Status Register 4.5.8.3 */ uint8_t sccs; /* SCC Status Register 4.5.8.3 */
rtems_unsigned8 res4; uint8_t res4;
rtems_unsigned16 res5; uint16_t res5;
} m302_SCC_Registers_t; } m302_SCC_Registers_t;
/* /*
@@ -509,77 +509,77 @@ typedef struct {
*/ */
typedef struct { typedef struct {
/* offset +800 */ /* offset +800 */
rtems_unsigned16 res0; uint16_t res0;
rtems_unsigned16 cmr; /* IDMA Channel Mode Register */ uint16_t cmr; /* IDMA Channel Mode Register */
rtems_unsigned32 sapr; /* IDMA Source Address Pointer */ uint32_t sapr; /* IDMA Source Address Pointer */
rtems_unsigned32 dapr; /* IDMA Destination Address Pointer */ uint32_t dapr; /* IDMA Destination Address Pointer */
rtems_unsigned16 bcr; /* IDMA Byte Count Register */ uint16_t bcr; /* IDMA Byte Count Register */
rtems_unsigned8 csr; /* IDMA Channel Status Register */ uint8_t csr; /* IDMA Channel Status Register */
rtems_unsigned8 res1; uint8_t res1;
rtems_unsigned8 fcr; /* IDMA Function Code Register */ uint8_t fcr; /* IDMA Function Code Register */
rtems_unsigned8 res2; uint8_t res2;
/* offset +812 */ /* offset +812 */
rtems_unsigned16 gimr; /* Global Interrupt Mode Register */ uint16_t gimr; /* Global Interrupt Mode Register */
rtems_unsigned16 ipr; /* Interrupt Pending Register */ uint16_t ipr; /* Interrupt Pending Register */
rtems_unsigned16 imr; /* Interrupt Mask Register */ uint16_t imr; /* Interrupt Mask Register */
rtems_unsigned16 isr; /* Interrupt In-Service Register */ uint16_t isr; /* Interrupt In-Service Register */
rtems_unsigned16 res3; uint16_t res3;
rtems_unsigned16 res4; uint16_t res4;
/* offset +81e */ /* offset +81e */
rtems_unsigned16 pacnt; /* Port A Control Register */ uint16_t pacnt; /* Port A Control Register */
rtems_unsigned16 paddr; /* Port A Data Direction Register */ uint16_t paddr; /* Port A Data Direction Register */
rtems_unsigned16 padat; /* Port A Data Register */ uint16_t padat; /* Port A Data Register */
rtems_unsigned16 pbcnt; /* Port B Control Register */ uint16_t pbcnt; /* Port B Control Register */
rtems_unsigned16 pbddr; /* Port B Data Direction Register */ uint16_t pbddr; /* Port B Data Direction Register */
rtems_unsigned16 pbdat; /* Port B Data Register */ uint16_t pbdat; /* Port B Data Register */
rtems_unsigned16 res5; uint16_t res5;
/* offset +82c */ /* offset +82c */
rtems_unsigned16 res6; uint16_t res6;
rtems_unsigned16 res7; uint16_t res7;
rtems_unsigned16 br0; /* Base Register (CS0) */ uint16_t br0; /* Base Register (CS0) */
rtems_unsigned16 or0; /* Option Register (CS0) */ uint16_t or0; /* Option Register (CS0) */
rtems_unsigned16 br1; /* Base Register (CS1) */ uint16_t br1; /* Base Register (CS1) */
rtems_unsigned16 or1; /* Option Register (CS1) */ uint16_t or1; /* Option Register (CS1) */
rtems_unsigned16 br2; /* Base Register (CS2) */ uint16_t br2; /* Base Register (CS2) */
rtems_unsigned16 or2; /* Option Register (CS2) */ uint16_t or2; /* Option Register (CS2) */
rtems_unsigned16 br3; /* Base Register (CS3) */ uint16_t br3; /* Base Register (CS3) */
rtems_unsigned16 or3; /* Option Register (CS3) */ uint16_t or3; /* Option Register (CS3) */
/* offset +840 */ /* offset +840 */
rtems_unsigned16 tmr1; /* Timer Unit 1 Mode Register */ uint16_t tmr1; /* Timer Unit 1 Mode Register */
rtems_unsigned16 trr1; /* Timer Unit 1 Reference Register */ uint16_t trr1; /* Timer Unit 1 Reference Register */
rtems_unsigned16 tcr1; /* Timer Unit 1 Capture Register */ uint16_t tcr1; /* Timer Unit 1 Capture Register */
rtems_unsigned16 tcn1; /* Timer Unit 1 Counter */ uint16_t tcn1; /* Timer Unit 1 Counter */
rtems_unsigned8 res8; uint8_t res8;
rtems_unsigned8 ter1; /* Timer Unit 1 Event Register */ uint8_t ter1; /* Timer Unit 1 Event Register */
rtems_unsigned16 wrr; /* Watchdog Reference Register */ uint16_t wrr; /* Watchdog Reference Register */
rtems_unsigned16 wcn; /* Watchdog Counter */ uint16_t wcn; /* Watchdog Counter */
rtems_unsigned16 res9; uint16_t res9;
rtems_unsigned16 tmr2; /* Timer Unit 2 Mode Register */ uint16_t tmr2; /* Timer Unit 2 Mode Register */
rtems_unsigned16 trr2; /* Timer Unit 2 Reference Register */ uint16_t trr2; /* Timer Unit 2 Reference Register */
rtems_unsigned16 tcr2; /* Timer Unit 2 Capture Register */ uint16_t tcr2; /* Timer Unit 2 Capture Register */
rtems_unsigned16 tcn2; /* Timer Unit 2 Counter */ uint16_t tcn2; /* Timer Unit 2 Counter */
rtems_unsigned8 resa; uint8_t resa;
rtems_unsigned8 ter2; /* Timer Unit 2 Event Register */ uint8_t ter2; /* Timer Unit 2 Event Register */
rtems_unsigned16 resb; uint16_t resb;
rtems_unsigned16 resc; uint16_t resc;
rtems_unsigned16 resd; uint16_t resd;
/* offset +860 */ /* offset +860 */
rtems_unsigned8 cr; /* Command Register */ uint8_t cr; /* Command Register */
rtems_unsigned8 rese[0x1f]; uint8_t rese[0x1f];
/* offset +880, +890, +8a0 */ /* offset +880, +890, +8a0 */
m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */ m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */
/* offset +8b0 */ /* offset +8b0 */
rtems_unsigned16 spmode; /* SCP,SMC Mode and Clock Cntrl Reg */ uint16_t spmode; /* SCP,SMC Mode and Clock Cntrl Reg */
rtems_unsigned16 simask; /* Serial Interface Mask Register */ uint16_t simask; /* Serial Interface Mask Register */
rtems_unsigned16 simode; /* Serial Interface Mode Register */ uint16_t simode; /* Serial Interface Mode Register */
} m302_internalReg_t ; } m302_internalReg_t ;
@@ -589,12 +589,12 @@ typedef struct {
* Section 2.8 * Section 2.8
*/ */
typedef struct { typedef struct {
rtems_unsigned8 mem[0x240]; /* +000 User Data Memory */ uint8_t mem[0x240]; /* +000 User Data Memory */
rtems_unsigned8 res1[0x1c0]; /* +240 reserved, (not implemented) */ uint8_t res1[0x1c0]; /* +240 reserved, (not implemented) */
m302_SCC_t scc1; /* +400 SCC1 */ m302_SCC_t scc1; /* +400 SCC1 */
m302_SCC_t scc2; /* +500 SCC2 */ m302_SCC_t scc2; /* +500 SCC2 */
m302_SCC_t scc3; /* +600 SCC3 */ m302_SCC_t scc3; /* +600 SCC3 */
rtems_unsigned8 res2[0x100]; /* +700 reserved, (not implemented) */ uint8_t res2[0x100]; /* +700 reserved, (not implemented) */
m302_internalReg_t reg; /* +800 68302 Internal Registers */ m302_internalReg_t reg; /* +800 68302 Internal Registers */
} m302_dualPortRAM_t; } m302_dualPortRAM_t;

72
cpukit/score/cpu/m68k/rtems/score/cpu.h
View File

@@ -105,13 +105,13 @@ extern "C" {
*/ */
typedef struct { typedef struct {
unsigned32 sr; /* (sr) status register */ uint32_t sr; /* (sr) status register */
unsigned32 d2; /* (d2) data register 2 */ uint32_t d2; /* (d2) data register 2 */
unsigned32 d3; /* (d3) data register 3 */ uint32_t d3; /* (d3) data register 3 */
unsigned32 d4; /* (d4) data register 4 */ uint32_t d4; /* (d4) data register 4 */
unsigned32 d5; /* (d5) data register 5 */ uint32_t d5; /* (d5) data register 5 */
unsigned32 d6; /* (d6) data register 6 */ uint32_t d6; /* (d6) data register 6 */
unsigned32 d7; /* (d7) data register 7 */ uint32_t d7; /* (d7) data register 7 */
void *a2; /* (a2) address register 2 */ void *a2; /* (a2) address register 2 */
void *a3; /* (a3) address register 3 */ void *a3; /* (a3) address register 3 */
void *a4; /* (a4) address register 4 */ void *a4; /* (a4) address register 4 */
@@ -134,12 +134,12 @@ typedef struct {
*/ */
typedef struct { typedef struct {
unsigned16 _exception_bits; uint16_t _exception_bits;
unsigned16 _trap_enable_bits; uint16_t _trap_enable_bits;
unsigned16 _sticky_bits; uint16_t _sticky_bits;
unsigned16 _rounding_mode; uint16_t _rounding_mode;
unsigned16 _format; uint16_t _format;
unsigned16 _last_operation; uint16_t _last_operation;
union { union {
float sf; float sf;
double df; double df;
@@ -157,7 +157,7 @@ typedef struct {
*/ */
typedef struct { typedef struct {
unsigned8 fp_save_area[332]; /* 216 bytes for FSAVE/FRESTORE */ uint8_t fp_save_area[332]; /* 216 bytes for FSAVE/FRESTORE */
/* 96 bytes for FMOVEM FP0-7 */ /* 96 bytes for FMOVEM FP0-7 */
/* 12 bytes for FMOVEM CREGS */ /* 12 bytes for FMOVEM CREGS */
/* 4 bytes for non-null flag */ /* 4 bytes for non-null flag */
@@ -172,15 +172,15 @@ typedef struct {
*/ */
typedef struct { typedef struct {
unsigned32 vecnum; /* vector number */ uint32_t vecnum; /* vector number */
} CPU_Interrupt_frame; } CPU_Interrupt_frame;
typedef struct { typedef struct {
unsigned32 vecnum; /* vector number */ uint32_t vecnum; /* vector number */
unsigned32 sr; /* status register */ uint32_t sr; /* status register */
unsigned32 pc; /* program counter */ uint32_t pc; /* program counter */
unsigned32 d0, d1, d2, d3, d4, d5, d6, d7; uint32_t d0, d1, d2, d3, d4, d5, d6, d7;
unsigned32 a0, a1, a2, a3, a4, a5, a6, a7; uint32_t a0, a1, a2, a3, a4, a5, a6, a7;
} CPU_Exception_frame; } CPU_Exception_frame;
/* /*
@@ -194,10 +194,10 @@ typedef struct {
void (*postdriver_hook)( void ); void (*postdriver_hook)( void );
void (*idle_task)( void ); void (*idle_task)( void );
boolean do_zero_of_workspace; boolean do_zero_of_workspace;
unsigned32 idle_task_stack_size; uint32_t idle_task_stack_size;
unsigned32 interrupt_stack_size; uint32_t interrupt_stack_size;
unsigned32 extra_mpci_receive_server_stack; uint32_t extra_mpci_receive_server_stack;
void * (*stack_allocate_hook)( unsigned32 ); void * (*stack_allocate_hook)( uint32_t );
void (*stack_free_hook)( void* ); void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */ /* end of fields required on all CPUs */
@@ -236,10 +236,10 @@ extern char _VBR[];
*/ */
typedef struct { typedef struct {
unsigned16 move_a7; /* move #FORMAT_ID,%a7@- */ uint16_t move_a7; /* move #FORMAT_ID,%a7@- */
unsigned16 format_id; uint16_t format_id;
unsigned16 jmp; /* jmp _ISR_Handlers */ uint16_t jmp; /* jmp _ISR_Handlers */
unsigned32 isr_handler; uint32_t isr_handler;
} _CPU_ISR_handler_entry; } _CPU_ISR_handler_entry;
#define M68K_MOVE_A7 0x3F3C #define M68K_MOVE_A7 0x3F3C
@@ -337,7 +337,7 @@ SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
#define _CPU_ISR_Set_level( _newlevel ) \ #define _CPU_ISR_Set_level( _newlevel ) \
m68k_set_interrupt_level( _newlevel ) m68k_set_interrupt_level( _newlevel )
unsigned32 _CPU_ISR_Get_level( void ); uint32_t _CPU_ISR_Get_level( void );
/* end of ISR handler macros */ /* end of ISR handler macros */
@@ -354,10 +354,10 @@ unsigned32 _CPU_ISR_Get_level( void );
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
_isr, _entry_point, _is_fp ) \ _isr, _entry_point, _is_fp ) \
do { \ do { \
unsigned32 _stack; \ uint32_t _stack; \
\ \
(_the_context)->sr = 0x3000 | ((_isr) << 8); \ (_the_context)->sr = 0x3000 | ((_isr) << 8); \
_stack = (unsigned32)(_stack_base) + (_size) - 4; \ _stack = (uint32_t )(_stack_base) + (_size) - 4; \
(_the_context)->a7_msp = (void *)_stack; \ (_the_context)->a7_msp = (void *)_stack; \
*(void **)_stack = (void *)(_entry_point); \ *(void **)_stack = (void *)(_entry_point); \
} while ( 0 ) } while ( 0 )
@@ -407,10 +407,10 @@ unsigned32 _CPU_ISR_Get_level( void );
) )
#define _CPU_Context_Initialize_fp( _fp_area ) \ #define _CPU_Context_Initialize_fp( _fp_area ) \
{ unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \ { uint32_t *_fp_context = (uint32_t *)*(_fp_area); \
\ \
*(--(_fp_context)) = 0; \ *(--(_fp_context)) = 0; \
*(_fp_area) = (unsigned8 *)(_fp_context); \ *(_fp_area) = (uint8_t *)(_fp_context); \
} }
#endif #endif
@@ -586,7 +586,7 @@ void _CPU_Initialize(
*/ */
void _CPU_ISR_install_raw_handler( void _CPU_ISR_install_raw_handler(
unsigned32 vector, uint32_t vector,
proc_ptr new_handler, proc_ptr new_handler,
proc_ptr *old_handler proc_ptr *old_handler
); );
@@ -598,7 +598,7 @@ void _CPU_ISR_install_raw_handler(
*/ */
void _CPU_ISR_install_vector( void _CPU_ISR_install_vector(
unsigned32 vector, uint32_t vector,
proc_ptr new_handler, proc_ptr new_handler,
proc_ptr *old_handler proc_ptr *old_handler
); );
@@ -671,7 +671,7 @@ void _CPU_Context_restore_fp(
void M68KFPSPInstallExceptionHandlers (void); void M68KFPSPInstallExceptionHandlers (void);
SCORE_EXTERN int (*_FPSP_install_raw_handler)( SCORE_EXTERN int (*_FPSP_install_raw_handler)(
unsigned32 vector, uint32_t vector,
proc_ptr new_handler, proc_ptr new_handler,
proc_ptr *old_handler proc_ptr *old_handler
); );

10
cpukit/score/cpu/m68k/rtems/score/m68k.h
View File

@@ -256,7 +256,7 @@ extern "C" {
#if ( M68K_COLDFIRE_ARCH == 1 ) #if ( M68K_COLDFIRE_ARCH == 1 )
#define m68k_disable_interrupts( _level ) \ #define m68k_disable_interrupts( _level ) \
do { register unsigned32 _tmpsr = 0x0700; \ do { register uint32_t _tmpsr = 0x0700; \
asm volatile ( "move.w %%sr,%0\n\t" \ asm volatile ( "move.w %%sr,%0\n\t" \
"or.l %0,%1\n\t" \ "or.l %0,%1\n\t" \
"move.w %1,%%sr" \ "move.w %1,%%sr" \
@@ -274,7 +274,7 @@ extern "C" {
#if ( M68K_COLDFIRE_ARCH == 1 ) #if ( M68K_COLDFIRE_ARCH == 1 )
#define m68k_flash_interrupts( _level ) \ #define m68k_flash_interrupts( _level ) \
do { register unsigned32 _tmpsr = 0x0700; \ do { register uint32_t _tmpsr = 0x0700; \
asm volatile ( "move.w %2,%%sr\n\t" \ asm volatile ( "move.w %2,%%sr\n\t" \
"or.l %2,%1\n\t" \ "or.l %2,%1\n\t" \
"move.w %1,%%sr" \ "move.w %1,%%sr" \
@@ -289,7 +289,7 @@ extern "C" {
#define m68k_get_interrupt_level( _level ) \ #define m68k_get_interrupt_level( _level ) \
do { \ do { \
register unsigned32 _tmpsr; \ register uint32_t _tmpsr; \
\ \
asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
_level = (_tmpsr & 0x0700) >> 8; \ _level = (_tmpsr & 0x0700) >> 8; \
@@ -297,7 +297,7 @@ extern "C" {
#define m68k_set_interrupt_level( _newlevel ) \ #define m68k_set_interrupt_level( _newlevel ) \
do { \ do { \
register unsigned32 _tmpsr; \ register uint32_t _tmpsr; \
\ \
asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
_tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \ _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
@@ -339,7 +339,7 @@ static inline unsigned int m68k_swap_u32(
unsigned int value unsigned int value
) )
{ {
unsigned32 byte1, byte2, byte3, byte4, swapped; uint32_t byte1, byte2, byte3, byte4, swapped;
byte4 = (value >> 24) & 0xff; byte4 = (value >> 24) & 0xff;
byte3 = (value >> 16) & 0xff; byte3 = (value >> 16) & 0xff;