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2005-02-13 Ralf Corsepius <ralf.corsepius@rtems.org>

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* rtems/old-exceptions/cpu.h: Add _PPC_MSR_DISABLE_MASK.
	Use _PPC_MSR_DISABLE_MASK instead of PPC_MSR_DISABLE_MASK to set up
	_disable_mask.
This commit is contained in:
Ralf Corsepius
2005-02-13 07:33:35 +00:00
parent 9dc84b5706
commit d3fcd2b0ec
2 changed files with 11 additions and 3 deletions
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6
cpukit/score/cpu/powerpc/ChangeLog
View File

@@ -1,3 +1,9 @@
2005-02-13 Ralf Corsepius <ralf.corsepius@rtems.org>
* rtems/old-exceptions/cpu.h: Add _PPC_MSR_DISABLE_MASK.
Use _PPC_MSR_DISABLE_MASK instead of PPC_MSR_DISABLE_MASK to set up
_disable_mask.
2005-02-12 Ralf Corsepius <ralf.corsepius@rtems.org> 2005-02-12 Ralf Corsepius <ralf.corsepius@rtems.org>
* cpu.c: New (Stub file for consistency with other ports). * cpu.c: New (Stub file for consistency with other ports).

8
cpukit/score/cpu/powerpc/rtems/old-exceptions/cpu.h
View File

@@ -683,6 +683,8 @@ void _CPU_Initialize_vectors(void);
*/ */
#ifndef ASM #ifndef ASM
extern const unsigned int _PPC_MSR_DISABLE_MASK;
#define _CPU_MSR_Value( _msr_value ) \ #define _CPU_MSR_Value( _msr_value ) \
do { \ do { \
_msr_value = 0; \ _msr_value = 0; \
@@ -694,7 +696,7 @@ void _CPU_Initialize_vectors(void);
#if 0 #if 0
#define _CPU_ISR_Disable( _isr_cookie ) \ #define _CPU_ISR_Disable( _isr_cookie ) \
{ register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \ { register unsigned int _disable_mask = _PPC_MSR_DISABLE_MASK; \
_isr_cookie = 0; \ _isr_cookie = 0; \
asm volatile ( asm volatile (
"mfmsr %0" : \ "mfmsr %0" : \
@@ -715,7 +717,7 @@ void _CPU_Initialize_vectors(void);
#endif #endif
#define _CPU_ISR_Disable( _isr_cookie ) \ #define _CPU_ISR_Disable( _isr_cookie ) \
{ register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \ { register unsigned int _disable_mask = _PPC_MSR_DISABLE_MASK; \
_isr_cookie = 0; \ _isr_cookie = 0; \
asm volatile ( \ asm volatile ( \
"mfmsr %0; andc %1,%0,%1; mtmsr %1" : \ "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
@@ -753,7 +755,7 @@ void _CPU_Initialize_vectors(void);
#ifndef ASM #ifndef ASM
#define _CPU_ISR_Flash( _isr_cookie ) \ #define _CPU_ISR_Flash( _isr_cookie ) \
{ register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \ { register unsigned int _disable_mask = _PPC_MSR_DISABLE_MASK; \
asm volatile ( \ asm volatile ( \
"mtmsr %0; andc %1,%0,%1; mtmsr %1" : \ "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
"=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \ "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \