mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2025-12-05 15:15:44 +00:00
updated mvme162 code from Misha (mms@eiscathq.irf.se)
This commit is contained in:
Joel Sherrill
@@ -112,6 +112,14 @@ parser;
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crossgcc mailing list
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- to FSF and Cygnus Support for great free software;
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What's new
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----------
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- 28.07.95 BSP adjusted to rtems-3.2.0.
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- Now console driver uses interrupts on receive (ring buffer
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code lifted with thanks from the IDP BSP next door (../idp))
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- both front-panel serial interfaces are supported
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- serious bug in timer interrupts fixed
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- interrupt test tm27 now supported
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+----------------------------------+-------------------------------+
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| Dr. Mikhail (Misha) Savitski | Voice : +46-980-79162 |
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@@ -35,8 +35,7 @@
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#define CLOCK_INT_LEVEL 6 /* T2's interrupt level */
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rtems_unsigned32 Clock_isrs; /* ISRs until next tick */
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volatile rtems_unsigned32 Clock_driver_ticks;
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/* ticks since initialization */
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volatile rtems_unsigned32 Clock_driver_ticks; /* ticks since initialization */
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rtems_isr_entry Old_ticker;
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rtems_device_driver Clock_initialize(
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@@ -50,32 +49,30 @@ rtems_device_driver Clock_initialize(
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Install_clock( Clock_isr );
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}
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void ReInstall_clock( clock_isr )
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rtems_isr_entry clock_isr;
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void ReInstall_clock(rtems_isr_entry clock_isr)
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{
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rtems_unsigned32 isrlevel;
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rtems_interrupt_disable( isrlevel );
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(void) set_vector( clock_isr, (VECTOR_BASE >> 28) * 0x10 + 0x9, 1 );
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(void) set_vector( clock_isr, VBR0 * 0x10 + 0x9, 1 );
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rtems_interrupt_enable( isrlevel );
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}
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void Install_clock( clock_isr )
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rtems_isr_entry clock_isr;
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void Install_clock(rtems_isr_entry clock_isr )
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{
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Clock_driver_ticks = 0;
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Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
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if ( BSP_Configuration.ticks_per_timeslice ) {
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Old_ticker = (rtems_isr_entry)
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set_vector( clock_isr, (VECTOR_BASE >> 28) * 0x10 + 0x9, 1 );
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lcsr->vector_base = 0x67800000; /* set vb, enable interrupts */
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Old_ticker =
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(rtems_isr_entry) set_vector( clock_isr, VBR0 * 0x10 + 0x9, 1 );
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lcsr->vector_base |= MASK_INT; /* unmask VMEchip2 interrupts */
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lcsr->to_ctl = 0xE7; /* prescaler to 1 MHz (see Appendix A1) */
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lcsr->timer_cmp_2 = MS_COUNT;
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lcsr->timer_cnt_2 = 0; /* clear counter */
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lcsr->board_ctl |= 0x700; /* increment, reset-on-compare, clear-ovfl-cnt */
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lcsr->board_ctl |= 0x700; /* increment, reset-on-compare, and */
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/* clear-overflow-cnt */
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lcsr->intr_level[0] |= CLOCK_INT_LEVEL * 0x10; /* set int level */
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lcsr->intr_ena |= 0x02000000; /* enable tick timer 2 interrupt */
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@@ -24,18 +24,33 @@
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#include <rtems.h>
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#include "console.h"
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#include "bsp.h"
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#include "ringbuf.h"
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/* console_initialize
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*
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* This routine initializes the console IO driver.
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*
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* Input parameters: NONE
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*
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* Output parameters: NONE
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*
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* Return values:
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Ring_buffer_t Buffer[2];
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/*
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* Interrupt handler for receiver interrupts
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*/
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rtems_isr C_Receive_ISR(rtems_vector_number vector)
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{
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register int ipend, port;
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ZWRITE0(1, 0x38); /* reset highest IUS */
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ipend = ZREAD(1, 3); /* read int pending from A side */
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if (ipend == 0x04) port = 0; /* channel B intr pending */
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else if (ipend == 0x20) port = 1; /* channel A intr pending */
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else return;
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Ring_buffer_Add_character(&Buffer[port], ZREADD(port));
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if (ZREAD(port, 1) & 0x70) { /* check error stat */
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ZWRITE0(port, 0x30); /* reset error */
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}
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}
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rtems_device_driver console_initialize(
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rtems_device_major_number major,
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rtems_device_minor_number minor,
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@@ -44,122 +59,82 @@ rtems_device_driver console_initialize(
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rtems_unsigned32 *status
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)
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{
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int i;
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/*
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* Initialise receiver interrupts on both ports
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*/
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for (i = 0; i <= 1; i++) {
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Ring_buffer_Initialize( &Buffer[i] );
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ZWRITE(i, 2, SCC_VECTOR);
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ZWRITE(i, 10, 0);
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ZWRITE(i, 1, 0x10); /* int on all Rx chars or special condition */
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ZWRITE(i, 9, 8); /* master interrupt enable */
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}
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set_vector(C_Receive_ISR, SCC_VECTOR, 1); /* install ISR for ports A and B */
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mcchip->vector_base = 0;
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mcchip->gen_control = 2; /* MIEN */
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mcchip->SCC_int_ctl = 0x13; /* SCC IEN, IPL3 */
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*status = RTEMS_SUCCESSFUL;
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}
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/* is_character_ready
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*
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* This routine returns TRUE if a character is available.
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*
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* Input parameters: NONE
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*
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* Output parameters: NONE
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*
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* Return values:
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/*
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* Non-blocking char input
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*/
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rtems_boolean is_character_ready(
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char *ch
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)
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rtems_boolean char_ready(int port, char *ch)
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{
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rtems_unsigned8 rr_0;
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if ( Ring_buffer_Is_empty( &Buffer[port] ) )
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return FALSE;
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Z8x30_READ_CONTROL( CONSOLE_CONTROL, RR_0, rr_0 );
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if ( !(rr_0 & RR_0_RX_DATA_AVAILABLE) )
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return( FALSE );
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Ring_buffer_Remove_character( &Buffer[port], *ch );
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Z8x30_READ_DATA( CONSOLE_DATA, *ch );
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return(TRUE);
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}
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/* inbyte
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*
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* This routine reads a character from the SCC.
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*
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* Input parameters: NONE
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*
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* Output parameters: NONE
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*
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* Return values:
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* character read from SCC
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*/
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char inbyte( void )
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{
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rtems_unsigned8 rr_0;
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char ch;
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while ( 1 ) {
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Z8x30_READ_CONTROL( CONSOLE_CONTROL, RR_0, rr_0 );
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if ( (rr_0 & RR_0_RX_DATA_AVAILABLE) != 0 )
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break;
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}
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Z8x30_READ_DATA( CONSOLE_DATA, ch );
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return ch;
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}
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/* outbyte
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*
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* This routine transmits a character out the SCC. It supports
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* XON/XOFF flow control.
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*
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* Input parameters:
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* ch - character to be transmitted
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*
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* Output parameters: NONE
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*/
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void outbyte(
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char ch
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)
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{
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rtems_unsigned8 rr_0;
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char flow_control;
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while ( 1 ) {
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Z8x30_READ_CONTROL( CONSOLE_CONTROL, RR_0, rr_0 );
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if ( (rr_0 & RR_0_TX_BUFFER_EMPTY) != 0 )
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break;
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}
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while ( 1 ) {
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Z8x30_READ_CONTROL( CONSOLE_CONTROL, RR_0, rr_0 );
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if ( (rr_0 & RR_0_RX_DATA_AVAILABLE) == 0 )
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break;
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Z8x30_READ_DATA( CONSOLE_DATA, flow_control );
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if ( flow_control == XOFF )
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do {
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do {
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Z8x30_READ_CONTROL( CONSOLE_CONTROL, RR_0, rr_0 );
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} while ( (rr_0 & RR_0_RX_DATA_AVAILABLE) == 0 );
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Z8x30_READ_DATA( CONSOLE_DATA, flow_control );
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} while ( flow_control != XON );
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}
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Z8x30_WRITE_DATA( CONSOLE_DATA, ch );
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return TRUE;
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}
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/*
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* __read -- read bytes from the serial port. Ignore fd, since
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* we only have stdin.
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* Block on char input
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*/
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int __read(
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int fd,
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char *buf,
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int nbytes
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)
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char char_wait(int port)
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{
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int i = 0;
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unsigned char tmp_char;
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while ( !char_ready(port, &tmp_char) );
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return tmp_char;
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}
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/*
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* This routine transmits a character out the SCC. It no longer supports
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* XON/XOFF flow control.
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*/
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void char_put(int port, char ch)
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{
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while (1) {
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if (ZREAD0(port) & TX_BUFFER_EMPTY) break;
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}
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ZWRITED(port, ch);
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}
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/*
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* Map port A (1) to stdin, stdout, and stderr.
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* Map everything else to port B (0).
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*/
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int __read(int fd, char *buf, int nbytes)
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{
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int i, port;
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if ( fd <= 2 ) port = 1;
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else port = 0;
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for (i = 0; i < nbytes; i++) {
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*(buf + i) = inbyte();
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*(buf + i) = char_wait(port);
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if ((*(buf + i) == '\n') || (*(buf + i) == '\r')) {
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(*(buf + i++)) = '\n';
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(*(buf + i)) = 0;
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@@ -170,24 +145,22 @@ int __read(
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}
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/*
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* __write -- write bytes to the serial port. Ignore fd, since
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* stdout and stderr are the same. Since we have no filesystem,
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* open will only return an error.
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* Map port A (1) to stdin, stdout, and stderr.
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* Map everything else to port B (0).
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*/
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int __write(
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int fd,
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char *buf,
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int nbytes
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)
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int __write(int fd, char *buf, int nbytes)
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{
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int i;
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int i, port;
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if ( fd <= 2 ) port = 1;
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else port = 0;
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for (i = 0; i < nbytes; i++) {
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if (*(buf + i) == '\n') {
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outbyte ('\r');
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char_put (port, '\r');
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}
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outbyte (*(buf + i));
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char_put (port, *(buf + i));
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}
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return (nbytes);
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}
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@@ -29,23 +29,30 @@ extern "C" {
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#include <rtems.h>
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#include <iosupp.h>
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#include <z8530.h>
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/*
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// Following defines must reflect the setup of the particular MVME162
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//-----------------------------------
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* Following defines must reflect the setup of the particular MVME162
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*/
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#define GROUP_BASE_ADDRESS 0x0000F200
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#define BOARD_BASE_ADDRESS 0x00000000
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#define BOARD_BASE_ADDRESS 0xFFFF0000
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/* Base for local interrupters' vectors (with enable bit set) */
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#define VECTOR_BASE 0x67800000
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#define MASK_INT 0x00800000
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#define VBR0 0x6
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#define VBR1 0x7
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/* RAM limits */
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#define RAM_START 0x00100000
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#define RAM_END 0x00200000
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/*
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//-----------------------------------
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* ----------------------------------
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*/
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static volatile struct lcsr {
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typedef volatile struct lcsr_regs {
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unsigned long slave_adr[2];
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unsigned long slave_trn[2];
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unsigned long slave_ctl;
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@@ -73,80 +80,135 @@ static volatile struct lcsr {
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unsigned long intr_clear;
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unsigned long intr_level[4];
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unsigned long vector_base;
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} *lcsr = (void *) 0xFFF40000;
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} lcsr_regs;
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#define USE_CHANNEL_A 1 /* 1 = use channel A for console */
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#define USE_CHANNEL_B 0 /* 1 = use channel B for console */
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#define lcsr ((lcsr_regs * const) 0xFFF40000)
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/* Constants */
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typedef volatile struct mcchip_regs {
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#if (USE_CHANNEL_A == 1)
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#define CONSOLE_CONTROL 0xFFF45005
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#define CONSOLE_DATA 0xFFF45007
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#elif (USE_CHANNEL_B == 1)
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#define CONSOLE_CONTROL 0xFFF45001
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#define CONSOLE_DATA 0xFFF45003
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#endif
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unsigned char chipID;
|
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unsigned char chipREV;
|
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unsigned char gen_control;
|
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unsigned char vector_base;
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|
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unsigned long timer_cmp_1;
|
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unsigned long timer_cnt_1;
|
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unsigned long timer_cmp_2;
|
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unsigned long timer_cnt_2;
|
||||
|
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unsigned char LSB_prescaler_count;
|
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unsigned char prescaler_clock_adjust;
|
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unsigned char time_ctl_2;
|
||||
unsigned char time_ctl_1;
|
||||
|
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unsigned char time_int_ctl_4;
|
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unsigned char time_int_ctl_3;
|
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unsigned char time_int_ctl_2;
|
||||
unsigned char time_int_ctl_1;
|
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|
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unsigned char dram_err_int_ctl;
|
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unsigned char SCC_int_ctl;
|
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unsigned char time_ctl_4;
|
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unsigned char time_ctl_3;
|
||||
|
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unsigned short DRAM_space_base;
|
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unsigned short SRAM_space_base;
|
||||
|
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unsigned char DRAM_size;
|
||||
unsigned char DRAM_SRAM_opt;
|
||||
unsigned char SRAM_size;
|
||||
unsigned char reserved;
|
||||
|
||||
unsigned char LANC_error;
|
||||
unsigned char reserved1;
|
||||
unsigned char LANC_int_ctl;
|
||||
unsigned char LANC_berr_ctl;
|
||||
|
||||
unsigned char SCSI_error;
|
||||
unsigned char general_inputs;
|
||||
unsigned char MVME_162_version;
|
||||
unsigned char SCSI_int_ctl;
|
||||
|
||||
unsigned long timer_cmp_3;
|
||||
unsigned long timer_cnt_3;
|
||||
unsigned long timer_cmp_4;
|
||||
unsigned long timer_cnt_4;
|
||||
|
||||
unsigned char bus_clk;
|
||||
unsigned char PROM_acc_time_ctl;
|
||||
unsigned char FLASH_acc_time_ctl;
|
||||
unsigned char ABORT_int_ctl;
|
||||
|
||||
unsigned char RESET_ctl;
|
||||
unsigned char watchdog_timer_ctl;
|
||||
unsigned char acc_watchdog_time_base_sel;
|
||||
unsigned char reserved2;
|
||||
|
||||
unsigned char DRAM_ctl;
|
||||
unsigned char reserved4;
|
||||
unsigned char MPU_status;
|
||||
unsigned char reserved3;
|
||||
|
||||
unsigned long prescaler_count;
|
||||
|
||||
} mcchip_regs;
|
||||
|
||||
#define mcchip ((mcchip_regs * const) 0xFFF42000)
|
||||
|
||||
/*----------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
// The following registers are located in the VMEbus short
|
||||
// IO space and respond to address modifier codes $29 and $2D.
|
||||
// On FORCE SPARC CPU use address gcsr_vme and device /dev/vme16d32.
|
||||
* SCC Z8523(0) defines and macros
|
||||
* -------------------------------
|
||||
* Prototypes for the low-level serial io are also included here,
|
||||
* because such stuff is bsp-specific (yet). The function bodies
|
||||
* are in console.c
|
||||
*/
|
||||
static volatile struct gcsr {
|
||||
|
||||
enum {portB, portA};
|
||||
|
||||
rtems_boolean char_ready(int port, char *ch);
|
||||
char char_wait(int port);
|
||||
void char_put(int port, char ch);
|
||||
|
||||
#define TX_BUFFER_EMPTY 0x04
|
||||
#define RX_DATA_AVAILABLE 0x01
|
||||
#define SCC_VECTOR 0x40
|
||||
|
||||
typedef volatile struct scc_regs {
|
||||
unsigned char pad1;
|
||||
volatile unsigned char csr;
|
||||
unsigned char pad2;
|
||||
volatile unsigned char buf;
|
||||
} scc_regs;
|
||||
|
||||
#define scc ((scc_regs * const) 0xFFF45000)
|
||||
|
||||
#define ZWRITE0(port, v) (scc[port].csr = (unsigned char)(v))
|
||||
#define ZREAD0(port) (scc[port].csr)
|
||||
|
||||
#define ZREAD(port, n) (ZWRITE0(port, n), (scc[port].csr))
|
||||
#define ZREADD(port) (scc[port].buf)
|
||||
|
||||
#define ZWRITE(port, n, v) (ZWRITE0(port, n), ZWRITE0(port, v))
|
||||
#define ZWRITED(port, v) (scc[port].buf = (unsigned char)(v))
|
||||
/*----------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* The following registers are located in the VMEbus short
|
||||
* IO space and respond to address modifier codes $29 and $2D.
|
||||
* On FORCE CPU use address gcsr_vme and device /dev/vme16d32.
|
||||
*/
|
||||
typedef volatile struct gcsr_regs {
|
||||
unsigned char chip_revision;
|
||||
unsigned char chip_id;
|
||||
unsigned char lmsig;
|
||||
unsigned char board_scr;
|
||||
unsigned short gpr[6];
|
||||
} *gcsr_vme = (void *) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS),
|
||||
*gcsr = (void *) 0xFFF40100;
|
||||
} gcsr_regs;
|
||||
|
||||
static volatile unsigned short *ipio[6] = { (unsigned short *) 0xFFF58000,
|
||||
(unsigned short *) 0xFFF58100,
|
||||
(unsigned short *) 0xFFF58200,
|
||||
(unsigned short *) 0xFFF58300,
|
||||
(unsigned short *) 0xFFF58400,
|
||||
(unsigned short *) 0xFFF58500
|
||||
};
|
||||
|
||||
static volatile unsigned short *ipid[6] = { (unsigned short *) 0xFFF58080,
|
||||
(unsigned short *) 0xFFF58180,
|
||||
(unsigned short *) 0xFFF58280,
|
||||
(unsigned short *) 0xFFF58380,
|
||||
(unsigned short *) 0xFFF58080,
|
||||
(unsigned short *) 0xFFF58280
|
||||
};
|
||||
|
||||
static volatile struct ipic_space {
|
||||
struct sing {
|
||||
unsigned short io_space[64];
|
||||
unsigned short id_space[32];
|
||||
unsigned short id_reptd[32];
|
||||
} single[4];
|
||||
struct twin {
|
||||
unsigned short io_space[128];
|
||||
unsigned short io_reptd[128];
|
||||
} twin[2];
|
||||
} *ipic_space = (void *) 0xFFF58000;
|
||||
|
||||
static volatile struct ipic_csr {
|
||||
unsigned char chip_id;
|
||||
unsigned char chip_rev;
|
||||
unsigned char res[2];
|
||||
unsigned short a_31_16_base;
|
||||
unsigned short b_31_16_base;
|
||||
unsigned short c_31_16_base;
|
||||
unsigned short d_31_16_base;
|
||||
unsigned char a_23_16_size;
|
||||
unsigned char b_23_16_size;
|
||||
unsigned char c_23_16_size;
|
||||
unsigned char d_23_16_size;
|
||||
unsigned short a_intr_cnt;
|
||||
unsigned short b_intr_cnt;
|
||||
unsigned short c_intr_cnt;
|
||||
unsigned short d_intr_cnt;
|
||||
} *ipic_csr = (void *) 0xFFFBC000;
|
||||
#define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
|
||||
#define gcsr ((gcsr_regs * const) 0xFFF40100)
|
||||
|
||||
/*
|
||||
* Define the time limits for RTEMS Test Suite test durations.
|
||||
@@ -162,38 +224,23 @@ static volatile struct ipic_csr {
|
||||
/*
|
||||
* Define the interrupt mechanism for Time Test 27
|
||||
*
|
||||
* NOTE: Not implemented
|
||||
* NOTE: We use software interrupt 0
|
||||
*/
|
||||
|
||||
#define MUST_WAIT_FOR_INTERRUPT 0
|
||||
|
||||
#define Install_tm27_vector( handler )
|
||||
#define Install_tm27_vector( handler ) \
|
||||
set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \
|
||||
lcsr->intr_level[2] |= 3; \
|
||||
lcsr->intr_ena |= 0x100;
|
||||
|
||||
#define Cause_tm27_intr()
|
||||
#define Cause_tm27_intr() lcsr->intr_soft_set |= 0x100
|
||||
|
||||
#define Clear_tm27_intr()
|
||||
#define Clear_tm27_intr() lcsr->intr_clear |= 0x100
|
||||
|
||||
#define Lower_tm27_intr()
|
||||
|
||||
/*
|
||||
* Simple spin delay in microsecond units for device drivers.
|
||||
* This is very dependent on the clock speed of the target.
|
||||
*/
|
||||
|
||||
#define delay( microseconds ) \
|
||||
{ register rtems_unsigned32 _delay=(microseconds); \
|
||||
register rtems_unsigned32 _tmp=123; \
|
||||
asm volatile( "0: \
|
||||
nbcd %0 ; \
|
||||
nbcd %0 ; \
|
||||
dbf %1,0b" \
|
||||
: "=d" (_tmp), "=d" (_delay) \
|
||||
: "0" (_tmp), "1" (_delay) ); \
|
||||
}
|
||||
|
||||
/* Constants */
|
||||
|
||||
#ifdef 1626_INIT
|
||||
#ifdef M162_INIT
|
||||
#undef EXTERN
|
||||
#define EXTERN
|
||||
#else
|
||||
|
||||
@@ -103,11 +103,13 @@ int bsp_start(
|
||||
m68k_set_vbr( &M68Kvec );
|
||||
|
||||
/*
|
||||
* You may wish to make VME access round-robin here, currently
|
||||
* You may wish to make the VME arbitration round-robin here, currently
|
||||
* we leave it as it is.
|
||||
*/
|
||||
|
||||
lcsr->vector_base = VECTOR_BASE; /* set the vector base register */
|
||||
/* set the Interrupt Base Vectors */
|
||||
|
||||
lcsr->vector_base = (VBR0 << 28) | (VBR1 << 24);
|
||||
|
||||
m68k_enable_caching();
|
||||
|
||||
|
||||
@@ -31,41 +31,42 @@
|
||||
* $Id$
|
||||
*/
|
||||
|
||||
|
||||
#include <rtems.h>
|
||||
#include <bsp.h>
|
||||
|
||||
/* Periodic tick interval */
|
||||
#define TICK_INTERVAL 0x10000
|
||||
#define TICK_INTERVAL 0x10000U
|
||||
#define TIMER_INT_LEVEL 6
|
||||
|
||||
int Ttimer_val;
|
||||
rtems_unsigned32 Ttimer_val;
|
||||
rtems_boolean Timer_driver_Find_average_overhead;
|
||||
|
||||
rtems_isr timerisr();
|
||||
|
||||
void Timer_initialize()
|
||||
{
|
||||
(void) set_vector( timerisr, (VECTOR_BASE >> 28) * 0x10 + 0x8, 0 );
|
||||
(void) set_vector( timerisr, VBR0 * 0x10 + 0x8, 0 );
|
||||
|
||||
Ttimer_val = 0; /* clear timer ISR count */
|
||||
lcsr->vector_base = 0x67800000; /* set vb, enable interrupts */
|
||||
lcsr->vector_base |= MASK_INT; /* unmask VMEchip2 interrupts */
|
||||
lcsr->intr_clear |= 0x01000000; /* clear pending interrupt */
|
||||
lcsr->to_ctl = 0xE7; /* prescaler to 1 MHz (see Appendix A1) */
|
||||
lcsr->timer_cmp_1 = TICK_INTERVAL;
|
||||
lcsr->timer_cnt_1 = 0; /* clear counter */
|
||||
lcsr->board_ctl |= 7; /* increment, reset-on-compare, clear-ovfl-cnt */
|
||||
lcsr->board_ctl |= 7; /* increment, reset-on-compare, */
|
||||
/* and clear-overflow-cnt */
|
||||
|
||||
lcsr->intr_level[0] |= TIMER_INT_LEVEL; /* set int level */
|
||||
lcsr->intr_ena |= 0x01000000; /* enable tick timer 1 interrupt */
|
||||
}
|
||||
|
||||
#define AVG_OVERHEAD 6 /* It typically takes 3.0 microseconds */
|
||||
/* (6 countdowns) to start/stop the timer. */
|
||||
#define LEAST_VALID 10 /* Don't trust a value lower than this */
|
||||
#define AVG_OVERHEAD 3U /* It typically takes 3.0 microseconds */
|
||||
/* (3 countdowns) to start/stop the timer. */
|
||||
#define LEAST_VALID 10U /* Don't trust a value lower than this */
|
||||
|
||||
int Read_timer()
|
||||
{
|
||||
unsigned long total;
|
||||
rtems_unsigned32 total;
|
||||
|
||||
total = (Ttimer_val * TICK_INTERVAL) + lcsr->timer_cnt_1;
|
||||
|
||||
@@ -75,9 +76,10 @@ int Read_timer()
|
||||
if ( total < LEAST_VALID )
|
||||
return 0; /* below timer resolution */
|
||||
|
||||
return (total-AVG_OVERHEAD); /* in musec units */
|
||||
return (total-AVG_OVERHEAD) >> 1;
|
||||
}
|
||||
|
||||
|
||||
rtems_status_code Empty_function( void )
|
||||
{
|
||||
return RTEMS_SUCCESSFUL;
|
||||
|
||||
@@ -33,6 +33,7 @@ BEGIN_CODE
|
||||
.set INTR_CLEAR_REG, 0xfff40074 | interrupt clear register
|
||||
.set RELOAD, 0x01000000 | clear tick 1 interrupt
|
||||
|
||||
PUBLIC (Ttimer_val)
|
||||
PUBLIC (timerisr)
|
||||
SYM (timerisr):
|
||||
move.l a0, -(a7) | save a0
|
||||
|
||||
@@ -85,8 +85,7 @@ int issrec(char *str)
|
||||
*/
|
||||
{
|
||||
/* Check first character for S */
|
||||
if ((isupper(str[0]) && (str[0] == 'S')) ||
|
||||
(islower(str[0]) && (str[0] == 's')))
|
||||
if ((isupper(str[0]) && (str[0] == 'S')) || (islower(str[0]) && (str[0] == 's')))
|
||||
{
|
||||
/* check for valid header number */
|
||||
switch (str[1]) {
|
||||
@@ -128,8 +127,7 @@ int validrec(char *str)
|
||||
if (((strlen(str)-4)/2U) != rlen) return(-3);
|
||||
|
||||
/* get checksum from string */
|
||||
rchksum = ahdtoi(str[rlen*2+2])*0x10 + ahdtoi(str[rlen*2+3]);
|
||||
/* string chksum */
|
||||
rchksum = ahdtoi(str[rlen*2+2])*0x10 + ahdtoi(str[rlen*2+3]); /* string chksum */
|
||||
|
||||
/* now calculate my own checksum */
|
||||
for (cn=2; cn <= rlen*2; )
|
||||
@@ -170,19 +168,16 @@ unsigned long getaddr(char *str)
|
||||
case 0 :
|
||||
case 1 :
|
||||
case 5 :
|
||||
case 9 :
|
||||
addr = ahdtoi(str[4])*0x1000 + ahdtoi(str[5])*0x100
|
||||
case 9 : addr = ahdtoi(str[4])*0x1000 + ahdtoi(str[5])*0x100
|
||||
+ ahdtoi(str[6])*0x10 + ahdtoi(str[7]);
|
||||
return(addr);
|
||||
case 2 :
|
||||
case 8 :
|
||||
addr = ahdtoi(str[4])*0x100000 + ahdtoi(str[5])*0x10000
|
||||
case 8 : addr = ahdtoi(str[4])*0x100000 + ahdtoi(str[5])*0x10000
|
||||
+ ahdtoi(str[6])*0x1000 + ahdtoi(str[7])*0x100
|
||||
+ ahdtoi(str[8])*0x10 + ahdtoi(str[9]);
|
||||
return(addr);
|
||||
case 3 :
|
||||
case 7 :
|
||||
addr = ahdtoi(str[4])*0x10000000 + ahdtoi(str[5])*0x1000000
|
||||
case 7 : addr = ahdtoi(str[4])*0x10000000 + ahdtoi(str[5])*0x1000000
|
||||
+ ahdtoi(str[6])*0x100000 + ahdtoi(str[7])*0x10000
|
||||
+ ahdtoi(str[8])*0x1000 + ahdtoi(str[9])*0x100
|
||||
+ ahdtoi(str[10])*0x10 + ahdtoi(str[11]);
|
||||
@@ -252,8 +247,7 @@ int MVMEControl(u_long entry, int reset, int go)
|
||||
}
|
||||
|
||||
/* "MAP_SHARED" is important here */
|
||||
gcsr_map = (struct gcsr *)
|
||||
mmap(0, 0x1000, PROT_WRITE|PROT_READ, MAP_SHARED,
|
||||
gcsr_map = (struct gcsr *) mmap(0, 0x1000, PROT_WRITE|PROT_READ, MAP_SHARED,
|
||||
vme, (u_long)gcsr_vme / pagesize * pagesize);
|
||||
if (gcsr_map == (struct gcsr *) - 1) {
|
||||
perror("mmap");
|
||||
@@ -266,8 +260,7 @@ int MVMEControl(u_long entry, int reset, int go)
|
||||
* use GCSR to start execution in MVME162
|
||||
* adjust pointer to compensate for page alignement
|
||||
*/
|
||||
gcsr_map = (struct gcsr *)((u_long)gcsr_map +
|
||||
(u_long)gcsr_vme % pagesize);
|
||||
gcsr_map = (struct gcsr *)((u_long)gcsr_map + (u_long)gcsr_vme % pagesize);
|
||||
|
||||
if (reset) { /* reset the local bus... */
|
||||
gcsr_map->board_scr |= 0x80;
|
||||
@@ -461,15 +454,9 @@ main(int argc, char *argv[])
|
||||
}
|
||||
break;
|
||||
case 7 :
|
||||
if (lastrec==DATA19){
|
||||
if (verbose) printf("\t$%04lX\t%lu",naddr-1,blksize);
|
||||
}
|
||||
if (lastrec==DATA28){
|
||||
if (verbose) printf("\t$%06lX\t%lu",naddr-1,blksize);
|
||||
}
|
||||
if (lastrec==DATA37){
|
||||
if (verbose) printf("\t$%08lX\t%lu",naddr-1,blksize);
|
||||
}
|
||||
if (lastrec==DATA19){if (verbose) printf("\t$%04lX\t%lu",naddr-1,blksize);}
|
||||
if (lastrec==DATA28){if (verbose) printf("\t$%06lX\t%lu",naddr-1,blksize);}
|
||||
if (lastrec==DATA37){if (verbose) printf("\t$%08lX\t%lu",naddr-1,blksize);}
|
||||
if (verbose) printf("\t%d\n",blknum);
|
||||
addr = getaddr(inpstr);
|
||||
if (verbose) printf("TERM\tS37");
|
||||
@@ -477,15 +464,9 @@ main(int argc, char *argv[])
|
||||
lastrec=TERMINATOR;
|
||||
break;
|
||||
case 8 :
|
||||
if (lastrec==DATA19){
|
||||
if (verbose) printf("\t$%04lX\t%lu",naddr-1,blksize);
|
||||
}
|
||||
if (lastrec==DATA28){
|
||||
if (verbose) printf("\t$%06lX\t%lu",naddr-1,blksize);
|
||||
}
|
||||
if (lastrec==DATA37){
|
||||
if (verbose) printf("\t$%08lX\t%lu",naddr-1,blksize);
|
||||
}
|
||||
if (lastrec==DATA19){if (verbose) printf("\t$%04lX\t%lu",naddr-1,blksize);}
|
||||
if (lastrec==DATA28){if (verbose) printf("\t$%06lX\t%lu",naddr-1,blksize);}
|
||||
if (lastrec==DATA37){if (verbose) printf("\t$%08lX\t%lu",naddr-1,blksize);}
|
||||
if (verbose) printf("\t%d\n",blknum);
|
||||
addr = getaddr(inpstr);
|
||||
if (verbose) printf("TERM\tS28");
|
||||
@@ -493,15 +474,9 @@ main(int argc, char *argv[])
|
||||
lastrec=TERMINATOR;
|
||||
break;
|
||||
case 9 :
|
||||
if (lastrec==DATA19){
|
||||
if (verbose) printf("\t$%04lX\t%lu",naddr-1,blksize);
|
||||
}
|
||||
if (lastrec==DATA28){
|
||||
if (verbose) printf("\t$%06lX\t%lu",naddr-1,blksize);
|
||||
}
|
||||
if (lastrec==DATA37){
|
||||
if (verbose) printf("\t$%08lX\t%lu",naddr-1,blksize);
|
||||
}
|
||||
if (lastrec==DATA19){if (verbose) printf("\t$%04lX\t%lu",naddr-1,blksize);}
|
||||
if (lastrec==DATA28){if (verbose) printf("\t$%06lX\t%lu",naddr-1,blksize);}
|
||||
if (lastrec==DATA37){if (verbose) printf("\t$%08lX\t%lu",naddr-1,blksize);}
|
||||
if (verbose) printf("\t%d\n",blknum);
|
||||
addr = getaddr(inpstr);
|
||||
if (verbose) printf("TERM\tS19");
|
||||
@@ -522,15 +497,9 @@ main(int argc, char *argv[])
|
||||
}
|
||||
|
||||
if ((lastrec==DATA19) || (lastrec==DATA28) || (lastrec==DATA37)) {
|
||||
if (lastrec==DATA19){
|
||||
if (verbose) printf("\t$%04lX\t%lu",naddr-1,blksize);
|
||||
}
|
||||
if (lastrec==DATA28){
|
||||
if (verbose) printf("\t$%06lX\t%lu",naddr-1,blksize);
|
||||
}
|
||||
if (lastrec==DATA37){
|
||||
if (verbose) printf("\t$%08lX\t%lu",naddr-1,blksize);
|
||||
}
|
||||
if (lastrec==DATA19){if (verbose) printf("\t$%04lX\t%lu",naddr-1,blksize);}
|
||||
if (lastrec==DATA28){if (verbose) printf("\t$%06lX\t%lu",naddr-1,blksize);}
|
||||
if (lastrec==DATA37){if (verbose) printf("\t$%08lX\t%lu",naddr-1,blksize);}
|
||||
if (verbose) printf("\t%d\n",blknum);
|
||||
printf("ERROR: terminator record not found.\n");
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user