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2004-11-10 Richard Campbell <richard.campbell@oarcorp.com>

Browse Source 
* ChangeLog, Makefile.am, bootloader/misc.c, bootloader/pci.c,
	bootloader/pci.h, console/console.c, console/inch.c,
	console/reboot.c, console/uart.c, console/uart.h, include/bsp.h,
	irq/irq.c, irq/irq.h, irq/irq_init.c, motorola/motorola.c,
	motorola/motorola.h, openpic/openpic.c, openpic/openpic.h,
	pci/detect_raven_bridge.c, pci/pci.c, pci/pci.h, start/start.S,
	startup/bspstart.c, vectors/vectors_init.c, vme/vmeconfig.c: Add
	MVME2100 BSP and MPC8240 support. There was also a significant amount
	of spelling and whitespace cleanup.
	* tod/.cvsignore, tod/Makefile.am, tod/todcfg.c: New files.
This commit is contained in:
Joel Sherrill
2004-11-10 22:15:01 +00:00
parent ae460ecea9
commit bd91ff4e71
28 changed files with 681 additions and 289 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
c/src/lib/libbsp/powerpc/shared/ChangeLog
View File

@@ -1,3 +1,27 @@
2004-11-10 Richard Campbell <richard.campbell@oarcorp.com>
* ChangeLog, Makefile.am, bootloader/misc.c, bootloader/pci.c,
bootloader/pci.h, console/console.c, console/inch.c,
console/reboot.c, console/uart.c, console/uart.h, include/bsp.h,
irq/irq.c, irq/irq.h, irq/irq_init.c, motorola/motorola.c,
motorola/motorola.h, openpic/openpic.c, openpic/openpic.h,
pci/detect_raven_bridge.c, pci/pci.c, pci/pci.h, start/start.S,
startup/bspstart.c, vectors/vectors_init.c, vme/vmeconfig.c: Add
MVME2100 BSP and MPC8240 support. There was also a significant amount
of spelling and whitespace cleanup.
* tod/.cvsignore, tod/Makefile.am, tod/todcfg.c: New files.
2004-11-10 Richard Campbell <richard.campbell@oarcorp.com>
* Makefile.am, bootloader/misc.c, bootloader/pci.c, bootloader/pci.h,
console/console.c, console/inch.c, console/reboot.c, console/uart.c,
console/uart.h, include/bsp.h, irq/irq.c, irq/irq.h, irq/irq_init.c,
motorola/motorola.c, motorola/motorola.h, openpic/openpic.c,
openpic/openpic.h, pci/detect_raven_bridge.c, pci/pci.c, pci/pci.h,
start/start.S, startup/bspstart.c, vectors/vectors_init.c,
vme/vmeconfig.c: Add MVME2100 BSP and MPC8240 support.
* tod/.cvsignore, tod/Makefile.am, tod/todcfg.c: New files.
2004-09-27 Greg Menke <gregory.menke@gsfc.nasa.gov>
PR 606/bsps

2
c/src/lib/libbsp/powerpc/shared/Makefile.am
View File

@@ -5,7 +5,7 @@
if need_shared
SUBDIRS = clock console include pci residual openpic irq vectors start \
startup motorola bootloader vme
startup motorola bootloader vme tod
endif
include $(top_srcdir)/../../../../../automake/subdirs.am

10
c/src/lib/libbsp/powerpc/shared/bootloader/misc.c
View File

@@ -24,6 +24,7 @@
#include <libcpu/page.h>
#include <libcpu/byteorder.h>
#include <rtems/bspIo.h>
#include <bsp.h>
SPR_RW(DEC)
SPR_RO(PVR)
@@ -280,8 +281,13 @@ setup_hw(void)
/* We check that the keyboard is present and immediately
* select the serial console if not.
*/
#if defined(BSP_KBD_IOBASE)
err = kbdreset();
if (err) select_console(CONSOLE_SERIAL);
if (err) select_console(CONSOLE_SERIAL);
#else
err = 1;
select_console(CONSOLE_SERIAL);
#endif
printk("\nModel: %s\nSerial: %s\n"
"Processor/Bus frequencies (Hz): %ld/%ld\n"
@@ -293,8 +299,6 @@ setup_hw(void)
vpd.ProcessorBusHz,
(vpd.TimeBaseDivisor ? vpd.TimeBaseDivisor : 4000),
res->TotalMemory);
printk("Original MSR: %lx\nOriginal HID0: %lx\nOriginal R31: %lx\n",
bd->o_msr, bd->o_hid0, bd->o_r31);
/* This reconfigures all the PCI subsystem */
pci_init();

1
c/src/lib/libbsp/powerpc/shared/bootloader/pci.c
View File

@@ -24,6 +24,7 @@
#include <libcpu/io.h>
#include <libcpu/page.h>
#include <bsp/consoleIo.h>
#include <string.h>
typedef unsigned int u32;

1
c/src/lib/libbsp/powerpc/shared/bootloader/pci.h
View File

@@ -497,6 +497,7 @@
#define PCI_VENDOR_ID_MOTOROLA 0x1057
#define PCI_DEVICE_ID_MOTOROLA_MPC105 0x0001
#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002
#define PCI_DEVICE_ID_MOTOROLA_MPC8240 0x0003
#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801
#define PCI_VENDOR_ID_PROMISE 0x105a

29
c/src/lib/libbsp/powerpc/shared/console/console.c
View File

@@ -75,7 +75,6 @@ static TtySTblRec ttyS[]={
},
};
/*-------------------------------------------------------------------------+
| Console device driver INITIALIZE entry point.
+--------------------------------------------------------------------------+
@@ -135,6 +134,7 @@ console_initialize(rtems_device_major_number major,
}
}
return RTEMS_SUCCESSFUL;
} /* console_initialize */
@@ -174,22 +174,35 @@ console_open(rtems_device_major_number major,
{
rtems_status_code status;
static rtems_termios_callbacks cb =
#if defined(USE_POLLED_IO)
{
NULL, /* firstOpen */
NULL, /* lastClose */
NULL, /* pollRead */
BSP_uart_termios_write_polled, /* write */
conSetAttr, /* setAttributes */
NULL, /* stopRemoteTx */
NULL, /* startRemoteTx */
0 /* outputUsesInterrupts */
};
#else
{
console_first_open, /* firstOpen */
console_last_close, /* lastClose */
NULL, /* pollRead */
BSP_uart_termios_write_com, /* write */
conSetAttr, /* setAttributes */
NULL, /* stopRemoteTx */
NULL, /* startRemoteTx */
1 /* outputUsesInterrupts */
NULL, /* pollRead */
BSP_uart_termios_write_com, /* write */
conSetAttr, /* setAttributes */
NULL, /* stopRemoteTx */
NULL, /* startRemoteTx */
1 /* outputUsesInterrupts */
};
#endif
status = rtems_termios_open (major, minor, arg, &cb);
if(status != RTEMS_SUCCESSFUL)
{
printk("Error openning console device\n");
printk("Error opening console device\n");
return status;
}

8
c/src/lib/libbsp/powerpc/shared/console/inch.c
View File

@@ -20,6 +20,7 @@
*/
#include <bsp.h>
#if defined(BSP_KBD_IOBASE)
#include <bsp/irq.h>
#include "console.inl"
@@ -299,9 +300,4 @@ _IBMPC_inch_sleep(void)
return c;
} /* _IBMPC_inch */
#endif

2
c/src/lib/libbsp/powerpc/shared/console/reboot.c
View File

@@ -16,5 +16,7 @@ void rtemsReboot(void)
printk("Printing a stack trace for your convenience :-)\n");
CPU_print_stack();
/* shutdown and reboot */
#if defined(BSP_KBD_IOBASE)
kbd_outb(0x4, 0xFE); /* use keyboard controler to do the job... */
#endif
} /* rtemsReboot */

32
c/src/lib/libbsp/powerpc/shared/console/uart.c
View File

@@ -185,6 +185,7 @@ BSP_uart_init(int uart, int baud, int hwFlow)
/* Remember state */
uart_data[uart].hwFlow = hwFlow;
uart_data[uart].baud = baud;
return;
}
@@ -201,7 +202,7 @@ BSP_uart_set_baud(int uart, int baud)
/*
* This function may be called whenever TERMIOS parameters
* are changed, so we have to make sire that baud change is
* are changed, so we have to make sure that baud change is
* indeed required
*/
@@ -460,8 +461,14 @@ uart_noop(const rtems_irq_connect_data *unused)
static int
uart_isr_is_on(const rtems_irq_connect_data *irq)
{
int uart = (irq->name == BSP_ISA_UART_COM1_IRQ) ?
int uart;
#if defined(mvme2100)
uart = BSP_UART_COM1;
#else
uart = (irq->name == BSP_ISA_UART_COM1_IRQ) ?
BSP_UART_COM1 : BSP_UART_COM2;
#endif
return uread(uart,IER);
}
@@ -469,8 +476,12 @@ static int
doit(int uart, rtems_irq_hdl handler, int (*p)(const rtems_irq_connect_data*))
{
rtems_irq_connect_data d={0};
#if defined(mvme2100)
d.name = BSP_UART_COM1_IRQ;
#else
d.name = (uart == BSP_UART_COM1) ?
BSP_ISA_UART_COM1_IRQ : BSP_ISA_UART_COM2_IRQ;
#endif
d.off = d.on = uart_noop;
d.isOn = uart_isr_is_on;
d.hdl = handler;
@@ -525,6 +536,21 @@ BSP_uart_termios_set(int uart, void *ttyp)
return;
}
int
BSP_uart_termios_write_polled(int minor, const char *buf, int len)
{
int uart=minor; /* could differ, theoretically */
int nwrite;
const char *b = buf;
assert(buf != NULL);
for (nwrite=0 ; nwrite < len ; nwrite++) {
BSP_uart_polled_write(uart, *b++);
}
return nwrite;
}
int
BSP_uart_termios_write_com(int minor, const char *buf, int len)
{
@@ -536,7 +562,7 @@ BSP_uart_termios_write_com(int minor, const char *buf, int len)
return 0;
}
/* If there TX buffer is busy - something is royally screwed up */
/* If the TX buffer is busy - something is royally screwed up */
/* assert((uread(BSP_UART_COM1, LSR) & THRE) != 0); */

3
c/src/lib/libbsp/powerpc/shared/console/uart.h
View File

@@ -16,7 +16,7 @@
#include <rtems/libio.h>
void BSP_uart_init(int uart, int baud, int hwFlow);
void BSP_uart_set_baud(int aurt, int baud);
void BSP_uart_set_baud(int uart, int baud);
void BSP_uart_intr_ctrl(int uart, int cmd);
void BSP_uart_throttle(int uart);
void BSP_uart_unthrottle(int uart);
@@ -31,6 +31,7 @@ void BSP_uart_dbgisr_com1(void);
void BSP_uart_dbgisr_com2(void);
int BSP_uart_install_isr(int uart, rtems_irq_hdl handler);
int BSP_uart_remove_isr(int uart, rtems_irq_hdl handler);
int BSP_uart_termios_write_polled(int minor, const char *buf, int len);
int BSP_uart_get_break_cb(int uart, rtems_libio_ioctl_args_t *arg);
int BSP_uart_set_break_cb(int uart, rtems_libio_ioctl_args_t *arg);

49
c/src/lib/libbsp/powerpc/shared/include/bsp.h
View File

@@ -26,28 +26,69 @@
* - Interrupt stack space is not minimum if defined.
*/
#if defined(mvme2100)
#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 1
#else
#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
#endif
#define CONFIGURE_INTERRUPT_STACK_MEMORY (16 * 1024)
/* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */
#define _IO_BASE PREP_ISA_IO_BASE
/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
#if defined(mvme2100)
#define _IO_BASE CHRP_ISA_IO_BASE
#define _ISA_MEM_BASE CHRP_ISA_MEM_BASE
/* address of our ram on the PCI bus */
#define PCI_DRAM_OFFSET CHRP_PCI_DRAM_OFFSET
#define PCI_MEM_BASE 0x80000000
#define PCI_MEM_BASE_ADJUSTMENT 0
#else
#define _IO_BASE PREP_ISA_IO_BASE
#define _ISA_MEM_BASE PREP_ISA_MEM_BASE
/* address of our ram on the PCI bus */
#define PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET
/* offset of pci memory as seen from the CPU */
#define PCI_MEM_BASE PREP_ISA_MEM_BASE
#define PCI_MEM_BASE_ADJUSTMENT PREP_ISA_MEM_BASE
#endif
/*
* base address definitions for several devices
* Base address definitions for several devices
*
* MVME2100 is very similar but has fewer devices and uses on-CPU EPIC
* implementation of OpenPIC controller. It also cannot be probed to
* find out what it is which is VERY different from other Motorola boards.
*/
#if defined(mvme2100)
#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e10000)
/* #define BSP_UART_IOBASE_COM1 (0xffe10000) */
#define BSP_OPEN_PIC_BASE_OFFSET 0x40000
#define MVME_HAS_DEC21140
#else
#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x3f8)
#define BSP_UART_IOBASE_COM2 ((_IO_BASE)+0x2f8)
#define BSP_KBD_IOBASE ((_IO_BASE)+0x60)
#define BSP_VGA_IOBASE ((_IO_BASE)+0x3c0)
#define BSP_CONSOLE_PORT BSP_UART_COM1
#if defined(mvme2300)
#define MVME_HAS_DEC21140
#endif
#endif
#define BSP_UART_BAUD_BASE 115200
#define BSP_CONSOLE_PORT BSP_UART_COM1
#if defined(MVME_HAS_DEC21140)
struct rtems_bsdnet_ifconfig;
int rtems_dec21140_driver_attach (struct rtems_bsdnet_ifconfig *, int);
#define RTEMS_BSP_NETWORK_DRIVER_NAME "dc1"
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_dec21140_driver_attach
#endif
#include <bsp/openpic.h>
#define BSP_PIC_DO_EOI openpic_eoi(0)

10
c/src/lib/libbsp/powerpc/shared/irq/irq.c
View File

@@ -21,6 +21,7 @@
#include <libcpu/raw_exception.h>
#include <libcpu/io.h>
#include <bsp/vectors.h>
#include <stdlib.h>
#include <rtems/bspIo.h> /* for printk */
#define RAVEN_INTR_ACK_REG 0xfeff0030
@@ -28,7 +29,7 @@
/*
* pointer to the mask representing the additionnal irq vectors
* that must be disabled when a particular entry is activated.
* They will be dynamically computed from teh prioruty table given
* They will be dynamically computed from the priority table given
* in BSP_rtems_irq_mngt_set();
* CAUTION : this table is accessed directly by interrupt routine
* prologue.
@@ -67,7 +68,7 @@ static inline int is_pci_irq(const rtems_irq_symbolic_name irqLine)
}
/*
* Check if IRQ is a Porcessor IRQ
* Check if IRQ is a Processor IRQ
*/
static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
{
@@ -363,7 +364,7 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
}
/*
* ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
* RTEMS Global Interrupt Handler Management Routines
*/
int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
@@ -517,7 +518,6 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
register unsigned msr;
register unsigned new_msr;
if (excNum == ASM_DEC_VECTOR) {
_CPU_MSR_GET(msr);
new_msr = msr | MSR_EE;
@@ -527,8 +527,8 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
_CPU_MSR_SET(msr);
return;
}
irq = openpic_irq(0);
if (irq == OPENPIC_VEC_SPURIOUS) {
++BSP_spuriousIntr;

110
c/src/lib/libbsp/powerpc/shared/irq/irq.h
View File

@@ -1,9 +1,9 @@
/* irq.h
*
* This include file describe the data structure and the functions implemented
* by rtems to write interrupt handlers.
* by RTEMS to write interrupt handlers.
*
* CopyRight (C) 1999 valette@crf.canon.fr
* Copyright (C) 1999 valette@crf.canon.fr
*
* This code is heavilly inspired by the public specification of STREAM V2
* that can be found at :
@@ -21,7 +21,6 @@
#ifndef LIBBSP_POWERPC_MCP750_IRQ_IRQ_H
#define LIBBSP_POWERPC_MCP750_IRQ_IRQ_H
/*
* 8259 edge/level control definitions at VIA
*/
@@ -65,71 +64,79 @@ extern "C" {
/*
* Symblolic IRQ names and related definitions.
* Symbolic IRQ names and related definitions.
*/
typedef enum {
/* Base vector for our ISA IRQ handlers. */
BSP_ISA_IRQ_VECTOR_BASE = BSP_ASM_IRQ_VECTOR_BASE,
BSP_ISA_IRQ_VECTOR_BASE = BSP_ASM_IRQ_VECTOR_BASE,
/*
* ISA IRQ handler related definitions
*/
BSP_ISA_IRQ_NUMBER = 16,
BSP_ISA_IRQ_LOWEST_OFFSET = 0,
BSP_ISA_IRQ_MAX_OFFSET = BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1,
BSP_ISA_IRQ_NUMBER = 16,
BSP_ISA_IRQ_LOWEST_OFFSET = 0,
BSP_ISA_IRQ_MAX_OFFSET = BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1,
/*
* PCI IRQ handlers related definitions
* CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
*/
BSP_PCI_IRQ_NUMBER = 16,
BSP_PCI_IRQ_LOWEST_OFFSET = BSP_ISA_IRQ_NUMBER,
BSP_PCI_IRQ_MAX_OFFSET = BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1,
BSP_PCI_IRQ_NUMBER = 16,
BSP_PCI_IRQ_LOWEST_OFFSET = BSP_ISA_IRQ_NUMBER,
BSP_PCI_IRQ_MAX_OFFSET = BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1,
/*
* PowerPc exceptions handled as interrupt where a rtems managed interrupt
* PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
* handler might be connected
*/
BSP_PROCESSOR_IRQ_NUMBER = 1,
BSP_PROCESSOR_IRQ_LOWEST_OFFSET = BSP_PCI_IRQ_MAX_OFFSET + 1,
BSP_PROCESSOR_IRQ_MAX_OFFSET = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1,
BSP_PROCESSOR_IRQ_NUMBER = 1,
BSP_PROCESSOR_IRQ_LOWEST_OFFSET = BSP_PCI_IRQ_MAX_OFFSET + 1,
BSP_PROCESSOR_IRQ_MAX_OFFSET = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1,
/* Misc vectors for OPENPIC irqs (IPI, timers)
*/
BSP_MISC_IRQ_NUMBER = 8,
BSP_MISC_IRQ_LOWEST_OFFSET = BSP_PROCESSOR_IRQ_MAX_OFFSET + 1,
BSP_MISC_IRQ_MAX_OFFSET = BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1,
BSP_MISC_IRQ_NUMBER = 8,
BSP_MISC_IRQ_LOWEST_OFFSET = BSP_PROCESSOR_IRQ_MAX_OFFSET + 1,
BSP_MISC_IRQ_MAX_OFFSET = BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1,
/*
* Summary
*/
BSP_IRQ_NUMBER = BSP_MISC_IRQ_MAX_OFFSET + 1,
BSP_LOWEST_OFFSET = BSP_ISA_IRQ_LOWEST_OFFSET,
BSP_MAX_OFFSET = BSP_MISC_IRQ_MAX_OFFSET,
BSP_IRQ_NUMBER = BSP_MISC_IRQ_MAX_OFFSET + 1,
BSP_LOWEST_OFFSET = BSP_ISA_IRQ_LOWEST_OFFSET,
BSP_MAX_OFFSET = BSP_MISC_IRQ_MAX_OFFSET,
/*
* Some ISA IRQ symbolic name definition
*/
BSP_ISA_PERIODIC_TIMER = 0,
BSP_ISA_KEYBOARD = 1,
BSP_ISA_UART_COM2_IRQ = 3,
BSP_ISA_UART_COM1_IRQ = 4,
BSP_ISA_RT_TIMER1 = 8,
BSP_ISA_RT_TIMER3 = 10,
BSP_ISA_PERIODIC_TIMER = 0,
BSP_ISA_KEYBOARD = 1,
BSP_ISA_UART_COM2_IRQ = 3,
BSP_ISA_UART_COM1_IRQ = 4,
BSP_ISA_RT_TIMER1 = 8,
BSP_ISA_RT_TIMER3 = 10,
/*
* Some PCI IRQ symbolic name definition
*/
BSP_PCI_IRQ0 = BSP_PCI_IRQ_LOWEST_OFFSET,
BSP_PCI_ISA_BRIDGE_IRQ = BSP_PCI_IRQ0,
BSP_PCI_IRQ0 = BSP_PCI_IRQ_LOWEST_OFFSET,
BSP_PCI_ISA_BRIDGE_IRQ = BSP_PCI_IRQ0,
#if defined(mvme2100)
BSP_DEC21143_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 1,
BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 2,
BSP_PCMIP_TYPE1_SLOT1_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 3,
BSP_PCMIP_TYPE2_SLOT0_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 4,
BSP_PCMIP_TYPE2_SLOT1_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 5,
BSP_PCI_INTA_UNIVERSE_LINT0_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 7,
BSP_PCI_INTB_UNIVERSE_LINT1_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 8,
BSP_PCI_INTC_UNIVERSE_LINT2_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 9,
BSP_PCI_INTD_UNIVERSE_LINT3_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 10,
BSP_UART_COM1_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 13,
BSP_FRONT_PANEL_ABORT_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 14,
BSP_RTC_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 15,
#endif
/*
* Some Processor execption handled as rtems IRQ symbolic name definition
* Some Processor exception handled as RTEMS IRQ symbolic name definition
*/
BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET
}rtems_irq_symbolic_name;
BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET
} rtems_irq_symbolic_name;
/*
* Type definition for RTEMS managed interrupts
@@ -162,7 +169,6 @@ typedef struct __rtems_irq_connect_data__ {
* It is usually called immediately AFTER connecting the interrupt handler.
* RTEMS may well need such a function when restoring normal interrupt
* processing after a debug session.
*
*/
rtems_irq_enable on;
/*
@@ -236,10 +242,10 @@ int BSP_irq_disable_at_i8259s (const rtems_irq_symbolic_name irqLine);
*/
int BSP_irq_enable_at_i8259s (const rtems_irq_symbolic_name irqLine);
/*
* function to acknoledge a particular irq at 8259 level. After calling
* function to acknowledge a particular irq at 8259 level. After calling
* this function, if a device asserts an enabled interrupt line it will
* be propagated further to the processor. Mainly usefull for people
* writting raw handlers as this is automagically done for rtems managed
* be propagated further to the processor. Mainly useful for people
* writing raw handlers as this is automagically done for RTEMS managed
* handlers.
*/
int BSP_irq_ack_at_i8259s (const rtems_irq_symbolic_name irqLine);
@@ -260,18 +266,18 @@ int BSP_irq_enabled_at_i8259s (const rtems_irq_symbolic_name irqLine);
* 3) store the current i8259s' interrupt masks
* 4) modify them to disable the current interrupt at 8259 level (and may
* be others depending on software priorities)
* 5) aknowledge the i8259s',
* 5) acknowledge the i8259s',
* 6) demask the processor,
* 7) call the application handler
*
* As a result the hdl function provided
*
* a) can perfectly be written is C,
* b) may also well directly call the part of the RTEMS API that can be used
* from interrupt level,
* c) It only responsible for handling the jobs that need to be done at
* the device level including (aknowledging/re-enabling the interrupt at device,
* level, getting the data,...)
* b) may also well directly call the part of the RTEMS API that can be
* used from interrupt level,
* c) It is only responsible for handling the jobs that need to be done at
* the device level including (acknowledging/re-enabling the interrupt
* at the device level, getting the data,...)
*
* When returning from the function, the following will be performed by
* the RTEMS irq epilogue :
@@ -282,7 +288,6 @@ int BSP_irq_enabled_at_i8259s (const rtems_irq_symbolic_name irqLine);
* 4) perform rescheduling when necessary,
* 5) restore the C scratch registers...
* 6) restore initial execution flow
*
*/
int BSP_install_rtems_irq_handler (const rtems_irq_connect_data*);
int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data*);
@@ -296,7 +301,8 @@ int BSP_install_rtems_shared_irq_handler (const rtems_irq_connect_data*);
int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* ptr);
/*
* function to get disconnect the RTEMS irq handler for ptr->name.
* This function checks that the value given is the current one for safety reason.
* This function checks that the value given is the current one for safety
* reasons.
* The user can use the previous function to get it.
*/
int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data*);

68
c/src/lib/libbsp/powerpc/shared/irq/irq_init.c
View File

@@ -29,10 +29,6 @@
#include <bsp/motorola.h>
#include <rtems/bspIo.h>
/*
#define SHOW_ISA_PCI_BRIDGE_SETTINGS
*/
typedef struct {
unsigned char bus; /* few chance the PCI/ISA bridge is not on first bus but ... */
unsigned char device;
@@ -68,14 +64,14 @@ static rtems_irq_connect_data defaultIrq = {
};
static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
/*
* actual rpiorities for interrupt :
* actual priorities for interrupt :
* 0 means that only current interrupt is masked
* 255 means all other interrupts are masked
*/
/*
* ISA interrupts.
* The second entry has a priority of 255 because
* it is the slave pic entry and is should always remain
* it is the slave pic entry and should always remain
* unmasked.
*/
0,0,
@@ -91,6 +87,45 @@ static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
0
};
#if defined(mvme2100)
static unsigned char mvme2100_openpic_initpolarities[16] = {
0, /* Not used - should be disabled */
0, /* DEC21143 Controller */
0, /* PMC/PC-MIP Type I Slot 0 */
0, /* PC-MIP Type I Slot 1 */
0, /* PC-MIP Type II Slot 0 */
0, /* PC-MIP Type II Slot 1 */
0, /* Not used - should be disabled */
0, /* PCI Expansion Interrupt A/Universe II (LINT0) */
0, /* PCI Expansion Interrupt B/Universe II (LINT1) */
0, /* PCI Expansion Interrupt C/Universe II (LINT2) */
0, /* PCI Expansion Interrupt D/Universe II (LINT3) */
0, /* Not used - should be disabled */
0, /* Not used - should be disabled */
1, /* 16550 UART */
0, /* Front panel Abort Switch */
0, /* RTC IRQ */
};
static unsigned char mvme2100_openpic_initsenses[] = {
0, /* Not used - should be disabled */
1, /* DEC21143 Controller */
1, /* PMC/PC-MIP Type I Slot 0 */
1, /* PC-MIP Type I Slot 1 */
1, /* PC-MIP Type II Slot 0 */
1, /* PC-MIP Type II Slot 1 */
0, /* Not used - should be disabled */
1, /* PCI Expansion Interrupt A/Universe II (LINT0) */
1, /* PCI Expansion Interrupt B/Universe II (LINT1) */
1, /* PCI Expansion Interrupt C/Universe II (LINT2) */
1, /* PCI Expansion Interrupt D/Universe II (LINT3) */
0, /* Not used - should be disabled */
0, /* Not used - should be disabled */
1, /* 16550 UART */
0, /* Front panel Abort Switch */
1, /* RTC IRQ */
};
#else
static unsigned char mcp750_openpic_initpolarities[16] = {
1, /* 8259 cascade */
0, /* all the rest of them */
@@ -114,6 +149,7 @@ static unsigned char mcp750_openpic_initsenses[] = {
1, /* MCP750_INT_PCI_BUS2_INTC */
1, /* MCP750_INT_PCI_BUS2_INTD */
};
#endif
void VIA_isa_bridge_interrupts_setup(void)
{
@@ -226,17 +262,28 @@ loop_exit:
*/
void BSP_rtems_irq_mng_init(unsigned cpuId)
{
rtems_raw_except_connect_data vectorDesc;
#if !defined(mvme2100)
int known_cpi_isa_bridge = 0;
#endif
rtems_raw_except_connect_data vectorDesc;
int i;
/*
* First initialize the Interrupt management hardware
*/
#if defined(mvme2100)
#ifdef TRACE_IRQ_INIT
printk("Going to initialize EPIC interrupt controller (openpic compliant)\n");
#endif
openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses);
#else
#ifdef TRACE_IRQ_INIT
printk("Going to initialize raven interrupt controller (openpic compliant)\n");
#endif
openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses);
#endif
#if !defined(mvme2100)
#ifdef TRACE_IRQ_INIT
printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
#endif
@@ -261,9 +308,12 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
#ifdef TRACE_IRQ_INIT
printk("Going to initialize the ISA PC legacy IRQ management hardware\n");
#endif
BSP_i8259s_init();
#endif
/*
* Initialize Rtems management interrupt table
* Initialize RTEMS management interrupt table
*/
/*
* re-init the rtemsIrq table
@@ -310,7 +360,7 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
BSP_panic("Unable to initialize RTEMS external raw exception\n");
}
#ifdef TRACE_IRQ_INIT
printk("RTEMS IRQ management is now operationnal\n");
printk("RTEMS IRQ management is now operational\n");
#endif
}

50
c/src/lib/libbsp/powerpc/shared/motorola/motorola.c
View File

@@ -12,7 +12,7 @@
* $Id$
*/
#include <bsp.h>
#include <bsp/motorola.h>
#include <rtems/bspIo.h>
#include <libcpu/io.h>
@@ -20,8 +20,8 @@
/*
** Board-specific table that maps interrupt names to onboard pci
** peripherals as well as local pci busses. This table is used at
** Board-specific table that maps interrupt names to onboard PCI
** peripherals as well as local PCI busses. This table is used at
** bspstart() to configure the interrupt name & pin for all devices that
** do not have it already specified. If the device is already
** configured, we leave it alone but sanity check & print a warning if
@@ -116,12 +116,18 @@ static struct _int_map mtx603_intmap[] = {
NULL_INTMAP };
static struct _int_map mvme2100_intmap[] = {
{0, 0, 0, {{1, {16,-1,-1,-1}}, /* something shows up in slot 0 and OpenPIC */
/* 0 is unused. This hushes the init code. */
NULL_PINMAP}},
{0, 13, 0, {{1, {23,24,25,26}}, /* PCI INT[A-D]/Universe Lint[0-3] */
NULL_PINMAP}},
{0, 14, 0, {{1, {17,-1,-1,-1}}, /* onboard ethernet */
NULL_PINMAP}},
NULL_INTMAP };
/*
* This table represents the standard PCI swizzle defined in the
@@ -141,14 +147,6 @@ static int prep_pci_swizzle(int slot, int pin)
return prep_pci_intpins[ slot % 4 ][ pin-1 ];
}
typedef struct {
/*
* 0x100 mask assumes for Raven and Hawk boards
@@ -163,7 +161,6 @@ typedef struct {
int (*swizzler)(int, int);
} mot_info_t;
static const mot_info_t mot_boards[] = {
{0x300, 0x00, "MVME 2400", NULL, NULL},
{0x010, 0x00, "Genesis", NULL, NULL},
@@ -185,13 +182,13 @@ static const mot_info_t mot_boards[] = {
{0x1E0, 0xFD, "MVME 3600 with MVME712M", NULL, NULL},
{0x1E0, 0xFE, "MVME 3600 with MVME761", NULL, NULL},
{0x1E0, 0xFF, "MVME 1600-001 or 1600-011", NULL, NULL},
{0x000, 0x00, ""}
{0x000, 0x00, ""}, /* end of probeable values for automatic scan */
{0x000, 0x00, "MVME 2100", mvme2100_intmap, prep_pci_swizzle},
};
prep_t currentPrepType;
motorolaBoard currentBoard;
motorolaBoard currentBoard;
prep_t checkPrepBoardType(RESIDUAL *res)
{
prep_t PREP_type;
@@ -213,8 +210,17 @@ prep_t checkPrepBoardType(RESIDUAL *res)
return PREP_type;
}
motorolaBoard getMotorolaBoard()
motorolaBoard getMotorolaBoard()
{
/*
* At least the MVME2100 does not have the CPU Type and Base Type Registers,
* so it cannot be probed.
*
* NOTE: Every path must set currentBoard.
*/
#if defined(mvme2100)
currentBoard = (motorolaBoard) MVME_2100;
#else
unsigned char cpu_type;
unsigned char base_mod;
int entry;
@@ -234,7 +240,7 @@ motorolaBoard getMotorolaBoard()
if (mot_boards[entry].base_type != base_mod)
continue;
else{
else {
mot_entry = entry;
break;
}
@@ -247,6 +253,7 @@ motorolaBoard getMotorolaBoard()
return currentBoard;
}
currentBoard = (motorolaBoard) mot_entry;
#endif
return currentBoard;
}
@@ -261,6 +268,7 @@ const char* motorolaBoardToString(motorolaBoard board)
const struct _int_map *motorolaIntMap(motorolaBoard board)
{
if (board == MOTOROLA_UNKNOWN) return NULL;
/* printk( "IntMap board %d 0x%08x\n", board, mot_boards[board].intmap ); */
return mot_boards[board].intmap;
}

4
c/src/lib/libbsp/powerpc/shared/motorola/motorola.h
View File

@@ -52,6 +52,8 @@ typedef enum {
MVME_3600_W_MVME712M = 17,
MVME_3600_W_MVME761 = 18,
MVME_1600 = 19,
/* In the table, slot 20 is the marker for end of automatic probe and scan */
MVME_2100 = 21,
MOTOROLA_UNKNOWN = 255
} motorolaBoard;
@@ -59,7 +61,7 @@ typedef enum {
HOST_BRIDGE_RAVEN = 0,
HOST_BRIDGE_HAWK = 1,
HOST_BRIDGE_UNKNOWN = 255
}motorolaHostBridge;
} motorolaHostBridge;
#define MOTOROLA_CPUTYPE_REG 0x800
#define MOTOROLA_BASETYPE_REG 0x803

9
c/src/lib/libbsp/powerpc/shared/openpic/openpic.c
View File

@@ -20,12 +20,12 @@
*/
#include <rtems.h>
#include <bsp.h>
#include <rtems/bspIo.h>
#include <bsp/openpic.h>
#include <bsp/pci.h>
#include <libcpu/io.h>
#include <libcpu/byteorder.h>
#include <bsp.h>
#include <rtems/bspIo.h>
#ifndef NULL
@@ -198,7 +198,9 @@ void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses
OPENPIC_VENDOR_ID_STEPPING_SHIFT;
/* Kludge for the Raven */
/*
pci_read_config_dword(0, 0, 0, 0, &t);
*/
if (t == PCI_VENDOR_ID_MOTOROLA + (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) {
vendor = "Motorola";
device = "Raven";
@@ -479,6 +481,11 @@ unsigned long flags;
void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vec, int pol, int sense)
{
#if 0
printk("openpic_initirq: irq=%d pri=%d vec=%d pol=%d sense=%d\n",
irq, pri, vec, pol, sense);
#endif
check_arg_irq(irq);
check_arg_pri(pri);
check_arg_vec(vec);

8
c/src/lib/libbsp/powerpc/shared/openpic/openpic.h
View File

@@ -37,12 +37,15 @@
#ifndef _RTEMS_OPENPIC_H
#define _RTEMS_OPENPIC_H
/*
* OpenPIC supports up to 2048 interrupt sources and up to 32 processors
*/
#if defined(mpc8240) || defined(mpc8245)
#define OPENPIC_MAX_SOURCES (2048 - 16)
#else
#define OPENPIC_MAX_SOURCES 2048
#endif
#define OPENPIC_MAX_PROCESSORS 32
#define OPENPIC_NUM_TIMERS 4
@@ -157,6 +160,9 @@ typedef struct _OpenPIC_Global {
OpenPIC_Reg _Timer_Frequency; /* Read/Write */
OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS];
char Pad1[0xee00];
#if defined(mpc8240) || defined(mpc8245)
char Pad2[0x0200];
#endif
} OpenPIC_Global;

90
c/src/lib/libbsp/powerpc/shared/pci/detect_raven_bridge.c
View File

@@ -12,20 +12,22 @@
#include <bsp/openpic.h>
#include <rtems/bspIo.h>
#include <libcpu/cpuIdent.h>
#define RAVEN_MPIC_IOSPACE_ENABLE 0x1
#define RAVEN_MPIC_MEMSPACE_ENABLE 0x2
#define RAVEN_MASTER_ENABLE 0x4
#define RAVEN_PARITY_CHECK_ENABLE 0x40
#define RAVEN_SYSTEM_ERROR_ENABLE 0x100
#define RAVEN_CLEAR_EVENTS_MASK 0xf9000000
#define RAVEN_MPIC_IOSPACE_ENABLE 0x0001
#define RAVEN_MPIC_MEMSPACE_ENABLE 0x0002
#define RAVEN_MASTER_ENABLE 0x0004
#define RAVEN_PARITY_CHECK_ENABLE 0x0040
#define RAVEN_SYSTEM_ERROR_ENABLE 0x0100
#define RAVEN_CLEAR_EVENTS_MASK 0xf9000000
#define RAVEN_MPIC_MEREN ((volatile unsigned *)0xfeff0020)
#define RAVEN_MPIC_MERST ((volatile unsigned *)0xfeff0024)
#define RAVEN_MPIC_MEREN ((volatile unsigned *)0xfeff0020)
#define RAVEN_MPIC_MERST ((volatile unsigned *)0xfeff0024)
/* enable machine check on all conditions */
#define MEREN_VAL 0x2f00
#define MEREN_VAL 0x2f00
#define pci BSP_pci_configuration
extern unsigned int EUMBBAR;
extern const pci_config_access_functions pci_direct_functions;
extern const pci_config_access_functions pci_indirect_functions;
@@ -35,25 +37,39 @@ _BSP_clear_hostbridge_errors(int enableMCP, int quiet)
{
unsigned merst;
merst = in_be32(RAVEN_MPIC_MERST);
/* write back value to clear status */
out_be32(RAVEN_MPIC_MERST, merst);
merst = in_be32(RAVEN_MPIC_MERST);
/* write back value to clear status */
out_be32(RAVEN_MPIC_MERST, merst);
if (enableMCP) {
if (!quiet)
printk("Enabling MCP generation on hostbridge errors\n");
out_be32(RAVEN_MPIC_MEREN, MEREN_VAL);
} else {
out_be32(RAVEN_MPIC_MEREN, 0);
if ( !quiet && enableMCP ) {
printk("leaving MCP interrupt disabled\n");
}
}
return (merst & 0xffff);
if (enableMCP) {
if (!quiet)
printk("Enabling MCP generation on hostbridge errors\n");
out_be32(RAVEN_MPIC_MEREN, MEREN_VAL);
} else {
out_be32(RAVEN_MPIC_MEREN, 0);
if ( !quiet && enableMCP ) {
printk("leaving MCP interrupt disabled\n");
}
}
return (merst & 0xffff);
}
void detect_host_bridge()
{
#if (defined(mpc8240) || defined(mpc8245))
/*
* If the processor is an 8240 or an 8245 then the PIC is built
* in instead of being on the PCI bus. The MVME2100 is using Processor
* Address Map B (CHRP) although the Programmer's Reference Guide says
* it defaults to Map A.
*/
/* We have an EPIC Interrupt Controller */
OpenPIC = (volatile struct OpenPIC *) (EUMBBAR + BSP_OPEN_PIC_BASE_OFFSET);
pci.pci_functions = &pci_indirect_functions;
pci.pci_config_addr = (volatile unsigned char *) 0xfec00000;
pci.pci_config_data = (volatile unsigned char *) 0xfee00000;
#else
PPC_DEVICE *hostbridge;
unsigned int id0;
unsigned int tmp;
@@ -65,8 +81,9 @@ void detect_host_bridge()
* (still used in BSD source code) works.
*/
hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL,
BridgeController,
PCIBridge, -1, 0);
BridgeController,
PCIBridge, -1, 0);
if (hostbridge) {
if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) {
pci.pci_functions=&pci_indirect_functions;
@@ -76,7 +93,7 @@ void detect_host_bridge()
* this case anyway.
*/
pci.pci_config_addr = ((volatile unsigned char *)
(ptr_mem_map->io_base+0xcf8));
(ptr_mem_map->io_base+0xcf8));
pci.pci_config_data = ptr_mem_map->io_base+0xcfc;
} else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) {
pci.pci_functions=&pci_direct_functions;
@@ -88,13 +105,14 @@ void detect_host_bridge()
pci.pci_functions = &pci_direct_functions;
/* On all direct bridges I know the host bridge itself
* appears as device 0 function 0.
*/
*/
pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0);
if (id0==~0U) {
pci.pci_functions = &pci_indirect_functions;
pci.pci_config_addr = ((volatile unsigned char*)
(ptr_mem_map->io_base+0xcf8));
pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc);
pci.pci_config_addr = (volatile unsigned char*)
(ptr_mem_map->io_base+0xcf8);
pci.pci_config_data = (volatile unsigned char*)
(ptr_mem_map->io_base+0xcfc);
}
/* Here we should check that the host bridge is actually
* present, but if it not, we are in such a desperate
@@ -102,6 +120,7 @@ void detect_host_bridge()
*/
}
pci_read_config_dword(0, 0, 0, 0, &id0);
if(id0 == PCI_VENDOR_ID_MOTOROLA +
(PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) {
/*
@@ -121,21 +140,22 @@ void detect_host_bridge()
if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) {
pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp);
#ifdef SHOW_RAVEN_SETTING
printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1));
printk("Raven MPIC is accessed via IO Space Access at address : %x\n",
(tmp & ~0x1));
#endif
}
if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) {
pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp);
#ifdef SHOW_RAVEN_SETTING
printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp);
printk("Raven MPIC is accessed via memory Space Access"
"at address : %x\n", tmp)
#endif
OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE);
printk("OpenPIC found at %x.\n",
OpenPIC);
printk("OpenPIC found at %x.\n", OpenPIC);
}
}
#endif
if (OpenPIC == (volatile struct OpenPIC *)0) {
BSP_panic("OpenPic Not found\n");
}
}

27
c/src/lib/libbsp/powerpc/shared/pci/pci.c
View File

@@ -1,9 +1,9 @@
/*
* pci.c : this file contains basic PCI Io functions.
*
* CopyRight (C) 1999 valette@crf.canon.fr
* Copyright (C) 1999 valette@crf.canon.fr
*
* This code is heavilly inspired by the public specification of STREAM V2
* This code is heavily inspired by the public specification of STREAM V2
* that can be found at :
*
* <http://www.chorus.com/Documentation/index.html> by following
@@ -217,17 +217,6 @@ const pci_config_access_functions pci_direct_functions = {
};
#define PRINT_MSG() \
printk("pci : Device %d:%02x routed to interrupt_line %d\n", pbus, pslot, int_name )
@@ -236,9 +225,15 @@ const pci_config_access_functions pci_direct_functions = {
** Validate a test interrupt name and print a warning if its not one of
** the names defined in the routing record.
*/
static int test_intname( struct _int_map *row, int pbus, int pslot, int int_pin, int int_name )
static int test_intname(
const struct _int_map *row,
int pbus,
int pslot,
int int_pin,
int int_name
)
{
int j,k;
int j, k;
int _nopin= -1, _noname= -1;
for(j=0; row->pin_route[j].pin > -1; j++)
@@ -333,7 +328,7 @@ static int FindPCIbridge( int mybus, struct pcibridge *pb )
void FixupPCI( struct _int_map *bspmap, int (*swizzler)(int,int) )
void FixupPCI( const struct _int_map *bspmap, int (*swizzler)(int,int) )
{
unsigned char cvalue;
unsigned16 devid;

2
c/src/lib/libbsp/powerpc/shared/pci/pci.h
View File

@@ -1164,7 +1164,7 @@ struct _int_map
struct _pin_routes pin_route[5];
};
void FixupPCI( struct _int_map *, int (*swizzler)(int,int) );
void FixupPCI( const struct _int_map *, int (*swizzler)(int,int) );
/* scan for a specific device */

27
c/src/lib/libbsp/powerpc/shared/start/start.S
View File

@@ -14,6 +14,7 @@
#include <asm.h>
#include <rtems/score/cpu.h>
#include <libcpu/io.h>
#include <bspopts.h>
#define SYNC \
sync; \
@@ -28,7 +29,6 @@
li r10,0x63 ; \
sc
.text
.globl __rtems_entry_point
.type __rtems_entry_point,@function
@@ -67,13 +67,24 @@ __rtems_entry_point:
* of RAM to KERNELBASE.
*/
lis r11,KERNELBASE@h
ori r11,r11,0x1ffe /* set up BAT registers for 604 */
/* set up BAT registers for 604 */
ori r11,r11,0x1ffe
li r8,2 /* R/W access */
isync
#if defined(mvme2100)
/* BSP_vme_config() wants to use BAT0, this board will use the
* available BAT1 to map RAM.
*/
mtspr DBAT1L,r8 /* N.B. 6xx (not 601) have valid */
mtspr DBAT1U,r11 /* bit in upper BAT register */
mtspr IBAT1L,r8
mtspr IBAT1U,r11
#else
mtspr DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
mtspr DBAT0U,r11 /* bit in upper BAT register */
mtspr IBAT0L,r8
mtspr IBAT0U,r11
#endif
isync
/*
@@ -87,7 +98,7 @@ __rtems_entry_point:
enter_C_code:
bl MMUon
bl __eabi /* setup EABI and SYSV environment */
bl __eabi /* setup EABI and SYSV environment */
bl zero_bss
/*
* restore prep boot params
@@ -105,7 +116,8 @@ enter_C_code:
addi r9,r9, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@l
mr r1, r9
/*
* We are know in a environment that is totally independent from bootloader setup.
* We are now in a environment that is totally independent from
* bootloader setup.
*/
lis r5,environ@ha
la r5,environ@l(r5) /* environp */
@@ -118,11 +130,14 @@ enter_C_code:
.type MMUon,@function
MMUon:
mfmsr r0
#if (PPC_HAS_FPU == 0)
ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
#if defined(mvme2100)
/* Data addr translation is broken for the mvme2100, disable it here */
xori r0,r0, MSR_DR
#endif
#if (PPC_HAS_FPU == 0)
xori r0, r0, MSR_EE | MSR_IP | MSR_FP
#else
ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
xori r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1
#endif
mflr r11

245
c/src/lib/libbsp/powerpc/shared/startup/bspstart.c
View File

@@ -19,6 +19,7 @@
#include <string.h>
#include <bsp.h>
#include <rtems/libio.h>
#include <rtems/libcsupport.h>
#include <bsp/consoleIo.h>
@@ -28,7 +29,6 @@
#include <bsp/openpic.h>
#include <bsp/irq.h>
#include <bsp/VME.h>
#include <bsp.h>
#include <libcpu/bat.h>
#include <libcpu/pte121.h>
#include <libcpu/cpuIdent.h>
@@ -48,6 +48,41 @@ extern void BSP_vme_config();
SPR_RW(SPRG0)
SPR_RW(SPRG1)
#if defined(DEBUG_BATS)
void printBAT( int bat, unsigned32 upper, unsigned32 lower )
{
unsigned32 lowest_addr;
unsigned32 size;
printk("BAT%d raw(upper=0x%08x, lower=0x%08x) ", bat, upper, lower );
lowest_addr = (upper & 0xFFFE0000);
size = (((upper & 0x00001FFC) >> 2) + 1) * (128 * 1024);
printk(" range(0x%08x, 0x%08x) %s%s %s%s%s%s %s\n",
lowest_addr,
lowest_addr + (size - 1),
(upper & 0x01) ? "P" : "p",
(upper & 0x02) ? "S" : "s",
(lower & 0x08) ? "G" : "g",
(lower & 0x10) ? "M" : "m",
(lower & 0x20) ? "I" : "i",
(lower & 0x40) ? "W" : "w",
(lower & 0x01) ? "Read Only" :
((lower & 0x02) ? "Read/Write" : "No Access")
);
}
void ShowBATS(){
unsigned32 lower;
unsigned32 upper;
__MFSPR(536, upper); __MFSPR(537, lower); printBAT( 0, upper, lower );
__MFSPR(538, upper); __MFSPR(539, lower); printBAT( 1, upper, lower );
__MFSPR(540, upper); __MFSPR(541, lower); printBAT( 2, upper, lower );
__MFSPR(542, upper); __MFSPR(543, lower); printBAT( 3, upper, lower );
}
#endif
/*
* Copy of residuals passed by firmware
*/
@@ -130,28 +165,28 @@ void bsp_libc_init( void *, unsigned32, int );
void bsp_pretasking_hook(void)
{
rtems_unsigned32 heap_start;
rtems_unsigned32 heap_size;
rtems_unsigned32 heap_sbrk_spared;
extern rtems_unsigned32 _bsp_sbrk_init(rtems_unsigned32, rtems_unsigned32*);
rtems_unsigned32 heap_start;
rtems_unsigned32 heap_size;
rtems_unsigned32 heap_sbrk_spared;
extern rtems_unsigned32 _bsp_sbrk_init(rtems_unsigned32, rtems_unsigned32*);
heap_start = ((rtems_unsigned32) __rtems_end) +INIT_STACK_SIZE + INTR_STACK_SIZE;
if (heap_start & (CPU_ALIGNMENT-1))
heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
heap_start = ((rtems_unsigned32) __rtems_end) +
INIT_STACK_SIZE + INTR_STACK_SIZE;
if (heap_start & (CPU_ALIGNMENT-1))
heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size;
heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size);
heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size;
heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size);
#ifdef SHOW_MORE_INIT_SETTINGS
printk(" HEAP start %x size %x (%x bytes spared for sbrk)\n", heap_start, heap_size, heap_sbrk_spared);
printk( "HEAP start %x size %x (%x bytes spared for sbrk)\n",
heap_start, heap_size, heap_sbrk_spared);
#endif
bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared);
bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared);
#ifdef RTEMS_DEBUG
rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
#endif
}
@@ -173,6 +208,33 @@ void save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_op
loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0';
}
#if defined(mpc8240) || defined(mpc8245)
unsigned int EUMBBAR;
/*
* Return the current value of the Embedded Utilities Memory Block Base Address
* Register (EUMBBAR) as read from the processor configuration register using
* Processor Address Map B (CHRP).
*/
unsigned int get_eumbbar() {
register int a, e;
asm volatile( "lis %0,0xfec0; ori %0,%0,0x0000": "=r" (a) );
asm volatile("sync");
asm volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) );
asm volatile("stwbrx %0,0x0,%1": "=r"(e): "r"(a));
asm volatile("sync");
asm volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) );
asm volatile("sync");
asm volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a));
asm volatile("isync");
return e;
}
#endif
/*
* bsp_start
*
@@ -181,9 +243,10 @@ void save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_op
void bsp_start( void )
{
int err;
unsigned char *stack;
#if !defined(mpc8240) && !defined(mpc8245)
unsigned l2cr;
#endif
register unsigned char* intrStack;
unsigned char *work_space_start;
ppc_cpu_id_t myCpu;
@@ -191,17 +254,30 @@ void bsp_start( void )
prep_t boardManufacturer;
motorolaBoard myBoard;
Triv121PgTbl pt=0;
select_console(CONSOLE_SERIAL);
/*
* Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
* store the result in global variables so that it can be used latter...
* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
* function store the result in global variables so that it can be used
* later...
*/
myCpu = get_ppc_cpu_type();
myCpuRevision = get_ppc_cpu_revision();
#if defined(mvme2100)
EUMBBAR = get_eumbbar();
Cpu_table.exceptions_in_RAM = TRUE;
{ unsigned v = 0x3000 ; _CPU_MSR_SET(v); }
#endif
#if !defined(mpc8240) && !defined(mpc8245)
/*
* enables L1 Cache. Note that the L1_caches_enables() codes checks for
* relevant CPU type so that the reason why there is no use of myCpu...
*/
L1_caches_enables();
/*
* Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
* relevant CPU type (mpc750)...
@@ -212,24 +288,28 @@ void bsp_start( void )
#endif
if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1))
set_L2CR(0xb9A14000);
#endif
/*
* the initial stack has aready been set to this value in start.S
* the initial stack has already been set to this value in start.S
* so there is no need to set it in r1 again... It is just for info
* so that It can be printed without accessing R1.
*/
stack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
stack = ((unsigned char*) __rtems_end) +
INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
/* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
/* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
*((unsigned32 *)stack) = 0;
/*
* Initialize the interrupt related settings
* SPRG1 = software managed IRQ stack
*
* This could be done latter (e.g in IRQ_INIT) but it helps to understand
* This could be done later (e.g in IRQ_INIT) but it helps to understand
* some settings below...
*/
intrStack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
intrStack = ((unsigned char*) __rtems_end) +
INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
/* make sure it's properly aligned */
(unsigned32)intrStack &= ~(CPU_STACK_ALIGNMENT-1);
@@ -243,38 +323,47 @@ void bsp_start( void )
_write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
/*
* Initialize default raw exception hanlders. See vectors/vectors_init.c
* Initialize default raw exception handlers. See vectors/vectors_init.c
*/
initialize_exceptions();
/*
* Init MMU block address translation to enable hardware
* access
* Init MMU block address translation to enable hardware access
*/
#if !defined(mvme2100)
/*
* PC legacy IO space used for inb/outb and all PC
* compatible hardware
* PC legacy IO space used for inb/outb and all PC compatible hardware
*/
setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
#endif
/*
* PCI devices memory area. Needed to access OPENPIC features
* provided by the RAVEN
*/
/* T. Straumann: give more PCI address space */
setdbat(2, PCI_MEM_BASE, PCI_MEM_BASE, 0x10000000, IO_PAGE);
/*
* Must have acces to open pic PCI ACK registers
* provided by the RAVEN
* PCI devices memory area. Needed to access OpenPIC features
* provided by the Raven
*
* T. Straumann: give more PCI address space
*/
setdbat(2, PCI_MEM_BASE, PCI_MEM_BASE, 0x10000000, IO_PAGE);
/*
* Must have access to OpenPIC PCI ACK registers provided by the Raven
*/
setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
select_console(CONSOLE_LOG);
/* We check that the keyboard is present and immediately
/*
* We check that the keyboard is present and immediately
* select the serial console if not.
*/
err = kbdreset();
if (err) select_console(CONSOLE_SERIAL);
#if defined(BSP_KBD_IOBASE)
{ int err;
err = kbdreset();
if (err) select_console(CONSOLE_SERIAL);
}
#else
select_console(CONSOLE_SERIAL);
#endif
boardManufacturer = checkPrepBoardType(&residualCopy);
if (boardManufacturer != PREP_Motorola) {
@@ -284,7 +373,8 @@ void bsp_start( void )
myBoard = getMotorolaBoard();
printk("-----------------------------------------\n");
printk("Welcome to %s on %s\n", _RTEMS_version, motorolaBoardToString(myBoard));
printk("Welcome to %s on %s\n", _RTEMS_version,
motorolaBoardToString(myBoard));
printk("-----------------------------------------\n");
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Residuals are located at %x\n", (unsigned) &residualCopy);
@@ -308,18 +398,17 @@ void bsp_start( void )
#endif
InitializePCI();
{
struct _int_map *bspmap = motorolaIntMap(currentBoard);
if( bspmap )
{
printk("pci : Configuring interrupt routing for '%s'\n", motorolaBoardToString(currentBoard));
{
const struct _int_map *bspmap = motorolaIntMap(currentBoard);
if( bspmap ) {
printk("pci : Configuring interrupt routing for '%s'\n",
motorolaBoardToString(currentBoard));
FixupPCI(bspmap, motorolaIntSwizzle(currentBoard) );
}
else
printk("pci : Interrupt routing not available for this bsp\n");
}
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Number of PCI buses found is : %d\n", BusCountPCI());
#endif
@@ -330,25 +419,31 @@ void bsp_start( void )
*/
__asm__ __volatile ("sc");
/*
* Check we can still catch exceptions and returned coorectly.
* Check we can still catch exceptions and return correctly.
*/
printk("Testing exception handling Part 2\n");
__asm__ __volatile ("sc");
/*
* Somehow doing the above seems to clobber SPRG0 on the mvme2100. It
* is probably a not so subtle hint that you do not want to use PPCBug
* once RTEMS is up and running. Anyway, we still needs to indicate
* that we have fixed PR288. Eventually, this should go away.
*/
_write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
#endif
BSP_mem_size = residualCopy.TotalMemory;
BSP_bus_frequency = residualCopy.VitalProductData.ProcessorBusHz;
BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz;
BSP_time_base_divisor = (residualCopy.VitalProductData.TimeBaseDivisor?
residualCopy.VitalProductData.TimeBaseDivisor : 4000);
BSP_mem_size = residualCopy.TotalMemory;
BSP_bus_frequency = residualCopy.VitalProductData.ProcessorBusHz;
BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz;
BSP_time_base_divisor = (residualCopy.VitalProductData.TimeBaseDivisor?
residualCopy.VitalProductData.TimeBaseDivisor : 4000);
/* clear hostbridge errors but leave MCP disabled -
* PCI config space scanning code will trip otherwise :-(
*/
_BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/);
/* Allocate and set up the page table mappings
* This is only available on >604 CPUs.
*
@@ -358,16 +453,11 @@ void bsp_start( void )
*/
pt = BSP_pgtbl_setup(&BSP_mem_size);
if (!pt ||
TRIV121_MAP_SUCCESS != triv121PgTblMap(
pt,
TRIV121_121_VSID,
0xfeff0000,
1,
TRIV121_ATTR_IO_PAGE,
TRIV121_PP_RW_PAGE
)) {
printk("WARNING: unable to setup page tables VME bridge must share PCI space\n");
if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap(
pt, TRIV121_121_VSID, 0xfeff0000, 1,
TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) {
printk("WARNING: unable to setup page tables VME "
"bridge must share PCI space\n");
}
/*
@@ -384,12 +474,14 @@ void bsp_start( void )
Cpu_table.exceptions_in_RAM = TRUE;
#ifdef SHOW_MORE_INIT_SETTINGS
printk("BSP_Configuration.work_space_size = %x\n", BSP_Configuration.work_space_size);
printk("BSP_Configuration.work_space_size = %x\n",
BSP_Configuration.work_space_size);
#endif
work_space_start =
(unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size;
if ( work_space_start <= ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) {
if ( work_space_start <=
((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) {
printk( "bspstart: Not enough RAM!!!\n" );
bsp_cleanup();
}
@@ -401,7 +493,6 @@ void bsp_start( void )
*/
BSP_rtems_irq_mng_init(0);
/* Activate the page table mappings only after
* initializing interrupts because the irq_mng_init()
* routine needs to modify the text
@@ -411,23 +502,27 @@ void bsp_start( void )
printk("Page table setup finished; will activate it NOW...\n");
#endif
BSP_pgtbl_activate(pt);
/* finally, switch off DBAT3 */
setdbat(3, 0, 0, 0, 0);
/* finally, switch off DBAT3 */
setdbat(3, 0, 0, 0, 0);
}
/*
* Initialize VME bridge - needs working PCI
* and IRQ subsystems...
* Initialize VME bridge - needs working PCI and IRQ subsystems...
*/
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Going to initialize VME bridge\n");
#endif
/* VME initialization is in a separate file so apps which don't use
* VME or want a different configuration may link against a customized
* routine.
/*
* VME initialization is in a separate file so apps which don't use VME or
* want a different configuration may link against a customized routine.
*/
BSP_vme_config();
#if defined(DEBUG_BATS)
ShowBATS();
#endif
#ifdef SHOW_MORE_INIT_SETTINGS
printk("Exit from bspstart\n");
#endif

2
c/src/lib/libbsp/powerpc/shared/tod/.cvsignore Normal file
View File

@@ -0,0 +1,2 @@
Makefile
Makefile.in

12
c/src/lib/libbsp/powerpc/shared/tod/Makefile.am Normal file
View File

@@ -0,0 +1,12 @@
##
## $Id$
##
C_FILES = todcfg.c
all-local:
EXTRA_DIST = todcfg.c
include $(top_srcdir)/../../../../../automake/local.am

69
c/src/lib/libbsp/powerpc/shared/tod/todcfg.c Normal file
View File

@@ -0,0 +1,69 @@
/*
* This file contains the RTC driver table for Motorola shared BSPs.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
* $Id$
*/
#include <bsp.h>
#include <libchip/rtc.h>
#include <libchip/m48t08.h>
/* Forward function declaration */
#if !defined(mvme2100)
unsigned32 mvmertc_get_register( unsigned32, unsigned8 );
void mvmertc_set_register( unsigned32, unsigned8, unsigned32 );
#endif
/* The following table configures the RTC drivers used in this BSP */
rtc_tbl RTC_Table[] = {
{
"/dev/rtc", /* sDeviceName */
RTC_M48T08, /* deviceType -- actually M48T59 */
&m48t08_fns, /* pDeviceFns */
rtc_probe, /* deviceProbe */
NULL, /* pDeviceParams */
#if defined(mvme2100)
0xFFE81ff8, /* ulCtrlPort1 */
0x00, /* ulDataPort */
m48t08_get_register, /* getRegister */
m48t08_set_register /* setRegister */
#else
0xFFE81ff8, /* ulCtrlPort1 */
0x00, /* ulDataPort */
mvmertc_get_register, /* getRegister */
mvmertc_set_register /* setRegister */
#endif
}
};
/* Some information used by the RTC driver */
#define NUM_RTCS (sizeof(RTC_Table)/sizeof(rtc_tbl))
unsigned long RTC_Count = NUM_RTCS;
rtems_device_minor_number RTC_Minor;
#if !defined(mvme2100)
#include <rtems/bspIo.h>
void mvmertc_set_register(
unsigned32 base,
unsigned8 reg,
unsigned32 value
)
{
printk( "RTC SUPPORT NOT IMPLEMENTED ON THIS BOARD\n");
}
unsigned32 mvmertc_get_register(
unsigned32 base,
unsigned8 reg
)
{
printk( "RTC SUPPORT NOT IMPLEMENTED ON THIS BOARD\n");
}
#endif

2
c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c
View File

@@ -175,7 +175,9 @@ void initialize_exceptions()
if (!mpc60x_init_exceptions(&exception_config)) {
BSP_panic("Exception handling initialization failed\n");
}
#ifdef RTEMS_DEBUG
else {
printk("Exception handling initialization done\n");
}
#endif
}

12
c/src/lib/libbsp/powerpc/shared/vme/vmeconfig.c
View File

@@ -34,23 +34,17 @@ union {
unsigned long batbits;
} dbat0u;
if (currentBoard < MVME_2300 || currentBoard >= MVME_1600) {
printk("VME bridge for this board is unknown - if it's a Tundra Universe, add the board to 'shared/vme/vmeconfig.c'\n");
printk("Skipping VME initialization...\n");
return;
}
vmeUniverseInit();
vmeUniverseReset();
/* setup a PCI area to map the VME bus */
dbat0u.batbits = _read_DBAT0U();
/* if we have page tables, BAT0 is available */
if (dbat0u.bat.vs || dbat0u.bat.vp) {
printk("WARNING: BAT0 is taken (no pagetables?); VME bridge must share PCI range for VME access\n");
printk("Skipping VME initialization...\n");
printk("WARNING: BAT0 is taken (no pagetables?); "
"VME bridge must share PCI range for VME access\n"
"Skipping VME initialization...\n");
return;
}