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Joel Sherrill
1999-12-21 17:05:15 +00:00
parent 8437abd4f0
commit a3ba9f9886
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39
c/src/lib/libbsp/powerpc/mcp750/README.MVME2300 Normal file
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This BSP was adapted from Eric Valette MCP750 Generic motorola
port to MVME2300 by Jay Kulpinski <jskulpin@eng01.gdds.com>.
In other to work correctly, the Tundra Universe chip must
be turned off using PPCBug as explained below.
The Tundra Universe chip is a bridge between the PCI and VME buses.
It has four programmable mapping windows in each direction, much like
the Raven. PPCBUG lets you specify the mappings if you don't want
to do it in your application. The mappings on our board, which may
or not be the default Motorola mappings, had one window appearing
at 0x01000000 in PCI space. This is the same place the bootloader
code remapped the Raven registers. The windows' mappings are
very likely to be application specific, so I wouldn't worry too
much about setting them in the BSP, but it would be nice to have
a standard interface to do so. Whoever needs that first can
incorporate the ppcn_60x BSP code for the Universe chip. :-)
These options in PPCBUG's ENV command did the job:
VME3PCI Master Master Enable [Y/N] = Y?
PCI Slave Image 0 Control = 00000000? <-----
PCI Slave Image 0 Base Address Register = 00000000?
PCI Slave Image 0 Bound Address Register = 00000000?
PCI Slave Image 0 Translation Offset = 00000000?
PCI Slave Image 1 Control = 00000000? <-----
PCI Slave Image 1 Base Address Register = 01000000?
PCI Slave Image 1 Bound Address Register = 20000000?
PCI Slave Image 1 Translation Offset = 00000000?
PCI Slave Image 2 Control = 00000000? <-----
PCI Slave Image 2 Base Address Register = 20000000?
PCI Slave Image 2 Bound Address Register = 22000000?
PCI Slave Image 2 Translation Offset = D0000000?
PCI Slave Image 3 Control = 00000000? <-----
PCI Slave Image 3 Base Address Register = 2FFF0000?
PCI Slave Image 3 Bound Address Register = 30000000?
PCI Slave Image 3 Translation Offset = D0000000?

39
c/src/lib/libbsp/powerpc/motorola_powerpc/README.MVME2300 Normal file
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This BSP was adapted from Eric Valette MCP750 Generic motorola
port to MVME2300 by Jay Kulpinski <jskulpin@eng01.gdds.com>.
In other to work correctly, the Tundra Universe chip must
be turned off using PPCBug as explained below.
The Tundra Universe chip is a bridge between the PCI and VME buses.
It has four programmable mapping windows in each direction, much like
the Raven. PPCBUG lets you specify the mappings if you don't want
to do it in your application. The mappings on our board, which may
or not be the default Motorola mappings, had one window appearing
at 0x01000000 in PCI space. This is the same place the bootloader
code remapped the Raven registers. The windows' mappings are
very likely to be application specific, so I wouldn't worry too
much about setting them in the BSP, but it would be nice to have
a standard interface to do so. Whoever needs that first can
incorporate the ppcn_60x BSP code for the Universe chip. :-)
These options in PPCBUG's ENV command did the job:
VME3PCI Master Master Enable [Y/N] = Y?
PCI Slave Image 0 Control = 00000000? <-----
PCI Slave Image 0 Base Address Register = 00000000?
PCI Slave Image 0 Bound Address Register = 00000000?
PCI Slave Image 0 Translation Offset = 00000000?
PCI Slave Image 1 Control = 00000000? <-----
PCI Slave Image 1 Base Address Register = 01000000?
PCI Slave Image 1 Bound Address Register = 20000000?
PCI Slave Image 1 Translation Offset = 00000000?
PCI Slave Image 2 Control = 00000000? <-----
PCI Slave Image 2 Base Address Register = 20000000?
PCI Slave Image 2 Bound Address Register = 22000000?
PCI Slave Image 2 Translation Offset = D0000000?
PCI Slave Image 3 Control = 00000000? <-----
PCI Slave Image 3 Base Address Register = 2FFF0000?
PCI Slave Image 3 Bound Address Register = 30000000?
PCI Slave Image 3 Translation Offset = D0000000?

119
c/src/lib/libbsp/shared/include/coverhd.h Normal file
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/* coverhd.h
*
* This include file has defines to represent the overhead associated
* with calling a particular directive from C. These are used in the
* Timing Test Suite to ignore the overhead required to pass arguments
* to directives. On some CPUs and/or target boards, this overhead
* is significant and makes it difficult to distinguish internal
* RTEMS execution time from that used to call the directive.
* This file should be updated after running the C overhead timing
* test. Once this update has been performed, the RTEMS Time Test
* Suite should be rebuilt to account for these overhead times in the
* timing results.
*
* NOTE: If these are all zero, then the times reported include
* calling overhead including passing of arguments.
*
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id$
*/
#ifndef __COVERHD_h
#define __COVERHD_h
#ifdef __cplusplus
extern "C" {
#endif
#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0
#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0
#define CALLING_OVERHEAD_TASK_CREATE 0
#define CALLING_OVERHEAD_TASK_IDENT 0
#define CALLING_OVERHEAD_TASK_START 0
#define CALLING_OVERHEAD_TASK_RESTART 0
#define CALLING_OVERHEAD_TASK_DELETE 0
#define CALLING_OVERHEAD_TASK_SUSPEND 0
#define CALLING_OVERHEAD_TASK_RESUME 0
#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0
#define CALLING_OVERHEAD_TASK_MODE 0
#define CALLING_OVERHEAD_TASK_GET_NOTE 0
#define CALLING_OVERHEAD_TASK_SET_NOTE 0
#define CALLING_OVERHEAD_TASK_WAKE_WHEN 0
#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0
#define CALLING_OVERHEAD_INTERRUPT_CATCH 0
#define CALLING_OVERHEAD_CLOCK_GET 0
#define CALLING_OVERHEAD_CLOCK_SET 0
#define CALLING_OVERHEAD_CLOCK_TICK 0
#define CALLING_OVERHEAD_TIMER_CREATE 0
#define CALLING_OVERHEAD_TIMER_IDENT 0
#define CALLING_OVERHEAD_TIMER_DELETE 0
#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 0
#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 0
#define CALLING_OVERHEAD_TIMER_RESET 0
#define CALLING_OVERHEAD_TIMER_CANCEL 0
#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0
#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0
#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0
#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0
#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0
#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0
#define CALLING_OVERHEAD_EVENT_SEND 0
#define CALLING_OVERHEAD_EVENT_RECEIVE 0
#define CALLING_OVERHEAD_SIGNAL_CATCH 0
#define CALLING_OVERHEAD_SIGNAL_SEND 0
#define CALLING_OVERHEAD_PARTITION_CREATE 0
#define CALLING_OVERHEAD_PARTITION_IDENT 0
#define CALLING_OVERHEAD_PARTITION_DELETE 0
#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0
#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0
#define CALLING_OVERHEAD_REGION_CREATE 0
#define CALLING_OVERHEAD_REGION_IDENT 0
#define CALLING_OVERHEAD_REGION_DELETE 0
#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0
#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0
#define CALLING_OVERHEAD_PORT_CREATE 0
#define CALLING_OVERHEAD_PORT_IDENT 0
#define CALLING_OVERHEAD_PORT_DELETE 0
#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0
#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0
#define CALLING_OVERHEAD_IO_INITIALIZE 0
#define CALLING_OVERHEAD_IO_OPEN 0
#define CALLING_OVERHEAD_IO_CLOSE 0
#define CALLING_OVERHEAD_IO_READ 0
#define CALLING_OVERHEAD_IO_WRITE 0
#define CALLING_OVERHEAD_IO_CONTROL 0
#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0
#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0
#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0
#ifdef __cplusplus
}
#endif
#endif
/* end of include file */