mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2025-11-16 12:34:45 +00:00
2008-10-02 Joel Sherrill <joel.sherrill@OARcorp.com>
* console/init68360.c: Delete unused code.
This commit is contained in:
Joel Sherrill
@@ -1,3 +1,7 @@
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2008-10-02 Joel Sherrill <joel.sherrill@OARcorp.com>
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* console/init68360.c: Delete unused code.
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2008-09-29 Ralf Corsépius <ralf.corsepius@rtems.org>
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* Makefile.am: Remove noinst_PROGRAMS (Unused).
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@@ -35,636 +35,3 @@ void M360ExecuteRISC( volatile m360_t *m360, uint16_t command)
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m360->cr = command | M360_CR_FLG;
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rtems_interrupt_enable(sr);
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}
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#if 0
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/*
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* Initialize MC68360
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*/
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void _Init68360 (void)
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{
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int i;
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m68k_isr_entry *vbr;
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unsigned long ramSize;
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extern void _CopyDataClearBSSAndStart (unsigned long ramSize);
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#if (defined (__mc68040__))
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/*
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*******************************************
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* Motorola 68040 and companion-mode 68360 *
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*******************************************
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*/
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/*
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* Step 6: Is this a power-up reset?
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* For now we just ignore this and do *all* the steps
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* Someday we might want to:
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* if (Hard, Loss of Clock, Power-up)
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* Do all steps
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* else if (Double bus fault, watchdog or soft reset)
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* Skip to step 12
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* else (must be a reset command)
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* Skip to step 14
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*/
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/*
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* Step 7: Deal with clock synthesizer
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* HARDWARE:
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* Change if you're not using an external 25 MHz oscillator.
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*/
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m360.clkocr = 0x83; /* No more writes, full-power CLKO2 */
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m360.pllcr = 0xD000; /* PLL, no writes, no prescale,
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no LPSTOP slowdown, PLL X1 */
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m360.cdvcr = 0x8000; /* No more writes, no clock division */
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/*
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* Step 8: Initialize system protection
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* Enable watchdog
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* Watchdog causes system reset
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* Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
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* Enable double bus fault monitor
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* Enable bus monitor for external cycles
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* 1024 clocks for external timeout
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*/
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m360.sypcr = 0xEC;
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/*
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* Step 9: Clear parameter RAM and reset communication processor module
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*/
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for (i = 0 ; i < 192 ; i += sizeof (long)) {
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*((long *)((char *)&m360 + 0xC00 + i)) = 0;
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*((long *)((char *)&m360 + 0xD00 + i)) = 0;
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*((long *)((char *)&m360 + 0xE00 + i)) = 0;
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*((long *)((char *)&m360 + 0xF00 + i)) = 0;
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}
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M360ExecuteRISC (M360_CR_RST);
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/*
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* Step 10: Write PEPAR
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* SINTOUT standard M68000 family interrupt level encoding
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* CF1MODE=10 (BCLRO* output)
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* No RAS1* double drive
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* A31 - A28
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* AMUX output
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* CAS2* - CAS3*
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* CAS0* - CAS1*
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* CS7*
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* AVEC*
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*/
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m360.pepar = 0x3440;
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/*
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* Step 11: Remap Chip Select 0 (CS0*), set up GMR
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*/
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/*
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* 512 addresses per DRAM page (256K DRAM chips)
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* 70 nsec DRAM
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* 180 nsec ROM (3 wait states)
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*/
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m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
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M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
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M360_GMR_DPS_32BIT | M360_GMR_NCS |
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M360_GMR_TSS40;
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m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
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M360_MEMC_BR_V;
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m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
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M360_MEMC_OR_32BIT;
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/*
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* Step 12: Initialize the system RAM
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*/
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/*
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* Set up option/base registers
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* 1M DRAM
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* 70 nsec DRAM
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* Enable burst mode
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* No parity checking
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* Wait for chips to power up
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* Perform 8 read cycles
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*/
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ramSize = 1 * 1024 * 1024;
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m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
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M360_MEMC_OR_1MB |
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M360_MEMC_OR_DRAM;
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m360.memc[1].br = (unsigned long)&_RamBase |
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M360_MEMC_BR_BACK40 |
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M360_MEMC_BR_V;
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for (i = 0; i < 50000; i++)
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continue;
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for (i = 0; i < 8; ++i)
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*((volatile unsigned long *)(unsigned long)&_RamBase);
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/*
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* Step 13: Copy the exception vector table to system RAM
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*/
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m68k_get_vbr (vbr);
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for (i = 0; i < 256; ++i)
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M68Kvec[i] = vbr[i];
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m68k_set_vbr (M68Kvec);
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/*
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* Step 14: More system initialization
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* SDCR (Serial DMA configuration register)
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* Enable SDMA during FREEZE
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* Give SDMA priority over all interrupt handlers
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* Set DMA arbiration level to 4
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* CICR (CPM interrupt configuration register):
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* SCC1 requests at SCCa position
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* SCC2 requests at SCCb position
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* SCC3 requests at SCCc position
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* SCC4 requests at SCCd position
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* Interrupt request level 4
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* Maintain original priority order
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* Vector base 128
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* SCCs priority grouped at top of table
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*/
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m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
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m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
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(4 << 13) | (0x1F << 8) | (128);
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/*
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* Step 15: Set module configuration register
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* Bus request MC68040 Arbitration ID 3
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* Bus asynchronous timing mode (work around bug in Rev. B)
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* Arbitration asynchronous timing mode
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* Disable timers during FREEZE
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* Disable bus monitor during FREEZE
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* BCLRO* arbitration level 3
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* No show cycles
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* User/supervisor access
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* Bus clear in arbitration ID level 3
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* SIM60 interrupt sources higher priority than CPM
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*/
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m360.mcr = 0x6000EC3F;
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#elif (defined (M68360_ATLAS_HSB))
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/*
|
||||
******************************************
|
||||
* Standalone Motorola 68360 -- ATLAS HSB *
|
||||
******************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
* Step 6: Is this a power-up reset?
|
||||
* For now we just ignore this and do *all* the steps
|
||||
* Someday we might want to:
|
||||
* if (Hard, Loss of Clock, Power-up)
|
||||
* Do all steps
|
||||
* else if (Double bus fault, watchdog or soft reset)
|
||||
* Skip to step 12
|
||||
* else (must be a CPU32+ reset command)
|
||||
* Skip to step 14
|
||||
*/
|
||||
|
||||
/*
|
||||
* Step 7: Deal with clock synthesizer
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||||
* HARDWARE:
|
||||
* Change if you're not using an external 25 MHz oscillator.
|
||||
*/
|
||||
m360.clkocr = 0x8F; /* No more writes, no clock outputs */
|
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m360.pllcr = 0xD000; /* PLL, no writes, no prescale,
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no LPSTOP slowdown, PLL X1 */
|
||||
m360.cdvcr = 0x8000; /* No more writes, no clock division */
|
||||
|
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/*
|
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* Step 8: Initialize system protection
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* Enable watchdog
|
||||
* Watchdog causes system reset
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||||
* Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
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* Enable double bus fault monitor
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* Enable bus monitor for external cycles
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* 1024 clocks for external timeout
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*/
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m360.sypcr = 0xEC;
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/*
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* Step 9: Clear parameter RAM and reset communication processor module
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*/
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for (i = 0 ; i < 192 ; i += sizeof (long)) {
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*((long *)((char *)&m360 + 0xC00 + i)) = 0;
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*((long *)((char *)&m360 + 0xD00 + i)) = 0;
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*((long *)((char *)&m360 + 0xE00 + i)) = 0;
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*((long *)((char *)&m360 + 0xF00 + i)) = 0;
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}
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M360ExecuteRISC (M360_CR_RST);
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/*
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* Step 10: Write PEPAR
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* SINTOUT not used (CPU32+ mode)
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* CF1MODE=00 (CONFIG1 input)
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* RAS1* double drive
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* WE0* - WE3*
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* OE* output
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* CAS2* - CAS3*
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* CAS0* - CAS1*
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* CS7*
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* AVEC*
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* HARDWARE:
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* Change if you are using a different memory configuration
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* (static RAM, external address multiplexing, etc).
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*/
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m360.pepar = 0x0180;
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/*
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* Step 11: Remap Chip Select 0 (CS0*), set up GMR
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*/
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m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN |
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M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
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M360_GMR_DPS_32BIT | M360_GMR_DWQ |
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M360_GMR_GAMX;
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m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
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M360_MEMC_BR_V;
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m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
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M360_MEMC_OR_8BIT;
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/*
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* Step 12: Initialize the system RAM
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*/
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ramSize = 2 * 1024 * 1024;
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/* first bank 1MByte DRAM */
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m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
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M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
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m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
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/* second bank 1MByte DRAM */
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m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
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M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
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m360.memc[2].br = ((unsigned long)&_RamBase + 0x100000) |
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M360_MEMC_BR_V;
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/* flash rom socket U6 on CS5 */
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m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP |
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M360_MEMC_BR_V;
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m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
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M360_MEMC_OR_8BIT;
|
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/* CSRs on CS7 */
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m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB |
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M360_MEMC_OR_8BIT;
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m360.memc[7].br = ATLASHSB_ESR | 0x01;
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for (i = 0; i < 50000; i++)
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continue;
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for (i = 0; i < 8; ++i)
|
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*((volatile unsigned long *)(unsigned long)&_RamBase);
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|
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/*
|
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* Step 13: Copy the exception vector table to system RAM
|
||||
*/
|
||||
m68k_get_vbr (vbr);
|
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for (i = 0; i < 256; ++i)
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||||
M68Kvec[i] = vbr[i];
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m68k_set_vbr (M68Kvec);
|
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|
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/*
|
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* Step 14: More system initialization
|
||||
* SDCR (Serial DMA configuration register)
|
||||
* Enable SDMA during FREEZE
|
||||
* Give SDMA priority over all interrupt handlers
|
||||
* Set DMA arbiration level to 4
|
||||
* CICR (CPM interrupt configuration register):
|
||||
* SCC1 requests at SCCa position
|
||||
* SCC2 requests at SCCb position
|
||||
* SCC3 requests at SCCc position
|
||||
* SCC4 requests at SCCd position
|
||||
* Interrupt request level 4
|
||||
* Maintain original priority order
|
||||
* Vector base 128
|
||||
* SCCs priority grouped at top of table
|
||||
*/
|
||||
m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
|
||||
m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
|
||||
(4 << 13) | (0x1F << 8) | (128);
|
||||
|
||||
/*
|
||||
* Step 15: Set module configuration register
|
||||
* Disable timers during FREEZE
|
||||
* Enable bus monitor during FREEZE
|
||||
* BCLRO* arbitration level 3
|
||||
*/
|
||||
|
||||
#elif (defined (GEN68360_WITH_SRAM))
|
||||
/*
|
||||
***************************************************
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||||
* Generic Standalone Motorola 68360 *
|
||||
* As described in MC68360 User's Manual *
|
||||
* But uses SRAM instead of DRAM *
|
||||
* CS0* - 512kx8 flash memory *
|
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* CS1* - 512kx32 static RAM *
|
||||
* CS2* - 512kx32 static RAM *
|
||||
***************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
* Step 7: Deal with clock synthesizer
|
||||
* HARDWARE:
|
||||
* Change if you're not using an external oscillator which
|
||||
* oscillates at the system clock rate.
|
||||
*/
|
||||
m360.clkocr = 0x8F; /* No more writes, no clock outputs */
|
||||
m360.pllcr = 0xD000; /* PLL, no writes, no prescale,
|
||||
no LPSTOP slowdown, PLL X1 */
|
||||
m360.cdvcr = 0x8000; /* No more writes, no clock division */
|
||||
|
||||
/*
|
||||
* Step 8: Initialize system protection
|
||||
* Enable watchdog
|
||||
* Watchdog causes system reset
|
||||
* Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
|
||||
* Enable double bus fault monitor
|
||||
* Enable bus monitor for external cycles
|
||||
* 1024 clocks for external timeout
|
||||
*/
|
||||
m360.sypcr = 0xEC;
|
||||
|
||||
/*
|
||||
* Step 9: Clear parameter RAM and reset communication processor module
|
||||
*/
|
||||
for (i = 0 ; i < 192 ; i += sizeof (long)) {
|
||||
*((long *)((char *)&m360 + 0xC00 + i)) = 0;
|
||||
*((long *)((char *)&m360 + 0xD00 + i)) = 0;
|
||||
*((long *)((char *)&m360 + 0xE00 + i)) = 0;
|
||||
*((long *)((char *)&m360 + 0xF00 + i)) = 0;
|
||||
}
|
||||
M360ExecuteRISC (M360_CR_RST);
|
||||
|
||||
/*
|
||||
* Step 10: Write PEPAR
|
||||
* SINTOUT not used (CPU32+ mode)
|
||||
* CF1MODE=00 (CONFIG1 input)
|
||||
* IPIPE1*
|
||||
* WE0* - WE3*
|
||||
* OE* output
|
||||
* CAS2* - CAS3*
|
||||
* CAS0* - CAS1*
|
||||
* CS7*
|
||||
* AVEC*
|
||||
* HARDWARE:
|
||||
* Change if you are using a different memory configuration
|
||||
* (static RAM, external address multiplexing, etc).
|
||||
*/
|
||||
m360.pepar = 0x0080;
|
||||
|
||||
/*
|
||||
* Step 11: Set up GMR
|
||||
*
|
||||
*/
|
||||
m360.gmr = 0x0;
|
||||
|
||||
/*
|
||||
* Step 11a: Remap 512Kx8 flash memory on CS0*
|
||||
* 2 wait states
|
||||
* Make it read-only for now
|
||||
*/
|
||||
m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
|
||||
M360_MEMC_BR_V;
|
||||
m360.memc[0].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
|
||||
M360_MEMC_OR_8BIT;
|
||||
/*
|
||||
* Step 12: Set up main memory
|
||||
* 512Kx32 SRAM on CS1*
|
||||
* 512Kx32 SRAM on CS2*
|
||||
* 0 wait states
|
||||
*/
|
||||
ramSize = 4 * 1024 * 1024;
|
||||
m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
|
||||
m360.memc[1].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
|
||||
M360_MEMC_OR_32BIT;
|
||||
m360.memc[2].br = ((unsigned long)&_RamBase + 0x200000) | M360_MEMC_BR_V;
|
||||
m360.memc[2].or = M360_MEMC_OR_WAITS(0) | M360_MEMC_OR_2MB |
|
||||
M360_MEMC_OR_32BIT;
|
||||
/*
|
||||
* Step 13: Copy the exception vector table to system RAM
|
||||
*/
|
||||
m68k_get_vbr (vbr);
|
||||
for (i = 0; i < 256; ++i)
|
||||
M68Kvec[i] = vbr[i];
|
||||
m68k_set_vbr (M68Kvec);
|
||||
|
||||
/*
|
||||
* Step 14: More system initialization
|
||||
* SDCR (Serial DMA configuration register)
|
||||
* Enable SDMA during FREEZE
|
||||
* Give SDMA priority over all interrupt handlers
|
||||
* Set DMA arbiration level to 4
|
||||
* CICR (CPM interrupt configuration register):
|
||||
* SCC1 requests at SCCa position
|
||||
* SCC2 requests at SCCb position
|
||||
* SCC3 requests at SCCc position
|
||||
* SCC4 requests at SCCd position
|
||||
* Interrupt request level 4
|
||||
* Maintain original priority order
|
||||
* Vector base 128
|
||||
* SCCs priority grouped at top of table
|
||||
*/
|
||||
m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
|
||||
m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
|
||||
(4 << 13) | (0x1F << 8) | (128);
|
||||
|
||||
/*
|
||||
* Step 15: Set module configuration register
|
||||
* Disable timers during FREEZE
|
||||
* Enable bus monitor during FREEZE
|
||||
* BCLRO* arbitration level 3
|
||||
* No show cycles
|
||||
* User/supervisor access
|
||||
* Bus clear interrupt service level 7
|
||||
* SIM60 interrupt sources higher priority than CPM
|
||||
*/
|
||||
m360.mcr = 0x4C7F;
|
||||
|
||||
#else
|
||||
/*
|
||||
***************************************************
|
||||
* Generic Standalone Motorola 68360 *
|
||||
* As described in MC68360 User's Manual *
|
||||
* Atlas ACE360 *
|
||||
***************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
* Step 6: Is this a power-up reset?
|
||||
* For now we just ignore this and do *all* the steps
|
||||
* Someday we might want to:
|
||||
* if (Hard, Loss of Clock, Power-up)
|
||||
* Do all steps
|
||||
* else if (Double bus fault, watchdog or soft reset)
|
||||
* Skip to step 12
|
||||
* else (must be a CPU32+ reset command)
|
||||
* Skip to step 14
|
||||
*/
|
||||
|
||||
/*
|
||||
* Step 7: Deal with clock synthesizer
|
||||
* HARDWARE:
|
||||
* Change if you're not using an external 25 MHz oscillator.
|
||||
*/
|
||||
m360.clkocr = 0x8F; /* No more writes, no clock outputs */
|
||||
m360.pllcr = 0xD000; /* PLL, no writes, no prescale,
|
||||
no LPSTOP slowdown, PLL X1 */
|
||||
m360.cdvcr = 0x8000; /* No more writes, no clock division */
|
||||
|
||||
/*
|
||||
* Step 8: Initialize system protection
|
||||
* Enable watchdog
|
||||
* Watchdog causes system reset
|
||||
* Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
|
||||
* Enable double bus fault monitor
|
||||
* Enable bus monitor for external cycles
|
||||
* 1024 clocks for external timeout
|
||||
*/
|
||||
m360.sypcr = 0xEC;
|
||||
|
||||
/*
|
||||
* Step 9: Clear parameter RAM and reset communication processor module
|
||||
*/
|
||||
for (i = 0 ; i < 192 ; i += sizeof (long)) {
|
||||
*((long *)((char *)&m360 + 0xC00 + i)) = 0;
|
||||
*((long *)((char *)&m360 + 0xD00 + i)) = 0;
|
||||
*((long *)((char *)&m360 + 0xE00 + i)) = 0;
|
||||
*((long *)((char *)&m360 + 0xF00 + i)) = 0;
|
||||
}
|
||||
M360ExecuteRISC (M360_CR_RST);
|
||||
|
||||
/*
|
||||
* Step 10: Write PEPAR
|
||||
* SINTOUT not used (CPU32+ mode)
|
||||
* CF1MODE=00 (CONFIG1 input)
|
||||
* RAS1* double drive
|
||||
* WE0* - WE3*
|
||||
* OE* output
|
||||
* CAS2* - CAS3*
|
||||
* CAS0* - CAS1*
|
||||
* CS7*
|
||||
* AVEC*
|
||||
* HARDWARE:
|
||||
* Change if you are using a different memory configuration
|
||||
* (static RAM, external address multiplexing, etc).
|
||||
*/
|
||||
m360.pepar = 0x0180;
|
||||
|
||||
/*
|
||||
* Step 11: Remap Chip Select 0 (CS0*), set up GMR
|
||||
* 32-bit DRAM
|
||||
* Internal DRAM address multiplexing
|
||||
* 60 nsec DRAM
|
||||
* 180 nsec ROM (3 wait states)
|
||||
* 15.36 usec DRAM refresh interval
|
||||
* The DRAM page size selection is not modified since this
|
||||
* startup code may be running in a bootstrap PROM or in
|
||||
* a program downloaded by the bootstrap PROM.
|
||||
*/
|
||||
m360.gmr = (m360.gmr & 0x001C0000) | M360_GMR_RCNT(23) |
|
||||
M360_GMR_RFEN | M360_GMR_RCYC(0) |
|
||||
M360_GMR_DPS_32BIT | M360_GMR_NCS |
|
||||
M360_GMR_GAMX;
|
||||
m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
|
||||
M360_MEMC_BR_V;
|
||||
m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
|
||||
M360_MEMC_OR_8BIT;
|
||||
|
||||
/*
|
||||
* Step 12: Initialize the system RAM
|
||||
* Do this only if the DRAM has not already been set up
|
||||
*/
|
||||
if ((m360.memc[1].br & M360_MEMC_BR_V) == 0) {
|
||||
/*
|
||||
* Set up GMR DRAM page size, option and base registers
|
||||
* Assume 16Mbytes of DRAM
|
||||
* 60 nsec DRAM
|
||||
*/
|
||||
m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(5);
|
||||
m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
|
||||
M360_MEMC_OR_16MB |
|
||||
M360_MEMC_OR_DRAM;
|
||||
m360.memc[1].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
|
||||
|
||||
/*
|
||||
* Wait for chips to power up
|
||||
* Perform 8 read cycles
|
||||
*/
|
||||
for (i = 0; i < 50000; i++)
|
||||
continue;
|
||||
for (i = 0; i < 8; ++i)
|
||||
*((volatile unsigned long *)(unsigned long)&_RamBase);
|
||||
|
||||
/*
|
||||
* Determine memory size (1, 4, or 16 Mbytes)
|
||||
* Set GMR DRAM page size appropriately.
|
||||
* The OR is left at 16 Mbytes. The bootstrap PROM places its
|
||||
* .data and .bss segments at the top of the 16 Mbyte space.
|
||||
* A 1 Mbyte or 4 Mbyte DRAM will show up several times in
|
||||
* the memory map, but will work with the same bootstrap PROM.
|
||||
*/
|
||||
*(volatile char *)&_RamBase = 0;
|
||||
*((volatile char *)&_RamBase+0x00C01800) = 1;
|
||||
if (*(volatile char *)&_RamBase) {
|
||||
m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(1);
|
||||
}
|
||||
else {
|
||||
*((volatile char *)&_RamBase+0x00801000) = 1;
|
||||
if (*(volatile char *)&_RamBase) {
|
||||
m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(3);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable parity checking
|
||||
*/
|
||||
m360.memc[1].br |= M360_MEMC_BR_PAREN;
|
||||
}
|
||||
switch (m360.gmr & 0x001C0000) {
|
||||
default: ramSize = 4 * 1024 * 1024; break;
|
||||
case M360_GMR_PGS(1): ramSize = 1 * 1024 * 1024; break;
|
||||
case M360_GMR_PGS(3): ramSize = 4 * 1024 * 1024; break;
|
||||
case M360_GMR_PGS(5): ramSize = 16 * 1024 * 1024; break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Step 13: Copy the exception vector table to system RAM
|
||||
*/
|
||||
m68k_get_vbr (vbr);
|
||||
for (i = 0; i < 256; ++i)
|
||||
M68Kvec[i] = vbr[i];
|
||||
m68k_set_vbr (M68Kvec);
|
||||
|
||||
/*
|
||||
* Step 14: More system initialization
|
||||
* SDCR (Serial DMA configuration register)
|
||||
* Enable SDMA during FREEZE
|
||||
* Give SDMA priority over all interrupt handlers
|
||||
* Set DMA arbiration level to 4
|
||||
* CICR (CPM interrupt configuration register):
|
||||
* SCC1 requests at SCCa position
|
||||
* SCC2 requests at SCCb position
|
||||
* SCC3 requests at SCCc position
|
||||
* SCC4 requests at SCCd position
|
||||
* Interrupt request level 4
|
||||
* Maintain original priority order
|
||||
* Vector base 128
|
||||
* SCCs priority grouped at top of table
|
||||
*/
|
||||
m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
|
||||
m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
|
||||
(4 << 13) | (0x1F << 8) | (128);
|
||||
|
||||
/*
|
||||
* Step 15: Set module configuration register
|
||||
* Disable timers during FREEZE
|
||||
* Enable bus monitor during FREEZE
|
||||
* BCLRO* arbitration level 3
|
||||
* No show cycles
|
||||
* User/supervisor access
|
||||
* Bus clear interrupt service level 7
|
||||
* SIM60 interrupt sources higher priority than CPM
|
||||
*/
|
||||
m360.mcr = 0x4C7F;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Copy data, clear BSS, switch stacks and call main()
|
||||
* Must pass ramSize as argument since the data/bss segment
|
||||
* may be overwritten.
|
||||
*/
|
||||
_CopyDataClearBSSAndStart (ramSize);
|
||||
}
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user