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score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib.

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Some/many Cortex-A cores have data cache line length 64 bytes and maximum
value has to be used for system structures alignment.

Updates #2782
Updates #2783
This commit is contained in:
Pavel Pisa
2016-07-02 14:33:11 +02:00
parent d5ff46bd52
commit 9aaf8f2b0b
2 changed files with 11 additions and 2 deletions
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4
cpukit/score/cpu/arm/rtems/score/arm.h
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@@ -53,6 +53,10 @@ extern "C" {
#define ARM_MULTILIB_HAS_THREAD_ID_REGISTER
#endif
#if defined(__ARM_ARCH_7A__)
#define ARM_MULTILIB_CACHE_LINE_MAX_64
#endif
#if !defined(__SOFTFP__)
#if defined(__ARM_NEON__)
#define ARM_MULTILIB_VFP_D32

9
cpukit/score/cpu/arm/rtems/score/cpu.h
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@@ -145,8 +145,13 @@
#define CPU_STACK_GROWS_UP FALSE
/* XXX Why 32? */
#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32)))
#if defined(ARM_MULTILIB_CACHE_LINE_MAX_64)
#define CPU_CACHE_LINE_BYTES 32
#else
#define CPU_CACHE_LINE_BYTES 64
#endif
#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (CPU_CACHE_LINE_BYTES )))
#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE