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https://gitlab.rtems.org/rtems/rtos/rtems.git
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Added file .. fixed RCS Id
This commit is contained in:
Joel Sherrill
285
c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.s
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285
c/src/lib/libbsp/powerpc/papyrus/flashentry/flashentry.s
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/* dlentry.s 1.0 - 95/08/08
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*
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* This file contains the entry veneer for RTEMS programs
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* stored in Papyrus' flash ROM.
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*
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* Author: Andrew Bray <andy@i-cubed.demon.co.uk>
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*
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* COPYRIGHT (c) 1995 by i-cubed ltd.
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*
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* To anyone who acknowledges that this file is provided "AS IS"
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* without any express or implied warranty:
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* permission to use, copy, modify, and distribute this file
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* for any purpose is hereby granted without fee, provided that
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* the above copyright notice and this notice appears in all
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* copies, and that the name of i-cubed limited not be used in
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* advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission.
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* i-cubed limited makes no representations about the suitability
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* of this software for any purpose.
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*/
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#include "asm.h"
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/*
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* The Papyrus ELF link scripts support three special sections:
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* .entry The actual entry point, this must contain less
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* than 256 bytes of code/data to fit below the
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* .vectors section. This always preceeds any other
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* code or data.
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* .vectors The section containing the interrupt entry veneers.
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* .entry2 Any code overflowing from .entry
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* .descriptors The PowerOpen function indirection blocks.
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*/
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/*
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* Flash sections are linked in the following order:
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* .entry
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* .vectors
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* .entry2
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* .text
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* .descriptors
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* .data
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* .bss
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* usually starting from 0xFFF00000.
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*
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* The initial stack is set to run BELOW the final location of
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* the initialised data.
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*
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* All the entry veneer has to do is to copy the initialised data
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* to its final location and clear the BSS.
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*/
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/*
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* GDB likes to have debugging information for the entry veneer.
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* Here is some DWARF information.
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*/
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#if PPC_ASM == PPC_ASM_ELF
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.section .entry,"ax",@progbits
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.L_text_b:
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.L_LC1:
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.previous
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.section .debug_sfnames
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.L_sfnames_b:
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.byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/flashentry/"
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.byte 0
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.L_F0:
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.byte "flashentry.s"
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.byte 0
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.previous
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.section .line
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.L_line_b:
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.4byte .L_line_e-.L_line_b
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.4byte .L_text_b
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.L_LE1:
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.L_line_last:
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.4byte 0x0
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.2byte 0xffff
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.4byte .L_text_e-.L_text_b
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.L_line_e:
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.previous
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.section .debug_srcinfo
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.L_srcinfo_b:
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.4byte .L_line_b
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.4byte .L_sfnames_b
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.4byte .L_text_b
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.4byte .L_text_e
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.4byte 0xffffffff
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.4byte .L_LE1-.L_line_b
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.4byte .L_F0-.L_sfnames_b
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.4byte .L_line_last-.L_line_b
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.4byte 0xffffffff
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.previous
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.section .debug_pubnames
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.4byte .L_debug_b
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.4byte .L_P0
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.byte "flash_entry"
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.byte 0
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.4byte 0x0
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.byte 0
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.previous
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.section .debug_aranges
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.4byte .L_debug_b
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.4byte .L_text_b
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.4byte .L_text_e-.L_text_b
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.4byte 0
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.4byte 0
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.4byte 0
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.4byte 0
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.4byte 0
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.4byte 0
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.4byte 0x0
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.4byte 0x0
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.previous
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.section .debug
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.L_debug_b:
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.L_D1:
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.4byte .L_D1_e-.L_D1
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.2byte 0x11 /* TAG_compile_unit */
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.2byte 0x12 /* AT_sibling */
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.4byte .L_D2
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.2byte 0x38 /* AT_name */
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.byte "flashentry.s"
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.byte 0
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.2byte 0x258 /* AT_producer */
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.byte "GAS 2.5.2"
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.byte 0
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.2byte 0x111 /* AT_low_pc */
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.4byte .L_text_b
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.2byte 0x121 /* AT_high_pc */
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.4byte .L_text_e
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.2byte 0x106 /* AT_stmt_list */
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.4byte .L_line_b
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.2byte 0x1b8 /* AT_comp_dir */
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.byte "/home/andy/powerpc/rtems-3.2.0/c/src/lib/libcpu/ppc/ppc403/dlentry/"
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.byte 0
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.2byte 0x8006 /* AT_sf_names */
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.4byte .L_sfnames_b
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.2byte 0x8016 /* AT_src_info */
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.4byte .L_srcinfo_b
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.L_D1_e:
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.L_P0:
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.L_D3:
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.4byte .L_D3_e-.L_D3
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.2byte 0x6 /* TAG_global_subroutine */
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.2byte 0x12 /* AT_sibling */
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.4byte .L_D4
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.2byte 0x38 /* AT_name */
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.byte "flash_entry"
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.byte 0
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.2byte 0x278 /* AT_prototyped */
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.byte 0
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.2byte 0x111 /* AT_low_pc */
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.4byte .L_text_b
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.2byte 0x121 /* AT_high_pc */
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.4byte .L_text_e
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.2byte 0x8041 /* AT_body_begin */
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.4byte .L_text_b
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.2byte 0x8051 /* AT_body_end */
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.4byte .L_text_e
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.L_D3_e:
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.L_D4:
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.4byte .L_D4_e-.L_D4
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.align 2
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.L_D4_e:
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.L_D2:
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.previous
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#endif
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/*-------------------------------------------------------------------------------
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* ROM Vector area.
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*------------------------------------------------------------------------------*/
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#if PPC_ASM == PPC_ASM_ELF
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.section .entry
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#else
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.csect .text[PR]
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#endif
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PUBLIC_VAR (flash_entry)
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SYM (flash_entry):
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bl .startup
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base_addr:
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/*-------------------------------------------------------------------------------
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* Parameters from linker
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*------------------------------------------------------------------------------*/
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toc_pointer:
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#if PPC_ASM == PPC_ASM_ELF
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.long s.got
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#else
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.long TOC[tc0]
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#endif
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text_length:
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.long t.size
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text_addr:
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.long t.start
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data_length:
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.long copy.size
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data_addr:
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.long copy.dest
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bss_length:
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.long bss.size
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bss_addr:
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.long bss.start
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/*-------------------------------------------------------------------------------
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* Reset_entry.
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*------------------------------------------------------------------------------*/
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.startup:
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/* Get start address */
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mflr r1
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/* Assume Bank regs set up..., cache etc. */
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/*-----------------------------------------------------------------------
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* Check the DRAM where STACK+ DATA+ BBS will be placed. If this is OK
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* we will return here.
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*----------------------------------------------------------------------*/
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bl rom2ram
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/*-----------------------------------------------------------------------
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* Enable two 128MB cachable regions.
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*----------------------------------------------------------------------*/
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addis r2,r0,0x8000
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addi r2,r2,0x0001
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mticcr r2
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mtdccr r2
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/*-----------------------------------------------------------------------
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* C_setup.
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*----------------------------------------------------------------------*/
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lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */
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lwz r1,data_addr-base_addr(r1) /* set r1 to data_addr */
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addi r1,r1,-56 /* start stack at data_addr - 56 */
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addi r3,r0,0x0 /* clear r3 */
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stw r3, 0(r1) /* Clear stack chain */
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stw r3, 4(r1)
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stw r3, 8(r1)
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stw r3, 12(r1)
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.extern .main
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b .main /* call the first C routine */
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/*-------------------------------------------------------------------------------
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* Rom2ram.
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*------------------------------------------------------------------------------*/
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rom2ram:
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lwz r2,data_addr-base_addr(r1) /* start of data set by loader */
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lwz r3,data_length-base_addr(r1) /* data length */
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rlwinm r3,r3,30,0x3FFFFFFF /* form length/4 */
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mtctr r3 /* set ctr reg */
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/*-----------------------------------------------------------------------
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* Calculate offset of data in image.
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*----------------------------------------------------------------------*/
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lwz r5,text_length-base_addr(r1) /* get text length */
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lwz r4,text_addr-base_addr(r1) /* get text length */
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add r4,r4,r5 /* r4 = data pointer */
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move_data:
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lswi r6,r4,0x4 /* load r6 */
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stswi r6,r2,0x4 /* store r6 */
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addi r4,r4,0x4 /* update r4 */
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addi r2,r2,0x4 /* update r2 */
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bdnz move_data /* decrement counter and loop */
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/*-----------------------------------------------------------------------
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* Data move finished, zero out bss.
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*----------------------------------------------------------------------*/
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lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */
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lwz r3,bss_length-base_addr(r1) /* bss length */
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rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */
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beqlr /* no bss */
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mtctr r3 /* set ctr reg */
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xor r6,r6,r6 /* r6 = 0 */
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clear_bss:
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stswi r6,r2,0x4 /* store r6 */
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addi r3,r2,0x4 /* update r2 */
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bdnz clear_bss /* decrement counter and loop */
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blr /* return */
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.L_text_e:
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#if PPC_ABI == PPC_ABI_POWEROPEN
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DESCRIPTOR (startup)
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#endif
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